pccbb.c revision 1.132
1 /* $NetBSD: pccbb.c,v 1.132 2006/07/08 20:20:27 christos Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: pccbb.c,v 1.132 2006/07/08 20:20:27 christos Exp $"); 35 36 /* 37 #define CBB_DEBUG 38 #define SHOW_REGS 39 */ 40 41 /* 42 * BROKEN! 43 #define PCCBB_PCMCIA_POLL 44 #define CB_PCMCIA_POLL 45 #define CB_PCMCIA_POLL_ONLY 46 #define LEVEL2 47 */ 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/kernel.h> 52 #include <sys/errno.h> 53 #include <sys/ioctl.h> 54 #include <sys/reboot.h> /* for bootverbose */ 55 #include <sys/syslog.h> 56 #include <sys/device.h> 57 #include <sys/malloc.h> 58 #include <sys/proc.h> 59 60 #include <machine/intr.h> 61 #include <machine/bus.h> 62 63 #include <dev/pci/pcivar.h> 64 #include <dev/pci/pcireg.h> 65 #include <dev/pci/pcidevs.h> 66 67 #include <dev/pci/pccbbreg.h> 68 69 #include <dev/cardbus/cardslotvar.h> 70 71 #include <dev/cardbus/cardbusvar.h> 72 73 #include <dev/pcmcia/pcmciareg.h> 74 #include <dev/pcmcia/pcmciavar.h> 75 76 #include <dev/ic/i82365reg.h> 77 #include <dev/ic/i82365var.h> 78 #include <dev/pci/pccbbvar.h> 79 80 #include "locators.h" 81 82 #if defined(__i386__) 83 #include "ioapic.h" 84 #include "acpi.h" 85 #endif 86 87 #ifndef __NetBSD_Version__ 88 struct cfdriver cbb_cd = { 89 NULL, "cbb", DV_DULL 90 }; 91 #endif 92 93 #ifdef CBB_DEBUG 94 #define DPRINTF(x) printf x 95 #define STATIC 96 #else 97 #define DPRINTF(x) 98 #define STATIC static 99 #endif 100 101 /* 102 * DELAY_MS() is a wait millisecond. It shall use instead of delay() 103 * if you want to wait more than 1 ms. 104 */ 105 #define DELAY_MS(time, param) \ 106 do { \ 107 if (cold == 0) { \ 108 int xtick = (hz*(time))/1000; \ 109 \ 110 if (xtick <= 1) { \ 111 xtick = 2; \ 112 } \ 113 tsleep((void *)(param), PWAIT, "pccbb", xtick); \ 114 } else { \ 115 delay((time)*1000); \ 116 } \ 117 } while (/*CONSTCOND*/0) 118 119 int pcicbbmatch(struct device *, struct cfdata *, void *); 120 void pccbbattach(struct device *, struct device *, void *); 121 int pccbbintr(void *); 122 static void pci113x_insert(void *); 123 static int pccbbintr_function(struct pccbb_softc *); 124 125 static int pccbb_detect_card(struct pccbb_softc *); 126 127 static void pccbb_pcmcia_write(struct pcic_handle *, int, u_int8_t); 128 static u_int8_t pccbb_pcmcia_read(struct pcic_handle *, int); 129 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 130 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 131 132 STATIC int cb_reset(struct pccbb_softc *); 133 STATIC int cb_detect_voltage(struct pccbb_softc *); 134 STATIC int cbbprint(void *, const char *); 135 136 static int cb_chipset(u_int32_t, int *); 137 STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *, 138 struct pcmciabus_attach_args *); 139 #if 0 140 STATIC void pccbb_pcmcia_attach_card(struct pcic_handle *); 141 STATIC void pccbb_pcmcia_detach_card(struct pcic_handle *, int); 142 STATIC void pccbb_pcmcia_deactivate_card(struct pcic_handle *); 143 #endif 144 145 STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int); 146 STATIC int pccbb_power(cardbus_chipset_tag_t, int); 147 STATIC int pccbb_cardenable(struct pccbb_softc * sc, int function); 148 #if !rbus 149 static int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 150 static int pccbb_io_close(cardbus_chipset_tag_t, int); 151 static int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 152 static int pccbb_mem_close(cardbus_chipset_tag_t, int); 153 #endif /* !rbus */ 154 static void *pccbb_intr_establish(struct pccbb_softc *, int irq, 155 int level, int (*ih) (void *), void *sc); 156 static void pccbb_intr_disestablish(struct pccbb_softc *, void *ih); 157 158 static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t, int irq, 159 int level, int (*ih) (void *), void *sc); 160 static void pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih); 161 162 static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t, int, int); 163 static void pccbb_free_tag(cardbus_chipset_tag_t, cardbustag_t); 164 static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t, cardbustag_t, int); 165 static void pccbb_conf_write(cardbus_chipset_tag_t, cardbustag_t, int, 166 cardbusreg_t); 167 static void pccbb_chipinit(struct pccbb_softc *); 168 169 STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 170 struct pcmcia_mem_handle *); 171 STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t, 172 struct pcmcia_mem_handle *); 173 STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 174 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *); 175 STATIC void pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t, int); 176 STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 177 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 178 STATIC void pccbb_pcmcia_io_free(pcmcia_chipset_handle_t, 179 struct pcmcia_io_handle *); 180 STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 181 bus_size_t, struct pcmcia_io_handle *, int *); 182 STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t, int); 183 STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t, 184 struct pcmcia_function *, int, int (*)(void *), void *); 185 STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t, void *); 186 STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t); 187 STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t); 188 STATIC void pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t, int); 189 STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch); 190 191 static int pccbb_pcmcia_wait_ready(struct pcic_handle *); 192 static void pccbb_pcmcia_delay(struct pcic_handle *, int, const char *); 193 194 static void pccbb_pcmcia_do_io_map(struct pcic_handle *, int); 195 static void pccbb_pcmcia_do_mem_map(struct pcic_handle *, int); 196 static void pccbb_powerhook(int, void *); 197 198 /* bus-space allocation and deallocation functions */ 199 #if rbus 200 201 static int pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t, rbus_tag_t, 202 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 203 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp); 204 static int pccbb_rbus_cb_space_free(cardbus_chipset_tag_t, rbus_tag_t, 205 bus_space_handle_t, bus_size_t); 206 207 #endif /* rbus */ 208 209 #if rbus 210 211 static int pccbb_open_win(struct pccbb_softc *, bus_space_tag_t, 212 bus_addr_t, bus_size_t, bus_space_handle_t, int flags); 213 static int pccbb_close_win(struct pccbb_softc *, bus_space_tag_t, 214 bus_space_handle_t, bus_size_t); 215 static int pccbb_winlist_insert(struct pccbb_win_chain_head *, bus_addr_t, 216 bus_size_t, bus_space_handle_t, int); 217 static int pccbb_winlist_delete(struct pccbb_win_chain_head *, 218 bus_space_handle_t, bus_size_t); 219 static void pccbb_winset(bus_addr_t align, struct pccbb_softc *, 220 bus_space_tag_t); 221 void pccbb_winlist_show(struct pccbb_win_chain *); 222 223 #endif /* rbus */ 224 225 /* for config_defer */ 226 static void pccbb_pci_callback(struct device *); 227 228 #if defined SHOW_REGS 229 static void cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, 230 bus_space_tag_t memt, bus_space_handle_t memh); 231 #endif 232 233 CFATTACH_DECL(cbb_pci, sizeof(struct pccbb_softc), 234 pcicbbmatch, pccbbattach, NULL, NULL); 235 236 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 237 pccbb_pcmcia_mem_alloc, 238 pccbb_pcmcia_mem_free, 239 pccbb_pcmcia_mem_map, 240 pccbb_pcmcia_mem_unmap, 241 pccbb_pcmcia_io_alloc, 242 pccbb_pcmcia_io_free, 243 pccbb_pcmcia_io_map, 244 pccbb_pcmcia_io_unmap, 245 pccbb_pcmcia_intr_establish, 246 pccbb_pcmcia_intr_disestablish, 247 pccbb_pcmcia_socket_enable, 248 pccbb_pcmcia_socket_disable, 249 pccbb_pcmcia_socket_settype, 250 pccbb_pcmcia_card_detect 251 }; 252 253 #if rbus 254 static struct cardbus_functions pccbb_funcs = { 255 pccbb_rbus_cb_space_alloc, 256 pccbb_rbus_cb_space_free, 257 pccbb_cb_intr_establish, 258 pccbb_cb_intr_disestablish, 259 pccbb_ctrl, 260 pccbb_power, 261 pccbb_make_tag, 262 pccbb_free_tag, 263 pccbb_conf_read, 264 pccbb_conf_write, 265 }; 266 #else 267 static struct cardbus_functions pccbb_funcs = { 268 pccbb_ctrl, 269 pccbb_power, 270 pccbb_mem_open, 271 pccbb_mem_close, 272 pccbb_io_open, 273 pccbb_io_close, 274 pccbb_cb_intr_establish, 275 pccbb_cb_intr_disestablish, 276 pccbb_make_tag, 277 pccbb_conf_read, 278 pccbb_conf_write, 279 }; 280 #endif 281 282 int 283 pcicbbmatch(parent, match, aux) 284 struct device *parent; 285 struct cfdata *match; 286 void *aux; 287 { 288 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 289 290 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 291 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 292 PCI_INTERFACE(pa->pa_class) == 0) { 293 return 1; 294 } 295 296 return 0; 297 } 298 299 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 300 | ((prod) << PCI_PRODUCT_SHIFT)) 301 302 const struct yenta_chipinfo { 303 pcireg_t yc_id; /* vendor tag | product tag */ 304 int yc_chiptype; 305 int yc_flags; 306 } yc_chipsets[] = { 307 /* Texas Instruments chips */ 308 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 309 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 310 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 311 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 312 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI125X, 313 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 314 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 315 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 316 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 317 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 318 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 319 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 320 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI125X, 321 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 322 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI125X, 323 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 324 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 325 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 326 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 327 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 328 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 329 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 330 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI125X, 331 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 332 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 333 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 334 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1520), CB_TI12XX, 335 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 336 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4410YENTA), CB_TI12XX, 337 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 338 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4520YENTA), CB_TI12XX, 339 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 340 341 /* Ricoh chips */ 342 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 343 PCCBB_PCMCIA_MEM_32}, 344 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 345 PCCBB_PCMCIA_MEM_32}, 346 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 347 PCCBB_PCMCIA_MEM_32}, 348 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 349 PCCBB_PCMCIA_MEM_32}, 350 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 351 PCCBB_PCMCIA_MEM_32}, 352 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 353 PCCBB_PCMCIA_MEM_32}, 354 355 /* Toshiba products */ 356 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 357 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 358 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 359 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 360 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 361 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 362 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 363 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 364 365 /* Cirrus Logic products */ 366 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 367 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 368 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 369 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 370 371 /* sentinel, or Generic chip */ 372 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 373 }; 374 375 static int 376 cb_chipset(pci_id, flagp) 377 u_int32_t pci_id; 378 int *flagp; 379 { 380 const struct yenta_chipinfo *yc; 381 382 /* Loop over except the last default entry. */ 383 for (yc = yc_chipsets; yc < yc_chipsets + 384 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 385 if (pci_id == yc->yc_id) 386 break; 387 388 if (flagp != NULL) 389 *flagp = yc->yc_flags; 390 391 return (yc->yc_chiptype); 392 } 393 394 static void 395 pccbb_shutdown(void *arg) 396 { 397 struct pccbb_softc *sc = arg; 398 pcireg_t command; 399 400 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 401 402 /* 403 * turn off power 404 * 405 * XXX - do not turn off power if chipset is TI 113X because 406 * only TI 1130 with PowerMac 2400 hangs in pccbb_power(). 407 */ 408 if (sc->sc_chipset != CB_TI113X) { 409 pccbb_power((cardbus_chipset_tag_t)sc, 410 CARDBUS_VCC_0V | CARDBUS_VPP_0V); 411 } 412 413 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 414 0); 415 416 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 417 418 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 419 PCI_COMMAND_MASTER_ENABLE); 420 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 421 422 } 423 424 void 425 pccbbattach(parent, self, aux) 426 struct device *parent; 427 struct device *self; 428 void *aux; 429 { 430 struct pccbb_softc *sc = (void *)self; 431 struct pci_attach_args *pa = aux; 432 pci_chipset_tag_t pc = pa->pa_pc; 433 pcireg_t busreg, reg, sock_base; 434 bus_addr_t sockbase; 435 char devinfo[256]; 436 int flags; 437 int pwrmgt_offs; 438 439 #ifdef __HAVE_PCCBB_ATTACH_HOOK 440 pccbb_attach_hook(parent, self, pa); 441 #endif 442 443 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 444 445 pci_devinfo(pa->pa_id, 0, 0, devinfo, sizeof(devinfo)); 446 printf(": %s (rev. 0x%02x)", devinfo, PCI_REVISION(pa->pa_class)); 447 #ifdef CBB_DEBUG 448 printf(" (chipflags %x)", flags); 449 #endif 450 printf("\n"); 451 452 TAILQ_INIT(&sc->sc_memwindow); 453 TAILQ_INIT(&sc->sc_iowindow); 454 455 #if rbus 456 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 457 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 458 459 #if 0 460 printf("pa->pa_memt: %08x vs rbus_mem->rb_bt: %08x\n", 461 pa->pa_memt, sc->sc_rbus_memt->rb_bt); 462 #endif 463 #endif /* rbus */ 464 465 sc->sc_flags &= ~CBB_MEMHMAPPED; 466 467 /* power management: set D0 state */ 468 sc->sc_pwrmgt_offs = 0; 469 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, 470 &pwrmgt_offs, 0)) { 471 reg = pci_conf_read(pc, pa->pa_tag, pwrmgt_offs + PCI_PMCSR); 472 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 473 reg & 0x100 /* PCI_PMCSR_PME_EN */) { 474 reg &= ~PCI_PMCSR_STATE_MASK; 475 reg |= PCI_PMCSR_STATE_D0; 476 reg &= ~(0x100 /* PCI_PMCSR_PME_EN */); 477 pci_conf_write(pc, pa->pa_tag, 478 pwrmgt_offs + PCI_PMCSR, reg); 479 } 480 481 sc->sc_pwrmgt_offs = pwrmgt_offs; 482 } 483 484 /* 485 * MAP socket registers and ExCA registers on memory-space 486 * When no valid address is set on socket base registers (on pci 487 * config space), get it not polite way. 488 */ 489 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 490 491 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 492 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 493 /* The address must be valid. */ 494 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 495 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL)) { 496 printf("%s: can't map socket base address 0x%lx\n", 497 sc->sc_dev.dv_xname, (unsigned long)sock_base); 498 /* 499 * I think it's funny: socket base registers must be 500 * mapped on memory space, but ... 501 */ 502 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 503 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 504 NULL)) { 505 printf("%s: can't map socket base address" 506 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 507 (unsigned long)sockbase); 508 /* give up... allocate reg space via rbus. */ 509 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 510 } else 511 sc->sc_flags |= CBB_MEMHMAPPED; 512 } else { 513 DPRINTF(("%s: socket base address 0x%lx\n", 514 sc->sc_dev.dv_xname, (unsigned long)sockbase)); 515 sc->sc_flags |= CBB_MEMHMAPPED; 516 } 517 } 518 519 sc->sc_mem_start = 0; /* XXX */ 520 sc->sc_mem_end = 0xffffffff; /* XXX */ 521 522 /* 523 * When interrupt isn't routed correctly, give up probing cbb and do 524 * not kill pcic-compatible port. 525 * 526 * However, if we are using an ioapic, avoid this check -- pa_intrline 527 * may well be zero, with the interrupt routed through the apic. 528 */ 529 530 #if NIOAPIC == 0 && NACPI == 0 531 if ((0 == pa->pa_intrline) || (255 == pa->pa_intrline)) { 532 printf("%s: NOT USED because of unconfigured interrupt\n", 533 sc->sc_dev.dv_xname); 534 return; 535 } 536 #endif 537 538 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 539 540 /* pccbb_machdep.c end */ 541 542 #if defined CBB_DEBUG 543 { 544 static const char *intrname[] = { "NON", "A", "B", "C", "D" }; 545 printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname, 546 intrname[pa->pa_intrpin], pa->pa_intrline); 547 } 548 #endif 549 550 /* setup softc */ 551 sc->sc_pc = pc; 552 sc->sc_iot = pa->pa_iot; 553 sc->sc_memt = pa->pa_memt; 554 sc->sc_dmat = pa->pa_dmat; 555 sc->sc_tag = pa->pa_tag; 556 sc->sc_function = pa->pa_function; 557 sc->sc_sockbase = sock_base; 558 sc->sc_busnum = busreg; 559 560 memcpy(&sc->sc_pa, pa, sizeof(*pa)); 561 562 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 563 564 shutdownhook_establish(pccbb_shutdown, sc); 565 566 /* Disable legacy register mapping. */ 567 switch (sc->sc_chipset) { 568 case CB_RX5C46X: /* fallthrough */ 569 #if 0 570 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 571 case CB_RX5C47X: 572 #endif 573 /* 574 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 575 * cannot be disabled by substituting 0 into PCI_LEGACY 576 * register. Ricoh CardBus bridges have special bits on Bridge 577 * control reg (addr 0x3e on PCI config space). 578 */ 579 reg = pci_conf_read(pc, pa->pa_tag, PCI_BCR_INTR); 580 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 581 pci_conf_write(pc, pa->pa_tag, PCI_BCR_INTR, reg); 582 break; 583 584 default: 585 /* XXX I don't know proper way to kill legacy I/O. */ 586 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 587 break; 588 } 589 590 config_defer(self, pccbb_pci_callback); 591 } 592 593 594 595 596 /* 597 * static void pccbb_pci_callback(struct device *self) 598 * 599 * The actual attach routine: get memory space for YENTA register 600 * space, setup YENTA register and route interrupt. 601 * 602 * This function should be deferred because this device may obtain 603 * memory space dynamically. This function must avoid obtaining 604 * memory area which has already kept for another device. 605 */ 606 static void 607 pccbb_pci_callback(self) 608 struct device *self; 609 { 610 struct pccbb_softc *sc = (void *)self; 611 pci_chipset_tag_t pc = sc->sc_pc; 612 pci_intr_handle_t ih; 613 const char *intrstr = NULL; 614 bus_addr_t sockbase; 615 struct cbslot_attach_args cba; 616 struct pcmciabus_attach_args paa; 617 struct cardslot_attach_args caa; 618 struct cardslot_softc *csc; 619 620 if (!(sc->sc_flags & CBB_MEMHMAPPED)) { 621 /* The socket registers aren't mapped correctly. */ 622 #if rbus 623 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 624 (sc->sc_chipset == CB_RX5C47X 625 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 626 0, &sockbase, &sc->sc_base_memh)) { 627 return; 628 } 629 sc->sc_base_memt = sc->sc_memt; 630 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 631 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 632 sc->sc_dev.dv_xname, (unsigned long)sockbase, 633 (unsigned long)pci_conf_read(pc, sc->sc_tag, 634 PCI_SOCKBASE))); 635 #else 636 sc->sc_base_memt = sc->sc_memt; 637 #if !defined CBB_PCI_BASE 638 #define CBB_PCI_BASE 0x20000000 639 #endif 640 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 641 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 642 /* cannot allocate memory space */ 643 return; 644 } 645 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 646 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 647 sc->sc_dev.dv_xname, (unsigned long)sock_base, 648 (unsigned long)pci_conf_read(pc, 649 sc->sc_tag, PCI_SOCKBASE))); 650 sc->sc_sockbase = sockbase; 651 #endif 652 sc->sc_flags |= CBB_MEMHMAPPED; 653 } 654 655 /* bus bridge initialization */ 656 pccbb_chipinit(sc); 657 658 /* clear data structure for child device interrupt handlers */ 659 LIST_INIT(&sc->sc_pil); 660 sc->sc_pil_intr_enable = 1; 661 662 /* Map and establish the interrupt. */ 663 if (pci_intr_map(&sc->sc_pa, &ih)) { 664 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 665 return; 666 } 667 intrstr = pci_intr_string(pc, ih); 668 669 /* 670 * XXX pccbbintr should be called under the priority lower 671 * than any other hard interupts. 672 */ 673 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 674 675 if (sc->sc_ih == NULL) { 676 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 677 if (intrstr != NULL) { 678 printf(" at %s", intrstr); 679 } 680 printf("\n"); 681 return; 682 } 683 684 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 685 powerhook_establish(pccbb_powerhook, sc); 686 687 { 688 u_int32_t sockstat; 689 690 sockstat = bus_space_read_4(sc->sc_base_memt, 691 sc->sc_base_memh, CB_SOCKET_STAT); 692 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 693 sc->sc_flags |= CBB_CARDEXIST; 694 } 695 } 696 697 /* 698 * attach cardbus 699 */ 700 { 701 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 702 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 703 704 /* initialize cbslot_attach */ 705 cba.cba_busname = "cardbus"; 706 cba.cba_iot = sc->sc_iot; 707 cba.cba_memt = sc->sc_memt; 708 cba.cba_dmat = sc->sc_dmat; 709 cba.cba_bus = (busreg >> 8) & 0x0ff; 710 cba.cba_cc = (void *)sc; 711 cba.cba_cf = &pccbb_funcs; 712 cba.cba_intrline = sc->sc_pa.pa_intrline; 713 714 #if rbus 715 cba.cba_rbus_iot = sc->sc_rbus_iot; 716 cba.cba_rbus_memt = sc->sc_rbus_memt; 717 #endif 718 719 cba.cba_cacheline = PCI_CACHELINE(bhlc); 720 cba.cba_lattimer = PCI_CB_LATENCY(busreg); 721 722 if (bootverbose) { 723 printf("%s: cacheline 0x%x lattimer 0x%x\n", 724 sc->sc_dev.dv_xname, cba.cba_cacheline, 725 cba.cba_lattimer); 726 printf("%s: bhlc 0x%x lscp 0x%x\n", 727 sc->sc_dev.dv_xname, bhlc, busreg); 728 } 729 #if defined SHOW_REGS 730 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 731 sc->sc_base_memh); 732 #endif 733 } 734 735 pccbb_pcmcia_attach_setup(sc, &paa); 736 caa.caa_cb_attach = NULL; 737 if (cba.cba_bus == 0) 738 printf("%s: secondary bus number uninitialized; try PCI_BUS_FIXUP\n", sc->sc_dev.dv_xname); 739 else 740 caa.caa_cb_attach = &cba; 741 caa.caa_16_attach = &paa; 742 caa.caa_ph = &sc->sc_pcmcia_h; 743 744 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 745 DPRINTF(("pccbbattach: found cardslot\n")); 746 sc->sc_csc = csc; 747 } 748 749 return; 750 } 751 752 753 754 755 756 /* 757 * static void pccbb_chipinit(struct pccbb_softc *sc) 758 * 759 * This function initialize YENTA chip registers listed below: 760 * 1) PCI command reg, 761 * 2) PCI and CardBus latency timer, 762 * 3) route PCI interrupt, 763 * 4) close all memory and io windows. 764 * 5) turn off bus power. 765 * 6) card detect and power cycle interrupts on. 766 * 7) clear interrupt 767 */ 768 static void 769 pccbb_chipinit(sc) 770 struct pccbb_softc *sc; 771 { 772 pci_chipset_tag_t pc = sc->sc_pc; 773 pcitag_t tag = sc->sc_tag; 774 bus_space_tag_t bmt = sc->sc_base_memt; 775 bus_space_handle_t bmh = sc->sc_base_memh; 776 pcireg_t reg; 777 778 /* 779 * Set PCI command reg. 780 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 781 */ 782 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 783 /* I believe it is harmless. */ 784 reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 785 PCI_COMMAND_MASTER_ENABLE); 786 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg); 787 788 /* 789 * Set CardBus latency timer. 790 */ 791 reg = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 792 if (PCI_CB_LATENCY(reg) < 0x20) { 793 reg &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 794 reg |= (0x20 << PCI_CB_LATENCY_SHIFT); 795 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, reg); 796 } 797 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 798 PCI_CB_LATENCY(reg), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 799 800 /* 801 * Set PCI latency timer. 802 */ 803 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 804 if (PCI_LATTIMER(reg) < 0x10) { 805 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 806 reg |= (0x10 << PCI_LATTIMER_SHIFT); 807 pci_conf_write(pc, tag, PCI_BHLC_REG, reg); 808 } 809 DPRINTF(("PCI latency timer 0x%x (%x)\n", 810 PCI_LATTIMER(reg), pci_conf_read(pc, tag, PCI_BHLC_REG))); 811 812 813 /* Route functional interrupts to PCI. */ 814 reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 815 reg |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 816 reg |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 817 reg |= CB_BCR_RESET_ENABLE; /* assert reset */ 818 pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 819 820 switch (sc->sc_chipset) { 821 case CB_TI113X: 822 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 823 /* This bit is shared, but may read as 0 on some chips, so set 824 it explicitly on both functions. */ 825 reg |= PCI113X_CBCTRL_PCI_IRQ_ENA; 826 /* CSC intr enable */ 827 reg |= PCI113X_CBCTRL_PCI_CSC; 828 /* functional intr prohibit | prohibit ISA routing */ 829 reg &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 830 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 831 break; 832 833 case CB_TI12XX: 834 /* 835 * Some TI 12xx (and [14][45]xx) based pci cards 836 * sometimes have issues with the MFUNC register not 837 * being initialized due to a bad EEPROM on board. 838 * Laptops that this matters on have this register 839 * properly initialized. 840 * 841 * The TI125X parts have a different register. 842 */ 843 reg = pci_conf_read(pc, tag, PCI12XX_MFUNC); 844 if (reg == 0) { 845 reg &= ~PCI12XX_MFUNC_PIN0; 846 reg |= PCI12XX_MFUNC_PIN0_INTA; 847 if ((pci_conf_read(pc, tag, PCI_SYSCTRL) & 848 PCI12XX_SYSCTRL_INTRTIE) == 0) { 849 reg &= ~PCI12XX_MFUNC_PIN1; 850 reg |= PCI12XX_MFUNC_PIN1_INTB; 851 } 852 pci_conf_write(pc, tag, PCI12XX_MFUNC, reg); 853 } 854 /* fallthrough */ 855 856 case CB_TI125X: 857 /* 858 * Disable zoom video. Some machines initialize this 859 * improperly and experience has shown that this helps 860 * prevent strange behavior. 861 */ 862 pci_conf_write(pc, tag, PCI12XX_MMCTRL, 0); 863 864 reg = pci_conf_read(pc, tag, PCI_SYSCTRL); 865 reg |= PCI12XX_SYSCTRL_VCCPROT; 866 pci_conf_write(pc, tag, PCI_SYSCTRL, reg); 867 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 868 reg |= PCI12XX_CBCTRL_CSC; 869 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 870 break; 871 872 case CB_TOPIC95B: 873 reg = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 874 reg |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 875 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, reg); 876 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 877 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 878 sc->sc_dev.dv_xname, reg)); 879 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 880 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 881 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 882 DPRINTF(("0x%x\n", reg)); 883 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 884 break; 885 886 case CB_TOPIC97: 887 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 888 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 889 sc->sc_dev.dv_xname, reg)); 890 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 891 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 892 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 893 reg |= TOPIC97_SLOT_CTRL_PCIINT; 894 reg &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 895 DPRINTF(("0x%x\n", reg)); 896 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 897 /* make sure to assert LV card support bits */ 898 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 899 0x800 + 0x3e, 900 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 901 0x800 + 0x3e) | 0x03); 902 break; 903 } 904 905 /* Close all memory and I/O windows. */ 906 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 907 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 908 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 909 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 910 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 911 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 912 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 913 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 914 915 /* reset 16-bit pcmcia bus */ 916 bus_space_write_1(bmt, bmh, 0x800 + PCIC_INTR, 917 bus_space_read_1(bmt, bmh, 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 918 919 /* turn off power */ 920 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 921 922 /* CSC Interrupt: Card detect and power cycle interrupts on */ 923 reg = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 924 reg |= CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; 925 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, reg); 926 /* reset interrupt */ 927 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 928 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 929 } 930 931 932 933 934 /* 935 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 936 * struct pcmciabus_attach_args *paa) 937 * 938 * This function attaches 16-bit PCcard bus. 939 */ 940 STATIC void 941 pccbb_pcmcia_attach_setup(sc, paa) 942 struct pccbb_softc *sc; 943 struct pcmciabus_attach_args *paa; 944 { 945 struct pcic_handle *ph = &sc->sc_pcmcia_h; 946 #if rbus 947 rbus_tag_t rb; 948 #endif 949 950 /* initialize pcmcia part in pccbb_softc */ 951 ph->ph_parent = (struct device *)sc; 952 ph->sock = sc->sc_function; 953 ph->flags = 0; 954 ph->shutdown = 0; 955 ph->ih_irq = sc->sc_pa.pa_intrline; 956 ph->ph_bus_t = sc->sc_base_memt; 957 ph->ph_bus_h = sc->sc_base_memh; 958 ph->ph_read = pccbb_pcmcia_read; 959 ph->ph_write = pccbb_pcmcia_write; 960 sc->sc_pct = &pccbb_pcmcia_funcs; 961 962 /* 963 * We need to do a few things here: 964 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 965 * setting the IRQ numbers to 0. 966 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 967 * routing of CSC interrupts (e.g. card removal) to PCI while in 968 * PCMCIA mode. We just leave this set all the time. 969 * 3) Enable card insertion/removal interrupts in case the chip also 970 * needs that while in PCMCIA mode. 971 * 4) Clear any pending CSC interrupt. 972 */ 973 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE); 974 if (sc->sc_chipset == CB_TI113X) { 975 Pcic_write(ph, PCIC_CSC_INTR, 0); 976 } else { 977 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 978 Pcic_read(ph, PCIC_CSC); 979 } 980 981 /* initialize pcmcia bus attachment */ 982 paa->paa_busname = "pcmcia"; 983 paa->pct = sc->sc_pct; 984 paa->pch = ph; 985 paa->iobase = 0; /* I don't use them */ 986 paa->iosize = 0; 987 #if rbus 988 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 989 paa->iobase = rb->rb_start + rb->rb_offset; 990 paa->iosize = rb->rb_end - rb->rb_start; 991 #endif 992 993 return; 994 } 995 996 #if 0 997 STATIC void 998 pccbb_pcmcia_attach_card(ph) 999 struct pcic_handle *ph; 1000 { 1001 if (ph->flags & PCIC_FLAG_CARDP) { 1002 panic("pccbb_pcmcia_attach_card: already attached"); 1003 } 1004 1005 /* call the MI attach function */ 1006 pcmcia_card_attach(ph->pcmcia); 1007 1008 ph->flags |= PCIC_FLAG_CARDP; 1009 } 1010 1011 STATIC void 1012 pccbb_pcmcia_detach_card(ph, flags) 1013 struct pcic_handle *ph; 1014 int flags; 1015 { 1016 if (!(ph->flags & PCIC_FLAG_CARDP)) { 1017 panic("pccbb_pcmcia_detach_card: already detached"); 1018 } 1019 1020 ph->flags &= ~PCIC_FLAG_CARDP; 1021 1022 /* call the MI detach function */ 1023 pcmcia_card_detach(ph->pcmcia, flags); 1024 } 1025 #endif 1026 1027 /* 1028 * int pccbbintr(arg) 1029 * void *arg; 1030 * This routine handles the interrupt from Yenta PCI-CardBus bridge 1031 * itself. 1032 */ 1033 int 1034 pccbbintr(arg) 1035 void *arg; 1036 { 1037 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1038 u_int32_t sockevent, sockstate; 1039 bus_space_tag_t memt = sc->sc_base_memt; 1040 bus_space_handle_t memh = sc->sc_base_memh; 1041 struct pcic_handle *ph = &sc->sc_pcmcia_h; 1042 1043 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 1044 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 1045 Pcic_read(ph, PCIC_CSC); 1046 1047 if (sockevent == 0) { 1048 /* This intr is not for me: it may be for my child devices. */ 1049 if (sc->sc_pil_intr_enable) { 1050 return pccbbintr_function(sc); 1051 } else { 1052 return 0; 1053 } 1054 } 1055 1056 if (sockevent & CB_SOCKET_EVENT_CD) { 1057 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1058 if (0x00 != (sockstate & CB_SOCKET_STAT_CD)) { 1059 /* A card should be removed. */ 1060 if (sc->sc_flags & CBB_CARDEXIST) { 1061 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 1062 sockevent)); 1063 DPRINTF((" card removed, 0x%08x\n", sockstate)); 1064 sc->sc_flags &= ~CBB_CARDEXIST; 1065 if (sc->sc_csc->sc_status & 1066 CARDSLOT_STATUS_CARD_16) { 1067 #if 0 1068 struct pcic_handle *ph = 1069 &sc->sc_pcmcia_h; 1070 1071 pcmcia_card_deactivate(ph->pcmcia); 1072 pccbb_pcmcia_socket_disable(ph); 1073 pccbb_pcmcia_detach_card(ph, 1074 DETACH_FORCE); 1075 #endif 1076 cardslot_event_throw(sc->sc_csc, 1077 CARDSLOT_EVENT_REMOVAL_16); 1078 } else if (sc->sc_csc->sc_status & 1079 CARDSLOT_STATUS_CARD_CB) { 1080 /* Cardbus intr removed */ 1081 cardslot_event_throw(sc->sc_csc, 1082 CARDSLOT_EVENT_REMOVAL_CB); 1083 } 1084 } else if (sc->sc_flags & CBB_INSERTING) { 1085 sc->sc_flags &= ~CBB_INSERTING; 1086 callout_stop(&sc->sc_insert_ch); 1087 } 1088 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 1089 /* 1090 * The pccbbintr may called from powerdown hook when 1091 * the system resumed, to detect the card 1092 * insertion/removal during suspension. 1093 */ 1094 (sc->sc_flags & CBB_CARDEXIST) == 0) { 1095 if (sc->sc_flags & CBB_INSERTING) { 1096 callout_stop(&sc->sc_insert_ch); 1097 } 1098 callout_reset(&sc->sc_insert_ch, hz / 5, 1099 pci113x_insert, sc); 1100 sc->sc_flags |= CBB_INSERTING; 1101 } 1102 } 1103 1104 if (sockevent & CB_SOCKET_EVENT_POWER) { 1105 DPRINTF(("Powercycling because of socket event\n")); 1106 /* XXX: Does not happen when attaching a 16-bit card */ 1107 sc->sc_pwrcycle++; 1108 wakeup(&sc->sc_pwrcycle); 1109 } 1110 1111 return (1); 1112 } 1113 1114 /* 1115 * static int pccbbintr_function(struct pccbb_softc *sc) 1116 * 1117 * This function calls each interrupt handler registered at the 1118 * bridge. The interrupt handlers are called in registered order. 1119 */ 1120 static int 1121 pccbbintr_function(sc) 1122 struct pccbb_softc *sc; 1123 { 1124 int retval = 0, val; 1125 struct pccbb_intrhand_list *pil; 1126 int s, splchanged; 1127 1128 for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1129 pil = LIST_NEXT(pil, pil_next)) { 1130 /* 1131 * XXX priority change. gross. I use if-else 1132 * sentense instead of switch-case sentense because of 1133 * avoiding duplicate case value error. More than one 1134 * IPL_XXX use same value. It depends on 1135 * implimentation. 1136 */ 1137 splchanged = 1; 1138 if (pil->pil_level == IPL_SERIAL) { 1139 s = splserial(); 1140 } else if (pil->pil_level == IPL_HIGH) { 1141 s = splhigh(); 1142 } else if (pil->pil_level == IPL_CLOCK) { 1143 s = splclock(); 1144 } else if (pil->pil_level == IPL_AUDIO) { 1145 s = splaudio(); 1146 } else if (pil->pil_level == IPL_VM) { 1147 s = splvm(); 1148 } else if (pil->pil_level == IPL_TTY) { 1149 s = spltty(); 1150 } else if (pil->pil_level == IPL_SOFTSERIAL) { 1151 s = splsoftserial(); 1152 } else if (pil->pil_level == IPL_NET) { 1153 s = splnet(); 1154 } else { 1155 s = 0; /* XXX: gcc */ 1156 splchanged = 0; 1157 /* XXX: ih lower than IPL_BIO runs w/ IPL_BIO. */ 1158 } 1159 1160 val = (*pil->pil_func)(pil->pil_arg); 1161 1162 if (splchanged != 0) { 1163 splx(s); 1164 } 1165 1166 retval = retval == 1 ? 1 : 1167 retval == 0 ? val : val != 0 ? val : retval; 1168 } 1169 1170 return retval; 1171 } 1172 1173 static void 1174 pci113x_insert(arg) 1175 void *arg; 1176 { 1177 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1178 u_int32_t sockevent, sockstate; 1179 1180 if (!(sc->sc_flags & CBB_INSERTING)) { 1181 /* We add a card only under inserting state. */ 1182 return; 1183 } 1184 sc->sc_flags &= ~CBB_INSERTING; 1185 1186 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1187 CB_SOCKET_EVENT); 1188 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1189 CB_SOCKET_STAT); 1190 1191 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1192 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1193 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1194 sc->sc_flags |= CBB_CARDEXIST; 1195 /* call pccard interrupt handler here */ 1196 if (sockstate & CB_SOCKET_STAT_16BIT) { 1197 /* 16-bit card found */ 1198 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1199 cardslot_event_throw(sc->sc_csc, 1200 CARDSLOT_EVENT_INSERTION_16); 1201 } else if (sockstate & CB_SOCKET_STAT_CB) { 1202 /* cardbus card found */ 1203 /* cardbus_attach_card(sc->sc_csc); */ 1204 cardslot_event_throw(sc->sc_csc, 1205 CARDSLOT_EVENT_INSERTION_CB); 1206 } else { 1207 /* who are you? */ 1208 } 1209 } else { 1210 callout_reset(&sc->sc_insert_ch, hz / 10, 1211 pci113x_insert, sc); 1212 } 1213 } 1214 1215 #define PCCBB_PCMCIA_OFFSET 0x800 1216 static u_int8_t 1217 pccbb_pcmcia_read(ph, reg) 1218 struct pcic_handle *ph; 1219 int reg; 1220 { 1221 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1222 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1223 1224 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1225 PCCBB_PCMCIA_OFFSET + reg); 1226 } 1227 1228 static void 1229 pccbb_pcmcia_write(ph, reg, val) 1230 struct pcic_handle *ph; 1231 int reg; 1232 u_int8_t val; 1233 { 1234 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1235 val); 1236 1237 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1238 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1239 } 1240 1241 /* 1242 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1243 */ 1244 STATIC int 1245 pccbb_ctrl(ct, command) 1246 cardbus_chipset_tag_t ct; 1247 int command; 1248 { 1249 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1250 1251 switch (command) { 1252 case CARDBUS_CD: 1253 if (2 == pccbb_detect_card(sc)) { 1254 int retval = 0; 1255 int status = cb_detect_voltage(sc); 1256 if (PCCARD_VCC_5V & status) { 1257 retval |= CARDBUS_5V_CARD; 1258 } 1259 if (PCCARD_VCC_3V & status) { 1260 retval |= CARDBUS_3V_CARD; 1261 } 1262 if (PCCARD_VCC_XV & status) { 1263 retval |= CARDBUS_XV_CARD; 1264 } 1265 if (PCCARD_VCC_YV & status) { 1266 retval |= CARDBUS_YV_CARD; 1267 } 1268 return retval; 1269 } else { 1270 return 0; 1271 } 1272 case CARDBUS_RESET: 1273 return cb_reset(sc); 1274 case CARDBUS_IO_ENABLE: /* fallthrough */ 1275 case CARDBUS_IO_DISABLE: /* fallthrough */ 1276 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1277 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1278 case CARDBUS_BM_ENABLE: /* fallthrough */ 1279 case CARDBUS_BM_DISABLE: /* fallthrough */ 1280 /* XXX: I think we don't need to call this function below. */ 1281 return pccbb_cardenable(sc, command); 1282 } 1283 1284 return 0; 1285 } 1286 1287 /* 1288 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1289 * This function returns true when it succeeds and returns false when 1290 * it fails. 1291 */ 1292 STATIC int 1293 pccbb_power(ct, command) 1294 cardbus_chipset_tag_t ct; 1295 int command; 1296 { 1297 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1298 u_int32_t status, sock_ctrl, reg_ctrl; 1299 bus_space_tag_t memt = sc->sc_base_memt; 1300 bus_space_handle_t memh = sc->sc_base_memh; 1301 int on = 0, pwrcycle; 1302 1303 DPRINTF(("pccbb_power: %s and %s [0x%x]\n", 1304 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1305 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1306 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1307 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1308 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1309 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1310 "UNKNOWN", 1311 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1312 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1313 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1314 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1315 "UNKNOWN", command)); 1316 1317 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1318 sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1319 1320 switch (command & CARDBUS_VCCMASK) { 1321 case CARDBUS_VCC_UC: 1322 break; 1323 case CARDBUS_VCC_5V: 1324 on++; 1325 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1326 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1327 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1328 } else { 1329 printf("%s: BAD voltage request: no 5 V card\n", 1330 sc->sc_dev.dv_xname); 1331 return 0; 1332 } 1333 break; 1334 case CARDBUS_VCC_3V: 1335 on++; 1336 if (CB_SOCKET_STAT_3VCARD & status) { 1337 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1338 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1339 } else { 1340 printf("%s: BAD voltage request: no 3.3 V card\n", 1341 sc->sc_dev.dv_xname); 1342 return 0; 1343 } 1344 break; 1345 case CARDBUS_VCC_0V: 1346 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1347 break; 1348 default: 1349 return 0; /* power NEVER changed */ 1350 } 1351 1352 switch (command & CARDBUS_VPPMASK) { 1353 case CARDBUS_VPP_UC: 1354 break; 1355 case CARDBUS_VPP_0V: 1356 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1357 break; 1358 case CARDBUS_VPP_VCC: 1359 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1360 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1361 break; 1362 case CARDBUS_VPP_12V: 1363 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1364 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1365 break; 1366 } 1367 1368 pwrcycle = sc->sc_pwrcycle; 1369 1370 #if 0 1371 DPRINTF(("sock_ctrl: 0x%x\n", sock_ctrl)); 1372 #endif 1373 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1374 1375 if (on) { 1376 int s, error = 0; 1377 struct timeval before, after, diff; 1378 1379 DPRINTF(("Waiting for bridge to power up\n")); 1380 microtime(&before); 1381 s = splbio(); 1382 while (pwrcycle == sc->sc_pwrcycle) { 1383 /* 1384 * XXX: Set timeout to 200ms because power cycle event 1385 * will never happen when attaching a 16-bit card. 1386 */ 1387 if ((error = tsleep(&sc->sc_pwrcycle, PWAIT, "pccpwr", 1388 hz / 5)) == EWOULDBLOCK) 1389 break; 1390 } 1391 splx(s); 1392 microtime(&after); 1393 timersub(&after, &before, &diff); 1394 aprint_debug("%s: wait took%s %ld.%06lds\n", 1395 sc->sc_dev.dv_xname, 1396 error == EWOULDBLOCK ? " too long" : "", 1397 diff.tv_sec, diff.tv_usec); 1398 } 1399 1400 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1401 1402 if (on && sc->sc_chipset != CB_TOPIC95B) { 1403 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0) 1404 printf("%s: power on failed?\n", sc->sc_dev.dv_xname); 1405 } 1406 1407 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1408 printf("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1409 sc->sc_dev.dv_xname, sock_ctrl, status); 1410 printf("%s: disabling socket\n", sc->sc_dev.dv_xname); 1411 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1412 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1413 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1414 status &= ~CB_SOCKET_STAT_BADVCC; 1415 bus_space_write_4(memt, memh, CB_SOCKET_STAT, status); 1416 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1417 CB_SOCKET_STAT)); 1418 return 0; 1419 } 1420 1421 if (sc->sc_chipset == CB_TOPIC97) { 1422 reg_ctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL); 1423 reg_ctrl &= ~TOPIC97_REG_CTRL_TESTMODE; 1424 if ((command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V) 1425 reg_ctrl &= ~TOPIC97_REG_CTRL_CLKRUN_ENA; 1426 else 1427 reg_ctrl |= TOPIC97_REG_CTRL_CLKRUN_ENA; 1428 pci_conf_write(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL, reg_ctrl); 1429 } 1430 1431 return 1; /* power changed correctly */ 1432 } 1433 1434 #if defined CB_PCMCIA_POLL 1435 struct cb_poll_str { 1436 void *arg; 1437 int (*func)(void *); 1438 int level; 1439 pccard_chipset_tag_t ct; 1440 int count; 1441 struct callout poll_ch; 1442 }; 1443 1444 static struct cb_poll_str cb_poll[10]; 1445 static int cb_poll_n = 0; 1446 1447 static void cb_pcmcia_poll(void *arg); 1448 1449 static void 1450 cb_pcmcia_poll(arg) 1451 void *arg; 1452 { 1453 struct cb_poll_str *poll = arg; 1454 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1455 struct pccbb_softc *sc = psc->cpc_parent; 1456 int s; 1457 u_int32_t spsr; /* socket present-state reg */ 1458 1459 callout_reset(&poll->poll_ch, hz / 10, cb_pcmcia_poll, poll); 1460 switch (poll->level) { 1461 case IPL_NET: 1462 s = splnet(); 1463 break; 1464 case IPL_BIO: 1465 s = splbio(); 1466 break; 1467 case IPL_TTY: /* fallthrough */ 1468 default: 1469 s = spltty(); 1470 break; 1471 } 1472 1473 spsr = 1474 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1475 CB_SOCKET_STAT); 1476 1477 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1478 if (!(spsr & 0x40)) { /* CINT low */ 1479 #else 1480 if (1) { 1481 #endif 1482 if ((*poll->func) (poll->arg) == 1) { 1483 ++poll->count; 1484 printf("intr: reported from poller, 0x%x\n", spsr); 1485 #if defined LEVEL2 1486 } else { 1487 printf("intr: miss! 0x%x\n", spsr); 1488 #endif 1489 } 1490 } 1491 splx(s); 1492 } 1493 #endif /* defined CB_PCMCIA_POLL */ 1494 1495 /* 1496 * static int pccbb_detect_card(struct pccbb_softc *sc) 1497 * return value: 0 if no card exists. 1498 * 1 if 16-bit card exists. 1499 * 2 if cardbus card exists. 1500 */ 1501 static int 1502 pccbb_detect_card(sc) 1503 struct pccbb_softc *sc; 1504 { 1505 bus_space_handle_t base_memh = sc->sc_base_memh; 1506 bus_space_tag_t base_memt = sc->sc_base_memt; 1507 u_int32_t sockstat = 1508 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1509 int retval = 0; 1510 1511 /* CD1 and CD2 asserted */ 1512 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1513 /* card must be present */ 1514 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1515 /* NOTACARD DEASSERTED */ 1516 if (CB_SOCKET_STAT_CB & sockstat) { 1517 /* CardBus mode */ 1518 retval = 2; 1519 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1520 /* 16-bit mode */ 1521 retval = 1; 1522 } 1523 } 1524 } 1525 return retval; 1526 } 1527 1528 /* 1529 * STATIC int cb_reset(struct pccbb_softc *sc) 1530 * This function resets CardBus card. 1531 */ 1532 STATIC int 1533 cb_reset(sc) 1534 struct pccbb_softc *sc; 1535 { 1536 /* 1537 * Reset Assert at least 20 ms 1538 * Some machines request longer duration. 1539 */ 1540 int reset_duration = 1541 (sc->sc_chipset == CB_RX5C47X ? 400 : 40); 1542 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1543 1544 /* Reset bit Assert (bit 6 at 0x3E) */ 1545 bcr |= CB_BCR_RESET_ENABLE; 1546 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1547 DELAY_MS(reset_duration, sc); 1548 1549 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1550 /* Reset bit Deassert (bit 6 at 0x3E) */ 1551 bcr &= ~CB_BCR_RESET_ENABLE; 1552 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1553 DELAY_MS(reset_duration, sc); 1554 } 1555 /* No card found on the slot. Keep Reset. */ 1556 return 1; 1557 } 1558 1559 /* 1560 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1561 * This function detect card Voltage. 1562 */ 1563 STATIC int 1564 cb_detect_voltage(sc) 1565 struct pccbb_softc *sc; 1566 { 1567 u_int32_t psr; /* socket present-state reg */ 1568 bus_space_tag_t iot = sc->sc_base_memt; 1569 bus_space_handle_t ioh = sc->sc_base_memh; 1570 int vol = PCCARD_VCC_UKN; /* set 0 */ 1571 1572 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1573 1574 if (0x400u & psr) { 1575 vol |= PCCARD_VCC_5V; 1576 } 1577 if (0x800u & psr) { 1578 vol |= PCCARD_VCC_3V; 1579 } 1580 1581 return vol; 1582 } 1583 1584 STATIC int 1585 cbbprint(aux, pcic) 1586 void *aux; 1587 const char *pcic; 1588 { 1589 /* 1590 struct cbslot_attach_args *cba = aux; 1591 1592 if (cba->cba_slot >= 0) { 1593 aprint_normal(" slot %d", cba->cba_slot); 1594 } 1595 */ 1596 return UNCONF; 1597 } 1598 1599 /* 1600 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1601 * This function enables and disables the card 1602 */ 1603 STATIC int 1604 pccbb_cardenable(sc, function) 1605 struct pccbb_softc *sc; 1606 int function; 1607 { 1608 u_int32_t command = 1609 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1610 1611 DPRINTF(("pccbb_cardenable:")); 1612 switch (function) { 1613 case CARDBUS_IO_ENABLE: 1614 command |= PCI_COMMAND_IO_ENABLE; 1615 break; 1616 case CARDBUS_IO_DISABLE: 1617 command &= ~PCI_COMMAND_IO_ENABLE; 1618 break; 1619 case CARDBUS_MEM_ENABLE: 1620 command |= PCI_COMMAND_MEM_ENABLE; 1621 break; 1622 case CARDBUS_MEM_DISABLE: 1623 command &= ~PCI_COMMAND_MEM_ENABLE; 1624 break; 1625 case CARDBUS_BM_ENABLE: 1626 command |= PCI_COMMAND_MASTER_ENABLE; 1627 break; 1628 case CARDBUS_BM_DISABLE: 1629 command &= ~PCI_COMMAND_MASTER_ENABLE; 1630 break; 1631 default: 1632 return 0; 1633 } 1634 1635 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1636 DPRINTF((" command reg 0x%x\n", command)); 1637 return 1; 1638 } 1639 1640 #if !rbus 1641 /* 1642 * int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1643 */ 1644 static int 1645 pccbb_io_open(ct, win, start, end) 1646 cardbus_chipset_tag_t ct; 1647 int win; 1648 u_int32_t start, end; 1649 { 1650 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1651 int basereg; 1652 int limitreg; 1653 1654 if ((win < 0) || (win > 2)) { 1655 #if defined DIAGNOSTIC 1656 printf("cardbus_io_open: window out of range %d\n", win); 1657 #endif 1658 return 0; 1659 } 1660 1661 basereg = win * 8 + 0x2c; 1662 limitreg = win * 8 + 0x30; 1663 1664 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1665 start, basereg, end, limitreg)); 1666 1667 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1668 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1669 return 1; 1670 } 1671 1672 /* 1673 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1674 */ 1675 static int 1676 pccbb_io_close(ct, win) 1677 cardbus_chipset_tag_t ct; 1678 int win; 1679 { 1680 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1681 int basereg; 1682 int limitreg; 1683 1684 if ((win < 0) || (win > 2)) { 1685 #if defined DIAGNOSTIC 1686 printf("cardbus_io_close: window out of range %d\n", win); 1687 #endif 1688 return 0; 1689 } 1690 1691 basereg = win * 8 + 0x2c; 1692 limitreg = win * 8 + 0x30; 1693 1694 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1695 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1696 return 1; 1697 } 1698 1699 /* 1700 * int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1701 */ 1702 static int 1703 pccbb_mem_open(ct, win, start, end) 1704 cardbus_chipset_tag_t ct; 1705 int win; 1706 u_int32_t start, end; 1707 { 1708 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1709 int basereg; 1710 int limitreg; 1711 1712 if ((win < 0) || (win > 2)) { 1713 #if defined DIAGNOSTIC 1714 printf("cardbus_mem_open: window out of range %d\n", win); 1715 #endif 1716 return 0; 1717 } 1718 1719 basereg = win * 8 + 0x1c; 1720 limitreg = win * 8 + 0x20; 1721 1722 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1723 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1724 return 1; 1725 } 1726 1727 /* 1728 * int pccbb_mem_close(cardbus_chipset_tag_t, int) 1729 */ 1730 static int 1731 pccbb_mem_close(ct, win) 1732 cardbus_chipset_tag_t ct; 1733 int win; 1734 { 1735 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1736 int basereg; 1737 int limitreg; 1738 1739 if ((win < 0) || (win > 2)) { 1740 #if defined DIAGNOSTIC 1741 printf("cardbus_mem_close: window out of range %d\n", win); 1742 #endif 1743 return 0; 1744 } 1745 1746 basereg = win * 8 + 0x1c; 1747 limitreg = win * 8 + 0x20; 1748 1749 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1750 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1751 return 1; 1752 } 1753 #endif 1754 1755 /* 1756 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1757 * int irq, 1758 * int level, 1759 * int (* func)(void *), 1760 * void *arg) 1761 * 1762 * This function registers an interrupt handler at the bridge, in 1763 * order not to call the interrupt handlers of child devices when 1764 * a card-deletion interrupt occurs. 1765 * 1766 * The arguments irq and level are not used. 1767 */ 1768 static void * 1769 pccbb_cb_intr_establish(ct, irq, level, func, arg) 1770 cardbus_chipset_tag_t ct; 1771 int irq, level; 1772 int (*func)(void *); 1773 void *arg; 1774 { 1775 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1776 1777 return pccbb_intr_establish(sc, irq, level, func, arg); 1778 } 1779 1780 1781 /* 1782 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1783 * void *ih) 1784 * 1785 * This function removes an interrupt handler pointed by ih. 1786 */ 1787 static void 1788 pccbb_cb_intr_disestablish(ct, ih) 1789 cardbus_chipset_tag_t ct; 1790 void *ih; 1791 { 1792 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1793 1794 pccbb_intr_disestablish(sc, ih); 1795 } 1796 1797 1798 void 1799 pccbb_intr_route(sc) 1800 struct pccbb_softc *sc; 1801 { 1802 pcireg_t reg; 1803 1804 /* initialize bridge intr routing */ 1805 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1806 reg &= ~CB_BCR_INTR_IREQ_ENABLE; 1807 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1808 1809 switch (sc->sc_chipset) { 1810 case CB_TI113X: 1811 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1812 /* functional intr enabled */ 1813 reg |= PCI113X_CBCTRL_PCI_INTR; 1814 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1815 break; 1816 default: 1817 break; 1818 } 1819 } 1820 1821 /* 1822 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1823 * int irq, 1824 * int level, 1825 * int (* func)(void *), 1826 * void *arg) 1827 * 1828 * This function registers an interrupt handler at the bridge, in 1829 * order not to call the interrupt handlers of child devices when 1830 * a card-deletion interrupt occurs. 1831 * 1832 * The arguments irq is not used because pccbb selects intr vector. 1833 */ 1834 static void * 1835 pccbb_intr_establish(sc, irq, level, func, arg) 1836 struct pccbb_softc *sc; 1837 int irq, level; 1838 int (*func)(void *); 1839 void *arg; 1840 { 1841 struct pccbb_intrhand_list *pil, *newpil; 1842 1843 DPRINTF(("pccbb_intr_establish start. %p\n", LIST_FIRST(&sc->sc_pil))); 1844 1845 if (LIST_EMPTY(&sc->sc_pil)) { 1846 pccbb_intr_route(sc); 1847 } 1848 1849 /* 1850 * Allocate a room for interrupt handler structure. 1851 */ 1852 if (NULL == (newpil = 1853 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1854 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1855 return NULL; 1856 } 1857 1858 newpil->pil_func = func; 1859 newpil->pil_arg = arg; 1860 newpil->pil_level = level; 1861 1862 if (LIST_EMPTY(&sc->sc_pil)) { 1863 LIST_INSERT_HEAD(&sc->sc_pil, newpil, pil_next); 1864 } else { 1865 for (pil = LIST_FIRST(&sc->sc_pil); 1866 LIST_NEXT(pil, pil_next) != NULL; 1867 pil = LIST_NEXT(pil, pil_next)); 1868 LIST_INSERT_AFTER(pil, newpil, pil_next); 1869 } 1870 1871 DPRINTF(("pccbb_intr_establish add pil. %p\n", 1872 LIST_FIRST(&sc->sc_pil))); 1873 1874 return newpil; 1875 } 1876 1877 /* 1878 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1879 * void *ih) 1880 * 1881 * This function removes an interrupt handler pointed by ih. ih 1882 * should be the value returned by cardbus_intr_establish() or 1883 * NULL. 1884 * 1885 * When ih is NULL, this function will do nothing. 1886 */ 1887 static void 1888 pccbb_intr_disestablish(sc, ih) 1889 struct pccbb_softc *sc; 1890 void *ih; 1891 { 1892 struct pccbb_intrhand_list *pil; 1893 pcireg_t reg; 1894 1895 DPRINTF(("pccbb_intr_disestablish start. %p\n", 1896 LIST_FIRST(&sc->sc_pil))); 1897 1898 if (ih == NULL) { 1899 /* intr handler is not set */ 1900 DPRINTF(("pccbb_intr_disestablish: no ih\n")); 1901 return; 1902 } 1903 1904 #ifdef DIAGNOSTIC 1905 for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1906 pil = LIST_NEXT(pil, pil_next)) { 1907 DPRINTF(("pccbb_intr_disestablish: pil %p\n", pil)); 1908 if (pil == ih) { 1909 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1910 break; 1911 } 1912 } 1913 if (pil == NULL) { 1914 panic("pccbb_intr_disestablish: %s cannot find pil %p", 1915 sc->sc_dev.dv_xname, ih); 1916 } 1917 #endif 1918 1919 pil = (struct pccbb_intrhand_list *)ih; 1920 LIST_REMOVE(pil, pil_next); 1921 free(pil, M_DEVBUF); 1922 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1923 1924 if (LIST_EMPTY(&sc->sc_pil)) { 1925 /* No interrupt handlers */ 1926 1927 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1928 1929 /* stop routing PCI intr */ 1930 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1931 reg |= CB_BCR_INTR_IREQ_ENABLE; 1932 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1933 1934 switch (sc->sc_chipset) { 1935 case CB_TI113X: 1936 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1937 /* functional intr disabled */ 1938 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1939 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1940 break; 1941 default: 1942 break; 1943 } 1944 } 1945 } 1946 1947 #if defined SHOW_REGS 1948 static void 1949 cb_show_regs(pc, tag, memt, memh) 1950 pci_chipset_tag_t pc; 1951 pcitag_t tag; 1952 bus_space_tag_t memt; 1953 bus_space_handle_t memh; 1954 { 1955 int i; 1956 printf("PCI config regs:"); 1957 for (i = 0; i < 0x50; i += 4) { 1958 if (i % 16 == 0) { 1959 printf("\n 0x%02x:", i); 1960 } 1961 printf(" %08x", pci_conf_read(pc, tag, i)); 1962 } 1963 for (i = 0x80; i < 0xb0; i += 4) { 1964 if (i % 16 == 0) { 1965 printf("\n 0x%02x:", i); 1966 } 1967 printf(" %08x", pci_conf_read(pc, tag, i)); 1968 } 1969 1970 if (memh == 0) { 1971 printf("\n"); 1972 return; 1973 } 1974 1975 printf("\nsocket regs:"); 1976 for (i = 0; i <= 0x10; i += 0x04) { 1977 printf(" %08x", bus_space_read_4(memt, memh, i)); 1978 } 1979 printf("\nExCA regs:"); 1980 for (i = 0; i < 0x08; ++i) { 1981 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1982 } 1983 printf("\n"); 1984 return; 1985 } 1986 #endif 1987 1988 /* 1989 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1990 * int busno, int function) 1991 * This is the function to make a tag to access config space of 1992 * a CardBus Card. It works same as pci_conf_read. 1993 */ 1994 static cardbustag_t 1995 pccbb_make_tag(cc, busno, function) 1996 cardbus_chipset_tag_t cc; 1997 int busno, function; 1998 { 1999 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 2000 2001 return pci_make_tag(sc->sc_pc, busno, 0, function); 2002 } 2003 2004 static void 2005 pccbb_free_tag(cc, tag) 2006 cardbus_chipset_tag_t cc; 2007 cardbustag_t tag; 2008 { 2009 } 2010 2011 /* 2012 * static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t cc, 2013 * cardbustag_t tag, int offset) 2014 * This is the function to read the config space of a CardBus Card. 2015 * It works same as pci_conf_read. 2016 */ 2017 static cardbusreg_t 2018 pccbb_conf_read(cc, tag, offset) 2019 cardbus_chipset_tag_t cc; 2020 cardbustag_t tag; 2021 int offset; /* register offset */ 2022 { 2023 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 2024 2025 return pci_conf_read(sc->sc_pc, tag, offset); 2026 } 2027 2028 /* 2029 * static void pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, 2030 * int offs, cardbusreg_t val) 2031 * This is the function to write the config space of a CardBus Card. 2032 * It works same as pci_conf_write. 2033 */ 2034 static void 2035 pccbb_conf_write(cc, tag, reg, val) 2036 cardbus_chipset_tag_t cc; 2037 cardbustag_t tag; 2038 int reg; /* register offset */ 2039 cardbusreg_t val; 2040 { 2041 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 2042 2043 pci_conf_write(sc->sc_pc, tag, reg, val); 2044 } 2045 2046 #if 0 2047 STATIC int 2048 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 2049 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 2050 int speed, int flags, 2051 bus_space_handle_t * iohp) 2052 #endif 2053 /* 2054 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 2055 * bus_addr_t start, bus_size_t size, 2056 * bus_size_t align, 2057 * struct pcmcia_io_handle *pcihp 2058 * 2059 * This function only allocates I/O region for pccard. This function 2060 * never maps the allocated region to pccard I/O area. 2061 * 2062 * XXX: The interface of this function is not very good, I believe. 2063 */ 2064 STATIC int 2065 pccbb_pcmcia_io_alloc(pch, start, size, align, pcihp) 2066 pcmcia_chipset_handle_t pch; 2067 bus_addr_t start; /* start address */ 2068 bus_size_t size; 2069 bus_size_t align; 2070 struct pcmcia_io_handle *pcihp; 2071 { 2072 struct pcic_handle *ph = (struct pcic_handle *)pch; 2073 bus_addr_t ioaddr; 2074 int flags = 0; 2075 bus_space_tag_t iot; 2076 bus_space_handle_t ioh; 2077 bus_addr_t mask; 2078 #if rbus 2079 rbus_tag_t rb; 2080 #endif 2081 if (align == 0) { 2082 align = size; /* XXX: funny??? */ 2083 } 2084 2085 if (start != 0) { 2086 /* XXX: assume all card decode lower 10 bits by its hardware */ 2087 mask = 0x3ff; 2088 /* enforce to use only masked address */ 2089 start &= mask; 2090 } else { 2091 /* 2092 * calculate mask: 2093 * 1. get the most significant bit of size (call it msb). 2094 * 2. compare msb with the value of size. 2095 * 3. if size is larger, shift msb left once. 2096 * 4. obtain mask value to decrement msb. 2097 */ 2098 bus_size_t size_tmp = size; 2099 int shifts = 0; 2100 2101 mask = 1; 2102 while (size_tmp) { 2103 ++shifts; 2104 size_tmp >>= 1; 2105 } 2106 mask = (1 << shifts); 2107 if (mask < size) { 2108 mask <<= 1; 2109 } 2110 --mask; 2111 } 2112 2113 /* 2114 * Allocate some arbitrary I/O space. 2115 */ 2116 2117 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 2118 2119 #if rbus 2120 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 2121 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 2122 return 1; 2123 } 2124 DPRINTF(("pccbb_pcmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2125 (u_long) ioaddr, (u_long) size)); 2126 #else 2127 if (start) { 2128 ioaddr = start; 2129 if (bus_space_map(iot, start, size, 0, &ioh)) { 2130 return 1; 2131 } 2132 DPRINTF(("pccbb_pcmcia_io_alloc map port 0x%lx+0x%lx\n", 2133 (u_long) ioaddr, (u_long) size)); 2134 } else { 2135 flags |= PCMCIA_IO_ALLOCATED; 2136 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 2137 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 2138 size, align, 0, 0, &ioaddr, &ioh)) { 2139 /* No room be able to be get. */ 2140 return 1; 2141 } 2142 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2143 (u_long) ioaddr, (u_long) size)); 2144 } 2145 #endif 2146 2147 pcihp->iot = iot; 2148 pcihp->ioh = ioh; 2149 pcihp->addr = ioaddr; 2150 pcihp->size = size; 2151 pcihp->flags = flags; 2152 2153 return 0; 2154 } 2155 2156 /* 2157 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2158 * struct pcmcia_io_handle *pcihp) 2159 * 2160 * This function only frees I/O region for pccard. 2161 * 2162 * XXX: The interface of this function is not very good, I believe. 2163 */ 2164 void 2165 pccbb_pcmcia_io_free(pch, pcihp) 2166 pcmcia_chipset_handle_t pch; 2167 struct pcmcia_io_handle *pcihp; 2168 { 2169 #if !rbus 2170 bus_space_tag_t iot = pcihp->iot; 2171 #endif 2172 bus_space_handle_t ioh = pcihp->ioh; 2173 bus_size_t size = pcihp->size; 2174 2175 #if rbus 2176 struct pccbb_softc *sc = 2177 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 2178 rbus_tag_t rb = sc->sc_rbus_iot; 2179 2180 rbus_space_free(rb, ioh, size, NULL); 2181 #else 2182 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 2183 bus_space_free(iot, ioh, size); 2184 else 2185 bus_space_unmap(iot, ioh, size); 2186 #endif 2187 } 2188 2189 /* 2190 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 2191 * bus_addr_t offset, bus_size_t size, 2192 * struct pcmcia_io_handle *pcihp, 2193 * int *windowp) 2194 * 2195 * This function maps the allocated I/O region to pccard. This function 2196 * never allocates any I/O region for pccard I/O area. I don't 2197 * understand why the original authors of pcmciabus separated alloc and 2198 * map. I believe the two must be unite. 2199 * 2200 * XXX: no wait timing control? 2201 */ 2202 int 2203 pccbb_pcmcia_io_map(pch, width, offset, size, pcihp, windowp) 2204 pcmcia_chipset_handle_t pch; 2205 int width; 2206 bus_addr_t offset; 2207 bus_size_t size; 2208 struct pcmcia_io_handle *pcihp; 2209 int *windowp; 2210 { 2211 struct pcic_handle *ph = (struct pcic_handle *)pch; 2212 bus_addr_t ioaddr = pcihp->addr + offset; 2213 int i, win; 2214 #if defined CBB_DEBUG 2215 static const char *width_names[] = { "dynamic", "io8", "io16" }; 2216 #endif 2217 2218 /* Sanity check I/O handle. */ 2219 2220 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 2221 panic("pccbb_pcmcia_io_map iot is bogus"); 2222 } 2223 2224 /* XXX Sanity check offset/size. */ 2225 2226 win = -1; 2227 for (i = 0; i < PCIC_IO_WINS; i++) { 2228 if ((ph->ioalloc & (1 << i)) == 0) { 2229 win = i; 2230 ph->ioalloc |= (1 << i); 2231 break; 2232 } 2233 } 2234 2235 if (win == -1) { 2236 return 1; 2237 } 2238 2239 *windowp = win; 2240 2241 /* XXX this is pretty gross */ 2242 2243 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2244 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2245 2246 /* XXX wtf is this doing here? */ 2247 2248 #if 0 2249 printf(" port 0x%lx", (u_long) ioaddr); 2250 if (size > 1) { 2251 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2252 } 2253 #endif 2254 2255 ph->io[win].addr = ioaddr; 2256 ph->io[win].size = size; 2257 ph->io[win].width = width; 2258 2259 /* actual dirty register-value changing in the function below. */ 2260 pccbb_pcmcia_do_io_map(ph, win); 2261 2262 return 0; 2263 } 2264 2265 /* 2266 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2267 * 2268 * This function changes register-value to map I/O region for pccard. 2269 */ 2270 static void 2271 pccbb_pcmcia_do_io_map(ph, win) 2272 struct pcic_handle *ph; 2273 int win; 2274 { 2275 static u_int8_t pcic_iowidth[3] = { 2276 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2277 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2278 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2279 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2280 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2281 }; 2282 2283 #define PCIC_SIA_START_LOW 0 2284 #define PCIC_SIA_START_HIGH 1 2285 #define PCIC_SIA_STOP_LOW 2 2286 #define PCIC_SIA_STOP_HIGH 3 2287 2288 int regbase_win = 0x8 + win * 0x04; 2289 u_int8_t ioctl, enable; 2290 2291 DPRINTF(("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx " 2292 "width %d\n", win, (unsigned long)ph->io[win].addr, 2293 (unsigned long)ph->io[win].size, ph->io[win].width * 8)); 2294 2295 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2296 ph->io[win].addr & 0xff); 2297 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2298 (ph->io[win].addr >> 8) & 0xff); 2299 2300 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2301 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2302 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2303 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2304 2305 ioctl = Pcic_read(ph, PCIC_IOCTL); 2306 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2307 switch (win) { 2308 case 0: 2309 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2310 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2311 PCIC_IOCTL_IO0_DATASIZE_MASK); 2312 ioctl |= pcic_iowidth[ph->io[win].width]; 2313 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2314 break; 2315 case 1: 2316 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2317 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2318 PCIC_IOCTL_IO1_DATASIZE_MASK); 2319 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2320 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2321 break; 2322 } 2323 Pcic_write(ph, PCIC_IOCTL, ioctl); 2324 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2325 #if defined CBB_DEBUG 2326 { 2327 u_int8_t start_low = 2328 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2329 u_int8_t start_high = 2330 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2331 u_int8_t stop_low = 2332 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2333 u_int8_t stop_high = 2334 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2335 printf 2336 (" start %02x %02x, stop %02x %02x, ioctl %02x enable %02x\n", 2337 start_low, start_high, stop_low, stop_high, ioctl, enable); 2338 } 2339 #endif 2340 } 2341 2342 /* 2343 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2344 * 2345 * This function unmaps I/O region. No return value. 2346 */ 2347 STATIC void 2348 pccbb_pcmcia_io_unmap(pch, win) 2349 pcmcia_chipset_handle_t pch; 2350 int win; 2351 { 2352 struct pcic_handle *ph = (struct pcic_handle *)pch; 2353 int reg; 2354 2355 if (win >= PCIC_IO_WINS || win < 0) { 2356 panic("pccbb_pcmcia_io_unmap: window out of range"); 2357 } 2358 2359 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2360 switch (win) { 2361 case 0: 2362 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2363 break; 2364 case 1: 2365 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2366 break; 2367 } 2368 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2369 2370 ph->ioalloc &= ~(1 << win); 2371 } 2372 2373 static int 2374 pccbb_pcmcia_wait_ready(ph) 2375 struct pcic_handle *ph; 2376 { 2377 u_int8_t stat; 2378 int i; 2379 2380 /* wait an initial 10ms for quick cards */ 2381 stat = Pcic_read(ph, PCIC_IF_STATUS); 2382 if (stat & PCIC_IF_STATUS_READY) 2383 return (0); 2384 pccbb_pcmcia_delay(ph, 10, "pccwr0"); 2385 for (i = 0; i < 50; i++) { 2386 stat = Pcic_read(ph, PCIC_IF_STATUS); 2387 if (stat & PCIC_IF_STATUS_READY) 2388 return (0); 2389 if ((stat & PCIC_IF_STATUS_CARDDETECT_MASK) != 2390 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2391 return (ENXIO); 2392 /* wait .1s (100ms) each iteration now */ 2393 pccbb_pcmcia_delay(ph, 100, "pccwr1"); 2394 } 2395 2396 printf("pccbb_pcmcia_wait_ready: ready never happened, status=%02x\n", stat); 2397 return (EWOULDBLOCK); 2398 } 2399 2400 /* 2401 * Perform long (msec order) delay. 2402 */ 2403 static void 2404 pccbb_pcmcia_delay(ph, timo, wmesg) 2405 struct pcic_handle *ph; 2406 int timo; /* in ms. must not be zero */ 2407 const char *wmesg; 2408 { 2409 2410 #ifdef DIAGNOSTIC 2411 if (timo <= 0) 2412 panic("pccbb_pcmcia_delay: called with timeout %d", timo); 2413 if (!curlwp) 2414 panic("pccbb_pcmcia_delay: called in interrupt context"); 2415 #if 0 2416 if (!ph->event_thread) 2417 panic("pccbb_pcmcia_delay: no event thread"); 2418 #endif 2419 #endif 2420 DPRINTF(("pccbb_pcmcia_delay: \"%s\" %p, sleep %d ms\n", 2421 wmesg, ph->event_thread, timo)); 2422 tsleep(pccbb_pcmcia_delay, PWAIT, wmesg, roundup(timo * hz, 1000) / 1000); 2423 } 2424 2425 /* 2426 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2427 * 2428 * This function enables the card. All information is stored in 2429 * the first argument, pcmcia_chipset_handle_t. 2430 */ 2431 STATIC void 2432 pccbb_pcmcia_socket_enable(pch) 2433 pcmcia_chipset_handle_t pch; 2434 { 2435 struct pcic_handle *ph = (struct pcic_handle *)pch; 2436 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2437 pcireg_t spsr; 2438 int voltage; 2439 int win; 2440 u_int8_t power, intr; 2441 #ifdef DIAGNOSTIC 2442 int reg; 2443 #endif 2444 2445 /* this bit is mostly stolen from pcic_attach_card */ 2446 2447 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2448 2449 /* get card Vcc info */ 2450 spsr = 2451 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2452 CB_SOCKET_STAT); 2453 if (spsr & CB_SOCKET_STAT_5VCARD) { 2454 DPRINTF(("5V card\n")); 2455 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2456 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2457 DPRINTF(("3V card\n")); 2458 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2459 } else { 2460 printf("?V card, 0x%x\n", spsr); /* XXX */ 2461 return; 2462 } 2463 2464 /* disable interrupts; assert RESET */ 2465 intr = Pcic_read(ph, PCIC_INTR); 2466 intr &= PCIC_INTR_ENABLE; 2467 Pcic_write(ph, PCIC_INTR, intr); 2468 2469 /* zero out the address windows */ 2470 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2471 2472 /* power down the socket to reset it, clear the card reset pin */ 2473 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2474 2475 /* power off; assert output enable bit */ 2476 power = PCIC_PWRCTL_OE; 2477 Pcic_write(ph, PCIC_PWRCTL, power); 2478 2479 /* power up the socket */ 2480 if (pccbb_power(sc, voltage) == 0) 2481 return; 2482 2483 /* 2484 * Table 4-18 and figure 4-6 of the PC Card specifiction say: 2485 * Vcc Rising Time (Tpr) = 100ms (handled in pccbb_power() above) 2486 * RESET Width (Th (Hi-z RESET)) = 1ms 2487 * RESET Width (Tw (RESET)) = 10us 2488 * 2489 * some machines require some more time to be settled 2490 * for example old toshiba topic bridges! 2491 * (100ms is added here). 2492 */ 2493 pccbb_pcmcia_delay(ph, 200 + 1, "pccen1"); 2494 2495 /* negate RESET */ 2496 intr |= PCIC_INTR_RESET; 2497 Pcic_write(ph, PCIC_INTR, intr); 2498 2499 /* 2500 * RESET Setup Time (Tsu (RESET)) = 20ms 2501 */ 2502 pccbb_pcmcia_delay(ph, 20, "pccen2"); 2503 2504 #ifdef DIAGNOSTIC 2505 reg = Pcic_read(ph, PCIC_IF_STATUS); 2506 if ((reg & PCIC_IF_STATUS_POWERACTIVE) == 0) 2507 printf("pccbb_pcmcia_socket_enable: no power, status=%x\n", reg); 2508 #endif 2509 2510 /* wait for the chip to finish initializing */ 2511 if (pccbb_pcmcia_wait_ready(ph)) { 2512 /* XXX return a failure status?? */ 2513 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2514 Pcic_write(ph, PCIC_PWRCTL, 0); 2515 return; 2516 } 2517 2518 /* reinstall all the memory and io mappings */ 2519 for (win = 0; win < PCIC_MEM_WINS; ++win) 2520 if (ph->memalloc & (1 << win)) 2521 pccbb_pcmcia_do_mem_map(ph, win); 2522 for (win = 0; win < PCIC_IO_WINS; ++win) 2523 if (ph->ioalloc & (1 << win)) 2524 pccbb_pcmcia_do_io_map(ph, win); 2525 } 2526 2527 /* 2528 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2529 * 2530 * This function disables the card. All information is stored in 2531 * the first argument, pcmcia_chipset_handle_t. 2532 */ 2533 STATIC void 2534 pccbb_pcmcia_socket_disable(pch) 2535 pcmcia_chipset_handle_t pch; 2536 { 2537 struct pcic_handle *ph = (struct pcic_handle *)pch; 2538 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2539 u_int8_t intr; 2540 2541 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2542 2543 /* disable interrupts; assert RESET */ 2544 intr = Pcic_read(ph, PCIC_INTR); 2545 intr &= PCIC_INTR_ENABLE; 2546 Pcic_write(ph, PCIC_INTR, intr); 2547 2548 /* zero out the address windows */ 2549 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2550 2551 /* power down the socket to reset it, clear the card reset pin */ 2552 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2553 2554 /* disable socket: negate output enable bit and power off */ 2555 Pcic_write(ph, PCIC_PWRCTL, 0); 2556 2557 /* 2558 * Vcc Falling Time (Tpf) = 300ms 2559 */ 2560 pccbb_pcmcia_delay(ph, 300, "pccwr1"); 2561 } 2562 2563 STATIC void 2564 pccbb_pcmcia_socket_settype(pch, type) 2565 pcmcia_chipset_handle_t pch; 2566 int type; 2567 { 2568 struct pcic_handle *ph = (struct pcic_handle *)pch; 2569 u_int8_t intr; 2570 2571 /* set the card type */ 2572 2573 intr = Pcic_read(ph, PCIC_INTR); 2574 intr &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_CARDTYPE_MASK); 2575 if (type == PCMCIA_IFTYPE_IO) 2576 intr |= PCIC_INTR_CARDTYPE_IO; 2577 else 2578 intr |= PCIC_INTR_CARDTYPE_MEM; 2579 Pcic_write(ph, PCIC_INTR, intr); 2580 2581 DPRINTF(("%s: pccbb_pcmcia_socket_settype %02x type %s %02x\n", 2582 ph->ph_parent->dv_xname, ph->sock, 2583 ((type == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2584 } 2585 2586 /* 2587 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2588 * 2589 * This function detects whether a card is in the slot or not. 2590 * If a card is inserted, return 1. Otherwise, return 0. 2591 */ 2592 STATIC int 2593 pccbb_pcmcia_card_detect(pch) 2594 pcmcia_chipset_handle_t pch; 2595 { 2596 struct pcic_handle *ph = (struct pcic_handle *)pch; 2597 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2598 2599 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2600 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2601 } 2602 2603 #if 0 2604 STATIC int 2605 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2606 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2607 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2608 #endif 2609 /* 2610 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2611 * bus_size_t size, 2612 * struct pcmcia_mem_handle *pcmhp) 2613 * 2614 * This function only allocates memory region for pccard. This 2615 * function never maps the allocated region to pccard memory area. 2616 * 2617 * XXX: Why the argument of start address is not in? 2618 */ 2619 STATIC int 2620 pccbb_pcmcia_mem_alloc(pch, size, pcmhp) 2621 pcmcia_chipset_handle_t pch; 2622 bus_size_t size; 2623 struct pcmcia_mem_handle *pcmhp; 2624 { 2625 struct pcic_handle *ph = (struct pcic_handle *)pch; 2626 bus_space_handle_t memh; 2627 bus_addr_t addr; 2628 bus_size_t sizepg; 2629 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2630 #if rbus 2631 rbus_tag_t rb; 2632 #endif 2633 2634 /* Check that the card is still there. */ 2635 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2636 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2637 return 1; 2638 2639 /* out of sc->memh, allocate as many pages as necessary */ 2640 2641 /* convert size to PCIC pages */ 2642 /* 2643 * This is not enough; when the requested region is on the page 2644 * boundaries, this may calculate wrong result. 2645 */ 2646 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2647 #if 0 2648 if (sizepg > PCIC_MAX_MEM_PAGES) { 2649 return 1; 2650 } 2651 #endif 2652 2653 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2654 return 1; 2655 } 2656 2657 addr = 0; /* XXX gcc -Wuninitialized */ 2658 2659 #if rbus 2660 rb = sc->sc_rbus_memt; 2661 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2662 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2663 &addr, &memh)) { 2664 return 1; 2665 } 2666 #else 2667 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2668 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2669 0, /* boundary */ 2670 0, /* flags */ 2671 &addr, &memh)) { 2672 return 1; 2673 } 2674 #endif 2675 2676 DPRINTF(("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, " 2677 "realsize 0x%lx\n", (unsigned long)addr, (unsigned long)size, 2678 (unsigned long)sizepg * PCIC_MEM_PAGESIZE)); 2679 2680 pcmhp->memt = sc->sc_memt; 2681 pcmhp->memh = memh; 2682 pcmhp->addr = addr; 2683 pcmhp->size = size; 2684 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2685 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2686 pcmhp->mhandle = 0; 2687 /* No offset??? Funny. */ 2688 2689 return 0; 2690 } 2691 2692 /* 2693 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2694 * struct pcmcia_mem_handle *pcmhp) 2695 * 2696 * This function release the memory space allocated by the function 2697 * pccbb_pcmcia_mem_alloc(). 2698 */ 2699 STATIC void 2700 pccbb_pcmcia_mem_free(pch, pcmhp) 2701 pcmcia_chipset_handle_t pch; 2702 struct pcmcia_mem_handle *pcmhp; 2703 { 2704 #if rbus 2705 struct pcic_handle *ph = (struct pcic_handle *)pch; 2706 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2707 2708 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2709 #else 2710 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2711 #endif 2712 } 2713 2714 /* 2715 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2716 * 2717 * This function release the memory space allocated by the function 2718 * pccbb_pcmcia_mem_alloc(). 2719 */ 2720 STATIC void 2721 pccbb_pcmcia_do_mem_map(ph, win) 2722 struct pcic_handle *ph; 2723 int win; 2724 { 2725 int regbase_win; 2726 bus_addr_t phys_addr; 2727 bus_addr_t phys_end; 2728 2729 #define PCIC_SMM_START_LOW 0 2730 #define PCIC_SMM_START_HIGH 1 2731 #define PCIC_SMM_STOP_LOW 2 2732 #define PCIC_SMM_STOP_HIGH 3 2733 #define PCIC_CMA_LOW 4 2734 #define PCIC_CMA_HIGH 5 2735 2736 u_int8_t start_low, start_high = 0; 2737 u_int8_t stop_low, stop_high; 2738 u_int8_t off_low, off_high; 2739 u_int8_t mem_window; 2740 int reg; 2741 2742 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2743 int mem8 = 2744 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2745 || (kind == PCMCIA_MEM_ATTR); 2746 2747 regbase_win = 0x10 + win * 0x08; 2748 2749 phys_addr = ph->mem[win].addr; 2750 phys_end = phys_addr + ph->mem[win].size; 2751 2752 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2753 (unsigned long)phys_addr, (unsigned long)phys_end, 2754 (unsigned long)ph->mem[win].offset)); 2755 2756 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2757 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2758 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2759 2760 /* bit 19:12 */ 2761 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2762 /* bit 23:20 and bit 7 on */ 2763 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2764 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2765 /* bit 31:24, for 32-bit address */ 2766 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2767 2768 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2769 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2770 2771 if (((struct pccbb_softc *)ph-> 2772 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2773 Pcic_write(ph, 0x40 + win, mem_window); 2774 } 2775 2776 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2777 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2778 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2779 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2780 2781 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2782 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2783 2784 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2785 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2786 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2787 | ((kind == PCMCIA_MEM_ATTR) ? 2788 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2789 2790 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2791 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2792 2793 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2794 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2795 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2796 2797 #if defined CBB_DEBUG 2798 { 2799 int r1, r2, r3, r4, r5, r6, r7 = 0; 2800 2801 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2802 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2803 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2804 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2805 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2806 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2807 if (((struct pccbb_softc *)(ph-> 2808 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2809 r7 = Pcic_read(ph, 0x40 + win); 2810 } 2811 2812 DPRINTF(("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2813 "%02x%02x", win, r1, r2, r3, r4, r5, r6)); 2814 if (((struct pccbb_softc *)(ph-> 2815 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2816 DPRINTF((" %02x", r7)); 2817 } 2818 DPRINTF(("\n")); 2819 } 2820 #endif 2821 } 2822 2823 /* 2824 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2825 * bus_addr_t card_addr, bus_size_t size, 2826 * struct pcmcia_mem_handle *pcmhp, 2827 * bus_addr_t *offsetp, int *windowp) 2828 * 2829 * This function maps memory space allocated by the function 2830 * pccbb_pcmcia_mem_alloc(). 2831 */ 2832 STATIC int 2833 pccbb_pcmcia_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 2834 pcmcia_chipset_handle_t pch; 2835 int kind; 2836 bus_addr_t card_addr; 2837 bus_size_t size; 2838 struct pcmcia_mem_handle *pcmhp; 2839 bus_addr_t *offsetp; 2840 int *windowp; 2841 { 2842 struct pcic_handle *ph = (struct pcic_handle *)pch; 2843 bus_addr_t busaddr; 2844 long card_offset; 2845 int win; 2846 2847 /* Check that the card is still there. */ 2848 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2849 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2850 return 1; 2851 2852 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2853 if ((ph->memalloc & (1 << win)) == 0) { 2854 ph->memalloc |= (1 << win); 2855 break; 2856 } 2857 } 2858 2859 if (win == PCIC_MEM_WINS) { 2860 return 1; 2861 } 2862 2863 *windowp = win; 2864 2865 /* XXX this is pretty gross */ 2866 2867 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2868 panic("pccbb_pcmcia_mem_map memt is bogus"); 2869 } 2870 2871 busaddr = pcmhp->addr; 2872 2873 /* 2874 * compute the address offset to the pcmcia address space for the 2875 * pcic. this is intentionally signed. The masks and shifts below 2876 * will cause TRT to happen in the pcic registers. Deal with making 2877 * sure the address is aligned, and return the alignment offset. 2878 */ 2879 2880 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2881 card_addr -= *offsetp; 2882 2883 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2884 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2885 (u_long) card_addr)); 2886 2887 /* 2888 * include the offset in the size, and decrement size by one, since 2889 * the hw wants start/stop 2890 */ 2891 size += *offsetp - 1; 2892 2893 card_offset = (((long)card_addr) - ((long)busaddr)); 2894 2895 ph->mem[win].addr = busaddr; 2896 ph->mem[win].size = size; 2897 ph->mem[win].offset = card_offset; 2898 ph->mem[win].kind = kind; 2899 2900 pccbb_pcmcia_do_mem_map(ph, win); 2901 2902 return 0; 2903 } 2904 2905 /* 2906 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2907 * int window) 2908 * 2909 * This function unmaps memory space which mapped by the function 2910 * pccbb_pcmcia_mem_map(). 2911 */ 2912 STATIC void 2913 pccbb_pcmcia_mem_unmap(pch, window) 2914 pcmcia_chipset_handle_t pch; 2915 int window; 2916 { 2917 struct pcic_handle *ph = (struct pcic_handle *)pch; 2918 int reg; 2919 2920 if (window >= PCIC_MEM_WINS) { 2921 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2922 } 2923 2924 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2925 reg &= ~(1 << window); 2926 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2927 2928 ph->memalloc &= ~(1 << window); 2929 } 2930 2931 #if defined PCCBB_PCMCIA_POLL 2932 struct pccbb_poll_str { 2933 void *arg; 2934 int (*func)(void *); 2935 int level; 2936 struct pcic_handle *ph; 2937 int count; 2938 int num; 2939 struct callout poll_ch; 2940 }; 2941 2942 static struct pccbb_poll_str pccbb_poll[10]; 2943 static int pccbb_poll_n = 0; 2944 2945 static void pccbb_pcmcia_poll(void *arg); 2946 2947 static void 2948 pccbb_pcmcia_poll(arg) 2949 void *arg; 2950 { 2951 struct pccbb_poll_str *poll = arg; 2952 struct pcic_handle *ph = poll->ph; 2953 struct pccbb_softc *sc = ph->sc; 2954 int s; 2955 u_int32_t spsr; /* socket present-state reg */ 2956 2957 callout_reset(&poll->poll_ch, hz * 2, pccbb_pcmcia_poll, arg); 2958 switch (poll->level) { 2959 case IPL_NET: 2960 s = splnet(); 2961 break; 2962 case IPL_BIO: 2963 s = splbio(); 2964 break; 2965 case IPL_TTY: /* fallthrough */ 2966 default: 2967 s = spltty(); 2968 break; 2969 } 2970 2971 spsr = 2972 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2973 CB_SOCKET_STAT); 2974 2975 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2976 if (!(spsr & 0x40)) /* CINT low */ 2977 #else 2978 if (1) 2979 #endif 2980 { 2981 if ((*poll->func) (poll->arg) > 0) { 2982 ++poll->count; 2983 /* printf("intr: reported from poller, 0x%x\n", spsr); */ 2984 #if defined LEVEL2 2985 } else { 2986 printf("intr: miss! 0x%x\n", spsr); 2987 #endif 2988 } 2989 } 2990 splx(s); 2991 } 2992 #endif /* defined CB_PCMCIA_POLL */ 2993 2994 /* 2995 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2996 * struct pcmcia_function *pf, 2997 * int ipl, 2998 * int (*func)(void *), 2999 * void *arg); 3000 * 3001 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 3002 */ 3003 STATIC void * 3004 pccbb_pcmcia_intr_establish(pch, pf, ipl, func, arg) 3005 pcmcia_chipset_handle_t pch; 3006 struct pcmcia_function *pf; 3007 int ipl; 3008 int (*func)(void *); 3009 void *arg; 3010 { 3011 struct pcic_handle *ph = (struct pcic_handle *)pch; 3012 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 3013 3014 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 3015 /* what should I do? */ 3016 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 3017 DPRINTF(("%s does not provide edge nor pulse " 3018 "interrupt\n", sc->sc_dev.dv_xname)); 3019 return NULL; 3020 } 3021 /* 3022 * XXX Noooooo! The interrupt flag must set properly!! 3023 * dumb pcmcia driver!! 3024 */ 3025 } 3026 3027 return pccbb_intr_establish(sc, 0, ipl, func, arg); 3028 } 3029 3030 /* 3031 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 3032 * void *ih) 3033 * 3034 * This function disables PC-Card interrupt. 3035 */ 3036 STATIC void 3037 pccbb_pcmcia_intr_disestablish(pch, ih) 3038 pcmcia_chipset_handle_t pch; 3039 void *ih; 3040 { 3041 struct pcic_handle *ph = (struct pcic_handle *)pch; 3042 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 3043 3044 pccbb_intr_disestablish(sc, ih); 3045 } 3046 3047 #if rbus 3048 /* 3049 * static int 3050 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 3051 * bus_addr_t addr, bus_size_t size, 3052 * bus_addr_t mask, bus_size_t align, 3053 * int flags, bus_addr_t *addrp; 3054 * bus_space_handle_t *bshp) 3055 * 3056 * This function allocates a portion of memory or io space for 3057 * clients. This function is called from CardBus card drivers. 3058 */ 3059 static int 3060 pccbb_rbus_cb_space_alloc(ct, rb, addr, size, mask, align, flags, addrp, bshp) 3061 cardbus_chipset_tag_t ct; 3062 rbus_tag_t rb; 3063 bus_addr_t addr; 3064 bus_size_t size; 3065 bus_addr_t mask; 3066 bus_size_t align; 3067 int flags; 3068 bus_addr_t *addrp; 3069 bus_space_handle_t *bshp; 3070 { 3071 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 3072 3073 DPRINTF(("pccbb_rbus_cb_space_alloc: addr 0x%lx, size 0x%lx, " 3074 "mask 0x%lx, align 0x%lx\n", (unsigned long)addr, 3075 (unsigned long)size, (unsigned long)mask, (unsigned long)align)); 3076 3077 if (align == 0) { 3078 align = size; 3079 } 3080 3081 if (rb->rb_bt == sc->sc_memt) { 3082 if (align < 16) { 3083 return 1; 3084 } 3085 /* 3086 * XXX: align more than 0x1000 to avoid overwrapping 3087 * memory windows for two or more devices. 0x1000 3088 * means memory window's granularity. 3089 * 3090 * Two or more devices should be able to share same 3091 * memory window region. However, overrapping memory 3092 * window is not good because some devices, such as 3093 * 3Com 3C575[BC], have a broken address decoder and 3094 * intrude other's memory region. 3095 */ 3096 if (align < 0x1000) { 3097 align = 0x1000; 3098 } 3099 } else if (rb->rb_bt == sc->sc_iot) { 3100 if (align < 4) { 3101 return 1; 3102 } 3103 /* XXX: hack for avoiding ISA image */ 3104 if (mask < 0x0100) { 3105 mask = 0x3ff; 3106 addr = 0x300; 3107 } 3108 3109 } else { 3110 DPRINTF(("pccbb_rbus_cb_space_alloc: Bus space tag 0x%lx is " 3111 "NOT used. io: 0x%lx, mem: 0x%lx\n", 3112 (unsigned long)rb->rb_bt, (unsigned long)sc->sc_iot, 3113 (unsigned long)sc->sc_memt)); 3114 return 1; 3115 /* XXX: panic here? */ 3116 } 3117 3118 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 3119 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 3120 return 1; 3121 } 3122 3123 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 3124 3125 return 0; 3126 } 3127 3128 /* 3129 * static int 3130 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 3131 * bus_space_handle_t *bshp, bus_size_t size); 3132 * 3133 * This function is called from CardBus card drivers. 3134 */ 3135 static int 3136 pccbb_rbus_cb_space_free(ct, rb, bsh, size) 3137 cardbus_chipset_tag_t ct; 3138 rbus_tag_t rb; 3139 bus_space_handle_t bsh; 3140 bus_size_t size; 3141 { 3142 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 3143 bus_space_tag_t bt = rb->rb_bt; 3144 3145 pccbb_close_win(sc, bt, bsh, size); 3146 3147 if (bt == sc->sc_memt) { 3148 } else if (bt == sc->sc_iot) { 3149 } else { 3150 return 1; 3151 /* XXX: panic here? */ 3152 } 3153 3154 return rbus_space_free(rb, bsh, size, NULL); 3155 } 3156 #endif /* rbus */ 3157 3158 #if rbus 3159 3160 static int 3161 pccbb_open_win(sc, bst, addr, size, bsh, flags) 3162 struct pccbb_softc *sc; 3163 bus_space_tag_t bst; 3164 bus_addr_t addr; 3165 bus_size_t size; 3166 bus_space_handle_t bsh; 3167 int flags; 3168 { 3169 struct pccbb_win_chain_head *head; 3170 bus_addr_t align; 3171 3172 head = &sc->sc_iowindow; 3173 align = 0x04; 3174 if (sc->sc_memt == bst) { 3175 head = &sc->sc_memwindow; 3176 align = 0x1000; 3177 DPRINTF(("using memory window, 0x%lx 0x%lx 0x%lx\n\n", 3178 (unsigned long)sc->sc_iot, (unsigned long)sc->sc_memt, 3179 (unsigned long)bst)); 3180 } 3181 3182 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 3183 printf("%s: pccbb_open_win: %s winlist insert failed\n", 3184 sc->sc_dev.dv_xname, 3185 (head == &sc->sc_memwindow) ? "mem" : "io"); 3186 } 3187 pccbb_winset(align, sc, bst); 3188 3189 return 0; 3190 } 3191 3192 static int 3193 pccbb_close_win(sc, bst, bsh, size) 3194 struct pccbb_softc *sc; 3195 bus_space_tag_t bst; 3196 bus_space_handle_t bsh; 3197 bus_size_t size; 3198 { 3199 struct pccbb_win_chain_head *head; 3200 bus_addr_t align; 3201 3202 head = &sc->sc_iowindow; 3203 align = 0x04; 3204 if (sc->sc_memt == bst) { 3205 head = &sc->sc_memwindow; 3206 align = 0x1000; 3207 } 3208 3209 if (pccbb_winlist_delete(head, bsh, size)) { 3210 printf("%s: pccbb_close_win: %s winlist delete failed\n", 3211 sc->sc_dev.dv_xname, 3212 (head == &sc->sc_memwindow) ? "mem" : "io"); 3213 } 3214 pccbb_winset(align, sc, bst); 3215 3216 return 0; 3217 } 3218 3219 static int 3220 pccbb_winlist_insert(head, start, size, bsh, flags) 3221 struct pccbb_win_chain_head *head; 3222 bus_addr_t start; 3223 bus_size_t size; 3224 bus_space_handle_t bsh; 3225 int flags; 3226 { 3227 struct pccbb_win_chain *chainp, *elem; 3228 3229 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 3230 M_NOWAIT)) == NULL) 3231 return (1); /* fail */ 3232 3233 elem->wc_start = start; 3234 elem->wc_end = start + (size - 1); 3235 elem->wc_handle = bsh; 3236 elem->wc_flags = flags; 3237 3238 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3239 chainp = TAILQ_NEXT(chainp, wc_list)) { 3240 if (chainp->wc_end < start) 3241 continue; 3242 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 3243 return (0); 3244 } 3245 3246 TAILQ_INSERT_TAIL(head, elem, wc_list); 3247 return (0); 3248 } 3249 3250 static int 3251 pccbb_winlist_delete(head, bsh, size) 3252 struct pccbb_win_chain_head *head; 3253 bus_space_handle_t bsh; 3254 bus_size_t size; 3255 { 3256 struct pccbb_win_chain *chainp; 3257 3258 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3259 chainp = TAILQ_NEXT(chainp, wc_list)) { 3260 if (memcmp(&chainp->wc_handle, &bsh, sizeof(bsh))) 3261 continue; 3262 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 3263 printf("pccbb_winlist_delete: window 0x%lx size " 3264 "inconsistent: 0x%lx, 0x%lx\n", 3265 (unsigned long)chainp->wc_start, 3266 (unsigned long)(chainp->wc_end - chainp->wc_start), 3267 (unsigned long)(size - 1)); 3268 return 1; 3269 } 3270 3271 TAILQ_REMOVE(head, chainp, wc_list); 3272 free(chainp, M_DEVBUF); 3273 3274 return 0; 3275 } 3276 3277 return 1; /* fail: no candidate to remove */ 3278 } 3279 3280 static void 3281 pccbb_winset(align, sc, bst) 3282 bus_addr_t align; 3283 struct pccbb_softc *sc; 3284 bus_space_tag_t bst; 3285 { 3286 pci_chipset_tag_t pc; 3287 pcitag_t tag; 3288 bus_addr_t mask = ~(align - 1); 3289 struct { 3290 cardbusreg_t win_start; 3291 cardbusreg_t win_limit; 3292 int win_flags; 3293 } win[2]; 3294 struct pccbb_win_chain *chainp; 3295 int offs; 3296 3297 win[0].win_start = win[1].win_start = 0xffffffff; 3298 win[0].win_limit = win[1].win_limit = 0; 3299 win[0].win_flags = win[1].win_flags = 0; 3300 3301 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3302 offs = 0x2c; 3303 if (sc->sc_memt == bst) { 3304 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3305 offs = 0x1c; 3306 } 3307 3308 if (chainp != NULL) { 3309 win[0].win_start = chainp->wc_start & mask; 3310 win[0].win_limit = chainp->wc_end & mask; 3311 win[0].win_flags = chainp->wc_flags; 3312 chainp = TAILQ_NEXT(chainp, wc_list); 3313 } 3314 3315 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3316 if (win[1].win_start == 0xffffffff) { 3317 /* window 1 is not used */ 3318 if ((win[0].win_flags == chainp->wc_flags) && 3319 (win[0].win_limit + align >= 3320 (chainp->wc_start & mask))) { 3321 /* concatenate */ 3322 win[0].win_limit = chainp->wc_end & mask; 3323 } else { 3324 /* make new window */ 3325 win[1].win_start = chainp->wc_start & mask; 3326 win[1].win_limit = chainp->wc_end & mask; 3327 win[1].win_flags = chainp->wc_flags; 3328 } 3329 continue; 3330 } 3331 3332 /* Both windows are engaged. */ 3333 if (win[0].win_flags == win[1].win_flags) { 3334 /* same flags */ 3335 if (win[0].win_flags == chainp->wc_flags) { 3336 if (win[1].win_start - (win[0].win_limit + 3337 align) < 3338 (chainp->wc_start & mask) - 3339 ((chainp->wc_end & mask) + align)) { 3340 /* 3341 * merge window 0 and 1, and set win1 3342 * to chainp 3343 */ 3344 win[0].win_limit = win[1].win_limit; 3345 win[1].win_start = 3346 chainp->wc_start & mask; 3347 win[1].win_limit = 3348 chainp->wc_end & mask; 3349 } else { 3350 win[1].win_limit = 3351 chainp->wc_end & mask; 3352 } 3353 } else { 3354 /* different flags */ 3355 3356 /* concatenate win0 and win1 */ 3357 win[0].win_limit = win[1].win_limit; 3358 /* allocate win[1] to new space */ 3359 win[1].win_start = chainp->wc_start & mask; 3360 win[1].win_limit = chainp->wc_end & mask; 3361 win[1].win_flags = chainp->wc_flags; 3362 } 3363 } else { 3364 /* the flags of win[0] and win[1] is different */ 3365 if (win[0].win_flags == chainp->wc_flags) { 3366 win[0].win_limit = chainp->wc_end & mask; 3367 /* 3368 * XXX this creates overlapping windows, so 3369 * what should the poor bridge do if one is 3370 * cachable, and the other is not? 3371 */ 3372 printf("%s: overlapping windows\n", 3373 sc->sc_dev.dv_xname); 3374 } else { 3375 win[1].win_limit = chainp->wc_end & mask; 3376 } 3377 } 3378 } 3379 3380 pc = sc->sc_pc; 3381 tag = sc->sc_tag; 3382 pci_conf_write(pc, tag, offs, win[0].win_start); 3383 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3384 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3385 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3386 DPRINTF(("--pccbb_winset: win0 [0x%lx, 0x%lx), win1 [0x%lx, 0x%lx)\n", 3387 (unsigned long)pci_conf_read(pc, tag, offs), 3388 (unsigned long)pci_conf_read(pc, tag, offs + 4) + align, 3389 (unsigned long)pci_conf_read(pc, tag, offs + 8), 3390 (unsigned long)pci_conf_read(pc, tag, offs + 12) + align)); 3391 3392 if (bst == sc->sc_memt) { 3393 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3394 3395 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 3396 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 3397 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3398 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 3399 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3400 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3401 } 3402 } 3403 3404 #endif /* rbus */ 3405 3406 static void 3407 pccbb_powerhook(why, arg) 3408 int why; 3409 void *arg; 3410 { 3411 struct pccbb_softc *sc = arg; 3412 pcireg_t reg; 3413 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3414 bus_space_handle_t base_memh = sc->sc_base_memh; 3415 3416 DPRINTF(("%s: power: why %d\n", sc->sc_dev.dv_xname, why)); 3417 3418 if (why == PWR_SUSPEND || why == PWR_STANDBY) { 3419 DPRINTF(("%s: power: why %d stopping intr\n", 3420 sc->sc_dev.dv_xname, why)); 3421 if (sc->sc_pil_intr_enable) { 3422 (void)pccbbintr_function(sc); 3423 } 3424 sc->sc_pil_intr_enable = 0; 3425 3426 pci_conf_capture(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf); 3427 3428 if (sc->sc_chipset == CB_RX5C47X) 3429 sc->sc_ricoh_misc_ctrl = pci_conf_read(sc->sc_pc, 3430 sc->sc_tag, 3431 RICOH_PCI_MISC_CTRL); 3432 3433 /* ToDo: deactivate or suspend child devices */ 3434 } 3435 3436 if (why == PWR_RESUME) { 3437 if (sc->sc_pwrmgt_offs != 0) { 3438 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, 3439 sc->sc_pwrmgt_offs + 4); 3440 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 3441 reg & 0x100) { 3442 /* powrstate != D0 */ 3443 3444 printf("%s going back to D0 mode\n", 3445 sc->sc_dev.dv_xname); 3446 reg &= ~PCI_PMCSR_STATE_MASK; 3447 reg |= PCI_PMCSR_STATE_D0; 3448 reg &= ~(0x100 /* PCI_PMCSR_PME_EN */); 3449 pci_conf_write(sc->sc_pc, sc->sc_tag, 3450 sc->sc_pwrmgt_offs + 4, reg); 3451 3452 pci_conf_write(sc->sc_pc, sc->sc_tag, 3453 PCI_SOCKBASE, sc->sc_sockbase); 3454 pci_conf_write(sc->sc_pc, sc->sc_tag, 3455 PCI_BUSNUM, sc->sc_busnum); 3456 pccbb_chipinit(sc); 3457 /* setup memory and io space window for CB */ 3458 pccbb_winset(0x1000, sc, sc->sc_memt); 3459 pccbb_winset(0x04, sc, sc->sc_iot); 3460 goto norestore; 3461 } 3462 } 3463 3464 norestore: 3465 pci_conf_restore(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf); 3466 if (sc->sc_chipset == CB_RX5C47X) { 3467 pci_conf_write(sc->sc_pc, sc->sc_tag, 3468 RICOH_PCI_MISC_CTRL, sc->sc_ricoh_misc_ctrl); 3469 } 3470 3471 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_SOCKBASE) == 0) 3472 /* BIOS did not recover this register */ 3473 pci_conf_write (sc->sc_pc, sc->sc_tag, 3474 PCI_SOCKBASE, sc->sc_sockbase); 3475 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_BUSNUM) == 0) 3476 /* BIOS did not recover this register */ 3477 pci_conf_write (sc->sc_pc, sc->sc_tag, 3478 PCI_BUSNUM, sc->sc_busnum); 3479 /* CSC Interrupt: Card detect interrupt on */ 3480 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3481 /* Card detect intr is turned on. */ 3482 reg |= CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; 3483 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3484 /* reset interrupt */ 3485 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3486 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3487 3488 /* 3489 * check for card insertion or removal during suspend period. 3490 * XXX: the code can't cope with card swap (remove then 3491 * insert). how can we detect such situation? 3492 */ 3493 (void)pccbbintr(sc); 3494 3495 sc->sc_pil_intr_enable = 1; 3496 DPRINTF(("%s: power: RESUME enabling intr\n", 3497 sc->sc_dev.dv_xname)); 3498 3499 /* ToDo: activate or wakeup child devices */ 3500 } 3501 } 3502
Indexes created Fri Sep 26 20:09:58 GMT 2025