pccbb.c revision 1.134
1 /* $NetBSD: pccbb.c,v 1.134 2006/09/24 03:53:09 jmcneill Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: pccbb.c,v 1.134 2006/09/24 03:53:09 jmcneill Exp $"); 35 36 /* 37 #define CBB_DEBUG 38 #define SHOW_REGS 39 */ 40 41 /* 42 * BROKEN! 43 #define PCCBB_PCMCIA_POLL 44 #define CB_PCMCIA_POLL 45 #define CB_PCMCIA_POLL_ONLY 46 #define LEVEL2 47 */ 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/kernel.h> 52 #include <sys/errno.h> 53 #include <sys/ioctl.h> 54 #include <sys/reboot.h> /* for bootverbose */ 55 #include <sys/syslog.h> 56 #include <sys/device.h> 57 #include <sys/malloc.h> 58 #include <sys/proc.h> 59 60 #include <machine/intr.h> 61 #include <machine/bus.h> 62 63 #include <dev/pci/pcivar.h> 64 #include <dev/pci/pcireg.h> 65 #include <dev/pci/pcidevs.h> 66 67 #include <dev/pci/pccbbreg.h> 68 69 #include <dev/cardbus/cardslotvar.h> 70 71 #include <dev/cardbus/cardbusvar.h> 72 73 #include <dev/pcmcia/pcmciareg.h> 74 #include <dev/pcmcia/pcmciavar.h> 75 76 #include <dev/ic/i82365reg.h> 77 #include <dev/ic/i82365var.h> 78 #include <dev/pci/pccbbvar.h> 79 80 #include "locators.h" 81 82 #if defined(__i386__) 83 #include "ioapic.h" 84 #include "acpi.h" 85 #endif 86 87 #ifndef __NetBSD_Version__ 88 struct cfdriver cbb_cd = { 89 NULL, "cbb", DV_DULL 90 }; 91 #endif 92 93 #ifdef CBB_DEBUG 94 #define DPRINTF(x) printf x 95 #define STATIC 96 #else 97 #define DPRINTF(x) 98 #define STATIC static 99 #endif 100 101 /* 102 * DELAY_MS() is a wait millisecond. It shall use instead of delay() 103 * if you want to wait more than 1 ms. 104 */ 105 #define DELAY_MS(time, param) \ 106 do { \ 107 if (cold == 0) { \ 108 int xtick = (hz*(time))/1000; \ 109 \ 110 if (xtick <= 1) { \ 111 xtick = 2; \ 112 } \ 113 tsleep((void *)(param), PWAIT, "pccbb", xtick); \ 114 } else { \ 115 delay((time)*1000); \ 116 } \ 117 } while (/*CONSTCOND*/0) 118 119 int pcicbbmatch(struct device *, struct cfdata *, void *); 120 void pccbbattach(struct device *, struct device *, void *); 121 int pccbbintr(void *); 122 static void pci113x_insert(void *); 123 static int pccbbintr_function(struct pccbb_softc *); 124 125 static int pccbb_detect_card(struct pccbb_softc *); 126 127 static void pccbb_pcmcia_write(struct pcic_handle *, int, u_int8_t); 128 static u_int8_t pccbb_pcmcia_read(struct pcic_handle *, int); 129 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 130 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 131 132 STATIC int cb_reset(struct pccbb_softc *); 133 STATIC int cb_detect_voltage(struct pccbb_softc *); 134 STATIC int cbbprint(void *, const char *); 135 136 static int cb_chipset(u_int32_t, int *); 137 STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *, 138 struct pcmciabus_attach_args *); 139 #if 0 140 STATIC void pccbb_pcmcia_attach_card(struct pcic_handle *); 141 STATIC void pccbb_pcmcia_detach_card(struct pcic_handle *, int); 142 STATIC void pccbb_pcmcia_deactivate_card(struct pcic_handle *); 143 #endif 144 145 STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int); 146 STATIC int pccbb_power(cardbus_chipset_tag_t, int); 147 STATIC int pccbb_cardenable(struct pccbb_softc * sc, int function); 148 #if !rbus 149 static int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 150 static int pccbb_io_close(cardbus_chipset_tag_t, int); 151 static int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 152 static int pccbb_mem_close(cardbus_chipset_tag_t, int); 153 #endif /* !rbus */ 154 static void *pccbb_intr_establish(struct pccbb_softc *, int irq, 155 int level, int (*ih) (void *), void *sc); 156 static void pccbb_intr_disestablish(struct pccbb_softc *, void *ih); 157 158 static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t, int irq, 159 int level, int (*ih) (void *), void *sc); 160 static void pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih); 161 162 static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t, int, int); 163 static void pccbb_free_tag(cardbus_chipset_tag_t, cardbustag_t); 164 static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t, cardbustag_t, int); 165 static void pccbb_conf_write(cardbus_chipset_tag_t, cardbustag_t, int, 166 cardbusreg_t); 167 static void pccbb_chipinit(struct pccbb_softc *); 168 169 STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 170 struct pcmcia_mem_handle *); 171 STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t, 172 struct pcmcia_mem_handle *); 173 STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 174 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *); 175 STATIC void pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t, int); 176 STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 177 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 178 STATIC void pccbb_pcmcia_io_free(pcmcia_chipset_handle_t, 179 struct pcmcia_io_handle *); 180 STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 181 bus_size_t, struct pcmcia_io_handle *, int *); 182 STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t, int); 183 STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t, 184 struct pcmcia_function *, int, int (*)(void *), void *); 185 STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t, void *); 186 STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t); 187 STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t); 188 STATIC void pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t, int); 189 STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch); 190 191 static int pccbb_pcmcia_wait_ready(struct pcic_handle *); 192 static void pccbb_pcmcia_delay(struct pcic_handle *, int, const char *); 193 194 static void pccbb_pcmcia_do_io_map(struct pcic_handle *, int); 195 static void pccbb_pcmcia_do_mem_map(struct pcic_handle *, int); 196 static void pccbb_powerhook(int, void *); 197 198 /* bus-space allocation and deallocation functions */ 199 #if rbus 200 201 static int pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t, rbus_tag_t, 202 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 203 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp); 204 static int pccbb_rbus_cb_space_free(cardbus_chipset_tag_t, rbus_tag_t, 205 bus_space_handle_t, bus_size_t); 206 207 #endif /* rbus */ 208 209 #if rbus 210 211 static int pccbb_open_win(struct pccbb_softc *, bus_space_tag_t, 212 bus_addr_t, bus_size_t, bus_space_handle_t, int flags); 213 static int pccbb_close_win(struct pccbb_softc *, bus_space_tag_t, 214 bus_space_handle_t, bus_size_t); 215 static int pccbb_winlist_insert(struct pccbb_win_chain_head *, bus_addr_t, 216 bus_size_t, bus_space_handle_t, int); 217 static int pccbb_winlist_delete(struct pccbb_win_chain_head *, 218 bus_space_handle_t, bus_size_t); 219 static void pccbb_winset(bus_addr_t align, struct pccbb_softc *, 220 bus_space_tag_t); 221 void pccbb_winlist_show(struct pccbb_win_chain *); 222 223 #endif /* rbus */ 224 225 /* for config_defer */ 226 static void pccbb_pci_callback(struct device *); 227 228 #if defined SHOW_REGS 229 static void cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, 230 bus_space_tag_t memt, bus_space_handle_t memh); 231 #endif 232 233 CFATTACH_DECL(cbb_pci, sizeof(struct pccbb_softc), 234 pcicbbmatch, pccbbattach, NULL, NULL); 235 236 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 237 pccbb_pcmcia_mem_alloc, 238 pccbb_pcmcia_mem_free, 239 pccbb_pcmcia_mem_map, 240 pccbb_pcmcia_mem_unmap, 241 pccbb_pcmcia_io_alloc, 242 pccbb_pcmcia_io_free, 243 pccbb_pcmcia_io_map, 244 pccbb_pcmcia_io_unmap, 245 pccbb_pcmcia_intr_establish, 246 pccbb_pcmcia_intr_disestablish, 247 pccbb_pcmcia_socket_enable, 248 pccbb_pcmcia_socket_disable, 249 pccbb_pcmcia_socket_settype, 250 pccbb_pcmcia_card_detect 251 }; 252 253 #if rbus 254 static struct cardbus_functions pccbb_funcs = { 255 pccbb_rbus_cb_space_alloc, 256 pccbb_rbus_cb_space_free, 257 pccbb_cb_intr_establish, 258 pccbb_cb_intr_disestablish, 259 pccbb_ctrl, 260 pccbb_power, 261 pccbb_make_tag, 262 pccbb_free_tag, 263 pccbb_conf_read, 264 pccbb_conf_write, 265 }; 266 #else 267 static struct cardbus_functions pccbb_funcs = { 268 pccbb_ctrl, 269 pccbb_power, 270 pccbb_mem_open, 271 pccbb_mem_close, 272 pccbb_io_open, 273 pccbb_io_close, 274 pccbb_cb_intr_establish, 275 pccbb_cb_intr_disestablish, 276 pccbb_make_tag, 277 pccbb_conf_read, 278 pccbb_conf_write, 279 }; 280 #endif 281 282 int 283 pcicbbmatch(parent, match, aux) 284 struct device *parent; 285 struct cfdata *match; 286 void *aux; 287 { 288 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 289 290 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 291 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 292 PCI_INTERFACE(pa->pa_class) == 0) { 293 return 1; 294 } 295 296 return 0; 297 } 298 299 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 300 | ((prod) << PCI_PRODUCT_SHIFT)) 301 302 const struct yenta_chipinfo { 303 pcireg_t yc_id; /* vendor tag | product tag */ 304 int yc_chiptype; 305 int yc_flags; 306 } yc_chipsets[] = { 307 /* Texas Instruments chips */ 308 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 309 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 310 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 311 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 312 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI125X, 313 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 314 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 315 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 316 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 317 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 318 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 319 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 320 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI125X, 321 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 322 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI125X, 323 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 324 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 325 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 326 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 327 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 328 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 329 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 330 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI125X, 331 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 332 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 333 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 334 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1520), CB_TI12XX, 335 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 336 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4410YENTA), CB_TI12XX, 337 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 338 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4520YENTA), CB_TI12XX, 339 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 340 341 /* Ricoh chips */ 342 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 343 PCCBB_PCMCIA_MEM_32}, 344 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 345 PCCBB_PCMCIA_MEM_32}, 346 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 347 PCCBB_PCMCIA_MEM_32}, 348 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 349 PCCBB_PCMCIA_MEM_32}, 350 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 351 PCCBB_PCMCIA_MEM_32}, 352 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 353 PCCBB_PCMCIA_MEM_32}, 354 355 /* Toshiba products */ 356 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 357 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 358 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 359 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 360 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 361 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 362 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 363 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 364 365 /* Cirrus Logic products */ 366 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 367 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 368 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 369 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 370 371 /* sentinel, or Generic chip */ 372 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 373 }; 374 375 static int 376 cb_chipset(pci_id, flagp) 377 u_int32_t pci_id; 378 int *flagp; 379 { 380 const struct yenta_chipinfo *yc; 381 382 /* Loop over except the last default entry. */ 383 for (yc = yc_chipsets; yc < yc_chipsets + 384 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 385 if (pci_id == yc->yc_id) 386 break; 387 388 if (flagp != NULL) 389 *flagp = yc->yc_flags; 390 391 return (yc->yc_chiptype); 392 } 393 394 static void 395 pccbb_shutdown(void *arg) 396 { 397 struct pccbb_softc *sc = arg; 398 pcireg_t command; 399 400 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 401 402 /* 403 * turn off power 404 * 405 * XXX - do not turn off power if chipset is TI 113X because 406 * only TI 1130 with PowerMac 2400 hangs in pccbb_power(). 407 */ 408 if (sc->sc_chipset != CB_TI113X) { 409 pccbb_power((cardbus_chipset_tag_t)sc, 410 CARDBUS_VCC_0V | CARDBUS_VPP_0V); 411 } 412 413 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 414 0); 415 416 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 417 418 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 419 PCI_COMMAND_MASTER_ENABLE); 420 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 421 422 } 423 424 void 425 pccbbattach(parent, self, aux) 426 struct device *parent; 427 struct device *self; 428 void *aux; 429 { 430 struct pccbb_softc *sc = (void *)self; 431 struct pci_attach_args *pa = aux; 432 pci_chipset_tag_t pc = pa->pa_pc; 433 pcireg_t busreg, reg, sock_base; 434 bus_addr_t sockbase; 435 char devinfo[256]; 436 int flags; 437 int pwrmgt_offs; 438 439 #ifdef __HAVE_PCCBB_ATTACH_HOOK 440 pccbb_attach_hook(parent, self, pa); 441 #endif 442 443 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 444 445 pci_devinfo(pa->pa_id, 0, 0, devinfo, sizeof(devinfo)); 446 printf(": %s (rev. 0x%02x)", devinfo, PCI_REVISION(pa->pa_class)); 447 DPRINTF((" (chipflags %x)", flags)); 448 printf("\n"); 449 450 TAILQ_INIT(&sc->sc_memwindow); 451 TAILQ_INIT(&sc->sc_iowindow); 452 453 #if rbus 454 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 455 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 456 457 #if 0 458 printf("pa->pa_memt: %08x vs rbus_mem->rb_bt: %08x\n", 459 pa->pa_memt, sc->sc_rbus_memt->rb_bt); 460 #endif 461 #endif /* rbus */ 462 463 sc->sc_flags &= ~CBB_MEMHMAPPED; 464 465 /* power management: set D0 state */ 466 sc->sc_pwrmgt_offs = 0; 467 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, 468 &pwrmgt_offs, 0)) { 469 reg = pci_conf_read(pc, pa->pa_tag, pwrmgt_offs + PCI_PMCSR); 470 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 471 reg & 0x100 /* PCI_PMCSR_PME_EN */) { 472 reg &= ~PCI_PMCSR_STATE_MASK; 473 reg |= PCI_PMCSR_STATE_D0; 474 reg &= ~(0x100 /* PCI_PMCSR_PME_EN */); 475 pci_conf_write(pc, pa->pa_tag, 476 pwrmgt_offs + PCI_PMCSR, reg); 477 } 478 479 sc->sc_pwrmgt_offs = pwrmgt_offs; 480 } 481 482 /* 483 * MAP socket registers and ExCA registers on memory-space 484 * When no valid address is set on socket base registers (on pci 485 * config space), get it not polite way. 486 */ 487 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 488 489 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 490 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 491 /* The address must be valid. */ 492 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 493 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL)) { 494 printf("%s: can't map socket base address 0x%lx\n", 495 sc->sc_dev.dv_xname, (unsigned long)sock_base); 496 /* 497 * I think it's funny: socket base registers must be 498 * mapped on memory space, but ... 499 */ 500 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 501 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 502 NULL)) { 503 printf("%s: can't map socket base address" 504 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 505 (unsigned long)sockbase); 506 /* give up... allocate reg space via rbus. */ 507 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 508 } else 509 sc->sc_flags |= CBB_MEMHMAPPED; 510 } else { 511 DPRINTF(("%s: socket base address 0x%lx\n", 512 sc->sc_dev.dv_xname, (unsigned long)sockbase)); 513 sc->sc_flags |= CBB_MEMHMAPPED; 514 } 515 } 516 517 sc->sc_mem_start = 0; /* XXX */ 518 sc->sc_mem_end = 0xffffffff; /* XXX */ 519 520 /* 521 * When interrupt isn't routed correctly, give up probing cbb and do 522 * not kill pcic-compatible port. 523 * 524 * However, if we are using an ioapic, avoid this check -- pa_intrline 525 * may well be zero, with the interrupt routed through the apic. 526 */ 527 528 #if NIOAPIC == 0 && NACPI == 0 529 if ((0 == pa->pa_intrline) || (255 == pa->pa_intrline)) { 530 printf("%s: NOT USED because of unconfigured interrupt\n", 531 sc->sc_dev.dv_xname); 532 return; 533 } 534 #endif 535 536 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 537 538 /* pccbb_machdep.c end */ 539 540 #if defined CBB_DEBUG 541 { 542 static const char *intrname[] = { "NON", "A", "B", "C", "D" }; 543 printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname, 544 intrname[pa->pa_intrpin], pa->pa_intrline); 545 } 546 #endif 547 548 /* setup softc */ 549 sc->sc_pc = pc; 550 sc->sc_iot = pa->pa_iot; 551 sc->sc_memt = pa->pa_memt; 552 sc->sc_dmat = pa->pa_dmat; 553 sc->sc_tag = pa->pa_tag; 554 sc->sc_function = pa->pa_function; 555 sc->sc_sockbase = sock_base; 556 sc->sc_busnum = busreg; 557 558 memcpy(&sc->sc_pa, pa, sizeof(*pa)); 559 560 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 561 562 shutdownhook_establish(pccbb_shutdown, sc); 563 564 /* Disable legacy register mapping. */ 565 switch (sc->sc_chipset) { 566 case CB_RX5C46X: /* fallthrough */ 567 #if 0 568 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 569 case CB_RX5C47X: 570 #endif 571 /* 572 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 573 * cannot be disabled by substituting 0 into PCI_LEGACY 574 * register. Ricoh CardBus bridges have special bits on Bridge 575 * control reg (addr 0x3e on PCI config space). 576 */ 577 reg = pci_conf_read(pc, pa->pa_tag, PCI_BCR_INTR); 578 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 579 pci_conf_write(pc, pa->pa_tag, PCI_BCR_INTR, reg); 580 break; 581 582 default: 583 /* XXX I don't know proper way to kill legacy I/O. */ 584 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 585 break; 586 } 587 588 config_defer(self, pccbb_pci_callback); 589 } 590 591 592 593 594 /* 595 * static void pccbb_pci_callback(struct device *self) 596 * 597 * The actual attach routine: get memory space for YENTA register 598 * space, setup YENTA register and route interrupt. 599 * 600 * This function should be deferred because this device may obtain 601 * memory space dynamically. This function must avoid obtaining 602 * memory area which has already kept for another device. 603 */ 604 static void 605 pccbb_pci_callback(self) 606 struct device *self; 607 { 608 struct pccbb_softc *sc = (void *)self; 609 pci_chipset_tag_t pc = sc->sc_pc; 610 pci_intr_handle_t ih; 611 const char *intrstr = NULL; 612 bus_addr_t sockbase; 613 struct cbslot_attach_args cba; 614 struct pcmciabus_attach_args paa; 615 struct cardslot_attach_args caa; 616 struct cardslot_softc *csc; 617 618 if (!(sc->sc_flags & CBB_MEMHMAPPED)) { 619 /* The socket registers aren't mapped correctly. */ 620 #if rbus 621 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 622 (sc->sc_chipset == CB_RX5C47X 623 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 624 0, &sockbase, &sc->sc_base_memh)) { 625 return; 626 } 627 sc->sc_base_memt = sc->sc_memt; 628 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 629 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 630 sc->sc_dev.dv_xname, (unsigned long)sockbase, 631 (unsigned long)pci_conf_read(pc, sc->sc_tag, 632 PCI_SOCKBASE))); 633 #else 634 sc->sc_base_memt = sc->sc_memt; 635 #if !defined CBB_PCI_BASE 636 #define CBB_PCI_BASE 0x20000000 637 #endif 638 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 639 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 640 /* cannot allocate memory space */ 641 return; 642 } 643 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 644 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 645 sc->sc_dev.dv_xname, (unsigned long)sock_base, 646 (unsigned long)pci_conf_read(pc, 647 sc->sc_tag, PCI_SOCKBASE))); 648 sc->sc_sockbase = sockbase; 649 #endif 650 sc->sc_flags |= CBB_MEMHMAPPED; 651 } 652 653 /* bus bridge initialization */ 654 pccbb_chipinit(sc); 655 656 /* clear data structure for child device interrupt handlers */ 657 LIST_INIT(&sc->sc_pil); 658 sc->sc_pil_intr_enable = 1; 659 660 /* Map and establish the interrupt. */ 661 if (pci_intr_map(&sc->sc_pa, &ih)) { 662 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 663 return; 664 } 665 intrstr = pci_intr_string(pc, ih); 666 667 /* 668 * XXX pccbbintr should be called under the priority lower 669 * than any other hard interupts. 670 */ 671 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 672 673 if (sc->sc_ih == NULL) { 674 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 675 if (intrstr != NULL) { 676 printf(" at %s", intrstr); 677 } 678 printf("\n"); 679 return; 680 } 681 682 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 683 powerhook_establish(sc->sc_dev.dv_xname, pccbb_powerhook, sc); 684 685 { 686 u_int32_t sockstat; 687 688 sockstat = bus_space_read_4(sc->sc_base_memt, 689 sc->sc_base_memh, CB_SOCKET_STAT); 690 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 691 sc->sc_flags |= CBB_CARDEXIST; 692 } 693 } 694 695 /* 696 * attach cardbus 697 */ 698 { 699 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 700 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 701 702 /* initialize cbslot_attach */ 703 cba.cba_busname = "cardbus"; 704 cba.cba_iot = sc->sc_iot; 705 cba.cba_memt = sc->sc_memt; 706 cba.cba_dmat = sc->sc_dmat; 707 cba.cba_bus = (busreg >> 8) & 0x0ff; 708 cba.cba_cc = (void *)sc; 709 cba.cba_cf = &pccbb_funcs; 710 cba.cba_intrline = sc->sc_pa.pa_intrline; 711 712 #if rbus 713 cba.cba_rbus_iot = sc->sc_rbus_iot; 714 cba.cba_rbus_memt = sc->sc_rbus_memt; 715 #endif 716 717 cba.cba_cacheline = PCI_CACHELINE(bhlc); 718 cba.cba_lattimer = PCI_CB_LATENCY(busreg); 719 720 if (bootverbose) { 721 printf("%s: cacheline 0x%x lattimer 0x%x\n", 722 sc->sc_dev.dv_xname, cba.cba_cacheline, 723 cba.cba_lattimer); 724 printf("%s: bhlc 0x%x lscp 0x%x\n", 725 sc->sc_dev.dv_xname, bhlc, busreg); 726 } 727 #if defined SHOW_REGS 728 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 729 sc->sc_base_memh); 730 #endif 731 } 732 733 pccbb_pcmcia_attach_setup(sc, &paa); 734 caa.caa_cb_attach = NULL; 735 if (cba.cba_bus == 0) 736 printf("%s: secondary bus number uninitialized; try PCI_BUS_FIXUP\n", sc->sc_dev.dv_xname); 737 else 738 caa.caa_cb_attach = &cba; 739 caa.caa_16_attach = &paa; 740 caa.caa_ph = &sc->sc_pcmcia_h; 741 742 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 743 DPRINTF(("pccbbattach: found cardslot\n")); 744 sc->sc_csc = csc; 745 } 746 747 return; 748 } 749 750 751 752 753 754 /* 755 * static void pccbb_chipinit(struct pccbb_softc *sc) 756 * 757 * This function initialize YENTA chip registers listed below: 758 * 1) PCI command reg, 759 * 2) PCI and CardBus latency timer, 760 * 3) route PCI interrupt, 761 * 4) close all memory and io windows. 762 * 5) turn off bus power. 763 * 6) card detect and power cycle interrupts on. 764 * 7) clear interrupt 765 */ 766 static void 767 pccbb_chipinit(sc) 768 struct pccbb_softc *sc; 769 { 770 pci_chipset_tag_t pc = sc->sc_pc; 771 pcitag_t tag = sc->sc_tag; 772 bus_space_tag_t bmt = sc->sc_base_memt; 773 bus_space_handle_t bmh = sc->sc_base_memh; 774 pcireg_t reg; 775 776 /* 777 * Set PCI command reg. 778 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 779 */ 780 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 781 /* I believe it is harmless. */ 782 reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 783 PCI_COMMAND_MASTER_ENABLE); 784 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg); 785 786 /* 787 * Set CardBus latency timer. 788 */ 789 reg = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 790 if (PCI_CB_LATENCY(reg) < 0x20) { 791 reg &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 792 reg |= (0x20 << PCI_CB_LATENCY_SHIFT); 793 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, reg); 794 } 795 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 796 PCI_CB_LATENCY(reg), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 797 798 /* 799 * Set PCI latency timer. 800 */ 801 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 802 if (PCI_LATTIMER(reg) < 0x10) { 803 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 804 reg |= (0x10 << PCI_LATTIMER_SHIFT); 805 pci_conf_write(pc, tag, PCI_BHLC_REG, reg); 806 } 807 DPRINTF(("PCI latency timer 0x%x (%x)\n", 808 PCI_LATTIMER(reg), pci_conf_read(pc, tag, PCI_BHLC_REG))); 809 810 811 /* Route functional interrupts to PCI. */ 812 reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 813 reg |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 814 reg |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 815 reg |= CB_BCR_RESET_ENABLE; /* assert reset */ 816 pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 817 818 switch (sc->sc_chipset) { 819 case CB_TI113X: 820 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 821 /* This bit is shared, but may read as 0 on some chips, so set 822 it explicitly on both functions. */ 823 reg |= PCI113X_CBCTRL_PCI_IRQ_ENA; 824 /* CSC intr enable */ 825 reg |= PCI113X_CBCTRL_PCI_CSC; 826 /* functional intr prohibit | prohibit ISA routing */ 827 reg &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 828 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 829 break; 830 831 case CB_TI12XX: 832 /* 833 * Some TI 12xx (and [14][45]xx) based pci cards 834 * sometimes have issues with the MFUNC register not 835 * being initialized due to a bad EEPROM on board. 836 * Laptops that this matters on have this register 837 * properly initialized. 838 * 839 * The TI125X parts have a different register. 840 */ 841 reg = pci_conf_read(pc, tag, PCI12XX_MFUNC); 842 if (reg == 0) { 843 reg &= ~PCI12XX_MFUNC_PIN0; 844 reg |= PCI12XX_MFUNC_PIN0_INTA; 845 if ((pci_conf_read(pc, tag, PCI_SYSCTRL) & 846 PCI12XX_SYSCTRL_INTRTIE) == 0) { 847 reg &= ~PCI12XX_MFUNC_PIN1; 848 reg |= PCI12XX_MFUNC_PIN1_INTB; 849 } 850 pci_conf_write(pc, tag, PCI12XX_MFUNC, reg); 851 } 852 /* fallthrough */ 853 854 case CB_TI125X: 855 /* 856 * Disable zoom video. Some machines initialize this 857 * improperly and experience has shown that this helps 858 * prevent strange behavior. 859 */ 860 pci_conf_write(pc, tag, PCI12XX_MMCTRL, 0); 861 862 reg = pci_conf_read(pc, tag, PCI_SYSCTRL); 863 reg |= PCI12XX_SYSCTRL_VCCPROT; 864 pci_conf_write(pc, tag, PCI_SYSCTRL, reg); 865 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 866 reg |= PCI12XX_CBCTRL_CSC; 867 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 868 break; 869 870 case CB_TOPIC95B: 871 reg = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 872 reg |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 873 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, reg); 874 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 875 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 876 sc->sc_dev.dv_xname, reg)); 877 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 878 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 879 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 880 DPRINTF(("0x%x\n", reg)); 881 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 882 break; 883 884 case CB_TOPIC97: 885 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 886 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 887 sc->sc_dev.dv_xname, reg)); 888 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 889 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 890 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 891 reg |= TOPIC97_SLOT_CTRL_PCIINT; 892 reg &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 893 DPRINTF(("0x%x\n", reg)); 894 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 895 /* make sure to assert LV card support bits */ 896 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 897 0x800 + 0x3e, 898 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 899 0x800 + 0x3e) | 0x03); 900 break; 901 } 902 903 /* Close all memory and I/O windows. */ 904 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 905 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 906 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 907 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 908 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 909 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 910 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 911 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 912 913 /* reset 16-bit pcmcia bus */ 914 bus_space_write_1(bmt, bmh, 0x800 + PCIC_INTR, 915 bus_space_read_1(bmt, bmh, 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 916 917 /* turn off power */ 918 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 919 920 /* CSC Interrupt: Card detect and power cycle interrupts on */ 921 reg = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 922 reg |= CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; 923 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, reg); 924 /* reset interrupt */ 925 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 926 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 927 } 928 929 930 931 932 /* 933 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 934 * struct pcmciabus_attach_args *paa) 935 * 936 * This function attaches 16-bit PCcard bus. 937 */ 938 STATIC void 939 pccbb_pcmcia_attach_setup(sc, paa) 940 struct pccbb_softc *sc; 941 struct pcmciabus_attach_args *paa; 942 { 943 struct pcic_handle *ph = &sc->sc_pcmcia_h; 944 #if rbus 945 rbus_tag_t rb; 946 #endif 947 948 /* initialize pcmcia part in pccbb_softc */ 949 ph->ph_parent = (struct device *)sc; 950 ph->sock = sc->sc_function; 951 ph->flags = 0; 952 ph->shutdown = 0; 953 ph->ih_irq = sc->sc_pa.pa_intrline; 954 ph->ph_bus_t = sc->sc_base_memt; 955 ph->ph_bus_h = sc->sc_base_memh; 956 ph->ph_read = pccbb_pcmcia_read; 957 ph->ph_write = pccbb_pcmcia_write; 958 sc->sc_pct = &pccbb_pcmcia_funcs; 959 960 /* 961 * We need to do a few things here: 962 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 963 * setting the IRQ numbers to 0. 964 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 965 * routing of CSC interrupts (e.g. card removal) to PCI while in 966 * PCMCIA mode. We just leave this set all the time. 967 * 3) Enable card insertion/removal interrupts in case the chip also 968 * needs that while in PCMCIA mode. 969 * 4) Clear any pending CSC interrupt. 970 */ 971 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE); 972 if (sc->sc_chipset == CB_TI113X) { 973 Pcic_write(ph, PCIC_CSC_INTR, 0); 974 } else { 975 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 976 Pcic_read(ph, PCIC_CSC); 977 } 978 979 /* initialize pcmcia bus attachment */ 980 paa->paa_busname = "pcmcia"; 981 paa->pct = sc->sc_pct; 982 paa->pch = ph; 983 paa->iobase = 0; /* I don't use them */ 984 paa->iosize = 0; 985 #if rbus 986 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 987 paa->iobase = rb->rb_start + rb->rb_offset; 988 paa->iosize = rb->rb_end - rb->rb_start; 989 #endif 990 991 return; 992 } 993 994 #if 0 995 STATIC void 996 pccbb_pcmcia_attach_card(ph) 997 struct pcic_handle *ph; 998 { 999 if (ph->flags & PCIC_FLAG_CARDP) { 1000 panic("pccbb_pcmcia_attach_card: already attached"); 1001 } 1002 1003 /* call the MI attach function */ 1004 pcmcia_card_attach(ph->pcmcia); 1005 1006 ph->flags |= PCIC_FLAG_CARDP; 1007 } 1008 1009 STATIC void 1010 pccbb_pcmcia_detach_card(ph, flags) 1011 struct pcic_handle *ph; 1012 int flags; 1013 { 1014 if (!(ph->flags & PCIC_FLAG_CARDP)) { 1015 panic("pccbb_pcmcia_detach_card: already detached"); 1016 } 1017 1018 ph->flags &= ~PCIC_FLAG_CARDP; 1019 1020 /* call the MI detach function */ 1021 pcmcia_card_detach(ph->pcmcia, flags); 1022 } 1023 #endif 1024 1025 /* 1026 * int pccbbintr(arg) 1027 * void *arg; 1028 * This routine handles the interrupt from Yenta PCI-CardBus bridge 1029 * itself. 1030 */ 1031 int 1032 pccbbintr(arg) 1033 void *arg; 1034 { 1035 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1036 u_int32_t sockevent, sockstate; 1037 bus_space_tag_t memt = sc->sc_base_memt; 1038 bus_space_handle_t memh = sc->sc_base_memh; 1039 struct pcic_handle *ph = &sc->sc_pcmcia_h; 1040 1041 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 1042 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 1043 Pcic_read(ph, PCIC_CSC); 1044 1045 if (sockevent == 0) { 1046 /* This intr is not for me: it may be for my child devices. */ 1047 if (sc->sc_pil_intr_enable) { 1048 return pccbbintr_function(sc); 1049 } else { 1050 return 0; 1051 } 1052 } 1053 1054 if (sockevent & CB_SOCKET_EVENT_CD) { 1055 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1056 if (0x00 != (sockstate & CB_SOCKET_STAT_CD)) { 1057 /* A card should be removed. */ 1058 if (sc->sc_flags & CBB_CARDEXIST) { 1059 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 1060 sockevent)); 1061 DPRINTF((" card removed, 0x%08x\n", sockstate)); 1062 sc->sc_flags &= ~CBB_CARDEXIST; 1063 if (sc->sc_csc->sc_status & 1064 CARDSLOT_STATUS_CARD_16) { 1065 #if 0 1066 struct pcic_handle *ph = 1067 &sc->sc_pcmcia_h; 1068 1069 pcmcia_card_deactivate(ph->pcmcia); 1070 pccbb_pcmcia_socket_disable(ph); 1071 pccbb_pcmcia_detach_card(ph, 1072 DETACH_FORCE); 1073 #endif 1074 cardslot_event_throw(sc->sc_csc, 1075 CARDSLOT_EVENT_REMOVAL_16); 1076 } else if (sc->sc_csc->sc_status & 1077 CARDSLOT_STATUS_CARD_CB) { 1078 /* Cardbus intr removed */ 1079 cardslot_event_throw(sc->sc_csc, 1080 CARDSLOT_EVENT_REMOVAL_CB); 1081 } 1082 } else if (sc->sc_flags & CBB_INSERTING) { 1083 sc->sc_flags &= ~CBB_INSERTING; 1084 callout_stop(&sc->sc_insert_ch); 1085 } 1086 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 1087 /* 1088 * The pccbbintr may called from powerdown hook when 1089 * the system resumed, to detect the card 1090 * insertion/removal during suspension. 1091 */ 1092 (sc->sc_flags & CBB_CARDEXIST) == 0) { 1093 if (sc->sc_flags & CBB_INSERTING) { 1094 callout_stop(&sc->sc_insert_ch); 1095 } 1096 callout_reset(&sc->sc_insert_ch, hz / 5, 1097 pci113x_insert, sc); 1098 sc->sc_flags |= CBB_INSERTING; 1099 } 1100 } 1101 1102 if (sockevent & CB_SOCKET_EVENT_POWER) { 1103 DPRINTF(("Powercycling because of socket event\n")); 1104 /* XXX: Does not happen when attaching a 16-bit card */ 1105 sc->sc_pwrcycle++; 1106 wakeup(&sc->sc_pwrcycle); 1107 } 1108 1109 return (1); 1110 } 1111 1112 /* 1113 * static int pccbbintr_function(struct pccbb_softc *sc) 1114 * 1115 * This function calls each interrupt handler registered at the 1116 * bridge. The interrupt handlers are called in registered order. 1117 */ 1118 static int 1119 pccbbintr_function(sc) 1120 struct pccbb_softc *sc; 1121 { 1122 int retval = 0, val; 1123 struct pccbb_intrhand_list *pil; 1124 int s, splchanged; 1125 1126 for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1127 pil = LIST_NEXT(pil, pil_next)) { 1128 /* 1129 * XXX priority change. gross. I use if-else 1130 * sentense instead of switch-case sentense because of 1131 * avoiding duplicate case value error. More than one 1132 * IPL_XXX use same value. It depends on 1133 * implimentation. 1134 */ 1135 splchanged = 1; 1136 if (pil->pil_level == IPL_SERIAL) { 1137 s = splserial(); 1138 } else if (pil->pil_level == IPL_HIGH) { 1139 s = splhigh(); 1140 } else if (pil->pil_level == IPL_CLOCK) { 1141 s = splclock(); 1142 } else if (pil->pil_level == IPL_AUDIO) { 1143 s = splaudio(); 1144 } else if (pil->pil_level == IPL_VM) { 1145 s = splvm(); 1146 } else if (pil->pil_level == IPL_TTY) { 1147 s = spltty(); 1148 } else if (pil->pil_level == IPL_SOFTSERIAL) { 1149 s = splsoftserial(); 1150 } else if (pil->pil_level == IPL_NET) { 1151 s = splnet(); 1152 } else { 1153 s = 0; /* XXX: gcc */ 1154 splchanged = 0; 1155 /* XXX: ih lower than IPL_BIO runs w/ IPL_BIO. */ 1156 } 1157 1158 val = (*pil->pil_func)(pil->pil_arg); 1159 1160 if (splchanged != 0) { 1161 splx(s); 1162 } 1163 1164 retval = retval == 1 ? 1 : 1165 retval == 0 ? val : val != 0 ? val : retval; 1166 } 1167 1168 return retval; 1169 } 1170 1171 static void 1172 pci113x_insert(arg) 1173 void *arg; 1174 { 1175 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1176 u_int32_t sockevent, sockstate; 1177 1178 if (!(sc->sc_flags & CBB_INSERTING)) { 1179 /* We add a card only under inserting state. */ 1180 return; 1181 } 1182 sc->sc_flags &= ~CBB_INSERTING; 1183 1184 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1185 CB_SOCKET_EVENT); 1186 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1187 CB_SOCKET_STAT); 1188 1189 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1190 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1191 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1192 sc->sc_flags |= CBB_CARDEXIST; 1193 /* call pccard interrupt handler here */ 1194 if (sockstate & CB_SOCKET_STAT_16BIT) { 1195 /* 16-bit card found */ 1196 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1197 cardslot_event_throw(sc->sc_csc, 1198 CARDSLOT_EVENT_INSERTION_16); 1199 } else if (sockstate & CB_SOCKET_STAT_CB) { 1200 /* cardbus card found */ 1201 /* cardbus_attach_card(sc->sc_csc); */ 1202 cardslot_event_throw(sc->sc_csc, 1203 CARDSLOT_EVENT_INSERTION_CB); 1204 } else { 1205 /* who are you? */ 1206 } 1207 } else { 1208 callout_reset(&sc->sc_insert_ch, hz / 10, 1209 pci113x_insert, sc); 1210 } 1211 } 1212 1213 #define PCCBB_PCMCIA_OFFSET 0x800 1214 static u_int8_t 1215 pccbb_pcmcia_read(ph, reg) 1216 struct pcic_handle *ph; 1217 int reg; 1218 { 1219 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1220 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1221 1222 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1223 PCCBB_PCMCIA_OFFSET + reg); 1224 } 1225 1226 static void 1227 pccbb_pcmcia_write(ph, reg, val) 1228 struct pcic_handle *ph; 1229 int reg; 1230 u_int8_t val; 1231 { 1232 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1233 val); 1234 1235 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1236 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1237 } 1238 1239 /* 1240 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1241 */ 1242 STATIC int 1243 pccbb_ctrl(ct, command) 1244 cardbus_chipset_tag_t ct; 1245 int command; 1246 { 1247 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1248 1249 switch (command) { 1250 case CARDBUS_CD: 1251 if (2 == pccbb_detect_card(sc)) { 1252 int retval = 0; 1253 int status = cb_detect_voltage(sc); 1254 if (PCCARD_VCC_5V & status) { 1255 retval |= CARDBUS_5V_CARD; 1256 } 1257 if (PCCARD_VCC_3V & status) { 1258 retval |= CARDBUS_3V_CARD; 1259 } 1260 if (PCCARD_VCC_XV & status) { 1261 retval |= CARDBUS_XV_CARD; 1262 } 1263 if (PCCARD_VCC_YV & status) { 1264 retval |= CARDBUS_YV_CARD; 1265 } 1266 return retval; 1267 } else { 1268 return 0; 1269 } 1270 case CARDBUS_RESET: 1271 return cb_reset(sc); 1272 case CARDBUS_IO_ENABLE: /* fallthrough */ 1273 case CARDBUS_IO_DISABLE: /* fallthrough */ 1274 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1275 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1276 case CARDBUS_BM_ENABLE: /* fallthrough */ 1277 case CARDBUS_BM_DISABLE: /* fallthrough */ 1278 /* XXX: I think we don't need to call this function below. */ 1279 return pccbb_cardenable(sc, command); 1280 } 1281 1282 return 0; 1283 } 1284 1285 /* 1286 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1287 * This function returns true when it succeeds and returns false when 1288 * it fails. 1289 */ 1290 STATIC int 1291 pccbb_power(ct, command) 1292 cardbus_chipset_tag_t ct; 1293 int command; 1294 { 1295 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1296 u_int32_t status, sock_ctrl, reg_ctrl; 1297 bus_space_tag_t memt = sc->sc_base_memt; 1298 bus_space_handle_t memh = sc->sc_base_memh; 1299 int on = 0, pwrcycle; 1300 1301 DPRINTF(("pccbb_power: %s and %s [0x%x]\n", 1302 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1303 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1304 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1305 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1306 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1307 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1308 "UNKNOWN", 1309 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1310 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1311 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1312 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1313 "UNKNOWN", command)); 1314 1315 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1316 sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1317 1318 switch (command & CARDBUS_VCCMASK) { 1319 case CARDBUS_VCC_UC: 1320 break; 1321 case CARDBUS_VCC_5V: 1322 on++; 1323 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1324 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1325 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1326 } else { 1327 printf("%s: BAD voltage request: no 5 V card\n", 1328 sc->sc_dev.dv_xname); 1329 return 0; 1330 } 1331 break; 1332 case CARDBUS_VCC_3V: 1333 on++; 1334 if (CB_SOCKET_STAT_3VCARD & status) { 1335 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1336 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1337 } else { 1338 printf("%s: BAD voltage request: no 3.3 V card\n", 1339 sc->sc_dev.dv_xname); 1340 return 0; 1341 } 1342 break; 1343 case CARDBUS_VCC_0V: 1344 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1345 break; 1346 default: 1347 return 0; /* power NEVER changed */ 1348 } 1349 1350 switch (command & CARDBUS_VPPMASK) { 1351 case CARDBUS_VPP_UC: 1352 break; 1353 case CARDBUS_VPP_0V: 1354 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1355 break; 1356 case CARDBUS_VPP_VCC: 1357 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1358 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1359 break; 1360 case CARDBUS_VPP_12V: 1361 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1362 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1363 break; 1364 } 1365 1366 pwrcycle = sc->sc_pwrcycle; 1367 1368 #if 0 1369 DPRINTF(("sock_ctrl: 0x%x\n", sock_ctrl)); 1370 #endif 1371 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1372 1373 if (on) { 1374 int s, error = 0; 1375 struct timeval before, after, diff; 1376 1377 DPRINTF(("Waiting for bridge to power up\n")); 1378 microtime(&before); 1379 s = splbio(); 1380 while (pwrcycle == sc->sc_pwrcycle) { 1381 /* 1382 * XXX: Set timeout to 200ms because power cycle event 1383 * will never happen when attaching a 16-bit card. 1384 */ 1385 if ((error = tsleep(&sc->sc_pwrcycle, PWAIT, "pccpwr", 1386 hz / 5)) == EWOULDBLOCK) 1387 break; 1388 } 1389 splx(s); 1390 microtime(&after); 1391 timersub(&after, &before, &diff); 1392 aprint_debug("%s: wait took%s %ld.%06lds\n", 1393 sc->sc_dev.dv_xname, 1394 error == EWOULDBLOCK ? " too long" : "", 1395 diff.tv_sec, diff.tv_usec); 1396 1397 /* 1398 * Ok, wait a bit longer for things to settle. 1399 */ 1400 if (sc->sc_chipset == CB_TOPIC95B) 1401 DELAY_MS(100, sc); 1402 } 1403 1404 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1405 1406 if (on && sc->sc_chipset != CB_TOPIC95B) { 1407 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0) 1408 printf("%s: power on failed?\n", sc->sc_dev.dv_xname); 1409 } 1410 1411 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1412 printf("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1413 sc->sc_dev.dv_xname, sock_ctrl, status); 1414 printf("%s: disabling socket\n", sc->sc_dev.dv_xname); 1415 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1416 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1417 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1418 status &= ~CB_SOCKET_STAT_BADVCC; 1419 bus_space_write_4(memt, memh, CB_SOCKET_STAT, status); 1420 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1421 CB_SOCKET_STAT)); 1422 return 0; 1423 } 1424 1425 if (sc->sc_chipset == CB_TOPIC97) { 1426 reg_ctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL); 1427 reg_ctrl &= ~TOPIC97_REG_CTRL_TESTMODE; 1428 if ((command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V) 1429 reg_ctrl &= ~TOPIC97_REG_CTRL_CLKRUN_ENA; 1430 else 1431 reg_ctrl |= TOPIC97_REG_CTRL_CLKRUN_ENA; 1432 pci_conf_write(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL, reg_ctrl); 1433 } 1434 1435 return 1; /* power changed correctly */ 1436 } 1437 1438 #if defined CB_PCMCIA_POLL 1439 struct cb_poll_str { 1440 void *arg; 1441 int (*func)(void *); 1442 int level; 1443 pccard_chipset_tag_t ct; 1444 int count; 1445 struct callout poll_ch; 1446 }; 1447 1448 static struct cb_poll_str cb_poll[10]; 1449 static int cb_poll_n = 0; 1450 1451 static void cb_pcmcia_poll(void *arg); 1452 1453 static void 1454 cb_pcmcia_poll(arg) 1455 void *arg; 1456 { 1457 struct cb_poll_str *poll = arg; 1458 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1459 struct pccbb_softc *sc = psc->cpc_parent; 1460 int s; 1461 u_int32_t spsr; /* socket present-state reg */ 1462 1463 callout_reset(&poll->poll_ch, hz / 10, cb_pcmcia_poll, poll); 1464 switch (poll->level) { 1465 case IPL_NET: 1466 s = splnet(); 1467 break; 1468 case IPL_BIO: 1469 s = splbio(); 1470 break; 1471 case IPL_TTY: /* fallthrough */ 1472 default: 1473 s = spltty(); 1474 break; 1475 } 1476 1477 spsr = 1478 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1479 CB_SOCKET_STAT); 1480 1481 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1482 if (!(spsr & 0x40)) { /* CINT low */ 1483 #else 1484 if (1) { 1485 #endif 1486 if ((*poll->func) (poll->arg) == 1) { 1487 ++poll->count; 1488 printf("intr: reported from poller, 0x%x\n", spsr); 1489 #if defined LEVEL2 1490 } else { 1491 printf("intr: miss! 0x%x\n", spsr); 1492 #endif 1493 } 1494 } 1495 splx(s); 1496 } 1497 #endif /* defined CB_PCMCIA_POLL */ 1498 1499 /* 1500 * static int pccbb_detect_card(struct pccbb_softc *sc) 1501 * return value: 0 if no card exists. 1502 * 1 if 16-bit card exists. 1503 * 2 if cardbus card exists. 1504 */ 1505 static int 1506 pccbb_detect_card(sc) 1507 struct pccbb_softc *sc; 1508 { 1509 bus_space_handle_t base_memh = sc->sc_base_memh; 1510 bus_space_tag_t base_memt = sc->sc_base_memt; 1511 u_int32_t sockstat = 1512 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1513 int retval = 0; 1514 1515 /* CD1 and CD2 asserted */ 1516 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1517 /* card must be present */ 1518 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1519 /* NOTACARD DEASSERTED */ 1520 if (CB_SOCKET_STAT_CB & sockstat) { 1521 /* CardBus mode */ 1522 retval = 2; 1523 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1524 /* 16-bit mode */ 1525 retval = 1; 1526 } 1527 } 1528 } 1529 return retval; 1530 } 1531 1532 /* 1533 * STATIC int cb_reset(struct pccbb_softc *sc) 1534 * This function resets CardBus card. 1535 */ 1536 STATIC int 1537 cb_reset(sc) 1538 struct pccbb_softc *sc; 1539 { 1540 /* 1541 * Reset Assert at least 20 ms 1542 * Some machines request longer duration. 1543 */ 1544 int reset_duration = 1545 (sc->sc_chipset == CB_RX5C47X ? 400 : 40); 1546 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1547 1548 /* Reset bit Assert (bit 6 at 0x3E) */ 1549 bcr |= CB_BCR_RESET_ENABLE; 1550 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1551 DELAY_MS(reset_duration, sc); 1552 1553 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1554 /* Reset bit Deassert (bit 6 at 0x3E) */ 1555 bcr &= ~CB_BCR_RESET_ENABLE; 1556 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1557 DELAY_MS(reset_duration, sc); 1558 } 1559 /* No card found on the slot. Keep Reset. */ 1560 return 1; 1561 } 1562 1563 /* 1564 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1565 * This function detect card Voltage. 1566 */ 1567 STATIC int 1568 cb_detect_voltage(sc) 1569 struct pccbb_softc *sc; 1570 { 1571 u_int32_t psr; /* socket present-state reg */ 1572 bus_space_tag_t iot = sc->sc_base_memt; 1573 bus_space_handle_t ioh = sc->sc_base_memh; 1574 int vol = PCCARD_VCC_UKN; /* set 0 */ 1575 1576 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1577 1578 if (0x400u & psr) { 1579 vol |= PCCARD_VCC_5V; 1580 } 1581 if (0x800u & psr) { 1582 vol |= PCCARD_VCC_3V; 1583 } 1584 1585 return vol; 1586 } 1587 1588 STATIC int 1589 cbbprint(aux, pcic) 1590 void *aux; 1591 const char *pcic; 1592 { 1593 /* 1594 struct cbslot_attach_args *cba = aux; 1595 1596 if (cba->cba_slot >= 0) { 1597 aprint_normal(" slot %d", cba->cba_slot); 1598 } 1599 */ 1600 return UNCONF; 1601 } 1602 1603 /* 1604 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1605 * This function enables and disables the card 1606 */ 1607 STATIC int 1608 pccbb_cardenable(sc, function) 1609 struct pccbb_softc *sc; 1610 int function; 1611 { 1612 u_int32_t command = 1613 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1614 1615 DPRINTF(("pccbb_cardenable:")); 1616 switch (function) { 1617 case CARDBUS_IO_ENABLE: 1618 command |= PCI_COMMAND_IO_ENABLE; 1619 break; 1620 case CARDBUS_IO_DISABLE: 1621 command &= ~PCI_COMMAND_IO_ENABLE; 1622 break; 1623 case CARDBUS_MEM_ENABLE: 1624 command |= PCI_COMMAND_MEM_ENABLE; 1625 break; 1626 case CARDBUS_MEM_DISABLE: 1627 command &= ~PCI_COMMAND_MEM_ENABLE; 1628 break; 1629 case CARDBUS_BM_ENABLE: 1630 command |= PCI_COMMAND_MASTER_ENABLE; 1631 break; 1632 case CARDBUS_BM_DISABLE: 1633 command &= ~PCI_COMMAND_MASTER_ENABLE; 1634 break; 1635 default: 1636 return 0; 1637 } 1638 1639 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1640 DPRINTF((" command reg 0x%x\n", command)); 1641 return 1; 1642 } 1643 1644 #if !rbus 1645 /* 1646 * int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1647 */ 1648 static int 1649 pccbb_io_open(ct, win, start, end) 1650 cardbus_chipset_tag_t ct; 1651 int win; 1652 u_int32_t start, end; 1653 { 1654 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1655 int basereg; 1656 int limitreg; 1657 1658 if ((win < 0) || (win > 2)) { 1659 #if defined DIAGNOSTIC 1660 printf("cardbus_io_open: window out of range %d\n", win); 1661 #endif 1662 return 0; 1663 } 1664 1665 basereg = win * 8 + 0x2c; 1666 limitreg = win * 8 + 0x30; 1667 1668 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1669 start, basereg, end, limitreg)); 1670 1671 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1672 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1673 return 1; 1674 } 1675 1676 /* 1677 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1678 */ 1679 static int 1680 pccbb_io_close(ct, win) 1681 cardbus_chipset_tag_t ct; 1682 int win; 1683 { 1684 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1685 int basereg; 1686 int limitreg; 1687 1688 if ((win < 0) || (win > 2)) { 1689 #if defined DIAGNOSTIC 1690 printf("cardbus_io_close: window out of range %d\n", win); 1691 #endif 1692 return 0; 1693 } 1694 1695 basereg = win * 8 + 0x2c; 1696 limitreg = win * 8 + 0x30; 1697 1698 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1699 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1700 return 1; 1701 } 1702 1703 /* 1704 * int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1705 */ 1706 static int 1707 pccbb_mem_open(ct, win, start, end) 1708 cardbus_chipset_tag_t ct; 1709 int win; 1710 u_int32_t start, end; 1711 { 1712 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1713 int basereg; 1714 int limitreg; 1715 1716 if ((win < 0) || (win > 2)) { 1717 #if defined DIAGNOSTIC 1718 printf("cardbus_mem_open: window out of range %d\n", win); 1719 #endif 1720 return 0; 1721 } 1722 1723 basereg = win * 8 + 0x1c; 1724 limitreg = win * 8 + 0x20; 1725 1726 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1727 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1728 return 1; 1729 } 1730 1731 /* 1732 * int pccbb_mem_close(cardbus_chipset_tag_t, int) 1733 */ 1734 static int 1735 pccbb_mem_close(ct, win) 1736 cardbus_chipset_tag_t ct; 1737 int win; 1738 { 1739 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1740 int basereg; 1741 int limitreg; 1742 1743 if ((win < 0) || (win > 2)) { 1744 #if defined DIAGNOSTIC 1745 printf("cardbus_mem_close: window out of range %d\n", win); 1746 #endif 1747 return 0; 1748 } 1749 1750 basereg = win * 8 + 0x1c; 1751 limitreg = win * 8 + 0x20; 1752 1753 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1754 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1755 return 1; 1756 } 1757 #endif 1758 1759 /* 1760 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1761 * int irq, 1762 * int level, 1763 * int (* func)(void *), 1764 * void *arg) 1765 * 1766 * This function registers an interrupt handler at the bridge, in 1767 * order not to call the interrupt handlers of child devices when 1768 * a card-deletion interrupt occurs. 1769 * 1770 * The arguments irq and level are not used. 1771 */ 1772 static void * 1773 pccbb_cb_intr_establish(ct, irq, level, func, arg) 1774 cardbus_chipset_tag_t ct; 1775 int irq, level; 1776 int (*func)(void *); 1777 void *arg; 1778 { 1779 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1780 1781 return pccbb_intr_establish(sc, irq, level, func, arg); 1782 } 1783 1784 1785 /* 1786 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1787 * void *ih) 1788 * 1789 * This function removes an interrupt handler pointed by ih. 1790 */ 1791 static void 1792 pccbb_cb_intr_disestablish(ct, ih) 1793 cardbus_chipset_tag_t ct; 1794 void *ih; 1795 { 1796 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1797 1798 pccbb_intr_disestablish(sc, ih); 1799 } 1800 1801 1802 void 1803 pccbb_intr_route(sc) 1804 struct pccbb_softc *sc; 1805 { 1806 pcireg_t reg; 1807 1808 /* initialize bridge intr routing */ 1809 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1810 reg &= ~CB_BCR_INTR_IREQ_ENABLE; 1811 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1812 1813 switch (sc->sc_chipset) { 1814 case CB_TI113X: 1815 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1816 /* functional intr enabled */ 1817 reg |= PCI113X_CBCTRL_PCI_INTR; 1818 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1819 break; 1820 default: 1821 break; 1822 } 1823 } 1824 1825 /* 1826 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1827 * int irq, 1828 * int level, 1829 * int (* func)(void *), 1830 * void *arg) 1831 * 1832 * This function registers an interrupt handler at the bridge, in 1833 * order not to call the interrupt handlers of child devices when 1834 * a card-deletion interrupt occurs. 1835 * 1836 * The arguments irq is not used because pccbb selects intr vector. 1837 */ 1838 static void * 1839 pccbb_intr_establish(sc, irq, level, func, arg) 1840 struct pccbb_softc *sc; 1841 int irq, level; 1842 int (*func)(void *); 1843 void *arg; 1844 { 1845 struct pccbb_intrhand_list *pil, *newpil; 1846 1847 DPRINTF(("pccbb_intr_establish start. %p\n", LIST_FIRST(&sc->sc_pil))); 1848 1849 if (LIST_EMPTY(&sc->sc_pil)) { 1850 pccbb_intr_route(sc); 1851 } 1852 1853 /* 1854 * Allocate a room for interrupt handler structure. 1855 */ 1856 if (NULL == (newpil = 1857 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1858 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1859 return NULL; 1860 } 1861 1862 newpil->pil_func = func; 1863 newpil->pil_arg = arg; 1864 newpil->pil_level = level; 1865 1866 if (LIST_EMPTY(&sc->sc_pil)) { 1867 LIST_INSERT_HEAD(&sc->sc_pil, newpil, pil_next); 1868 } else { 1869 for (pil = LIST_FIRST(&sc->sc_pil); 1870 LIST_NEXT(pil, pil_next) != NULL; 1871 pil = LIST_NEXT(pil, pil_next)); 1872 LIST_INSERT_AFTER(pil, newpil, pil_next); 1873 } 1874 1875 DPRINTF(("pccbb_intr_establish add pil. %p\n", 1876 LIST_FIRST(&sc->sc_pil))); 1877 1878 return newpil; 1879 } 1880 1881 /* 1882 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1883 * void *ih) 1884 * 1885 * This function removes an interrupt handler pointed by ih. ih 1886 * should be the value returned by cardbus_intr_establish() or 1887 * NULL. 1888 * 1889 * When ih is NULL, this function will do nothing. 1890 */ 1891 static void 1892 pccbb_intr_disestablish(sc, ih) 1893 struct pccbb_softc *sc; 1894 void *ih; 1895 { 1896 struct pccbb_intrhand_list *pil; 1897 pcireg_t reg; 1898 1899 DPRINTF(("pccbb_intr_disestablish start. %p\n", 1900 LIST_FIRST(&sc->sc_pil))); 1901 1902 if (ih == NULL) { 1903 /* intr handler is not set */ 1904 DPRINTF(("pccbb_intr_disestablish: no ih\n")); 1905 return; 1906 } 1907 1908 #ifdef DIAGNOSTIC 1909 for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1910 pil = LIST_NEXT(pil, pil_next)) { 1911 DPRINTF(("pccbb_intr_disestablish: pil %p\n", pil)); 1912 if (pil == ih) { 1913 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1914 break; 1915 } 1916 } 1917 if (pil == NULL) { 1918 panic("pccbb_intr_disestablish: %s cannot find pil %p", 1919 sc->sc_dev.dv_xname, ih); 1920 } 1921 #endif 1922 1923 pil = (struct pccbb_intrhand_list *)ih; 1924 LIST_REMOVE(pil, pil_next); 1925 free(pil, M_DEVBUF); 1926 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1927 1928 if (LIST_EMPTY(&sc->sc_pil)) { 1929 /* No interrupt handlers */ 1930 1931 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1932 1933 /* stop routing PCI intr */ 1934 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1935 reg |= CB_BCR_INTR_IREQ_ENABLE; 1936 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1937 1938 switch (sc->sc_chipset) { 1939 case CB_TI113X: 1940 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1941 /* functional intr disabled */ 1942 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1943 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1944 break; 1945 default: 1946 break; 1947 } 1948 } 1949 } 1950 1951 #if defined SHOW_REGS 1952 static void 1953 cb_show_regs(pc, tag, memt, memh) 1954 pci_chipset_tag_t pc; 1955 pcitag_t tag; 1956 bus_space_tag_t memt; 1957 bus_space_handle_t memh; 1958 { 1959 int i; 1960 printf("PCI config regs:"); 1961 for (i = 0; i < 0x50; i += 4) { 1962 if (i % 16 == 0) { 1963 printf("\n 0x%02x:", i); 1964 } 1965 printf(" %08x", pci_conf_read(pc, tag, i)); 1966 } 1967 for (i = 0x80; i < 0xb0; i += 4) { 1968 if (i % 16 == 0) { 1969 printf("\n 0x%02x:", i); 1970 } 1971 printf(" %08x", pci_conf_read(pc, tag, i)); 1972 } 1973 1974 if (memh == 0) { 1975 printf("\n"); 1976 return; 1977 } 1978 1979 printf("\nsocket regs:"); 1980 for (i = 0; i <= 0x10; i += 0x04) { 1981 printf(" %08x", bus_space_read_4(memt, memh, i)); 1982 } 1983 printf("\nExCA regs:"); 1984 for (i = 0; i < 0x08; ++i) { 1985 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1986 } 1987 printf("\n"); 1988 return; 1989 } 1990 #endif 1991 1992 /* 1993 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1994 * int busno, int function) 1995 * This is the function to make a tag to access config space of 1996 * a CardBus Card. It works same as pci_conf_read. 1997 */ 1998 static cardbustag_t 1999 pccbb_make_tag(cc, busno, function) 2000 cardbus_chipset_tag_t cc; 2001 int busno, function; 2002 { 2003 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 2004 2005 return pci_make_tag(sc->sc_pc, busno, 0, function); 2006 } 2007 2008 static void 2009 pccbb_free_tag(cc, tag) 2010 cardbus_chipset_tag_t cc; 2011 cardbustag_t tag; 2012 { 2013 } 2014 2015 /* 2016 * static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t cc, 2017 * cardbustag_t tag, int offset) 2018 * This is the function to read the config space of a CardBus Card. 2019 * It works same as pci_conf_read. 2020 */ 2021 static cardbusreg_t 2022 pccbb_conf_read(cc, tag, offset) 2023 cardbus_chipset_tag_t cc; 2024 cardbustag_t tag; 2025 int offset; /* register offset */ 2026 { 2027 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 2028 2029 return pci_conf_read(sc->sc_pc, tag, offset); 2030 } 2031 2032 /* 2033 * static void pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, 2034 * int offs, cardbusreg_t val) 2035 * This is the function to write the config space of a CardBus Card. 2036 * It works same as pci_conf_write. 2037 */ 2038 static void 2039 pccbb_conf_write(cc, tag, reg, val) 2040 cardbus_chipset_tag_t cc; 2041 cardbustag_t tag; 2042 int reg; /* register offset */ 2043 cardbusreg_t val; 2044 { 2045 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 2046 2047 pci_conf_write(sc->sc_pc, tag, reg, val); 2048 } 2049 2050 #if 0 2051 STATIC int 2052 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 2053 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 2054 int speed, int flags, 2055 bus_space_handle_t * iohp) 2056 #endif 2057 /* 2058 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 2059 * bus_addr_t start, bus_size_t size, 2060 * bus_size_t align, 2061 * struct pcmcia_io_handle *pcihp 2062 * 2063 * This function only allocates I/O region for pccard. This function 2064 * never maps the allocated region to pccard I/O area. 2065 * 2066 * XXX: The interface of this function is not very good, I believe. 2067 */ 2068 STATIC int 2069 pccbb_pcmcia_io_alloc(pch, start, size, align, pcihp) 2070 pcmcia_chipset_handle_t pch; 2071 bus_addr_t start; /* start address */ 2072 bus_size_t size; 2073 bus_size_t align; 2074 struct pcmcia_io_handle *pcihp; 2075 { 2076 struct pcic_handle *ph = (struct pcic_handle *)pch; 2077 bus_addr_t ioaddr; 2078 int flags = 0; 2079 bus_space_tag_t iot; 2080 bus_space_handle_t ioh; 2081 bus_addr_t mask; 2082 #if rbus 2083 rbus_tag_t rb; 2084 #endif 2085 if (align == 0) { 2086 align = size; /* XXX: funny??? */ 2087 } 2088 2089 if (start != 0) { 2090 /* XXX: assume all card decode lower 10 bits by its hardware */ 2091 mask = 0x3ff; 2092 /* enforce to use only masked address */ 2093 start &= mask; 2094 } else { 2095 /* 2096 * calculate mask: 2097 * 1. get the most significant bit of size (call it msb). 2098 * 2. compare msb with the value of size. 2099 * 3. if size is larger, shift msb left once. 2100 * 4. obtain mask value to decrement msb. 2101 */ 2102 bus_size_t size_tmp = size; 2103 int shifts = 0; 2104 2105 mask = 1; 2106 while (size_tmp) { 2107 ++shifts; 2108 size_tmp >>= 1; 2109 } 2110 mask = (1 << shifts); 2111 if (mask < size) { 2112 mask <<= 1; 2113 } 2114 --mask; 2115 } 2116 2117 /* 2118 * Allocate some arbitrary I/O space. 2119 */ 2120 2121 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 2122 2123 #if rbus 2124 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 2125 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 2126 return 1; 2127 } 2128 DPRINTF(("pccbb_pcmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2129 (u_long) ioaddr, (u_long) size)); 2130 #else 2131 if (start) { 2132 ioaddr = start; 2133 if (bus_space_map(iot, start, size, 0, &ioh)) { 2134 return 1; 2135 } 2136 DPRINTF(("pccbb_pcmcia_io_alloc map port 0x%lx+0x%lx\n", 2137 (u_long) ioaddr, (u_long) size)); 2138 } else { 2139 flags |= PCMCIA_IO_ALLOCATED; 2140 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 2141 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 2142 size, align, 0, 0, &ioaddr, &ioh)) { 2143 /* No room be able to be get. */ 2144 return 1; 2145 } 2146 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2147 (u_long) ioaddr, (u_long) size)); 2148 } 2149 #endif 2150 2151 pcihp->iot = iot; 2152 pcihp->ioh = ioh; 2153 pcihp->addr = ioaddr; 2154 pcihp->size = size; 2155 pcihp->flags = flags; 2156 2157 return 0; 2158 } 2159 2160 /* 2161 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2162 * struct pcmcia_io_handle *pcihp) 2163 * 2164 * This function only frees I/O region for pccard. 2165 * 2166 * XXX: The interface of this function is not very good, I believe. 2167 */ 2168 void 2169 pccbb_pcmcia_io_free(pch, pcihp) 2170 pcmcia_chipset_handle_t pch; 2171 struct pcmcia_io_handle *pcihp; 2172 { 2173 #if !rbus 2174 bus_space_tag_t iot = pcihp->iot; 2175 #endif 2176 bus_space_handle_t ioh = pcihp->ioh; 2177 bus_size_t size = pcihp->size; 2178 2179 #if rbus 2180 struct pccbb_softc *sc = 2181 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 2182 rbus_tag_t rb = sc->sc_rbus_iot; 2183 2184 rbus_space_free(rb, ioh, size, NULL); 2185 #else 2186 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 2187 bus_space_free(iot, ioh, size); 2188 else 2189 bus_space_unmap(iot, ioh, size); 2190 #endif 2191 } 2192 2193 /* 2194 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 2195 * bus_addr_t offset, bus_size_t size, 2196 * struct pcmcia_io_handle *pcihp, 2197 * int *windowp) 2198 * 2199 * This function maps the allocated I/O region to pccard. This function 2200 * never allocates any I/O region for pccard I/O area. I don't 2201 * understand why the original authors of pcmciabus separated alloc and 2202 * map. I believe the two must be unite. 2203 * 2204 * XXX: no wait timing control? 2205 */ 2206 int 2207 pccbb_pcmcia_io_map(pch, width, offset, size, pcihp, windowp) 2208 pcmcia_chipset_handle_t pch; 2209 int width; 2210 bus_addr_t offset; 2211 bus_size_t size; 2212 struct pcmcia_io_handle *pcihp; 2213 int *windowp; 2214 { 2215 struct pcic_handle *ph = (struct pcic_handle *)pch; 2216 bus_addr_t ioaddr = pcihp->addr + offset; 2217 int i, win; 2218 #if defined CBB_DEBUG 2219 static const char *width_names[] = { "dynamic", "io8", "io16" }; 2220 #endif 2221 2222 /* Sanity check I/O handle. */ 2223 2224 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 2225 panic("pccbb_pcmcia_io_map iot is bogus"); 2226 } 2227 2228 /* XXX Sanity check offset/size. */ 2229 2230 win = -1; 2231 for (i = 0; i < PCIC_IO_WINS; i++) { 2232 if ((ph->ioalloc & (1 << i)) == 0) { 2233 win = i; 2234 ph->ioalloc |= (1 << i); 2235 break; 2236 } 2237 } 2238 2239 if (win == -1) { 2240 return 1; 2241 } 2242 2243 *windowp = win; 2244 2245 /* XXX this is pretty gross */ 2246 2247 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2248 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2249 2250 /* XXX wtf is this doing here? */ 2251 2252 #if 0 2253 printf(" port 0x%lx", (u_long) ioaddr); 2254 if (size > 1) { 2255 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2256 } 2257 #endif 2258 2259 ph->io[win].addr = ioaddr; 2260 ph->io[win].size = size; 2261 ph->io[win].width = width; 2262 2263 /* actual dirty register-value changing in the function below. */ 2264 pccbb_pcmcia_do_io_map(ph, win); 2265 2266 return 0; 2267 } 2268 2269 /* 2270 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2271 * 2272 * This function changes register-value to map I/O region for pccard. 2273 */ 2274 static void 2275 pccbb_pcmcia_do_io_map(ph, win) 2276 struct pcic_handle *ph; 2277 int win; 2278 { 2279 static u_int8_t pcic_iowidth[3] = { 2280 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2281 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2282 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2283 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2284 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2285 }; 2286 2287 #define PCIC_SIA_START_LOW 0 2288 #define PCIC_SIA_START_HIGH 1 2289 #define PCIC_SIA_STOP_LOW 2 2290 #define PCIC_SIA_STOP_HIGH 3 2291 2292 int regbase_win = 0x8 + win * 0x04; 2293 u_int8_t ioctl, enable; 2294 2295 DPRINTF(("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx " 2296 "width %d\n", win, (unsigned long)ph->io[win].addr, 2297 (unsigned long)ph->io[win].size, ph->io[win].width * 8)); 2298 2299 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2300 ph->io[win].addr & 0xff); 2301 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2302 (ph->io[win].addr >> 8) & 0xff); 2303 2304 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2305 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2306 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2307 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2308 2309 ioctl = Pcic_read(ph, PCIC_IOCTL); 2310 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2311 switch (win) { 2312 case 0: 2313 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2314 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2315 PCIC_IOCTL_IO0_DATASIZE_MASK); 2316 ioctl |= pcic_iowidth[ph->io[win].width]; 2317 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2318 break; 2319 case 1: 2320 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2321 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2322 PCIC_IOCTL_IO1_DATASIZE_MASK); 2323 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2324 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2325 break; 2326 } 2327 Pcic_write(ph, PCIC_IOCTL, ioctl); 2328 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2329 #if defined(CBB_DEBUG) 2330 { 2331 u_int8_t start_low = 2332 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2333 u_int8_t start_high = 2334 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2335 u_int8_t stop_low = 2336 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2337 u_int8_t stop_high = 2338 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2339 printf("pccbb_pcmcia_do_io_map start %02x %02x, " 2340 "stop %02x %02x, ioctl %02x enable %02x\n", 2341 start_low, start_high, stop_low, stop_high, ioctl, enable); 2342 } 2343 #endif 2344 } 2345 2346 /* 2347 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2348 * 2349 * This function unmaps I/O region. No return value. 2350 */ 2351 STATIC void 2352 pccbb_pcmcia_io_unmap(pch, win) 2353 pcmcia_chipset_handle_t pch; 2354 int win; 2355 { 2356 struct pcic_handle *ph = (struct pcic_handle *)pch; 2357 int reg; 2358 2359 if (win >= PCIC_IO_WINS || win < 0) { 2360 panic("pccbb_pcmcia_io_unmap: window out of range"); 2361 } 2362 2363 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2364 switch (win) { 2365 case 0: 2366 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2367 break; 2368 case 1: 2369 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2370 break; 2371 } 2372 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2373 2374 ph->ioalloc &= ~(1 << win); 2375 } 2376 2377 static int 2378 pccbb_pcmcia_wait_ready(ph) 2379 struct pcic_handle *ph; 2380 { 2381 u_int8_t stat; 2382 int i; 2383 2384 /* wait an initial 10ms for quick cards */ 2385 stat = Pcic_read(ph, PCIC_IF_STATUS); 2386 if (stat & PCIC_IF_STATUS_READY) 2387 return (0); 2388 pccbb_pcmcia_delay(ph, 10, "pccwr0"); 2389 for (i = 0; i < 50; i++) { 2390 stat = Pcic_read(ph, PCIC_IF_STATUS); 2391 if (stat & PCIC_IF_STATUS_READY) 2392 return (0); 2393 if ((stat & PCIC_IF_STATUS_CARDDETECT_MASK) != 2394 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2395 return (ENXIO); 2396 /* wait .1s (100ms) each iteration now */ 2397 pccbb_pcmcia_delay(ph, 100, "pccwr1"); 2398 } 2399 2400 printf("pccbb_pcmcia_wait_ready: ready never happened, status=%02x\n", stat); 2401 return (EWOULDBLOCK); 2402 } 2403 2404 /* 2405 * Perform long (msec order) delay. 2406 */ 2407 static void 2408 pccbb_pcmcia_delay(ph, timo, wmesg) 2409 struct pcic_handle *ph; 2410 int timo; /* in ms. must not be zero */ 2411 const char *wmesg; 2412 { 2413 #ifdef DIAGNOSTIC 2414 if (timo <= 0) 2415 panic("pccbb_pcmcia_delay: called with timeout %d", timo); 2416 if (!curlwp) 2417 panic("pccbb_pcmcia_delay: called in interrupt context"); 2418 #if 0 2419 if (!ph->event_thread) 2420 panic("pccbb_pcmcia_delay: no event thread"); 2421 #endif 2422 #endif 2423 DPRINTF(("pccbb_pcmcia_delay: \"%s\" %p, sleep %d ms\n", 2424 wmesg, ph->event_thread, timo)); 2425 tsleep(pccbb_pcmcia_delay, PWAIT, wmesg, roundup(timo * hz, 1000) / 1000); 2426 } 2427 2428 /* 2429 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2430 * 2431 * This function enables the card. All information is stored in 2432 * the first argument, pcmcia_chipset_handle_t. 2433 */ 2434 STATIC void 2435 pccbb_pcmcia_socket_enable(pch) 2436 pcmcia_chipset_handle_t pch; 2437 { 2438 struct pcic_handle *ph = (struct pcic_handle *)pch; 2439 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2440 pcireg_t spsr; 2441 int voltage; 2442 int win; 2443 u_int8_t power, intr; 2444 #ifdef DIAGNOSTIC 2445 int reg; 2446 #endif 2447 2448 /* this bit is mostly stolen from pcic_attach_card */ 2449 2450 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2451 2452 /* get card Vcc info */ 2453 spsr = 2454 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2455 CB_SOCKET_STAT); 2456 if (spsr & CB_SOCKET_STAT_5VCARD) { 2457 DPRINTF(("5V card\n")); 2458 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2459 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2460 DPRINTF(("3V card\n")); 2461 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2462 } else { 2463 DPRINTF(("?V card, 0x%x\n", spsr)); /* XXX */ 2464 return; 2465 } 2466 2467 /* disable interrupts; assert RESET */ 2468 intr = Pcic_read(ph, PCIC_INTR); 2469 intr &= PCIC_INTR_ENABLE; 2470 Pcic_write(ph, PCIC_INTR, intr); 2471 2472 /* zero out the address windows */ 2473 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2474 2475 /* power down the socket to reset it, clear the card reset pin */ 2476 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2477 2478 /* power off; assert output enable bit */ 2479 power = PCIC_PWRCTL_OE; 2480 Pcic_write(ph, PCIC_PWRCTL, power); 2481 2482 /* power up the socket */ 2483 if (pccbb_power(sc, voltage) == 0) 2484 return; 2485 2486 /* 2487 * Table 4-18 and figure 4-6 of the PC Card specifiction say: 2488 * Vcc Rising Time (Tpr) = 100ms (handled in pccbb_power() above) 2489 * RESET Width (Th (Hi-z RESET)) = 1ms 2490 * RESET Width (Tw (RESET)) = 10us 2491 * 2492 * some machines require some more time to be settled 2493 * for example old toshiba topic bridges! 2494 * (100ms is added here). 2495 */ 2496 pccbb_pcmcia_delay(ph, 200 + 1, "pccen1"); 2497 2498 /* negate RESET */ 2499 intr |= PCIC_INTR_RESET; 2500 Pcic_write(ph, PCIC_INTR, intr); 2501 2502 /* 2503 * RESET Setup Time (Tsu (RESET)) = 20ms 2504 */ 2505 pccbb_pcmcia_delay(ph, 20, "pccen2"); 2506 2507 #ifdef DIAGNOSTIC 2508 reg = Pcic_read(ph, PCIC_IF_STATUS); 2509 if ((reg & PCIC_IF_STATUS_POWERACTIVE) == 0) 2510 printf("pccbb_pcmcia_socket_enable: no power, status=%x\n", reg); 2511 #endif 2512 2513 /* wait for the chip to finish initializing */ 2514 if (pccbb_pcmcia_wait_ready(ph)) { 2515 #ifdef DIAGNOSTIC 2516 printf("pccbb_pcmcia_socket_enable: never became ready\n"); 2517 #endif 2518 /* XXX return a failure status?? */ 2519 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2520 Pcic_write(ph, PCIC_PWRCTL, 0); 2521 return; 2522 } 2523 2524 /* reinstall all the memory and io mappings */ 2525 for (win = 0; win < PCIC_MEM_WINS; ++win) 2526 if (ph->memalloc & (1 << win)) 2527 pccbb_pcmcia_do_mem_map(ph, win); 2528 for (win = 0; win < PCIC_IO_WINS; ++win) 2529 if (ph->ioalloc & (1 << win)) 2530 pccbb_pcmcia_do_io_map(ph, win); 2531 } 2532 2533 /* 2534 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2535 * 2536 * This function disables the card. All information is stored in 2537 * the first argument, pcmcia_chipset_handle_t. 2538 */ 2539 STATIC void 2540 pccbb_pcmcia_socket_disable(pch) 2541 pcmcia_chipset_handle_t pch; 2542 { 2543 struct pcic_handle *ph = (struct pcic_handle *)pch; 2544 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2545 u_int8_t intr; 2546 2547 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2548 2549 /* disable interrupts; assert RESET */ 2550 intr = Pcic_read(ph, PCIC_INTR); 2551 intr &= PCIC_INTR_ENABLE; 2552 Pcic_write(ph, PCIC_INTR, intr); 2553 2554 /* zero out the address windows */ 2555 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2556 2557 /* power down the socket to reset it, clear the card reset pin */ 2558 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2559 2560 /* disable socket: negate output enable bit and power off */ 2561 Pcic_write(ph, PCIC_PWRCTL, 0); 2562 2563 /* 2564 * Vcc Falling Time (Tpf) = 300ms 2565 */ 2566 pccbb_pcmcia_delay(ph, 300, "pccwr1"); 2567 } 2568 2569 STATIC void 2570 pccbb_pcmcia_socket_settype(pch, type) 2571 pcmcia_chipset_handle_t pch; 2572 int type; 2573 { 2574 struct pcic_handle *ph = (struct pcic_handle *)pch; 2575 u_int8_t intr; 2576 2577 /* set the card type */ 2578 2579 intr = Pcic_read(ph, PCIC_INTR); 2580 intr &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_CARDTYPE_MASK); 2581 if (type == PCMCIA_IFTYPE_IO) 2582 intr |= PCIC_INTR_CARDTYPE_IO; 2583 else 2584 intr |= PCIC_INTR_CARDTYPE_MEM; 2585 Pcic_write(ph, PCIC_INTR, intr); 2586 2587 DPRINTF(("%s: pccbb_pcmcia_socket_settype %02x type %s %02x\n", 2588 ph->ph_parent->dv_xname, ph->sock, 2589 ((type == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2590 } 2591 2592 /* 2593 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2594 * 2595 * This function detects whether a card is in the slot or not. 2596 * If a card is inserted, return 1. Otherwise, return 0. 2597 */ 2598 STATIC int 2599 pccbb_pcmcia_card_detect(pch) 2600 pcmcia_chipset_handle_t pch; 2601 { 2602 struct pcic_handle *ph = (struct pcic_handle *)pch; 2603 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2604 2605 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2606 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2607 } 2608 2609 #if 0 2610 STATIC int 2611 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2612 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2613 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2614 #endif 2615 /* 2616 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2617 * bus_size_t size, 2618 * struct pcmcia_mem_handle *pcmhp) 2619 * 2620 * This function only allocates memory region for pccard. This 2621 * function never maps the allocated region to pccard memory area. 2622 * 2623 * XXX: Why the argument of start address is not in? 2624 */ 2625 STATIC int 2626 pccbb_pcmcia_mem_alloc(pch, size, pcmhp) 2627 pcmcia_chipset_handle_t pch; 2628 bus_size_t size; 2629 struct pcmcia_mem_handle *pcmhp; 2630 { 2631 struct pcic_handle *ph = (struct pcic_handle *)pch; 2632 bus_space_handle_t memh; 2633 bus_addr_t addr; 2634 bus_size_t sizepg; 2635 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2636 #if rbus 2637 rbus_tag_t rb; 2638 #endif 2639 2640 /* Check that the card is still there. */ 2641 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2642 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2643 return 1; 2644 2645 /* out of sc->memh, allocate as many pages as necessary */ 2646 2647 /* convert size to PCIC pages */ 2648 /* 2649 * This is not enough; when the requested region is on the page 2650 * boundaries, this may calculate wrong result. 2651 */ 2652 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2653 #if 0 2654 if (sizepg > PCIC_MAX_MEM_PAGES) { 2655 return 1; 2656 } 2657 #endif 2658 2659 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2660 return 1; 2661 } 2662 2663 addr = 0; /* XXX gcc -Wuninitialized */ 2664 2665 #if rbus 2666 rb = sc->sc_rbus_memt; 2667 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2668 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2669 &addr, &memh)) { 2670 return 1; 2671 } 2672 #else 2673 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2674 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2675 0, /* boundary */ 2676 0, /* flags */ 2677 &addr, &memh)) { 2678 return 1; 2679 } 2680 #endif 2681 2682 DPRINTF(("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, " 2683 "realsize 0x%lx\n", (unsigned long)addr, (unsigned long)size, 2684 (unsigned long)sizepg * PCIC_MEM_PAGESIZE)); 2685 2686 pcmhp->memt = sc->sc_memt; 2687 pcmhp->memh = memh; 2688 pcmhp->addr = addr; 2689 pcmhp->size = size; 2690 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2691 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2692 pcmhp->mhandle = 0; 2693 /* No offset??? Funny. */ 2694 2695 return 0; 2696 } 2697 2698 /* 2699 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2700 * struct pcmcia_mem_handle *pcmhp) 2701 * 2702 * This function release the memory space allocated by the function 2703 * pccbb_pcmcia_mem_alloc(). 2704 */ 2705 STATIC void 2706 pccbb_pcmcia_mem_free(pch, pcmhp) 2707 pcmcia_chipset_handle_t pch; 2708 struct pcmcia_mem_handle *pcmhp; 2709 { 2710 #if rbus 2711 struct pcic_handle *ph = (struct pcic_handle *)pch; 2712 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2713 2714 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2715 #else 2716 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2717 #endif 2718 } 2719 2720 /* 2721 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2722 * 2723 * This function release the memory space allocated by the function 2724 * pccbb_pcmcia_mem_alloc(). 2725 */ 2726 STATIC void 2727 pccbb_pcmcia_do_mem_map(ph, win) 2728 struct pcic_handle *ph; 2729 int win; 2730 { 2731 int regbase_win; 2732 bus_addr_t phys_addr; 2733 bus_addr_t phys_end; 2734 2735 #define PCIC_SMM_START_LOW 0 2736 #define PCIC_SMM_START_HIGH 1 2737 #define PCIC_SMM_STOP_LOW 2 2738 #define PCIC_SMM_STOP_HIGH 3 2739 #define PCIC_CMA_LOW 4 2740 #define PCIC_CMA_HIGH 5 2741 2742 u_int8_t start_low, start_high = 0; 2743 u_int8_t stop_low, stop_high; 2744 u_int8_t off_low, off_high; 2745 u_int8_t mem_window; 2746 int reg; 2747 2748 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2749 int mem8 = 2750 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2751 || (kind == PCMCIA_MEM_ATTR); 2752 2753 regbase_win = 0x10 + win * 0x08; 2754 2755 phys_addr = ph->mem[win].addr; 2756 phys_end = phys_addr + ph->mem[win].size; 2757 2758 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2759 (unsigned long)phys_addr, (unsigned long)phys_end, 2760 (unsigned long)ph->mem[win].offset)); 2761 2762 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2763 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2764 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2765 2766 /* bit 19:12 */ 2767 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2768 /* bit 23:20 and bit 7 on */ 2769 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2770 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2771 /* bit 31:24, for 32-bit address */ 2772 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2773 2774 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2775 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2776 2777 if (((struct pccbb_softc *)ph-> 2778 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2779 Pcic_write(ph, 0x40 + win, mem_window); 2780 } 2781 2782 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2783 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2784 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2785 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2786 2787 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2788 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2789 2790 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2791 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2792 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2793 | ((kind == PCMCIA_MEM_ATTR) ? 2794 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2795 2796 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2797 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2798 2799 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2800 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2801 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2802 2803 #if defined(CBB_DEBUG) 2804 { 2805 int r1, r2, r3, r4, r5, r6, r7 = 0; 2806 2807 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2808 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2809 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2810 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2811 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2812 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2813 if (((struct pccbb_softc *)(ph-> 2814 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2815 r7 = Pcic_read(ph, 0x40 + win); 2816 } 2817 2818 printf("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2819 "%02x%02x", win, r1, r2, r3, r4, r5, r6); 2820 if (((struct pccbb_softc *)(ph-> 2821 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2822 printf(" %02x", r7); 2823 } 2824 printf("\n"); 2825 } 2826 #endif 2827 } 2828 2829 /* 2830 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2831 * bus_addr_t card_addr, bus_size_t size, 2832 * struct pcmcia_mem_handle *pcmhp, 2833 * bus_addr_t *offsetp, int *windowp) 2834 * 2835 * This function maps memory space allocated by the function 2836 * pccbb_pcmcia_mem_alloc(). 2837 */ 2838 STATIC int 2839 pccbb_pcmcia_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 2840 pcmcia_chipset_handle_t pch; 2841 int kind; 2842 bus_addr_t card_addr; 2843 bus_size_t size; 2844 struct pcmcia_mem_handle *pcmhp; 2845 bus_addr_t *offsetp; 2846 int *windowp; 2847 { 2848 struct pcic_handle *ph = (struct pcic_handle *)pch; 2849 bus_addr_t busaddr; 2850 long card_offset; 2851 int win; 2852 2853 /* Check that the card is still there. */ 2854 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2855 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2856 return 1; 2857 2858 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2859 if ((ph->memalloc & (1 << win)) == 0) { 2860 ph->memalloc |= (1 << win); 2861 break; 2862 } 2863 } 2864 2865 if (win == PCIC_MEM_WINS) { 2866 return 1; 2867 } 2868 2869 *windowp = win; 2870 2871 /* XXX this is pretty gross */ 2872 2873 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2874 panic("pccbb_pcmcia_mem_map memt is bogus"); 2875 } 2876 2877 busaddr = pcmhp->addr; 2878 2879 /* 2880 * compute the address offset to the pcmcia address space for the 2881 * pcic. this is intentionally signed. The masks and shifts below 2882 * will cause TRT to happen in the pcic registers. Deal with making 2883 * sure the address is aligned, and return the alignment offset. 2884 */ 2885 2886 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2887 card_addr -= *offsetp; 2888 2889 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2890 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2891 (u_long) card_addr)); 2892 2893 /* 2894 * include the offset in the size, and decrement size by one, since 2895 * the hw wants start/stop 2896 */ 2897 size += *offsetp - 1; 2898 2899 card_offset = (((long)card_addr) - ((long)busaddr)); 2900 2901 ph->mem[win].addr = busaddr; 2902 ph->mem[win].size = size; 2903 ph->mem[win].offset = card_offset; 2904 ph->mem[win].kind = kind; 2905 2906 pccbb_pcmcia_do_mem_map(ph, win); 2907 2908 return 0; 2909 } 2910 2911 /* 2912 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2913 * int window) 2914 * 2915 * This function unmaps memory space which mapped by the function 2916 * pccbb_pcmcia_mem_map(). 2917 */ 2918 STATIC void 2919 pccbb_pcmcia_mem_unmap(pch, window) 2920 pcmcia_chipset_handle_t pch; 2921 int window; 2922 { 2923 struct pcic_handle *ph = (struct pcic_handle *)pch; 2924 int reg; 2925 2926 if (window >= PCIC_MEM_WINS) { 2927 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2928 } 2929 2930 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2931 reg &= ~(1 << window); 2932 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2933 2934 ph->memalloc &= ~(1 << window); 2935 } 2936 2937 #if defined PCCBB_PCMCIA_POLL 2938 struct pccbb_poll_str { 2939 void *arg; 2940 int (*func)(void *); 2941 int level; 2942 struct pcic_handle *ph; 2943 int count; 2944 int num; 2945 struct callout poll_ch; 2946 }; 2947 2948 static struct pccbb_poll_str pccbb_poll[10]; 2949 static int pccbb_poll_n = 0; 2950 2951 static void pccbb_pcmcia_poll(void *arg); 2952 2953 static void 2954 pccbb_pcmcia_poll(arg) 2955 void *arg; 2956 { 2957 struct pccbb_poll_str *poll = arg; 2958 struct pcic_handle *ph = poll->ph; 2959 struct pccbb_softc *sc = ph->sc; 2960 int s; 2961 u_int32_t spsr; /* socket present-state reg */ 2962 2963 callout_reset(&poll->poll_ch, hz * 2, pccbb_pcmcia_poll, arg); 2964 switch (poll->level) { 2965 case IPL_NET: 2966 s = splnet(); 2967 break; 2968 case IPL_BIO: 2969 s = splbio(); 2970 break; 2971 case IPL_TTY: /* fallthrough */ 2972 default: 2973 s = spltty(); 2974 break; 2975 } 2976 2977 spsr = 2978 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2979 CB_SOCKET_STAT); 2980 2981 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2982 if (!(spsr & 0x40)) /* CINT low */ 2983 #else 2984 if (1) 2985 #endif 2986 { 2987 if ((*poll->func) (poll->arg) > 0) { 2988 ++poll->count; 2989 /* printf("intr: reported from poller, 0x%x\n", spsr); */ 2990 #if defined LEVEL2 2991 } else { 2992 printf("intr: miss! 0x%x\n", spsr); 2993 #endif 2994 } 2995 } 2996 splx(s); 2997 } 2998 #endif /* defined CB_PCMCIA_POLL */ 2999 3000 /* 3001 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 3002 * struct pcmcia_function *pf, 3003 * int ipl, 3004 * int (*func)(void *), 3005 * void *arg); 3006 * 3007 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 3008 */ 3009 STATIC void * 3010 pccbb_pcmcia_intr_establish(pch, pf, ipl, func, arg) 3011 pcmcia_chipset_handle_t pch; 3012 struct pcmcia_function *pf; 3013 int ipl; 3014 int (*func)(void *); 3015 void *arg; 3016 { 3017 struct pcic_handle *ph = (struct pcic_handle *)pch; 3018 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 3019 3020 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 3021 /* what should I do? */ 3022 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 3023 DPRINTF(("%s does not provide edge nor pulse " 3024 "interrupt\n", sc->sc_dev.dv_xname)); 3025 return NULL; 3026 } 3027 /* 3028 * XXX Noooooo! The interrupt flag must set properly!! 3029 * dumb pcmcia driver!! 3030 */ 3031 } 3032 3033 return pccbb_intr_establish(sc, 0, ipl, func, arg); 3034 } 3035 3036 /* 3037 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 3038 * void *ih) 3039 * 3040 * This function disables PC-Card interrupt. 3041 */ 3042 STATIC void 3043 pccbb_pcmcia_intr_disestablish(pch, ih) 3044 pcmcia_chipset_handle_t pch; 3045 void *ih; 3046 { 3047 struct pcic_handle *ph = (struct pcic_handle *)pch; 3048 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 3049 3050 pccbb_intr_disestablish(sc, ih); 3051 } 3052 3053 #if rbus 3054 /* 3055 * static int 3056 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 3057 * bus_addr_t addr, bus_size_t size, 3058 * bus_addr_t mask, bus_size_t align, 3059 * int flags, bus_addr_t *addrp; 3060 * bus_space_handle_t *bshp) 3061 * 3062 * This function allocates a portion of memory or io space for 3063 * clients. This function is called from CardBus card drivers. 3064 */ 3065 static int 3066 pccbb_rbus_cb_space_alloc(ct, rb, addr, size, mask, align, flags, addrp, bshp) 3067 cardbus_chipset_tag_t ct; 3068 rbus_tag_t rb; 3069 bus_addr_t addr; 3070 bus_size_t size; 3071 bus_addr_t mask; 3072 bus_size_t align; 3073 int flags; 3074 bus_addr_t *addrp; 3075 bus_space_handle_t *bshp; 3076 { 3077 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 3078 3079 DPRINTF(("pccbb_rbus_cb_space_alloc: addr 0x%lx, size 0x%lx, " 3080 "mask 0x%lx, align 0x%lx\n", (unsigned long)addr, 3081 (unsigned long)size, (unsigned long)mask, (unsigned long)align)); 3082 3083 if (align == 0) { 3084 align = size; 3085 } 3086 3087 if (rb->rb_bt == sc->sc_memt) { 3088 if (align < 16) { 3089 return 1; 3090 } 3091 /* 3092 * XXX: align more than 0x1000 to avoid overwrapping 3093 * memory windows for two or more devices. 0x1000 3094 * means memory window's granularity. 3095 * 3096 * Two or more devices should be able to share same 3097 * memory window region. However, overrapping memory 3098 * window is not good because some devices, such as 3099 * 3Com 3C575[BC], have a broken address decoder and 3100 * intrude other's memory region. 3101 */ 3102 if (align < 0x1000) { 3103 align = 0x1000; 3104 } 3105 } else if (rb->rb_bt == sc->sc_iot) { 3106 if (align < 4) { 3107 return 1; 3108 } 3109 /* XXX: hack for avoiding ISA image */ 3110 if (mask < 0x0100) { 3111 mask = 0x3ff; 3112 addr = 0x300; 3113 } 3114 3115 } else { 3116 DPRINTF(("pccbb_rbus_cb_space_alloc: Bus space tag 0x%lx is " 3117 "NOT used. io: 0x%lx, mem: 0x%lx\n", 3118 (unsigned long)rb->rb_bt, (unsigned long)sc->sc_iot, 3119 (unsigned long)sc->sc_memt)); 3120 return 1; 3121 /* XXX: panic here? */ 3122 } 3123 3124 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 3125 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 3126 return 1; 3127 } 3128 3129 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 3130 3131 return 0; 3132 } 3133 3134 /* 3135 * static int 3136 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 3137 * bus_space_handle_t *bshp, bus_size_t size); 3138 * 3139 * This function is called from CardBus card drivers. 3140 */ 3141 static int 3142 pccbb_rbus_cb_space_free(ct, rb, bsh, size) 3143 cardbus_chipset_tag_t ct; 3144 rbus_tag_t rb; 3145 bus_space_handle_t bsh; 3146 bus_size_t size; 3147 { 3148 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 3149 bus_space_tag_t bt = rb->rb_bt; 3150 3151 pccbb_close_win(sc, bt, bsh, size); 3152 3153 if (bt == sc->sc_memt) { 3154 } else if (bt == sc->sc_iot) { 3155 } else { 3156 return 1; 3157 /* XXX: panic here? */ 3158 } 3159 3160 return rbus_space_free(rb, bsh, size, NULL); 3161 } 3162 #endif /* rbus */ 3163 3164 #if rbus 3165 3166 static int 3167 pccbb_open_win(sc, bst, addr, size, bsh, flags) 3168 struct pccbb_softc *sc; 3169 bus_space_tag_t bst; 3170 bus_addr_t addr; 3171 bus_size_t size; 3172 bus_space_handle_t bsh; 3173 int flags; 3174 { 3175 struct pccbb_win_chain_head *head; 3176 bus_addr_t align; 3177 3178 head = &sc->sc_iowindow; 3179 align = 0x04; 3180 if (sc->sc_memt == bst) { 3181 head = &sc->sc_memwindow; 3182 align = 0x1000; 3183 DPRINTF(("using memory window, 0x%lx 0x%lx 0x%lx\n\n", 3184 (unsigned long)sc->sc_iot, (unsigned long)sc->sc_memt, 3185 (unsigned long)bst)); 3186 } 3187 3188 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 3189 printf("%s: pccbb_open_win: %s winlist insert failed\n", 3190 sc->sc_dev.dv_xname, 3191 (head == &sc->sc_memwindow) ? "mem" : "io"); 3192 } 3193 pccbb_winset(align, sc, bst); 3194 3195 return 0; 3196 } 3197 3198 static int 3199 pccbb_close_win(sc, bst, bsh, size) 3200 struct pccbb_softc *sc; 3201 bus_space_tag_t bst; 3202 bus_space_handle_t bsh; 3203 bus_size_t size; 3204 { 3205 struct pccbb_win_chain_head *head; 3206 bus_addr_t align; 3207 3208 head = &sc->sc_iowindow; 3209 align = 0x04; 3210 if (sc->sc_memt == bst) { 3211 head = &sc->sc_memwindow; 3212 align = 0x1000; 3213 } 3214 3215 if (pccbb_winlist_delete(head, bsh, size)) { 3216 printf("%s: pccbb_close_win: %s winlist delete failed\n", 3217 sc->sc_dev.dv_xname, 3218 (head == &sc->sc_memwindow) ? "mem" : "io"); 3219 } 3220 pccbb_winset(align, sc, bst); 3221 3222 return 0; 3223 } 3224 3225 static int 3226 pccbb_winlist_insert(head, start, size, bsh, flags) 3227 struct pccbb_win_chain_head *head; 3228 bus_addr_t start; 3229 bus_size_t size; 3230 bus_space_handle_t bsh; 3231 int flags; 3232 { 3233 struct pccbb_win_chain *chainp, *elem; 3234 3235 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 3236 M_NOWAIT)) == NULL) 3237 return (1); /* fail */ 3238 3239 elem->wc_start = start; 3240 elem->wc_end = start + (size - 1); 3241 elem->wc_handle = bsh; 3242 elem->wc_flags = flags; 3243 3244 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3245 chainp = TAILQ_NEXT(chainp, wc_list)) { 3246 if (chainp->wc_end < start) 3247 continue; 3248 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 3249 return (0); 3250 } 3251 3252 TAILQ_INSERT_TAIL(head, elem, wc_list); 3253 return (0); 3254 } 3255 3256 static int 3257 pccbb_winlist_delete(head, bsh, size) 3258 struct pccbb_win_chain_head *head; 3259 bus_space_handle_t bsh; 3260 bus_size_t size; 3261 { 3262 struct pccbb_win_chain *chainp; 3263 3264 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3265 chainp = TAILQ_NEXT(chainp, wc_list)) { 3266 if (memcmp(&chainp->wc_handle, &bsh, sizeof(bsh))) 3267 continue; 3268 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 3269 printf("pccbb_winlist_delete: window 0x%lx size " 3270 "inconsistent: 0x%lx, 0x%lx\n", 3271 (unsigned long)chainp->wc_start, 3272 (unsigned long)(chainp->wc_end - chainp->wc_start), 3273 (unsigned long)(size - 1)); 3274 return 1; 3275 } 3276 3277 TAILQ_REMOVE(head, chainp, wc_list); 3278 free(chainp, M_DEVBUF); 3279 3280 return 0; 3281 } 3282 3283 return 1; /* fail: no candidate to remove */ 3284 } 3285 3286 static void 3287 pccbb_winset(align, sc, bst) 3288 bus_addr_t align; 3289 struct pccbb_softc *sc; 3290 bus_space_tag_t bst; 3291 { 3292 pci_chipset_tag_t pc; 3293 pcitag_t tag; 3294 bus_addr_t mask = ~(align - 1); 3295 struct { 3296 cardbusreg_t win_start; 3297 cardbusreg_t win_limit; 3298 int win_flags; 3299 } win[2]; 3300 struct pccbb_win_chain *chainp; 3301 int offs; 3302 3303 win[0].win_start = win[1].win_start = 0xffffffff; 3304 win[0].win_limit = win[1].win_limit = 0; 3305 win[0].win_flags = win[1].win_flags = 0; 3306 3307 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3308 offs = 0x2c; 3309 if (sc->sc_memt == bst) { 3310 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3311 offs = 0x1c; 3312 } 3313 3314 if (chainp != NULL) { 3315 win[0].win_start = chainp->wc_start & mask; 3316 win[0].win_limit = chainp->wc_end & mask; 3317 win[0].win_flags = chainp->wc_flags; 3318 chainp = TAILQ_NEXT(chainp, wc_list); 3319 } 3320 3321 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3322 if (win[1].win_start == 0xffffffff) { 3323 /* window 1 is not used */ 3324 if ((win[0].win_flags == chainp->wc_flags) && 3325 (win[0].win_limit + align >= 3326 (chainp->wc_start & mask))) { 3327 /* concatenate */ 3328 win[0].win_limit = chainp->wc_end & mask; 3329 } else { 3330 /* make new window */ 3331 win[1].win_start = chainp->wc_start & mask; 3332 win[1].win_limit = chainp->wc_end & mask; 3333 win[1].win_flags = chainp->wc_flags; 3334 } 3335 continue; 3336 } 3337 3338 /* Both windows are engaged. */ 3339 if (win[0].win_flags == win[1].win_flags) { 3340 /* same flags */ 3341 if (win[0].win_flags == chainp->wc_flags) { 3342 if (win[1].win_start - (win[0].win_limit + 3343 align) < 3344 (chainp->wc_start & mask) - 3345 ((chainp->wc_end & mask) + align)) { 3346 /* 3347 * merge window 0 and 1, and set win1 3348 * to chainp 3349 */ 3350 win[0].win_limit = win[1].win_limit; 3351 win[1].win_start = 3352 chainp->wc_start & mask; 3353 win[1].win_limit = 3354 chainp->wc_end & mask; 3355 } else { 3356 win[1].win_limit = 3357 chainp->wc_end & mask; 3358 } 3359 } else { 3360 /* different flags */ 3361 3362 /* concatenate win0 and win1 */ 3363 win[0].win_limit = win[1].win_limit; 3364 /* allocate win[1] to new space */ 3365 win[1].win_start = chainp->wc_start & mask; 3366 win[1].win_limit = chainp->wc_end & mask; 3367 win[1].win_flags = chainp->wc_flags; 3368 } 3369 } else { 3370 /* the flags of win[0] and win[1] is different */ 3371 if (win[0].win_flags == chainp->wc_flags) { 3372 win[0].win_limit = chainp->wc_end & mask; 3373 /* 3374 * XXX this creates overlapping windows, so 3375 * what should the poor bridge do if one is 3376 * cachable, and the other is not? 3377 */ 3378 printf("%s: overlapping windows\n", 3379 sc->sc_dev.dv_xname); 3380 } else { 3381 win[1].win_limit = chainp->wc_end & mask; 3382 } 3383 } 3384 } 3385 3386 pc = sc->sc_pc; 3387 tag = sc->sc_tag; 3388 pci_conf_write(pc, tag, offs, win[0].win_start); 3389 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3390 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3391 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3392 DPRINTF(("--pccbb_winset: win0 [0x%lx, 0x%lx), win1 [0x%lx, 0x%lx)\n", 3393 (unsigned long)pci_conf_read(pc, tag, offs), 3394 (unsigned long)pci_conf_read(pc, tag, offs + 4) + align, 3395 (unsigned long)pci_conf_read(pc, tag, offs + 8), 3396 (unsigned long)pci_conf_read(pc, tag, offs + 12) + align)); 3397 3398 if (bst == sc->sc_memt) { 3399 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3400 3401 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 3402 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 3403 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3404 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 3405 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3406 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3407 } 3408 } 3409 3410 #endif /* rbus */ 3411 3412 static void 3413 pccbb_powerhook(why, arg) 3414 int why; 3415 void *arg; 3416 { 3417 struct pccbb_softc *sc = arg; 3418 pcireg_t reg; 3419 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3420 bus_space_handle_t base_memh = sc->sc_base_memh; 3421 3422 DPRINTF(("%s: power: why %d\n", sc->sc_dev.dv_xname, why)); 3423 3424 if (why == PWR_SUSPEND || why == PWR_STANDBY) { 3425 DPRINTF(("%s: power: why %d stopping intr\n", 3426 sc->sc_dev.dv_xname, why)); 3427 if (sc->sc_pil_intr_enable) { 3428 (void)pccbbintr_function(sc); 3429 } 3430 sc->sc_pil_intr_enable = 0; 3431 3432 pci_conf_capture(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf); 3433 3434 if (sc->sc_chipset == CB_RX5C47X) 3435 sc->sc_ricoh_misc_ctrl = pci_conf_read(sc->sc_pc, 3436 sc->sc_tag, 3437 RICOH_PCI_MISC_CTRL); 3438 3439 /* ToDo: deactivate or suspend child devices */ 3440 } 3441 3442 if (why == PWR_RESUME) { 3443 if (sc->sc_pwrmgt_offs != 0) { 3444 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, 3445 sc->sc_pwrmgt_offs + 4); 3446 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 3447 reg & 0x100) { 3448 /* powrstate != D0 */ 3449 3450 printf("%s going back to D0 mode\n", 3451 sc->sc_dev.dv_xname); 3452 reg &= ~PCI_PMCSR_STATE_MASK; 3453 reg |= PCI_PMCSR_STATE_D0; 3454 reg &= ~(0x100 /* PCI_PMCSR_PME_EN */); 3455 pci_conf_write(sc->sc_pc, sc->sc_tag, 3456 sc->sc_pwrmgt_offs + 4, reg); 3457 3458 pci_conf_write(sc->sc_pc, sc->sc_tag, 3459 PCI_SOCKBASE, sc->sc_sockbase); 3460 pci_conf_write(sc->sc_pc, sc->sc_tag, 3461 PCI_BUSNUM, sc->sc_busnum); 3462 pccbb_chipinit(sc); 3463 /* setup memory and io space window for CB */ 3464 pccbb_winset(0x1000, sc, sc->sc_memt); 3465 pccbb_winset(0x04, sc, sc->sc_iot); 3466 goto norestore; 3467 } 3468 } 3469 3470 norestore: 3471 pci_conf_restore(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf); 3472 if (sc->sc_chipset == CB_RX5C47X) { 3473 pci_conf_write(sc->sc_pc, sc->sc_tag, 3474 RICOH_PCI_MISC_CTRL, sc->sc_ricoh_misc_ctrl); 3475 } 3476 3477 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_SOCKBASE) == 0) 3478 /* BIOS did not recover this register */ 3479 pci_conf_write (sc->sc_pc, sc->sc_tag, 3480 PCI_SOCKBASE, sc->sc_sockbase); 3481 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_BUSNUM) == 0) 3482 /* BIOS did not recover this register */ 3483 pci_conf_write (sc->sc_pc, sc->sc_tag, 3484 PCI_BUSNUM, sc->sc_busnum); 3485 /* CSC Interrupt: Card detect interrupt on */ 3486 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3487 /* Card detect intr is turned on. */ 3488 reg |= CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; 3489 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3490 /* reset interrupt */ 3491 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3492 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3493 3494 /* 3495 * check for card insertion or removal during suspend period. 3496 * XXX: the code can't cope with card swap (remove then 3497 * insert). how can we detect such situation? 3498 */ 3499 (void)pccbbintr(sc); 3500 3501 sc->sc_pil_intr_enable = 1; 3502 DPRINTF(("%s: power: RESUME enabling intr\n", 3503 sc->sc_dev.dv_xname)); 3504 3505 /* ToDo: activate or wakeup child devices */ 3506 } 3507 } 3508
Indexes created Fri Sep 26 20:09:58 GMT 2025