pccbb.c revision 1.136
1 /* $NetBSD: pccbb.c,v 1.136 2006/10/24 14:16:39 itohy Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: pccbb.c,v 1.136 2006/10/24 14:16:39 itohy Exp $"); 35 36 /* 37 #define CBB_DEBUG 38 #define SHOW_REGS 39 */ 40 41 /* 42 * BROKEN! 43 #define PCCBB_PCMCIA_POLL 44 #define CB_PCMCIA_POLL 45 #define CB_PCMCIA_POLL_ONLY 46 #define LEVEL2 47 */ 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/kernel.h> 52 #include <sys/errno.h> 53 #include <sys/ioctl.h> 54 #include <sys/reboot.h> /* for bootverbose */ 55 #include <sys/syslog.h> 56 #include <sys/device.h> 57 #include <sys/malloc.h> 58 #include <sys/proc.h> 59 60 #include <machine/intr.h> 61 #include <machine/bus.h> 62 63 #include <dev/pci/pcivar.h> 64 #include <dev/pci/pcireg.h> 65 #include <dev/pci/pcidevs.h> 66 67 #include <dev/pci/pccbbreg.h> 68 69 #include <dev/cardbus/cardslotvar.h> 70 71 #include <dev/cardbus/cardbusvar.h> 72 73 #include <dev/pcmcia/pcmciareg.h> 74 #include <dev/pcmcia/pcmciavar.h> 75 76 #include <dev/ic/i82365reg.h> 77 #include <dev/ic/i82365var.h> 78 #include <dev/pci/pccbbvar.h> 79 80 #include "locators.h" 81 82 #if defined(__i386__) 83 #include "ioapic.h" 84 #include "acpi.h" 85 #endif 86 87 #ifndef __NetBSD_Version__ 88 struct cfdriver cbb_cd = { 89 NULL, "cbb", DV_DULL 90 }; 91 #endif 92 93 #ifdef CBB_DEBUG 94 #define DPRINTF(x) printf x 95 #define STATIC 96 #else 97 #define DPRINTF(x) 98 #define STATIC static 99 #endif 100 101 /* 102 * DELAY_MS() is a wait millisecond. It shall use instead of delay() 103 * if you want to wait more than 1 ms. 104 */ 105 #define DELAY_MS(time, param) \ 106 do { \ 107 if (cold == 0) { \ 108 int xtick = (hz*(time))/1000; \ 109 \ 110 if (xtick <= 1) { \ 111 xtick = 2; \ 112 } \ 113 tsleep((void *)(param), PWAIT, "pccbb", xtick); \ 114 } else { \ 115 delay((time)*1000); \ 116 } \ 117 } while (/*CONSTCOND*/0) 118 119 int pcicbbmatch(struct device *, struct cfdata *, void *); 120 void pccbbattach(struct device *, struct device *, void *); 121 int pccbbintr(void *); 122 static void pci113x_insert(void *); 123 static int pccbbintr_function(struct pccbb_softc *); 124 125 static int pccbb_detect_card(struct pccbb_softc *); 126 127 static void pccbb_pcmcia_write(struct pcic_handle *, int, u_int8_t); 128 static u_int8_t pccbb_pcmcia_read(struct pcic_handle *, int); 129 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 130 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 131 132 STATIC int cb_reset(struct pccbb_softc *); 133 STATIC int cb_detect_voltage(struct pccbb_softc *); 134 STATIC int cbbprint(void *, const char *); 135 136 static int cb_chipset(u_int32_t, int *); 137 STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *, 138 struct pcmciabus_attach_args *); 139 #if 0 140 STATIC void pccbb_pcmcia_attach_card(struct pcic_handle *); 141 STATIC void pccbb_pcmcia_detach_card(struct pcic_handle *, int); 142 STATIC void pccbb_pcmcia_deactivate_card(struct pcic_handle *); 143 #endif 144 145 STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int); 146 STATIC int pccbb_power(cardbus_chipset_tag_t, int); 147 STATIC int pccbb_cardenable(struct pccbb_softc * sc, int function); 148 #if !rbus 149 static int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 150 static int pccbb_io_close(cardbus_chipset_tag_t, int); 151 static int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 152 static int pccbb_mem_close(cardbus_chipset_tag_t, int); 153 #endif /* !rbus */ 154 static void *pccbb_intr_establish(struct pccbb_softc *, int irq, 155 int level, int (*ih) (void *), void *sc); 156 static void pccbb_intr_disestablish(struct pccbb_softc *, void *ih); 157 158 static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t, int irq, 159 int level, int (*ih) (void *), void *sc); 160 static void pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih); 161 162 static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t, int, int); 163 static void pccbb_free_tag(cardbus_chipset_tag_t, cardbustag_t); 164 static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t, cardbustag_t, int); 165 static void pccbb_conf_write(cardbus_chipset_tag_t, cardbustag_t, int, 166 cardbusreg_t); 167 static void pccbb_chipinit(struct pccbb_softc *); 168 169 STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 170 struct pcmcia_mem_handle *); 171 STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t, 172 struct pcmcia_mem_handle *); 173 STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 174 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *); 175 STATIC void pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t, int); 176 STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 177 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 178 STATIC void pccbb_pcmcia_io_free(pcmcia_chipset_handle_t, 179 struct pcmcia_io_handle *); 180 STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 181 bus_size_t, struct pcmcia_io_handle *, int *); 182 STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t, int); 183 STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t, 184 struct pcmcia_function *, int, int (*)(void *), void *); 185 STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t, void *); 186 STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t); 187 STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t); 188 STATIC void pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t, int); 189 STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch); 190 191 static int pccbb_pcmcia_wait_ready(struct pcic_handle *); 192 static void pccbb_pcmcia_delay(struct pcic_handle *, int, const char *); 193 194 static void pccbb_pcmcia_do_io_map(struct pcic_handle *, int); 195 static void pccbb_pcmcia_do_mem_map(struct pcic_handle *, int); 196 static void pccbb_powerhook(int, void *); 197 198 /* bus-space allocation and deallocation functions */ 199 #if rbus 200 201 static int pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t, rbus_tag_t, 202 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 203 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp); 204 static int pccbb_rbus_cb_space_free(cardbus_chipset_tag_t, rbus_tag_t, 205 bus_space_handle_t, bus_size_t); 206 207 #endif /* rbus */ 208 209 #if rbus 210 211 static int pccbb_open_win(struct pccbb_softc *, bus_space_tag_t, 212 bus_addr_t, bus_size_t, bus_space_handle_t, int flags); 213 static int pccbb_close_win(struct pccbb_softc *, bus_space_tag_t, 214 bus_space_handle_t, bus_size_t); 215 static int pccbb_winlist_insert(struct pccbb_win_chain_head *, bus_addr_t, 216 bus_size_t, bus_space_handle_t, int); 217 static int pccbb_winlist_delete(struct pccbb_win_chain_head *, 218 bus_space_handle_t, bus_size_t); 219 static void pccbb_winset(bus_addr_t align, struct pccbb_softc *, 220 bus_space_tag_t); 221 void pccbb_winlist_show(struct pccbb_win_chain *); 222 223 #endif /* rbus */ 224 225 /* for config_defer */ 226 static void pccbb_pci_callback(struct device *); 227 228 #if defined SHOW_REGS 229 static void cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, 230 bus_space_tag_t memt, bus_space_handle_t memh); 231 #endif 232 233 CFATTACH_DECL(cbb_pci, sizeof(struct pccbb_softc), 234 pcicbbmatch, pccbbattach, NULL, NULL); 235 236 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 237 pccbb_pcmcia_mem_alloc, 238 pccbb_pcmcia_mem_free, 239 pccbb_pcmcia_mem_map, 240 pccbb_pcmcia_mem_unmap, 241 pccbb_pcmcia_io_alloc, 242 pccbb_pcmcia_io_free, 243 pccbb_pcmcia_io_map, 244 pccbb_pcmcia_io_unmap, 245 pccbb_pcmcia_intr_establish, 246 pccbb_pcmcia_intr_disestablish, 247 pccbb_pcmcia_socket_enable, 248 pccbb_pcmcia_socket_disable, 249 pccbb_pcmcia_socket_settype, 250 pccbb_pcmcia_card_detect 251 }; 252 253 #if rbus 254 static struct cardbus_functions pccbb_funcs = { 255 pccbb_rbus_cb_space_alloc, 256 pccbb_rbus_cb_space_free, 257 pccbb_cb_intr_establish, 258 pccbb_cb_intr_disestablish, 259 pccbb_ctrl, 260 pccbb_power, 261 pccbb_make_tag, 262 pccbb_free_tag, 263 pccbb_conf_read, 264 pccbb_conf_write, 265 }; 266 #else 267 static struct cardbus_functions pccbb_funcs = { 268 pccbb_ctrl, 269 pccbb_power, 270 pccbb_mem_open, 271 pccbb_mem_close, 272 pccbb_io_open, 273 pccbb_io_close, 274 pccbb_cb_intr_establish, 275 pccbb_cb_intr_disestablish, 276 pccbb_make_tag, 277 pccbb_conf_read, 278 pccbb_conf_write, 279 }; 280 #endif 281 282 int 283 pcicbbmatch(struct device *parent __unused, struct cfdata *match __unused, 284 void *aux) 285 { 286 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 287 288 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 289 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 290 PCI_INTERFACE(pa->pa_class) == 0) { 291 return 1; 292 } 293 294 return 0; 295 } 296 297 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 298 | ((prod) << PCI_PRODUCT_SHIFT)) 299 300 const struct yenta_chipinfo { 301 pcireg_t yc_id; /* vendor tag | product tag */ 302 int yc_chiptype; 303 int yc_flags; 304 } yc_chipsets[] = { 305 /* Texas Instruments chips */ 306 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 307 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 308 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 309 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 310 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI125X, 311 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 312 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 313 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 314 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 315 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 316 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 317 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 318 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI125X, 319 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 320 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI125X, 321 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 322 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 323 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 324 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 325 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 326 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 327 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 328 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI125X, 329 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 330 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 331 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 332 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1520), CB_TI12XX, 333 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 334 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4410YENTA), CB_TI12XX, 335 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 336 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4520YENTA), CB_TI12XX, 337 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 338 339 /* Ricoh chips */ 340 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 341 PCCBB_PCMCIA_MEM_32}, 342 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 343 PCCBB_PCMCIA_MEM_32}, 344 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 345 PCCBB_PCMCIA_MEM_32}, 346 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 347 PCCBB_PCMCIA_MEM_32}, 348 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 349 PCCBB_PCMCIA_MEM_32}, 350 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 351 PCCBB_PCMCIA_MEM_32}, 352 353 /* Toshiba products */ 354 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 355 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 356 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 357 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 358 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 359 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 360 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 361 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 362 363 /* Cirrus Logic products */ 364 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 365 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 366 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 367 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 368 369 /* sentinel, or Generic chip */ 370 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 371 }; 372 373 static int 374 cb_chipset(pci_id, flagp) 375 u_int32_t pci_id; 376 int *flagp; 377 { 378 const struct yenta_chipinfo *yc; 379 380 /* Loop over except the last default entry. */ 381 for (yc = yc_chipsets; yc < yc_chipsets + 382 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 383 if (pci_id == yc->yc_id) 384 break; 385 386 if (flagp != NULL) 387 *flagp = yc->yc_flags; 388 389 return (yc->yc_chiptype); 390 } 391 392 static void 393 pccbb_shutdown(void *arg) 394 { 395 struct pccbb_softc *sc = arg; 396 pcireg_t command; 397 398 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 399 400 /* 401 * turn off power 402 * 403 * XXX - do not turn off power if chipset is TI 113X because 404 * only TI 1130 with PowerMac 2400 hangs in pccbb_power(). 405 */ 406 if (sc->sc_chipset != CB_TI113X) { 407 pccbb_power((cardbus_chipset_tag_t)sc, 408 CARDBUS_VCC_0V | CARDBUS_VPP_0V); 409 } 410 411 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 412 0); 413 414 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 415 416 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 417 PCI_COMMAND_MASTER_ENABLE); 418 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 419 420 } 421 422 void 423 pccbbattach(struct device *parent __unused, struct device *self, void *aux) 424 { 425 struct pccbb_softc *sc = (void *)self; 426 struct pci_attach_args *pa = aux; 427 pci_chipset_tag_t pc = pa->pa_pc; 428 pcireg_t busreg, reg, sock_base; 429 bus_addr_t sockbase; 430 char devinfo[256]; 431 int flags; 432 int pwrmgt_offs; 433 434 #ifdef __HAVE_PCCBB_ATTACH_HOOK 435 pccbb_attach_hook(parent, self, pa); 436 #endif 437 438 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 439 440 pci_devinfo(pa->pa_id, 0, 0, devinfo, sizeof(devinfo)); 441 printf(": %s (rev. 0x%02x)", devinfo, PCI_REVISION(pa->pa_class)); 442 DPRINTF((" (chipflags %x)", flags)); 443 printf("\n"); 444 445 TAILQ_INIT(&sc->sc_memwindow); 446 TAILQ_INIT(&sc->sc_iowindow); 447 448 #if rbus 449 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 450 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 451 452 #if 0 453 printf("pa->pa_memt: %08x vs rbus_mem->rb_bt: %08x\n", 454 pa->pa_memt, sc->sc_rbus_memt->rb_bt); 455 #endif 456 #endif /* rbus */ 457 458 sc->sc_flags &= ~CBB_MEMHMAPPED; 459 460 /* power management: set D0 state */ 461 sc->sc_pwrmgt_offs = 0; 462 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, 463 &pwrmgt_offs, 0)) { 464 reg = pci_conf_read(pc, pa->pa_tag, pwrmgt_offs + PCI_PMCSR); 465 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 466 reg & 0x100 /* PCI_PMCSR_PME_EN */) { 467 reg &= ~PCI_PMCSR_STATE_MASK; 468 reg |= PCI_PMCSR_STATE_D0; 469 reg &= ~(0x100 /* PCI_PMCSR_PME_EN */); 470 pci_conf_write(pc, pa->pa_tag, 471 pwrmgt_offs + PCI_PMCSR, reg); 472 } 473 474 sc->sc_pwrmgt_offs = pwrmgt_offs; 475 } 476 477 /* 478 * MAP socket registers and ExCA registers on memory-space 479 * When no valid address is set on socket base registers (on pci 480 * config space), get it not polite way. 481 */ 482 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 483 484 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 485 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 486 /* The address must be valid. */ 487 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 488 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL)) { 489 printf("%s: can't map socket base address 0x%lx\n", 490 sc->sc_dev.dv_xname, (unsigned long)sock_base); 491 /* 492 * I think it's funny: socket base registers must be 493 * mapped on memory space, but ... 494 */ 495 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 496 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 497 NULL)) { 498 printf("%s: can't map socket base address" 499 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 500 (unsigned long)sockbase); 501 /* give up... allocate reg space via rbus. */ 502 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 503 } else 504 sc->sc_flags |= CBB_MEMHMAPPED; 505 } else { 506 DPRINTF(("%s: socket base address 0x%lx\n", 507 sc->sc_dev.dv_xname, (unsigned long)sockbase)); 508 sc->sc_flags |= CBB_MEMHMAPPED; 509 } 510 } 511 512 sc->sc_mem_start = 0; /* XXX */ 513 sc->sc_mem_end = 0xffffffff; /* XXX */ 514 515 /* 516 * When interrupt isn't routed correctly, give up probing cbb and do 517 * not kill pcic-compatible port. 518 * 519 * However, if we are using an ioapic, avoid this check -- pa_intrline 520 * may well be zero, with the interrupt routed through the apic. 521 */ 522 523 #if NIOAPIC == 0 && NACPI == 0 524 if ((0 == pa->pa_intrline) || (255 == pa->pa_intrline)) { 525 printf("%s: NOT USED because of unconfigured interrupt\n", 526 sc->sc_dev.dv_xname); 527 return; 528 } 529 #endif 530 531 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 532 533 /* pccbb_machdep.c end */ 534 535 #if defined CBB_DEBUG 536 { 537 static const char *intrname[] = { "NON", "A", "B", "C", "D" }; 538 printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname, 539 intrname[pa->pa_intrpin], pa->pa_intrline); 540 } 541 #endif 542 543 /* setup softc */ 544 sc->sc_pc = pc; 545 sc->sc_iot = pa->pa_iot; 546 sc->sc_memt = pa->pa_memt; 547 sc->sc_dmat = pa->pa_dmat; 548 sc->sc_tag = pa->pa_tag; 549 sc->sc_function = pa->pa_function; 550 sc->sc_sockbase = sock_base; 551 sc->sc_busnum = busreg; 552 553 memcpy(&sc->sc_pa, pa, sizeof(*pa)); 554 555 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 556 557 shutdownhook_establish(pccbb_shutdown, sc); 558 559 /* Disable legacy register mapping. */ 560 switch (sc->sc_chipset) { 561 case CB_RX5C46X: /* fallthrough */ 562 #if 0 563 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 564 case CB_RX5C47X: 565 #endif 566 /* 567 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 568 * cannot be disabled by substituting 0 into PCI_LEGACY 569 * register. Ricoh CardBus bridges have special bits on Bridge 570 * control reg (addr 0x3e on PCI config space). 571 */ 572 reg = pci_conf_read(pc, pa->pa_tag, PCI_BCR_INTR); 573 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 574 pci_conf_write(pc, pa->pa_tag, PCI_BCR_INTR, reg); 575 break; 576 577 default: 578 /* XXX I don't know proper way to kill legacy I/O. */ 579 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 580 break; 581 } 582 583 config_defer(self, pccbb_pci_callback); 584 } 585 586 587 588 589 /* 590 * static void pccbb_pci_callback(struct device *self) 591 * 592 * The actual attach routine: get memory space for YENTA register 593 * space, setup YENTA register and route interrupt. 594 * 595 * This function should be deferred because this device may obtain 596 * memory space dynamically. This function must avoid obtaining 597 * memory area which has already kept for another device. 598 */ 599 static void 600 pccbb_pci_callback(self) 601 struct device *self; 602 { 603 struct pccbb_softc *sc = (void *)self; 604 pci_chipset_tag_t pc = sc->sc_pc; 605 pci_intr_handle_t ih; 606 const char *intrstr = NULL; 607 bus_addr_t sockbase; 608 struct cbslot_attach_args cba; 609 struct pcmciabus_attach_args paa; 610 struct cardslot_attach_args caa; 611 struct cardslot_softc *csc; 612 613 if (!(sc->sc_flags & CBB_MEMHMAPPED)) { 614 /* The socket registers aren't mapped correctly. */ 615 #if rbus 616 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 617 (sc->sc_chipset == CB_RX5C47X 618 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 619 0, &sockbase, &sc->sc_base_memh)) { 620 return; 621 } 622 sc->sc_base_memt = sc->sc_memt; 623 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 624 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 625 sc->sc_dev.dv_xname, (unsigned long)sockbase, 626 (unsigned long)pci_conf_read(pc, sc->sc_tag, 627 PCI_SOCKBASE))); 628 #else 629 sc->sc_base_memt = sc->sc_memt; 630 #if !defined CBB_PCI_BASE 631 #define CBB_PCI_BASE 0x20000000 632 #endif 633 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 634 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 635 /* cannot allocate memory space */ 636 return; 637 } 638 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 639 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 640 sc->sc_dev.dv_xname, (unsigned long)sock_base, 641 (unsigned long)pci_conf_read(pc, 642 sc->sc_tag, PCI_SOCKBASE))); 643 sc->sc_sockbase = sockbase; 644 #endif 645 sc->sc_flags |= CBB_MEMHMAPPED; 646 } 647 648 /* bus bridge initialization */ 649 pccbb_chipinit(sc); 650 651 /* clear data structure for child device interrupt handlers */ 652 LIST_INIT(&sc->sc_pil); 653 sc->sc_pil_intr_enable = 1; 654 655 /* Map and establish the interrupt. */ 656 if (pci_intr_map(&sc->sc_pa, &ih)) { 657 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 658 return; 659 } 660 intrstr = pci_intr_string(pc, ih); 661 662 /* 663 * XXX pccbbintr should be called under the priority lower 664 * than any other hard interupts. 665 */ 666 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 667 668 if (sc->sc_ih == NULL) { 669 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 670 if (intrstr != NULL) { 671 printf(" at %s", intrstr); 672 } 673 printf("\n"); 674 return; 675 } 676 677 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 678 powerhook_establish(sc->sc_dev.dv_xname, pccbb_powerhook, sc); 679 680 { 681 u_int32_t sockstat; 682 683 sockstat = bus_space_read_4(sc->sc_base_memt, 684 sc->sc_base_memh, CB_SOCKET_STAT); 685 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 686 sc->sc_flags |= CBB_CARDEXIST; 687 } 688 } 689 690 /* 691 * attach cardbus 692 */ 693 { 694 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 695 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 696 697 /* initialize cbslot_attach */ 698 cba.cba_busname = "cardbus"; 699 cba.cba_iot = sc->sc_iot; 700 cba.cba_memt = sc->sc_memt; 701 cba.cba_dmat = sc->sc_dmat; 702 cba.cba_bus = (busreg >> 8) & 0x0ff; 703 cba.cba_cc = (void *)sc; 704 cba.cba_cf = &pccbb_funcs; 705 cba.cba_intrline = sc->sc_pa.pa_intrline; 706 707 #if rbus 708 cba.cba_rbus_iot = sc->sc_rbus_iot; 709 cba.cba_rbus_memt = sc->sc_rbus_memt; 710 #endif 711 712 cba.cba_cacheline = PCI_CACHELINE(bhlc); 713 cba.cba_lattimer = PCI_CB_LATENCY(busreg); 714 715 if (bootverbose) { 716 printf("%s: cacheline 0x%x lattimer 0x%x\n", 717 sc->sc_dev.dv_xname, cba.cba_cacheline, 718 cba.cba_lattimer); 719 printf("%s: bhlc 0x%x lscp 0x%x\n", 720 sc->sc_dev.dv_xname, bhlc, busreg); 721 } 722 #if defined SHOW_REGS 723 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 724 sc->sc_base_memh); 725 #endif 726 } 727 728 pccbb_pcmcia_attach_setup(sc, &paa); 729 caa.caa_cb_attach = NULL; 730 if (cba.cba_bus == 0) 731 printf("%s: secondary bus number uninitialized; try PCI_BUS_FIXUP\n", sc->sc_dev.dv_xname); 732 else 733 caa.caa_cb_attach = &cba; 734 caa.caa_16_attach = &paa; 735 caa.caa_ph = &sc->sc_pcmcia_h; 736 737 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 738 DPRINTF(("pccbbattach: found cardslot\n")); 739 sc->sc_csc = csc; 740 } 741 742 return; 743 } 744 745 746 747 748 749 /* 750 * static void pccbb_chipinit(struct pccbb_softc *sc) 751 * 752 * This function initialize YENTA chip registers listed below: 753 * 1) PCI command reg, 754 * 2) PCI and CardBus latency timer, 755 * 3) route PCI interrupt, 756 * 4) close all memory and io windows. 757 * 5) turn off bus power. 758 * 6) card detect and power cycle interrupts on. 759 * 7) clear interrupt 760 */ 761 static void 762 pccbb_chipinit(sc) 763 struct pccbb_softc *sc; 764 { 765 pci_chipset_tag_t pc = sc->sc_pc; 766 pcitag_t tag = sc->sc_tag; 767 bus_space_tag_t bmt = sc->sc_base_memt; 768 bus_space_handle_t bmh = sc->sc_base_memh; 769 pcireg_t reg; 770 771 /* 772 * Set PCI command reg. 773 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 774 */ 775 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 776 /* I believe it is harmless. */ 777 reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 778 PCI_COMMAND_MASTER_ENABLE); 779 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg); 780 781 /* 782 * Set CardBus latency timer. 783 */ 784 reg = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 785 if (PCI_CB_LATENCY(reg) < 0x20) { 786 reg &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 787 reg |= (0x20 << PCI_CB_LATENCY_SHIFT); 788 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, reg); 789 } 790 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 791 PCI_CB_LATENCY(reg), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 792 793 /* 794 * Set PCI latency timer. 795 */ 796 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 797 if (PCI_LATTIMER(reg) < 0x10) { 798 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 799 reg |= (0x10 << PCI_LATTIMER_SHIFT); 800 pci_conf_write(pc, tag, PCI_BHLC_REG, reg); 801 } 802 DPRINTF(("PCI latency timer 0x%x (%x)\n", 803 PCI_LATTIMER(reg), pci_conf_read(pc, tag, PCI_BHLC_REG))); 804 805 806 /* Route functional interrupts to PCI. */ 807 reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 808 reg |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 809 reg |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 810 reg |= CB_BCR_RESET_ENABLE; /* assert reset */ 811 pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 812 813 switch (sc->sc_chipset) { 814 case CB_TI113X: 815 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 816 /* This bit is shared, but may read as 0 on some chips, so set 817 it explicitly on both functions. */ 818 reg |= PCI113X_CBCTRL_PCI_IRQ_ENA; 819 /* CSC intr enable */ 820 reg |= PCI113X_CBCTRL_PCI_CSC; 821 /* functional intr prohibit | prohibit ISA routing */ 822 reg &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 823 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 824 break; 825 826 case CB_TI12XX: 827 /* 828 * Some TI 12xx (and [14][45]xx) based pci cards 829 * sometimes have issues with the MFUNC register not 830 * being initialized due to a bad EEPROM on board. 831 * Laptops that this matters on have this register 832 * properly initialized. 833 * 834 * The TI125X parts have a different register. 835 */ 836 reg = pci_conf_read(pc, tag, PCI12XX_MFUNC); 837 if (reg == 0) { 838 reg &= ~PCI12XX_MFUNC_PIN0; 839 reg |= PCI12XX_MFUNC_PIN0_INTA; 840 if ((pci_conf_read(pc, tag, PCI_SYSCTRL) & 841 PCI12XX_SYSCTRL_INTRTIE) == 0) { 842 reg &= ~PCI12XX_MFUNC_PIN1; 843 reg |= PCI12XX_MFUNC_PIN1_INTB; 844 } 845 pci_conf_write(pc, tag, PCI12XX_MFUNC, reg); 846 } 847 /* fallthrough */ 848 849 case CB_TI125X: 850 /* 851 * Disable zoom video. Some machines initialize this 852 * improperly and experience has shown that this helps 853 * prevent strange behavior. 854 */ 855 pci_conf_write(pc, tag, PCI12XX_MMCTRL, 0); 856 857 reg = pci_conf_read(pc, tag, PCI_SYSCTRL); 858 reg |= PCI12XX_SYSCTRL_VCCPROT; 859 pci_conf_write(pc, tag, PCI_SYSCTRL, reg); 860 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 861 reg |= PCI12XX_CBCTRL_CSC; 862 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 863 break; 864 865 case CB_TOPIC95B: 866 reg = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 867 reg |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 868 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, reg); 869 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 870 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 871 sc->sc_dev.dv_xname, reg)); 872 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 873 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 874 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 875 DPRINTF(("0x%x\n", reg)); 876 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 877 break; 878 879 case CB_TOPIC97: 880 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 881 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 882 sc->sc_dev.dv_xname, reg)); 883 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 884 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 885 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 886 reg |= TOPIC97_SLOT_CTRL_PCIINT; 887 reg &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 888 DPRINTF(("0x%x\n", reg)); 889 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 890 /* make sure to assert LV card support bits */ 891 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 892 0x800 + 0x3e, 893 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 894 0x800 + 0x3e) | 0x03); 895 break; 896 } 897 898 /* Close all memory and I/O windows. */ 899 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 900 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 901 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 902 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 903 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 904 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 905 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 906 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 907 908 /* reset 16-bit pcmcia bus */ 909 bus_space_write_1(bmt, bmh, 0x800 + PCIC_INTR, 910 bus_space_read_1(bmt, bmh, 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 911 912 /* turn off power */ 913 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 914 915 /* CSC Interrupt: Card detect and power cycle interrupts on */ 916 reg = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 917 reg |= CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; 918 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, reg); 919 /* reset interrupt */ 920 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 921 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 922 } 923 924 925 926 927 /* 928 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 929 * struct pcmciabus_attach_args *paa) 930 * 931 * This function attaches 16-bit PCcard bus. 932 */ 933 STATIC void 934 pccbb_pcmcia_attach_setup(sc, paa) 935 struct pccbb_softc *sc; 936 struct pcmciabus_attach_args *paa; 937 { 938 struct pcic_handle *ph = &sc->sc_pcmcia_h; 939 #if rbus 940 rbus_tag_t rb; 941 #endif 942 943 /* initialize pcmcia part in pccbb_softc */ 944 ph->ph_parent = (struct device *)sc; 945 ph->sock = sc->sc_function; 946 ph->flags = 0; 947 ph->shutdown = 0; 948 ph->ih_irq = sc->sc_pa.pa_intrline; 949 ph->ph_bus_t = sc->sc_base_memt; 950 ph->ph_bus_h = sc->sc_base_memh; 951 ph->ph_read = pccbb_pcmcia_read; 952 ph->ph_write = pccbb_pcmcia_write; 953 sc->sc_pct = &pccbb_pcmcia_funcs; 954 955 /* 956 * We need to do a few things here: 957 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 958 * setting the IRQ numbers to 0. 959 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 960 * routing of CSC interrupts (e.g. card removal) to PCI while in 961 * PCMCIA mode. We just leave this set all the time. 962 * 3) Enable card insertion/removal interrupts in case the chip also 963 * needs that while in PCMCIA mode. 964 * 4) Clear any pending CSC interrupt. 965 */ 966 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE); 967 if (sc->sc_chipset == CB_TI113X) { 968 Pcic_write(ph, PCIC_CSC_INTR, 0); 969 } else { 970 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 971 Pcic_read(ph, PCIC_CSC); 972 } 973 974 /* initialize pcmcia bus attachment */ 975 paa->paa_busname = "pcmcia"; 976 paa->pct = sc->sc_pct; 977 paa->pch = ph; 978 paa->iobase = 0; /* I don't use them */ 979 paa->iosize = 0; 980 #if rbus 981 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 982 paa->iobase = rb->rb_start + rb->rb_offset; 983 paa->iosize = rb->rb_end - rb->rb_start; 984 #endif 985 986 return; 987 } 988 989 #if 0 990 STATIC void 991 pccbb_pcmcia_attach_card(ph) 992 struct pcic_handle *ph; 993 { 994 if (ph->flags & PCIC_FLAG_CARDP) { 995 panic("pccbb_pcmcia_attach_card: already attached"); 996 } 997 998 /* call the MI attach function */ 999 pcmcia_card_attach(ph->pcmcia); 1000 1001 ph->flags |= PCIC_FLAG_CARDP; 1002 } 1003 1004 STATIC void 1005 pccbb_pcmcia_detach_card(ph, flags) 1006 struct pcic_handle *ph; 1007 int flags; 1008 { 1009 if (!(ph->flags & PCIC_FLAG_CARDP)) { 1010 panic("pccbb_pcmcia_detach_card: already detached"); 1011 } 1012 1013 ph->flags &= ~PCIC_FLAG_CARDP; 1014 1015 /* call the MI detach function */ 1016 pcmcia_card_detach(ph->pcmcia, flags); 1017 } 1018 #endif 1019 1020 /* 1021 * int pccbbintr(arg) 1022 * void *arg; 1023 * This routine handles the interrupt from Yenta PCI-CardBus bridge 1024 * itself. 1025 */ 1026 int 1027 pccbbintr(arg) 1028 void *arg; 1029 { 1030 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1031 u_int32_t sockevent, sockstate; 1032 bus_space_tag_t memt = sc->sc_base_memt; 1033 bus_space_handle_t memh = sc->sc_base_memh; 1034 struct pcic_handle *ph = &sc->sc_pcmcia_h; 1035 1036 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 1037 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 1038 Pcic_read(ph, PCIC_CSC); 1039 1040 if (sockevent == 0) { 1041 /* This intr is not for me: it may be for my child devices. */ 1042 if (sc->sc_pil_intr_enable) { 1043 return pccbbintr_function(sc); 1044 } else { 1045 return 0; 1046 } 1047 } 1048 1049 if (sockevent & CB_SOCKET_EVENT_CD) { 1050 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1051 if (0x00 != (sockstate & CB_SOCKET_STAT_CD)) { 1052 /* A card should be removed. */ 1053 if (sc->sc_flags & CBB_CARDEXIST) { 1054 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 1055 sockevent)); 1056 DPRINTF((" card removed, 0x%08x\n", sockstate)); 1057 sc->sc_flags &= ~CBB_CARDEXIST; 1058 if (sc->sc_csc->sc_status & 1059 CARDSLOT_STATUS_CARD_16) { 1060 #if 0 1061 struct pcic_handle *ph = 1062 &sc->sc_pcmcia_h; 1063 1064 pcmcia_card_deactivate(ph->pcmcia); 1065 pccbb_pcmcia_socket_disable(ph); 1066 pccbb_pcmcia_detach_card(ph, 1067 DETACH_FORCE); 1068 #endif 1069 cardslot_event_throw(sc->sc_csc, 1070 CARDSLOT_EVENT_REMOVAL_16); 1071 } else if (sc->sc_csc->sc_status & 1072 CARDSLOT_STATUS_CARD_CB) { 1073 /* Cardbus intr removed */ 1074 cardslot_event_throw(sc->sc_csc, 1075 CARDSLOT_EVENT_REMOVAL_CB); 1076 } 1077 } else if (sc->sc_flags & CBB_INSERTING) { 1078 sc->sc_flags &= ~CBB_INSERTING; 1079 callout_stop(&sc->sc_insert_ch); 1080 } 1081 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 1082 /* 1083 * The pccbbintr may called from powerdown hook when 1084 * the system resumed, to detect the card 1085 * insertion/removal during suspension. 1086 */ 1087 (sc->sc_flags & CBB_CARDEXIST) == 0) { 1088 if (sc->sc_flags & CBB_INSERTING) { 1089 callout_stop(&sc->sc_insert_ch); 1090 } 1091 callout_reset(&sc->sc_insert_ch, hz / 5, 1092 pci113x_insert, sc); 1093 sc->sc_flags |= CBB_INSERTING; 1094 } 1095 } 1096 1097 if (sockevent & CB_SOCKET_EVENT_POWER) { 1098 DPRINTF(("Powercycling because of socket event\n")); 1099 /* XXX: Does not happen when attaching a 16-bit card */ 1100 sc->sc_pwrcycle++; 1101 wakeup(&sc->sc_pwrcycle); 1102 } 1103 1104 return (1); 1105 } 1106 1107 /* 1108 * static int pccbbintr_function(struct pccbb_softc *sc) 1109 * 1110 * This function calls each interrupt handler registered at the 1111 * bridge. The interrupt handlers are called in registered order. 1112 */ 1113 static int 1114 pccbbintr_function(sc) 1115 struct pccbb_softc *sc; 1116 { 1117 int retval = 0, val; 1118 struct pccbb_intrhand_list *pil; 1119 int s, splchanged; 1120 1121 for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1122 pil = LIST_NEXT(pil, pil_next)) { 1123 /* 1124 * XXX priority change. gross. I use if-else 1125 * sentense instead of switch-case sentense because of 1126 * avoiding duplicate case value error. More than one 1127 * IPL_XXX use same value. It depends on 1128 * implimentation. 1129 */ 1130 splchanged = 1; 1131 if (pil->pil_level == IPL_SERIAL) { 1132 s = splserial(); 1133 } else if (pil->pil_level == IPL_HIGH) { 1134 s = splhigh(); 1135 } else if (pil->pil_level == IPL_CLOCK) { 1136 s = splclock(); 1137 } else if (pil->pil_level == IPL_AUDIO) { 1138 s = splaudio(); 1139 } else if (pil->pil_level == IPL_VM) { 1140 s = splvm(); 1141 } else if (pil->pil_level == IPL_TTY) { 1142 s = spltty(); 1143 } else if (pil->pil_level == IPL_SOFTSERIAL) { 1144 s = splsoftserial(); 1145 } else if (pil->pil_level == IPL_NET) { 1146 s = splnet(); 1147 } else { 1148 s = 0; /* XXX: gcc */ 1149 splchanged = 0; 1150 /* XXX: ih lower than IPL_BIO runs w/ IPL_BIO. */ 1151 } 1152 1153 val = (*pil->pil_func)(pil->pil_arg); 1154 1155 if (splchanged != 0) { 1156 splx(s); 1157 } 1158 1159 retval = retval == 1 ? 1 : 1160 retval == 0 ? val : val != 0 ? val : retval; 1161 } 1162 1163 return retval; 1164 } 1165 1166 static void 1167 pci113x_insert(arg) 1168 void *arg; 1169 { 1170 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1171 u_int32_t sockevent, sockstate; 1172 1173 if (!(sc->sc_flags & CBB_INSERTING)) { 1174 /* We add a card only under inserting state. */ 1175 return; 1176 } 1177 sc->sc_flags &= ~CBB_INSERTING; 1178 1179 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1180 CB_SOCKET_EVENT); 1181 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1182 CB_SOCKET_STAT); 1183 1184 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1185 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1186 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1187 sc->sc_flags |= CBB_CARDEXIST; 1188 /* call pccard interrupt handler here */ 1189 if (sockstate & CB_SOCKET_STAT_16BIT) { 1190 /* 16-bit card found */ 1191 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1192 cardslot_event_throw(sc->sc_csc, 1193 CARDSLOT_EVENT_INSERTION_16); 1194 } else if (sockstate & CB_SOCKET_STAT_CB) { 1195 /* cardbus card found */ 1196 /* cardbus_attach_card(sc->sc_csc); */ 1197 cardslot_event_throw(sc->sc_csc, 1198 CARDSLOT_EVENT_INSERTION_CB); 1199 } else { 1200 /* who are you? */ 1201 } 1202 } else { 1203 callout_reset(&sc->sc_insert_ch, hz / 10, 1204 pci113x_insert, sc); 1205 } 1206 } 1207 1208 #define PCCBB_PCMCIA_OFFSET 0x800 1209 static u_int8_t 1210 pccbb_pcmcia_read(ph, reg) 1211 struct pcic_handle *ph; 1212 int reg; 1213 { 1214 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1215 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1216 1217 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1218 PCCBB_PCMCIA_OFFSET + reg); 1219 } 1220 1221 static void 1222 pccbb_pcmcia_write(ph, reg, val) 1223 struct pcic_handle *ph; 1224 int reg; 1225 u_int8_t val; 1226 { 1227 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1228 val); 1229 1230 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1231 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1232 } 1233 1234 /* 1235 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1236 */ 1237 STATIC int 1238 pccbb_ctrl(ct, command) 1239 cardbus_chipset_tag_t ct; 1240 int command; 1241 { 1242 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1243 1244 switch (command) { 1245 case CARDBUS_CD: 1246 if (2 == pccbb_detect_card(sc)) { 1247 int retval = 0; 1248 int status = cb_detect_voltage(sc); 1249 if (PCCARD_VCC_5V & status) { 1250 retval |= CARDBUS_5V_CARD; 1251 } 1252 if (PCCARD_VCC_3V & status) { 1253 retval |= CARDBUS_3V_CARD; 1254 } 1255 if (PCCARD_VCC_XV & status) { 1256 retval |= CARDBUS_XV_CARD; 1257 } 1258 if (PCCARD_VCC_YV & status) { 1259 retval |= CARDBUS_YV_CARD; 1260 } 1261 return retval; 1262 } else { 1263 return 0; 1264 } 1265 case CARDBUS_RESET: 1266 return cb_reset(sc); 1267 case CARDBUS_IO_ENABLE: /* fallthrough */ 1268 case CARDBUS_IO_DISABLE: /* fallthrough */ 1269 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1270 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1271 case CARDBUS_BM_ENABLE: /* fallthrough */ 1272 case CARDBUS_BM_DISABLE: /* fallthrough */ 1273 /* XXX: I think we don't need to call this function below. */ 1274 return pccbb_cardenable(sc, command); 1275 } 1276 1277 return 0; 1278 } 1279 1280 /* 1281 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1282 * This function returns true when it succeeds and returns false when 1283 * it fails. 1284 */ 1285 STATIC int 1286 pccbb_power(ct, command) 1287 cardbus_chipset_tag_t ct; 1288 int command; 1289 { 1290 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1291 u_int32_t status, sock_ctrl, reg_ctrl; 1292 bus_space_tag_t memt = sc->sc_base_memt; 1293 bus_space_handle_t memh = sc->sc_base_memh; 1294 int on = 0, pwrcycle; 1295 1296 DPRINTF(("pccbb_power: %s and %s [0x%x]\n", 1297 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1298 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1299 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1300 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1301 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1302 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1303 "UNKNOWN", 1304 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1305 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1306 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1307 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1308 "UNKNOWN", command)); 1309 1310 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1311 sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1312 1313 switch (command & CARDBUS_VCCMASK) { 1314 case CARDBUS_VCC_UC: 1315 break; 1316 case CARDBUS_VCC_5V: 1317 on++; 1318 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1319 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1320 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1321 } else { 1322 printf("%s: BAD voltage request: no 5 V card\n", 1323 sc->sc_dev.dv_xname); 1324 return 0; 1325 } 1326 break; 1327 case CARDBUS_VCC_3V: 1328 on++; 1329 if (CB_SOCKET_STAT_3VCARD & status) { 1330 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1331 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1332 } else { 1333 printf("%s: BAD voltage request: no 3.3 V card\n", 1334 sc->sc_dev.dv_xname); 1335 return 0; 1336 } 1337 break; 1338 case CARDBUS_VCC_0V: 1339 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1340 break; 1341 default: 1342 return 0; /* power NEVER changed */ 1343 } 1344 1345 switch (command & CARDBUS_VPPMASK) { 1346 case CARDBUS_VPP_UC: 1347 break; 1348 case CARDBUS_VPP_0V: 1349 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1350 break; 1351 case CARDBUS_VPP_VCC: 1352 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1353 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1354 break; 1355 case CARDBUS_VPP_12V: 1356 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1357 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1358 break; 1359 } 1360 1361 pwrcycle = sc->sc_pwrcycle; 1362 1363 #if 0 1364 DPRINTF(("sock_ctrl: 0x%x\n", sock_ctrl)); 1365 #endif 1366 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1367 1368 if (on) { 1369 int s, error = 0; 1370 struct timeval before, after, diff; 1371 1372 DPRINTF(("Waiting for bridge to power up\n")); 1373 microtime(&before); 1374 s = splbio(); 1375 while (pwrcycle == sc->sc_pwrcycle) { 1376 /* 1377 * XXX: Set timeout to 200ms because power cycle event 1378 * will never happen when attaching a 16-bit card. 1379 */ 1380 if ((error = tsleep(&sc->sc_pwrcycle, PWAIT, "pccpwr", 1381 hz / 5)) == EWOULDBLOCK) 1382 break; 1383 } 1384 splx(s); 1385 microtime(&after); 1386 timersub(&after, &before, &diff); 1387 aprint_debug("%s: wait took%s %ld.%06lds\n", 1388 sc->sc_dev.dv_xname, 1389 error == EWOULDBLOCK ? " too long" : "", 1390 diff.tv_sec, diff.tv_usec); 1391 1392 /* 1393 * Ok, wait a bit longer for things to settle. 1394 */ 1395 if (sc->sc_chipset == CB_TOPIC95B) 1396 DELAY_MS(100, sc); 1397 } 1398 1399 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1400 1401 if (on && sc->sc_chipset != CB_TOPIC95B) { 1402 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0) 1403 printf("%s: power on failed?\n", sc->sc_dev.dv_xname); 1404 } 1405 1406 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1407 printf("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1408 sc->sc_dev.dv_xname, sock_ctrl, status); 1409 printf("%s: disabling socket\n", sc->sc_dev.dv_xname); 1410 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1411 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1412 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1413 status &= ~CB_SOCKET_STAT_BADVCC; 1414 bus_space_write_4(memt, memh, CB_SOCKET_STAT, status); 1415 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1416 CB_SOCKET_STAT)); 1417 return 0; 1418 } 1419 1420 if (sc->sc_chipset == CB_TOPIC97) { 1421 reg_ctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL); 1422 reg_ctrl &= ~TOPIC97_REG_CTRL_TESTMODE; 1423 if ((command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V) 1424 reg_ctrl &= ~TOPIC97_REG_CTRL_CLKRUN_ENA; 1425 else 1426 reg_ctrl |= TOPIC97_REG_CTRL_CLKRUN_ENA; 1427 pci_conf_write(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL, reg_ctrl); 1428 } 1429 1430 return 1; /* power changed correctly */ 1431 } 1432 1433 #if defined CB_PCMCIA_POLL 1434 struct cb_poll_str { 1435 void *arg; 1436 int (*func)(void *); 1437 int level; 1438 pccard_chipset_tag_t ct; 1439 int count; 1440 struct callout poll_ch; 1441 }; 1442 1443 static struct cb_poll_str cb_poll[10]; 1444 static int cb_poll_n = 0; 1445 1446 static void cb_pcmcia_poll(void *arg); 1447 1448 static void 1449 cb_pcmcia_poll(arg) 1450 void *arg; 1451 { 1452 struct cb_poll_str *poll = arg; 1453 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1454 struct pccbb_softc *sc = psc->cpc_parent; 1455 int s; 1456 u_int32_t spsr; /* socket present-state reg */ 1457 1458 callout_reset(&poll->poll_ch, hz / 10, cb_pcmcia_poll, poll); 1459 switch (poll->level) { 1460 case IPL_NET: 1461 s = splnet(); 1462 break; 1463 case IPL_BIO: 1464 s = splbio(); 1465 break; 1466 case IPL_TTY: /* fallthrough */ 1467 default: 1468 s = spltty(); 1469 break; 1470 } 1471 1472 spsr = 1473 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1474 CB_SOCKET_STAT); 1475 1476 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1477 if (!(spsr & 0x40)) { /* CINT low */ 1478 #else 1479 if (1) { 1480 #endif 1481 if ((*poll->func) (poll->arg) == 1) { 1482 ++poll->count; 1483 printf("intr: reported from poller, 0x%x\n", spsr); 1484 #if defined LEVEL2 1485 } else { 1486 printf("intr: miss! 0x%x\n", spsr); 1487 #endif 1488 } 1489 } 1490 splx(s); 1491 } 1492 #endif /* defined CB_PCMCIA_POLL */ 1493 1494 /* 1495 * static int pccbb_detect_card(struct pccbb_softc *sc) 1496 * return value: 0 if no card exists. 1497 * 1 if 16-bit card exists. 1498 * 2 if cardbus card exists. 1499 */ 1500 static int 1501 pccbb_detect_card(sc) 1502 struct pccbb_softc *sc; 1503 { 1504 bus_space_handle_t base_memh = sc->sc_base_memh; 1505 bus_space_tag_t base_memt = sc->sc_base_memt; 1506 u_int32_t sockstat = 1507 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1508 int retval = 0; 1509 1510 /* CD1 and CD2 asserted */ 1511 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1512 /* card must be present */ 1513 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1514 /* NOTACARD DEASSERTED */ 1515 if (CB_SOCKET_STAT_CB & sockstat) { 1516 /* CardBus mode */ 1517 retval = 2; 1518 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1519 /* 16-bit mode */ 1520 retval = 1; 1521 } 1522 } 1523 } 1524 return retval; 1525 } 1526 1527 /* 1528 * STATIC int cb_reset(struct pccbb_softc *sc) 1529 * This function resets CardBus card. 1530 */ 1531 STATIC int 1532 cb_reset(sc) 1533 struct pccbb_softc *sc; 1534 { 1535 /* 1536 * Reset Assert at least 20 ms 1537 * Some machines request longer duration. 1538 */ 1539 int reset_duration = 1540 (sc->sc_chipset == CB_RX5C47X ? 400 : 50); 1541 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1542 1543 /* Reset bit Assert (bit 6 at 0x3E) */ 1544 bcr |= CB_BCR_RESET_ENABLE; 1545 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1546 DELAY_MS(reset_duration, sc); 1547 1548 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1549 /* Reset bit Deassert (bit 6 at 0x3E) */ 1550 bcr &= ~CB_BCR_RESET_ENABLE; 1551 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1552 DELAY_MS(reset_duration, sc); 1553 } 1554 /* No card found on the slot. Keep Reset. */ 1555 return 1; 1556 } 1557 1558 /* 1559 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1560 * This function detect card Voltage. 1561 */ 1562 STATIC int 1563 cb_detect_voltage(sc) 1564 struct pccbb_softc *sc; 1565 { 1566 u_int32_t psr; /* socket present-state reg */ 1567 bus_space_tag_t iot = sc->sc_base_memt; 1568 bus_space_handle_t ioh = sc->sc_base_memh; 1569 int vol = PCCARD_VCC_UKN; /* set 0 */ 1570 1571 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1572 1573 if (0x400u & psr) { 1574 vol |= PCCARD_VCC_5V; 1575 } 1576 if (0x800u & psr) { 1577 vol |= PCCARD_VCC_3V; 1578 } 1579 1580 return vol; 1581 } 1582 1583 STATIC int 1584 cbbprint(void *aux __unused, const char *pcic __unused) 1585 { 1586 #if 0 1587 struct cbslot_attach_args *cba = aux; 1588 1589 if (cba->cba_slot >= 0) { 1590 aprint_normal(" slot %d", cba->cba_slot); 1591 } 1592 #endif 1593 return UNCONF; 1594 } 1595 1596 /* 1597 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1598 * This function enables and disables the card 1599 */ 1600 STATIC int 1601 pccbb_cardenable(sc, function) 1602 struct pccbb_softc *sc; 1603 int function; 1604 { 1605 u_int32_t command = 1606 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1607 1608 DPRINTF(("pccbb_cardenable:")); 1609 switch (function) { 1610 case CARDBUS_IO_ENABLE: 1611 command |= PCI_COMMAND_IO_ENABLE; 1612 break; 1613 case CARDBUS_IO_DISABLE: 1614 command &= ~PCI_COMMAND_IO_ENABLE; 1615 break; 1616 case CARDBUS_MEM_ENABLE: 1617 command |= PCI_COMMAND_MEM_ENABLE; 1618 break; 1619 case CARDBUS_MEM_DISABLE: 1620 command &= ~PCI_COMMAND_MEM_ENABLE; 1621 break; 1622 case CARDBUS_BM_ENABLE: 1623 command |= PCI_COMMAND_MASTER_ENABLE; 1624 break; 1625 case CARDBUS_BM_DISABLE: 1626 command &= ~PCI_COMMAND_MASTER_ENABLE; 1627 break; 1628 default: 1629 return 0; 1630 } 1631 1632 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1633 DPRINTF((" command reg 0x%x\n", command)); 1634 return 1; 1635 } 1636 1637 #if !rbus 1638 /* 1639 * int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1640 */ 1641 static int 1642 pccbb_io_open(ct, win, start, end) 1643 cardbus_chipset_tag_t ct; 1644 int win; 1645 u_int32_t start, end; 1646 { 1647 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1648 int basereg; 1649 int limitreg; 1650 1651 if ((win < 0) || (win > 2)) { 1652 #if defined DIAGNOSTIC 1653 printf("cardbus_io_open: window out of range %d\n", win); 1654 #endif 1655 return 0; 1656 } 1657 1658 basereg = win * 8 + 0x2c; 1659 limitreg = win * 8 + 0x30; 1660 1661 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1662 start, basereg, end, limitreg)); 1663 1664 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1665 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1666 return 1; 1667 } 1668 1669 /* 1670 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1671 */ 1672 static int 1673 pccbb_io_close(ct, win) 1674 cardbus_chipset_tag_t ct; 1675 int win; 1676 { 1677 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1678 int basereg; 1679 int limitreg; 1680 1681 if ((win < 0) || (win > 2)) { 1682 #if defined DIAGNOSTIC 1683 printf("cardbus_io_close: window out of range %d\n", win); 1684 #endif 1685 return 0; 1686 } 1687 1688 basereg = win * 8 + 0x2c; 1689 limitreg = win * 8 + 0x30; 1690 1691 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1692 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1693 return 1; 1694 } 1695 1696 /* 1697 * int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1698 */ 1699 static int 1700 pccbb_mem_open(ct, win, start, end) 1701 cardbus_chipset_tag_t ct; 1702 int win; 1703 u_int32_t start, end; 1704 { 1705 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1706 int basereg; 1707 int limitreg; 1708 1709 if ((win < 0) || (win > 2)) { 1710 #if defined DIAGNOSTIC 1711 printf("cardbus_mem_open: window out of range %d\n", win); 1712 #endif 1713 return 0; 1714 } 1715 1716 basereg = win * 8 + 0x1c; 1717 limitreg = win * 8 + 0x20; 1718 1719 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1720 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1721 return 1; 1722 } 1723 1724 /* 1725 * int pccbb_mem_close(cardbus_chipset_tag_t, int) 1726 */ 1727 static int 1728 pccbb_mem_close(ct, win) 1729 cardbus_chipset_tag_t ct; 1730 int win; 1731 { 1732 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1733 int basereg; 1734 int limitreg; 1735 1736 if ((win < 0) || (win > 2)) { 1737 #if defined DIAGNOSTIC 1738 printf("cardbus_mem_close: window out of range %d\n", win); 1739 #endif 1740 return 0; 1741 } 1742 1743 basereg = win * 8 + 0x1c; 1744 limitreg = win * 8 + 0x20; 1745 1746 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1747 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1748 return 1; 1749 } 1750 #endif 1751 1752 /* 1753 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1754 * int irq, 1755 * int level, 1756 * int (* func)(void *), 1757 * void *arg) 1758 * 1759 * This function registers an interrupt handler at the bridge, in 1760 * order not to call the interrupt handlers of child devices when 1761 * a card-deletion interrupt occurs. 1762 * 1763 * The arguments irq and level are not used. 1764 */ 1765 static void * 1766 pccbb_cb_intr_establish(ct, irq, level, func, arg) 1767 cardbus_chipset_tag_t ct; 1768 int irq, level; 1769 int (*func)(void *); 1770 void *arg; 1771 { 1772 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1773 1774 return pccbb_intr_establish(sc, irq, level, func, arg); 1775 } 1776 1777 1778 /* 1779 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1780 * void *ih) 1781 * 1782 * This function removes an interrupt handler pointed by ih. 1783 */ 1784 static void 1785 pccbb_cb_intr_disestablish(ct, ih) 1786 cardbus_chipset_tag_t ct; 1787 void *ih; 1788 { 1789 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1790 1791 pccbb_intr_disestablish(sc, ih); 1792 } 1793 1794 1795 void 1796 pccbb_intr_route(sc) 1797 struct pccbb_softc *sc; 1798 { 1799 pcireg_t reg; 1800 1801 /* initialize bridge intr routing */ 1802 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1803 reg &= ~CB_BCR_INTR_IREQ_ENABLE; 1804 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1805 1806 switch (sc->sc_chipset) { 1807 case CB_TI113X: 1808 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1809 /* functional intr enabled */ 1810 reg |= PCI113X_CBCTRL_PCI_INTR; 1811 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1812 break; 1813 default: 1814 break; 1815 } 1816 } 1817 1818 /* 1819 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1820 * int irq, 1821 * int level, 1822 * int (* func)(void *), 1823 * void *arg) 1824 * 1825 * This function registers an interrupt handler at the bridge, in 1826 * order not to call the interrupt handlers of child devices when 1827 * a card-deletion interrupt occurs. 1828 * 1829 * The arguments irq is not used because pccbb selects intr vector. 1830 */ 1831 static void * 1832 pccbb_intr_establish(struct pccbb_softc *sc, int irq __unused, int level, 1833 int (*func)(void *), void *arg) 1834 { 1835 struct pccbb_intrhand_list *pil, *newpil; 1836 1837 DPRINTF(("pccbb_intr_establish start. %p\n", LIST_FIRST(&sc->sc_pil))); 1838 1839 if (LIST_EMPTY(&sc->sc_pil)) { 1840 pccbb_intr_route(sc); 1841 } 1842 1843 /* 1844 * Allocate a room for interrupt handler structure. 1845 */ 1846 if (NULL == (newpil = 1847 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1848 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1849 return NULL; 1850 } 1851 1852 newpil->pil_func = func; 1853 newpil->pil_arg = arg; 1854 newpil->pil_level = level; 1855 1856 if (LIST_EMPTY(&sc->sc_pil)) { 1857 LIST_INSERT_HEAD(&sc->sc_pil, newpil, pil_next); 1858 } else { 1859 for (pil = LIST_FIRST(&sc->sc_pil); 1860 LIST_NEXT(pil, pil_next) != NULL; 1861 pil = LIST_NEXT(pil, pil_next)); 1862 LIST_INSERT_AFTER(pil, newpil, pil_next); 1863 } 1864 1865 DPRINTF(("pccbb_intr_establish add pil. %p\n", 1866 LIST_FIRST(&sc->sc_pil))); 1867 1868 return newpil; 1869 } 1870 1871 /* 1872 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1873 * void *ih) 1874 * 1875 * This function removes an interrupt handler pointed by ih. ih 1876 * should be the value returned by cardbus_intr_establish() or 1877 * NULL. 1878 * 1879 * When ih is NULL, this function will do nothing. 1880 */ 1881 static void 1882 pccbb_intr_disestablish(sc, ih) 1883 struct pccbb_softc *sc; 1884 void *ih; 1885 { 1886 struct pccbb_intrhand_list *pil; 1887 pcireg_t reg; 1888 1889 DPRINTF(("pccbb_intr_disestablish start. %p\n", 1890 LIST_FIRST(&sc->sc_pil))); 1891 1892 if (ih == NULL) { 1893 /* intr handler is not set */ 1894 DPRINTF(("pccbb_intr_disestablish: no ih\n")); 1895 return; 1896 } 1897 1898 #ifdef DIAGNOSTIC 1899 for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1900 pil = LIST_NEXT(pil, pil_next)) { 1901 DPRINTF(("pccbb_intr_disestablish: pil %p\n", pil)); 1902 if (pil == ih) { 1903 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1904 break; 1905 } 1906 } 1907 if (pil == NULL) { 1908 panic("pccbb_intr_disestablish: %s cannot find pil %p", 1909 sc->sc_dev.dv_xname, ih); 1910 } 1911 #endif 1912 1913 pil = (struct pccbb_intrhand_list *)ih; 1914 LIST_REMOVE(pil, pil_next); 1915 free(pil, M_DEVBUF); 1916 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1917 1918 if (LIST_EMPTY(&sc->sc_pil)) { 1919 /* No interrupt handlers */ 1920 1921 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1922 1923 /* stop routing PCI intr */ 1924 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1925 reg |= CB_BCR_INTR_IREQ_ENABLE; 1926 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1927 1928 switch (sc->sc_chipset) { 1929 case CB_TI113X: 1930 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1931 /* functional intr disabled */ 1932 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1933 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1934 break; 1935 default: 1936 break; 1937 } 1938 } 1939 } 1940 1941 #if defined SHOW_REGS 1942 static void 1943 cb_show_regs(pc, tag, memt, memh) 1944 pci_chipset_tag_t pc; 1945 pcitag_t tag; 1946 bus_space_tag_t memt; 1947 bus_space_handle_t memh; 1948 { 1949 int i; 1950 printf("PCI config regs:"); 1951 for (i = 0; i < 0x50; i += 4) { 1952 if (i % 16 == 0) { 1953 printf("\n 0x%02x:", i); 1954 } 1955 printf(" %08x", pci_conf_read(pc, tag, i)); 1956 } 1957 for (i = 0x80; i < 0xb0; i += 4) { 1958 if (i % 16 == 0) { 1959 printf("\n 0x%02x:", i); 1960 } 1961 printf(" %08x", pci_conf_read(pc, tag, i)); 1962 } 1963 1964 if (memh == 0) { 1965 printf("\n"); 1966 return; 1967 } 1968 1969 printf("\nsocket regs:"); 1970 for (i = 0; i <= 0x10; i += 0x04) { 1971 printf(" %08x", bus_space_read_4(memt, memh, i)); 1972 } 1973 printf("\nExCA regs:"); 1974 for (i = 0; i < 0x08; ++i) { 1975 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1976 } 1977 printf("\n"); 1978 return; 1979 } 1980 #endif 1981 1982 /* 1983 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1984 * int busno, int function) 1985 * This is the function to make a tag to access config space of 1986 * a CardBus Card. It works same as pci_conf_read. 1987 */ 1988 static cardbustag_t 1989 pccbb_make_tag(cc, busno, function) 1990 cardbus_chipset_tag_t cc; 1991 int busno, function; 1992 { 1993 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1994 1995 return pci_make_tag(sc->sc_pc, busno, 0, function); 1996 } 1997 1998 static void 1999 pccbb_free_tag(cardbus_chipset_tag_t cc __unused, cardbustag_t tag __unused) 2000 { 2001 } 2002 2003 /* 2004 * static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t cc, 2005 * cardbustag_t tag, int offset) 2006 * This is the function to read the config space of a CardBus Card. 2007 * It works same as pci_conf_read. 2008 */ 2009 static cardbusreg_t 2010 pccbb_conf_read(cc, tag, offset) 2011 cardbus_chipset_tag_t cc; 2012 cardbustag_t tag; 2013 int offset; /* register offset */ 2014 { 2015 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 2016 2017 return pci_conf_read(sc->sc_pc, tag, offset); 2018 } 2019 2020 /* 2021 * static void pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, 2022 * int offs, cardbusreg_t val) 2023 * This is the function to write the config space of a CardBus Card. 2024 * It works same as pci_conf_write. 2025 */ 2026 static void 2027 pccbb_conf_write(cc, tag, reg, val) 2028 cardbus_chipset_tag_t cc; 2029 cardbustag_t tag; 2030 int reg; /* register offset */ 2031 cardbusreg_t val; 2032 { 2033 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 2034 2035 pci_conf_write(sc->sc_pc, tag, reg, val); 2036 } 2037 2038 #if 0 2039 STATIC int 2040 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 2041 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 2042 int speed, int flags, 2043 bus_space_handle_t * iohp) 2044 #endif 2045 /* 2046 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 2047 * bus_addr_t start, bus_size_t size, 2048 * bus_size_t align, 2049 * struct pcmcia_io_handle *pcihp 2050 * 2051 * This function only allocates I/O region for pccard. This function 2052 * never maps the allocated region to pccard I/O area. 2053 * 2054 * XXX: The interface of this function is not very good, I believe. 2055 */ 2056 STATIC int 2057 pccbb_pcmcia_io_alloc(pch, start, size, align, pcihp) 2058 pcmcia_chipset_handle_t pch; 2059 bus_addr_t start; /* start address */ 2060 bus_size_t size; 2061 bus_size_t align; 2062 struct pcmcia_io_handle *pcihp; 2063 { 2064 struct pcic_handle *ph = (struct pcic_handle *)pch; 2065 bus_addr_t ioaddr; 2066 int flags = 0; 2067 bus_space_tag_t iot; 2068 bus_space_handle_t ioh; 2069 bus_addr_t mask; 2070 #if rbus 2071 rbus_tag_t rb; 2072 #endif 2073 if (align == 0) { 2074 align = size; /* XXX: funny??? */ 2075 } 2076 2077 if (start != 0) { 2078 /* XXX: assume all card decode lower 10 bits by its hardware */ 2079 mask = 0x3ff; 2080 /* enforce to use only masked address */ 2081 start &= mask; 2082 } else { 2083 /* 2084 * calculate mask: 2085 * 1. get the most significant bit of size (call it msb). 2086 * 2. compare msb with the value of size. 2087 * 3. if size is larger, shift msb left once. 2088 * 4. obtain mask value to decrement msb. 2089 */ 2090 bus_size_t size_tmp = size; 2091 int shifts = 0; 2092 2093 mask = 1; 2094 while (size_tmp) { 2095 ++shifts; 2096 size_tmp >>= 1; 2097 } 2098 mask = (1 << shifts); 2099 if (mask < size) { 2100 mask <<= 1; 2101 } 2102 --mask; 2103 } 2104 2105 /* 2106 * Allocate some arbitrary I/O space. 2107 */ 2108 2109 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 2110 2111 #if rbus 2112 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 2113 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 2114 return 1; 2115 } 2116 DPRINTF(("pccbb_pcmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2117 (u_long) ioaddr, (u_long) size)); 2118 #else 2119 if (start) { 2120 ioaddr = start; 2121 if (bus_space_map(iot, start, size, 0, &ioh)) { 2122 return 1; 2123 } 2124 DPRINTF(("pccbb_pcmcia_io_alloc map port 0x%lx+0x%lx\n", 2125 (u_long) ioaddr, (u_long) size)); 2126 } else { 2127 flags |= PCMCIA_IO_ALLOCATED; 2128 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 2129 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 2130 size, align, 0, 0, &ioaddr, &ioh)) { 2131 /* No room be able to be get. */ 2132 return 1; 2133 } 2134 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2135 (u_long) ioaddr, (u_long) size)); 2136 } 2137 #endif 2138 2139 pcihp->iot = iot; 2140 pcihp->ioh = ioh; 2141 pcihp->addr = ioaddr; 2142 pcihp->size = size; 2143 pcihp->flags = flags; 2144 2145 return 0; 2146 } 2147 2148 /* 2149 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2150 * struct pcmcia_io_handle *pcihp) 2151 * 2152 * This function only frees I/O region for pccard. 2153 * 2154 * XXX: The interface of this function is not very good, I believe. 2155 */ 2156 void 2157 pccbb_pcmcia_io_free(pch, pcihp) 2158 pcmcia_chipset_handle_t pch; 2159 struct pcmcia_io_handle *pcihp; 2160 { 2161 #if !rbus 2162 bus_space_tag_t iot = pcihp->iot; 2163 #endif 2164 bus_space_handle_t ioh = pcihp->ioh; 2165 bus_size_t size = pcihp->size; 2166 2167 #if rbus 2168 struct pccbb_softc *sc = 2169 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 2170 rbus_tag_t rb = sc->sc_rbus_iot; 2171 2172 rbus_space_free(rb, ioh, size, NULL); 2173 #else 2174 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 2175 bus_space_free(iot, ioh, size); 2176 else 2177 bus_space_unmap(iot, ioh, size); 2178 #endif 2179 } 2180 2181 /* 2182 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 2183 * bus_addr_t offset, bus_size_t size, 2184 * struct pcmcia_io_handle *pcihp, 2185 * int *windowp) 2186 * 2187 * This function maps the allocated I/O region to pccard. This function 2188 * never allocates any I/O region for pccard I/O area. I don't 2189 * understand why the original authors of pcmciabus separated alloc and 2190 * map. I believe the two must be unite. 2191 * 2192 * XXX: no wait timing control? 2193 */ 2194 int 2195 pccbb_pcmcia_io_map(pch, width, offset, size, pcihp, windowp) 2196 pcmcia_chipset_handle_t pch; 2197 int width; 2198 bus_addr_t offset; 2199 bus_size_t size; 2200 struct pcmcia_io_handle *pcihp; 2201 int *windowp; 2202 { 2203 struct pcic_handle *ph = (struct pcic_handle *)pch; 2204 bus_addr_t ioaddr = pcihp->addr + offset; 2205 int i, win; 2206 #if defined CBB_DEBUG 2207 static const char *width_names[] = { "dynamic", "io8", "io16" }; 2208 #endif 2209 2210 /* Sanity check I/O handle. */ 2211 2212 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 2213 panic("pccbb_pcmcia_io_map iot is bogus"); 2214 } 2215 2216 /* XXX Sanity check offset/size. */ 2217 2218 win = -1; 2219 for (i = 0; i < PCIC_IO_WINS; i++) { 2220 if ((ph->ioalloc & (1 << i)) == 0) { 2221 win = i; 2222 ph->ioalloc |= (1 << i); 2223 break; 2224 } 2225 } 2226 2227 if (win == -1) { 2228 return 1; 2229 } 2230 2231 *windowp = win; 2232 2233 /* XXX this is pretty gross */ 2234 2235 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2236 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2237 2238 /* XXX wtf is this doing here? */ 2239 2240 #if 0 2241 printf(" port 0x%lx", (u_long) ioaddr); 2242 if (size > 1) { 2243 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2244 } 2245 #endif 2246 2247 ph->io[win].addr = ioaddr; 2248 ph->io[win].size = size; 2249 ph->io[win].width = width; 2250 2251 /* actual dirty register-value changing in the function below. */ 2252 pccbb_pcmcia_do_io_map(ph, win); 2253 2254 return 0; 2255 } 2256 2257 /* 2258 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2259 * 2260 * This function changes register-value to map I/O region for pccard. 2261 */ 2262 static void 2263 pccbb_pcmcia_do_io_map(ph, win) 2264 struct pcic_handle *ph; 2265 int win; 2266 { 2267 static u_int8_t pcic_iowidth[3] = { 2268 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2269 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2270 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2271 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2272 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2273 }; 2274 2275 #define PCIC_SIA_START_LOW 0 2276 #define PCIC_SIA_START_HIGH 1 2277 #define PCIC_SIA_STOP_LOW 2 2278 #define PCIC_SIA_STOP_HIGH 3 2279 2280 int regbase_win = 0x8 + win * 0x04; 2281 u_int8_t ioctl, enable; 2282 2283 DPRINTF(("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx " 2284 "width %d\n", win, (unsigned long)ph->io[win].addr, 2285 (unsigned long)ph->io[win].size, ph->io[win].width * 8)); 2286 2287 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2288 ph->io[win].addr & 0xff); 2289 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2290 (ph->io[win].addr >> 8) & 0xff); 2291 2292 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2293 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2294 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2295 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2296 2297 ioctl = Pcic_read(ph, PCIC_IOCTL); 2298 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2299 switch (win) { 2300 case 0: 2301 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2302 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2303 PCIC_IOCTL_IO0_DATASIZE_MASK); 2304 ioctl |= pcic_iowidth[ph->io[win].width]; 2305 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2306 break; 2307 case 1: 2308 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2309 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2310 PCIC_IOCTL_IO1_DATASIZE_MASK); 2311 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2312 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2313 break; 2314 } 2315 Pcic_write(ph, PCIC_IOCTL, ioctl); 2316 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2317 #if defined(CBB_DEBUG) 2318 { 2319 u_int8_t start_low = 2320 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2321 u_int8_t start_high = 2322 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2323 u_int8_t stop_low = 2324 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2325 u_int8_t stop_high = 2326 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2327 printf("pccbb_pcmcia_do_io_map start %02x %02x, " 2328 "stop %02x %02x, ioctl %02x enable %02x\n", 2329 start_low, start_high, stop_low, stop_high, ioctl, enable); 2330 } 2331 #endif 2332 } 2333 2334 /* 2335 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2336 * 2337 * This function unmaps I/O region. No return value. 2338 */ 2339 STATIC void 2340 pccbb_pcmcia_io_unmap(pch, win) 2341 pcmcia_chipset_handle_t pch; 2342 int win; 2343 { 2344 struct pcic_handle *ph = (struct pcic_handle *)pch; 2345 int reg; 2346 2347 if (win >= PCIC_IO_WINS || win < 0) { 2348 panic("pccbb_pcmcia_io_unmap: window out of range"); 2349 } 2350 2351 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2352 switch (win) { 2353 case 0: 2354 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2355 break; 2356 case 1: 2357 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2358 break; 2359 } 2360 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2361 2362 ph->ioalloc &= ~(1 << win); 2363 } 2364 2365 static int 2366 pccbb_pcmcia_wait_ready(ph) 2367 struct pcic_handle *ph; 2368 { 2369 u_int8_t stat; 2370 int i; 2371 2372 /* wait an initial 10ms for quick cards */ 2373 stat = Pcic_read(ph, PCIC_IF_STATUS); 2374 if (stat & PCIC_IF_STATUS_READY) 2375 return (0); 2376 pccbb_pcmcia_delay(ph, 10, "pccwr0"); 2377 for (i = 0; i < 50; i++) { 2378 stat = Pcic_read(ph, PCIC_IF_STATUS); 2379 if (stat & PCIC_IF_STATUS_READY) 2380 return (0); 2381 if ((stat & PCIC_IF_STATUS_CARDDETECT_MASK) != 2382 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2383 return (ENXIO); 2384 /* wait .1s (100ms) each iteration now */ 2385 pccbb_pcmcia_delay(ph, 100, "pccwr1"); 2386 } 2387 2388 printf("pccbb_pcmcia_wait_ready: ready never happened, status=%02x\n", stat); 2389 return (EWOULDBLOCK); 2390 } 2391 2392 /* 2393 * Perform long (msec order) delay. 2394 */ 2395 static void 2396 pccbb_pcmcia_delay( 2397 struct pcic_handle *ph __unused, 2398 int timo, /* in ms. must not be zero */ 2399 const char *wmesg 2400 ) 2401 { 2402 #ifdef DIAGNOSTIC 2403 if (timo <= 0) 2404 panic("pccbb_pcmcia_delay: called with timeout %d", timo); 2405 if (!curlwp) 2406 panic("pccbb_pcmcia_delay: called in interrupt context"); 2407 #if 0 2408 if (!ph->event_thread) 2409 panic("pccbb_pcmcia_delay: no event thread"); 2410 #endif 2411 #endif 2412 DPRINTF(("pccbb_pcmcia_delay: \"%s\" %p, sleep %d ms\n", 2413 wmesg, ph->event_thread, timo)); 2414 tsleep(pccbb_pcmcia_delay, PWAIT, wmesg, roundup(timo * hz, 1000) / 1000); 2415 } 2416 2417 /* 2418 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2419 * 2420 * This function enables the card. All information is stored in 2421 * the first argument, pcmcia_chipset_handle_t. 2422 */ 2423 STATIC void 2424 pccbb_pcmcia_socket_enable(pch) 2425 pcmcia_chipset_handle_t pch; 2426 { 2427 struct pcic_handle *ph = (struct pcic_handle *)pch; 2428 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2429 pcireg_t spsr; 2430 int voltage; 2431 int win; 2432 u_int8_t power, intr; 2433 #ifdef DIAGNOSTIC 2434 int reg; 2435 #endif 2436 2437 /* this bit is mostly stolen from pcic_attach_card */ 2438 2439 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2440 2441 /* get card Vcc info */ 2442 spsr = 2443 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2444 CB_SOCKET_STAT); 2445 if (spsr & CB_SOCKET_STAT_5VCARD) { 2446 DPRINTF(("5V card\n")); 2447 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2448 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2449 DPRINTF(("3V card\n")); 2450 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2451 } else { 2452 DPRINTF(("?V card, 0x%x\n", spsr)); /* XXX */ 2453 return; 2454 } 2455 2456 /* disable interrupts; assert RESET */ 2457 intr = Pcic_read(ph, PCIC_INTR); 2458 intr &= PCIC_INTR_ENABLE; 2459 Pcic_write(ph, PCIC_INTR, intr); 2460 2461 /* zero out the address windows */ 2462 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2463 2464 /* power down the socket to reset it, clear the card reset pin */ 2465 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2466 2467 /* power off; assert output enable bit */ 2468 power = PCIC_PWRCTL_OE; 2469 Pcic_write(ph, PCIC_PWRCTL, power); 2470 2471 /* power up the socket */ 2472 if (pccbb_power(sc, voltage) == 0) 2473 return; 2474 2475 /* 2476 * Table 4-18 and figure 4-6 of the PC Card specifiction say: 2477 * Vcc Rising Time (Tpr) = 100ms (handled in pccbb_power() above) 2478 * RESET Width (Th (Hi-z RESET)) = 1ms 2479 * RESET Width (Tw (RESET)) = 10us 2480 * 2481 * some machines require some more time to be settled 2482 * for example old toshiba topic bridges! 2483 * (100ms is added here). 2484 */ 2485 pccbb_pcmcia_delay(ph, 200 + 1, "pccen1"); 2486 2487 /* negate RESET */ 2488 intr |= PCIC_INTR_RESET; 2489 Pcic_write(ph, PCIC_INTR, intr); 2490 2491 /* 2492 * RESET Setup Time (Tsu (RESET)) = 20ms 2493 */ 2494 pccbb_pcmcia_delay(ph, 20, "pccen2"); 2495 2496 #ifdef DIAGNOSTIC 2497 reg = Pcic_read(ph, PCIC_IF_STATUS); 2498 if ((reg & PCIC_IF_STATUS_POWERACTIVE) == 0) 2499 printf("pccbb_pcmcia_socket_enable: no power, status=%x\n", reg); 2500 #endif 2501 2502 /* wait for the chip to finish initializing */ 2503 if (pccbb_pcmcia_wait_ready(ph)) { 2504 #ifdef DIAGNOSTIC 2505 printf("pccbb_pcmcia_socket_enable: never became ready\n"); 2506 #endif 2507 /* XXX return a failure status?? */ 2508 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2509 Pcic_write(ph, PCIC_PWRCTL, 0); 2510 return; 2511 } 2512 2513 /* reinstall all the memory and io mappings */ 2514 for (win = 0; win < PCIC_MEM_WINS; ++win) 2515 if (ph->memalloc & (1 << win)) 2516 pccbb_pcmcia_do_mem_map(ph, win); 2517 for (win = 0; win < PCIC_IO_WINS; ++win) 2518 if (ph->ioalloc & (1 << win)) 2519 pccbb_pcmcia_do_io_map(ph, win); 2520 } 2521 2522 /* 2523 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2524 * 2525 * This function disables the card. All information is stored in 2526 * the first argument, pcmcia_chipset_handle_t. 2527 */ 2528 STATIC void 2529 pccbb_pcmcia_socket_disable(pch) 2530 pcmcia_chipset_handle_t pch; 2531 { 2532 struct pcic_handle *ph = (struct pcic_handle *)pch; 2533 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2534 u_int8_t intr; 2535 2536 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2537 2538 /* disable interrupts; assert RESET */ 2539 intr = Pcic_read(ph, PCIC_INTR); 2540 intr &= PCIC_INTR_ENABLE; 2541 Pcic_write(ph, PCIC_INTR, intr); 2542 2543 /* zero out the address windows */ 2544 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2545 2546 /* power down the socket to reset it, clear the card reset pin */ 2547 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2548 2549 /* disable socket: negate output enable bit and power off */ 2550 Pcic_write(ph, PCIC_PWRCTL, 0); 2551 2552 /* 2553 * Vcc Falling Time (Tpf) = 300ms 2554 */ 2555 pccbb_pcmcia_delay(ph, 300, "pccwr1"); 2556 } 2557 2558 STATIC void 2559 pccbb_pcmcia_socket_settype(pch, type) 2560 pcmcia_chipset_handle_t pch; 2561 int type; 2562 { 2563 struct pcic_handle *ph = (struct pcic_handle *)pch; 2564 u_int8_t intr; 2565 2566 /* set the card type */ 2567 2568 intr = Pcic_read(ph, PCIC_INTR); 2569 intr &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_CARDTYPE_MASK); 2570 if (type == PCMCIA_IFTYPE_IO) 2571 intr |= PCIC_INTR_CARDTYPE_IO; 2572 else 2573 intr |= PCIC_INTR_CARDTYPE_MEM; 2574 Pcic_write(ph, PCIC_INTR, intr); 2575 2576 DPRINTF(("%s: pccbb_pcmcia_socket_settype %02x type %s %02x\n", 2577 ph->ph_parent->dv_xname, ph->sock, 2578 ((type == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2579 } 2580 2581 /* 2582 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2583 * 2584 * This function detects whether a card is in the slot or not. 2585 * If a card is inserted, return 1. Otherwise, return 0. 2586 */ 2587 STATIC int 2588 pccbb_pcmcia_card_detect(pch) 2589 pcmcia_chipset_handle_t pch; 2590 { 2591 struct pcic_handle *ph = (struct pcic_handle *)pch; 2592 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2593 2594 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2595 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2596 } 2597 2598 #if 0 2599 STATIC int 2600 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2601 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2602 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2603 #endif 2604 /* 2605 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2606 * bus_size_t size, 2607 * struct pcmcia_mem_handle *pcmhp) 2608 * 2609 * This function only allocates memory region for pccard. This 2610 * function never maps the allocated region to pccard memory area. 2611 * 2612 * XXX: Why the argument of start address is not in? 2613 */ 2614 STATIC int 2615 pccbb_pcmcia_mem_alloc(pch, size, pcmhp) 2616 pcmcia_chipset_handle_t pch; 2617 bus_size_t size; 2618 struct pcmcia_mem_handle *pcmhp; 2619 { 2620 struct pcic_handle *ph = (struct pcic_handle *)pch; 2621 bus_space_handle_t memh; 2622 bus_addr_t addr; 2623 bus_size_t sizepg; 2624 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2625 #if rbus 2626 rbus_tag_t rb; 2627 #endif 2628 2629 /* Check that the card is still there. */ 2630 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2631 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2632 return 1; 2633 2634 /* out of sc->memh, allocate as many pages as necessary */ 2635 2636 /* convert size to PCIC pages */ 2637 /* 2638 * This is not enough; when the requested region is on the page 2639 * boundaries, this may calculate wrong result. 2640 */ 2641 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2642 #if 0 2643 if (sizepg > PCIC_MAX_MEM_PAGES) { 2644 return 1; 2645 } 2646 #endif 2647 2648 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2649 return 1; 2650 } 2651 2652 addr = 0; /* XXX gcc -Wuninitialized */ 2653 2654 #if rbus 2655 rb = sc->sc_rbus_memt; 2656 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2657 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2658 &addr, &memh)) { 2659 return 1; 2660 } 2661 #else 2662 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2663 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2664 0, /* boundary */ 2665 0, /* flags */ 2666 &addr, &memh)) { 2667 return 1; 2668 } 2669 #endif 2670 2671 DPRINTF(("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, " 2672 "realsize 0x%lx\n", (unsigned long)addr, (unsigned long)size, 2673 (unsigned long)sizepg * PCIC_MEM_PAGESIZE)); 2674 2675 pcmhp->memt = sc->sc_memt; 2676 pcmhp->memh = memh; 2677 pcmhp->addr = addr; 2678 pcmhp->size = size; 2679 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2680 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2681 pcmhp->mhandle = 0; 2682 /* No offset??? Funny. */ 2683 2684 return 0; 2685 } 2686 2687 /* 2688 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2689 * struct pcmcia_mem_handle *pcmhp) 2690 * 2691 * This function release the memory space allocated by the function 2692 * pccbb_pcmcia_mem_alloc(). 2693 */ 2694 STATIC void 2695 pccbb_pcmcia_mem_free(pch, pcmhp) 2696 pcmcia_chipset_handle_t pch; 2697 struct pcmcia_mem_handle *pcmhp; 2698 { 2699 #if rbus 2700 struct pcic_handle *ph = (struct pcic_handle *)pch; 2701 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2702 2703 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2704 #else 2705 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2706 #endif 2707 } 2708 2709 /* 2710 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2711 * 2712 * This function release the memory space allocated by the function 2713 * pccbb_pcmcia_mem_alloc(). 2714 */ 2715 STATIC void 2716 pccbb_pcmcia_do_mem_map(ph, win) 2717 struct pcic_handle *ph; 2718 int win; 2719 { 2720 int regbase_win; 2721 bus_addr_t phys_addr; 2722 bus_addr_t phys_end; 2723 2724 #define PCIC_SMM_START_LOW 0 2725 #define PCIC_SMM_START_HIGH 1 2726 #define PCIC_SMM_STOP_LOW 2 2727 #define PCIC_SMM_STOP_HIGH 3 2728 #define PCIC_CMA_LOW 4 2729 #define PCIC_CMA_HIGH 5 2730 2731 u_int8_t start_low, start_high = 0; 2732 u_int8_t stop_low, stop_high; 2733 u_int8_t off_low, off_high; 2734 u_int8_t mem_window; 2735 int reg; 2736 2737 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2738 int mem8 = 2739 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2740 || (kind == PCMCIA_MEM_ATTR); 2741 2742 regbase_win = 0x10 + win * 0x08; 2743 2744 phys_addr = ph->mem[win].addr; 2745 phys_end = phys_addr + ph->mem[win].size; 2746 2747 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2748 (unsigned long)phys_addr, (unsigned long)phys_end, 2749 (unsigned long)ph->mem[win].offset)); 2750 2751 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2752 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2753 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2754 2755 /* bit 19:12 */ 2756 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2757 /* bit 23:20 and bit 7 on */ 2758 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2759 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2760 /* bit 31:24, for 32-bit address */ 2761 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2762 2763 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2764 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2765 2766 if (((struct pccbb_softc *)ph-> 2767 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2768 Pcic_write(ph, 0x40 + win, mem_window); 2769 } 2770 2771 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2772 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2773 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2774 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2775 2776 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2777 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2778 2779 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2780 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2781 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2782 | ((kind == PCMCIA_MEM_ATTR) ? 2783 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2784 2785 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2786 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2787 2788 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2789 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2790 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2791 2792 #if defined(CBB_DEBUG) 2793 { 2794 int r1, r2, r3, r4, r5, r6, r7 = 0; 2795 2796 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2797 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2798 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2799 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2800 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2801 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2802 if (((struct pccbb_softc *)(ph-> 2803 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2804 r7 = Pcic_read(ph, 0x40 + win); 2805 } 2806 2807 printf("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2808 "%02x%02x", win, r1, r2, r3, r4, r5, r6); 2809 if (((struct pccbb_softc *)(ph-> 2810 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2811 printf(" %02x", r7); 2812 } 2813 printf("\n"); 2814 } 2815 #endif 2816 } 2817 2818 /* 2819 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2820 * bus_addr_t card_addr, bus_size_t size, 2821 * struct pcmcia_mem_handle *pcmhp, 2822 * bus_addr_t *offsetp, int *windowp) 2823 * 2824 * This function maps memory space allocated by the function 2825 * pccbb_pcmcia_mem_alloc(). 2826 */ 2827 STATIC int 2828 pccbb_pcmcia_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 2829 pcmcia_chipset_handle_t pch; 2830 int kind; 2831 bus_addr_t card_addr; 2832 bus_size_t size; 2833 struct pcmcia_mem_handle *pcmhp; 2834 bus_addr_t *offsetp; 2835 int *windowp; 2836 { 2837 struct pcic_handle *ph = (struct pcic_handle *)pch; 2838 bus_addr_t busaddr; 2839 long card_offset; 2840 int win; 2841 2842 /* Check that the card is still there. */ 2843 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2844 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2845 return 1; 2846 2847 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2848 if ((ph->memalloc & (1 << win)) == 0) { 2849 ph->memalloc |= (1 << win); 2850 break; 2851 } 2852 } 2853 2854 if (win == PCIC_MEM_WINS) { 2855 return 1; 2856 } 2857 2858 *windowp = win; 2859 2860 /* XXX this is pretty gross */ 2861 2862 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2863 panic("pccbb_pcmcia_mem_map memt is bogus"); 2864 } 2865 2866 busaddr = pcmhp->addr; 2867 2868 /* 2869 * compute the address offset to the pcmcia address space for the 2870 * pcic. this is intentionally signed. The masks and shifts below 2871 * will cause TRT to happen in the pcic registers. Deal with making 2872 * sure the address is aligned, and return the alignment offset. 2873 */ 2874 2875 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2876 card_addr -= *offsetp; 2877 2878 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2879 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2880 (u_long) card_addr)); 2881 2882 /* 2883 * include the offset in the size, and decrement size by one, since 2884 * the hw wants start/stop 2885 */ 2886 size += *offsetp - 1; 2887 2888 card_offset = (((long)card_addr) - ((long)busaddr)); 2889 2890 ph->mem[win].addr = busaddr; 2891 ph->mem[win].size = size; 2892 ph->mem[win].offset = card_offset; 2893 ph->mem[win].kind = kind; 2894 2895 pccbb_pcmcia_do_mem_map(ph, win); 2896 2897 return 0; 2898 } 2899 2900 /* 2901 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2902 * int window) 2903 * 2904 * This function unmaps memory space which mapped by the function 2905 * pccbb_pcmcia_mem_map(). 2906 */ 2907 STATIC void 2908 pccbb_pcmcia_mem_unmap(pch, window) 2909 pcmcia_chipset_handle_t pch; 2910 int window; 2911 { 2912 struct pcic_handle *ph = (struct pcic_handle *)pch; 2913 int reg; 2914 2915 if (window >= PCIC_MEM_WINS) { 2916 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2917 } 2918 2919 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2920 reg &= ~(1 << window); 2921 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2922 2923 ph->memalloc &= ~(1 << window); 2924 } 2925 2926 #if defined PCCBB_PCMCIA_POLL 2927 struct pccbb_poll_str { 2928 void *arg; 2929 int (*func)(void *); 2930 int level; 2931 struct pcic_handle *ph; 2932 int count; 2933 int num; 2934 struct callout poll_ch; 2935 }; 2936 2937 static struct pccbb_poll_str pccbb_poll[10]; 2938 static int pccbb_poll_n = 0; 2939 2940 static void pccbb_pcmcia_poll(void *arg); 2941 2942 static void 2943 pccbb_pcmcia_poll(arg) 2944 void *arg; 2945 { 2946 struct pccbb_poll_str *poll = arg; 2947 struct pcic_handle *ph = poll->ph; 2948 struct pccbb_softc *sc = ph->sc; 2949 int s; 2950 u_int32_t spsr; /* socket present-state reg */ 2951 2952 callout_reset(&poll->poll_ch, hz * 2, pccbb_pcmcia_poll, arg); 2953 switch (poll->level) { 2954 case IPL_NET: 2955 s = splnet(); 2956 break; 2957 case IPL_BIO: 2958 s = splbio(); 2959 break; 2960 case IPL_TTY: /* fallthrough */ 2961 default: 2962 s = spltty(); 2963 break; 2964 } 2965 2966 spsr = 2967 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2968 CB_SOCKET_STAT); 2969 2970 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2971 if (!(spsr & 0x40)) /* CINT low */ 2972 #else 2973 if (1) 2974 #endif 2975 { 2976 if ((*poll->func) (poll->arg) > 0) { 2977 ++poll->count; 2978 /* printf("intr: reported from poller, 0x%x\n", spsr); */ 2979 #if defined LEVEL2 2980 } else { 2981 printf("intr: miss! 0x%x\n", spsr); 2982 #endif 2983 } 2984 } 2985 splx(s); 2986 } 2987 #endif /* defined CB_PCMCIA_POLL */ 2988 2989 /* 2990 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2991 * struct pcmcia_function *pf, 2992 * int ipl, 2993 * int (*func)(void *), 2994 * void *arg); 2995 * 2996 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2997 */ 2998 STATIC void * 2999 pccbb_pcmcia_intr_establish(pch, pf, ipl, func, arg) 3000 pcmcia_chipset_handle_t pch; 3001 struct pcmcia_function *pf; 3002 int ipl; 3003 int (*func)(void *); 3004 void *arg; 3005 { 3006 struct pcic_handle *ph = (struct pcic_handle *)pch; 3007 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 3008 3009 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 3010 /* what should I do? */ 3011 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 3012 DPRINTF(("%s does not provide edge nor pulse " 3013 "interrupt\n", sc->sc_dev.dv_xname)); 3014 return NULL; 3015 } 3016 /* 3017 * XXX Noooooo! The interrupt flag must set properly!! 3018 * dumb pcmcia driver!! 3019 */ 3020 } 3021 3022 return pccbb_intr_establish(sc, 0, ipl, func, arg); 3023 } 3024 3025 /* 3026 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 3027 * void *ih) 3028 * 3029 * This function disables PC-Card interrupt. 3030 */ 3031 STATIC void 3032 pccbb_pcmcia_intr_disestablish(pch, ih) 3033 pcmcia_chipset_handle_t pch; 3034 void *ih; 3035 { 3036 struct pcic_handle *ph = (struct pcic_handle *)pch; 3037 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 3038 3039 pccbb_intr_disestablish(sc, ih); 3040 } 3041 3042 #if rbus 3043 /* 3044 * static int 3045 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 3046 * bus_addr_t addr, bus_size_t size, 3047 * bus_addr_t mask, bus_size_t align, 3048 * int flags, bus_addr_t *addrp; 3049 * bus_space_handle_t *bshp) 3050 * 3051 * This function allocates a portion of memory or io space for 3052 * clients. This function is called from CardBus card drivers. 3053 */ 3054 static int 3055 pccbb_rbus_cb_space_alloc(ct, rb, addr, size, mask, align, flags, addrp, bshp) 3056 cardbus_chipset_tag_t ct; 3057 rbus_tag_t rb; 3058 bus_addr_t addr; 3059 bus_size_t size; 3060 bus_addr_t mask; 3061 bus_size_t align; 3062 int flags; 3063 bus_addr_t *addrp; 3064 bus_space_handle_t *bshp; 3065 { 3066 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 3067 3068 DPRINTF(("pccbb_rbus_cb_space_alloc: addr 0x%lx, size 0x%lx, " 3069 "mask 0x%lx, align 0x%lx\n", (unsigned long)addr, 3070 (unsigned long)size, (unsigned long)mask, (unsigned long)align)); 3071 3072 if (align == 0) { 3073 align = size; 3074 } 3075 3076 if (rb->rb_bt == sc->sc_memt) { 3077 if (align < 16) { 3078 return 1; 3079 } 3080 /* 3081 * XXX: align more than 0x1000 to avoid overwrapping 3082 * memory windows for two or more devices. 0x1000 3083 * means memory window's granularity. 3084 * 3085 * Two or more devices should be able to share same 3086 * memory window region. However, overrapping memory 3087 * window is not good because some devices, such as 3088 * 3Com 3C575[BC], have a broken address decoder and 3089 * intrude other's memory region. 3090 */ 3091 if (align < 0x1000) { 3092 align = 0x1000; 3093 } 3094 } else if (rb->rb_bt == sc->sc_iot) { 3095 if (align < 4) { 3096 return 1; 3097 } 3098 /* XXX: hack for avoiding ISA image */ 3099 if (mask < 0x0100) { 3100 mask = 0x3ff; 3101 addr = 0x300; 3102 } 3103 3104 } else { 3105 DPRINTF(("pccbb_rbus_cb_space_alloc: Bus space tag 0x%lx is " 3106 "NOT used. io: 0x%lx, mem: 0x%lx\n", 3107 (unsigned long)rb->rb_bt, (unsigned long)sc->sc_iot, 3108 (unsigned long)sc->sc_memt)); 3109 return 1; 3110 /* XXX: panic here? */ 3111 } 3112 3113 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 3114 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 3115 return 1; 3116 } 3117 3118 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 3119 3120 return 0; 3121 } 3122 3123 /* 3124 * static int 3125 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 3126 * bus_space_handle_t *bshp, bus_size_t size); 3127 * 3128 * This function is called from CardBus card drivers. 3129 */ 3130 static int 3131 pccbb_rbus_cb_space_free(ct, rb, bsh, size) 3132 cardbus_chipset_tag_t ct; 3133 rbus_tag_t rb; 3134 bus_space_handle_t bsh; 3135 bus_size_t size; 3136 { 3137 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 3138 bus_space_tag_t bt = rb->rb_bt; 3139 3140 pccbb_close_win(sc, bt, bsh, size); 3141 3142 if (bt == sc->sc_memt) { 3143 } else if (bt == sc->sc_iot) { 3144 } else { 3145 return 1; 3146 /* XXX: panic here? */ 3147 } 3148 3149 return rbus_space_free(rb, bsh, size, NULL); 3150 } 3151 #endif /* rbus */ 3152 3153 #if rbus 3154 3155 static int 3156 pccbb_open_win(sc, bst, addr, size, bsh, flags) 3157 struct pccbb_softc *sc; 3158 bus_space_tag_t bst; 3159 bus_addr_t addr; 3160 bus_size_t size; 3161 bus_space_handle_t bsh; 3162 int flags; 3163 { 3164 struct pccbb_win_chain_head *head; 3165 bus_addr_t align; 3166 3167 head = &sc->sc_iowindow; 3168 align = 0x04; 3169 if (sc->sc_memt == bst) { 3170 head = &sc->sc_memwindow; 3171 align = 0x1000; 3172 DPRINTF(("using memory window, 0x%lx 0x%lx 0x%lx\n\n", 3173 (unsigned long)sc->sc_iot, (unsigned long)sc->sc_memt, 3174 (unsigned long)bst)); 3175 } 3176 3177 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 3178 printf("%s: pccbb_open_win: %s winlist insert failed\n", 3179 sc->sc_dev.dv_xname, 3180 (head == &sc->sc_memwindow) ? "mem" : "io"); 3181 } 3182 pccbb_winset(align, sc, bst); 3183 3184 return 0; 3185 } 3186 3187 static int 3188 pccbb_close_win(sc, bst, bsh, size) 3189 struct pccbb_softc *sc; 3190 bus_space_tag_t bst; 3191 bus_space_handle_t bsh; 3192 bus_size_t size; 3193 { 3194 struct pccbb_win_chain_head *head; 3195 bus_addr_t align; 3196 3197 head = &sc->sc_iowindow; 3198 align = 0x04; 3199 if (sc->sc_memt == bst) { 3200 head = &sc->sc_memwindow; 3201 align = 0x1000; 3202 } 3203 3204 if (pccbb_winlist_delete(head, bsh, size)) { 3205 printf("%s: pccbb_close_win: %s winlist delete failed\n", 3206 sc->sc_dev.dv_xname, 3207 (head == &sc->sc_memwindow) ? "mem" : "io"); 3208 } 3209 pccbb_winset(align, sc, bst); 3210 3211 return 0; 3212 } 3213 3214 static int 3215 pccbb_winlist_insert(head, start, size, bsh, flags) 3216 struct pccbb_win_chain_head *head; 3217 bus_addr_t start; 3218 bus_size_t size; 3219 bus_space_handle_t bsh; 3220 int flags; 3221 { 3222 struct pccbb_win_chain *chainp, *elem; 3223 3224 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 3225 M_NOWAIT)) == NULL) 3226 return (1); /* fail */ 3227 3228 elem->wc_start = start; 3229 elem->wc_end = start + (size - 1); 3230 elem->wc_handle = bsh; 3231 elem->wc_flags = flags; 3232 3233 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3234 chainp = TAILQ_NEXT(chainp, wc_list)) { 3235 if (chainp->wc_end < start) 3236 continue; 3237 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 3238 return (0); 3239 } 3240 3241 TAILQ_INSERT_TAIL(head, elem, wc_list); 3242 return (0); 3243 } 3244 3245 static int 3246 pccbb_winlist_delete(head, bsh, size) 3247 struct pccbb_win_chain_head *head; 3248 bus_space_handle_t bsh; 3249 bus_size_t size; 3250 { 3251 struct pccbb_win_chain *chainp; 3252 3253 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3254 chainp = TAILQ_NEXT(chainp, wc_list)) { 3255 if (memcmp(&chainp->wc_handle, &bsh, sizeof(bsh))) 3256 continue; 3257 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 3258 printf("pccbb_winlist_delete: window 0x%lx size " 3259 "inconsistent: 0x%lx, 0x%lx\n", 3260 (unsigned long)chainp->wc_start, 3261 (unsigned long)(chainp->wc_end - chainp->wc_start), 3262 (unsigned long)(size - 1)); 3263 return 1; 3264 } 3265 3266 TAILQ_REMOVE(head, chainp, wc_list); 3267 free(chainp, M_DEVBUF); 3268 3269 return 0; 3270 } 3271 3272 return 1; /* fail: no candidate to remove */ 3273 } 3274 3275 static void 3276 pccbb_winset(align, sc, bst) 3277 bus_addr_t align; 3278 struct pccbb_softc *sc; 3279 bus_space_tag_t bst; 3280 { 3281 pci_chipset_tag_t pc; 3282 pcitag_t tag; 3283 bus_addr_t mask = ~(align - 1); 3284 struct { 3285 cardbusreg_t win_start; 3286 cardbusreg_t win_limit; 3287 int win_flags; 3288 } win[2]; 3289 struct pccbb_win_chain *chainp; 3290 int offs; 3291 3292 win[0].win_start = win[1].win_start = 0xffffffff; 3293 win[0].win_limit = win[1].win_limit = 0; 3294 win[0].win_flags = win[1].win_flags = 0; 3295 3296 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3297 offs = 0x2c; 3298 if (sc->sc_memt == bst) { 3299 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3300 offs = 0x1c; 3301 } 3302 3303 if (chainp != NULL) { 3304 win[0].win_start = chainp->wc_start & mask; 3305 win[0].win_limit = chainp->wc_end & mask; 3306 win[0].win_flags = chainp->wc_flags; 3307 chainp = TAILQ_NEXT(chainp, wc_list); 3308 } 3309 3310 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3311 if (win[1].win_start == 0xffffffff) { 3312 /* window 1 is not used */ 3313 if ((win[0].win_flags == chainp->wc_flags) && 3314 (win[0].win_limit + align >= 3315 (chainp->wc_start & mask))) { 3316 /* concatenate */ 3317 win[0].win_limit = chainp->wc_end & mask; 3318 } else { 3319 /* make new window */ 3320 win[1].win_start = chainp->wc_start & mask; 3321 win[1].win_limit = chainp->wc_end & mask; 3322 win[1].win_flags = chainp->wc_flags; 3323 } 3324 continue; 3325 } 3326 3327 /* Both windows are engaged. */ 3328 if (win[0].win_flags == win[1].win_flags) { 3329 /* same flags */ 3330 if (win[0].win_flags == chainp->wc_flags) { 3331 if (win[1].win_start - (win[0].win_limit + 3332 align) < 3333 (chainp->wc_start & mask) - 3334 ((chainp->wc_end & mask) + align)) { 3335 /* 3336 * merge window 0 and 1, and set win1 3337 * to chainp 3338 */ 3339 win[0].win_limit = win[1].win_limit; 3340 win[1].win_start = 3341 chainp->wc_start & mask; 3342 win[1].win_limit = 3343 chainp->wc_end & mask; 3344 } else { 3345 win[1].win_limit = 3346 chainp->wc_end & mask; 3347 } 3348 } else { 3349 /* different flags */ 3350 3351 /* concatenate win0 and win1 */ 3352 win[0].win_limit = win[1].win_limit; 3353 /* allocate win[1] to new space */ 3354 win[1].win_start = chainp->wc_start & mask; 3355 win[1].win_limit = chainp->wc_end & mask; 3356 win[1].win_flags = chainp->wc_flags; 3357 } 3358 } else { 3359 /* the flags of win[0] and win[1] is different */ 3360 if (win[0].win_flags == chainp->wc_flags) { 3361 win[0].win_limit = chainp->wc_end & mask; 3362 /* 3363 * XXX this creates overlapping windows, so 3364 * what should the poor bridge do if one is 3365 * cachable, and the other is not? 3366 */ 3367 printf("%s: overlapping windows\n", 3368 sc->sc_dev.dv_xname); 3369 } else { 3370 win[1].win_limit = chainp->wc_end & mask; 3371 } 3372 } 3373 } 3374 3375 pc = sc->sc_pc; 3376 tag = sc->sc_tag; 3377 pci_conf_write(pc, tag, offs, win[0].win_start); 3378 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3379 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3380 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3381 DPRINTF(("--pccbb_winset: win0 [0x%lx, 0x%lx), win1 [0x%lx, 0x%lx)\n", 3382 (unsigned long)pci_conf_read(pc, tag, offs), 3383 (unsigned long)pci_conf_read(pc, tag, offs + 4) + align, 3384 (unsigned long)pci_conf_read(pc, tag, offs + 8), 3385 (unsigned long)pci_conf_read(pc, tag, offs + 12) + align)); 3386 3387 if (bst == sc->sc_memt) { 3388 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3389 3390 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 3391 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 3392 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3393 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 3394 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3395 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3396 } 3397 } 3398 3399 #endif /* rbus */ 3400 3401 static void 3402 pccbb_powerhook(why, arg) 3403 int why; 3404 void *arg; 3405 { 3406 struct pccbb_softc *sc = arg; 3407 pcireg_t reg; 3408 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3409 bus_space_handle_t base_memh = sc->sc_base_memh; 3410 3411 DPRINTF(("%s: power: why %d\n", sc->sc_dev.dv_xname, why)); 3412 3413 if (why == PWR_SUSPEND || why == PWR_STANDBY) { 3414 DPRINTF(("%s: power: why %d stopping intr\n", 3415 sc->sc_dev.dv_xname, why)); 3416 if (sc->sc_pil_intr_enable) { 3417 (void)pccbbintr_function(sc); 3418 } 3419 sc->sc_pil_intr_enable = 0; 3420 3421 pci_conf_capture(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf); 3422 3423 if (sc->sc_chipset == CB_RX5C47X) 3424 sc->sc_ricoh_misc_ctrl = pci_conf_read(sc->sc_pc, 3425 sc->sc_tag, 3426 RICOH_PCI_MISC_CTRL); 3427 3428 /* ToDo: deactivate or suspend child devices */ 3429 } 3430 3431 if (why == PWR_RESUME) { 3432 if (sc->sc_pwrmgt_offs != 0) { 3433 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, 3434 sc->sc_pwrmgt_offs + 4); 3435 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 3436 reg & 0x100) { 3437 /* powrstate != D0 */ 3438 3439 printf("%s going back to D0 mode\n", 3440 sc->sc_dev.dv_xname); 3441 reg &= ~PCI_PMCSR_STATE_MASK; 3442 reg |= PCI_PMCSR_STATE_D0; 3443 reg &= ~(0x100 /* PCI_PMCSR_PME_EN */); 3444 pci_conf_write(sc->sc_pc, sc->sc_tag, 3445 sc->sc_pwrmgt_offs + 4, reg); 3446 3447 pci_conf_write(sc->sc_pc, sc->sc_tag, 3448 PCI_SOCKBASE, sc->sc_sockbase); 3449 pci_conf_write(sc->sc_pc, sc->sc_tag, 3450 PCI_BUSNUM, sc->sc_busnum); 3451 pccbb_chipinit(sc); 3452 /* setup memory and io space window for CB */ 3453 pccbb_winset(0x1000, sc, sc->sc_memt); 3454 pccbb_winset(0x04, sc, sc->sc_iot); 3455 goto norestore; 3456 } 3457 } 3458 3459 norestore: 3460 pci_conf_restore(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf); 3461 if (sc->sc_chipset == CB_RX5C47X) { 3462 pci_conf_write(sc->sc_pc, sc->sc_tag, 3463 RICOH_PCI_MISC_CTRL, sc->sc_ricoh_misc_ctrl); 3464 } 3465 3466 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_SOCKBASE) == 0) 3467 /* BIOS did not recover this register */ 3468 pci_conf_write (sc->sc_pc, sc->sc_tag, 3469 PCI_SOCKBASE, sc->sc_sockbase); 3470 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_BUSNUM) == 0) 3471 /* BIOS did not recover this register */ 3472 pci_conf_write (sc->sc_pc, sc->sc_tag, 3473 PCI_BUSNUM, sc->sc_busnum); 3474 /* CSC Interrupt: Card detect interrupt on */ 3475 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3476 /* Card detect intr is turned on. */ 3477 reg |= CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; 3478 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3479 /* reset interrupt */ 3480 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3481 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3482 3483 /* 3484 * check for card insertion or removal during suspend period. 3485 * XXX: the code can't cope with card swap (remove then 3486 * insert). how can we detect such situation? 3487 */ 3488 (void)pccbbintr(sc); 3489 3490 sc->sc_pil_intr_enable = 1; 3491 DPRINTF(("%s: power: RESUME enabling intr\n", 3492 sc->sc_dev.dv_xname)); 3493 3494 /* ToDo: activate or wakeup child devices */ 3495 } 3496 } 3497
Indexes created Thu Sep 25 16:09:42 GMT 2025