pccbb.c revision 1.137.2.1
1 /* $NetBSD: pccbb.c,v 1.137.2.1 2007/07/30 21:52:30 liamjfoy Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: pccbb.c,v 1.137.2.1 2007/07/30 21:52:30 liamjfoy Exp $"); 35 36 /* 37 #define CBB_DEBUG 38 #define SHOW_REGS 39 */ 40 41 /* 42 * BROKEN! 43 #define PCCBB_PCMCIA_POLL 44 #define CB_PCMCIA_POLL 45 #define CB_PCMCIA_POLL_ONLY 46 #define LEVEL2 47 */ 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/kernel.h> 52 #include <sys/errno.h> 53 #include <sys/ioctl.h> 54 #include <sys/reboot.h> /* for bootverbose */ 55 #include <sys/syslog.h> 56 #include <sys/device.h> 57 #include <sys/malloc.h> 58 #include <sys/proc.h> 59 60 #include <machine/intr.h> 61 #include <machine/bus.h> 62 63 #include <dev/pci/pcivar.h> 64 #include <dev/pci/pcireg.h> 65 #include <dev/pci/pcidevs.h> 66 67 #include <dev/pci/pccbbreg.h> 68 69 #include <dev/cardbus/cardslotvar.h> 70 71 #include <dev/cardbus/cardbusvar.h> 72 73 #include <dev/pcmcia/pcmciareg.h> 74 #include <dev/pcmcia/pcmciavar.h> 75 76 #include <dev/ic/i82365reg.h> 77 #include <dev/ic/i82365var.h> 78 #include <dev/pci/pccbbvar.h> 79 80 #include "locators.h" 81 82 #if defined(__i386__) 83 #include "ioapic.h" 84 #include "acpi.h" 85 #endif 86 87 #ifndef __NetBSD_Version__ 88 struct cfdriver cbb_cd = { 89 NULL, "cbb", DV_DULL 90 }; 91 #endif 92 93 #ifdef CBB_DEBUG 94 #define DPRINTF(x) printf x 95 #define STATIC 96 #else 97 #define DPRINTF(x) 98 #define STATIC static 99 #endif 100 101 /* 102 * delay_ms() is wait in milliseconds. It should be used instead 103 * of delay() if you want to wait more than 1 ms. 104 */ 105 static inline void 106 delay_ms(int millis, void *param) 107 { 108 if (cold) 109 delay(millis * 1000); 110 else 111 tsleep(param, PWAIT, "pccbb", MAX(2, hz * millis / 1000)); 112 } 113 114 int pcicbbmatch(struct device *, struct cfdata *, void *); 115 void pccbbattach(struct device *, struct device *, void *); 116 int pccbbintr(void *); 117 static void pci113x_insert(void *); 118 static int pccbbintr_function(struct pccbb_softc *); 119 120 static int pccbb_detect_card(struct pccbb_softc *); 121 122 static void pccbb_pcmcia_write(struct pcic_handle *, int, u_int8_t); 123 static u_int8_t pccbb_pcmcia_read(struct pcic_handle *, int); 124 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 125 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 126 127 STATIC int cb_reset(struct pccbb_softc *); 128 STATIC int cb_detect_voltage(struct pccbb_softc *); 129 STATIC int cbbprint(void *, const char *); 130 131 static int cb_chipset(u_int32_t, int *); 132 STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *, 133 struct pcmciabus_attach_args *); 134 #if 0 135 STATIC void pccbb_pcmcia_attach_card(struct pcic_handle *); 136 STATIC void pccbb_pcmcia_detach_card(struct pcic_handle *, int); 137 STATIC void pccbb_pcmcia_deactivate_card(struct pcic_handle *); 138 #endif 139 140 STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int); 141 STATIC int pccbb_power(cardbus_chipset_tag_t, int); 142 STATIC int pccbb_cardenable(struct pccbb_softc * sc, int function); 143 #if !rbus 144 static int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 145 static int pccbb_io_close(cardbus_chipset_tag_t, int); 146 static int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 147 static int pccbb_mem_close(cardbus_chipset_tag_t, int); 148 #endif /* !rbus */ 149 static void *pccbb_intr_establish(struct pccbb_softc *, int irq, 150 int level, int (*ih) (void *), void *sc); 151 static void pccbb_intr_disestablish(struct pccbb_softc *, void *ih); 152 153 static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t, int irq, 154 int level, int (*ih) (void *), void *sc); 155 static void pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih); 156 157 static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t, int, int); 158 static void pccbb_free_tag(cardbus_chipset_tag_t, cardbustag_t); 159 static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t, cardbustag_t, int); 160 static void pccbb_conf_write(cardbus_chipset_tag_t, cardbustag_t, int, 161 cardbusreg_t); 162 static void pccbb_chipinit(struct pccbb_softc *); 163 164 STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 165 struct pcmcia_mem_handle *); 166 STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t, 167 struct pcmcia_mem_handle *); 168 STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 169 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *); 170 STATIC void pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t, int); 171 STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 172 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 173 STATIC void pccbb_pcmcia_io_free(pcmcia_chipset_handle_t, 174 struct pcmcia_io_handle *); 175 STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 176 bus_size_t, struct pcmcia_io_handle *, int *); 177 STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t, int); 178 STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t, 179 struct pcmcia_function *, int, int (*)(void *), void *); 180 STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t, void *); 181 STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t); 182 STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t); 183 STATIC void pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t, int); 184 STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch); 185 186 static int pccbb_pcmcia_wait_ready(struct pcic_handle *); 187 static void pccbb_pcmcia_delay(struct pcic_handle *, int, const char *); 188 189 static void pccbb_pcmcia_do_io_map(struct pcic_handle *, int); 190 static void pccbb_pcmcia_do_mem_map(struct pcic_handle *, int); 191 static void pccbb_powerhook(int, void *); 192 193 /* bus-space allocation and deallocation functions */ 194 #if rbus 195 196 static int pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t, rbus_tag_t, 197 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 198 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp); 199 static int pccbb_rbus_cb_space_free(cardbus_chipset_tag_t, rbus_tag_t, 200 bus_space_handle_t, bus_size_t); 201 202 #endif /* rbus */ 203 204 #if rbus 205 206 static int pccbb_open_win(struct pccbb_softc *, bus_space_tag_t, 207 bus_addr_t, bus_size_t, bus_space_handle_t, int flags); 208 static int pccbb_close_win(struct pccbb_softc *, bus_space_tag_t, 209 bus_space_handle_t, bus_size_t); 210 static int pccbb_winlist_insert(struct pccbb_win_chain_head *, bus_addr_t, 211 bus_size_t, bus_space_handle_t, int); 212 static int pccbb_winlist_delete(struct pccbb_win_chain_head *, 213 bus_space_handle_t, bus_size_t); 214 static void pccbb_winset(bus_addr_t align, struct pccbb_softc *, 215 bus_space_tag_t); 216 void pccbb_winlist_show(struct pccbb_win_chain *); 217 218 #endif /* rbus */ 219 220 /* for config_defer */ 221 static void pccbb_pci_callback(struct device *); 222 223 #if defined SHOW_REGS 224 static void cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, 225 bus_space_tag_t memt, bus_space_handle_t memh); 226 #endif 227 228 CFATTACH_DECL(cbb_pci, sizeof(struct pccbb_softc), 229 pcicbbmatch, pccbbattach, NULL, NULL); 230 231 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 232 pccbb_pcmcia_mem_alloc, 233 pccbb_pcmcia_mem_free, 234 pccbb_pcmcia_mem_map, 235 pccbb_pcmcia_mem_unmap, 236 pccbb_pcmcia_io_alloc, 237 pccbb_pcmcia_io_free, 238 pccbb_pcmcia_io_map, 239 pccbb_pcmcia_io_unmap, 240 pccbb_pcmcia_intr_establish, 241 pccbb_pcmcia_intr_disestablish, 242 pccbb_pcmcia_socket_enable, 243 pccbb_pcmcia_socket_disable, 244 pccbb_pcmcia_socket_settype, 245 pccbb_pcmcia_card_detect 246 }; 247 248 #if rbus 249 static struct cardbus_functions pccbb_funcs = { 250 pccbb_rbus_cb_space_alloc, 251 pccbb_rbus_cb_space_free, 252 pccbb_cb_intr_establish, 253 pccbb_cb_intr_disestablish, 254 pccbb_ctrl, 255 pccbb_power, 256 pccbb_make_tag, 257 pccbb_free_tag, 258 pccbb_conf_read, 259 pccbb_conf_write, 260 }; 261 #else 262 static struct cardbus_functions pccbb_funcs = { 263 pccbb_ctrl, 264 pccbb_power, 265 pccbb_mem_open, 266 pccbb_mem_close, 267 pccbb_io_open, 268 pccbb_io_close, 269 pccbb_cb_intr_establish, 270 pccbb_cb_intr_disestablish, 271 pccbb_make_tag, 272 pccbb_conf_read, 273 pccbb_conf_write, 274 }; 275 #endif 276 277 int 278 pcicbbmatch(struct device *parent, struct cfdata *match, void *aux) 279 { 280 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 281 282 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 283 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 284 PCI_INTERFACE(pa->pa_class) == 0) { 285 return 1; 286 } 287 288 return 0; 289 } 290 291 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 292 | ((prod) << PCI_PRODUCT_SHIFT)) 293 294 const struct yenta_chipinfo { 295 pcireg_t yc_id; /* vendor tag | product tag */ 296 int yc_chiptype; 297 int yc_flags; 298 } yc_chipsets[] = { 299 /* Texas Instruments chips */ 300 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 301 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 302 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 303 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 304 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI125X, 305 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 306 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 307 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 308 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 309 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 310 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 311 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 312 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI125X, 313 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 314 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI125X, 315 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 316 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 317 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 318 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 319 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 320 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 321 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 322 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI125X, 323 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 324 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 325 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 326 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1520), CB_TI12XX, 327 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 328 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4410YENTA), CB_TI12XX, 329 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 330 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4520YENTA), CB_TI12XX, 331 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 332 333 /* Ricoh chips */ 334 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 335 PCCBB_PCMCIA_MEM_32}, 336 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 337 PCCBB_PCMCIA_MEM_32}, 338 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 339 PCCBB_PCMCIA_MEM_32}, 340 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 341 PCCBB_PCMCIA_MEM_32}, 342 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 343 PCCBB_PCMCIA_MEM_32}, 344 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 345 PCCBB_PCMCIA_MEM_32}, 346 347 /* Toshiba products */ 348 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 349 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 350 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 351 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 352 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 353 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 354 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 355 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 356 357 /* Cirrus Logic products */ 358 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 359 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 360 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 361 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 362 363 /* sentinel, or Generic chip */ 364 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 365 }; 366 367 static int 368 cb_chipset(u_int32_t pci_id, int *flagp) 369 { 370 const struct yenta_chipinfo *yc; 371 372 /* Loop over except the last default entry. */ 373 for (yc = yc_chipsets; yc < yc_chipsets + 374 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 375 if (pci_id == yc->yc_id) 376 break; 377 378 if (flagp != NULL) 379 *flagp = yc->yc_flags; 380 381 return (yc->yc_chiptype); 382 } 383 384 static void 385 pccbb_shutdown(void *arg) 386 { 387 struct pccbb_softc *sc = arg; 388 pcireg_t command; 389 390 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 391 392 /* 393 * turn off power 394 * 395 * XXX - do not turn off power if chipset is TI 113X because 396 * only TI 1130 with PowerMac 2400 hangs in pccbb_power(). 397 */ 398 if (sc->sc_chipset != CB_TI113X) { 399 pccbb_power((cardbus_chipset_tag_t)sc, 400 CARDBUS_VCC_0V | CARDBUS_VPP_0V); 401 } 402 403 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 404 0); 405 406 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 407 408 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 409 PCI_COMMAND_MASTER_ENABLE); 410 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 411 412 } 413 414 void 415 pccbbattach(struct device *parent, struct device *self, void *aux) 416 { 417 struct pccbb_softc *sc = (void *)self; 418 struct pci_attach_args *pa = aux; 419 pci_chipset_tag_t pc = pa->pa_pc; 420 pcireg_t busreg, reg, sock_base; 421 bus_addr_t sockbase; 422 char devinfo[256]; 423 int flags; 424 int pwrmgt_offs; 425 426 #ifdef __HAVE_PCCBB_ATTACH_HOOK 427 pccbb_attach_hook(parent, self, pa); 428 #endif 429 430 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 431 432 pci_devinfo(pa->pa_id, 0, 0, devinfo, sizeof(devinfo)); 433 printf(": %s (rev. 0x%02x)", devinfo, PCI_REVISION(pa->pa_class)); 434 DPRINTF((" (chipflags %x)", flags)); 435 printf("\n"); 436 437 TAILQ_INIT(&sc->sc_memwindow); 438 TAILQ_INIT(&sc->sc_iowindow); 439 440 #if rbus 441 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 442 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 443 444 #if 0 445 printf("pa->pa_memt: %08x vs rbus_mem->rb_bt: %08x\n", 446 pa->pa_memt, sc->sc_rbus_memt->rb_bt); 447 #endif 448 #endif /* rbus */ 449 450 sc->sc_flags &= ~CBB_MEMHMAPPED; 451 452 /* power management: set D0 state */ 453 sc->sc_pwrmgt_offs = 0; 454 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, 455 &pwrmgt_offs, 0)) { 456 reg = pci_conf_read(pc, pa->pa_tag, pwrmgt_offs + PCI_PMCSR); 457 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 458 reg & 0x100 /* PCI_PMCSR_PME_EN */) { 459 reg &= ~PCI_PMCSR_STATE_MASK; 460 reg |= PCI_PMCSR_STATE_D0; 461 reg &= ~(0x100 /* PCI_PMCSR_PME_EN */); 462 pci_conf_write(pc, pa->pa_tag, 463 pwrmgt_offs + PCI_PMCSR, reg); 464 } 465 466 sc->sc_pwrmgt_offs = pwrmgt_offs; 467 } 468 469 /* 470 * MAP socket registers and ExCA registers on memory-space 471 * When no valid address is set on socket base registers (on pci 472 * config space), get it not polite way. 473 */ 474 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 475 476 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 477 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 478 /* The address must be valid. */ 479 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 480 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL)) { 481 printf("%s: can't map socket base address 0x%lx\n", 482 sc->sc_dev.dv_xname, (unsigned long)sock_base); 483 /* 484 * I think it's funny: socket base registers must be 485 * mapped on memory space, but ... 486 */ 487 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 488 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 489 NULL)) { 490 printf("%s: can't map socket base address" 491 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 492 (unsigned long)sockbase); 493 /* give up... allocate reg space via rbus. */ 494 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 495 } else 496 sc->sc_flags |= CBB_MEMHMAPPED; 497 } else { 498 DPRINTF(("%s: socket base address 0x%lx\n", 499 sc->sc_dev.dv_xname, (unsigned long)sockbase)); 500 sc->sc_flags |= CBB_MEMHMAPPED; 501 } 502 } 503 504 sc->sc_mem_start = 0; /* XXX */ 505 sc->sc_mem_end = 0xffffffff; /* XXX */ 506 507 /* 508 * When interrupt isn't routed correctly, give up probing cbb and do 509 * not kill pcic-compatible port. 510 * 511 * However, if we are using an ioapic, avoid this check -- pa_intrline 512 * may well be zero, with the interrupt routed through the apic. 513 */ 514 515 #if NIOAPIC == 0 && NACPI == 0 516 if ((0 == pa->pa_intrline) || (255 == pa->pa_intrline)) { 517 printf("%s: NOT USED because of unconfigured interrupt\n", 518 sc->sc_dev.dv_xname); 519 return; 520 } 521 #endif 522 523 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 524 525 /* pccbb_machdep.c end */ 526 527 #if defined CBB_DEBUG 528 { 529 static const char *intrname[] = { "NON", "A", "B", "C", "D" }; 530 printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname, 531 intrname[pa->pa_intrpin], pa->pa_intrline); 532 } 533 #endif 534 535 /* setup softc */ 536 sc->sc_pc = pc; 537 sc->sc_iot = pa->pa_iot; 538 sc->sc_memt = pa->pa_memt; 539 sc->sc_dmat = pa->pa_dmat; 540 sc->sc_tag = pa->pa_tag; 541 sc->sc_function = pa->pa_function; 542 sc->sc_sockbase = sock_base; 543 sc->sc_busnum = busreg; 544 545 memcpy(&sc->sc_pa, pa, sizeof(*pa)); 546 547 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 548 549 shutdownhook_establish(pccbb_shutdown, sc); 550 551 /* Disable legacy register mapping. */ 552 switch (sc->sc_chipset) { 553 case CB_RX5C46X: /* fallthrough */ 554 #if 0 555 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 556 case CB_RX5C47X: 557 #endif 558 /* 559 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 560 * cannot be disabled by substituting 0 into PCI_LEGACY 561 * register. Ricoh CardBus bridges have special bits on Bridge 562 * control reg (addr 0x3e on PCI config space). 563 */ 564 reg = pci_conf_read(pc, pa->pa_tag, PCI_BCR_INTR); 565 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 566 pci_conf_write(pc, pa->pa_tag, PCI_BCR_INTR, reg); 567 break; 568 569 default: 570 /* XXX I don't know proper way to kill legacy I/O. */ 571 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 572 break; 573 } 574 575 config_defer(self, pccbb_pci_callback); 576 } 577 578 579 580 581 /* 582 * static void pccbb_pci_callback(struct device *self) 583 * 584 * The actual attach routine: get memory space for YENTA register 585 * space, setup YENTA register and route interrupt. 586 * 587 * This function should be deferred because this device may obtain 588 * memory space dynamically. This function must avoid obtaining 589 * memory area which has already kept for another device. 590 */ 591 static void 592 pccbb_pci_callback(struct device *self) 593 { 594 struct pccbb_softc *sc = (void *)self; 595 pci_chipset_tag_t pc = sc->sc_pc; 596 pci_intr_handle_t ih; 597 const char *intrstr = NULL; 598 bus_addr_t sockbase; 599 struct cbslot_attach_args cba; 600 struct pcmciabus_attach_args paa; 601 struct cardslot_attach_args caa; 602 struct cardslot_softc *csc; 603 604 if (!(sc->sc_flags & CBB_MEMHMAPPED)) { 605 /* The socket registers aren't mapped correctly. */ 606 #if rbus 607 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 608 (sc->sc_chipset == CB_RX5C47X 609 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 610 0, &sockbase, &sc->sc_base_memh)) { 611 return; 612 } 613 sc->sc_base_memt = sc->sc_memt; 614 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 615 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 616 sc->sc_dev.dv_xname, (unsigned long)sockbase, 617 (unsigned long)pci_conf_read(pc, sc->sc_tag, 618 PCI_SOCKBASE))); 619 #else 620 sc->sc_base_memt = sc->sc_memt; 621 #if !defined CBB_PCI_BASE 622 #define CBB_PCI_BASE 0x20000000 623 #endif 624 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 625 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 626 /* cannot allocate memory space */ 627 return; 628 } 629 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 630 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 631 sc->sc_dev.dv_xname, (unsigned long)sock_base, 632 (unsigned long)pci_conf_read(pc, 633 sc->sc_tag, PCI_SOCKBASE))); 634 sc->sc_sockbase = sockbase; 635 #endif 636 sc->sc_flags |= CBB_MEMHMAPPED; 637 } 638 639 /* bus bridge initialization */ 640 pccbb_chipinit(sc); 641 642 /* clear data structure for child device interrupt handlers */ 643 LIST_INIT(&sc->sc_pil); 644 sc->sc_pil_intr_enable = 1; 645 646 /* Map and establish the interrupt. */ 647 if (pci_intr_map(&sc->sc_pa, &ih)) { 648 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 649 return; 650 } 651 intrstr = pci_intr_string(pc, ih); 652 653 /* 654 * XXX pccbbintr should be called under the priority lower 655 * than any other hard interupts. 656 */ 657 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 658 659 if (sc->sc_ih == NULL) { 660 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 661 if (intrstr != NULL) { 662 printf(" at %s", intrstr); 663 } 664 printf("\n"); 665 return; 666 } 667 668 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 669 powerhook_establish(sc->sc_dev.dv_xname, pccbb_powerhook, sc); 670 671 { 672 u_int32_t sockstat; 673 674 sockstat = bus_space_read_4(sc->sc_base_memt, 675 sc->sc_base_memh, CB_SOCKET_STAT); 676 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 677 sc->sc_flags |= CBB_CARDEXIST; 678 } 679 } 680 681 /* 682 * attach cardbus 683 */ 684 { 685 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 686 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 687 688 /* initialize cbslot_attach */ 689 cba.cba_busname = "cardbus"; 690 cba.cba_iot = sc->sc_iot; 691 cba.cba_memt = sc->sc_memt; 692 cba.cba_dmat = sc->sc_dmat; 693 cba.cba_bus = (busreg >> 8) & 0x0ff; 694 cba.cba_cc = (void *)sc; 695 cba.cba_cf = &pccbb_funcs; 696 cba.cba_intrline = sc->sc_pa.pa_intrline; 697 698 #if rbus 699 cba.cba_rbus_iot = sc->sc_rbus_iot; 700 cba.cba_rbus_memt = sc->sc_rbus_memt; 701 #endif 702 703 cba.cba_cacheline = PCI_CACHELINE(bhlc); 704 cba.cba_lattimer = PCI_CB_LATENCY(busreg); 705 706 if (bootverbose) { 707 printf("%s: cacheline 0x%x lattimer 0x%x\n", 708 sc->sc_dev.dv_xname, cba.cba_cacheline, 709 cba.cba_lattimer); 710 printf("%s: bhlc 0x%x lscp 0x%x\n", 711 sc->sc_dev.dv_xname, bhlc, busreg); 712 } 713 #if defined SHOW_REGS 714 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 715 sc->sc_base_memh); 716 #endif 717 } 718 719 pccbb_pcmcia_attach_setup(sc, &paa); 720 caa.caa_cb_attach = NULL; 721 if (cba.cba_bus == 0) 722 printf("%s: secondary bus number uninitialized; try PCI_BUS_FIXUP\n", sc->sc_dev.dv_xname); 723 else 724 caa.caa_cb_attach = &cba; 725 caa.caa_16_attach = &paa; 726 caa.caa_ph = &sc->sc_pcmcia_h; 727 728 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 729 DPRINTF(("%s: found cardslot\n", __func__)); 730 sc->sc_csc = csc; 731 } 732 733 return; 734 } 735 736 737 738 739 740 /* 741 * static void pccbb_chipinit(struct pccbb_softc *sc) 742 * 743 * This function initialize YENTA chip registers listed below: 744 * 1) PCI command reg, 745 * 2) PCI and CardBus latency timer, 746 * 3) route PCI interrupt, 747 * 4) close all memory and io windows. 748 * 5) turn off bus power. 749 * 6) card detect and power cycle interrupts on. 750 * 7) clear interrupt 751 */ 752 static void 753 pccbb_chipinit(struct pccbb_softc *sc) 754 { 755 pci_chipset_tag_t pc = sc->sc_pc; 756 pcitag_t tag = sc->sc_tag; 757 bus_space_tag_t bmt = sc->sc_base_memt; 758 bus_space_handle_t bmh = sc->sc_base_memh; 759 pcireg_t reg; 760 761 /* 762 * Set PCI command reg. 763 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 764 */ 765 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 766 /* I believe it is harmless. */ 767 reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 768 PCI_COMMAND_MASTER_ENABLE); 769 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg); 770 771 /* 772 * Set CardBus latency timer. 773 */ 774 reg = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 775 if (PCI_CB_LATENCY(reg) < 0x20) { 776 reg &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 777 reg |= (0x20 << PCI_CB_LATENCY_SHIFT); 778 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, reg); 779 } 780 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 781 PCI_CB_LATENCY(reg), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 782 783 /* 784 * Set PCI latency timer. 785 */ 786 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 787 if (PCI_LATTIMER(reg) < 0x10) { 788 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 789 reg |= (0x10 << PCI_LATTIMER_SHIFT); 790 pci_conf_write(pc, tag, PCI_BHLC_REG, reg); 791 } 792 DPRINTF(("PCI latency timer 0x%x (%x)\n", 793 PCI_LATTIMER(reg), pci_conf_read(pc, tag, PCI_BHLC_REG))); 794 795 796 /* Route functional interrupts to PCI. */ 797 reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 798 reg |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 799 reg |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 800 reg |= CB_BCR_RESET_ENABLE; /* assert reset */ 801 pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 802 803 switch (sc->sc_chipset) { 804 case CB_TI113X: 805 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 806 /* This bit is shared, but may read as 0 on some chips, so set 807 it explicitly on both functions. */ 808 reg |= PCI113X_CBCTRL_PCI_IRQ_ENA; 809 /* CSC intr enable */ 810 reg |= PCI113X_CBCTRL_PCI_CSC; 811 /* functional intr prohibit | prohibit ISA routing */ 812 reg &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 813 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 814 break; 815 816 case CB_TI12XX: 817 /* 818 * Some TI 12xx (and [14][45]xx) based pci cards 819 * sometimes have issues with the MFUNC register not 820 * being initialized due to a bad EEPROM on board. 821 * Laptops that this matters on have this register 822 * properly initialized. 823 * 824 * The TI125X parts have a different register. 825 */ 826 reg = pci_conf_read(pc, tag, PCI12XX_MFUNC); 827 if (reg == 0) { 828 reg &= ~PCI12XX_MFUNC_PIN0; 829 reg |= PCI12XX_MFUNC_PIN0_INTA; 830 if ((pci_conf_read(pc, tag, PCI_SYSCTRL) & 831 PCI12XX_SYSCTRL_INTRTIE) == 0) { 832 reg &= ~PCI12XX_MFUNC_PIN1; 833 reg |= PCI12XX_MFUNC_PIN1_INTB; 834 } 835 pci_conf_write(pc, tag, PCI12XX_MFUNC, reg); 836 } 837 /* fallthrough */ 838 839 case CB_TI125X: 840 /* 841 * Disable zoom video. Some machines initialize this 842 * improperly and experience has shown that this helps 843 * prevent strange behavior. 844 */ 845 pci_conf_write(pc, tag, PCI12XX_MMCTRL, 0); 846 847 reg = pci_conf_read(pc, tag, PCI_SYSCTRL); 848 reg |= PCI12XX_SYSCTRL_VCCPROT; 849 pci_conf_write(pc, tag, PCI_SYSCTRL, reg); 850 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 851 reg |= PCI12XX_CBCTRL_CSC; 852 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 853 break; 854 855 case CB_TOPIC95B: 856 reg = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 857 reg |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 858 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, reg); 859 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 860 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 861 sc->sc_dev.dv_xname, reg)); 862 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 863 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 864 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 865 DPRINTF(("0x%x\n", reg)); 866 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 867 break; 868 869 case CB_TOPIC97: 870 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 871 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 872 sc->sc_dev.dv_xname, reg)); 873 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 874 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 875 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 876 reg |= TOPIC97_SLOT_CTRL_PCIINT; 877 reg &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 878 DPRINTF(("0x%x\n", reg)); 879 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 880 /* make sure to assert LV card support bits */ 881 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 882 0x800 + 0x3e, 883 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 884 0x800 + 0x3e) | 0x03); 885 break; 886 } 887 888 /* Close all memory and I/O windows. */ 889 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 890 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 891 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 892 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 893 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 894 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 895 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 896 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 897 898 /* reset 16-bit pcmcia bus */ 899 bus_space_write_1(bmt, bmh, 0x800 + PCIC_INTR, 900 bus_space_read_1(bmt, bmh, 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 901 902 /* turn off power */ 903 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 904 905 /* CSC Interrupt: Card detect and power cycle interrupts on */ 906 reg = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 907 reg |= CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; 908 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, reg); 909 /* reset interrupt */ 910 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 911 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 912 } 913 914 915 916 917 /* 918 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 919 * struct pcmciabus_attach_args *paa) 920 * 921 * This function attaches 16-bit PCcard bus. 922 */ 923 STATIC void 924 pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 925 struct pcmciabus_attach_args *paa) 926 { 927 struct pcic_handle *ph = &sc->sc_pcmcia_h; 928 #if rbus 929 rbus_tag_t rb; 930 #endif 931 932 /* initialize pcmcia part in pccbb_softc */ 933 ph->ph_parent = (struct device *)sc; 934 ph->sock = sc->sc_function; 935 ph->flags = 0; 936 ph->shutdown = 0; 937 ph->ih_irq = sc->sc_pa.pa_intrline; 938 ph->ph_bus_t = sc->sc_base_memt; 939 ph->ph_bus_h = sc->sc_base_memh; 940 ph->ph_read = pccbb_pcmcia_read; 941 ph->ph_write = pccbb_pcmcia_write; 942 sc->sc_pct = &pccbb_pcmcia_funcs; 943 944 /* 945 * We need to do a few things here: 946 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 947 * setting the IRQ numbers to 0. 948 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 949 * routing of CSC interrupts (e.g. card removal) to PCI while in 950 * PCMCIA mode. We just leave this set all the time. 951 * 3) Enable card insertion/removal interrupts in case the chip also 952 * needs that while in PCMCIA mode. 953 * 4) Clear any pending CSC interrupt. 954 */ 955 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE); 956 if (sc->sc_chipset == CB_TI113X) { 957 Pcic_write(ph, PCIC_CSC_INTR, 0); 958 } else { 959 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 960 Pcic_read(ph, PCIC_CSC); 961 } 962 963 /* initialize pcmcia bus attachment */ 964 paa->paa_busname = "pcmcia"; 965 paa->pct = sc->sc_pct; 966 paa->pch = ph; 967 paa->iobase = 0; /* I don't use them */ 968 paa->iosize = 0; 969 #if rbus 970 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 971 paa->iobase = rb->rb_start + rb->rb_offset; 972 paa->iosize = rb->rb_end - rb->rb_start; 973 #endif 974 975 return; 976 } 977 978 #if 0 979 STATIC void 980 pccbb_pcmcia_attach_card(struct pcic_handle *ph) 981 { 982 if (ph->flags & PCIC_FLAG_CARDP) { 983 panic("pccbb_pcmcia_attach_card: already attached"); 984 } 985 986 /* call the MI attach function */ 987 pcmcia_card_attach(ph->pcmcia); 988 989 ph->flags |= PCIC_FLAG_CARDP; 990 } 991 992 STATIC void 993 pccbb_pcmcia_detach_card(struct pcic_handle *ph, int flags) 994 { 995 if (!(ph->flags & PCIC_FLAG_CARDP)) { 996 panic("pccbb_pcmcia_detach_card: already detached"); 997 } 998 999 ph->flags &= ~PCIC_FLAG_CARDP; 1000 1001 /* call the MI detach function */ 1002 pcmcia_card_detach(ph->pcmcia, flags); 1003 } 1004 #endif 1005 1006 /* 1007 * int pccbbintr(arg) 1008 * void *arg; 1009 * This routine handles the interrupt from Yenta PCI-CardBus bridge 1010 * itself. 1011 */ 1012 int 1013 pccbbintr(void *arg) 1014 { 1015 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1016 u_int32_t sockevent, sockstate; 1017 bus_space_tag_t memt = sc->sc_base_memt; 1018 bus_space_handle_t memh = sc->sc_base_memh; 1019 struct pcic_handle *ph = &sc->sc_pcmcia_h; 1020 1021 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 1022 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 1023 Pcic_read(ph, PCIC_CSC); 1024 1025 if (sockevent == 0) { 1026 /* This intr is not for me: it may be for my child devices. */ 1027 if (sc->sc_pil_intr_enable) { 1028 return pccbbintr_function(sc); 1029 } else { 1030 return 0; 1031 } 1032 } 1033 1034 aprint_debug("%s: enter sockevent %" PRIx32 "\n", __func__, sockevent); 1035 1036 if (sockevent & CB_SOCKET_EVENT_CD) { 1037 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1038 if (0x00 != (sockstate & CB_SOCKET_STAT_CD)) { 1039 /* A card should be removed. */ 1040 if (sc->sc_flags & CBB_CARDEXIST) { 1041 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 1042 sockevent)); 1043 DPRINTF((" card removed, 0x%08x\n", sockstate)); 1044 sc->sc_flags &= ~CBB_CARDEXIST; 1045 if (sc->sc_csc->sc_status & 1046 CARDSLOT_STATUS_CARD_16) { 1047 #if 0 1048 struct pcic_handle *ph = 1049 &sc->sc_pcmcia_h; 1050 1051 pcmcia_card_deactivate(ph->pcmcia); 1052 pccbb_pcmcia_socket_disable(ph); 1053 pccbb_pcmcia_detach_card(ph, 1054 DETACH_FORCE); 1055 #endif 1056 cardslot_event_throw(sc->sc_csc, 1057 CARDSLOT_EVENT_REMOVAL_16); 1058 } else if (sc->sc_csc->sc_status & 1059 CARDSLOT_STATUS_CARD_CB) { 1060 /* Cardbus intr removed */ 1061 cardslot_event_throw(sc->sc_csc, 1062 CARDSLOT_EVENT_REMOVAL_CB); 1063 } 1064 } else if (sc->sc_flags & CBB_INSERTING) { 1065 sc->sc_flags &= ~CBB_INSERTING; 1066 callout_stop(&sc->sc_insert_ch); 1067 } 1068 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 1069 /* 1070 * The pccbbintr may called from powerdown hook when 1071 * the system resumed, to detect the card 1072 * insertion/removal during suspension. 1073 */ 1074 (sc->sc_flags & CBB_CARDEXIST) == 0) { 1075 if (sc->sc_flags & CBB_INSERTING) { 1076 callout_stop(&sc->sc_insert_ch); 1077 } 1078 callout_reset(&sc->sc_insert_ch, hz / 5, 1079 pci113x_insert, sc); 1080 sc->sc_flags |= CBB_INSERTING; 1081 } 1082 } 1083 1084 if (sockevent & CB_SOCKET_EVENT_POWER) { 1085 DPRINTF(("Powercycling because of socket event\n")); 1086 /* XXX: Does not happen when attaching a 16-bit card */ 1087 sc->sc_pwrcycle++; 1088 wakeup(&sc->sc_pwrcycle); 1089 } 1090 1091 return (1); 1092 } 1093 1094 /* 1095 * static int pccbbintr_function(struct pccbb_softc *sc) 1096 * 1097 * This function calls each interrupt handler registered at the 1098 * bridge. The interrupt handlers are called in registered order. 1099 */ 1100 static int 1101 pccbbintr_function(struct pccbb_softc *sc) 1102 { 1103 int retval = 0, val; 1104 struct pccbb_intrhand_list *pil; 1105 int s, splchanged; 1106 1107 for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1108 pil = LIST_NEXT(pil, pil_next)) { 1109 /* 1110 * XXX priority change. gross. I use if-else 1111 * sentense instead of switch-case sentense because of 1112 * avoiding duplicate case value error. More than one 1113 * IPL_XXX use same value. It depends on 1114 * implimentation. 1115 */ 1116 splchanged = 1; 1117 if (pil->pil_level == IPL_SERIAL) { 1118 s = splserial(); 1119 } else if (pil->pil_level == IPL_HIGH) { 1120 s = splhigh(); 1121 } else if (pil->pil_level == IPL_CLOCK) { 1122 s = splclock(); 1123 } else if (pil->pil_level == IPL_AUDIO) { 1124 s = splaudio(); 1125 } else if (pil->pil_level == IPL_VM) { 1126 s = splvm(); 1127 } else if (pil->pil_level == IPL_TTY) { 1128 s = spltty(); 1129 } else if (pil->pil_level == IPL_SOFTSERIAL) { 1130 s = splsoftserial(); 1131 } else if (pil->pil_level == IPL_NET) { 1132 s = splnet(); 1133 } else { 1134 s = 0; /* XXX: gcc */ 1135 splchanged = 0; 1136 /* XXX: ih lower than IPL_BIO runs w/ IPL_BIO. */ 1137 } 1138 1139 val = (*pil->pil_func)(pil->pil_arg); 1140 1141 if (splchanged != 0) { 1142 splx(s); 1143 } 1144 1145 retval = retval == 1 ? 1 : 1146 retval == 0 ? val : val != 0 ? val : retval; 1147 } 1148 1149 return retval; 1150 } 1151 1152 static void 1153 pci113x_insert(void *arg) 1154 { 1155 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1156 u_int32_t sockevent, sockstate; 1157 1158 if (!(sc->sc_flags & CBB_INSERTING)) { 1159 /* We add a card only under inserting state. */ 1160 return; 1161 } 1162 sc->sc_flags &= ~CBB_INSERTING; 1163 1164 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1165 CB_SOCKET_EVENT); 1166 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1167 CB_SOCKET_STAT); 1168 1169 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1170 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1171 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1172 sc->sc_flags |= CBB_CARDEXIST; 1173 /* call pccard interrupt handler here */ 1174 if (sockstate & CB_SOCKET_STAT_16BIT) { 1175 /* 16-bit card found */ 1176 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1177 cardslot_event_throw(sc->sc_csc, 1178 CARDSLOT_EVENT_INSERTION_16); 1179 } else if (sockstate & CB_SOCKET_STAT_CB) { 1180 /* cardbus card found */ 1181 /* cardbus_attach_card(sc->sc_csc); */ 1182 cardslot_event_throw(sc->sc_csc, 1183 CARDSLOT_EVENT_INSERTION_CB); 1184 } else { 1185 /* who are you? */ 1186 } 1187 } else { 1188 callout_reset(&sc->sc_insert_ch, hz / 10, 1189 pci113x_insert, sc); 1190 } 1191 } 1192 1193 #define PCCBB_PCMCIA_OFFSET 0x800 1194 static u_int8_t 1195 pccbb_pcmcia_read(struct pcic_handle *ph, int reg) 1196 { 1197 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1198 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1199 1200 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1201 PCCBB_PCMCIA_OFFSET + reg); 1202 } 1203 1204 static void 1205 pccbb_pcmcia_write(struct pcic_handle *ph, int reg, u_int8_t val) 1206 { 1207 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1208 val); 1209 1210 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1211 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1212 } 1213 1214 /* 1215 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1216 */ 1217 STATIC int 1218 pccbb_ctrl(cardbus_chipset_tag_t ct, int command) 1219 { 1220 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1221 1222 switch (command) { 1223 case CARDBUS_CD: 1224 if (2 == pccbb_detect_card(sc)) { 1225 int retval = 0; 1226 int status = cb_detect_voltage(sc); 1227 if (PCCARD_VCC_5V & status) { 1228 retval |= CARDBUS_5V_CARD; 1229 } 1230 if (PCCARD_VCC_3V & status) { 1231 retval |= CARDBUS_3V_CARD; 1232 } 1233 if (PCCARD_VCC_XV & status) { 1234 retval |= CARDBUS_XV_CARD; 1235 } 1236 if (PCCARD_VCC_YV & status) { 1237 retval |= CARDBUS_YV_CARD; 1238 } 1239 return retval; 1240 } else { 1241 return 0; 1242 } 1243 case CARDBUS_RESET: 1244 return cb_reset(sc); 1245 case CARDBUS_IO_ENABLE: /* fallthrough */ 1246 case CARDBUS_IO_DISABLE: /* fallthrough */ 1247 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1248 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1249 case CARDBUS_BM_ENABLE: /* fallthrough */ 1250 case CARDBUS_BM_DISABLE: /* fallthrough */ 1251 /* XXX: I think we don't need to call this function below. */ 1252 return pccbb_cardenable(sc, command); 1253 } 1254 1255 return 0; 1256 } 1257 1258 /* 1259 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1260 * This function returns true when it succeeds and returns false when 1261 * it fails. 1262 */ 1263 STATIC int 1264 pccbb_power(cardbus_chipset_tag_t ct, int command) 1265 { 1266 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1267 u_int32_t status, osock_ctrl, sock_ctrl, reg_ctrl; 1268 bus_space_tag_t memt = sc->sc_base_memt; 1269 bus_space_handle_t memh = sc->sc_base_memh; 1270 int on = 0, pwrcycle, s, times; 1271 struct timeval before, after, diff; 1272 1273 DPRINTF(("pccbb_power: %s and %s [0x%x]\n", 1274 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1275 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1276 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1277 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1278 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1279 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1280 "UNKNOWN", 1281 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1282 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1283 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1284 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1285 "UNKNOWN", command)); 1286 1287 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1288 osock_ctrl = sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1289 1290 switch (command & CARDBUS_VCCMASK) { 1291 case CARDBUS_VCC_UC: 1292 break; 1293 case CARDBUS_VCC_5V: 1294 on++; 1295 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1296 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1297 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1298 } else { 1299 printf("%s: BAD voltage request: no 5 V card\n", 1300 sc->sc_dev.dv_xname); 1301 return 0; 1302 } 1303 break; 1304 case CARDBUS_VCC_3V: 1305 on++; 1306 if (CB_SOCKET_STAT_3VCARD & status) { 1307 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1308 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1309 } else { 1310 printf("%s: BAD voltage request: no 3.3 V card\n", 1311 sc->sc_dev.dv_xname); 1312 return 0; 1313 } 1314 break; 1315 case CARDBUS_VCC_0V: 1316 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1317 break; 1318 default: 1319 return 0; /* power NEVER changed */ 1320 } 1321 1322 switch (command & CARDBUS_VPPMASK) { 1323 case CARDBUS_VPP_UC: 1324 break; 1325 case CARDBUS_VPP_0V: 1326 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1327 break; 1328 case CARDBUS_VPP_VCC: 1329 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1330 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1331 break; 1332 case CARDBUS_VPP_12V: 1333 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1334 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1335 break; 1336 } 1337 1338 pwrcycle = sc->sc_pwrcycle; 1339 aprint_debug("%s: osock_ctrl %#" PRIx32 " sock_ctrl %#" PRIx32 "\n", 1340 device_xname(&sc->sc_dev), osock_ctrl, sock_ctrl); 1341 1342 microtime(&before); 1343 s = splbio(); 1344 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1345 1346 /* 1347 * Wait as long as 200ms for a power-cycle interrupt. If 1348 * interrupts are enabled, but the socket has already 1349 * changed to the desired status, keep waiting for the 1350 * interrupt. "Consuming" the interrupt in this way keeps 1351 * the interrupt from prematurely waking some subsequent 1352 * pccbb_power call. 1353 * 1354 * XXX Not every bridge interrupts on the ->OFF transition. 1355 * XXX That's ok, we will time-out after 200ms. 1356 * 1357 * XXX The power cycle event will never happen when attaching 1358 * XXX a 16-bit card. That's ok, we will time-out after 1359 * XXX 200ms. 1360 */ 1361 for (times = 5; --times >= 0; ) { 1362 if (cold) 1363 DELAY(40 * 1000); 1364 else { 1365 (void)tsleep(&sc->sc_pwrcycle, PWAIT, "pccpwr", 1366 hz / 25); 1367 if (pwrcycle == sc->sc_pwrcycle) 1368 continue; 1369 } 1370 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1371 if ((status & CB_SOCKET_STAT_PWRCYCLE) != 0 && on) 1372 break; 1373 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0 && !on) 1374 break; 1375 } 1376 splx(s); 1377 microtime(&after); 1378 timersub(&after, &before, &diff); 1379 aprint_debug("%s: wait took%s %ld.%06lds\n", sc->sc_dev.dv_xname, 1380 (on && times < 0) ? " too long" : "", diff.tv_sec, diff.tv_usec); 1381 1382 /* 1383 * Ok, wait a bit longer for things to settle. 1384 */ 1385 if (on && sc->sc_chipset == CB_TOPIC95B) 1386 delay_ms(100, sc); 1387 1388 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1389 1390 if (on && sc->sc_chipset != CB_TOPIC95B) { 1391 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0) 1392 printf("%s: power on failed?\n", sc->sc_dev.dv_xname); 1393 } 1394 1395 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1396 printf("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1397 sc->sc_dev.dv_xname, sock_ctrl, status); 1398 printf("%s: disabling socket\n", sc->sc_dev.dv_xname); 1399 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1400 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1401 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1402 status &= ~CB_SOCKET_STAT_BADVCC; 1403 bus_space_write_4(memt, memh, CB_SOCKET_STAT, status); 1404 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1405 CB_SOCKET_STAT)); 1406 return 0; 1407 } 1408 1409 if (sc->sc_chipset == CB_TOPIC97) { 1410 reg_ctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL); 1411 reg_ctrl &= ~TOPIC97_REG_CTRL_TESTMODE; 1412 if ((command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V) 1413 reg_ctrl &= ~TOPIC97_REG_CTRL_CLKRUN_ENA; 1414 else 1415 reg_ctrl |= TOPIC97_REG_CTRL_CLKRUN_ENA; 1416 pci_conf_write(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL, reg_ctrl); 1417 } 1418 1419 return 1; /* power changed correctly */ 1420 } 1421 1422 #if defined CB_PCMCIA_POLL 1423 struct cb_poll_str { 1424 void *arg; 1425 int (*func)(void *); 1426 int level; 1427 pccard_chipset_tag_t ct; 1428 int count; 1429 struct callout poll_ch; 1430 }; 1431 1432 static struct cb_poll_str cb_poll[10]; 1433 static int cb_poll_n = 0; 1434 1435 static void cb_pcmcia_poll(void *arg); 1436 1437 static void 1438 cb_pcmcia_poll(void *arg) 1439 { 1440 struct cb_poll_str *poll = arg; 1441 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1442 struct pccbb_softc *sc = psc->cpc_parent; 1443 int s; 1444 u_int32_t spsr; /* socket present-state reg */ 1445 1446 callout_reset(&poll->poll_ch, hz / 10, cb_pcmcia_poll, poll); 1447 switch (poll->level) { 1448 case IPL_NET: 1449 s = splnet(); 1450 break; 1451 case IPL_BIO: 1452 s = splbio(); 1453 break; 1454 case IPL_TTY: /* fallthrough */ 1455 default: 1456 s = spltty(); 1457 break; 1458 } 1459 1460 spsr = 1461 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1462 CB_SOCKET_STAT); 1463 1464 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1465 if (!(spsr & 0x40)) { /* CINT low */ 1466 #else 1467 if (1) { 1468 #endif 1469 if ((*poll->func) (poll->arg) == 1) { 1470 ++poll->count; 1471 printf("intr: reported from poller, 0x%x\n", spsr); 1472 #if defined LEVEL2 1473 } else { 1474 printf("intr: miss! 0x%x\n", spsr); 1475 #endif 1476 } 1477 } 1478 splx(s); 1479 } 1480 #endif /* defined CB_PCMCIA_POLL */ 1481 1482 /* 1483 * static int pccbb_detect_card(struct pccbb_softc *sc) 1484 * return value: 0 if no card exists. 1485 * 1 if 16-bit card exists. 1486 * 2 if cardbus card exists. 1487 */ 1488 static int 1489 pccbb_detect_card(struct pccbb_softc *sc) 1490 { 1491 bus_space_handle_t base_memh = sc->sc_base_memh; 1492 bus_space_tag_t base_memt = sc->sc_base_memt; 1493 u_int32_t sockstat = 1494 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1495 int retval = 0; 1496 1497 /* CD1 and CD2 asserted */ 1498 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1499 /* card must be present */ 1500 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1501 /* NOTACARD DEASSERTED */ 1502 if (CB_SOCKET_STAT_CB & sockstat) { 1503 /* CardBus mode */ 1504 retval = 2; 1505 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1506 /* 16-bit mode */ 1507 retval = 1; 1508 } 1509 } 1510 } 1511 return retval; 1512 } 1513 1514 /* 1515 * STATIC int cb_reset(struct pccbb_softc *sc) 1516 * This function resets CardBus card. 1517 */ 1518 STATIC int 1519 cb_reset(struct pccbb_softc *sc) 1520 { 1521 /* 1522 * Reset Assert at least 20 ms 1523 * Some machines request longer duration. 1524 */ 1525 int reset_duration = 1526 (sc->sc_chipset == CB_RX5C47X ? 400 : 50); 1527 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1528 1529 /* Reset bit Assert (bit 6 at 0x3E) */ 1530 bcr |= CB_BCR_RESET_ENABLE; 1531 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1532 delay_ms(reset_duration, sc); 1533 1534 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1535 /* Reset bit Deassert (bit 6 at 0x3E) */ 1536 bcr &= ~CB_BCR_RESET_ENABLE; 1537 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1538 delay_ms(reset_duration, sc); 1539 } 1540 /* No card found on the slot. Keep Reset. */ 1541 return 1; 1542 } 1543 1544 /* 1545 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1546 * This function detect card Voltage. 1547 */ 1548 STATIC int 1549 cb_detect_voltage(struct pccbb_softc *sc) 1550 { 1551 u_int32_t psr; /* socket present-state reg */ 1552 bus_space_tag_t iot = sc->sc_base_memt; 1553 bus_space_handle_t ioh = sc->sc_base_memh; 1554 int vol = PCCARD_VCC_UKN; /* set 0 */ 1555 1556 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1557 1558 if (0x400u & psr) { 1559 vol |= PCCARD_VCC_5V; 1560 } 1561 if (0x800u & psr) { 1562 vol |= PCCARD_VCC_3V; 1563 } 1564 1565 return vol; 1566 } 1567 1568 STATIC int 1569 cbbprint(void *aux, const char *pcic) 1570 { 1571 #if 0 1572 struct cbslot_attach_args *cba = aux; 1573 1574 if (cba->cba_slot >= 0) { 1575 aprint_normal(" slot %d", cba->cba_slot); 1576 } 1577 #endif 1578 return UNCONF; 1579 } 1580 1581 /* 1582 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1583 * This function enables and disables the card 1584 */ 1585 STATIC int 1586 pccbb_cardenable(struct pccbb_softc *sc, int function) 1587 { 1588 u_int32_t command = 1589 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1590 1591 DPRINTF(("pccbb_cardenable:")); 1592 switch (function) { 1593 case CARDBUS_IO_ENABLE: 1594 command |= PCI_COMMAND_IO_ENABLE; 1595 break; 1596 case CARDBUS_IO_DISABLE: 1597 command &= ~PCI_COMMAND_IO_ENABLE; 1598 break; 1599 case CARDBUS_MEM_ENABLE: 1600 command |= PCI_COMMAND_MEM_ENABLE; 1601 break; 1602 case CARDBUS_MEM_DISABLE: 1603 command &= ~PCI_COMMAND_MEM_ENABLE; 1604 break; 1605 case CARDBUS_BM_ENABLE: 1606 command |= PCI_COMMAND_MASTER_ENABLE; 1607 break; 1608 case CARDBUS_BM_DISABLE: 1609 command &= ~PCI_COMMAND_MASTER_ENABLE; 1610 break; 1611 default: 1612 return 0; 1613 } 1614 1615 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1616 DPRINTF((" command reg 0x%x\n", command)); 1617 return 1; 1618 } 1619 1620 #if !rbus 1621 static int 1622 pccbb_io_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 1623 { 1624 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1625 int basereg; 1626 int limitreg; 1627 1628 if ((win < 0) || (win > 2)) { 1629 #if defined DIAGNOSTIC 1630 printf("cardbus_io_open: window out of range %d\n", win); 1631 #endif 1632 return 0; 1633 } 1634 1635 basereg = win * 8 + 0x2c; 1636 limitreg = win * 8 + 0x30; 1637 1638 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1639 start, basereg, end, limitreg)); 1640 1641 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1642 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1643 return 1; 1644 } 1645 1646 /* 1647 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1648 */ 1649 static int 1650 pccbb_io_close(cardbus_chipset_tag_t ct, int win) 1651 { 1652 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1653 int basereg; 1654 int limitreg; 1655 1656 if ((win < 0) || (win > 2)) { 1657 #if defined DIAGNOSTIC 1658 printf("cardbus_io_close: window out of range %d\n", win); 1659 #endif 1660 return 0; 1661 } 1662 1663 basereg = win * 8 + 0x2c; 1664 limitreg = win * 8 + 0x30; 1665 1666 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1667 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1668 return 1; 1669 } 1670 1671 static int 1672 pccbb_mem_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 1673 { 1674 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1675 int basereg; 1676 int limitreg; 1677 1678 if ((win < 0) || (win > 2)) { 1679 #if defined DIAGNOSTIC 1680 printf("cardbus_mem_open: window out of range %d\n", win); 1681 #endif 1682 return 0; 1683 } 1684 1685 basereg = win * 8 + 0x1c; 1686 limitreg = win * 8 + 0x20; 1687 1688 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1689 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1690 return 1; 1691 } 1692 1693 static int 1694 pccbb_mem_close(cardbus_chipset_tag_t ct, int win) 1695 { 1696 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1697 int basereg; 1698 int limitreg; 1699 1700 if ((win < 0) || (win > 2)) { 1701 #if defined DIAGNOSTIC 1702 printf("cardbus_mem_close: window out of range %d\n", win); 1703 #endif 1704 return 0; 1705 } 1706 1707 basereg = win * 8 + 0x1c; 1708 limitreg = win * 8 + 0x20; 1709 1710 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1711 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1712 return 1; 1713 } 1714 #endif 1715 1716 /* 1717 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1718 * int irq, 1719 * int level, 1720 * int (* func)(void *), 1721 * void *arg) 1722 * 1723 * This function registers an interrupt handler at the bridge, in 1724 * order not to call the interrupt handlers of child devices when 1725 * a card-deletion interrupt occurs. 1726 * 1727 * The arguments irq and level are not used. 1728 */ 1729 static void * 1730 pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, int irq, int level, 1731 int (*func)(void *), void *arg) 1732 { 1733 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1734 1735 return pccbb_intr_establish(sc, irq, level, func, arg); 1736 } 1737 1738 1739 /* 1740 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1741 * void *ih) 1742 * 1743 * This function removes an interrupt handler pointed by ih. 1744 */ 1745 static void 1746 pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih) 1747 { 1748 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1749 1750 pccbb_intr_disestablish(sc, ih); 1751 } 1752 1753 1754 void 1755 pccbb_intr_route(struct pccbb_softc *sc) 1756 { 1757 pcireg_t bcr, cbctrl; 1758 1759 /* initialize bridge intr routing */ 1760 bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1761 bcr &= ~CB_BCR_INTR_IREQ_ENABLE; 1762 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1763 1764 switch (sc->sc_chipset) { 1765 case CB_TI113X: 1766 cbctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1767 /* functional intr enabled */ 1768 cbctrl |= PCI113X_CBCTRL_PCI_INTR; 1769 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, cbctrl); 1770 break; 1771 default: 1772 break; 1773 } 1774 } 1775 1776 /* 1777 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1778 * int irq, 1779 * int level, 1780 * int (* func)(void *), 1781 * void *arg) 1782 * 1783 * This function registers an interrupt handler at the bridge, in 1784 * order not to call the interrupt handlers of child devices when 1785 * a card-deletion interrupt occurs. 1786 * 1787 * The arguments irq is not used because pccbb selects intr vector. 1788 */ 1789 static void * 1790 pccbb_intr_establish(struct pccbb_softc *sc, int irq, int level, 1791 int (*func)(void *), void *arg) 1792 { 1793 struct pccbb_intrhand_list *pil, *newpil; 1794 1795 DPRINTF(("pccbb_intr_establish start. %p\n", LIST_FIRST(&sc->sc_pil))); 1796 1797 if (LIST_EMPTY(&sc->sc_pil)) { 1798 pccbb_intr_route(sc); 1799 } 1800 1801 /* 1802 * Allocate a room for interrupt handler structure. 1803 */ 1804 if (NULL == (newpil = 1805 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1806 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1807 return NULL; 1808 } 1809 1810 newpil->pil_func = func; 1811 newpil->pil_arg = arg; 1812 newpil->pil_level = level; 1813 1814 if (LIST_EMPTY(&sc->sc_pil)) { 1815 LIST_INSERT_HEAD(&sc->sc_pil, newpil, pil_next); 1816 } else { 1817 for (pil = LIST_FIRST(&sc->sc_pil); 1818 LIST_NEXT(pil, pil_next) != NULL; 1819 pil = LIST_NEXT(pil, pil_next)); 1820 LIST_INSERT_AFTER(pil, newpil, pil_next); 1821 } 1822 1823 DPRINTF(("pccbb_intr_establish add pil. %p\n", 1824 LIST_FIRST(&sc->sc_pil))); 1825 1826 return newpil; 1827 } 1828 1829 /* 1830 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1831 * void *ih) 1832 * 1833 * This function removes an interrupt handler pointed by ih. ih 1834 * should be the value returned by cardbus_intr_establish() or 1835 * NULL. 1836 * 1837 * When ih is NULL, this function will do nothing. 1838 */ 1839 static void 1840 pccbb_intr_disestablish(struct pccbb_softc *sc, void *ih) 1841 { 1842 struct pccbb_intrhand_list *pil; 1843 pcireg_t reg; 1844 1845 DPRINTF(("pccbb_intr_disestablish start. %p\n", 1846 LIST_FIRST(&sc->sc_pil))); 1847 1848 if (ih == NULL) { 1849 /* intr handler is not set */ 1850 DPRINTF(("pccbb_intr_disestablish: no ih\n")); 1851 return; 1852 } 1853 1854 #ifdef DIAGNOSTIC 1855 for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1856 pil = LIST_NEXT(pil, pil_next)) { 1857 DPRINTF(("pccbb_intr_disestablish: pil %p\n", pil)); 1858 if (pil == ih) { 1859 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1860 break; 1861 } 1862 } 1863 if (pil == NULL) { 1864 panic("pccbb_intr_disestablish: %s cannot find pil %p", 1865 sc->sc_dev.dv_xname, ih); 1866 } 1867 #endif 1868 1869 pil = (struct pccbb_intrhand_list *)ih; 1870 LIST_REMOVE(pil, pil_next); 1871 free(pil, M_DEVBUF); 1872 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1873 1874 if (LIST_EMPTY(&sc->sc_pil)) { 1875 /* No interrupt handlers */ 1876 1877 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1878 1879 /* stop routing PCI intr */ 1880 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1881 reg |= CB_BCR_INTR_IREQ_ENABLE; 1882 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1883 1884 switch (sc->sc_chipset) { 1885 case CB_TI113X: 1886 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1887 /* functional intr disabled */ 1888 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1889 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1890 break; 1891 default: 1892 break; 1893 } 1894 } 1895 } 1896 1897 #if defined SHOW_REGS 1898 static void 1899 cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, bus_space_tag_t memt, 1900 bus_space_handle_t memh) 1901 { 1902 int i; 1903 printf("PCI config regs:"); 1904 for (i = 0; i < 0x50; i += 4) { 1905 if (i % 16 == 0) 1906 printf("\n 0x%02x:", i); 1907 printf(" %08x", pci_conf_read(pc, tag, i)); 1908 } 1909 for (i = 0x80; i < 0xb0; i += 4) { 1910 if (i % 16 == 0) 1911 printf("\n 0x%02x:", i); 1912 printf(" %08x", pci_conf_read(pc, tag, i)); 1913 } 1914 1915 if (memh == 0) { 1916 printf("\n"); 1917 return; 1918 } 1919 1920 printf("\nsocket regs:"); 1921 for (i = 0; i <= 0x10; i += 0x04) 1922 printf(" %08x", bus_space_read_4(memt, memh, i)); 1923 printf("\nExCA regs:"); 1924 for (i = 0; i < 0x08; ++i) 1925 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1926 printf("\n"); 1927 return; 1928 } 1929 #endif 1930 1931 /* 1932 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1933 * int busno, int function) 1934 * This is the function to make a tag to access config space of 1935 * a CardBus Card. It works same as pci_conf_read. 1936 */ 1937 static cardbustag_t 1938 pccbb_make_tag(cardbus_chipset_tag_t cc, int busno, int function) 1939 { 1940 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1941 1942 return pci_make_tag(sc->sc_pc, busno, 0, function); 1943 } 1944 1945 static void 1946 pccbb_free_tag(cardbus_chipset_tag_t cc, cardbustag_t tag) 1947 { 1948 } 1949 1950 /* 1951 * pccbb_conf_read 1952 * 1953 * This is the function to read the config space of a CardBus card. 1954 * It works the same as pci_conf_read(9). 1955 */ 1956 static cardbusreg_t 1957 pccbb_conf_read(cardbus_chipset_tag_t cc, cardbustag_t tag, int offset) 1958 { 1959 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1960 1961 return pci_conf_read(sc->sc_pc, tag, offset); 1962 } 1963 1964 /* 1965 * pccbb_conf_write 1966 * 1967 * This is the function to write the config space of a CardBus 1968 * card. It works the same as pci_conf_write(9). 1969 */ 1970 static void 1971 pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, int reg, 1972 cardbusreg_t val) 1973 { 1974 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1975 1976 pci_conf_write(sc->sc_pc, tag, reg, val); 1977 } 1978 1979 #if 0 1980 STATIC int 1981 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1982 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 1983 int speed, int flags, 1984 bus_space_handle_t * iohp) 1985 #endif 1986 /* 1987 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1988 * bus_addr_t start, bus_size_t size, 1989 * bus_size_t align, 1990 * struct pcmcia_io_handle *pcihp 1991 * 1992 * This function only allocates I/O region for pccard. This function 1993 * never maps the allocated region to pccard I/O area. 1994 * 1995 * XXX: The interface of this function is not very good, I believe. 1996 */ 1997 STATIC int 1998 pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, 1999 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 2000 { 2001 struct pcic_handle *ph = (struct pcic_handle *)pch; 2002 bus_addr_t ioaddr; 2003 int flags = 0; 2004 bus_space_tag_t iot; 2005 bus_space_handle_t ioh; 2006 bus_addr_t mask; 2007 #if rbus 2008 rbus_tag_t rb; 2009 #endif 2010 if (align == 0) { 2011 align = size; /* XXX: funny??? */ 2012 } 2013 2014 if (start != 0) { 2015 /* XXX: assume all card decode lower 10 bits by its hardware */ 2016 mask = 0x3ff; 2017 /* enforce to use only masked address */ 2018 start &= mask; 2019 } else { 2020 /* 2021 * calculate mask: 2022 * 1. get the most significant bit of size (call it msb). 2023 * 2. compare msb with the value of size. 2024 * 3. if size is larger, shift msb left once. 2025 * 4. obtain mask value to decrement msb. 2026 */ 2027 bus_size_t size_tmp = size; 2028 int shifts = 0; 2029 2030 mask = 1; 2031 while (size_tmp) { 2032 ++shifts; 2033 size_tmp >>= 1; 2034 } 2035 mask = (1 << shifts); 2036 if (mask < size) { 2037 mask <<= 1; 2038 } 2039 --mask; 2040 } 2041 2042 /* 2043 * Allocate some arbitrary I/O space. 2044 */ 2045 2046 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 2047 2048 #if rbus 2049 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 2050 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 2051 return 1; 2052 } 2053 DPRINTF(("pccbb_pcmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2054 (u_long) ioaddr, (u_long) size)); 2055 #else 2056 if (start) { 2057 ioaddr = start; 2058 if (bus_space_map(iot, start, size, 0, &ioh)) { 2059 return 1; 2060 } 2061 DPRINTF(("pccbb_pcmcia_io_alloc map port 0x%lx+0x%lx\n", 2062 (u_long) ioaddr, (u_long) size)); 2063 } else { 2064 flags |= PCMCIA_IO_ALLOCATED; 2065 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 2066 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 2067 size, align, 0, 0, &ioaddr, &ioh)) { 2068 /* No room be able to be get. */ 2069 return 1; 2070 } 2071 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2072 (u_long) ioaddr, (u_long) size)); 2073 } 2074 #endif 2075 2076 pcihp->iot = iot; 2077 pcihp->ioh = ioh; 2078 pcihp->addr = ioaddr; 2079 pcihp->size = size; 2080 pcihp->flags = flags; 2081 2082 return 0; 2083 } 2084 2085 /* 2086 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2087 * struct pcmcia_io_handle *pcihp) 2088 * 2089 * This function only frees I/O region for pccard. 2090 * 2091 * XXX: The interface of this function is not very good, I believe. 2092 */ 2093 void 2094 pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2095 struct pcmcia_io_handle *pcihp) 2096 { 2097 #if !rbus 2098 bus_space_tag_t iot = pcihp->iot; 2099 #endif 2100 bus_space_handle_t ioh = pcihp->ioh; 2101 bus_size_t size = pcihp->size; 2102 2103 #if rbus 2104 struct pccbb_softc *sc = 2105 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 2106 rbus_tag_t rb = sc->sc_rbus_iot; 2107 2108 rbus_space_free(rb, ioh, size, NULL); 2109 #else 2110 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 2111 bus_space_free(iot, ioh, size); 2112 else 2113 bus_space_unmap(iot, ioh, size); 2114 #endif 2115 } 2116 2117 /* 2118 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 2119 * bus_addr_t offset, bus_size_t size, 2120 * struct pcmcia_io_handle *pcihp, 2121 * int *windowp) 2122 * 2123 * This function maps the allocated I/O region to pccard. This function 2124 * never allocates any I/O region for pccard I/O area. I don't 2125 * understand why the original authors of pcmciabus separated alloc and 2126 * map. I believe the two must be unite. 2127 * 2128 * XXX: no wait timing control? 2129 */ 2130 int 2131 pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, bus_addr_t offset, 2132 bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp) 2133 { 2134 struct pcic_handle *ph = (struct pcic_handle *)pch; 2135 bus_addr_t ioaddr = pcihp->addr + offset; 2136 int i, win; 2137 #if defined CBB_DEBUG 2138 static const char *width_names[] = { "dynamic", "io8", "io16" }; 2139 #endif 2140 2141 /* Sanity check I/O handle. */ 2142 2143 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 2144 panic("pccbb_pcmcia_io_map iot is bogus"); 2145 } 2146 2147 /* XXX Sanity check offset/size. */ 2148 2149 win = -1; 2150 for (i = 0; i < PCIC_IO_WINS; i++) { 2151 if ((ph->ioalloc & (1 << i)) == 0) { 2152 win = i; 2153 ph->ioalloc |= (1 << i); 2154 break; 2155 } 2156 } 2157 2158 if (win == -1) { 2159 return 1; 2160 } 2161 2162 *windowp = win; 2163 2164 /* XXX this is pretty gross */ 2165 2166 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2167 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2168 2169 /* XXX wtf is this doing here? */ 2170 2171 #if 0 2172 printf(" port 0x%lx", (u_long) ioaddr); 2173 if (size > 1) { 2174 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2175 } 2176 #endif 2177 2178 ph->io[win].addr = ioaddr; 2179 ph->io[win].size = size; 2180 ph->io[win].width = width; 2181 2182 /* actual dirty register-value changing in the function below. */ 2183 pccbb_pcmcia_do_io_map(ph, win); 2184 2185 return 0; 2186 } 2187 2188 /* 2189 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2190 * 2191 * This function changes register-value to map I/O region for pccard. 2192 */ 2193 static void 2194 pccbb_pcmcia_do_io_map(struct pcic_handle *ph, int win) 2195 { 2196 static u_int8_t pcic_iowidth[3] = { 2197 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2198 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2199 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2200 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2201 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2202 }; 2203 2204 #define PCIC_SIA_START_LOW 0 2205 #define PCIC_SIA_START_HIGH 1 2206 #define PCIC_SIA_STOP_LOW 2 2207 #define PCIC_SIA_STOP_HIGH 3 2208 2209 int regbase_win = 0x8 + win * 0x04; 2210 u_int8_t ioctl, enable; 2211 2212 DPRINTF(("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx " 2213 "width %d\n", win, (unsigned long)ph->io[win].addr, 2214 (unsigned long)ph->io[win].size, ph->io[win].width * 8)); 2215 2216 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2217 ph->io[win].addr & 0xff); 2218 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2219 (ph->io[win].addr >> 8) & 0xff); 2220 2221 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2222 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2223 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2224 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2225 2226 ioctl = Pcic_read(ph, PCIC_IOCTL); 2227 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2228 switch (win) { 2229 case 0: 2230 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2231 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2232 PCIC_IOCTL_IO0_DATASIZE_MASK); 2233 ioctl |= pcic_iowidth[ph->io[win].width]; 2234 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2235 break; 2236 case 1: 2237 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2238 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2239 PCIC_IOCTL_IO1_DATASIZE_MASK); 2240 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2241 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2242 break; 2243 } 2244 Pcic_write(ph, PCIC_IOCTL, ioctl); 2245 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2246 #if defined(CBB_DEBUG) 2247 { 2248 u_int8_t start_low = 2249 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2250 u_int8_t start_high = 2251 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2252 u_int8_t stop_low = 2253 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2254 u_int8_t stop_high = 2255 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2256 printf("pccbb_pcmcia_do_io_map start %02x %02x, " 2257 "stop %02x %02x, ioctl %02x enable %02x\n", 2258 start_low, start_high, stop_low, stop_high, ioctl, enable); 2259 } 2260 #endif 2261 } 2262 2263 /* 2264 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2265 * 2266 * This function unmaps I/O region. No return value. 2267 */ 2268 STATIC void 2269 pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t pch, int win) 2270 { 2271 struct pcic_handle *ph = (struct pcic_handle *)pch; 2272 int reg; 2273 2274 if (win >= PCIC_IO_WINS || win < 0) { 2275 panic("pccbb_pcmcia_io_unmap: window out of range"); 2276 } 2277 2278 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2279 switch (win) { 2280 case 0: 2281 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2282 break; 2283 case 1: 2284 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2285 break; 2286 } 2287 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2288 2289 ph->ioalloc &= ~(1 << win); 2290 } 2291 2292 static int 2293 pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 2294 { 2295 u_int8_t stat; 2296 int i; 2297 2298 /* wait an initial 10ms for quick cards */ 2299 stat = Pcic_read(ph, PCIC_IF_STATUS); 2300 if (stat & PCIC_IF_STATUS_READY) 2301 return (0); 2302 pccbb_pcmcia_delay(ph, 10, "pccwr0"); 2303 for (i = 0; i < 50; i++) { 2304 stat = Pcic_read(ph, PCIC_IF_STATUS); 2305 if (stat & PCIC_IF_STATUS_READY) 2306 return (0); 2307 if ((stat & PCIC_IF_STATUS_CARDDETECT_MASK) != 2308 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2309 return (ENXIO); 2310 /* wait .1s (100ms) each iteration now */ 2311 pccbb_pcmcia_delay(ph, 100, "pccwr1"); 2312 } 2313 2314 printf("pccbb_pcmcia_wait_ready: ready never happened, status=%02x\n", stat); 2315 return (EWOULDBLOCK); 2316 } 2317 2318 /* 2319 * Perform long (msec order) delay. timo is in milliseconds. 2320 */ 2321 static void 2322 pccbb_pcmcia_delay(struct pcic_handle *ph, int timo, const char *wmesg) 2323 { 2324 #ifdef DIAGNOSTIC 2325 if (timo <= 0) 2326 panic("pccbb_pcmcia_delay: called with timeout %d", timo); 2327 if (!curlwp) 2328 panic("pccbb_pcmcia_delay: called in interrupt context"); 2329 #if 0 2330 if (!ph->event_thread) 2331 panic("pccbb_pcmcia_delay: no event thread"); 2332 #endif 2333 #endif 2334 DPRINTF(("pccbb_pcmcia_delay: \"%s\" %p, sleep %d ms\n", 2335 wmesg, ph->event_thread, timo)); 2336 tsleep(pccbb_pcmcia_delay, PWAIT, wmesg, roundup(timo * hz, 1000) / 1000); 2337 } 2338 2339 /* 2340 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2341 * 2342 * This function enables the card. All information is stored in 2343 * the first argument, pcmcia_chipset_handle_t. 2344 */ 2345 STATIC void 2346 pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2347 { 2348 struct pcic_handle *ph = (struct pcic_handle *)pch; 2349 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2350 pcireg_t spsr; 2351 int voltage; 2352 int win; 2353 u_int8_t power, intr; 2354 #ifdef DIAGNOSTIC 2355 int reg; 2356 #endif 2357 2358 /* this bit is mostly stolen from pcic_attach_card */ 2359 2360 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2361 2362 /* get card Vcc info */ 2363 spsr = 2364 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2365 CB_SOCKET_STAT); 2366 if (spsr & CB_SOCKET_STAT_5VCARD) { 2367 DPRINTF(("5V card\n")); 2368 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2369 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2370 DPRINTF(("3V card\n")); 2371 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2372 } else { 2373 DPRINTF(("?V card, 0x%x\n", spsr)); /* XXX */ 2374 return; 2375 } 2376 2377 /* disable interrupts; assert RESET */ 2378 intr = Pcic_read(ph, PCIC_INTR); 2379 intr &= PCIC_INTR_ENABLE; 2380 Pcic_write(ph, PCIC_INTR, intr); 2381 2382 /* zero out the address windows */ 2383 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2384 2385 /* power down the socket to reset it, clear the card reset pin */ 2386 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2387 2388 /* power off; assert output enable bit */ 2389 power = PCIC_PWRCTL_OE; 2390 Pcic_write(ph, PCIC_PWRCTL, power); 2391 2392 /* power up the socket */ 2393 if (pccbb_power(sc, voltage) == 0) 2394 return; 2395 2396 /* 2397 * Table 4-18 and figure 4-6 of the PC Card specifiction say: 2398 * Vcc Rising Time (Tpr) = 100ms (handled in pccbb_power() above) 2399 * RESET Width (Th (Hi-z RESET)) = 1ms 2400 * RESET Width (Tw (RESET)) = 10us 2401 * 2402 * some machines require some more time to be settled 2403 * for example old toshiba topic bridges! 2404 * (100ms is added here). 2405 */ 2406 pccbb_pcmcia_delay(ph, 200 + 1, "pccen1"); 2407 2408 /* negate RESET */ 2409 intr |= PCIC_INTR_RESET; 2410 Pcic_write(ph, PCIC_INTR, intr); 2411 2412 /* 2413 * RESET Setup Time (Tsu (RESET)) = 20ms 2414 */ 2415 pccbb_pcmcia_delay(ph, 20, "pccen2"); 2416 2417 #ifdef DIAGNOSTIC 2418 reg = Pcic_read(ph, PCIC_IF_STATUS); 2419 if ((reg & PCIC_IF_STATUS_POWERACTIVE) == 0) 2420 printf("pccbb_pcmcia_socket_enable: no power, status=%x\n", reg); 2421 #endif 2422 2423 /* wait for the chip to finish initializing */ 2424 if (pccbb_pcmcia_wait_ready(ph)) { 2425 #ifdef DIAGNOSTIC 2426 printf("pccbb_pcmcia_socket_enable: never became ready\n"); 2427 #endif 2428 /* XXX return a failure status?? */ 2429 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2430 Pcic_write(ph, PCIC_PWRCTL, 0); 2431 return; 2432 } 2433 2434 /* reinstall all the memory and io mappings */ 2435 for (win = 0; win < PCIC_MEM_WINS; ++win) 2436 if (ph->memalloc & (1 << win)) 2437 pccbb_pcmcia_do_mem_map(ph, win); 2438 for (win = 0; win < PCIC_IO_WINS; ++win) 2439 if (ph->ioalloc & (1 << win)) 2440 pccbb_pcmcia_do_io_map(ph, win); 2441 } 2442 2443 /* 2444 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2445 * 2446 * This function disables the card. All information is stored in 2447 * the first argument, pcmcia_chipset_handle_t. 2448 */ 2449 STATIC void 2450 pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t pch) 2451 { 2452 struct pcic_handle *ph = (struct pcic_handle *)pch; 2453 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2454 u_int8_t intr; 2455 2456 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2457 2458 /* disable interrupts; assert RESET */ 2459 intr = Pcic_read(ph, PCIC_INTR); 2460 intr &= PCIC_INTR_ENABLE; 2461 Pcic_write(ph, PCIC_INTR, intr); 2462 2463 /* zero out the address windows */ 2464 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2465 2466 /* power down the socket to reset it, clear the card reset pin */ 2467 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2468 2469 /* disable socket: negate output enable bit and power off */ 2470 Pcic_write(ph, PCIC_PWRCTL, 0); 2471 2472 /* 2473 * Vcc Falling Time (Tpf) = 300ms 2474 */ 2475 pccbb_pcmcia_delay(ph, 300, "pccwr1"); 2476 } 2477 2478 STATIC void 2479 pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t pch, int type) 2480 { 2481 struct pcic_handle *ph = (struct pcic_handle *)pch; 2482 u_int8_t intr; 2483 2484 /* set the card type */ 2485 2486 intr = Pcic_read(ph, PCIC_INTR); 2487 intr &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_CARDTYPE_MASK); 2488 if (type == PCMCIA_IFTYPE_IO) 2489 intr |= PCIC_INTR_CARDTYPE_IO; 2490 else 2491 intr |= PCIC_INTR_CARDTYPE_MEM; 2492 Pcic_write(ph, PCIC_INTR, intr); 2493 2494 DPRINTF(("%s: pccbb_pcmcia_socket_settype %02x type %s %02x\n", 2495 ph->ph_parent->dv_xname, ph->sock, 2496 ((type == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2497 } 2498 2499 /* 2500 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2501 * 2502 * This function detects whether a card is in the slot or not. 2503 * If a card is inserted, return 1. Otherwise, return 0. 2504 */ 2505 STATIC int 2506 pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch) 2507 { 2508 struct pcic_handle *ph = (struct pcic_handle *)pch; 2509 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2510 2511 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2512 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2513 } 2514 2515 #if 0 2516 STATIC int 2517 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2518 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2519 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2520 #endif 2521 /* 2522 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2523 * bus_size_t size, 2524 * struct pcmcia_mem_handle *pcmhp) 2525 * 2526 * This function only allocates memory region for pccard. This 2527 * function never maps the allocated region to pccard memory area. 2528 * 2529 * XXX: Why the argument of start address is not in? 2530 */ 2531 STATIC int 2532 pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 2533 struct pcmcia_mem_handle *pcmhp) 2534 { 2535 struct pcic_handle *ph = (struct pcic_handle *)pch; 2536 bus_space_handle_t memh; 2537 bus_addr_t addr; 2538 bus_size_t sizepg; 2539 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2540 #if rbus 2541 rbus_tag_t rb; 2542 #endif 2543 2544 /* Check that the card is still there. */ 2545 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2546 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2547 return 1; 2548 2549 /* out of sc->memh, allocate as many pages as necessary */ 2550 2551 /* convert size to PCIC pages */ 2552 /* 2553 * This is not enough; when the requested region is on the page 2554 * boundaries, this may calculate wrong result. 2555 */ 2556 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2557 #if 0 2558 if (sizepg > PCIC_MAX_MEM_PAGES) { 2559 return 1; 2560 } 2561 #endif 2562 2563 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2564 return 1; 2565 } 2566 2567 addr = 0; /* XXX gcc -Wuninitialized */ 2568 2569 #if rbus 2570 rb = sc->sc_rbus_memt; 2571 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2572 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2573 &addr, &memh)) { 2574 return 1; 2575 } 2576 #else 2577 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2578 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2579 0, /* boundary */ 2580 0, /* flags */ 2581 &addr, &memh)) { 2582 return 1; 2583 } 2584 #endif 2585 2586 DPRINTF(("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, " 2587 "realsize 0x%lx\n", (unsigned long)addr, (unsigned long)size, 2588 (unsigned long)sizepg * PCIC_MEM_PAGESIZE)); 2589 2590 pcmhp->memt = sc->sc_memt; 2591 pcmhp->memh = memh; 2592 pcmhp->addr = addr; 2593 pcmhp->size = size; 2594 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2595 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2596 pcmhp->mhandle = 0; 2597 /* No offset??? Funny. */ 2598 2599 return 0; 2600 } 2601 2602 /* 2603 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2604 * struct pcmcia_mem_handle *pcmhp) 2605 * 2606 * This function release the memory space allocated by the function 2607 * pccbb_pcmcia_mem_alloc(). 2608 */ 2609 STATIC void 2610 pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2611 struct pcmcia_mem_handle *pcmhp) 2612 { 2613 #if rbus 2614 struct pcic_handle *ph = (struct pcic_handle *)pch; 2615 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2616 2617 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2618 #else 2619 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2620 #endif 2621 } 2622 2623 /* 2624 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2625 * 2626 * This function release the memory space allocated by the function 2627 * pccbb_pcmcia_mem_alloc(). 2628 */ 2629 STATIC void 2630 pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2631 { 2632 int regbase_win; 2633 bus_addr_t phys_addr; 2634 bus_addr_t phys_end; 2635 2636 #define PCIC_SMM_START_LOW 0 2637 #define PCIC_SMM_START_HIGH 1 2638 #define PCIC_SMM_STOP_LOW 2 2639 #define PCIC_SMM_STOP_HIGH 3 2640 #define PCIC_CMA_LOW 4 2641 #define PCIC_CMA_HIGH 5 2642 2643 u_int8_t start_low, start_high = 0; 2644 u_int8_t stop_low, stop_high; 2645 u_int8_t off_low, off_high; 2646 u_int8_t mem_window; 2647 int reg; 2648 2649 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2650 int mem8 = 2651 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2652 || (kind == PCMCIA_MEM_ATTR); 2653 2654 regbase_win = 0x10 + win * 0x08; 2655 2656 phys_addr = ph->mem[win].addr; 2657 phys_end = phys_addr + ph->mem[win].size; 2658 2659 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2660 (unsigned long)phys_addr, (unsigned long)phys_end, 2661 (unsigned long)ph->mem[win].offset)); 2662 2663 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2664 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2665 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2666 2667 /* bit 19:12 */ 2668 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2669 /* bit 23:20 and bit 7 on */ 2670 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2671 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2672 /* bit 31:24, for 32-bit address */ 2673 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2674 2675 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2676 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2677 2678 if (((struct pccbb_softc *)ph-> 2679 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2680 Pcic_write(ph, 0x40 + win, mem_window); 2681 } 2682 2683 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2684 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2685 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2686 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2687 2688 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2689 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2690 2691 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2692 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2693 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2694 | ((kind == PCMCIA_MEM_ATTR) ? 2695 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2696 2697 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2698 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2699 2700 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2701 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2702 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2703 2704 #if defined(CBB_DEBUG) 2705 { 2706 int r1, r2, r3, r4, r5, r6, r7 = 0; 2707 2708 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2709 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2710 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2711 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2712 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2713 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2714 if (((struct pccbb_softc *)(ph-> 2715 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2716 r7 = Pcic_read(ph, 0x40 + win); 2717 } 2718 2719 printf("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2720 "%02x%02x", win, r1, r2, r3, r4, r5, r6); 2721 if (((struct pccbb_softc *)(ph-> 2722 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2723 printf(" %02x", r7); 2724 } 2725 printf("\n"); 2726 } 2727 #endif 2728 } 2729 2730 /* 2731 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2732 * bus_addr_t card_addr, bus_size_t size, 2733 * struct pcmcia_mem_handle *pcmhp, 2734 * bus_addr_t *offsetp, int *windowp) 2735 * 2736 * This function maps memory space allocated by the function 2737 * pccbb_pcmcia_mem_alloc(). 2738 */ 2739 STATIC int 2740 pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2741 bus_addr_t card_addr, bus_size_t size, struct pcmcia_mem_handle *pcmhp, 2742 bus_addr_t *offsetp, int *windowp) 2743 { 2744 struct pcic_handle *ph = (struct pcic_handle *)pch; 2745 bus_addr_t busaddr; 2746 long card_offset; 2747 int win; 2748 2749 /* Check that the card is still there. */ 2750 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2751 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2752 return 1; 2753 2754 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2755 if ((ph->memalloc & (1 << win)) == 0) { 2756 ph->memalloc |= (1 << win); 2757 break; 2758 } 2759 } 2760 2761 if (win == PCIC_MEM_WINS) { 2762 return 1; 2763 } 2764 2765 *windowp = win; 2766 2767 /* XXX this is pretty gross */ 2768 2769 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2770 panic("pccbb_pcmcia_mem_map memt is bogus"); 2771 } 2772 2773 busaddr = pcmhp->addr; 2774 2775 /* 2776 * compute the address offset to the pcmcia address space for the 2777 * pcic. this is intentionally signed. The masks and shifts below 2778 * will cause TRT to happen in the pcic registers. Deal with making 2779 * sure the address is aligned, and return the alignment offset. 2780 */ 2781 2782 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2783 card_addr -= *offsetp; 2784 2785 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2786 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2787 (u_long) card_addr)); 2788 2789 /* 2790 * include the offset in the size, and decrement size by one, since 2791 * the hw wants start/stop 2792 */ 2793 size += *offsetp - 1; 2794 2795 card_offset = (((long)card_addr) - ((long)busaddr)); 2796 2797 ph->mem[win].addr = busaddr; 2798 ph->mem[win].size = size; 2799 ph->mem[win].offset = card_offset; 2800 ph->mem[win].kind = kind; 2801 2802 pccbb_pcmcia_do_mem_map(ph, win); 2803 2804 return 0; 2805 } 2806 2807 /* 2808 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2809 * int window) 2810 * 2811 * This function unmaps memory space which mapped by the function 2812 * pccbb_pcmcia_mem_map(). 2813 */ 2814 STATIC void 2815 pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, int window) 2816 { 2817 struct pcic_handle *ph = (struct pcic_handle *)pch; 2818 int reg; 2819 2820 if (window >= PCIC_MEM_WINS) { 2821 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2822 } 2823 2824 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2825 reg &= ~(1 << window); 2826 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2827 2828 ph->memalloc &= ~(1 << window); 2829 } 2830 2831 #if defined PCCBB_PCMCIA_POLL 2832 struct pccbb_poll_str { 2833 void *arg; 2834 int (*func)(void *); 2835 int level; 2836 struct pcic_handle *ph; 2837 int count; 2838 int num; 2839 struct callout poll_ch; 2840 }; 2841 2842 static struct pccbb_poll_str pccbb_poll[10]; 2843 static int pccbb_poll_n = 0; 2844 2845 static void pccbb_pcmcia_poll(void *arg); 2846 2847 static void 2848 pccbb_pcmcia_poll(void *arg) 2849 { 2850 struct pccbb_poll_str *poll = arg; 2851 struct pcic_handle *ph = poll->ph; 2852 struct pccbb_softc *sc = ph->sc; 2853 int s; 2854 u_int32_t spsr; /* socket present-state reg */ 2855 2856 callout_reset(&poll->poll_ch, hz * 2, pccbb_pcmcia_poll, arg); 2857 switch (poll->level) { 2858 case IPL_NET: 2859 s = splnet(); 2860 break; 2861 case IPL_BIO: 2862 s = splbio(); 2863 break; 2864 case IPL_TTY: /* fallthrough */ 2865 default: 2866 s = spltty(); 2867 break; 2868 } 2869 2870 spsr = 2871 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2872 CB_SOCKET_STAT); 2873 2874 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2875 if (!(spsr & 0x40)) /* CINT low */ 2876 #else 2877 if (1) 2878 #endif 2879 { 2880 if ((*poll->func) (poll->arg) > 0) { 2881 ++poll->count; 2882 /* printf("intr: reported from poller, 0x%x\n", spsr); */ 2883 #if defined LEVEL2 2884 } else { 2885 printf("intr: miss! 0x%x\n", spsr); 2886 #endif 2887 } 2888 } 2889 splx(s); 2890 } 2891 #endif /* defined CB_PCMCIA_POLL */ 2892 2893 /* 2894 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2895 * struct pcmcia_function *pf, 2896 * int ipl, 2897 * int (*func)(void *), 2898 * void *arg); 2899 * 2900 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2901 */ 2902 STATIC void * 2903 pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2904 struct pcmcia_function *pf, int ipl, int (*func)(void *), void *arg) 2905 { 2906 struct pcic_handle *ph = (struct pcic_handle *)pch; 2907 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2908 2909 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2910 /* what should I do? */ 2911 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2912 DPRINTF(("%s does not provide edge nor pulse " 2913 "interrupt\n", sc->sc_dev.dv_xname)); 2914 return NULL; 2915 } 2916 /* 2917 * XXX Noooooo! The interrupt flag must set properly!! 2918 * dumb pcmcia driver!! 2919 */ 2920 } 2921 2922 return pccbb_intr_establish(sc, 0, ipl, func, arg); 2923 } 2924 2925 /* 2926 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2927 * void *ih) 2928 * 2929 * This function disables PC-Card interrupt. 2930 */ 2931 STATIC void 2932 pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 2933 { 2934 struct pcic_handle *ph = (struct pcic_handle *)pch; 2935 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2936 2937 pccbb_intr_disestablish(sc, ih); 2938 } 2939 2940 #if rbus 2941 /* 2942 * static int 2943 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2944 * bus_addr_t addr, bus_size_t size, 2945 * bus_addr_t mask, bus_size_t align, 2946 * int flags, bus_addr_t *addrp; 2947 * bus_space_handle_t *bshp) 2948 * 2949 * This function allocates a portion of memory or io space for 2950 * clients. This function is called from CardBus card drivers. 2951 */ 2952 static int 2953 pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2954 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 2955 int flags, bus_addr_t *addrp, bus_space_handle_t *bshp) 2956 { 2957 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2958 2959 DPRINTF(("pccbb_rbus_cb_space_alloc: addr 0x%lx, size 0x%lx, " 2960 "mask 0x%lx, align 0x%lx\n", (unsigned long)addr, 2961 (unsigned long)size, (unsigned long)mask, (unsigned long)align)); 2962 2963 if (align == 0) { 2964 align = size; 2965 } 2966 2967 if (rb->rb_bt == sc->sc_memt) { 2968 if (align < 16) { 2969 return 1; 2970 } 2971 /* 2972 * XXX: align more than 0x1000 to avoid overwrapping 2973 * memory windows for two or more devices. 0x1000 2974 * means memory window's granularity. 2975 * 2976 * Two or more devices should be able to share same 2977 * memory window region. However, overrapping memory 2978 * window is not good because some devices, such as 2979 * 3Com 3C575[BC], have a broken address decoder and 2980 * intrude other's memory region. 2981 */ 2982 if (align < 0x1000) { 2983 align = 0x1000; 2984 } 2985 } else if (rb->rb_bt == sc->sc_iot) { 2986 if (align < 4) { 2987 return 1; 2988 } 2989 /* XXX: hack for avoiding ISA image */ 2990 if (mask < 0x0100) { 2991 mask = 0x3ff; 2992 addr = 0x300; 2993 } 2994 2995 } else { 2996 DPRINTF(("pccbb_rbus_cb_space_alloc: Bus space tag 0x%lx is " 2997 "NOT used. io: 0x%lx, mem: 0x%lx\n", 2998 (unsigned long)rb->rb_bt, (unsigned long)sc->sc_iot, 2999 (unsigned long)sc->sc_memt)); 3000 return 1; 3001 /* XXX: panic here? */ 3002 } 3003 3004 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 3005 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 3006 return 1; 3007 } 3008 3009 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 3010 3011 return 0; 3012 } 3013 3014 /* 3015 * static int 3016 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 3017 * bus_space_handle_t *bshp, bus_size_t size); 3018 * 3019 * This function is called from CardBus card drivers. 3020 */ 3021 static int 3022 pccbb_rbus_cb_space_free(cardbus_chipset_tag_t ct, rbus_tag_t rb, 3023 bus_space_handle_t bsh, bus_size_t size) 3024 { 3025 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 3026 bus_space_tag_t bt = rb->rb_bt; 3027 3028 pccbb_close_win(sc, bt, bsh, size); 3029 3030 if (bt == sc->sc_memt) { 3031 } else if (bt == sc->sc_iot) { 3032 } else { 3033 return 1; 3034 /* XXX: panic here? */ 3035 } 3036 3037 return rbus_space_free(rb, bsh, size, NULL); 3038 } 3039 #endif /* rbus */ 3040 3041 #if rbus 3042 3043 static int 3044 pccbb_open_win(struct pccbb_softc *sc, bus_space_tag_t bst, bus_addr_t addr, 3045 bus_size_t size, bus_space_handle_t bsh, int flags) 3046 { 3047 struct pccbb_win_chain_head *head; 3048 bus_addr_t align; 3049 3050 head = &sc->sc_iowindow; 3051 align = 0x04; 3052 if (sc->sc_memt == bst) { 3053 head = &sc->sc_memwindow; 3054 align = 0x1000; 3055 DPRINTF(("using memory window, 0x%lx 0x%lx 0x%lx\n\n", 3056 (unsigned long)sc->sc_iot, (unsigned long)sc->sc_memt, 3057 (unsigned long)bst)); 3058 } 3059 3060 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 3061 printf("%s: pccbb_open_win: %s winlist insert failed\n", 3062 sc->sc_dev.dv_xname, 3063 (head == &sc->sc_memwindow) ? "mem" : "io"); 3064 } 3065 pccbb_winset(align, sc, bst); 3066 3067 return 0; 3068 } 3069 3070 static int 3071 pccbb_close_win(struct pccbb_softc *sc, bus_space_tag_t bst, 3072 bus_space_handle_t bsh, bus_size_t size) 3073 { 3074 struct pccbb_win_chain_head *head; 3075 bus_addr_t align; 3076 3077 head = &sc->sc_iowindow; 3078 align = 0x04; 3079 if (sc->sc_memt == bst) { 3080 head = &sc->sc_memwindow; 3081 align = 0x1000; 3082 } 3083 3084 if (pccbb_winlist_delete(head, bsh, size)) { 3085 printf("%s: pccbb_close_win: %s winlist delete failed\n", 3086 sc->sc_dev.dv_xname, 3087 (head == &sc->sc_memwindow) ? "mem" : "io"); 3088 } 3089 pccbb_winset(align, sc, bst); 3090 3091 return 0; 3092 } 3093 3094 static int 3095 pccbb_winlist_insert(struct pccbb_win_chain_head *head, bus_addr_t start, 3096 bus_size_t size, bus_space_handle_t bsh, int flags) 3097 { 3098 struct pccbb_win_chain *chainp, *elem; 3099 3100 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 3101 M_NOWAIT)) == NULL) 3102 return (1); /* fail */ 3103 3104 elem->wc_start = start; 3105 elem->wc_end = start + (size - 1); 3106 elem->wc_handle = bsh; 3107 elem->wc_flags = flags; 3108 3109 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3110 chainp = TAILQ_NEXT(chainp, wc_list)) { 3111 if (chainp->wc_end < start) 3112 continue; 3113 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 3114 return (0); 3115 } 3116 3117 TAILQ_INSERT_TAIL(head, elem, wc_list); 3118 return (0); 3119 } 3120 3121 static int 3122 pccbb_winlist_delete(struct pccbb_win_chain_head *head, bus_space_handle_t bsh, 3123 bus_size_t size) 3124 { 3125 struct pccbb_win_chain *chainp; 3126 3127 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3128 chainp = TAILQ_NEXT(chainp, wc_list)) { 3129 if (memcmp(&chainp->wc_handle, &bsh, sizeof(bsh))) 3130 continue; 3131 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 3132 printf("pccbb_winlist_delete: window 0x%lx size " 3133 "inconsistent: 0x%lx, 0x%lx\n", 3134 (unsigned long)chainp->wc_start, 3135 (unsigned long)(chainp->wc_end - chainp->wc_start), 3136 (unsigned long)(size - 1)); 3137 return 1; 3138 } 3139 3140 TAILQ_REMOVE(head, chainp, wc_list); 3141 free(chainp, M_DEVBUF); 3142 3143 return 0; 3144 } 3145 3146 return 1; /* fail: no candidate to remove */ 3147 } 3148 3149 static void 3150 pccbb_winset(bus_addr_t align, struct pccbb_softc *sc, bus_space_tag_t bst) 3151 { 3152 pci_chipset_tag_t pc; 3153 pcitag_t tag; 3154 bus_addr_t mask = ~(align - 1); 3155 struct { 3156 cardbusreg_t win_start; 3157 cardbusreg_t win_limit; 3158 int win_flags; 3159 } win[2]; 3160 struct pccbb_win_chain *chainp; 3161 int offs; 3162 3163 win[0].win_start = win[1].win_start = 0xffffffff; 3164 win[0].win_limit = win[1].win_limit = 0; 3165 win[0].win_flags = win[1].win_flags = 0; 3166 3167 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3168 offs = 0x2c; 3169 if (sc->sc_memt == bst) { 3170 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3171 offs = 0x1c; 3172 } 3173 3174 if (chainp != NULL) { 3175 win[0].win_start = chainp->wc_start & mask; 3176 win[0].win_limit = chainp->wc_end & mask; 3177 win[0].win_flags = chainp->wc_flags; 3178 chainp = TAILQ_NEXT(chainp, wc_list); 3179 } 3180 3181 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3182 if (win[1].win_start == 0xffffffff) { 3183 /* window 1 is not used */ 3184 if ((win[0].win_flags == chainp->wc_flags) && 3185 (win[0].win_limit + align >= 3186 (chainp->wc_start & mask))) { 3187 /* concatenate */ 3188 win[0].win_limit = chainp->wc_end & mask; 3189 } else { 3190 /* make new window */ 3191 win[1].win_start = chainp->wc_start & mask; 3192 win[1].win_limit = chainp->wc_end & mask; 3193 win[1].win_flags = chainp->wc_flags; 3194 } 3195 continue; 3196 } 3197 3198 /* Both windows are engaged. */ 3199 if (win[0].win_flags == win[1].win_flags) { 3200 /* same flags */ 3201 if (win[0].win_flags == chainp->wc_flags) { 3202 if (win[1].win_start - (win[0].win_limit + 3203 align) < 3204 (chainp->wc_start & mask) - 3205 ((chainp->wc_end & mask) + align)) { 3206 /* 3207 * merge window 0 and 1, and set win1 3208 * to chainp 3209 */ 3210 win[0].win_limit = win[1].win_limit; 3211 win[1].win_start = 3212 chainp->wc_start & mask; 3213 win[1].win_limit = 3214 chainp->wc_end & mask; 3215 } else { 3216 win[1].win_limit = 3217 chainp->wc_end & mask; 3218 } 3219 } else { 3220 /* different flags */ 3221 3222 /* concatenate win0 and win1 */ 3223 win[0].win_limit = win[1].win_limit; 3224 /* allocate win[1] to new space */ 3225 win[1].win_start = chainp->wc_start & mask; 3226 win[1].win_limit = chainp->wc_end & mask; 3227 win[1].win_flags = chainp->wc_flags; 3228 } 3229 } else { 3230 /* the flags of win[0] and win[1] is different */ 3231 if (win[0].win_flags == chainp->wc_flags) { 3232 win[0].win_limit = chainp->wc_end & mask; 3233 /* 3234 * XXX this creates overlapping windows, so 3235 * what should the poor bridge do if one is 3236 * cachable, and the other is not? 3237 */ 3238 printf("%s: overlapping windows\n", 3239 sc->sc_dev.dv_xname); 3240 } else { 3241 win[1].win_limit = chainp->wc_end & mask; 3242 } 3243 } 3244 } 3245 3246 pc = sc->sc_pc; 3247 tag = sc->sc_tag; 3248 pci_conf_write(pc, tag, offs, win[0].win_start); 3249 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3250 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3251 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3252 DPRINTF(("--pccbb_winset: win0 [0x%lx, 0x%lx), win1 [0x%lx, 0x%lx)\n", 3253 (unsigned long)pci_conf_read(pc, tag, offs), 3254 (unsigned long)pci_conf_read(pc, tag, offs + 4) + align, 3255 (unsigned long)pci_conf_read(pc, tag, offs + 8), 3256 (unsigned long)pci_conf_read(pc, tag, offs + 12) + align)); 3257 3258 if (bst == sc->sc_memt) { 3259 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3260 3261 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 3262 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 3263 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3264 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 3265 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3266 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3267 } 3268 } 3269 3270 #endif /* rbus */ 3271 3272 static void 3273 pccbb_powerhook(int why, void *arg) 3274 { 3275 struct pccbb_softc *sc = arg; 3276 pcireg_t reg; 3277 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3278 bus_space_handle_t base_memh = sc->sc_base_memh; 3279 3280 DPRINTF(("%s: power: why %d\n", sc->sc_dev.dv_xname, why)); 3281 3282 if (why == PWR_SUSPEND || why == PWR_STANDBY) { 3283 DPRINTF(("%s: power: why %d stopping intr\n", 3284 sc->sc_dev.dv_xname, why)); 3285 if (sc->sc_pil_intr_enable) { 3286 (void)pccbbintr_function(sc); 3287 } 3288 sc->sc_pil_intr_enable = 0; 3289 3290 pci_conf_capture(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf); 3291 3292 if (sc->sc_chipset == CB_RX5C47X) 3293 sc->sc_ricoh_misc_ctrl = pci_conf_read(sc->sc_pc, 3294 sc->sc_tag, 3295 RICOH_PCI_MISC_CTRL); 3296 3297 /* ToDo: deactivate or suspend child devices */ 3298 } 3299 3300 if (why == PWR_RESUME) { 3301 if (sc->sc_pwrmgt_offs != 0) { 3302 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, 3303 sc->sc_pwrmgt_offs + PCI_PMCSR); 3304 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 3305 reg & PCI_PMCSR_PME_EN) { 3306 /* powrstate != D0 */ 3307 3308 printf("%s going back to D0 mode\n", 3309 sc->sc_dev.dv_xname); 3310 reg &= ~PCI_PMCSR_STATE_MASK; 3311 reg |= PCI_PMCSR_STATE_D0; 3312 reg &= ~PCI_PMCSR_PME_EN; 3313 pci_conf_write(sc->sc_pc, sc->sc_tag, 3314 sc->sc_pwrmgt_offs + PCI_PMCSR, reg); 3315 3316 pci_conf_write(sc->sc_pc, sc->sc_tag, 3317 PCI_SOCKBASE, sc->sc_sockbase); 3318 pci_conf_write(sc->sc_pc, sc->sc_tag, 3319 PCI_BUSNUM, sc->sc_busnum); 3320 pccbb_chipinit(sc); 3321 /* setup memory and io space window for CB */ 3322 pccbb_winset(0x1000, sc, sc->sc_memt); 3323 pccbb_winset(0x04, sc, sc->sc_iot); 3324 goto norestore; 3325 } 3326 } 3327 3328 norestore: 3329 pci_conf_restore(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf); 3330 if (sc->sc_chipset == CB_RX5C47X) { 3331 pci_conf_write(sc->sc_pc, sc->sc_tag, 3332 RICOH_PCI_MISC_CTRL, sc->sc_ricoh_misc_ctrl); 3333 } 3334 3335 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_SOCKBASE) == 0) 3336 /* BIOS did not recover this register */ 3337 pci_conf_write (sc->sc_pc, sc->sc_tag, 3338 PCI_SOCKBASE, sc->sc_sockbase); 3339 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_BUSNUM) == 0) 3340 /* BIOS did not recover this register */ 3341 pci_conf_write (sc->sc_pc, sc->sc_tag, 3342 PCI_BUSNUM, sc->sc_busnum); 3343 /* CSC Interrupt: Card detect interrupt on */ 3344 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3345 /* Card detect intr is turned on. */ 3346 reg |= CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; 3347 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3348 /* reset interrupt */ 3349 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3350 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3351 3352 /* 3353 * check for card insertion or removal during suspend period. 3354 * XXX: the code can't cope with card swap (remove then 3355 * insert). how can we detect such situation? 3356 */ 3357 (void)pccbbintr(sc); 3358 3359 sc->sc_pil_intr_enable = 1; 3360 DPRINTF(("%s: power: RESUME enabling intr\n", 3361 sc->sc_dev.dv_xname)); 3362 3363 /* ToDo: activate or wakeup child devices */ 3364 } 3365 } 3366
Indexes created Tue Oct 14 21:09:58 GMT 2025