pccbb.c revision 1.137.2.2
1 /* $NetBSD: pccbb.c,v 1.137.2.2 2007/10/26 23:14:57 xtraeme Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: pccbb.c,v 1.137.2.2 2007/10/26 23:14:57 xtraeme Exp $"); 35 36 /* 37 #define CBB_DEBUG 38 #define SHOW_REGS 39 */ 40 41 /* 42 * BROKEN! 43 #define PCCBB_PCMCIA_POLL 44 #define CB_PCMCIA_POLL 45 #define CB_PCMCIA_POLL_ONLY 46 #define LEVEL2 47 */ 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/kernel.h> 52 #include <sys/errno.h> 53 #include <sys/ioctl.h> 54 #include <sys/reboot.h> /* for bootverbose */ 55 #include <sys/syslog.h> 56 #include <sys/device.h> 57 #include <sys/malloc.h> 58 #include <sys/proc.h> 59 60 #include <machine/intr.h> 61 #include <machine/bus.h> 62 63 #include <dev/pci/pcivar.h> 64 #include <dev/pci/pcireg.h> 65 #include <dev/pci/pcidevs.h> 66 67 #include <dev/pci/pccbbreg.h> 68 69 #include <dev/cardbus/cardslotvar.h> 70 71 #include <dev/cardbus/cardbusvar.h> 72 73 #include <dev/pcmcia/pcmciareg.h> 74 #include <dev/pcmcia/pcmciavar.h> 75 76 #include <dev/ic/i82365reg.h> 77 #include <dev/ic/i82365var.h> 78 #include <dev/pci/pccbbvar.h> 79 80 #include "locators.h" 81 82 #if defined(__i386__) 83 #include "ioapic.h" 84 #include "acpi.h" 85 #endif 86 87 #ifndef __NetBSD_Version__ 88 struct cfdriver cbb_cd = { 89 NULL, "cbb", DV_DULL 90 }; 91 #endif 92 93 #ifdef CBB_DEBUG 94 #define DPRINTF(x) printf x 95 #define STATIC 96 #else 97 #define DPRINTF(x) 98 #define STATIC static 99 #endif 100 101 /* 102 * delay_ms() is wait in milliseconds. It should be used instead 103 * of delay() if you want to wait more than 1 ms. 104 */ 105 static inline void 106 delay_ms(int millis, void *param) 107 { 108 if (cold) 109 delay(millis * 1000); 110 else 111 tsleep(param, PWAIT, "pccbb", MAX(2, hz * millis / 1000)); 112 } 113 114 int pcicbbmatch(struct device *, struct cfdata *, void *); 115 void pccbbattach(struct device *, struct device *, void *); 116 int pccbbintr(void *); 117 static void pci113x_insert(void *); 118 static int pccbbintr_function(struct pccbb_softc *); 119 120 static int pccbb_detect_card(struct pccbb_softc *); 121 122 static void pccbb_pcmcia_write(struct pcic_handle *, int, u_int8_t); 123 static u_int8_t pccbb_pcmcia_read(struct pcic_handle *, int); 124 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 125 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 126 127 STATIC int cb_reset(struct pccbb_softc *); 128 STATIC int cb_detect_voltage(struct pccbb_softc *); 129 STATIC int cbbprint(void *, const char *); 130 131 static int cb_chipset(u_int32_t, int *); 132 STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *, 133 struct pcmciabus_attach_args *); 134 #if 0 135 STATIC void pccbb_pcmcia_attach_card(struct pcic_handle *); 136 STATIC void pccbb_pcmcia_detach_card(struct pcic_handle *, int); 137 STATIC void pccbb_pcmcia_deactivate_card(struct pcic_handle *); 138 #endif 139 140 STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int); 141 STATIC int pccbb_power(cardbus_chipset_tag_t, int); 142 STATIC int pccbb_cardenable(struct pccbb_softc * sc, int function); 143 #if !rbus 144 static int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 145 static int pccbb_io_close(cardbus_chipset_tag_t, int); 146 static int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 147 static int pccbb_mem_close(cardbus_chipset_tag_t, int); 148 #endif /* !rbus */ 149 static void *pccbb_intr_establish(struct pccbb_softc *, int irq, 150 int level, int (*ih) (void *), void *sc); 151 static void pccbb_intr_disestablish(struct pccbb_softc *, void *ih); 152 153 static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t, int irq, 154 int level, int (*ih) (void *), void *sc); 155 static void pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih); 156 157 static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t, int, int); 158 static void pccbb_free_tag(cardbus_chipset_tag_t, cardbustag_t); 159 static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t, cardbustag_t, int); 160 static void pccbb_conf_write(cardbus_chipset_tag_t, cardbustag_t, int, 161 cardbusreg_t); 162 static void pccbb_chipinit(struct pccbb_softc *); 163 164 STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 165 struct pcmcia_mem_handle *); 166 STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t, 167 struct pcmcia_mem_handle *); 168 STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 169 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *); 170 STATIC void pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t, int); 171 STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 172 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 173 STATIC void pccbb_pcmcia_io_free(pcmcia_chipset_handle_t, 174 struct pcmcia_io_handle *); 175 STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 176 bus_size_t, struct pcmcia_io_handle *, int *); 177 STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t, int); 178 STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t, 179 struct pcmcia_function *, int, int (*)(void *), void *); 180 STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t, void *); 181 STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t); 182 STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t); 183 STATIC void pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t, int); 184 STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch); 185 186 static int pccbb_pcmcia_wait_ready(struct pcic_handle *); 187 static void pccbb_pcmcia_delay(struct pcic_handle *, int, const char *); 188 189 static void pccbb_pcmcia_do_io_map(struct pcic_handle *, int); 190 static void pccbb_pcmcia_do_mem_map(struct pcic_handle *, int); 191 static void pccbb_powerhook(int, void *); 192 193 /* bus-space allocation and deallocation functions */ 194 #if rbus 195 196 static int pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t, rbus_tag_t, 197 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 198 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp); 199 static int pccbb_rbus_cb_space_free(cardbus_chipset_tag_t, rbus_tag_t, 200 bus_space_handle_t, bus_size_t); 201 202 #endif /* rbus */ 203 204 #if rbus 205 206 static int pccbb_open_win(struct pccbb_softc *, bus_space_tag_t, 207 bus_addr_t, bus_size_t, bus_space_handle_t, int flags); 208 static int pccbb_close_win(struct pccbb_softc *, bus_space_tag_t, 209 bus_space_handle_t, bus_size_t); 210 static int pccbb_winlist_insert(struct pccbb_win_chain_head *, bus_addr_t, 211 bus_size_t, bus_space_handle_t, int); 212 static int pccbb_winlist_delete(struct pccbb_win_chain_head *, 213 bus_space_handle_t, bus_size_t); 214 static void pccbb_winset(bus_addr_t align, struct pccbb_softc *, 215 bus_space_tag_t); 216 void pccbb_winlist_show(struct pccbb_win_chain *); 217 218 #endif /* rbus */ 219 220 /* for config_defer */ 221 static void pccbb_pci_callback(struct device *); 222 223 #if defined SHOW_REGS 224 static void cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, 225 bus_space_tag_t memt, bus_space_handle_t memh); 226 #endif 227 228 CFATTACH_DECL(cbb_pci, sizeof(struct pccbb_softc), 229 pcicbbmatch, pccbbattach, NULL, NULL); 230 231 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 232 pccbb_pcmcia_mem_alloc, 233 pccbb_pcmcia_mem_free, 234 pccbb_pcmcia_mem_map, 235 pccbb_pcmcia_mem_unmap, 236 pccbb_pcmcia_io_alloc, 237 pccbb_pcmcia_io_free, 238 pccbb_pcmcia_io_map, 239 pccbb_pcmcia_io_unmap, 240 pccbb_pcmcia_intr_establish, 241 pccbb_pcmcia_intr_disestablish, 242 pccbb_pcmcia_socket_enable, 243 pccbb_pcmcia_socket_disable, 244 pccbb_pcmcia_socket_settype, 245 pccbb_pcmcia_card_detect 246 }; 247 248 #if rbus 249 static struct cardbus_functions pccbb_funcs = { 250 pccbb_rbus_cb_space_alloc, 251 pccbb_rbus_cb_space_free, 252 pccbb_cb_intr_establish, 253 pccbb_cb_intr_disestablish, 254 pccbb_ctrl, 255 pccbb_power, 256 pccbb_make_tag, 257 pccbb_free_tag, 258 pccbb_conf_read, 259 pccbb_conf_write, 260 }; 261 #else 262 static struct cardbus_functions pccbb_funcs = { 263 pccbb_ctrl, 264 pccbb_power, 265 pccbb_mem_open, 266 pccbb_mem_close, 267 pccbb_io_open, 268 pccbb_io_close, 269 pccbb_cb_intr_establish, 270 pccbb_cb_intr_disestablish, 271 pccbb_make_tag, 272 pccbb_conf_read, 273 pccbb_conf_write, 274 }; 275 #endif 276 277 int 278 pcicbbmatch(struct device *parent, struct cfdata *match, void *aux) 279 { 280 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 281 282 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 283 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 284 PCI_INTERFACE(pa->pa_class) == 0) { 285 return 1; 286 } 287 288 return 0; 289 } 290 291 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 292 | ((prod) << PCI_PRODUCT_SHIFT)) 293 294 const struct yenta_chipinfo { 295 pcireg_t yc_id; /* vendor tag | product tag */ 296 int yc_chiptype; 297 int yc_flags; 298 } yc_chipsets[] = { 299 /* Texas Instruments chips */ 300 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 301 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 302 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 303 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 304 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI125X, 305 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 306 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 307 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 308 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 309 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 310 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 311 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 312 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI125X, 313 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 314 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI125X, 315 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 316 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 317 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 318 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 319 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 320 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 321 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 322 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI125X, 323 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 324 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 325 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 326 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1520), CB_TI12XX, 327 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 328 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4410YENTA), CB_TI12XX, 329 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 330 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4520YENTA), CB_TI12XX, 331 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 332 333 /* Ricoh chips */ 334 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 335 PCCBB_PCMCIA_MEM_32}, 336 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 337 PCCBB_PCMCIA_MEM_32}, 338 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 339 PCCBB_PCMCIA_MEM_32}, 340 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 341 PCCBB_PCMCIA_MEM_32}, 342 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 343 PCCBB_PCMCIA_MEM_32}, 344 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 345 PCCBB_PCMCIA_MEM_32}, 346 347 /* Toshiba products */ 348 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 349 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 350 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 351 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 352 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 353 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 354 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 355 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 356 357 /* Cirrus Logic products */ 358 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 359 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 360 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 361 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 362 363 /* sentinel, or Generic chip */ 364 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 365 }; 366 367 static int 368 cb_chipset(u_int32_t pci_id, int *flagp) 369 { 370 const struct yenta_chipinfo *yc; 371 372 /* Loop over except the last default entry. */ 373 for (yc = yc_chipsets; yc < yc_chipsets + 374 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 375 if (pci_id == yc->yc_id) 376 break; 377 378 if (flagp != NULL) 379 *flagp = yc->yc_flags; 380 381 return (yc->yc_chiptype); 382 } 383 384 static void 385 pccbb_shutdown(void *arg) 386 { 387 struct pccbb_softc *sc = arg; 388 pcireg_t command; 389 390 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 391 392 /* 393 * turn off power 394 * 395 * XXX - do not turn off power if chipset is TI 113X because 396 * only TI 1130 with PowerMac 2400 hangs in pccbb_power(). 397 */ 398 if (sc->sc_chipset != CB_TI113X) { 399 pccbb_power((cardbus_chipset_tag_t)sc, 400 CARDBUS_VCC_0V | CARDBUS_VPP_0V); 401 } 402 403 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 404 0); 405 406 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 407 408 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 409 PCI_COMMAND_MASTER_ENABLE); 410 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 411 412 } 413 414 void 415 pccbbattach(struct device *parent, struct device *self, void *aux) 416 { 417 struct pccbb_softc *sc = (void *)self; 418 struct pci_attach_args *pa = aux; 419 pci_chipset_tag_t pc = pa->pa_pc; 420 pcireg_t busreg, reg, sock_base; 421 bus_addr_t sockbase; 422 char devinfo[256]; 423 int flags; 424 int pwrmgt_offs; 425 426 #ifdef __HAVE_PCCBB_ATTACH_HOOK 427 pccbb_attach_hook(parent, self, pa); 428 #endif 429 430 callout_init(&sc->sc_insert_ch); 431 callout_setfunc(&sc->sc_insert_ch, pci113x_insert, sc); 432 433 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 434 435 pci_devinfo(pa->pa_id, 0, 0, devinfo, sizeof(devinfo)); 436 printf(": %s (rev. 0x%02x)", devinfo, PCI_REVISION(pa->pa_class)); 437 DPRINTF((" (chipflags %x)", flags)); 438 printf("\n"); 439 440 TAILQ_INIT(&sc->sc_memwindow); 441 TAILQ_INIT(&sc->sc_iowindow); 442 443 #if rbus 444 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 445 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 446 447 #if 0 448 printf("pa->pa_memt: %08x vs rbus_mem->rb_bt: %08x\n", 449 pa->pa_memt, sc->sc_rbus_memt->rb_bt); 450 #endif 451 #endif /* rbus */ 452 453 sc->sc_flags &= ~CBB_MEMHMAPPED; 454 455 /* power management: set D0 state */ 456 sc->sc_pwrmgt_offs = 0; 457 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, 458 &pwrmgt_offs, 0)) { 459 reg = pci_conf_read(pc, pa->pa_tag, pwrmgt_offs + PCI_PMCSR); 460 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 461 reg & 0x100 /* PCI_PMCSR_PME_EN */) { 462 reg &= ~PCI_PMCSR_STATE_MASK; 463 reg |= PCI_PMCSR_STATE_D0; 464 reg &= ~(0x100 /* PCI_PMCSR_PME_EN */); 465 pci_conf_write(pc, pa->pa_tag, 466 pwrmgt_offs + PCI_PMCSR, reg); 467 } 468 469 sc->sc_pwrmgt_offs = pwrmgt_offs; 470 } 471 472 /* 473 * MAP socket registers and ExCA registers on memory-space 474 * When no valid address is set on socket base registers (on pci 475 * config space), get it not polite way. 476 */ 477 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 478 479 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 480 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 481 /* The address must be valid. */ 482 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 483 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL)) { 484 printf("%s: can't map socket base address 0x%lx\n", 485 sc->sc_dev.dv_xname, (unsigned long)sock_base); 486 /* 487 * I think it's funny: socket base registers must be 488 * mapped on memory space, but ... 489 */ 490 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 491 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 492 NULL)) { 493 printf("%s: can't map socket base address" 494 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 495 (unsigned long)sockbase); 496 /* give up... allocate reg space via rbus. */ 497 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 498 } else 499 sc->sc_flags |= CBB_MEMHMAPPED; 500 } else { 501 DPRINTF(("%s: socket base address 0x%lx\n", 502 sc->sc_dev.dv_xname, (unsigned long)sockbase)); 503 sc->sc_flags |= CBB_MEMHMAPPED; 504 } 505 } 506 507 sc->sc_mem_start = 0; /* XXX */ 508 sc->sc_mem_end = 0xffffffff; /* XXX */ 509 510 /* 511 * When interrupt isn't routed correctly, give up probing cbb and do 512 * not kill pcic-compatible port. 513 * 514 * However, if we are using an ioapic, avoid this check -- pa_intrline 515 * may well be zero, with the interrupt routed through the apic. 516 */ 517 518 #if NIOAPIC == 0 && NACPI == 0 519 if ((0 == pa->pa_intrline) || (255 == pa->pa_intrline)) { 520 printf("%s: NOT USED because of unconfigured interrupt\n", 521 sc->sc_dev.dv_xname); 522 return; 523 } 524 #endif 525 526 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 527 528 /* pccbb_machdep.c end */ 529 530 #if defined CBB_DEBUG 531 { 532 static const char *intrname[] = { "NON", "A", "B", "C", "D" }; 533 printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname, 534 intrname[pa->pa_intrpin], pa->pa_intrline); 535 } 536 #endif 537 538 /* setup softc */ 539 sc->sc_pc = pc; 540 sc->sc_iot = pa->pa_iot; 541 sc->sc_memt = pa->pa_memt; 542 sc->sc_dmat = pa->pa_dmat; 543 sc->sc_tag = pa->pa_tag; 544 sc->sc_function = pa->pa_function; 545 sc->sc_sockbase = sock_base; 546 sc->sc_busnum = busreg; 547 548 memcpy(&sc->sc_pa, pa, sizeof(*pa)); 549 550 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 551 552 shutdownhook_establish(pccbb_shutdown, sc); 553 554 /* Disable legacy register mapping. */ 555 switch (sc->sc_chipset) { 556 case CB_RX5C46X: /* fallthrough */ 557 #if 0 558 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 559 case CB_RX5C47X: 560 #endif 561 /* 562 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 563 * cannot be disabled by substituting 0 into PCI_LEGACY 564 * register. Ricoh CardBus bridges have special bits on Bridge 565 * control reg (addr 0x3e on PCI config space). 566 */ 567 reg = pci_conf_read(pc, pa->pa_tag, PCI_BCR_INTR); 568 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 569 pci_conf_write(pc, pa->pa_tag, PCI_BCR_INTR, reg); 570 break; 571 572 default: 573 /* XXX I don't know proper way to kill legacy I/O. */ 574 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 575 break; 576 } 577 578 config_defer(self, pccbb_pci_callback); 579 } 580 581 582 583 584 /* 585 * static void pccbb_pci_callback(struct device *self) 586 * 587 * The actual attach routine: get memory space for YENTA register 588 * space, setup YENTA register and route interrupt. 589 * 590 * This function should be deferred because this device may obtain 591 * memory space dynamically. This function must avoid obtaining 592 * memory area which has already kept for another device. 593 */ 594 static void 595 pccbb_pci_callback(struct device *self) 596 { 597 struct pccbb_softc *sc = (void *)self; 598 pci_chipset_tag_t pc = sc->sc_pc; 599 pci_intr_handle_t ih; 600 const char *intrstr = NULL; 601 bus_addr_t sockbase; 602 struct cbslot_attach_args cba; 603 struct pcmciabus_attach_args paa; 604 struct cardslot_attach_args caa; 605 struct cardslot_softc *csc; 606 607 if (!(sc->sc_flags & CBB_MEMHMAPPED)) { 608 /* The socket registers aren't mapped correctly. */ 609 #if rbus 610 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 611 (sc->sc_chipset == CB_RX5C47X 612 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 613 0, &sockbase, &sc->sc_base_memh)) { 614 return; 615 } 616 sc->sc_base_memt = sc->sc_memt; 617 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 618 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 619 sc->sc_dev.dv_xname, (unsigned long)sockbase, 620 (unsigned long)pci_conf_read(pc, sc->sc_tag, 621 PCI_SOCKBASE))); 622 #else 623 sc->sc_base_memt = sc->sc_memt; 624 #if !defined CBB_PCI_BASE 625 #define CBB_PCI_BASE 0x20000000 626 #endif 627 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 628 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 629 /* cannot allocate memory space */ 630 return; 631 } 632 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 633 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 634 sc->sc_dev.dv_xname, (unsigned long)sock_base, 635 (unsigned long)pci_conf_read(pc, 636 sc->sc_tag, PCI_SOCKBASE))); 637 sc->sc_sockbase = sockbase; 638 #endif 639 sc->sc_flags |= CBB_MEMHMAPPED; 640 } 641 642 /* bus bridge initialization */ 643 pccbb_chipinit(sc); 644 645 /* clear data structure for child device interrupt handlers */ 646 LIST_INIT(&sc->sc_pil); 647 sc->sc_pil_intr_enable = 1; 648 649 /* Map and establish the interrupt. */ 650 if (pci_intr_map(&sc->sc_pa, &ih)) { 651 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 652 return; 653 } 654 intrstr = pci_intr_string(pc, ih); 655 656 /* 657 * XXX pccbbintr should be called under the priority lower 658 * than any other hard interupts. 659 */ 660 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 661 662 if (sc->sc_ih == NULL) { 663 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 664 if (intrstr != NULL) { 665 printf(" at %s", intrstr); 666 } 667 printf("\n"); 668 return; 669 } 670 671 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 672 powerhook_establish(sc->sc_dev.dv_xname, pccbb_powerhook, sc); 673 674 { 675 u_int32_t sockstat; 676 677 sockstat = bus_space_read_4(sc->sc_base_memt, 678 sc->sc_base_memh, CB_SOCKET_STAT); 679 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 680 sc->sc_flags |= CBB_CARDEXIST; 681 } 682 } 683 684 /* 685 * attach cardbus 686 */ 687 { 688 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 689 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 690 691 /* initialize cbslot_attach */ 692 cba.cba_busname = "cardbus"; 693 cba.cba_iot = sc->sc_iot; 694 cba.cba_memt = sc->sc_memt; 695 cba.cba_dmat = sc->sc_dmat; 696 cba.cba_bus = (busreg >> 8) & 0x0ff; 697 cba.cba_cc = (void *)sc; 698 cba.cba_cf = &pccbb_funcs; 699 cba.cba_intrline = sc->sc_pa.pa_intrline; 700 701 #if rbus 702 cba.cba_rbus_iot = sc->sc_rbus_iot; 703 cba.cba_rbus_memt = sc->sc_rbus_memt; 704 #endif 705 706 cba.cba_cacheline = PCI_CACHELINE(bhlc); 707 cba.cba_lattimer = PCI_CB_LATENCY(busreg); 708 709 if (bootverbose) { 710 printf("%s: cacheline 0x%x lattimer 0x%x\n", 711 sc->sc_dev.dv_xname, cba.cba_cacheline, 712 cba.cba_lattimer); 713 printf("%s: bhlc 0x%x lscp 0x%x\n", 714 sc->sc_dev.dv_xname, bhlc, busreg); 715 } 716 #if defined SHOW_REGS 717 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 718 sc->sc_base_memh); 719 #endif 720 } 721 722 pccbb_pcmcia_attach_setup(sc, &paa); 723 caa.caa_cb_attach = NULL; 724 if (cba.cba_bus == 0) 725 printf("%s: secondary bus number uninitialized; try PCI_BUS_FIXUP\n", sc->sc_dev.dv_xname); 726 else 727 caa.caa_cb_attach = &cba; 728 caa.caa_16_attach = &paa; 729 caa.caa_ph = &sc->sc_pcmcia_h; 730 731 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 732 DPRINTF(("%s: found cardslot\n", __func__)); 733 sc->sc_csc = csc; 734 } 735 736 return; 737 } 738 739 740 741 742 743 /* 744 * static void pccbb_chipinit(struct pccbb_softc *sc) 745 * 746 * This function initialize YENTA chip registers listed below: 747 * 1) PCI command reg, 748 * 2) PCI and CardBus latency timer, 749 * 3) route PCI interrupt, 750 * 4) close all memory and io windows. 751 * 5) turn off bus power. 752 * 6) card detect and power cycle interrupts on. 753 * 7) clear interrupt 754 */ 755 static void 756 pccbb_chipinit(struct pccbb_softc *sc) 757 { 758 pci_chipset_tag_t pc = sc->sc_pc; 759 pcitag_t tag = sc->sc_tag; 760 bus_space_tag_t bmt = sc->sc_base_memt; 761 bus_space_handle_t bmh = sc->sc_base_memh; 762 pcireg_t reg; 763 764 /* 765 * Set PCI command reg. 766 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 767 */ 768 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 769 /* I believe it is harmless. */ 770 reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 771 PCI_COMMAND_MASTER_ENABLE); 772 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg); 773 774 /* 775 * Set CardBus latency timer. 776 */ 777 reg = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 778 if (PCI_CB_LATENCY(reg) < 0x20) { 779 reg &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 780 reg |= (0x20 << PCI_CB_LATENCY_SHIFT); 781 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, reg); 782 } 783 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 784 PCI_CB_LATENCY(reg), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 785 786 /* 787 * Set PCI latency timer. 788 */ 789 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 790 if (PCI_LATTIMER(reg) < 0x10) { 791 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 792 reg |= (0x10 << PCI_LATTIMER_SHIFT); 793 pci_conf_write(pc, tag, PCI_BHLC_REG, reg); 794 } 795 DPRINTF(("PCI latency timer 0x%x (%x)\n", 796 PCI_LATTIMER(reg), pci_conf_read(pc, tag, PCI_BHLC_REG))); 797 798 799 /* Route functional interrupts to PCI. */ 800 reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 801 reg |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 802 reg |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 803 reg |= CB_BCR_RESET_ENABLE; /* assert reset */ 804 pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 805 806 switch (sc->sc_chipset) { 807 case CB_TI113X: 808 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 809 /* This bit is shared, but may read as 0 on some chips, so set 810 it explicitly on both functions. */ 811 reg |= PCI113X_CBCTRL_PCI_IRQ_ENA; 812 /* CSC intr enable */ 813 reg |= PCI113X_CBCTRL_PCI_CSC; 814 /* functional intr prohibit | prohibit ISA routing */ 815 reg &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 816 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 817 break; 818 819 case CB_TI12XX: 820 /* 821 * Some TI 12xx (and [14][45]xx) based pci cards 822 * sometimes have issues with the MFUNC register not 823 * being initialized due to a bad EEPROM on board. 824 * Laptops that this matters on have this register 825 * properly initialized. 826 * 827 * The TI125X parts have a different register. 828 */ 829 reg = pci_conf_read(pc, tag, PCI12XX_MFUNC); 830 if (reg == 0) { 831 reg &= ~PCI12XX_MFUNC_PIN0; 832 reg |= PCI12XX_MFUNC_PIN0_INTA; 833 if ((pci_conf_read(pc, tag, PCI_SYSCTRL) & 834 PCI12XX_SYSCTRL_INTRTIE) == 0) { 835 reg &= ~PCI12XX_MFUNC_PIN1; 836 reg |= PCI12XX_MFUNC_PIN1_INTB; 837 } 838 pci_conf_write(pc, tag, PCI12XX_MFUNC, reg); 839 } 840 /* fallthrough */ 841 842 case CB_TI125X: 843 /* 844 * Disable zoom video. Some machines initialize this 845 * improperly and experience has shown that this helps 846 * prevent strange behavior. 847 */ 848 pci_conf_write(pc, tag, PCI12XX_MMCTRL, 0); 849 850 reg = pci_conf_read(pc, tag, PCI_SYSCTRL); 851 reg |= PCI12XX_SYSCTRL_VCCPROT; 852 pci_conf_write(pc, tag, PCI_SYSCTRL, reg); 853 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 854 reg |= PCI12XX_CBCTRL_CSC; 855 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 856 break; 857 858 case CB_TOPIC95B: 859 reg = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 860 reg |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 861 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, reg); 862 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 863 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 864 sc->sc_dev.dv_xname, reg)); 865 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 866 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 867 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 868 DPRINTF(("0x%x\n", reg)); 869 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 870 break; 871 872 case CB_TOPIC97: 873 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 874 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 875 sc->sc_dev.dv_xname, reg)); 876 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 877 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 878 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 879 reg |= TOPIC97_SLOT_CTRL_PCIINT; 880 reg &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 881 DPRINTF(("0x%x\n", reg)); 882 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 883 /* make sure to assert LV card support bits */ 884 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 885 0x800 + 0x3e, 886 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 887 0x800 + 0x3e) | 0x03); 888 break; 889 } 890 891 /* Close all memory and I/O windows. */ 892 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 893 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 894 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 895 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 896 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 897 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 898 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 899 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 900 901 /* reset 16-bit pcmcia bus */ 902 bus_space_write_1(bmt, bmh, 0x800 + PCIC_INTR, 903 bus_space_read_1(bmt, bmh, 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 904 905 /* turn off power */ 906 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 907 908 /* CSC Interrupt: Card detect and power cycle interrupts on */ 909 reg = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 910 reg |= CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; 911 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, reg); 912 /* reset interrupt */ 913 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 914 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 915 } 916 917 918 919 920 /* 921 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 922 * struct pcmciabus_attach_args *paa) 923 * 924 * This function attaches 16-bit PCcard bus. 925 */ 926 STATIC void 927 pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 928 struct pcmciabus_attach_args *paa) 929 { 930 struct pcic_handle *ph = &sc->sc_pcmcia_h; 931 #if rbus 932 rbus_tag_t rb; 933 #endif 934 935 /* initialize pcmcia part in pccbb_softc */ 936 ph->ph_parent = (struct device *)sc; 937 ph->sock = sc->sc_function; 938 ph->flags = 0; 939 ph->shutdown = 0; 940 ph->ih_irq = sc->sc_pa.pa_intrline; 941 ph->ph_bus_t = sc->sc_base_memt; 942 ph->ph_bus_h = sc->sc_base_memh; 943 ph->ph_read = pccbb_pcmcia_read; 944 ph->ph_write = pccbb_pcmcia_write; 945 sc->sc_pct = &pccbb_pcmcia_funcs; 946 947 /* 948 * We need to do a few things here: 949 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 950 * setting the IRQ numbers to 0. 951 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 952 * routing of CSC interrupts (e.g. card removal) to PCI while in 953 * PCMCIA mode. We just leave this set all the time. 954 * 3) Enable card insertion/removal interrupts in case the chip also 955 * needs that while in PCMCIA mode. 956 * 4) Clear any pending CSC interrupt. 957 */ 958 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE); 959 if (sc->sc_chipset == CB_TI113X) { 960 Pcic_write(ph, PCIC_CSC_INTR, 0); 961 } else { 962 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 963 Pcic_read(ph, PCIC_CSC); 964 } 965 966 /* initialize pcmcia bus attachment */ 967 paa->paa_busname = "pcmcia"; 968 paa->pct = sc->sc_pct; 969 paa->pch = ph; 970 paa->iobase = 0; /* I don't use them */ 971 paa->iosize = 0; 972 #if rbus 973 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 974 paa->iobase = rb->rb_start + rb->rb_offset; 975 paa->iosize = rb->rb_end - rb->rb_start; 976 #endif 977 978 return; 979 } 980 981 #if 0 982 STATIC void 983 pccbb_pcmcia_attach_card(struct pcic_handle *ph) 984 { 985 if (ph->flags & PCIC_FLAG_CARDP) { 986 panic("pccbb_pcmcia_attach_card: already attached"); 987 } 988 989 /* call the MI attach function */ 990 pcmcia_card_attach(ph->pcmcia); 991 992 ph->flags |= PCIC_FLAG_CARDP; 993 } 994 995 STATIC void 996 pccbb_pcmcia_detach_card(struct pcic_handle *ph, int flags) 997 { 998 if (!(ph->flags & PCIC_FLAG_CARDP)) { 999 panic("pccbb_pcmcia_detach_card: already detached"); 1000 } 1001 1002 ph->flags &= ~PCIC_FLAG_CARDP; 1003 1004 /* call the MI detach function */ 1005 pcmcia_card_detach(ph->pcmcia, flags); 1006 } 1007 #endif 1008 1009 /* 1010 * int pccbbintr(arg) 1011 * void *arg; 1012 * This routine handles the interrupt from Yenta PCI-CardBus bridge 1013 * itself. 1014 */ 1015 int 1016 pccbbintr(void *arg) 1017 { 1018 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1019 u_int32_t sockevent, sockstate; 1020 bus_space_tag_t memt = sc->sc_base_memt; 1021 bus_space_handle_t memh = sc->sc_base_memh; 1022 struct pcic_handle *ph = &sc->sc_pcmcia_h; 1023 1024 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 1025 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 1026 Pcic_read(ph, PCIC_CSC); 1027 1028 if (sockevent == 0) { 1029 /* This intr is not for me: it may be for my child devices. */ 1030 if (sc->sc_pil_intr_enable) { 1031 return pccbbintr_function(sc); 1032 } else { 1033 return 0; 1034 } 1035 } 1036 1037 aprint_debug("%s: enter sockevent %" PRIx32 "\n", __func__, sockevent); 1038 1039 if (sockevent & CB_SOCKET_EVENT_CD) { 1040 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1041 if (0x00 != (sockstate & CB_SOCKET_STAT_CD)) { 1042 /* A card should be removed. */ 1043 if (sc->sc_flags & CBB_CARDEXIST) { 1044 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 1045 sockevent)); 1046 DPRINTF((" card removed, 0x%08x\n", sockstate)); 1047 sc->sc_flags &= ~CBB_CARDEXIST; 1048 if (sc->sc_csc->sc_status & 1049 CARDSLOT_STATUS_CARD_16) { 1050 #if 0 1051 struct pcic_handle *ph = 1052 &sc->sc_pcmcia_h; 1053 1054 pcmcia_card_deactivate(ph->pcmcia); 1055 pccbb_pcmcia_socket_disable(ph); 1056 pccbb_pcmcia_detach_card(ph, 1057 DETACH_FORCE); 1058 #endif 1059 cardslot_event_throw(sc->sc_csc, 1060 CARDSLOT_EVENT_REMOVAL_16); 1061 } else if (sc->sc_csc->sc_status & 1062 CARDSLOT_STATUS_CARD_CB) { 1063 /* Cardbus intr removed */ 1064 cardslot_event_throw(sc->sc_csc, 1065 CARDSLOT_EVENT_REMOVAL_CB); 1066 } 1067 } else if (sc->sc_flags & CBB_INSERTING) { 1068 sc->sc_flags &= ~CBB_INSERTING; 1069 callout_stop(&sc->sc_insert_ch); 1070 } 1071 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 1072 /* 1073 * The pccbbintr may called from powerdown hook when 1074 * the system resumed, to detect the card 1075 * insertion/removal during suspension. 1076 */ 1077 (sc->sc_flags & CBB_CARDEXIST) == 0) { 1078 if (sc->sc_flags & CBB_INSERTING) { 1079 callout_stop(&sc->sc_insert_ch); 1080 } 1081 callout_schedule(&sc->sc_insert_ch, hz / 5); 1082 sc->sc_flags |= CBB_INSERTING; 1083 } 1084 } 1085 1086 if (sockevent & CB_SOCKET_EVENT_POWER) { 1087 DPRINTF(("Powercycling because of socket event\n")); 1088 /* XXX: Does not happen when attaching a 16-bit card */ 1089 sc->sc_pwrcycle++; 1090 wakeup(&sc->sc_pwrcycle); 1091 } 1092 1093 return (1); 1094 } 1095 1096 /* 1097 * static int pccbbintr_function(struct pccbb_softc *sc) 1098 * 1099 * This function calls each interrupt handler registered at the 1100 * bridge. The interrupt handlers are called in registered order. 1101 */ 1102 static int 1103 pccbbintr_function(struct pccbb_softc *sc) 1104 { 1105 int retval = 0, val; 1106 struct pccbb_intrhand_list *pil; 1107 int s, splchanged; 1108 1109 for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1110 pil = LIST_NEXT(pil, pil_next)) { 1111 /* 1112 * XXX priority change. gross. I use if-else 1113 * sentense instead of switch-case sentense because of 1114 * avoiding duplicate case value error. More than one 1115 * IPL_XXX use same value. It depends on 1116 * implimentation. 1117 */ 1118 splchanged = 1; 1119 if (pil->pil_level == IPL_SERIAL) { 1120 s = splserial(); 1121 } else if (pil->pil_level == IPL_HIGH) { 1122 s = splhigh(); 1123 } else if (pil->pil_level == IPL_CLOCK) { 1124 s = splclock(); 1125 } else if (pil->pil_level == IPL_AUDIO) { 1126 s = splaudio(); 1127 } else if (pil->pil_level == IPL_VM) { 1128 s = splvm(); 1129 } else if (pil->pil_level == IPL_TTY) { 1130 s = spltty(); 1131 } else if (pil->pil_level == IPL_SOFTSERIAL) { 1132 s = splsoftserial(); 1133 } else if (pil->pil_level == IPL_NET) { 1134 s = splnet(); 1135 } else { 1136 s = 0; /* XXX: gcc */ 1137 splchanged = 0; 1138 /* XXX: ih lower than IPL_BIO runs w/ IPL_BIO. */ 1139 } 1140 1141 val = (*pil->pil_func)(pil->pil_arg); 1142 1143 if (splchanged != 0) { 1144 splx(s); 1145 } 1146 1147 retval = retval == 1 ? 1 : 1148 retval == 0 ? val : val != 0 ? val : retval; 1149 } 1150 1151 return retval; 1152 } 1153 1154 static void 1155 pci113x_insert(void *arg) 1156 { 1157 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1158 u_int32_t sockevent, sockstate; 1159 1160 if (!(sc->sc_flags & CBB_INSERTING)) { 1161 /* We add a card only under inserting state. */ 1162 return; 1163 } 1164 sc->sc_flags &= ~CBB_INSERTING; 1165 1166 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1167 CB_SOCKET_EVENT); 1168 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1169 CB_SOCKET_STAT); 1170 1171 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1172 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1173 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1174 sc->sc_flags |= CBB_CARDEXIST; 1175 /* call pccard interrupt handler here */ 1176 if (sockstate & CB_SOCKET_STAT_16BIT) { 1177 /* 16-bit card found */ 1178 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1179 cardslot_event_throw(sc->sc_csc, 1180 CARDSLOT_EVENT_INSERTION_16); 1181 } else if (sockstate & CB_SOCKET_STAT_CB) { 1182 /* cardbus card found */ 1183 /* cardbus_attach_card(sc->sc_csc); */ 1184 cardslot_event_throw(sc->sc_csc, 1185 CARDSLOT_EVENT_INSERTION_CB); 1186 } else { 1187 /* who are you? */ 1188 } 1189 } else { 1190 callout_schedule(&sc->sc_insert_ch, hz / 10); 1191 } 1192 } 1193 1194 #define PCCBB_PCMCIA_OFFSET 0x800 1195 static u_int8_t 1196 pccbb_pcmcia_read(struct pcic_handle *ph, int reg) 1197 { 1198 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1199 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1200 1201 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1202 PCCBB_PCMCIA_OFFSET + reg); 1203 } 1204 1205 static void 1206 pccbb_pcmcia_write(struct pcic_handle *ph, int reg, u_int8_t val) 1207 { 1208 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1209 val); 1210 1211 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1212 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1213 } 1214 1215 /* 1216 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1217 */ 1218 STATIC int 1219 pccbb_ctrl(cardbus_chipset_tag_t ct, int command) 1220 { 1221 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1222 1223 switch (command) { 1224 case CARDBUS_CD: 1225 if (2 == pccbb_detect_card(sc)) { 1226 int retval = 0; 1227 int status = cb_detect_voltage(sc); 1228 if (PCCARD_VCC_5V & status) { 1229 retval |= CARDBUS_5V_CARD; 1230 } 1231 if (PCCARD_VCC_3V & status) { 1232 retval |= CARDBUS_3V_CARD; 1233 } 1234 if (PCCARD_VCC_XV & status) { 1235 retval |= CARDBUS_XV_CARD; 1236 } 1237 if (PCCARD_VCC_YV & status) { 1238 retval |= CARDBUS_YV_CARD; 1239 } 1240 return retval; 1241 } else { 1242 return 0; 1243 } 1244 case CARDBUS_RESET: 1245 return cb_reset(sc); 1246 case CARDBUS_IO_ENABLE: /* fallthrough */ 1247 case CARDBUS_IO_DISABLE: /* fallthrough */ 1248 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1249 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1250 case CARDBUS_BM_ENABLE: /* fallthrough */ 1251 case CARDBUS_BM_DISABLE: /* fallthrough */ 1252 /* XXX: I think we don't need to call this function below. */ 1253 return pccbb_cardenable(sc, command); 1254 } 1255 1256 return 0; 1257 } 1258 1259 /* 1260 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1261 * This function returns true when it succeeds and returns false when 1262 * it fails. 1263 */ 1264 STATIC int 1265 pccbb_power(cardbus_chipset_tag_t ct, int command) 1266 { 1267 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1268 u_int32_t status, osock_ctrl, sock_ctrl, reg_ctrl; 1269 bus_space_tag_t memt = sc->sc_base_memt; 1270 bus_space_handle_t memh = sc->sc_base_memh; 1271 int on = 0, pwrcycle, s, times; 1272 struct timeval before, after, diff; 1273 1274 DPRINTF(("pccbb_power: %s and %s [0x%x]\n", 1275 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1276 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1277 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1278 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1279 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1280 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1281 "UNKNOWN", 1282 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1283 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1284 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1285 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1286 "UNKNOWN", command)); 1287 1288 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1289 osock_ctrl = sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1290 1291 switch (command & CARDBUS_VCCMASK) { 1292 case CARDBUS_VCC_UC: 1293 break; 1294 case CARDBUS_VCC_5V: 1295 on++; 1296 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1297 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1298 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1299 } else { 1300 printf("%s: BAD voltage request: no 5 V card\n", 1301 sc->sc_dev.dv_xname); 1302 return 0; 1303 } 1304 break; 1305 case CARDBUS_VCC_3V: 1306 on++; 1307 if (CB_SOCKET_STAT_3VCARD & status) { 1308 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1309 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1310 } else { 1311 printf("%s: BAD voltage request: no 3.3 V card\n", 1312 sc->sc_dev.dv_xname); 1313 return 0; 1314 } 1315 break; 1316 case CARDBUS_VCC_0V: 1317 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1318 break; 1319 default: 1320 return 0; /* power NEVER changed */ 1321 } 1322 1323 switch (command & CARDBUS_VPPMASK) { 1324 case CARDBUS_VPP_UC: 1325 break; 1326 case CARDBUS_VPP_0V: 1327 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1328 break; 1329 case CARDBUS_VPP_VCC: 1330 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1331 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1332 break; 1333 case CARDBUS_VPP_12V: 1334 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1335 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1336 break; 1337 } 1338 1339 pwrcycle = sc->sc_pwrcycle; 1340 aprint_debug("%s: osock_ctrl %#" PRIx32 " sock_ctrl %#" PRIx32 "\n", 1341 device_xname(&sc->sc_dev), osock_ctrl, sock_ctrl); 1342 1343 microtime(&before); 1344 s = splbio(); 1345 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1346 1347 /* 1348 * Wait as long as 200ms for a power-cycle interrupt. If 1349 * interrupts are enabled, but the socket has already 1350 * changed to the desired status, keep waiting for the 1351 * interrupt. "Consuming" the interrupt in this way keeps 1352 * the interrupt from prematurely waking some subsequent 1353 * pccbb_power call. 1354 * 1355 * XXX Not every bridge interrupts on the ->OFF transition. 1356 * XXX That's ok, we will time-out after 200ms. 1357 * 1358 * XXX The power cycle event will never happen when attaching 1359 * XXX a 16-bit card. That's ok, we will time-out after 1360 * XXX 200ms. 1361 */ 1362 for (times = 5; --times >= 0; ) { 1363 if (cold) 1364 DELAY(40 * 1000); 1365 else { 1366 (void)tsleep(&sc->sc_pwrcycle, PWAIT, "pccpwr", 1367 hz / 25); 1368 if (pwrcycle == sc->sc_pwrcycle) 1369 continue; 1370 } 1371 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1372 if ((status & CB_SOCKET_STAT_PWRCYCLE) != 0 && on) 1373 break; 1374 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0 && !on) 1375 break; 1376 } 1377 splx(s); 1378 microtime(&after); 1379 timersub(&after, &before, &diff); 1380 aprint_debug("%s: wait took%s %ld.%06lds\n", sc->sc_dev.dv_xname, 1381 (on && times < 0) ? " too long" : "", diff.tv_sec, diff.tv_usec); 1382 1383 /* 1384 * Ok, wait a bit longer for things to settle. 1385 */ 1386 if (on && sc->sc_chipset == CB_TOPIC95B) 1387 delay_ms(100, sc); 1388 1389 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1390 1391 if (on && sc->sc_chipset != CB_TOPIC95B) { 1392 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0) 1393 printf("%s: power on failed?\n", sc->sc_dev.dv_xname); 1394 } 1395 1396 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1397 printf("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1398 sc->sc_dev.dv_xname, sock_ctrl, status); 1399 printf("%s: disabling socket\n", sc->sc_dev.dv_xname); 1400 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1401 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1402 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1403 status &= ~CB_SOCKET_STAT_BADVCC; 1404 bus_space_write_4(memt, memh, CB_SOCKET_STAT, status); 1405 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1406 CB_SOCKET_STAT)); 1407 return 0; 1408 } 1409 1410 if (sc->sc_chipset == CB_TOPIC97) { 1411 reg_ctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL); 1412 reg_ctrl &= ~TOPIC97_REG_CTRL_TESTMODE; 1413 if ((command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V) 1414 reg_ctrl &= ~TOPIC97_REG_CTRL_CLKRUN_ENA; 1415 else 1416 reg_ctrl |= TOPIC97_REG_CTRL_CLKRUN_ENA; 1417 pci_conf_write(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL, reg_ctrl); 1418 } 1419 1420 return 1; /* power changed correctly */ 1421 } 1422 1423 #if defined CB_PCMCIA_POLL 1424 struct cb_poll_str { 1425 void *arg; 1426 int (*func)(void *); 1427 int level; 1428 pccard_chipset_tag_t ct; 1429 int count; 1430 struct callout poll_ch; 1431 }; 1432 1433 static struct cb_poll_str cb_poll[10]; 1434 static int cb_poll_n = 0; 1435 1436 static void cb_pcmcia_poll(void *arg); 1437 1438 static void 1439 cb_pcmcia_poll(void *arg) 1440 { 1441 struct cb_poll_str *poll = arg; 1442 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1443 struct pccbb_softc *sc = psc->cpc_parent; 1444 int s; 1445 u_int32_t spsr; /* socket present-state reg */ 1446 1447 callout_reset(&poll->poll_ch, hz / 10, cb_pcmcia_poll, poll); 1448 switch (poll->level) { 1449 case IPL_NET: 1450 s = splnet(); 1451 break; 1452 case IPL_BIO: 1453 s = splbio(); 1454 break; 1455 case IPL_TTY: /* fallthrough */ 1456 default: 1457 s = spltty(); 1458 break; 1459 } 1460 1461 spsr = 1462 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1463 CB_SOCKET_STAT); 1464 1465 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1466 if (!(spsr & 0x40)) { /* CINT low */ 1467 #else 1468 if (1) { 1469 #endif 1470 if ((*poll->func) (poll->arg) == 1) { 1471 ++poll->count; 1472 printf("intr: reported from poller, 0x%x\n", spsr); 1473 #if defined LEVEL2 1474 } else { 1475 printf("intr: miss! 0x%x\n", spsr); 1476 #endif 1477 } 1478 } 1479 splx(s); 1480 } 1481 #endif /* defined CB_PCMCIA_POLL */ 1482 1483 /* 1484 * static int pccbb_detect_card(struct pccbb_softc *sc) 1485 * return value: 0 if no card exists. 1486 * 1 if 16-bit card exists. 1487 * 2 if cardbus card exists. 1488 */ 1489 static int 1490 pccbb_detect_card(struct pccbb_softc *sc) 1491 { 1492 bus_space_handle_t base_memh = sc->sc_base_memh; 1493 bus_space_tag_t base_memt = sc->sc_base_memt; 1494 u_int32_t sockstat = 1495 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1496 int retval = 0; 1497 1498 /* CD1 and CD2 asserted */ 1499 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1500 /* card must be present */ 1501 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1502 /* NOTACARD DEASSERTED */ 1503 if (CB_SOCKET_STAT_CB & sockstat) { 1504 /* CardBus mode */ 1505 retval = 2; 1506 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1507 /* 16-bit mode */ 1508 retval = 1; 1509 } 1510 } 1511 } 1512 return retval; 1513 } 1514 1515 /* 1516 * STATIC int cb_reset(struct pccbb_softc *sc) 1517 * This function resets CardBus card. 1518 */ 1519 STATIC int 1520 cb_reset(struct pccbb_softc *sc) 1521 { 1522 /* 1523 * Reset Assert at least 20 ms 1524 * Some machines request longer duration. 1525 */ 1526 int reset_duration = 1527 (sc->sc_chipset == CB_RX5C47X ? 400 : 50); 1528 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1529 1530 /* Reset bit Assert (bit 6 at 0x3E) */ 1531 bcr |= CB_BCR_RESET_ENABLE; 1532 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1533 delay_ms(reset_duration, sc); 1534 1535 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1536 /* Reset bit Deassert (bit 6 at 0x3E) */ 1537 bcr &= ~CB_BCR_RESET_ENABLE; 1538 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1539 delay_ms(reset_duration, sc); 1540 } 1541 /* No card found on the slot. Keep Reset. */ 1542 return 1; 1543 } 1544 1545 /* 1546 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1547 * This function detect card Voltage. 1548 */ 1549 STATIC int 1550 cb_detect_voltage(struct pccbb_softc *sc) 1551 { 1552 u_int32_t psr; /* socket present-state reg */ 1553 bus_space_tag_t iot = sc->sc_base_memt; 1554 bus_space_handle_t ioh = sc->sc_base_memh; 1555 int vol = PCCARD_VCC_UKN; /* set 0 */ 1556 1557 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1558 1559 if (0x400u & psr) { 1560 vol |= PCCARD_VCC_5V; 1561 } 1562 if (0x800u & psr) { 1563 vol |= PCCARD_VCC_3V; 1564 } 1565 1566 return vol; 1567 } 1568 1569 STATIC int 1570 cbbprint(void *aux, const char *pcic) 1571 { 1572 #if 0 1573 struct cbslot_attach_args *cba = aux; 1574 1575 if (cba->cba_slot >= 0) { 1576 aprint_normal(" slot %d", cba->cba_slot); 1577 } 1578 #endif 1579 return UNCONF; 1580 } 1581 1582 /* 1583 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1584 * This function enables and disables the card 1585 */ 1586 STATIC int 1587 pccbb_cardenable(struct pccbb_softc *sc, int function) 1588 { 1589 u_int32_t command = 1590 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1591 1592 DPRINTF(("pccbb_cardenable:")); 1593 switch (function) { 1594 case CARDBUS_IO_ENABLE: 1595 command |= PCI_COMMAND_IO_ENABLE; 1596 break; 1597 case CARDBUS_IO_DISABLE: 1598 command &= ~PCI_COMMAND_IO_ENABLE; 1599 break; 1600 case CARDBUS_MEM_ENABLE: 1601 command |= PCI_COMMAND_MEM_ENABLE; 1602 break; 1603 case CARDBUS_MEM_DISABLE: 1604 command &= ~PCI_COMMAND_MEM_ENABLE; 1605 break; 1606 case CARDBUS_BM_ENABLE: 1607 command |= PCI_COMMAND_MASTER_ENABLE; 1608 break; 1609 case CARDBUS_BM_DISABLE: 1610 command &= ~PCI_COMMAND_MASTER_ENABLE; 1611 break; 1612 default: 1613 return 0; 1614 } 1615 1616 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1617 DPRINTF((" command reg 0x%x\n", command)); 1618 return 1; 1619 } 1620 1621 #if !rbus 1622 static int 1623 pccbb_io_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 1624 { 1625 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1626 int basereg; 1627 int limitreg; 1628 1629 if ((win < 0) || (win > 2)) { 1630 #if defined DIAGNOSTIC 1631 printf("cardbus_io_open: window out of range %d\n", win); 1632 #endif 1633 return 0; 1634 } 1635 1636 basereg = win * 8 + 0x2c; 1637 limitreg = win * 8 + 0x30; 1638 1639 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1640 start, basereg, end, limitreg)); 1641 1642 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1643 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1644 return 1; 1645 } 1646 1647 /* 1648 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1649 */ 1650 static int 1651 pccbb_io_close(cardbus_chipset_tag_t ct, int win) 1652 { 1653 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1654 int basereg; 1655 int limitreg; 1656 1657 if ((win < 0) || (win > 2)) { 1658 #if defined DIAGNOSTIC 1659 printf("cardbus_io_close: window out of range %d\n", win); 1660 #endif 1661 return 0; 1662 } 1663 1664 basereg = win * 8 + 0x2c; 1665 limitreg = win * 8 + 0x30; 1666 1667 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1668 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1669 return 1; 1670 } 1671 1672 static int 1673 pccbb_mem_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 1674 { 1675 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1676 int basereg; 1677 int limitreg; 1678 1679 if ((win < 0) || (win > 2)) { 1680 #if defined DIAGNOSTIC 1681 printf("cardbus_mem_open: window out of range %d\n", win); 1682 #endif 1683 return 0; 1684 } 1685 1686 basereg = win * 8 + 0x1c; 1687 limitreg = win * 8 + 0x20; 1688 1689 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1690 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1691 return 1; 1692 } 1693 1694 static int 1695 pccbb_mem_close(cardbus_chipset_tag_t ct, int win) 1696 { 1697 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1698 int basereg; 1699 int limitreg; 1700 1701 if ((win < 0) || (win > 2)) { 1702 #if defined DIAGNOSTIC 1703 printf("cardbus_mem_close: window out of range %d\n", win); 1704 #endif 1705 return 0; 1706 } 1707 1708 basereg = win * 8 + 0x1c; 1709 limitreg = win * 8 + 0x20; 1710 1711 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1712 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1713 return 1; 1714 } 1715 #endif 1716 1717 /* 1718 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1719 * int irq, 1720 * int level, 1721 * int (* func)(void *), 1722 * void *arg) 1723 * 1724 * This function registers an interrupt handler at the bridge, in 1725 * order not to call the interrupt handlers of child devices when 1726 * a card-deletion interrupt occurs. 1727 * 1728 * The arguments irq and level are not used. 1729 */ 1730 static void * 1731 pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, int irq, int level, 1732 int (*func)(void *), void *arg) 1733 { 1734 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1735 1736 return pccbb_intr_establish(sc, irq, level, func, arg); 1737 } 1738 1739 1740 /* 1741 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1742 * void *ih) 1743 * 1744 * This function removes an interrupt handler pointed by ih. 1745 */ 1746 static void 1747 pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih) 1748 { 1749 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1750 1751 pccbb_intr_disestablish(sc, ih); 1752 } 1753 1754 1755 void 1756 pccbb_intr_route(struct pccbb_softc *sc) 1757 { 1758 pcireg_t bcr, cbctrl; 1759 1760 /* initialize bridge intr routing */ 1761 bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1762 bcr &= ~CB_BCR_INTR_IREQ_ENABLE; 1763 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1764 1765 switch (sc->sc_chipset) { 1766 case CB_TI113X: 1767 cbctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1768 /* functional intr enabled */ 1769 cbctrl |= PCI113X_CBCTRL_PCI_INTR; 1770 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, cbctrl); 1771 break; 1772 default: 1773 break; 1774 } 1775 } 1776 1777 /* 1778 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1779 * int irq, 1780 * int level, 1781 * int (* func)(void *), 1782 * void *arg) 1783 * 1784 * This function registers an interrupt handler at the bridge, in 1785 * order not to call the interrupt handlers of child devices when 1786 * a card-deletion interrupt occurs. 1787 * 1788 * The arguments irq is not used because pccbb selects intr vector. 1789 */ 1790 static void * 1791 pccbb_intr_establish(struct pccbb_softc *sc, int irq, int level, 1792 int (*func)(void *), void *arg) 1793 { 1794 struct pccbb_intrhand_list *pil, *newpil; 1795 1796 DPRINTF(("pccbb_intr_establish start. %p\n", LIST_FIRST(&sc->sc_pil))); 1797 1798 if (LIST_EMPTY(&sc->sc_pil)) { 1799 pccbb_intr_route(sc); 1800 } 1801 1802 /* 1803 * Allocate a room for interrupt handler structure. 1804 */ 1805 if (NULL == (newpil = 1806 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1807 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1808 return NULL; 1809 } 1810 1811 newpil->pil_func = func; 1812 newpil->pil_arg = arg; 1813 newpil->pil_level = level; 1814 1815 if (LIST_EMPTY(&sc->sc_pil)) { 1816 LIST_INSERT_HEAD(&sc->sc_pil, newpil, pil_next); 1817 } else { 1818 for (pil = LIST_FIRST(&sc->sc_pil); 1819 LIST_NEXT(pil, pil_next) != NULL; 1820 pil = LIST_NEXT(pil, pil_next)); 1821 LIST_INSERT_AFTER(pil, newpil, pil_next); 1822 } 1823 1824 DPRINTF(("pccbb_intr_establish add pil. %p\n", 1825 LIST_FIRST(&sc->sc_pil))); 1826 1827 return newpil; 1828 } 1829 1830 /* 1831 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1832 * void *ih) 1833 * 1834 * This function removes an interrupt handler pointed by ih. ih 1835 * should be the value returned by cardbus_intr_establish() or 1836 * NULL. 1837 * 1838 * When ih is NULL, this function will do nothing. 1839 */ 1840 static void 1841 pccbb_intr_disestablish(struct pccbb_softc *sc, void *ih) 1842 { 1843 struct pccbb_intrhand_list *pil; 1844 pcireg_t reg; 1845 1846 DPRINTF(("pccbb_intr_disestablish start. %p\n", 1847 LIST_FIRST(&sc->sc_pil))); 1848 1849 if (ih == NULL) { 1850 /* intr handler is not set */ 1851 DPRINTF(("pccbb_intr_disestablish: no ih\n")); 1852 return; 1853 } 1854 1855 #ifdef DIAGNOSTIC 1856 for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1857 pil = LIST_NEXT(pil, pil_next)) { 1858 DPRINTF(("pccbb_intr_disestablish: pil %p\n", pil)); 1859 if (pil == ih) { 1860 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1861 break; 1862 } 1863 } 1864 if (pil == NULL) { 1865 panic("pccbb_intr_disestablish: %s cannot find pil %p", 1866 sc->sc_dev.dv_xname, ih); 1867 } 1868 #endif 1869 1870 pil = (struct pccbb_intrhand_list *)ih; 1871 LIST_REMOVE(pil, pil_next); 1872 free(pil, M_DEVBUF); 1873 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1874 1875 if (LIST_EMPTY(&sc->sc_pil)) { 1876 /* No interrupt handlers */ 1877 1878 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1879 1880 /* stop routing PCI intr */ 1881 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1882 reg |= CB_BCR_INTR_IREQ_ENABLE; 1883 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1884 1885 switch (sc->sc_chipset) { 1886 case CB_TI113X: 1887 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1888 /* functional intr disabled */ 1889 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1890 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1891 break; 1892 default: 1893 break; 1894 } 1895 } 1896 } 1897 1898 #if defined SHOW_REGS 1899 static void 1900 cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, bus_space_tag_t memt, 1901 bus_space_handle_t memh) 1902 { 1903 int i; 1904 printf("PCI config regs:"); 1905 for (i = 0; i < 0x50; i += 4) { 1906 if (i % 16 == 0) 1907 printf("\n 0x%02x:", i); 1908 printf(" %08x", pci_conf_read(pc, tag, i)); 1909 } 1910 for (i = 0x80; i < 0xb0; i += 4) { 1911 if (i % 16 == 0) 1912 printf("\n 0x%02x:", i); 1913 printf(" %08x", pci_conf_read(pc, tag, i)); 1914 } 1915 1916 if (memh == 0) { 1917 printf("\n"); 1918 return; 1919 } 1920 1921 printf("\nsocket regs:"); 1922 for (i = 0; i <= 0x10; i += 0x04) 1923 printf(" %08x", bus_space_read_4(memt, memh, i)); 1924 printf("\nExCA regs:"); 1925 for (i = 0; i < 0x08; ++i) 1926 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1927 printf("\n"); 1928 return; 1929 } 1930 #endif 1931 1932 /* 1933 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1934 * int busno, int function) 1935 * This is the function to make a tag to access config space of 1936 * a CardBus Card. It works same as pci_conf_read. 1937 */ 1938 static cardbustag_t 1939 pccbb_make_tag(cardbus_chipset_tag_t cc, int busno, int function) 1940 { 1941 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1942 1943 return pci_make_tag(sc->sc_pc, busno, 0, function); 1944 } 1945 1946 static void 1947 pccbb_free_tag(cardbus_chipset_tag_t cc, cardbustag_t tag) 1948 { 1949 } 1950 1951 /* 1952 * pccbb_conf_read 1953 * 1954 * This is the function to read the config space of a CardBus card. 1955 * It works the same as pci_conf_read(9). 1956 */ 1957 static cardbusreg_t 1958 pccbb_conf_read(cardbus_chipset_tag_t cc, cardbustag_t tag, int offset) 1959 { 1960 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1961 1962 return pci_conf_read(sc->sc_pc, tag, offset); 1963 } 1964 1965 /* 1966 * pccbb_conf_write 1967 * 1968 * This is the function to write the config space of a CardBus 1969 * card. It works the same as pci_conf_write(9). 1970 */ 1971 static void 1972 pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, int reg, 1973 cardbusreg_t val) 1974 { 1975 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1976 1977 pci_conf_write(sc->sc_pc, tag, reg, val); 1978 } 1979 1980 #if 0 1981 STATIC int 1982 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1983 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 1984 int speed, int flags, 1985 bus_space_handle_t * iohp) 1986 #endif 1987 /* 1988 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1989 * bus_addr_t start, bus_size_t size, 1990 * bus_size_t align, 1991 * struct pcmcia_io_handle *pcihp 1992 * 1993 * This function only allocates I/O region for pccard. This function 1994 * never maps the allocated region to pccard I/O area. 1995 * 1996 * XXX: The interface of this function is not very good, I believe. 1997 */ 1998 STATIC int 1999 pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, 2000 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 2001 { 2002 struct pcic_handle *ph = (struct pcic_handle *)pch; 2003 bus_addr_t ioaddr; 2004 int flags = 0; 2005 bus_space_tag_t iot; 2006 bus_space_handle_t ioh; 2007 bus_addr_t mask; 2008 #if rbus 2009 rbus_tag_t rb; 2010 #endif 2011 if (align == 0) { 2012 align = size; /* XXX: funny??? */ 2013 } 2014 2015 if (start != 0) { 2016 /* XXX: assume all card decode lower 10 bits by its hardware */ 2017 mask = 0x3ff; 2018 /* enforce to use only masked address */ 2019 start &= mask; 2020 } else { 2021 /* 2022 * calculate mask: 2023 * 1. get the most significant bit of size (call it msb). 2024 * 2. compare msb with the value of size. 2025 * 3. if size is larger, shift msb left once. 2026 * 4. obtain mask value to decrement msb. 2027 */ 2028 bus_size_t size_tmp = size; 2029 int shifts = 0; 2030 2031 mask = 1; 2032 while (size_tmp) { 2033 ++shifts; 2034 size_tmp >>= 1; 2035 } 2036 mask = (1 << shifts); 2037 if (mask < size) { 2038 mask <<= 1; 2039 } 2040 --mask; 2041 } 2042 2043 /* 2044 * Allocate some arbitrary I/O space. 2045 */ 2046 2047 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 2048 2049 #if rbus 2050 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 2051 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 2052 return 1; 2053 } 2054 DPRINTF(("pccbb_pcmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2055 (u_long) ioaddr, (u_long) size)); 2056 #else 2057 if (start) { 2058 ioaddr = start; 2059 if (bus_space_map(iot, start, size, 0, &ioh)) { 2060 return 1; 2061 } 2062 DPRINTF(("pccbb_pcmcia_io_alloc map port 0x%lx+0x%lx\n", 2063 (u_long) ioaddr, (u_long) size)); 2064 } else { 2065 flags |= PCMCIA_IO_ALLOCATED; 2066 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 2067 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 2068 size, align, 0, 0, &ioaddr, &ioh)) { 2069 /* No room be able to be get. */ 2070 return 1; 2071 } 2072 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2073 (u_long) ioaddr, (u_long) size)); 2074 } 2075 #endif 2076 2077 pcihp->iot = iot; 2078 pcihp->ioh = ioh; 2079 pcihp->addr = ioaddr; 2080 pcihp->size = size; 2081 pcihp->flags = flags; 2082 2083 return 0; 2084 } 2085 2086 /* 2087 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2088 * struct pcmcia_io_handle *pcihp) 2089 * 2090 * This function only frees I/O region for pccard. 2091 * 2092 * XXX: The interface of this function is not very good, I believe. 2093 */ 2094 void 2095 pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2096 struct pcmcia_io_handle *pcihp) 2097 { 2098 #if !rbus 2099 bus_space_tag_t iot = pcihp->iot; 2100 #endif 2101 bus_space_handle_t ioh = pcihp->ioh; 2102 bus_size_t size = pcihp->size; 2103 2104 #if rbus 2105 struct pccbb_softc *sc = 2106 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 2107 rbus_tag_t rb = sc->sc_rbus_iot; 2108 2109 rbus_space_free(rb, ioh, size, NULL); 2110 #else 2111 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 2112 bus_space_free(iot, ioh, size); 2113 else 2114 bus_space_unmap(iot, ioh, size); 2115 #endif 2116 } 2117 2118 /* 2119 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 2120 * bus_addr_t offset, bus_size_t size, 2121 * struct pcmcia_io_handle *pcihp, 2122 * int *windowp) 2123 * 2124 * This function maps the allocated I/O region to pccard. This function 2125 * never allocates any I/O region for pccard I/O area. I don't 2126 * understand why the original authors of pcmciabus separated alloc and 2127 * map. I believe the two must be unite. 2128 * 2129 * XXX: no wait timing control? 2130 */ 2131 int 2132 pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, bus_addr_t offset, 2133 bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp) 2134 { 2135 struct pcic_handle *ph = (struct pcic_handle *)pch; 2136 bus_addr_t ioaddr = pcihp->addr + offset; 2137 int i, win; 2138 #if defined CBB_DEBUG 2139 static const char *width_names[] = { "dynamic", "io8", "io16" }; 2140 #endif 2141 2142 /* Sanity check I/O handle. */ 2143 2144 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 2145 panic("pccbb_pcmcia_io_map iot is bogus"); 2146 } 2147 2148 /* XXX Sanity check offset/size. */ 2149 2150 win = -1; 2151 for (i = 0; i < PCIC_IO_WINS; i++) { 2152 if ((ph->ioalloc & (1 << i)) == 0) { 2153 win = i; 2154 ph->ioalloc |= (1 << i); 2155 break; 2156 } 2157 } 2158 2159 if (win == -1) { 2160 return 1; 2161 } 2162 2163 *windowp = win; 2164 2165 /* XXX this is pretty gross */ 2166 2167 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2168 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2169 2170 /* XXX wtf is this doing here? */ 2171 2172 #if 0 2173 printf(" port 0x%lx", (u_long) ioaddr); 2174 if (size > 1) { 2175 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2176 } 2177 #endif 2178 2179 ph->io[win].addr = ioaddr; 2180 ph->io[win].size = size; 2181 ph->io[win].width = width; 2182 2183 /* actual dirty register-value changing in the function below. */ 2184 pccbb_pcmcia_do_io_map(ph, win); 2185 2186 return 0; 2187 } 2188 2189 /* 2190 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2191 * 2192 * This function changes register-value to map I/O region for pccard. 2193 */ 2194 static void 2195 pccbb_pcmcia_do_io_map(struct pcic_handle *ph, int win) 2196 { 2197 static u_int8_t pcic_iowidth[3] = { 2198 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2199 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2200 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2201 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2202 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2203 }; 2204 2205 #define PCIC_SIA_START_LOW 0 2206 #define PCIC_SIA_START_HIGH 1 2207 #define PCIC_SIA_STOP_LOW 2 2208 #define PCIC_SIA_STOP_HIGH 3 2209 2210 int regbase_win = 0x8 + win * 0x04; 2211 u_int8_t ioctl, enable; 2212 2213 DPRINTF(("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx " 2214 "width %d\n", win, (unsigned long)ph->io[win].addr, 2215 (unsigned long)ph->io[win].size, ph->io[win].width * 8)); 2216 2217 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2218 ph->io[win].addr & 0xff); 2219 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2220 (ph->io[win].addr >> 8) & 0xff); 2221 2222 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2223 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2224 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2225 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2226 2227 ioctl = Pcic_read(ph, PCIC_IOCTL); 2228 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2229 switch (win) { 2230 case 0: 2231 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2232 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2233 PCIC_IOCTL_IO0_DATASIZE_MASK); 2234 ioctl |= pcic_iowidth[ph->io[win].width]; 2235 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2236 break; 2237 case 1: 2238 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2239 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2240 PCIC_IOCTL_IO1_DATASIZE_MASK); 2241 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2242 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2243 break; 2244 } 2245 Pcic_write(ph, PCIC_IOCTL, ioctl); 2246 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2247 #if defined(CBB_DEBUG) 2248 { 2249 u_int8_t start_low = 2250 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2251 u_int8_t start_high = 2252 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2253 u_int8_t stop_low = 2254 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2255 u_int8_t stop_high = 2256 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2257 printf("pccbb_pcmcia_do_io_map start %02x %02x, " 2258 "stop %02x %02x, ioctl %02x enable %02x\n", 2259 start_low, start_high, stop_low, stop_high, ioctl, enable); 2260 } 2261 #endif 2262 } 2263 2264 /* 2265 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2266 * 2267 * This function unmaps I/O region. No return value. 2268 */ 2269 STATIC void 2270 pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t pch, int win) 2271 { 2272 struct pcic_handle *ph = (struct pcic_handle *)pch; 2273 int reg; 2274 2275 if (win >= PCIC_IO_WINS || win < 0) { 2276 panic("pccbb_pcmcia_io_unmap: window out of range"); 2277 } 2278 2279 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2280 switch (win) { 2281 case 0: 2282 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2283 break; 2284 case 1: 2285 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2286 break; 2287 } 2288 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2289 2290 ph->ioalloc &= ~(1 << win); 2291 } 2292 2293 static int 2294 pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 2295 { 2296 u_int8_t stat; 2297 int i; 2298 2299 /* wait an initial 10ms for quick cards */ 2300 stat = Pcic_read(ph, PCIC_IF_STATUS); 2301 if (stat & PCIC_IF_STATUS_READY) 2302 return (0); 2303 pccbb_pcmcia_delay(ph, 10, "pccwr0"); 2304 for (i = 0; i < 50; i++) { 2305 stat = Pcic_read(ph, PCIC_IF_STATUS); 2306 if (stat & PCIC_IF_STATUS_READY) 2307 return (0); 2308 if ((stat & PCIC_IF_STATUS_CARDDETECT_MASK) != 2309 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2310 return (ENXIO); 2311 /* wait .1s (100ms) each iteration now */ 2312 pccbb_pcmcia_delay(ph, 100, "pccwr1"); 2313 } 2314 2315 printf("pccbb_pcmcia_wait_ready: ready never happened, status=%02x\n", stat); 2316 return (EWOULDBLOCK); 2317 } 2318 2319 /* 2320 * Perform long (msec order) delay. timo is in milliseconds. 2321 */ 2322 static void 2323 pccbb_pcmcia_delay(struct pcic_handle *ph, int timo, const char *wmesg) 2324 { 2325 #ifdef DIAGNOSTIC 2326 if (timo <= 0) 2327 panic("pccbb_pcmcia_delay: called with timeout %d", timo); 2328 if (!curlwp) 2329 panic("pccbb_pcmcia_delay: called in interrupt context"); 2330 #if 0 2331 if (!ph->event_thread) 2332 panic("pccbb_pcmcia_delay: no event thread"); 2333 #endif 2334 #endif 2335 DPRINTF(("pccbb_pcmcia_delay: \"%s\" %p, sleep %d ms\n", 2336 wmesg, ph->event_thread, timo)); 2337 tsleep(pccbb_pcmcia_delay, PWAIT, wmesg, roundup(timo * hz, 1000) / 1000); 2338 } 2339 2340 /* 2341 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2342 * 2343 * This function enables the card. All information is stored in 2344 * the first argument, pcmcia_chipset_handle_t. 2345 */ 2346 STATIC void 2347 pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2348 { 2349 struct pcic_handle *ph = (struct pcic_handle *)pch; 2350 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2351 pcireg_t spsr; 2352 int voltage; 2353 int win; 2354 u_int8_t power, intr; 2355 #ifdef DIAGNOSTIC 2356 int reg; 2357 #endif 2358 2359 /* this bit is mostly stolen from pcic_attach_card */ 2360 2361 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2362 2363 /* get card Vcc info */ 2364 spsr = 2365 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2366 CB_SOCKET_STAT); 2367 if (spsr & CB_SOCKET_STAT_5VCARD) { 2368 DPRINTF(("5V card\n")); 2369 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2370 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2371 DPRINTF(("3V card\n")); 2372 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2373 } else { 2374 DPRINTF(("?V card, 0x%x\n", spsr)); /* XXX */ 2375 return; 2376 } 2377 2378 /* disable interrupts; assert RESET */ 2379 intr = Pcic_read(ph, PCIC_INTR); 2380 intr &= PCIC_INTR_ENABLE; 2381 Pcic_write(ph, PCIC_INTR, intr); 2382 2383 /* zero out the address windows */ 2384 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2385 2386 /* power down the socket to reset it, clear the card reset pin */ 2387 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2388 2389 /* power off; assert output enable bit */ 2390 power = PCIC_PWRCTL_OE; 2391 Pcic_write(ph, PCIC_PWRCTL, power); 2392 2393 /* power up the socket */ 2394 if (pccbb_power(sc, voltage) == 0) 2395 return; 2396 2397 /* 2398 * Table 4-18 and figure 4-6 of the PC Card specifiction say: 2399 * Vcc Rising Time (Tpr) = 100ms (handled in pccbb_power() above) 2400 * RESET Width (Th (Hi-z RESET)) = 1ms 2401 * RESET Width (Tw (RESET)) = 10us 2402 * 2403 * some machines require some more time to be settled 2404 * for example old toshiba topic bridges! 2405 * (100ms is added here). 2406 */ 2407 pccbb_pcmcia_delay(ph, 200 + 1, "pccen1"); 2408 2409 /* negate RESET */ 2410 intr |= PCIC_INTR_RESET; 2411 Pcic_write(ph, PCIC_INTR, intr); 2412 2413 /* 2414 * RESET Setup Time (Tsu (RESET)) = 20ms 2415 */ 2416 pccbb_pcmcia_delay(ph, 20, "pccen2"); 2417 2418 #ifdef DIAGNOSTIC 2419 reg = Pcic_read(ph, PCIC_IF_STATUS); 2420 if ((reg & PCIC_IF_STATUS_POWERACTIVE) == 0) 2421 printf("pccbb_pcmcia_socket_enable: no power, status=%x\n", reg); 2422 #endif 2423 2424 /* wait for the chip to finish initializing */ 2425 if (pccbb_pcmcia_wait_ready(ph)) { 2426 #ifdef DIAGNOSTIC 2427 printf("pccbb_pcmcia_socket_enable: never became ready\n"); 2428 #endif 2429 /* XXX return a failure status?? */ 2430 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2431 Pcic_write(ph, PCIC_PWRCTL, 0); 2432 return; 2433 } 2434 2435 /* reinstall all the memory and io mappings */ 2436 for (win = 0; win < PCIC_MEM_WINS; ++win) 2437 if (ph->memalloc & (1 << win)) 2438 pccbb_pcmcia_do_mem_map(ph, win); 2439 for (win = 0; win < PCIC_IO_WINS; ++win) 2440 if (ph->ioalloc & (1 << win)) 2441 pccbb_pcmcia_do_io_map(ph, win); 2442 } 2443 2444 /* 2445 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2446 * 2447 * This function disables the card. All information is stored in 2448 * the first argument, pcmcia_chipset_handle_t. 2449 */ 2450 STATIC void 2451 pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t pch) 2452 { 2453 struct pcic_handle *ph = (struct pcic_handle *)pch; 2454 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2455 u_int8_t intr; 2456 2457 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2458 2459 /* disable interrupts; assert RESET */ 2460 intr = Pcic_read(ph, PCIC_INTR); 2461 intr &= PCIC_INTR_ENABLE; 2462 Pcic_write(ph, PCIC_INTR, intr); 2463 2464 /* zero out the address windows */ 2465 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2466 2467 /* power down the socket to reset it, clear the card reset pin */ 2468 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2469 2470 /* disable socket: negate output enable bit and power off */ 2471 Pcic_write(ph, PCIC_PWRCTL, 0); 2472 2473 /* 2474 * Vcc Falling Time (Tpf) = 300ms 2475 */ 2476 pccbb_pcmcia_delay(ph, 300, "pccwr1"); 2477 } 2478 2479 STATIC void 2480 pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t pch, int type) 2481 { 2482 struct pcic_handle *ph = (struct pcic_handle *)pch; 2483 u_int8_t intr; 2484 2485 /* set the card type */ 2486 2487 intr = Pcic_read(ph, PCIC_INTR); 2488 intr &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_CARDTYPE_MASK); 2489 if (type == PCMCIA_IFTYPE_IO) 2490 intr |= PCIC_INTR_CARDTYPE_IO; 2491 else 2492 intr |= PCIC_INTR_CARDTYPE_MEM; 2493 Pcic_write(ph, PCIC_INTR, intr); 2494 2495 DPRINTF(("%s: pccbb_pcmcia_socket_settype %02x type %s %02x\n", 2496 ph->ph_parent->dv_xname, ph->sock, 2497 ((type == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2498 } 2499 2500 /* 2501 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2502 * 2503 * This function detects whether a card is in the slot or not. 2504 * If a card is inserted, return 1. Otherwise, return 0. 2505 */ 2506 STATIC int 2507 pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch) 2508 { 2509 struct pcic_handle *ph = (struct pcic_handle *)pch; 2510 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2511 2512 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2513 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2514 } 2515 2516 #if 0 2517 STATIC int 2518 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2519 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2520 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2521 #endif 2522 /* 2523 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2524 * bus_size_t size, 2525 * struct pcmcia_mem_handle *pcmhp) 2526 * 2527 * This function only allocates memory region for pccard. This 2528 * function never maps the allocated region to pccard memory area. 2529 * 2530 * XXX: Why the argument of start address is not in? 2531 */ 2532 STATIC int 2533 pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 2534 struct pcmcia_mem_handle *pcmhp) 2535 { 2536 struct pcic_handle *ph = (struct pcic_handle *)pch; 2537 bus_space_handle_t memh; 2538 bus_addr_t addr; 2539 bus_size_t sizepg; 2540 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2541 #if rbus 2542 rbus_tag_t rb; 2543 #endif 2544 2545 /* Check that the card is still there. */ 2546 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2547 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2548 return 1; 2549 2550 /* out of sc->memh, allocate as many pages as necessary */ 2551 2552 /* convert size to PCIC pages */ 2553 /* 2554 * This is not enough; when the requested region is on the page 2555 * boundaries, this may calculate wrong result. 2556 */ 2557 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2558 #if 0 2559 if (sizepg > PCIC_MAX_MEM_PAGES) { 2560 return 1; 2561 } 2562 #endif 2563 2564 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2565 return 1; 2566 } 2567 2568 addr = 0; /* XXX gcc -Wuninitialized */ 2569 2570 #if rbus 2571 rb = sc->sc_rbus_memt; 2572 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2573 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2574 &addr, &memh)) { 2575 return 1; 2576 } 2577 #else 2578 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2579 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2580 0, /* boundary */ 2581 0, /* flags */ 2582 &addr, &memh)) { 2583 return 1; 2584 } 2585 #endif 2586 2587 DPRINTF(("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, " 2588 "realsize 0x%lx\n", (unsigned long)addr, (unsigned long)size, 2589 (unsigned long)sizepg * PCIC_MEM_PAGESIZE)); 2590 2591 pcmhp->memt = sc->sc_memt; 2592 pcmhp->memh = memh; 2593 pcmhp->addr = addr; 2594 pcmhp->size = size; 2595 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2596 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2597 pcmhp->mhandle = 0; 2598 /* No offset??? Funny. */ 2599 2600 return 0; 2601 } 2602 2603 /* 2604 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2605 * struct pcmcia_mem_handle *pcmhp) 2606 * 2607 * This function release the memory space allocated by the function 2608 * pccbb_pcmcia_mem_alloc(). 2609 */ 2610 STATIC void 2611 pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2612 struct pcmcia_mem_handle *pcmhp) 2613 { 2614 #if rbus 2615 struct pcic_handle *ph = (struct pcic_handle *)pch; 2616 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2617 2618 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2619 #else 2620 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2621 #endif 2622 } 2623 2624 /* 2625 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2626 * 2627 * This function release the memory space allocated by the function 2628 * pccbb_pcmcia_mem_alloc(). 2629 */ 2630 STATIC void 2631 pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2632 { 2633 int regbase_win; 2634 bus_addr_t phys_addr; 2635 bus_addr_t phys_end; 2636 2637 #define PCIC_SMM_START_LOW 0 2638 #define PCIC_SMM_START_HIGH 1 2639 #define PCIC_SMM_STOP_LOW 2 2640 #define PCIC_SMM_STOP_HIGH 3 2641 #define PCIC_CMA_LOW 4 2642 #define PCIC_CMA_HIGH 5 2643 2644 u_int8_t start_low, start_high = 0; 2645 u_int8_t stop_low, stop_high; 2646 u_int8_t off_low, off_high; 2647 u_int8_t mem_window; 2648 int reg; 2649 2650 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2651 int mem8 = 2652 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2653 || (kind == PCMCIA_MEM_ATTR); 2654 2655 regbase_win = 0x10 + win * 0x08; 2656 2657 phys_addr = ph->mem[win].addr; 2658 phys_end = phys_addr + ph->mem[win].size; 2659 2660 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2661 (unsigned long)phys_addr, (unsigned long)phys_end, 2662 (unsigned long)ph->mem[win].offset)); 2663 2664 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2665 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2666 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2667 2668 /* bit 19:12 */ 2669 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2670 /* bit 23:20 and bit 7 on */ 2671 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2672 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2673 /* bit 31:24, for 32-bit address */ 2674 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2675 2676 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2677 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2678 2679 if (((struct pccbb_softc *)ph-> 2680 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2681 Pcic_write(ph, 0x40 + win, mem_window); 2682 } 2683 2684 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2685 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2686 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2687 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2688 2689 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2690 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2691 2692 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2693 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2694 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2695 | ((kind == PCMCIA_MEM_ATTR) ? 2696 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2697 2698 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2699 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2700 2701 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2702 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2703 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2704 2705 #if defined(CBB_DEBUG) 2706 { 2707 int r1, r2, r3, r4, r5, r6, r7 = 0; 2708 2709 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2710 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2711 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2712 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2713 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2714 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2715 if (((struct pccbb_softc *)(ph-> 2716 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2717 r7 = Pcic_read(ph, 0x40 + win); 2718 } 2719 2720 printf("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2721 "%02x%02x", win, r1, r2, r3, r4, r5, r6); 2722 if (((struct pccbb_softc *)(ph-> 2723 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2724 printf(" %02x", r7); 2725 } 2726 printf("\n"); 2727 } 2728 #endif 2729 } 2730 2731 /* 2732 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2733 * bus_addr_t card_addr, bus_size_t size, 2734 * struct pcmcia_mem_handle *pcmhp, 2735 * bus_addr_t *offsetp, int *windowp) 2736 * 2737 * This function maps memory space allocated by the function 2738 * pccbb_pcmcia_mem_alloc(). 2739 */ 2740 STATIC int 2741 pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2742 bus_addr_t card_addr, bus_size_t size, struct pcmcia_mem_handle *pcmhp, 2743 bus_addr_t *offsetp, int *windowp) 2744 { 2745 struct pcic_handle *ph = (struct pcic_handle *)pch; 2746 bus_addr_t busaddr; 2747 long card_offset; 2748 int win; 2749 2750 /* Check that the card is still there. */ 2751 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2752 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2753 return 1; 2754 2755 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2756 if ((ph->memalloc & (1 << win)) == 0) { 2757 ph->memalloc |= (1 << win); 2758 break; 2759 } 2760 } 2761 2762 if (win == PCIC_MEM_WINS) { 2763 return 1; 2764 } 2765 2766 *windowp = win; 2767 2768 /* XXX this is pretty gross */ 2769 2770 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2771 panic("pccbb_pcmcia_mem_map memt is bogus"); 2772 } 2773 2774 busaddr = pcmhp->addr; 2775 2776 /* 2777 * compute the address offset to the pcmcia address space for the 2778 * pcic. this is intentionally signed. The masks and shifts below 2779 * will cause TRT to happen in the pcic registers. Deal with making 2780 * sure the address is aligned, and return the alignment offset. 2781 */ 2782 2783 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2784 card_addr -= *offsetp; 2785 2786 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2787 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2788 (u_long) card_addr)); 2789 2790 /* 2791 * include the offset in the size, and decrement size by one, since 2792 * the hw wants start/stop 2793 */ 2794 size += *offsetp - 1; 2795 2796 card_offset = (((long)card_addr) - ((long)busaddr)); 2797 2798 ph->mem[win].addr = busaddr; 2799 ph->mem[win].size = size; 2800 ph->mem[win].offset = card_offset; 2801 ph->mem[win].kind = kind; 2802 2803 pccbb_pcmcia_do_mem_map(ph, win); 2804 2805 return 0; 2806 } 2807 2808 /* 2809 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2810 * int window) 2811 * 2812 * This function unmaps memory space which mapped by the function 2813 * pccbb_pcmcia_mem_map(). 2814 */ 2815 STATIC void 2816 pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, int window) 2817 { 2818 struct pcic_handle *ph = (struct pcic_handle *)pch; 2819 int reg; 2820 2821 if (window >= PCIC_MEM_WINS) { 2822 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2823 } 2824 2825 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2826 reg &= ~(1 << window); 2827 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2828 2829 ph->memalloc &= ~(1 << window); 2830 } 2831 2832 #if defined PCCBB_PCMCIA_POLL 2833 struct pccbb_poll_str { 2834 void *arg; 2835 int (*func)(void *); 2836 int level; 2837 struct pcic_handle *ph; 2838 int count; 2839 int num; 2840 struct callout poll_ch; 2841 }; 2842 2843 static struct pccbb_poll_str pccbb_poll[10]; 2844 static int pccbb_poll_n = 0; 2845 2846 static void pccbb_pcmcia_poll(void *arg); 2847 2848 static void 2849 pccbb_pcmcia_poll(void *arg) 2850 { 2851 struct pccbb_poll_str *poll = arg; 2852 struct pcic_handle *ph = poll->ph; 2853 struct pccbb_softc *sc = ph->sc; 2854 int s; 2855 u_int32_t spsr; /* socket present-state reg */ 2856 2857 callout_reset(&poll->poll_ch, hz * 2, pccbb_pcmcia_poll, arg); 2858 switch (poll->level) { 2859 case IPL_NET: 2860 s = splnet(); 2861 break; 2862 case IPL_BIO: 2863 s = splbio(); 2864 break; 2865 case IPL_TTY: /* fallthrough */ 2866 default: 2867 s = spltty(); 2868 break; 2869 } 2870 2871 spsr = 2872 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2873 CB_SOCKET_STAT); 2874 2875 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2876 if (!(spsr & 0x40)) /* CINT low */ 2877 #else 2878 if (1) 2879 #endif 2880 { 2881 if ((*poll->func) (poll->arg) > 0) { 2882 ++poll->count; 2883 /* printf("intr: reported from poller, 0x%x\n", spsr); */ 2884 #if defined LEVEL2 2885 } else { 2886 printf("intr: miss! 0x%x\n", spsr); 2887 #endif 2888 } 2889 } 2890 splx(s); 2891 } 2892 #endif /* defined CB_PCMCIA_POLL */ 2893 2894 /* 2895 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2896 * struct pcmcia_function *pf, 2897 * int ipl, 2898 * int (*func)(void *), 2899 * void *arg); 2900 * 2901 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2902 */ 2903 STATIC void * 2904 pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2905 struct pcmcia_function *pf, int ipl, int (*func)(void *), void *arg) 2906 { 2907 struct pcic_handle *ph = (struct pcic_handle *)pch; 2908 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2909 2910 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2911 /* what should I do? */ 2912 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2913 DPRINTF(("%s does not provide edge nor pulse " 2914 "interrupt\n", sc->sc_dev.dv_xname)); 2915 return NULL; 2916 } 2917 /* 2918 * XXX Noooooo! The interrupt flag must set properly!! 2919 * dumb pcmcia driver!! 2920 */ 2921 } 2922 2923 return pccbb_intr_establish(sc, 0, ipl, func, arg); 2924 } 2925 2926 /* 2927 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2928 * void *ih) 2929 * 2930 * This function disables PC-Card interrupt. 2931 */ 2932 STATIC void 2933 pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 2934 { 2935 struct pcic_handle *ph = (struct pcic_handle *)pch; 2936 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2937 2938 pccbb_intr_disestablish(sc, ih); 2939 } 2940 2941 #if rbus 2942 /* 2943 * static int 2944 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2945 * bus_addr_t addr, bus_size_t size, 2946 * bus_addr_t mask, bus_size_t align, 2947 * int flags, bus_addr_t *addrp; 2948 * bus_space_handle_t *bshp) 2949 * 2950 * This function allocates a portion of memory or io space for 2951 * clients. This function is called from CardBus card drivers. 2952 */ 2953 static int 2954 pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2955 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 2956 int flags, bus_addr_t *addrp, bus_space_handle_t *bshp) 2957 { 2958 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2959 2960 DPRINTF(("pccbb_rbus_cb_space_alloc: addr 0x%lx, size 0x%lx, " 2961 "mask 0x%lx, align 0x%lx\n", (unsigned long)addr, 2962 (unsigned long)size, (unsigned long)mask, (unsigned long)align)); 2963 2964 if (align == 0) { 2965 align = size; 2966 } 2967 2968 if (rb->rb_bt == sc->sc_memt) { 2969 if (align < 16) { 2970 return 1; 2971 } 2972 /* 2973 * XXX: align more than 0x1000 to avoid overwrapping 2974 * memory windows for two or more devices. 0x1000 2975 * means memory window's granularity. 2976 * 2977 * Two or more devices should be able to share same 2978 * memory window region. However, overrapping memory 2979 * window is not good because some devices, such as 2980 * 3Com 3C575[BC], have a broken address decoder and 2981 * intrude other's memory region. 2982 */ 2983 if (align < 0x1000) { 2984 align = 0x1000; 2985 } 2986 } else if (rb->rb_bt == sc->sc_iot) { 2987 if (align < 4) { 2988 return 1; 2989 } 2990 /* XXX: hack for avoiding ISA image */ 2991 if (mask < 0x0100) { 2992 mask = 0x3ff; 2993 addr = 0x300; 2994 } 2995 2996 } else { 2997 DPRINTF(("pccbb_rbus_cb_space_alloc: Bus space tag 0x%lx is " 2998 "NOT used. io: 0x%lx, mem: 0x%lx\n", 2999 (unsigned long)rb->rb_bt, (unsigned long)sc->sc_iot, 3000 (unsigned long)sc->sc_memt)); 3001 return 1; 3002 /* XXX: panic here? */ 3003 } 3004 3005 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 3006 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 3007 return 1; 3008 } 3009 3010 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 3011 3012 return 0; 3013 } 3014 3015 /* 3016 * static int 3017 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 3018 * bus_space_handle_t *bshp, bus_size_t size); 3019 * 3020 * This function is called from CardBus card drivers. 3021 */ 3022 static int 3023 pccbb_rbus_cb_space_free(cardbus_chipset_tag_t ct, rbus_tag_t rb, 3024 bus_space_handle_t bsh, bus_size_t size) 3025 { 3026 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 3027 bus_space_tag_t bt = rb->rb_bt; 3028 3029 pccbb_close_win(sc, bt, bsh, size); 3030 3031 if (bt == sc->sc_memt) { 3032 } else if (bt == sc->sc_iot) { 3033 } else { 3034 return 1; 3035 /* XXX: panic here? */ 3036 } 3037 3038 return rbus_space_free(rb, bsh, size, NULL); 3039 } 3040 #endif /* rbus */ 3041 3042 #if rbus 3043 3044 static int 3045 pccbb_open_win(struct pccbb_softc *sc, bus_space_tag_t bst, bus_addr_t addr, 3046 bus_size_t size, bus_space_handle_t bsh, int flags) 3047 { 3048 struct pccbb_win_chain_head *head; 3049 bus_addr_t align; 3050 3051 head = &sc->sc_iowindow; 3052 align = 0x04; 3053 if (sc->sc_memt == bst) { 3054 head = &sc->sc_memwindow; 3055 align = 0x1000; 3056 DPRINTF(("using memory window, 0x%lx 0x%lx 0x%lx\n\n", 3057 (unsigned long)sc->sc_iot, (unsigned long)sc->sc_memt, 3058 (unsigned long)bst)); 3059 } 3060 3061 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 3062 printf("%s: pccbb_open_win: %s winlist insert failed\n", 3063 sc->sc_dev.dv_xname, 3064 (head == &sc->sc_memwindow) ? "mem" : "io"); 3065 } 3066 pccbb_winset(align, sc, bst); 3067 3068 return 0; 3069 } 3070 3071 static int 3072 pccbb_close_win(struct pccbb_softc *sc, bus_space_tag_t bst, 3073 bus_space_handle_t bsh, bus_size_t size) 3074 { 3075 struct pccbb_win_chain_head *head; 3076 bus_addr_t align; 3077 3078 head = &sc->sc_iowindow; 3079 align = 0x04; 3080 if (sc->sc_memt == bst) { 3081 head = &sc->sc_memwindow; 3082 align = 0x1000; 3083 } 3084 3085 if (pccbb_winlist_delete(head, bsh, size)) { 3086 printf("%s: pccbb_close_win: %s winlist delete failed\n", 3087 sc->sc_dev.dv_xname, 3088 (head == &sc->sc_memwindow) ? "mem" : "io"); 3089 } 3090 pccbb_winset(align, sc, bst); 3091 3092 return 0; 3093 } 3094 3095 static int 3096 pccbb_winlist_insert(struct pccbb_win_chain_head *head, bus_addr_t start, 3097 bus_size_t size, bus_space_handle_t bsh, int flags) 3098 { 3099 struct pccbb_win_chain *chainp, *elem; 3100 3101 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 3102 M_NOWAIT)) == NULL) 3103 return (1); /* fail */ 3104 3105 elem->wc_start = start; 3106 elem->wc_end = start + (size - 1); 3107 elem->wc_handle = bsh; 3108 elem->wc_flags = flags; 3109 3110 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3111 chainp = TAILQ_NEXT(chainp, wc_list)) { 3112 if (chainp->wc_end < start) 3113 continue; 3114 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 3115 return (0); 3116 } 3117 3118 TAILQ_INSERT_TAIL(head, elem, wc_list); 3119 return (0); 3120 } 3121 3122 static int 3123 pccbb_winlist_delete(struct pccbb_win_chain_head *head, bus_space_handle_t bsh, 3124 bus_size_t size) 3125 { 3126 struct pccbb_win_chain *chainp; 3127 3128 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3129 chainp = TAILQ_NEXT(chainp, wc_list)) { 3130 if (memcmp(&chainp->wc_handle, &bsh, sizeof(bsh))) 3131 continue; 3132 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 3133 printf("pccbb_winlist_delete: window 0x%lx size " 3134 "inconsistent: 0x%lx, 0x%lx\n", 3135 (unsigned long)chainp->wc_start, 3136 (unsigned long)(chainp->wc_end - chainp->wc_start), 3137 (unsigned long)(size - 1)); 3138 return 1; 3139 } 3140 3141 TAILQ_REMOVE(head, chainp, wc_list); 3142 free(chainp, M_DEVBUF); 3143 3144 return 0; 3145 } 3146 3147 return 1; /* fail: no candidate to remove */ 3148 } 3149 3150 static void 3151 pccbb_winset(bus_addr_t align, struct pccbb_softc *sc, bus_space_tag_t bst) 3152 { 3153 pci_chipset_tag_t pc; 3154 pcitag_t tag; 3155 bus_addr_t mask = ~(align - 1); 3156 struct { 3157 cardbusreg_t win_start; 3158 cardbusreg_t win_limit; 3159 int win_flags; 3160 } win[2]; 3161 struct pccbb_win_chain *chainp; 3162 int offs; 3163 3164 win[0].win_start = win[1].win_start = 0xffffffff; 3165 win[0].win_limit = win[1].win_limit = 0; 3166 win[0].win_flags = win[1].win_flags = 0; 3167 3168 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3169 offs = 0x2c; 3170 if (sc->sc_memt == bst) { 3171 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3172 offs = 0x1c; 3173 } 3174 3175 if (chainp != NULL) { 3176 win[0].win_start = chainp->wc_start & mask; 3177 win[0].win_limit = chainp->wc_end & mask; 3178 win[0].win_flags = chainp->wc_flags; 3179 chainp = TAILQ_NEXT(chainp, wc_list); 3180 } 3181 3182 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3183 if (win[1].win_start == 0xffffffff) { 3184 /* window 1 is not used */ 3185 if ((win[0].win_flags == chainp->wc_flags) && 3186 (win[0].win_limit + align >= 3187 (chainp->wc_start & mask))) { 3188 /* concatenate */ 3189 win[0].win_limit = chainp->wc_end & mask; 3190 } else { 3191 /* make new window */ 3192 win[1].win_start = chainp->wc_start & mask; 3193 win[1].win_limit = chainp->wc_end & mask; 3194 win[1].win_flags = chainp->wc_flags; 3195 } 3196 continue; 3197 } 3198 3199 /* Both windows are engaged. */ 3200 if (win[0].win_flags == win[1].win_flags) { 3201 /* same flags */ 3202 if (win[0].win_flags == chainp->wc_flags) { 3203 if (win[1].win_start - (win[0].win_limit + 3204 align) < 3205 (chainp->wc_start & mask) - 3206 ((chainp->wc_end & mask) + align)) { 3207 /* 3208 * merge window 0 and 1, and set win1 3209 * to chainp 3210 */ 3211 win[0].win_limit = win[1].win_limit; 3212 win[1].win_start = 3213 chainp->wc_start & mask; 3214 win[1].win_limit = 3215 chainp->wc_end & mask; 3216 } else { 3217 win[1].win_limit = 3218 chainp->wc_end & mask; 3219 } 3220 } else { 3221 /* different flags */ 3222 3223 /* concatenate win0 and win1 */ 3224 win[0].win_limit = win[1].win_limit; 3225 /* allocate win[1] to new space */ 3226 win[1].win_start = chainp->wc_start & mask; 3227 win[1].win_limit = chainp->wc_end & mask; 3228 win[1].win_flags = chainp->wc_flags; 3229 } 3230 } else { 3231 /* the flags of win[0] and win[1] is different */ 3232 if (win[0].win_flags == chainp->wc_flags) { 3233 win[0].win_limit = chainp->wc_end & mask; 3234 /* 3235 * XXX this creates overlapping windows, so 3236 * what should the poor bridge do if one is 3237 * cachable, and the other is not? 3238 */ 3239 printf("%s: overlapping windows\n", 3240 sc->sc_dev.dv_xname); 3241 } else { 3242 win[1].win_limit = chainp->wc_end & mask; 3243 } 3244 } 3245 } 3246 3247 pc = sc->sc_pc; 3248 tag = sc->sc_tag; 3249 pci_conf_write(pc, tag, offs, win[0].win_start); 3250 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3251 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3252 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3253 DPRINTF(("--pccbb_winset: win0 [0x%lx, 0x%lx), win1 [0x%lx, 0x%lx)\n", 3254 (unsigned long)pci_conf_read(pc, tag, offs), 3255 (unsigned long)pci_conf_read(pc, tag, offs + 4) + align, 3256 (unsigned long)pci_conf_read(pc, tag, offs + 8), 3257 (unsigned long)pci_conf_read(pc, tag, offs + 12) + align)); 3258 3259 if (bst == sc->sc_memt) { 3260 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3261 3262 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 3263 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 3264 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3265 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 3266 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3267 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3268 } 3269 } 3270 3271 #endif /* rbus */ 3272 3273 static void 3274 pccbb_powerhook(int why, void *arg) 3275 { 3276 struct pccbb_softc *sc = arg; 3277 pcireg_t reg; 3278 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3279 bus_space_handle_t base_memh = sc->sc_base_memh; 3280 3281 DPRINTF(("%s: power: why %d\n", sc->sc_dev.dv_xname, why)); 3282 3283 if (why == PWR_SUSPEND || why == PWR_STANDBY) { 3284 DPRINTF(("%s: power: why %d stopping intr\n", 3285 sc->sc_dev.dv_xname, why)); 3286 if (sc->sc_pil_intr_enable) { 3287 (void)pccbbintr_function(sc); 3288 } 3289 sc->sc_pil_intr_enable = 0; 3290 3291 pci_conf_capture(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf); 3292 3293 if (sc->sc_chipset == CB_RX5C47X) 3294 sc->sc_ricoh_misc_ctrl = pci_conf_read(sc->sc_pc, 3295 sc->sc_tag, 3296 RICOH_PCI_MISC_CTRL); 3297 3298 /* ToDo: deactivate or suspend child devices */ 3299 } 3300 3301 if (why == PWR_RESUME) { 3302 if (sc->sc_pwrmgt_offs != 0) { 3303 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, 3304 sc->sc_pwrmgt_offs + PCI_PMCSR); 3305 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 3306 reg & PCI_PMCSR_PME_EN) { 3307 /* powrstate != D0 */ 3308 3309 printf("%s going back to D0 mode\n", 3310 sc->sc_dev.dv_xname); 3311 reg &= ~PCI_PMCSR_STATE_MASK; 3312 reg |= PCI_PMCSR_STATE_D0; 3313 reg &= ~PCI_PMCSR_PME_EN; 3314 pci_conf_write(sc->sc_pc, sc->sc_tag, 3315 sc->sc_pwrmgt_offs + PCI_PMCSR, reg); 3316 3317 pci_conf_write(sc->sc_pc, sc->sc_tag, 3318 PCI_SOCKBASE, sc->sc_sockbase); 3319 pci_conf_write(sc->sc_pc, sc->sc_tag, 3320 PCI_BUSNUM, sc->sc_busnum); 3321 pccbb_chipinit(sc); 3322 /* setup memory and io space window for CB */ 3323 pccbb_winset(0x1000, sc, sc->sc_memt); 3324 pccbb_winset(0x04, sc, sc->sc_iot); 3325 goto norestore; 3326 } 3327 } 3328 3329 norestore: 3330 pci_conf_restore(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf); 3331 if (sc->sc_chipset == CB_RX5C47X) { 3332 pci_conf_write(sc->sc_pc, sc->sc_tag, 3333 RICOH_PCI_MISC_CTRL, sc->sc_ricoh_misc_ctrl); 3334 } 3335 3336 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_SOCKBASE) == 0) 3337 /* BIOS did not recover this register */ 3338 pci_conf_write (sc->sc_pc, sc->sc_tag, 3339 PCI_SOCKBASE, sc->sc_sockbase); 3340 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_BUSNUM) == 0) 3341 /* BIOS did not recover this register */ 3342 pci_conf_write (sc->sc_pc, sc->sc_tag, 3343 PCI_BUSNUM, sc->sc_busnum); 3344 /* CSC Interrupt: Card detect interrupt on */ 3345 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3346 /* Card detect intr is turned on. */ 3347 reg |= CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; 3348 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3349 /* reset interrupt */ 3350 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3351 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3352 3353 /* 3354 * check for card insertion or removal during suspend period. 3355 * XXX: the code can't cope with card swap (remove then 3356 * insert). how can we detect such situation? 3357 */ 3358 (void)pccbbintr(sc); 3359 3360 sc->sc_pil_intr_enable = 1; 3361 DPRINTF(("%s: power: RESUME enabling intr\n", 3362 sc->sc_dev.dv_xname)); 3363 3364 /* ToDo: activate or wakeup child devices */ 3365 } 3366 } 3367
Indexes created Wed Oct 15 03:09:54 GMT 2025