pccbb.c revision 1.137.2.3
1 /* $NetBSD: pccbb.c,v 1.137.2.3 2007/10/26 23:20:19 xtraeme Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: pccbb.c,v 1.137.2.3 2007/10/26 23:20:19 xtraeme Exp $"); 35 36 /* 37 #define CBB_DEBUG 38 #define SHOW_REGS 39 */ 40 41 /* 42 * BROKEN! 43 #define PCCBB_PCMCIA_POLL 44 #define CB_PCMCIA_POLL 45 #define CB_PCMCIA_POLL_ONLY 46 #define LEVEL2 47 */ 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/kernel.h> 52 #include <sys/errno.h> 53 #include <sys/ioctl.h> 54 #include <sys/reboot.h> /* for bootverbose */ 55 #include <sys/syslog.h> 56 #include <sys/device.h> 57 #include <sys/malloc.h> 58 #include <sys/proc.h> 59 60 #include <machine/intr.h> 61 #include <machine/bus.h> 62 63 #include <dev/pci/pcivar.h> 64 #include <dev/pci/pcireg.h> 65 #include <dev/pci/pcidevs.h> 66 67 #include <dev/pci/pccbbreg.h> 68 69 #include <dev/cardbus/cardslotvar.h> 70 71 #include <dev/cardbus/cardbusvar.h> 72 73 #include <dev/pcmcia/pcmciareg.h> 74 #include <dev/pcmcia/pcmciavar.h> 75 76 #include <dev/ic/i82365reg.h> 77 #include <dev/ic/i82365var.h> 78 #include <dev/pci/pccbbvar.h> 79 80 #include "locators.h" 81 82 #ifndef __NetBSD_Version__ 83 struct cfdriver cbb_cd = { 84 NULL, "cbb", DV_DULL 85 }; 86 #endif 87 88 #ifdef CBB_DEBUG 89 #define DPRINTF(x) printf x 90 #define STATIC 91 #else 92 #define DPRINTF(x) 93 #define STATIC static 94 #endif 95 96 /* 97 * delay_ms() is wait in milliseconds. It should be used instead 98 * of delay() if you want to wait more than 1 ms. 99 */ 100 static inline void 101 delay_ms(int millis, void *param) 102 { 103 if (cold) 104 delay(millis * 1000); 105 else 106 tsleep(param, PWAIT, "pccbb", MAX(2, hz * millis / 1000)); 107 } 108 109 int pcicbbmatch(struct device *, struct cfdata *, void *); 110 void pccbbattach(struct device *, struct device *, void *); 111 int pccbbintr(void *); 112 static void pci113x_insert(void *); 113 static int pccbbintr_function(struct pccbb_softc *); 114 115 static int pccbb_detect_card(struct pccbb_softc *); 116 117 static void pccbb_pcmcia_write(struct pcic_handle *, int, u_int8_t); 118 static u_int8_t pccbb_pcmcia_read(struct pcic_handle *, int); 119 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 120 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 121 122 STATIC int cb_reset(struct pccbb_softc *); 123 STATIC int cb_detect_voltage(struct pccbb_softc *); 124 STATIC int cbbprint(void *, const char *); 125 126 static int cb_chipset(u_int32_t, int *); 127 STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *, 128 struct pcmciabus_attach_args *); 129 #if 0 130 STATIC void pccbb_pcmcia_attach_card(struct pcic_handle *); 131 STATIC void pccbb_pcmcia_detach_card(struct pcic_handle *, int); 132 STATIC void pccbb_pcmcia_deactivate_card(struct pcic_handle *); 133 #endif 134 135 STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int); 136 STATIC int pccbb_power(cardbus_chipset_tag_t, int); 137 STATIC int pccbb_cardenable(struct pccbb_softc * sc, int function); 138 #if !rbus 139 static int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 140 static int pccbb_io_close(cardbus_chipset_tag_t, int); 141 static int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 142 static int pccbb_mem_close(cardbus_chipset_tag_t, int); 143 #endif /* !rbus */ 144 static void *pccbb_intr_establish(struct pccbb_softc *, int irq, 145 int level, int (*ih) (void *), void *sc); 146 static void pccbb_intr_disestablish(struct pccbb_softc *, void *ih); 147 148 static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t, int irq, 149 int level, int (*ih) (void *), void *sc); 150 static void pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih); 151 152 static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t, int, int); 153 static void pccbb_free_tag(cardbus_chipset_tag_t, cardbustag_t); 154 static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t, cardbustag_t, int); 155 static void pccbb_conf_write(cardbus_chipset_tag_t, cardbustag_t, int, 156 cardbusreg_t); 157 static void pccbb_chipinit(struct pccbb_softc *); 158 159 STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 160 struct pcmcia_mem_handle *); 161 STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t, 162 struct pcmcia_mem_handle *); 163 STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 164 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *); 165 STATIC void pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t, int); 166 STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 167 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 168 STATIC void pccbb_pcmcia_io_free(pcmcia_chipset_handle_t, 169 struct pcmcia_io_handle *); 170 STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 171 bus_size_t, struct pcmcia_io_handle *, int *); 172 STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t, int); 173 STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t, 174 struct pcmcia_function *, int, int (*)(void *), void *); 175 STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t, void *); 176 STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t); 177 STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t); 178 STATIC void pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t, int); 179 STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch); 180 181 static int pccbb_pcmcia_wait_ready(struct pcic_handle *); 182 static void pccbb_pcmcia_delay(struct pcic_handle *, int, const char *); 183 184 static void pccbb_pcmcia_do_io_map(struct pcic_handle *, int); 185 static void pccbb_pcmcia_do_mem_map(struct pcic_handle *, int); 186 static void pccbb_powerhook(int, void *); 187 188 /* bus-space allocation and deallocation functions */ 189 #if rbus 190 191 static int pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t, rbus_tag_t, 192 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 193 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp); 194 static int pccbb_rbus_cb_space_free(cardbus_chipset_tag_t, rbus_tag_t, 195 bus_space_handle_t, bus_size_t); 196 197 #endif /* rbus */ 198 199 #if rbus 200 201 static int pccbb_open_win(struct pccbb_softc *, bus_space_tag_t, 202 bus_addr_t, bus_size_t, bus_space_handle_t, int flags); 203 static int pccbb_close_win(struct pccbb_softc *, bus_space_tag_t, 204 bus_space_handle_t, bus_size_t); 205 static int pccbb_winlist_insert(struct pccbb_win_chain_head *, bus_addr_t, 206 bus_size_t, bus_space_handle_t, int); 207 static int pccbb_winlist_delete(struct pccbb_win_chain_head *, 208 bus_space_handle_t, bus_size_t); 209 static void pccbb_winset(bus_addr_t align, struct pccbb_softc *, 210 bus_space_tag_t); 211 void pccbb_winlist_show(struct pccbb_win_chain *); 212 213 #endif /* rbus */ 214 215 /* for config_defer */ 216 static void pccbb_pci_callback(struct device *); 217 218 #if defined SHOW_REGS 219 static void cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, 220 bus_space_tag_t memt, bus_space_handle_t memh); 221 #endif 222 223 CFATTACH_DECL(cbb_pci, sizeof(struct pccbb_softc), 224 pcicbbmatch, pccbbattach, NULL, NULL); 225 226 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 227 pccbb_pcmcia_mem_alloc, 228 pccbb_pcmcia_mem_free, 229 pccbb_pcmcia_mem_map, 230 pccbb_pcmcia_mem_unmap, 231 pccbb_pcmcia_io_alloc, 232 pccbb_pcmcia_io_free, 233 pccbb_pcmcia_io_map, 234 pccbb_pcmcia_io_unmap, 235 pccbb_pcmcia_intr_establish, 236 pccbb_pcmcia_intr_disestablish, 237 pccbb_pcmcia_socket_enable, 238 pccbb_pcmcia_socket_disable, 239 pccbb_pcmcia_socket_settype, 240 pccbb_pcmcia_card_detect 241 }; 242 243 #if rbus 244 static struct cardbus_functions pccbb_funcs = { 245 pccbb_rbus_cb_space_alloc, 246 pccbb_rbus_cb_space_free, 247 pccbb_cb_intr_establish, 248 pccbb_cb_intr_disestablish, 249 pccbb_ctrl, 250 pccbb_power, 251 pccbb_make_tag, 252 pccbb_free_tag, 253 pccbb_conf_read, 254 pccbb_conf_write, 255 }; 256 #else 257 static struct cardbus_functions pccbb_funcs = { 258 pccbb_ctrl, 259 pccbb_power, 260 pccbb_mem_open, 261 pccbb_mem_close, 262 pccbb_io_open, 263 pccbb_io_close, 264 pccbb_cb_intr_establish, 265 pccbb_cb_intr_disestablish, 266 pccbb_make_tag, 267 pccbb_conf_read, 268 pccbb_conf_write, 269 }; 270 #endif 271 272 int 273 pcicbbmatch(struct device *parent, struct cfdata *match, void *aux) 274 { 275 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 276 277 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 278 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 279 PCI_INTERFACE(pa->pa_class) == 0) { 280 return 1; 281 } 282 283 return 0; 284 } 285 286 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 287 | ((prod) << PCI_PRODUCT_SHIFT)) 288 289 const struct yenta_chipinfo { 290 pcireg_t yc_id; /* vendor tag | product tag */ 291 int yc_chiptype; 292 int yc_flags; 293 } yc_chipsets[] = { 294 /* Texas Instruments chips */ 295 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 296 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 297 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 298 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 299 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI125X, 300 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 301 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 302 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 303 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 304 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 305 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 306 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 307 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI125X, 308 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 309 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI125X, 310 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 311 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 312 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 313 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 314 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 315 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 316 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 317 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI125X, 318 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 319 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 320 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 321 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1520), CB_TI12XX, 322 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 323 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4410YENTA), CB_TI12XX, 324 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 325 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4520YENTA), CB_TI12XX, 326 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 327 328 /* Ricoh chips */ 329 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 330 PCCBB_PCMCIA_MEM_32}, 331 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 332 PCCBB_PCMCIA_MEM_32}, 333 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 334 PCCBB_PCMCIA_MEM_32}, 335 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 336 PCCBB_PCMCIA_MEM_32}, 337 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 338 PCCBB_PCMCIA_MEM_32}, 339 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 340 PCCBB_PCMCIA_MEM_32}, 341 342 /* Toshiba products */ 343 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 344 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 345 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 346 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 347 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 348 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 349 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 350 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 351 352 /* Cirrus Logic products */ 353 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 354 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 355 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 356 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 357 358 /* sentinel, or Generic chip */ 359 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 360 }; 361 362 static int 363 cb_chipset(u_int32_t pci_id, int *flagp) 364 { 365 const struct yenta_chipinfo *yc; 366 367 /* Loop over except the last default entry. */ 368 for (yc = yc_chipsets; yc < yc_chipsets + 369 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 370 if (pci_id == yc->yc_id) 371 break; 372 373 if (flagp != NULL) 374 *flagp = yc->yc_flags; 375 376 return (yc->yc_chiptype); 377 } 378 379 static void 380 pccbb_shutdown(void *arg) 381 { 382 struct pccbb_softc *sc = arg; 383 pcireg_t command; 384 385 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 386 387 /* 388 * turn off power 389 * 390 * XXX - do not turn off power if chipset is TI 113X because 391 * only TI 1130 with PowerMac 2400 hangs in pccbb_power(). 392 */ 393 if (sc->sc_chipset != CB_TI113X) { 394 pccbb_power((cardbus_chipset_tag_t)sc, 395 CARDBUS_VCC_0V | CARDBUS_VPP_0V); 396 } 397 398 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 399 0); 400 401 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 402 403 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 404 PCI_COMMAND_MASTER_ENABLE); 405 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 406 407 } 408 409 void 410 pccbbattach(struct device *parent, struct device *self, void *aux) 411 { 412 struct pccbb_softc *sc = (void *)self; 413 struct pci_attach_args *pa = aux; 414 pci_chipset_tag_t pc = pa->pa_pc; 415 pcireg_t busreg, reg, sock_base; 416 bus_addr_t sockbase; 417 char devinfo[256]; 418 int flags; 419 int pwrmgt_offs; 420 421 #ifdef __HAVE_PCCBB_ATTACH_HOOK 422 pccbb_attach_hook(parent, self, pa); 423 #endif 424 425 callout_init(&sc->sc_insert_ch); 426 callout_setfunc(&sc->sc_insert_ch, pci113x_insert, sc); 427 428 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 429 430 pci_devinfo(pa->pa_id, 0, 0, devinfo, sizeof(devinfo)); 431 printf(": %s (rev. 0x%02x)", devinfo, PCI_REVISION(pa->pa_class)); 432 DPRINTF((" (chipflags %x)", flags)); 433 printf("\n"); 434 435 TAILQ_INIT(&sc->sc_memwindow); 436 TAILQ_INIT(&sc->sc_iowindow); 437 438 #if rbus 439 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 440 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 441 442 #if 0 443 printf("pa->pa_memt: %08x vs rbus_mem->rb_bt: %08x\n", 444 pa->pa_memt, sc->sc_rbus_memt->rb_bt); 445 #endif 446 #endif /* rbus */ 447 448 sc->sc_flags &= ~CBB_MEMHMAPPED; 449 450 /* power management: set D0 state */ 451 sc->sc_pwrmgt_offs = 0; 452 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, 453 &pwrmgt_offs, 0)) { 454 reg = pci_conf_read(pc, pa->pa_tag, pwrmgt_offs + PCI_PMCSR); 455 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 456 reg & 0x100 /* PCI_PMCSR_PME_EN */) { 457 reg &= ~PCI_PMCSR_STATE_MASK; 458 reg |= PCI_PMCSR_STATE_D0; 459 reg &= ~(0x100 /* PCI_PMCSR_PME_EN */); 460 pci_conf_write(pc, pa->pa_tag, 461 pwrmgt_offs + PCI_PMCSR, reg); 462 } 463 464 sc->sc_pwrmgt_offs = pwrmgt_offs; 465 } 466 467 /* 468 * MAP socket registers and ExCA registers on memory-space 469 * When no valid address is set on socket base registers (on pci 470 * config space), get it not polite way. 471 */ 472 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 473 474 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 475 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 476 /* The address must be valid. */ 477 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 478 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL)) { 479 printf("%s: can't map socket base address 0x%lx\n", 480 sc->sc_dev.dv_xname, (unsigned long)sock_base); 481 /* 482 * I think it's funny: socket base registers must be 483 * mapped on memory space, but ... 484 */ 485 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 486 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 487 NULL)) { 488 printf("%s: can't map socket base address" 489 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 490 (unsigned long)sockbase); 491 /* give up... allocate reg space via rbus. */ 492 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 493 } else 494 sc->sc_flags |= CBB_MEMHMAPPED; 495 } else { 496 DPRINTF(("%s: socket base address 0x%lx\n", 497 sc->sc_dev.dv_xname, (unsigned long)sockbase)); 498 sc->sc_flags |= CBB_MEMHMAPPED; 499 } 500 } 501 502 sc->sc_mem_start = 0; /* XXX */ 503 sc->sc_mem_end = 0xffffffff; /* XXX */ 504 505 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 506 507 /* pccbb_machdep.c end */ 508 509 #if defined CBB_DEBUG 510 { 511 static const char *intrname[] = { "NON", "A", "B", "C", "D" }; 512 printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname, 513 intrname[pa->pa_intrpin], pa->pa_intrline); 514 } 515 #endif 516 517 /* setup softc */ 518 sc->sc_pc = pc; 519 sc->sc_iot = pa->pa_iot; 520 sc->sc_memt = pa->pa_memt; 521 sc->sc_dmat = pa->pa_dmat; 522 sc->sc_tag = pa->pa_tag; 523 sc->sc_function = pa->pa_function; 524 sc->sc_sockbase = sock_base; 525 sc->sc_busnum = busreg; 526 527 memcpy(&sc->sc_pa, pa, sizeof(*pa)); 528 529 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 530 531 shutdownhook_establish(pccbb_shutdown, sc); 532 533 /* Disable legacy register mapping. */ 534 switch (sc->sc_chipset) { 535 case CB_RX5C46X: /* fallthrough */ 536 #if 0 537 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 538 case CB_RX5C47X: 539 #endif 540 /* 541 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 542 * cannot be disabled by substituting 0 into PCI_LEGACY 543 * register. Ricoh CardBus bridges have special bits on Bridge 544 * control reg (addr 0x3e on PCI config space). 545 */ 546 reg = pci_conf_read(pc, pa->pa_tag, PCI_BCR_INTR); 547 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 548 pci_conf_write(pc, pa->pa_tag, PCI_BCR_INTR, reg); 549 break; 550 551 default: 552 /* XXX I don't know proper way to kill legacy I/O. */ 553 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 554 break; 555 } 556 557 config_defer(self, pccbb_pci_callback); 558 } 559 560 561 562 563 /* 564 * static void pccbb_pci_callback(struct device *self) 565 * 566 * The actual attach routine: get memory space for YENTA register 567 * space, setup YENTA register and route interrupt. 568 * 569 * This function should be deferred because this device may obtain 570 * memory space dynamically. This function must avoid obtaining 571 * memory area which has already kept for another device. 572 */ 573 static void 574 pccbb_pci_callback(struct device *self) 575 { 576 struct pccbb_softc *sc = (void *)self; 577 pci_chipset_tag_t pc = sc->sc_pc; 578 pci_intr_handle_t ih; 579 const char *intrstr = NULL; 580 bus_addr_t sockbase; 581 struct cbslot_attach_args cba; 582 struct pcmciabus_attach_args paa; 583 struct cardslot_attach_args caa; 584 struct cardslot_softc *csc; 585 586 if (!(sc->sc_flags & CBB_MEMHMAPPED)) { 587 /* The socket registers aren't mapped correctly. */ 588 #if rbus 589 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 590 (sc->sc_chipset == CB_RX5C47X 591 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 592 0, &sockbase, &sc->sc_base_memh)) { 593 return; 594 } 595 sc->sc_base_memt = sc->sc_memt; 596 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 597 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 598 sc->sc_dev.dv_xname, (unsigned long)sockbase, 599 (unsigned long)pci_conf_read(pc, sc->sc_tag, 600 PCI_SOCKBASE))); 601 #else 602 sc->sc_base_memt = sc->sc_memt; 603 #if !defined CBB_PCI_BASE 604 #define CBB_PCI_BASE 0x20000000 605 #endif 606 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 607 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 608 /* cannot allocate memory space */ 609 return; 610 } 611 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 612 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 613 sc->sc_dev.dv_xname, (unsigned long)sock_base, 614 (unsigned long)pci_conf_read(pc, 615 sc->sc_tag, PCI_SOCKBASE))); 616 sc->sc_sockbase = sockbase; 617 #endif 618 sc->sc_flags |= CBB_MEMHMAPPED; 619 } 620 621 /* bus bridge initialization */ 622 pccbb_chipinit(sc); 623 624 /* clear data structure for child device interrupt handlers */ 625 LIST_INIT(&sc->sc_pil); 626 sc->sc_pil_intr_enable = 1; 627 628 /* Map and establish the interrupt. */ 629 if (pci_intr_map(&sc->sc_pa, &ih)) { 630 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 631 return; 632 } 633 intrstr = pci_intr_string(pc, ih); 634 635 /* 636 * XXX pccbbintr should be called under the priority lower 637 * than any other hard interupts. 638 */ 639 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 640 641 if (sc->sc_ih == NULL) { 642 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 643 if (intrstr != NULL) { 644 printf(" at %s", intrstr); 645 } 646 printf("\n"); 647 return; 648 } 649 650 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 651 powerhook_establish(sc->sc_dev.dv_xname, pccbb_powerhook, sc); 652 653 { 654 u_int32_t sockstat; 655 656 sockstat = bus_space_read_4(sc->sc_base_memt, 657 sc->sc_base_memh, CB_SOCKET_STAT); 658 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 659 sc->sc_flags |= CBB_CARDEXIST; 660 } 661 } 662 663 /* 664 * attach cardbus 665 */ 666 { 667 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 668 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 669 670 /* initialize cbslot_attach */ 671 cba.cba_busname = "cardbus"; 672 cba.cba_iot = sc->sc_iot; 673 cba.cba_memt = sc->sc_memt; 674 cba.cba_dmat = sc->sc_dmat; 675 cba.cba_bus = (busreg >> 8) & 0x0ff; 676 cba.cba_cc = (void *)sc; 677 cba.cba_cf = &pccbb_funcs; 678 cba.cba_intrline = sc->sc_pa.pa_intrline; 679 680 #if rbus 681 cba.cba_rbus_iot = sc->sc_rbus_iot; 682 cba.cba_rbus_memt = sc->sc_rbus_memt; 683 #endif 684 685 cba.cba_cacheline = PCI_CACHELINE(bhlc); 686 cba.cba_lattimer = PCI_CB_LATENCY(busreg); 687 688 if (bootverbose) { 689 printf("%s: cacheline 0x%x lattimer 0x%x\n", 690 sc->sc_dev.dv_xname, cba.cba_cacheline, 691 cba.cba_lattimer); 692 printf("%s: bhlc 0x%x lscp 0x%x\n", 693 sc->sc_dev.dv_xname, bhlc, busreg); 694 } 695 #if defined SHOW_REGS 696 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 697 sc->sc_base_memh); 698 #endif 699 } 700 701 pccbb_pcmcia_attach_setup(sc, &paa); 702 caa.caa_cb_attach = NULL; 703 if (cba.cba_bus == 0) 704 printf("%s: secondary bus number uninitialized; try PCI_BUS_FIXUP\n", sc->sc_dev.dv_xname); 705 else 706 caa.caa_cb_attach = &cba; 707 caa.caa_16_attach = &paa; 708 caa.caa_ph = &sc->sc_pcmcia_h; 709 710 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 711 DPRINTF(("%s: found cardslot\n", __func__)); 712 sc->sc_csc = csc; 713 } 714 715 return; 716 } 717 718 719 720 721 722 /* 723 * static void pccbb_chipinit(struct pccbb_softc *sc) 724 * 725 * This function initialize YENTA chip registers listed below: 726 * 1) PCI command reg, 727 * 2) PCI and CardBus latency timer, 728 * 3) route PCI interrupt, 729 * 4) close all memory and io windows. 730 * 5) turn off bus power. 731 * 6) card detect and power cycle interrupts on. 732 * 7) clear interrupt 733 */ 734 static void 735 pccbb_chipinit(struct pccbb_softc *sc) 736 { 737 pci_chipset_tag_t pc = sc->sc_pc; 738 pcitag_t tag = sc->sc_tag; 739 bus_space_tag_t bmt = sc->sc_base_memt; 740 bus_space_handle_t bmh = sc->sc_base_memh; 741 pcireg_t reg; 742 743 /* 744 * Set PCI command reg. 745 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 746 */ 747 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 748 /* I believe it is harmless. */ 749 reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 750 PCI_COMMAND_MASTER_ENABLE); 751 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg); 752 753 /* 754 * Set CardBus latency timer. 755 */ 756 reg = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 757 if (PCI_CB_LATENCY(reg) < 0x20) { 758 reg &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 759 reg |= (0x20 << PCI_CB_LATENCY_SHIFT); 760 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, reg); 761 } 762 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 763 PCI_CB_LATENCY(reg), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 764 765 /* 766 * Set PCI latency timer. 767 */ 768 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 769 if (PCI_LATTIMER(reg) < 0x10) { 770 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 771 reg |= (0x10 << PCI_LATTIMER_SHIFT); 772 pci_conf_write(pc, tag, PCI_BHLC_REG, reg); 773 } 774 DPRINTF(("PCI latency timer 0x%x (%x)\n", 775 PCI_LATTIMER(reg), pci_conf_read(pc, tag, PCI_BHLC_REG))); 776 777 778 /* Route functional interrupts to PCI. */ 779 reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 780 reg |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 781 reg |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 782 reg |= CB_BCR_RESET_ENABLE; /* assert reset */ 783 pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 784 785 switch (sc->sc_chipset) { 786 case CB_TI113X: 787 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 788 /* This bit is shared, but may read as 0 on some chips, so set 789 it explicitly on both functions. */ 790 reg |= PCI113X_CBCTRL_PCI_IRQ_ENA; 791 /* CSC intr enable */ 792 reg |= PCI113X_CBCTRL_PCI_CSC; 793 /* functional intr prohibit | prohibit ISA routing */ 794 reg &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 795 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 796 break; 797 798 case CB_TI12XX: 799 /* 800 * Some TI 12xx (and [14][45]xx) based pci cards 801 * sometimes have issues with the MFUNC register not 802 * being initialized due to a bad EEPROM on board. 803 * Laptops that this matters on have this register 804 * properly initialized. 805 * 806 * The TI125X parts have a different register. 807 */ 808 reg = pci_conf_read(pc, tag, PCI12XX_MFUNC); 809 if (reg == 0) { 810 reg &= ~PCI12XX_MFUNC_PIN0; 811 reg |= PCI12XX_MFUNC_PIN0_INTA; 812 if ((pci_conf_read(pc, tag, PCI_SYSCTRL) & 813 PCI12XX_SYSCTRL_INTRTIE) == 0) { 814 reg &= ~PCI12XX_MFUNC_PIN1; 815 reg |= PCI12XX_MFUNC_PIN1_INTB; 816 } 817 pci_conf_write(pc, tag, PCI12XX_MFUNC, reg); 818 } 819 /* fallthrough */ 820 821 case CB_TI125X: 822 /* 823 * Disable zoom video. Some machines initialize this 824 * improperly and experience has shown that this helps 825 * prevent strange behavior. 826 */ 827 pci_conf_write(pc, tag, PCI12XX_MMCTRL, 0); 828 829 reg = pci_conf_read(pc, tag, PCI_SYSCTRL); 830 reg |= PCI12XX_SYSCTRL_VCCPROT; 831 pci_conf_write(pc, tag, PCI_SYSCTRL, reg); 832 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 833 reg |= PCI12XX_CBCTRL_CSC; 834 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 835 break; 836 837 case CB_TOPIC95B: 838 reg = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 839 reg |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 840 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, reg); 841 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 842 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 843 sc->sc_dev.dv_xname, reg)); 844 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 845 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 846 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 847 DPRINTF(("0x%x\n", reg)); 848 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 849 break; 850 851 case CB_TOPIC97: 852 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 853 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 854 sc->sc_dev.dv_xname, reg)); 855 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 856 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 857 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 858 reg |= TOPIC97_SLOT_CTRL_PCIINT; 859 reg &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 860 DPRINTF(("0x%x\n", reg)); 861 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 862 /* make sure to assert LV card support bits */ 863 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 864 0x800 + 0x3e, 865 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 866 0x800 + 0x3e) | 0x03); 867 break; 868 } 869 870 /* Close all memory and I/O windows. */ 871 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 872 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 873 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 874 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 875 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 876 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 877 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 878 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 879 880 /* reset 16-bit pcmcia bus */ 881 bus_space_write_1(bmt, bmh, 0x800 + PCIC_INTR, 882 bus_space_read_1(bmt, bmh, 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 883 884 /* turn off power */ 885 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 886 887 /* CSC Interrupt: Card detect and power cycle interrupts on */ 888 reg = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 889 reg |= CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; 890 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, reg); 891 /* reset interrupt */ 892 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 893 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 894 } 895 896 897 898 899 /* 900 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 901 * struct pcmciabus_attach_args *paa) 902 * 903 * This function attaches 16-bit PCcard bus. 904 */ 905 STATIC void 906 pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 907 struct pcmciabus_attach_args *paa) 908 { 909 struct pcic_handle *ph = &sc->sc_pcmcia_h; 910 #if rbus 911 rbus_tag_t rb; 912 #endif 913 914 /* initialize pcmcia part in pccbb_softc */ 915 ph->ph_parent = (struct device *)sc; 916 ph->sock = sc->sc_function; 917 ph->flags = 0; 918 ph->shutdown = 0; 919 ph->ih_irq = sc->sc_pa.pa_intrline; 920 ph->ph_bus_t = sc->sc_base_memt; 921 ph->ph_bus_h = sc->sc_base_memh; 922 ph->ph_read = pccbb_pcmcia_read; 923 ph->ph_write = pccbb_pcmcia_write; 924 sc->sc_pct = &pccbb_pcmcia_funcs; 925 926 /* 927 * We need to do a few things here: 928 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 929 * setting the IRQ numbers to 0. 930 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 931 * routing of CSC interrupts (e.g. card removal) to PCI while in 932 * PCMCIA mode. We just leave this set all the time. 933 * 3) Enable card insertion/removal interrupts in case the chip also 934 * needs that while in PCMCIA mode. 935 * 4) Clear any pending CSC interrupt. 936 */ 937 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE); 938 if (sc->sc_chipset == CB_TI113X) { 939 Pcic_write(ph, PCIC_CSC_INTR, 0); 940 } else { 941 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 942 Pcic_read(ph, PCIC_CSC); 943 } 944 945 /* initialize pcmcia bus attachment */ 946 paa->paa_busname = "pcmcia"; 947 paa->pct = sc->sc_pct; 948 paa->pch = ph; 949 paa->iobase = 0; /* I don't use them */ 950 paa->iosize = 0; 951 #if rbus 952 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 953 paa->iobase = rb->rb_start + rb->rb_offset; 954 paa->iosize = rb->rb_end - rb->rb_start; 955 #endif 956 957 return; 958 } 959 960 #if 0 961 STATIC void 962 pccbb_pcmcia_attach_card(struct pcic_handle *ph) 963 { 964 if (ph->flags & PCIC_FLAG_CARDP) { 965 panic("pccbb_pcmcia_attach_card: already attached"); 966 } 967 968 /* call the MI attach function */ 969 pcmcia_card_attach(ph->pcmcia); 970 971 ph->flags |= PCIC_FLAG_CARDP; 972 } 973 974 STATIC void 975 pccbb_pcmcia_detach_card(struct pcic_handle *ph, int flags) 976 { 977 if (!(ph->flags & PCIC_FLAG_CARDP)) { 978 panic("pccbb_pcmcia_detach_card: already detached"); 979 } 980 981 ph->flags &= ~PCIC_FLAG_CARDP; 982 983 /* call the MI detach function */ 984 pcmcia_card_detach(ph->pcmcia, flags); 985 } 986 #endif 987 988 /* 989 * int pccbbintr(arg) 990 * void *arg; 991 * This routine handles the interrupt from Yenta PCI-CardBus bridge 992 * itself. 993 */ 994 int 995 pccbbintr(void *arg) 996 { 997 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 998 u_int32_t sockevent, sockstate; 999 bus_space_tag_t memt = sc->sc_base_memt; 1000 bus_space_handle_t memh = sc->sc_base_memh; 1001 struct pcic_handle *ph = &sc->sc_pcmcia_h; 1002 1003 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 1004 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 1005 Pcic_read(ph, PCIC_CSC); 1006 1007 if (sockevent == 0) { 1008 /* This intr is not for me: it may be for my child devices. */ 1009 if (sc->sc_pil_intr_enable) { 1010 return pccbbintr_function(sc); 1011 } else { 1012 return 0; 1013 } 1014 } 1015 1016 aprint_debug("%s: enter sockevent %" PRIx32 "\n", __func__, sockevent); 1017 1018 if (sockevent & CB_SOCKET_EVENT_CD) { 1019 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1020 if (0x00 != (sockstate & CB_SOCKET_STAT_CD)) { 1021 /* A card should be removed. */ 1022 if (sc->sc_flags & CBB_CARDEXIST) { 1023 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 1024 sockevent)); 1025 DPRINTF((" card removed, 0x%08x\n", sockstate)); 1026 sc->sc_flags &= ~CBB_CARDEXIST; 1027 if (sc->sc_csc->sc_status & 1028 CARDSLOT_STATUS_CARD_16) { 1029 #if 0 1030 struct pcic_handle *ph = 1031 &sc->sc_pcmcia_h; 1032 1033 pcmcia_card_deactivate(ph->pcmcia); 1034 pccbb_pcmcia_socket_disable(ph); 1035 pccbb_pcmcia_detach_card(ph, 1036 DETACH_FORCE); 1037 #endif 1038 cardslot_event_throw(sc->sc_csc, 1039 CARDSLOT_EVENT_REMOVAL_16); 1040 } else if (sc->sc_csc->sc_status & 1041 CARDSLOT_STATUS_CARD_CB) { 1042 /* Cardbus intr removed */ 1043 cardslot_event_throw(sc->sc_csc, 1044 CARDSLOT_EVENT_REMOVAL_CB); 1045 } 1046 } else if (sc->sc_flags & CBB_INSERTING) { 1047 sc->sc_flags &= ~CBB_INSERTING; 1048 callout_stop(&sc->sc_insert_ch); 1049 } 1050 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 1051 /* 1052 * The pccbbintr may called from powerdown hook when 1053 * the system resumed, to detect the card 1054 * insertion/removal during suspension. 1055 */ 1056 (sc->sc_flags & CBB_CARDEXIST) == 0) { 1057 if (sc->sc_flags & CBB_INSERTING) { 1058 callout_stop(&sc->sc_insert_ch); 1059 } 1060 callout_schedule(&sc->sc_insert_ch, hz / 5); 1061 sc->sc_flags |= CBB_INSERTING; 1062 } 1063 } 1064 1065 if (sockevent & CB_SOCKET_EVENT_POWER) { 1066 DPRINTF(("Powercycling because of socket event\n")); 1067 /* XXX: Does not happen when attaching a 16-bit card */ 1068 sc->sc_pwrcycle++; 1069 wakeup(&sc->sc_pwrcycle); 1070 } 1071 1072 return (1); 1073 } 1074 1075 /* 1076 * static int pccbbintr_function(struct pccbb_softc *sc) 1077 * 1078 * This function calls each interrupt handler registered at the 1079 * bridge. The interrupt handlers are called in registered order. 1080 */ 1081 static int 1082 pccbbintr_function(struct pccbb_softc *sc) 1083 { 1084 int retval = 0, val; 1085 struct pccbb_intrhand_list *pil; 1086 int s, splchanged; 1087 1088 for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1089 pil = LIST_NEXT(pil, pil_next)) { 1090 /* 1091 * XXX priority change. gross. I use if-else 1092 * sentense instead of switch-case sentense because of 1093 * avoiding duplicate case value error. More than one 1094 * IPL_XXX use same value. It depends on 1095 * implimentation. 1096 */ 1097 splchanged = 1; 1098 if (pil->pil_level == IPL_SERIAL) { 1099 s = splserial(); 1100 } else if (pil->pil_level == IPL_HIGH) { 1101 s = splhigh(); 1102 } else if (pil->pil_level == IPL_CLOCK) { 1103 s = splclock(); 1104 } else if (pil->pil_level == IPL_AUDIO) { 1105 s = splaudio(); 1106 } else if (pil->pil_level == IPL_VM) { 1107 s = splvm(); 1108 } else if (pil->pil_level == IPL_TTY) { 1109 s = spltty(); 1110 } else if (pil->pil_level == IPL_SOFTSERIAL) { 1111 s = splsoftserial(); 1112 } else if (pil->pil_level == IPL_NET) { 1113 s = splnet(); 1114 } else { 1115 s = 0; /* XXX: gcc */ 1116 splchanged = 0; 1117 /* XXX: ih lower than IPL_BIO runs w/ IPL_BIO. */ 1118 } 1119 1120 val = (*pil->pil_func)(pil->pil_arg); 1121 1122 if (splchanged != 0) { 1123 splx(s); 1124 } 1125 1126 retval = retval == 1 ? 1 : 1127 retval == 0 ? val : val != 0 ? val : retval; 1128 } 1129 1130 return retval; 1131 } 1132 1133 static void 1134 pci113x_insert(void *arg) 1135 { 1136 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1137 u_int32_t sockevent, sockstate; 1138 1139 if (!(sc->sc_flags & CBB_INSERTING)) { 1140 /* We add a card only under inserting state. */ 1141 return; 1142 } 1143 sc->sc_flags &= ~CBB_INSERTING; 1144 1145 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1146 CB_SOCKET_EVENT); 1147 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1148 CB_SOCKET_STAT); 1149 1150 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1151 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1152 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1153 sc->sc_flags |= CBB_CARDEXIST; 1154 /* call pccard interrupt handler here */ 1155 if (sockstate & CB_SOCKET_STAT_16BIT) { 1156 /* 16-bit card found */ 1157 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1158 cardslot_event_throw(sc->sc_csc, 1159 CARDSLOT_EVENT_INSERTION_16); 1160 } else if (sockstate & CB_SOCKET_STAT_CB) { 1161 /* cardbus card found */ 1162 /* cardbus_attach_card(sc->sc_csc); */ 1163 cardslot_event_throw(sc->sc_csc, 1164 CARDSLOT_EVENT_INSERTION_CB); 1165 } else { 1166 /* who are you? */ 1167 } 1168 } else { 1169 callout_schedule(&sc->sc_insert_ch, hz / 10); 1170 } 1171 } 1172 1173 #define PCCBB_PCMCIA_OFFSET 0x800 1174 static u_int8_t 1175 pccbb_pcmcia_read(struct pcic_handle *ph, int reg) 1176 { 1177 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1178 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1179 1180 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1181 PCCBB_PCMCIA_OFFSET + reg); 1182 } 1183 1184 static void 1185 pccbb_pcmcia_write(struct pcic_handle *ph, int reg, u_int8_t val) 1186 { 1187 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1188 val); 1189 1190 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1191 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1192 } 1193 1194 /* 1195 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1196 */ 1197 STATIC int 1198 pccbb_ctrl(cardbus_chipset_tag_t ct, int command) 1199 { 1200 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1201 1202 switch (command) { 1203 case CARDBUS_CD: 1204 if (2 == pccbb_detect_card(sc)) { 1205 int retval = 0; 1206 int status = cb_detect_voltage(sc); 1207 if (PCCARD_VCC_5V & status) { 1208 retval |= CARDBUS_5V_CARD; 1209 } 1210 if (PCCARD_VCC_3V & status) { 1211 retval |= CARDBUS_3V_CARD; 1212 } 1213 if (PCCARD_VCC_XV & status) { 1214 retval |= CARDBUS_XV_CARD; 1215 } 1216 if (PCCARD_VCC_YV & status) { 1217 retval |= CARDBUS_YV_CARD; 1218 } 1219 return retval; 1220 } else { 1221 return 0; 1222 } 1223 case CARDBUS_RESET: 1224 return cb_reset(sc); 1225 case CARDBUS_IO_ENABLE: /* fallthrough */ 1226 case CARDBUS_IO_DISABLE: /* fallthrough */ 1227 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1228 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1229 case CARDBUS_BM_ENABLE: /* fallthrough */ 1230 case CARDBUS_BM_DISABLE: /* fallthrough */ 1231 /* XXX: I think we don't need to call this function below. */ 1232 return pccbb_cardenable(sc, command); 1233 } 1234 1235 return 0; 1236 } 1237 1238 /* 1239 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1240 * This function returns true when it succeeds and returns false when 1241 * it fails. 1242 */ 1243 STATIC int 1244 pccbb_power(cardbus_chipset_tag_t ct, int command) 1245 { 1246 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1247 u_int32_t status, osock_ctrl, sock_ctrl, reg_ctrl; 1248 bus_space_tag_t memt = sc->sc_base_memt; 1249 bus_space_handle_t memh = sc->sc_base_memh; 1250 int on = 0, pwrcycle, s, times; 1251 struct timeval before, after, diff; 1252 1253 DPRINTF(("pccbb_power: %s and %s [0x%x]\n", 1254 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1255 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1256 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1257 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1258 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1259 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1260 "UNKNOWN", 1261 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1262 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1263 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1264 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1265 "UNKNOWN", command)); 1266 1267 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1268 osock_ctrl = sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1269 1270 switch (command & CARDBUS_VCCMASK) { 1271 case CARDBUS_VCC_UC: 1272 break; 1273 case CARDBUS_VCC_5V: 1274 on++; 1275 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1276 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1277 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1278 } else { 1279 printf("%s: BAD voltage request: no 5 V card\n", 1280 sc->sc_dev.dv_xname); 1281 return 0; 1282 } 1283 break; 1284 case CARDBUS_VCC_3V: 1285 on++; 1286 if (CB_SOCKET_STAT_3VCARD & status) { 1287 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1288 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1289 } else { 1290 printf("%s: BAD voltage request: no 3.3 V card\n", 1291 sc->sc_dev.dv_xname); 1292 return 0; 1293 } 1294 break; 1295 case CARDBUS_VCC_0V: 1296 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1297 break; 1298 default: 1299 return 0; /* power NEVER changed */ 1300 } 1301 1302 switch (command & CARDBUS_VPPMASK) { 1303 case CARDBUS_VPP_UC: 1304 break; 1305 case CARDBUS_VPP_0V: 1306 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1307 break; 1308 case CARDBUS_VPP_VCC: 1309 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1310 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1311 break; 1312 case CARDBUS_VPP_12V: 1313 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1314 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1315 break; 1316 } 1317 1318 pwrcycle = sc->sc_pwrcycle; 1319 aprint_debug("%s: osock_ctrl %#" PRIx32 " sock_ctrl %#" PRIx32 "\n", 1320 device_xname(&sc->sc_dev), osock_ctrl, sock_ctrl); 1321 1322 microtime(&before); 1323 s = splbio(); 1324 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1325 1326 /* 1327 * Wait as long as 200ms for a power-cycle interrupt. If 1328 * interrupts are enabled, but the socket has already 1329 * changed to the desired status, keep waiting for the 1330 * interrupt. "Consuming" the interrupt in this way keeps 1331 * the interrupt from prematurely waking some subsequent 1332 * pccbb_power call. 1333 * 1334 * XXX Not every bridge interrupts on the ->OFF transition. 1335 * XXX That's ok, we will time-out after 200ms. 1336 * 1337 * XXX The power cycle event will never happen when attaching 1338 * XXX a 16-bit card. That's ok, we will time-out after 1339 * XXX 200ms. 1340 */ 1341 for (times = 5; --times >= 0; ) { 1342 if (cold) 1343 DELAY(40 * 1000); 1344 else { 1345 (void)tsleep(&sc->sc_pwrcycle, PWAIT, "pccpwr", 1346 hz / 25); 1347 if (pwrcycle == sc->sc_pwrcycle) 1348 continue; 1349 } 1350 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1351 if ((status & CB_SOCKET_STAT_PWRCYCLE) != 0 && on) 1352 break; 1353 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0 && !on) 1354 break; 1355 } 1356 splx(s); 1357 microtime(&after); 1358 timersub(&after, &before, &diff); 1359 aprint_debug("%s: wait took%s %ld.%06lds\n", sc->sc_dev.dv_xname, 1360 (on && times < 0) ? " too long" : "", diff.tv_sec, diff.tv_usec); 1361 1362 /* 1363 * Ok, wait a bit longer for things to settle. 1364 */ 1365 if (on && sc->sc_chipset == CB_TOPIC95B) 1366 delay_ms(100, sc); 1367 1368 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1369 1370 if (on && sc->sc_chipset != CB_TOPIC95B) { 1371 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0) 1372 printf("%s: power on failed?\n", sc->sc_dev.dv_xname); 1373 } 1374 1375 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1376 printf("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1377 sc->sc_dev.dv_xname, sock_ctrl, status); 1378 printf("%s: disabling socket\n", sc->sc_dev.dv_xname); 1379 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1380 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1381 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1382 status &= ~CB_SOCKET_STAT_BADVCC; 1383 bus_space_write_4(memt, memh, CB_SOCKET_STAT, status); 1384 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1385 CB_SOCKET_STAT)); 1386 return 0; 1387 } 1388 1389 if (sc->sc_chipset == CB_TOPIC97) { 1390 reg_ctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL); 1391 reg_ctrl &= ~TOPIC97_REG_CTRL_TESTMODE; 1392 if ((command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V) 1393 reg_ctrl &= ~TOPIC97_REG_CTRL_CLKRUN_ENA; 1394 else 1395 reg_ctrl |= TOPIC97_REG_CTRL_CLKRUN_ENA; 1396 pci_conf_write(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL, reg_ctrl); 1397 } 1398 1399 return 1; /* power changed correctly */ 1400 } 1401 1402 #if defined CB_PCMCIA_POLL 1403 struct cb_poll_str { 1404 void *arg; 1405 int (*func)(void *); 1406 int level; 1407 pccard_chipset_tag_t ct; 1408 int count; 1409 struct callout poll_ch; 1410 }; 1411 1412 static struct cb_poll_str cb_poll[10]; 1413 static int cb_poll_n = 0; 1414 1415 static void cb_pcmcia_poll(void *arg); 1416 1417 static void 1418 cb_pcmcia_poll(void *arg) 1419 { 1420 struct cb_poll_str *poll = arg; 1421 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1422 struct pccbb_softc *sc = psc->cpc_parent; 1423 int s; 1424 u_int32_t spsr; /* socket present-state reg */ 1425 1426 callout_reset(&poll->poll_ch, hz / 10, cb_pcmcia_poll, poll); 1427 switch (poll->level) { 1428 case IPL_NET: 1429 s = splnet(); 1430 break; 1431 case IPL_BIO: 1432 s = splbio(); 1433 break; 1434 case IPL_TTY: /* fallthrough */ 1435 default: 1436 s = spltty(); 1437 break; 1438 } 1439 1440 spsr = 1441 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1442 CB_SOCKET_STAT); 1443 1444 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1445 if (!(spsr & 0x40)) { /* CINT low */ 1446 #else 1447 if (1) { 1448 #endif 1449 if ((*poll->func) (poll->arg) == 1) { 1450 ++poll->count; 1451 printf("intr: reported from poller, 0x%x\n", spsr); 1452 #if defined LEVEL2 1453 } else { 1454 printf("intr: miss! 0x%x\n", spsr); 1455 #endif 1456 } 1457 } 1458 splx(s); 1459 } 1460 #endif /* defined CB_PCMCIA_POLL */ 1461 1462 /* 1463 * static int pccbb_detect_card(struct pccbb_softc *sc) 1464 * return value: 0 if no card exists. 1465 * 1 if 16-bit card exists. 1466 * 2 if cardbus card exists. 1467 */ 1468 static int 1469 pccbb_detect_card(struct pccbb_softc *sc) 1470 { 1471 bus_space_handle_t base_memh = sc->sc_base_memh; 1472 bus_space_tag_t base_memt = sc->sc_base_memt; 1473 u_int32_t sockstat = 1474 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1475 int retval = 0; 1476 1477 /* CD1 and CD2 asserted */ 1478 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1479 /* card must be present */ 1480 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1481 /* NOTACARD DEASSERTED */ 1482 if (CB_SOCKET_STAT_CB & sockstat) { 1483 /* CardBus mode */ 1484 retval = 2; 1485 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1486 /* 16-bit mode */ 1487 retval = 1; 1488 } 1489 } 1490 } 1491 return retval; 1492 } 1493 1494 /* 1495 * STATIC int cb_reset(struct pccbb_softc *sc) 1496 * This function resets CardBus card. 1497 */ 1498 STATIC int 1499 cb_reset(struct pccbb_softc *sc) 1500 { 1501 /* 1502 * Reset Assert at least 20 ms 1503 * Some machines request longer duration. 1504 */ 1505 int reset_duration = 1506 (sc->sc_chipset == CB_RX5C47X ? 400 : 50); 1507 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1508 1509 /* Reset bit Assert (bit 6 at 0x3E) */ 1510 bcr |= CB_BCR_RESET_ENABLE; 1511 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1512 delay_ms(reset_duration, sc); 1513 1514 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1515 /* Reset bit Deassert (bit 6 at 0x3E) */ 1516 bcr &= ~CB_BCR_RESET_ENABLE; 1517 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1518 delay_ms(reset_duration, sc); 1519 } 1520 /* No card found on the slot. Keep Reset. */ 1521 return 1; 1522 } 1523 1524 /* 1525 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1526 * This function detect card Voltage. 1527 */ 1528 STATIC int 1529 cb_detect_voltage(struct pccbb_softc *sc) 1530 { 1531 u_int32_t psr; /* socket present-state reg */ 1532 bus_space_tag_t iot = sc->sc_base_memt; 1533 bus_space_handle_t ioh = sc->sc_base_memh; 1534 int vol = PCCARD_VCC_UKN; /* set 0 */ 1535 1536 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1537 1538 if (0x400u & psr) { 1539 vol |= PCCARD_VCC_5V; 1540 } 1541 if (0x800u & psr) { 1542 vol |= PCCARD_VCC_3V; 1543 } 1544 1545 return vol; 1546 } 1547 1548 STATIC int 1549 cbbprint(void *aux, const char *pcic) 1550 { 1551 #if 0 1552 struct cbslot_attach_args *cba = aux; 1553 1554 if (cba->cba_slot >= 0) { 1555 aprint_normal(" slot %d", cba->cba_slot); 1556 } 1557 #endif 1558 return UNCONF; 1559 } 1560 1561 /* 1562 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1563 * This function enables and disables the card 1564 */ 1565 STATIC int 1566 pccbb_cardenable(struct pccbb_softc *sc, int function) 1567 { 1568 u_int32_t command = 1569 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1570 1571 DPRINTF(("pccbb_cardenable:")); 1572 switch (function) { 1573 case CARDBUS_IO_ENABLE: 1574 command |= PCI_COMMAND_IO_ENABLE; 1575 break; 1576 case CARDBUS_IO_DISABLE: 1577 command &= ~PCI_COMMAND_IO_ENABLE; 1578 break; 1579 case CARDBUS_MEM_ENABLE: 1580 command |= PCI_COMMAND_MEM_ENABLE; 1581 break; 1582 case CARDBUS_MEM_DISABLE: 1583 command &= ~PCI_COMMAND_MEM_ENABLE; 1584 break; 1585 case CARDBUS_BM_ENABLE: 1586 command |= PCI_COMMAND_MASTER_ENABLE; 1587 break; 1588 case CARDBUS_BM_DISABLE: 1589 command &= ~PCI_COMMAND_MASTER_ENABLE; 1590 break; 1591 default: 1592 return 0; 1593 } 1594 1595 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1596 DPRINTF((" command reg 0x%x\n", command)); 1597 return 1; 1598 } 1599 1600 #if !rbus 1601 static int 1602 pccbb_io_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 1603 { 1604 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1605 int basereg; 1606 int limitreg; 1607 1608 if ((win < 0) || (win > 2)) { 1609 #if defined DIAGNOSTIC 1610 printf("cardbus_io_open: window out of range %d\n", win); 1611 #endif 1612 return 0; 1613 } 1614 1615 basereg = win * 8 + 0x2c; 1616 limitreg = win * 8 + 0x30; 1617 1618 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1619 start, basereg, end, limitreg)); 1620 1621 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1622 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1623 return 1; 1624 } 1625 1626 /* 1627 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1628 */ 1629 static int 1630 pccbb_io_close(cardbus_chipset_tag_t ct, int win) 1631 { 1632 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1633 int basereg; 1634 int limitreg; 1635 1636 if ((win < 0) || (win > 2)) { 1637 #if defined DIAGNOSTIC 1638 printf("cardbus_io_close: window out of range %d\n", win); 1639 #endif 1640 return 0; 1641 } 1642 1643 basereg = win * 8 + 0x2c; 1644 limitreg = win * 8 + 0x30; 1645 1646 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1647 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1648 return 1; 1649 } 1650 1651 static int 1652 pccbb_mem_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 1653 { 1654 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1655 int basereg; 1656 int limitreg; 1657 1658 if ((win < 0) || (win > 2)) { 1659 #if defined DIAGNOSTIC 1660 printf("cardbus_mem_open: window out of range %d\n", win); 1661 #endif 1662 return 0; 1663 } 1664 1665 basereg = win * 8 + 0x1c; 1666 limitreg = win * 8 + 0x20; 1667 1668 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1669 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1670 return 1; 1671 } 1672 1673 static int 1674 pccbb_mem_close(cardbus_chipset_tag_t ct, int win) 1675 { 1676 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1677 int basereg; 1678 int limitreg; 1679 1680 if ((win < 0) || (win > 2)) { 1681 #if defined DIAGNOSTIC 1682 printf("cardbus_mem_close: window out of range %d\n", win); 1683 #endif 1684 return 0; 1685 } 1686 1687 basereg = win * 8 + 0x1c; 1688 limitreg = win * 8 + 0x20; 1689 1690 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1691 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1692 return 1; 1693 } 1694 #endif 1695 1696 /* 1697 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1698 * int irq, 1699 * int level, 1700 * int (* func)(void *), 1701 * void *arg) 1702 * 1703 * This function registers an interrupt handler at the bridge, in 1704 * order not to call the interrupt handlers of child devices when 1705 * a card-deletion interrupt occurs. 1706 * 1707 * The arguments irq and level are not used. 1708 */ 1709 static void * 1710 pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, int irq, int level, 1711 int (*func)(void *), void *arg) 1712 { 1713 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1714 1715 return pccbb_intr_establish(sc, irq, level, func, arg); 1716 } 1717 1718 1719 /* 1720 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1721 * void *ih) 1722 * 1723 * This function removes an interrupt handler pointed by ih. 1724 */ 1725 static void 1726 pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih) 1727 { 1728 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1729 1730 pccbb_intr_disestablish(sc, ih); 1731 } 1732 1733 1734 void 1735 pccbb_intr_route(struct pccbb_softc *sc) 1736 { 1737 pcireg_t bcr, cbctrl; 1738 1739 /* initialize bridge intr routing */ 1740 bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1741 bcr &= ~CB_BCR_INTR_IREQ_ENABLE; 1742 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1743 1744 switch (sc->sc_chipset) { 1745 case CB_TI113X: 1746 cbctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1747 /* functional intr enabled */ 1748 cbctrl |= PCI113X_CBCTRL_PCI_INTR; 1749 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, cbctrl); 1750 break; 1751 default: 1752 break; 1753 } 1754 } 1755 1756 /* 1757 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1758 * int irq, 1759 * int level, 1760 * int (* func)(void *), 1761 * void *arg) 1762 * 1763 * This function registers an interrupt handler at the bridge, in 1764 * order not to call the interrupt handlers of child devices when 1765 * a card-deletion interrupt occurs. 1766 * 1767 * The arguments irq is not used because pccbb selects intr vector. 1768 */ 1769 static void * 1770 pccbb_intr_establish(struct pccbb_softc *sc, int irq, int level, 1771 int (*func)(void *), void *arg) 1772 { 1773 struct pccbb_intrhand_list *pil, *newpil; 1774 1775 DPRINTF(("pccbb_intr_establish start. %p\n", LIST_FIRST(&sc->sc_pil))); 1776 1777 if (LIST_EMPTY(&sc->sc_pil)) { 1778 pccbb_intr_route(sc); 1779 } 1780 1781 /* 1782 * Allocate a room for interrupt handler structure. 1783 */ 1784 if (NULL == (newpil = 1785 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1786 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1787 return NULL; 1788 } 1789 1790 newpil->pil_func = func; 1791 newpil->pil_arg = arg; 1792 newpil->pil_level = level; 1793 1794 if (LIST_EMPTY(&sc->sc_pil)) { 1795 LIST_INSERT_HEAD(&sc->sc_pil, newpil, pil_next); 1796 } else { 1797 for (pil = LIST_FIRST(&sc->sc_pil); 1798 LIST_NEXT(pil, pil_next) != NULL; 1799 pil = LIST_NEXT(pil, pil_next)); 1800 LIST_INSERT_AFTER(pil, newpil, pil_next); 1801 } 1802 1803 DPRINTF(("pccbb_intr_establish add pil. %p\n", 1804 LIST_FIRST(&sc->sc_pil))); 1805 1806 return newpil; 1807 } 1808 1809 /* 1810 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1811 * void *ih) 1812 * 1813 * This function removes an interrupt handler pointed by ih. ih 1814 * should be the value returned by cardbus_intr_establish() or 1815 * NULL. 1816 * 1817 * When ih is NULL, this function will do nothing. 1818 */ 1819 static void 1820 pccbb_intr_disestablish(struct pccbb_softc *sc, void *ih) 1821 { 1822 struct pccbb_intrhand_list *pil; 1823 pcireg_t reg; 1824 1825 DPRINTF(("pccbb_intr_disestablish start. %p\n", 1826 LIST_FIRST(&sc->sc_pil))); 1827 1828 if (ih == NULL) { 1829 /* intr handler is not set */ 1830 DPRINTF(("pccbb_intr_disestablish: no ih\n")); 1831 return; 1832 } 1833 1834 #ifdef DIAGNOSTIC 1835 for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1836 pil = LIST_NEXT(pil, pil_next)) { 1837 DPRINTF(("pccbb_intr_disestablish: pil %p\n", pil)); 1838 if (pil == ih) { 1839 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1840 break; 1841 } 1842 } 1843 if (pil == NULL) { 1844 panic("pccbb_intr_disestablish: %s cannot find pil %p", 1845 sc->sc_dev.dv_xname, ih); 1846 } 1847 #endif 1848 1849 pil = (struct pccbb_intrhand_list *)ih; 1850 LIST_REMOVE(pil, pil_next); 1851 free(pil, M_DEVBUF); 1852 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1853 1854 if (LIST_EMPTY(&sc->sc_pil)) { 1855 /* No interrupt handlers */ 1856 1857 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1858 1859 /* stop routing PCI intr */ 1860 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1861 reg |= CB_BCR_INTR_IREQ_ENABLE; 1862 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1863 1864 switch (sc->sc_chipset) { 1865 case CB_TI113X: 1866 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1867 /* functional intr disabled */ 1868 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1869 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1870 break; 1871 default: 1872 break; 1873 } 1874 } 1875 } 1876 1877 #if defined SHOW_REGS 1878 static void 1879 cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, bus_space_tag_t memt, 1880 bus_space_handle_t memh) 1881 { 1882 int i; 1883 printf("PCI config regs:"); 1884 for (i = 0; i < 0x50; i += 4) { 1885 if (i % 16 == 0) 1886 printf("\n 0x%02x:", i); 1887 printf(" %08x", pci_conf_read(pc, tag, i)); 1888 } 1889 for (i = 0x80; i < 0xb0; i += 4) { 1890 if (i % 16 == 0) 1891 printf("\n 0x%02x:", i); 1892 printf(" %08x", pci_conf_read(pc, tag, i)); 1893 } 1894 1895 if (memh == 0) { 1896 printf("\n"); 1897 return; 1898 } 1899 1900 printf("\nsocket regs:"); 1901 for (i = 0; i <= 0x10; i += 0x04) 1902 printf(" %08x", bus_space_read_4(memt, memh, i)); 1903 printf("\nExCA regs:"); 1904 for (i = 0; i < 0x08; ++i) 1905 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1906 printf("\n"); 1907 return; 1908 } 1909 #endif 1910 1911 /* 1912 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1913 * int busno, int function) 1914 * This is the function to make a tag to access config space of 1915 * a CardBus Card. It works same as pci_conf_read. 1916 */ 1917 static cardbustag_t 1918 pccbb_make_tag(cardbus_chipset_tag_t cc, int busno, int function) 1919 { 1920 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1921 1922 return pci_make_tag(sc->sc_pc, busno, 0, function); 1923 } 1924 1925 static void 1926 pccbb_free_tag(cardbus_chipset_tag_t cc, cardbustag_t tag) 1927 { 1928 } 1929 1930 /* 1931 * pccbb_conf_read 1932 * 1933 * This is the function to read the config space of a CardBus card. 1934 * It works the same as pci_conf_read(9). 1935 */ 1936 static cardbusreg_t 1937 pccbb_conf_read(cardbus_chipset_tag_t cc, cardbustag_t tag, int offset) 1938 { 1939 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1940 1941 return pci_conf_read(sc->sc_pc, tag, offset); 1942 } 1943 1944 /* 1945 * pccbb_conf_write 1946 * 1947 * This is the function to write the config space of a CardBus 1948 * card. It works the same as pci_conf_write(9). 1949 */ 1950 static void 1951 pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, int reg, 1952 cardbusreg_t val) 1953 { 1954 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1955 1956 pci_conf_write(sc->sc_pc, tag, reg, val); 1957 } 1958 1959 #if 0 1960 STATIC int 1961 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1962 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 1963 int speed, int flags, 1964 bus_space_handle_t * iohp) 1965 #endif 1966 /* 1967 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1968 * bus_addr_t start, bus_size_t size, 1969 * bus_size_t align, 1970 * struct pcmcia_io_handle *pcihp 1971 * 1972 * This function only allocates I/O region for pccard. This function 1973 * never maps the allocated region to pccard I/O area. 1974 * 1975 * XXX: The interface of this function is not very good, I believe. 1976 */ 1977 STATIC int 1978 pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, 1979 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 1980 { 1981 struct pcic_handle *ph = (struct pcic_handle *)pch; 1982 bus_addr_t ioaddr; 1983 int flags = 0; 1984 bus_space_tag_t iot; 1985 bus_space_handle_t ioh; 1986 bus_addr_t mask; 1987 #if rbus 1988 rbus_tag_t rb; 1989 #endif 1990 if (align == 0) { 1991 align = size; /* XXX: funny??? */ 1992 } 1993 1994 if (start != 0) { 1995 /* XXX: assume all card decode lower 10 bits by its hardware */ 1996 mask = 0x3ff; 1997 /* enforce to use only masked address */ 1998 start &= mask; 1999 } else { 2000 /* 2001 * calculate mask: 2002 * 1. get the most significant bit of size (call it msb). 2003 * 2. compare msb with the value of size. 2004 * 3. if size is larger, shift msb left once. 2005 * 4. obtain mask value to decrement msb. 2006 */ 2007 bus_size_t size_tmp = size; 2008 int shifts = 0; 2009 2010 mask = 1; 2011 while (size_tmp) { 2012 ++shifts; 2013 size_tmp >>= 1; 2014 } 2015 mask = (1 << shifts); 2016 if (mask < size) { 2017 mask <<= 1; 2018 } 2019 --mask; 2020 } 2021 2022 /* 2023 * Allocate some arbitrary I/O space. 2024 */ 2025 2026 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 2027 2028 #if rbus 2029 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 2030 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 2031 return 1; 2032 } 2033 DPRINTF(("pccbb_pcmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2034 (u_long) ioaddr, (u_long) size)); 2035 #else 2036 if (start) { 2037 ioaddr = start; 2038 if (bus_space_map(iot, start, size, 0, &ioh)) { 2039 return 1; 2040 } 2041 DPRINTF(("pccbb_pcmcia_io_alloc map port 0x%lx+0x%lx\n", 2042 (u_long) ioaddr, (u_long) size)); 2043 } else { 2044 flags |= PCMCIA_IO_ALLOCATED; 2045 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 2046 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 2047 size, align, 0, 0, &ioaddr, &ioh)) { 2048 /* No room be able to be get. */ 2049 return 1; 2050 } 2051 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2052 (u_long) ioaddr, (u_long) size)); 2053 } 2054 #endif 2055 2056 pcihp->iot = iot; 2057 pcihp->ioh = ioh; 2058 pcihp->addr = ioaddr; 2059 pcihp->size = size; 2060 pcihp->flags = flags; 2061 2062 return 0; 2063 } 2064 2065 /* 2066 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2067 * struct pcmcia_io_handle *pcihp) 2068 * 2069 * This function only frees I/O region for pccard. 2070 * 2071 * XXX: The interface of this function is not very good, I believe. 2072 */ 2073 void 2074 pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2075 struct pcmcia_io_handle *pcihp) 2076 { 2077 #if !rbus 2078 bus_space_tag_t iot = pcihp->iot; 2079 #endif 2080 bus_space_handle_t ioh = pcihp->ioh; 2081 bus_size_t size = pcihp->size; 2082 2083 #if rbus 2084 struct pccbb_softc *sc = 2085 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 2086 rbus_tag_t rb = sc->sc_rbus_iot; 2087 2088 rbus_space_free(rb, ioh, size, NULL); 2089 #else 2090 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 2091 bus_space_free(iot, ioh, size); 2092 else 2093 bus_space_unmap(iot, ioh, size); 2094 #endif 2095 } 2096 2097 /* 2098 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 2099 * bus_addr_t offset, bus_size_t size, 2100 * struct pcmcia_io_handle *pcihp, 2101 * int *windowp) 2102 * 2103 * This function maps the allocated I/O region to pccard. This function 2104 * never allocates any I/O region for pccard I/O area. I don't 2105 * understand why the original authors of pcmciabus separated alloc and 2106 * map. I believe the two must be unite. 2107 * 2108 * XXX: no wait timing control? 2109 */ 2110 int 2111 pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, bus_addr_t offset, 2112 bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp) 2113 { 2114 struct pcic_handle *ph = (struct pcic_handle *)pch; 2115 bus_addr_t ioaddr = pcihp->addr + offset; 2116 int i, win; 2117 #if defined CBB_DEBUG 2118 static const char *width_names[] = { "dynamic", "io8", "io16" }; 2119 #endif 2120 2121 /* Sanity check I/O handle. */ 2122 2123 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 2124 panic("pccbb_pcmcia_io_map iot is bogus"); 2125 } 2126 2127 /* XXX Sanity check offset/size. */ 2128 2129 win = -1; 2130 for (i = 0; i < PCIC_IO_WINS; i++) { 2131 if ((ph->ioalloc & (1 << i)) == 0) { 2132 win = i; 2133 ph->ioalloc |= (1 << i); 2134 break; 2135 } 2136 } 2137 2138 if (win == -1) { 2139 return 1; 2140 } 2141 2142 *windowp = win; 2143 2144 /* XXX this is pretty gross */ 2145 2146 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2147 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2148 2149 /* XXX wtf is this doing here? */ 2150 2151 #if 0 2152 printf(" port 0x%lx", (u_long) ioaddr); 2153 if (size > 1) { 2154 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2155 } 2156 #endif 2157 2158 ph->io[win].addr = ioaddr; 2159 ph->io[win].size = size; 2160 ph->io[win].width = width; 2161 2162 /* actual dirty register-value changing in the function below. */ 2163 pccbb_pcmcia_do_io_map(ph, win); 2164 2165 return 0; 2166 } 2167 2168 /* 2169 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2170 * 2171 * This function changes register-value to map I/O region for pccard. 2172 */ 2173 static void 2174 pccbb_pcmcia_do_io_map(struct pcic_handle *ph, int win) 2175 { 2176 static u_int8_t pcic_iowidth[3] = { 2177 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2178 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2179 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2180 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2181 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2182 }; 2183 2184 #define PCIC_SIA_START_LOW 0 2185 #define PCIC_SIA_START_HIGH 1 2186 #define PCIC_SIA_STOP_LOW 2 2187 #define PCIC_SIA_STOP_HIGH 3 2188 2189 int regbase_win = 0x8 + win * 0x04; 2190 u_int8_t ioctl, enable; 2191 2192 DPRINTF(("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx " 2193 "width %d\n", win, (unsigned long)ph->io[win].addr, 2194 (unsigned long)ph->io[win].size, ph->io[win].width * 8)); 2195 2196 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2197 ph->io[win].addr & 0xff); 2198 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2199 (ph->io[win].addr >> 8) & 0xff); 2200 2201 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2202 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2203 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2204 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2205 2206 ioctl = Pcic_read(ph, PCIC_IOCTL); 2207 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2208 switch (win) { 2209 case 0: 2210 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2211 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2212 PCIC_IOCTL_IO0_DATASIZE_MASK); 2213 ioctl |= pcic_iowidth[ph->io[win].width]; 2214 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2215 break; 2216 case 1: 2217 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2218 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2219 PCIC_IOCTL_IO1_DATASIZE_MASK); 2220 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2221 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2222 break; 2223 } 2224 Pcic_write(ph, PCIC_IOCTL, ioctl); 2225 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2226 #if defined(CBB_DEBUG) 2227 { 2228 u_int8_t start_low = 2229 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2230 u_int8_t start_high = 2231 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2232 u_int8_t stop_low = 2233 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2234 u_int8_t stop_high = 2235 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2236 printf("pccbb_pcmcia_do_io_map start %02x %02x, " 2237 "stop %02x %02x, ioctl %02x enable %02x\n", 2238 start_low, start_high, stop_low, stop_high, ioctl, enable); 2239 } 2240 #endif 2241 } 2242 2243 /* 2244 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2245 * 2246 * This function unmaps I/O region. No return value. 2247 */ 2248 STATIC void 2249 pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t pch, int win) 2250 { 2251 struct pcic_handle *ph = (struct pcic_handle *)pch; 2252 int reg; 2253 2254 if (win >= PCIC_IO_WINS || win < 0) { 2255 panic("pccbb_pcmcia_io_unmap: window out of range"); 2256 } 2257 2258 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2259 switch (win) { 2260 case 0: 2261 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2262 break; 2263 case 1: 2264 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2265 break; 2266 } 2267 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2268 2269 ph->ioalloc &= ~(1 << win); 2270 } 2271 2272 static int 2273 pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 2274 { 2275 u_int8_t stat; 2276 int i; 2277 2278 /* wait an initial 10ms for quick cards */ 2279 stat = Pcic_read(ph, PCIC_IF_STATUS); 2280 if (stat & PCIC_IF_STATUS_READY) 2281 return (0); 2282 pccbb_pcmcia_delay(ph, 10, "pccwr0"); 2283 for (i = 0; i < 50; i++) { 2284 stat = Pcic_read(ph, PCIC_IF_STATUS); 2285 if (stat & PCIC_IF_STATUS_READY) 2286 return (0); 2287 if ((stat & PCIC_IF_STATUS_CARDDETECT_MASK) != 2288 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2289 return (ENXIO); 2290 /* wait .1s (100ms) each iteration now */ 2291 pccbb_pcmcia_delay(ph, 100, "pccwr1"); 2292 } 2293 2294 printf("pccbb_pcmcia_wait_ready: ready never happened, status=%02x\n", stat); 2295 return (EWOULDBLOCK); 2296 } 2297 2298 /* 2299 * Perform long (msec order) delay. timo is in milliseconds. 2300 */ 2301 static void 2302 pccbb_pcmcia_delay(struct pcic_handle *ph, int timo, const char *wmesg) 2303 { 2304 #ifdef DIAGNOSTIC 2305 if (timo <= 0) 2306 panic("pccbb_pcmcia_delay: called with timeout %d", timo); 2307 if (!curlwp) 2308 panic("pccbb_pcmcia_delay: called in interrupt context"); 2309 #if 0 2310 if (!ph->event_thread) 2311 panic("pccbb_pcmcia_delay: no event thread"); 2312 #endif 2313 #endif 2314 DPRINTF(("pccbb_pcmcia_delay: \"%s\" %p, sleep %d ms\n", 2315 wmesg, ph->event_thread, timo)); 2316 tsleep(pccbb_pcmcia_delay, PWAIT, wmesg, roundup(timo * hz, 1000) / 1000); 2317 } 2318 2319 /* 2320 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2321 * 2322 * This function enables the card. All information is stored in 2323 * the first argument, pcmcia_chipset_handle_t. 2324 */ 2325 STATIC void 2326 pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2327 { 2328 struct pcic_handle *ph = (struct pcic_handle *)pch; 2329 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2330 pcireg_t spsr; 2331 int voltage; 2332 int win; 2333 u_int8_t power, intr; 2334 #ifdef DIAGNOSTIC 2335 int reg; 2336 #endif 2337 2338 /* this bit is mostly stolen from pcic_attach_card */ 2339 2340 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2341 2342 /* get card Vcc info */ 2343 spsr = 2344 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2345 CB_SOCKET_STAT); 2346 if (spsr & CB_SOCKET_STAT_5VCARD) { 2347 DPRINTF(("5V card\n")); 2348 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2349 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2350 DPRINTF(("3V card\n")); 2351 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2352 } else { 2353 DPRINTF(("?V card, 0x%x\n", spsr)); /* XXX */ 2354 return; 2355 } 2356 2357 /* disable interrupts; assert RESET */ 2358 intr = Pcic_read(ph, PCIC_INTR); 2359 intr &= PCIC_INTR_ENABLE; 2360 Pcic_write(ph, PCIC_INTR, intr); 2361 2362 /* zero out the address windows */ 2363 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2364 2365 /* power down the socket to reset it, clear the card reset pin */ 2366 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2367 2368 /* power off; assert output enable bit */ 2369 power = PCIC_PWRCTL_OE; 2370 Pcic_write(ph, PCIC_PWRCTL, power); 2371 2372 /* power up the socket */ 2373 if (pccbb_power(sc, voltage) == 0) 2374 return; 2375 2376 /* 2377 * Table 4-18 and figure 4-6 of the PC Card specifiction say: 2378 * Vcc Rising Time (Tpr) = 100ms (handled in pccbb_power() above) 2379 * RESET Width (Th (Hi-z RESET)) = 1ms 2380 * RESET Width (Tw (RESET)) = 10us 2381 * 2382 * some machines require some more time to be settled 2383 * for example old toshiba topic bridges! 2384 * (100ms is added here). 2385 */ 2386 pccbb_pcmcia_delay(ph, 200 + 1, "pccen1"); 2387 2388 /* negate RESET */ 2389 intr |= PCIC_INTR_RESET; 2390 Pcic_write(ph, PCIC_INTR, intr); 2391 2392 /* 2393 * RESET Setup Time (Tsu (RESET)) = 20ms 2394 */ 2395 pccbb_pcmcia_delay(ph, 20, "pccen2"); 2396 2397 #ifdef DIAGNOSTIC 2398 reg = Pcic_read(ph, PCIC_IF_STATUS); 2399 if ((reg & PCIC_IF_STATUS_POWERACTIVE) == 0) 2400 printf("pccbb_pcmcia_socket_enable: no power, status=%x\n", reg); 2401 #endif 2402 2403 /* wait for the chip to finish initializing */ 2404 if (pccbb_pcmcia_wait_ready(ph)) { 2405 #ifdef DIAGNOSTIC 2406 printf("pccbb_pcmcia_socket_enable: never became ready\n"); 2407 #endif 2408 /* XXX return a failure status?? */ 2409 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2410 Pcic_write(ph, PCIC_PWRCTL, 0); 2411 return; 2412 } 2413 2414 /* reinstall all the memory and io mappings */ 2415 for (win = 0; win < PCIC_MEM_WINS; ++win) 2416 if (ph->memalloc & (1 << win)) 2417 pccbb_pcmcia_do_mem_map(ph, win); 2418 for (win = 0; win < PCIC_IO_WINS; ++win) 2419 if (ph->ioalloc & (1 << win)) 2420 pccbb_pcmcia_do_io_map(ph, win); 2421 } 2422 2423 /* 2424 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2425 * 2426 * This function disables the card. All information is stored in 2427 * the first argument, pcmcia_chipset_handle_t. 2428 */ 2429 STATIC void 2430 pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t pch) 2431 { 2432 struct pcic_handle *ph = (struct pcic_handle *)pch; 2433 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2434 u_int8_t intr; 2435 2436 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2437 2438 /* disable interrupts; assert RESET */ 2439 intr = Pcic_read(ph, PCIC_INTR); 2440 intr &= PCIC_INTR_ENABLE; 2441 Pcic_write(ph, PCIC_INTR, intr); 2442 2443 /* zero out the address windows */ 2444 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2445 2446 /* power down the socket to reset it, clear the card reset pin */ 2447 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2448 2449 /* disable socket: negate output enable bit and power off */ 2450 Pcic_write(ph, PCIC_PWRCTL, 0); 2451 2452 /* 2453 * Vcc Falling Time (Tpf) = 300ms 2454 */ 2455 pccbb_pcmcia_delay(ph, 300, "pccwr1"); 2456 } 2457 2458 STATIC void 2459 pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t pch, int type) 2460 { 2461 struct pcic_handle *ph = (struct pcic_handle *)pch; 2462 u_int8_t intr; 2463 2464 /* set the card type */ 2465 2466 intr = Pcic_read(ph, PCIC_INTR); 2467 intr &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_CARDTYPE_MASK); 2468 if (type == PCMCIA_IFTYPE_IO) 2469 intr |= PCIC_INTR_CARDTYPE_IO; 2470 else 2471 intr |= PCIC_INTR_CARDTYPE_MEM; 2472 Pcic_write(ph, PCIC_INTR, intr); 2473 2474 DPRINTF(("%s: pccbb_pcmcia_socket_settype %02x type %s %02x\n", 2475 ph->ph_parent->dv_xname, ph->sock, 2476 ((type == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2477 } 2478 2479 /* 2480 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2481 * 2482 * This function detects whether a card is in the slot or not. 2483 * If a card is inserted, return 1. Otherwise, return 0. 2484 */ 2485 STATIC int 2486 pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch) 2487 { 2488 struct pcic_handle *ph = (struct pcic_handle *)pch; 2489 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2490 2491 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2492 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2493 } 2494 2495 #if 0 2496 STATIC int 2497 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2498 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2499 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2500 #endif 2501 /* 2502 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2503 * bus_size_t size, 2504 * struct pcmcia_mem_handle *pcmhp) 2505 * 2506 * This function only allocates memory region for pccard. This 2507 * function never maps the allocated region to pccard memory area. 2508 * 2509 * XXX: Why the argument of start address is not in? 2510 */ 2511 STATIC int 2512 pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 2513 struct pcmcia_mem_handle *pcmhp) 2514 { 2515 struct pcic_handle *ph = (struct pcic_handle *)pch; 2516 bus_space_handle_t memh; 2517 bus_addr_t addr; 2518 bus_size_t sizepg; 2519 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2520 #if rbus 2521 rbus_tag_t rb; 2522 #endif 2523 2524 /* Check that the card is still there. */ 2525 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2526 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2527 return 1; 2528 2529 /* out of sc->memh, allocate as many pages as necessary */ 2530 2531 /* convert size to PCIC pages */ 2532 /* 2533 * This is not enough; when the requested region is on the page 2534 * boundaries, this may calculate wrong result. 2535 */ 2536 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2537 #if 0 2538 if (sizepg > PCIC_MAX_MEM_PAGES) { 2539 return 1; 2540 } 2541 #endif 2542 2543 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2544 return 1; 2545 } 2546 2547 addr = 0; /* XXX gcc -Wuninitialized */ 2548 2549 #if rbus 2550 rb = sc->sc_rbus_memt; 2551 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2552 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2553 &addr, &memh)) { 2554 return 1; 2555 } 2556 #else 2557 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2558 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2559 0, /* boundary */ 2560 0, /* flags */ 2561 &addr, &memh)) { 2562 return 1; 2563 } 2564 #endif 2565 2566 DPRINTF(("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, " 2567 "realsize 0x%lx\n", (unsigned long)addr, (unsigned long)size, 2568 (unsigned long)sizepg * PCIC_MEM_PAGESIZE)); 2569 2570 pcmhp->memt = sc->sc_memt; 2571 pcmhp->memh = memh; 2572 pcmhp->addr = addr; 2573 pcmhp->size = size; 2574 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2575 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2576 pcmhp->mhandle = 0; 2577 /* No offset??? Funny. */ 2578 2579 return 0; 2580 } 2581 2582 /* 2583 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2584 * struct pcmcia_mem_handle *pcmhp) 2585 * 2586 * This function release the memory space allocated by the function 2587 * pccbb_pcmcia_mem_alloc(). 2588 */ 2589 STATIC void 2590 pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2591 struct pcmcia_mem_handle *pcmhp) 2592 { 2593 #if rbus 2594 struct pcic_handle *ph = (struct pcic_handle *)pch; 2595 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2596 2597 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2598 #else 2599 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2600 #endif 2601 } 2602 2603 /* 2604 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2605 * 2606 * This function release the memory space allocated by the function 2607 * pccbb_pcmcia_mem_alloc(). 2608 */ 2609 STATIC void 2610 pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2611 { 2612 int regbase_win; 2613 bus_addr_t phys_addr; 2614 bus_addr_t phys_end; 2615 2616 #define PCIC_SMM_START_LOW 0 2617 #define PCIC_SMM_START_HIGH 1 2618 #define PCIC_SMM_STOP_LOW 2 2619 #define PCIC_SMM_STOP_HIGH 3 2620 #define PCIC_CMA_LOW 4 2621 #define PCIC_CMA_HIGH 5 2622 2623 u_int8_t start_low, start_high = 0; 2624 u_int8_t stop_low, stop_high; 2625 u_int8_t off_low, off_high; 2626 u_int8_t mem_window; 2627 int reg; 2628 2629 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2630 int mem8 = 2631 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2632 || (kind == PCMCIA_MEM_ATTR); 2633 2634 regbase_win = 0x10 + win * 0x08; 2635 2636 phys_addr = ph->mem[win].addr; 2637 phys_end = phys_addr + ph->mem[win].size; 2638 2639 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2640 (unsigned long)phys_addr, (unsigned long)phys_end, 2641 (unsigned long)ph->mem[win].offset)); 2642 2643 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2644 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2645 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2646 2647 /* bit 19:12 */ 2648 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2649 /* bit 23:20 and bit 7 on */ 2650 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2651 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2652 /* bit 31:24, for 32-bit address */ 2653 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2654 2655 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2656 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2657 2658 if (((struct pccbb_softc *)ph-> 2659 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2660 Pcic_write(ph, 0x40 + win, mem_window); 2661 } 2662 2663 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2664 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2665 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2666 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2667 2668 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2669 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2670 2671 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2672 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2673 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2674 | ((kind == PCMCIA_MEM_ATTR) ? 2675 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2676 2677 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2678 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2679 2680 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2681 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2682 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2683 2684 #if defined(CBB_DEBUG) 2685 { 2686 int r1, r2, r3, r4, r5, r6, r7 = 0; 2687 2688 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2689 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2690 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2691 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2692 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2693 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2694 if (((struct pccbb_softc *)(ph-> 2695 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2696 r7 = Pcic_read(ph, 0x40 + win); 2697 } 2698 2699 printf("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2700 "%02x%02x", win, r1, r2, r3, r4, r5, r6); 2701 if (((struct pccbb_softc *)(ph-> 2702 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2703 printf(" %02x", r7); 2704 } 2705 printf("\n"); 2706 } 2707 #endif 2708 } 2709 2710 /* 2711 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2712 * bus_addr_t card_addr, bus_size_t size, 2713 * struct pcmcia_mem_handle *pcmhp, 2714 * bus_addr_t *offsetp, int *windowp) 2715 * 2716 * This function maps memory space allocated by the function 2717 * pccbb_pcmcia_mem_alloc(). 2718 */ 2719 STATIC int 2720 pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2721 bus_addr_t card_addr, bus_size_t size, struct pcmcia_mem_handle *pcmhp, 2722 bus_addr_t *offsetp, int *windowp) 2723 { 2724 struct pcic_handle *ph = (struct pcic_handle *)pch; 2725 bus_addr_t busaddr; 2726 long card_offset; 2727 int win; 2728 2729 /* Check that the card is still there. */ 2730 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2731 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2732 return 1; 2733 2734 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2735 if ((ph->memalloc & (1 << win)) == 0) { 2736 ph->memalloc |= (1 << win); 2737 break; 2738 } 2739 } 2740 2741 if (win == PCIC_MEM_WINS) { 2742 return 1; 2743 } 2744 2745 *windowp = win; 2746 2747 /* XXX this is pretty gross */ 2748 2749 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2750 panic("pccbb_pcmcia_mem_map memt is bogus"); 2751 } 2752 2753 busaddr = pcmhp->addr; 2754 2755 /* 2756 * compute the address offset to the pcmcia address space for the 2757 * pcic. this is intentionally signed. The masks and shifts below 2758 * will cause TRT to happen in the pcic registers. Deal with making 2759 * sure the address is aligned, and return the alignment offset. 2760 */ 2761 2762 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2763 card_addr -= *offsetp; 2764 2765 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2766 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2767 (u_long) card_addr)); 2768 2769 /* 2770 * include the offset in the size, and decrement size by one, since 2771 * the hw wants start/stop 2772 */ 2773 size += *offsetp - 1; 2774 2775 card_offset = (((long)card_addr) - ((long)busaddr)); 2776 2777 ph->mem[win].addr = busaddr; 2778 ph->mem[win].size = size; 2779 ph->mem[win].offset = card_offset; 2780 ph->mem[win].kind = kind; 2781 2782 pccbb_pcmcia_do_mem_map(ph, win); 2783 2784 return 0; 2785 } 2786 2787 /* 2788 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2789 * int window) 2790 * 2791 * This function unmaps memory space which mapped by the function 2792 * pccbb_pcmcia_mem_map(). 2793 */ 2794 STATIC void 2795 pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, int window) 2796 { 2797 struct pcic_handle *ph = (struct pcic_handle *)pch; 2798 int reg; 2799 2800 if (window >= PCIC_MEM_WINS) { 2801 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2802 } 2803 2804 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2805 reg &= ~(1 << window); 2806 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2807 2808 ph->memalloc &= ~(1 << window); 2809 } 2810 2811 #if defined PCCBB_PCMCIA_POLL 2812 struct pccbb_poll_str { 2813 void *arg; 2814 int (*func)(void *); 2815 int level; 2816 struct pcic_handle *ph; 2817 int count; 2818 int num; 2819 struct callout poll_ch; 2820 }; 2821 2822 static struct pccbb_poll_str pccbb_poll[10]; 2823 static int pccbb_poll_n = 0; 2824 2825 static void pccbb_pcmcia_poll(void *arg); 2826 2827 static void 2828 pccbb_pcmcia_poll(void *arg) 2829 { 2830 struct pccbb_poll_str *poll = arg; 2831 struct pcic_handle *ph = poll->ph; 2832 struct pccbb_softc *sc = ph->sc; 2833 int s; 2834 u_int32_t spsr; /* socket present-state reg */ 2835 2836 callout_reset(&poll->poll_ch, hz * 2, pccbb_pcmcia_poll, arg); 2837 switch (poll->level) { 2838 case IPL_NET: 2839 s = splnet(); 2840 break; 2841 case IPL_BIO: 2842 s = splbio(); 2843 break; 2844 case IPL_TTY: /* fallthrough */ 2845 default: 2846 s = spltty(); 2847 break; 2848 } 2849 2850 spsr = 2851 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2852 CB_SOCKET_STAT); 2853 2854 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2855 if (!(spsr & 0x40)) /* CINT low */ 2856 #else 2857 if (1) 2858 #endif 2859 { 2860 if ((*poll->func) (poll->arg) > 0) { 2861 ++poll->count; 2862 /* printf("intr: reported from poller, 0x%x\n", spsr); */ 2863 #if defined LEVEL2 2864 } else { 2865 printf("intr: miss! 0x%x\n", spsr); 2866 #endif 2867 } 2868 } 2869 splx(s); 2870 } 2871 #endif /* defined CB_PCMCIA_POLL */ 2872 2873 /* 2874 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2875 * struct pcmcia_function *pf, 2876 * int ipl, 2877 * int (*func)(void *), 2878 * void *arg); 2879 * 2880 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2881 */ 2882 STATIC void * 2883 pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2884 struct pcmcia_function *pf, int ipl, int (*func)(void *), void *arg) 2885 { 2886 struct pcic_handle *ph = (struct pcic_handle *)pch; 2887 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2888 2889 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2890 /* what should I do? */ 2891 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2892 DPRINTF(("%s does not provide edge nor pulse " 2893 "interrupt\n", sc->sc_dev.dv_xname)); 2894 return NULL; 2895 } 2896 /* 2897 * XXX Noooooo! The interrupt flag must set properly!! 2898 * dumb pcmcia driver!! 2899 */ 2900 } 2901 2902 return pccbb_intr_establish(sc, 0, ipl, func, arg); 2903 } 2904 2905 /* 2906 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2907 * void *ih) 2908 * 2909 * This function disables PC-Card interrupt. 2910 */ 2911 STATIC void 2912 pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 2913 { 2914 struct pcic_handle *ph = (struct pcic_handle *)pch; 2915 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2916 2917 pccbb_intr_disestablish(sc, ih); 2918 } 2919 2920 #if rbus 2921 /* 2922 * static int 2923 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2924 * bus_addr_t addr, bus_size_t size, 2925 * bus_addr_t mask, bus_size_t align, 2926 * int flags, bus_addr_t *addrp; 2927 * bus_space_handle_t *bshp) 2928 * 2929 * This function allocates a portion of memory or io space for 2930 * clients. This function is called from CardBus card drivers. 2931 */ 2932 static int 2933 pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2934 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 2935 int flags, bus_addr_t *addrp, bus_space_handle_t *bshp) 2936 { 2937 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2938 2939 DPRINTF(("pccbb_rbus_cb_space_alloc: addr 0x%lx, size 0x%lx, " 2940 "mask 0x%lx, align 0x%lx\n", (unsigned long)addr, 2941 (unsigned long)size, (unsigned long)mask, (unsigned long)align)); 2942 2943 if (align == 0) { 2944 align = size; 2945 } 2946 2947 if (rb->rb_bt == sc->sc_memt) { 2948 if (align < 16) { 2949 return 1; 2950 } 2951 /* 2952 * XXX: align more than 0x1000 to avoid overwrapping 2953 * memory windows for two or more devices. 0x1000 2954 * means memory window's granularity. 2955 * 2956 * Two or more devices should be able to share same 2957 * memory window region. However, overrapping memory 2958 * window is not good because some devices, such as 2959 * 3Com 3C575[BC], have a broken address decoder and 2960 * intrude other's memory region. 2961 */ 2962 if (align < 0x1000) { 2963 align = 0x1000; 2964 } 2965 } else if (rb->rb_bt == sc->sc_iot) { 2966 if (align < 4) { 2967 return 1; 2968 } 2969 /* XXX: hack for avoiding ISA image */ 2970 if (mask < 0x0100) { 2971 mask = 0x3ff; 2972 addr = 0x300; 2973 } 2974 2975 } else { 2976 DPRINTF(("pccbb_rbus_cb_space_alloc: Bus space tag 0x%lx is " 2977 "NOT used. io: 0x%lx, mem: 0x%lx\n", 2978 (unsigned long)rb->rb_bt, (unsigned long)sc->sc_iot, 2979 (unsigned long)sc->sc_memt)); 2980 return 1; 2981 /* XXX: panic here? */ 2982 } 2983 2984 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 2985 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 2986 return 1; 2987 } 2988 2989 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 2990 2991 return 0; 2992 } 2993 2994 /* 2995 * static int 2996 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 2997 * bus_space_handle_t *bshp, bus_size_t size); 2998 * 2999 * This function is called from CardBus card drivers. 3000 */ 3001 static int 3002 pccbb_rbus_cb_space_free(cardbus_chipset_tag_t ct, rbus_tag_t rb, 3003 bus_space_handle_t bsh, bus_size_t size) 3004 { 3005 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 3006 bus_space_tag_t bt = rb->rb_bt; 3007 3008 pccbb_close_win(sc, bt, bsh, size); 3009 3010 if (bt == sc->sc_memt) { 3011 } else if (bt == sc->sc_iot) { 3012 } else { 3013 return 1; 3014 /* XXX: panic here? */ 3015 } 3016 3017 return rbus_space_free(rb, bsh, size, NULL); 3018 } 3019 #endif /* rbus */ 3020 3021 #if rbus 3022 3023 static int 3024 pccbb_open_win(struct pccbb_softc *sc, bus_space_tag_t bst, bus_addr_t addr, 3025 bus_size_t size, bus_space_handle_t bsh, int flags) 3026 { 3027 struct pccbb_win_chain_head *head; 3028 bus_addr_t align; 3029 3030 head = &sc->sc_iowindow; 3031 align = 0x04; 3032 if (sc->sc_memt == bst) { 3033 head = &sc->sc_memwindow; 3034 align = 0x1000; 3035 DPRINTF(("using memory window, 0x%lx 0x%lx 0x%lx\n\n", 3036 (unsigned long)sc->sc_iot, (unsigned long)sc->sc_memt, 3037 (unsigned long)bst)); 3038 } 3039 3040 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 3041 printf("%s: pccbb_open_win: %s winlist insert failed\n", 3042 sc->sc_dev.dv_xname, 3043 (head == &sc->sc_memwindow) ? "mem" : "io"); 3044 } 3045 pccbb_winset(align, sc, bst); 3046 3047 return 0; 3048 } 3049 3050 static int 3051 pccbb_close_win(struct pccbb_softc *sc, bus_space_tag_t bst, 3052 bus_space_handle_t bsh, bus_size_t size) 3053 { 3054 struct pccbb_win_chain_head *head; 3055 bus_addr_t align; 3056 3057 head = &sc->sc_iowindow; 3058 align = 0x04; 3059 if (sc->sc_memt == bst) { 3060 head = &sc->sc_memwindow; 3061 align = 0x1000; 3062 } 3063 3064 if (pccbb_winlist_delete(head, bsh, size)) { 3065 printf("%s: pccbb_close_win: %s winlist delete failed\n", 3066 sc->sc_dev.dv_xname, 3067 (head == &sc->sc_memwindow) ? "mem" : "io"); 3068 } 3069 pccbb_winset(align, sc, bst); 3070 3071 return 0; 3072 } 3073 3074 static int 3075 pccbb_winlist_insert(struct pccbb_win_chain_head *head, bus_addr_t start, 3076 bus_size_t size, bus_space_handle_t bsh, int flags) 3077 { 3078 struct pccbb_win_chain *chainp, *elem; 3079 3080 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 3081 M_NOWAIT)) == NULL) 3082 return (1); /* fail */ 3083 3084 elem->wc_start = start; 3085 elem->wc_end = start + (size - 1); 3086 elem->wc_handle = bsh; 3087 elem->wc_flags = flags; 3088 3089 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3090 chainp = TAILQ_NEXT(chainp, wc_list)) { 3091 if (chainp->wc_end < start) 3092 continue; 3093 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 3094 return (0); 3095 } 3096 3097 TAILQ_INSERT_TAIL(head, elem, wc_list); 3098 return (0); 3099 } 3100 3101 static int 3102 pccbb_winlist_delete(struct pccbb_win_chain_head *head, bus_space_handle_t bsh, 3103 bus_size_t size) 3104 { 3105 struct pccbb_win_chain *chainp; 3106 3107 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3108 chainp = TAILQ_NEXT(chainp, wc_list)) { 3109 if (memcmp(&chainp->wc_handle, &bsh, sizeof(bsh))) 3110 continue; 3111 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 3112 printf("pccbb_winlist_delete: window 0x%lx size " 3113 "inconsistent: 0x%lx, 0x%lx\n", 3114 (unsigned long)chainp->wc_start, 3115 (unsigned long)(chainp->wc_end - chainp->wc_start), 3116 (unsigned long)(size - 1)); 3117 return 1; 3118 } 3119 3120 TAILQ_REMOVE(head, chainp, wc_list); 3121 free(chainp, M_DEVBUF); 3122 3123 return 0; 3124 } 3125 3126 return 1; /* fail: no candidate to remove */ 3127 } 3128 3129 static void 3130 pccbb_winset(bus_addr_t align, struct pccbb_softc *sc, bus_space_tag_t bst) 3131 { 3132 pci_chipset_tag_t pc; 3133 pcitag_t tag; 3134 bus_addr_t mask = ~(align - 1); 3135 struct { 3136 cardbusreg_t win_start; 3137 cardbusreg_t win_limit; 3138 int win_flags; 3139 } win[2]; 3140 struct pccbb_win_chain *chainp; 3141 int offs; 3142 3143 win[0].win_start = win[1].win_start = 0xffffffff; 3144 win[0].win_limit = win[1].win_limit = 0; 3145 win[0].win_flags = win[1].win_flags = 0; 3146 3147 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3148 offs = 0x2c; 3149 if (sc->sc_memt == bst) { 3150 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3151 offs = 0x1c; 3152 } 3153 3154 if (chainp != NULL) { 3155 win[0].win_start = chainp->wc_start & mask; 3156 win[0].win_limit = chainp->wc_end & mask; 3157 win[0].win_flags = chainp->wc_flags; 3158 chainp = TAILQ_NEXT(chainp, wc_list); 3159 } 3160 3161 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3162 if (win[1].win_start == 0xffffffff) { 3163 /* window 1 is not used */ 3164 if ((win[0].win_flags == chainp->wc_flags) && 3165 (win[0].win_limit + align >= 3166 (chainp->wc_start & mask))) { 3167 /* concatenate */ 3168 win[0].win_limit = chainp->wc_end & mask; 3169 } else { 3170 /* make new window */ 3171 win[1].win_start = chainp->wc_start & mask; 3172 win[1].win_limit = chainp->wc_end & mask; 3173 win[1].win_flags = chainp->wc_flags; 3174 } 3175 continue; 3176 } 3177 3178 /* Both windows are engaged. */ 3179 if (win[0].win_flags == win[1].win_flags) { 3180 /* same flags */ 3181 if (win[0].win_flags == chainp->wc_flags) { 3182 if (win[1].win_start - (win[0].win_limit + 3183 align) < 3184 (chainp->wc_start & mask) - 3185 ((chainp->wc_end & mask) + align)) { 3186 /* 3187 * merge window 0 and 1, and set win1 3188 * to chainp 3189 */ 3190 win[0].win_limit = win[1].win_limit; 3191 win[1].win_start = 3192 chainp->wc_start & mask; 3193 win[1].win_limit = 3194 chainp->wc_end & mask; 3195 } else { 3196 win[1].win_limit = 3197 chainp->wc_end & mask; 3198 } 3199 } else { 3200 /* different flags */ 3201 3202 /* concatenate win0 and win1 */ 3203 win[0].win_limit = win[1].win_limit; 3204 /* allocate win[1] to new space */ 3205 win[1].win_start = chainp->wc_start & mask; 3206 win[1].win_limit = chainp->wc_end & mask; 3207 win[1].win_flags = chainp->wc_flags; 3208 } 3209 } else { 3210 /* the flags of win[0] and win[1] is different */ 3211 if (win[0].win_flags == chainp->wc_flags) { 3212 win[0].win_limit = chainp->wc_end & mask; 3213 /* 3214 * XXX this creates overlapping windows, so 3215 * what should the poor bridge do if one is 3216 * cachable, and the other is not? 3217 */ 3218 printf("%s: overlapping windows\n", 3219 sc->sc_dev.dv_xname); 3220 } else { 3221 win[1].win_limit = chainp->wc_end & mask; 3222 } 3223 } 3224 } 3225 3226 pc = sc->sc_pc; 3227 tag = sc->sc_tag; 3228 pci_conf_write(pc, tag, offs, win[0].win_start); 3229 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3230 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3231 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3232 DPRINTF(("--pccbb_winset: win0 [0x%lx, 0x%lx), win1 [0x%lx, 0x%lx)\n", 3233 (unsigned long)pci_conf_read(pc, tag, offs), 3234 (unsigned long)pci_conf_read(pc, tag, offs + 4) + align, 3235 (unsigned long)pci_conf_read(pc, tag, offs + 8), 3236 (unsigned long)pci_conf_read(pc, tag, offs + 12) + align)); 3237 3238 if (bst == sc->sc_memt) { 3239 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3240 3241 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 3242 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 3243 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3244 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 3245 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3246 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3247 } 3248 } 3249 3250 #endif /* rbus */ 3251 3252 static void 3253 pccbb_powerhook(int why, void *arg) 3254 { 3255 struct pccbb_softc *sc = arg; 3256 pcireg_t reg; 3257 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3258 bus_space_handle_t base_memh = sc->sc_base_memh; 3259 3260 DPRINTF(("%s: power: why %d\n", sc->sc_dev.dv_xname, why)); 3261 3262 if (why == PWR_SUSPEND || why == PWR_STANDBY) { 3263 DPRINTF(("%s: power: why %d stopping intr\n", 3264 sc->sc_dev.dv_xname, why)); 3265 if (sc->sc_pil_intr_enable) { 3266 (void)pccbbintr_function(sc); 3267 } 3268 sc->sc_pil_intr_enable = 0; 3269 3270 pci_conf_capture(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf); 3271 3272 if (sc->sc_chipset == CB_RX5C47X) 3273 sc->sc_ricoh_misc_ctrl = pci_conf_read(sc->sc_pc, 3274 sc->sc_tag, 3275 RICOH_PCI_MISC_CTRL); 3276 3277 /* ToDo: deactivate or suspend child devices */ 3278 } 3279 3280 if (why == PWR_RESUME) { 3281 if (sc->sc_pwrmgt_offs != 0) { 3282 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, 3283 sc->sc_pwrmgt_offs + PCI_PMCSR); 3284 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 3285 reg & PCI_PMCSR_PME_EN) { 3286 /* powrstate != D0 */ 3287 3288 printf("%s going back to D0 mode\n", 3289 sc->sc_dev.dv_xname); 3290 reg &= ~PCI_PMCSR_STATE_MASK; 3291 reg |= PCI_PMCSR_STATE_D0; 3292 reg &= ~PCI_PMCSR_PME_EN; 3293 pci_conf_write(sc->sc_pc, sc->sc_tag, 3294 sc->sc_pwrmgt_offs + PCI_PMCSR, reg); 3295 3296 pci_conf_write(sc->sc_pc, sc->sc_tag, 3297 PCI_SOCKBASE, sc->sc_sockbase); 3298 pci_conf_write(sc->sc_pc, sc->sc_tag, 3299 PCI_BUSNUM, sc->sc_busnum); 3300 pccbb_chipinit(sc); 3301 /* setup memory and io space window for CB */ 3302 pccbb_winset(0x1000, sc, sc->sc_memt); 3303 pccbb_winset(0x04, sc, sc->sc_iot); 3304 goto norestore; 3305 } 3306 } 3307 3308 norestore: 3309 pci_conf_restore(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf); 3310 if (sc->sc_chipset == CB_RX5C47X) { 3311 pci_conf_write(sc->sc_pc, sc->sc_tag, 3312 RICOH_PCI_MISC_CTRL, sc->sc_ricoh_misc_ctrl); 3313 } 3314 3315 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_SOCKBASE) == 0) 3316 /* BIOS did not recover this register */ 3317 pci_conf_write (sc->sc_pc, sc->sc_tag, 3318 PCI_SOCKBASE, sc->sc_sockbase); 3319 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_BUSNUM) == 0) 3320 /* BIOS did not recover this register */ 3321 pci_conf_write (sc->sc_pc, sc->sc_tag, 3322 PCI_BUSNUM, sc->sc_busnum); 3323 /* CSC Interrupt: Card detect interrupt on */ 3324 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3325 /* Card detect intr is turned on. */ 3326 reg |= CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; 3327 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3328 /* reset interrupt */ 3329 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3330 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3331 3332 /* 3333 * check for card insertion or removal during suspend period. 3334 * XXX: the code can't cope with card swap (remove then 3335 * insert). how can we detect such situation? 3336 */ 3337 (void)pccbbintr(sc); 3338 3339 sc->sc_pil_intr_enable = 1; 3340 DPRINTF(("%s: power: RESUME enabling intr\n", 3341 sc->sc_dev.dv_xname)); 3342 3343 /* ToDo: activate or wakeup child devices */ 3344 } 3345 } 3346
Indexes created Tue Oct 14 21:09:58 GMT 2025