pccbb.c revision 1.14
1 /* $NetBSD: pccbb.c,v 1.14 2000/01/17 12:57:27 joda Exp $ */ 2 3 /* 4 * Copyright (c) 1998 and 1999 HAYAKAWA Koichi. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by HAYAKAWA Koichi. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 #define CBB_DEBUG 34 #define SHOW_REGS 35 #define PCCBB_PCMCIA_POLL 36 */ 37 /* #define CBB_DEBUG */ 38 39 /* 40 #define CB_PCMCIA_POLL 41 #define CB_PCMCIA_POLL_ONLY 42 #define LEVEL2 43 */ 44 45 #include <sys/types.h> 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/kernel.h> 49 #include <sys/errno.h> 50 #include <sys/ioctl.h> 51 #include <sys/syslog.h> 52 #include <sys/device.h> 53 #include <sys/malloc.h> 54 55 #include <machine/intr.h> 56 #include <machine/bus.h> 57 58 #include <dev/pci/pcivar.h> 59 #include <dev/pci/pcireg.h> 60 #include <dev/pci/pcidevs.h> 61 62 #include <dev/pci/pccbbreg.h> 63 64 #include <dev/cardbus/cardslotvar.h> 65 66 #include <dev/cardbus/cardbusvar.h> 67 68 #include <dev/pcmcia/pcmciareg.h> 69 #include <dev/pcmcia/pcmciavar.h> 70 71 #include <dev/ic/i82365reg.h> 72 #include <dev/ic/i82365var.h> 73 #include <dev/pci/pccbbvar.h> 74 75 #include "locators.h" 76 77 78 #ifndef __NetBSD_Version__ 79 struct cfdriver cbb_cd = { 80 NULL, "cbb", DV_DULL 81 }; 82 #endif 83 84 #if defined CBB_DEBUG 85 #define DPRINTF(x) printf x 86 #define STATIC 87 #else 88 #define DPRINTF(x) 89 #define STATIC static 90 #endif 91 92 93 #ifdef __BROKEN_INDIRECT_CONFIG 94 int pcicbbmatch __P((struct device *, void *, void *)); 95 #else 96 int pcicbbmatch __P((struct device *, struct cfdata *, void *)); 97 #endif 98 void pccbbattach __P((struct device *, struct device *, void *)); 99 int pccbbintr __P((void *)); 100 static void pci113x_insert __P((void *)); 101 102 static int pccbb_detect_card __P((struct pccbb_softc *)); 103 104 static void pccbb_pcmcia_write __P((struct pcic_handle *, int, u_int8_t)); 105 static u_int8_t pccbb_pcmcia_read __P((struct pcic_handle *, int)); 106 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 107 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 108 109 110 STATIC int cb_reset __P((struct pccbb_softc *)); 111 STATIC int cb_detect_voltage __P((struct pccbb_softc *)); 112 STATIC int cbbprint __P((void *, const char *)); 113 114 static int cb_chipset __P((u_int32_t, char const **, int *)); 115 STATIC void pccbb_pcmcia_attach_setup __P((struct pccbb_softc *, struct pcmciabus_attach_args *)); 116 #if 0 117 STATIC void pccbb_pcmcia_attach_card __P((struct pcic_handle *)); 118 STATIC void pccbb_pcmcia_detach_card __P((struct pcic_handle *, int)); 119 STATIC void pccbb_pcmcia_deactivate_card __P((struct pcic_handle *)); 120 #endif 121 122 STATIC int pccbb_ctrl __P((cardbus_chipset_tag_t, int)); 123 STATIC int pccbb_power __P((cardbus_chipset_tag_t, int)); 124 STATIC int pccbb_cardenable __P((struct pccbb_softc *sc, int function)); 125 #if !rbus 126 static int pccbb_io_open __P((cardbus_chipset_tag_t, int, u_int32_t, u_int32_t)); 127 static int pccbb_io_close __P((cardbus_chipset_tag_t, int)); 128 static int pccbb_mem_open __P((cardbus_chipset_tag_t, int, u_int32_t, u_int32_t)); 129 static int pccbb_mem_close __P((cardbus_chipset_tag_t, int)); 130 #endif /* !rbus */ 131 static void *pccbb_intr_establish __P((cardbus_chipset_tag_t, int irq, int level, int (* ih)(void *), void *sc)); 132 static void pccbb_intr_disestablish __P((cardbus_chipset_tag_t ct, void *ih)); 133 134 static cardbustag_t pccbb_make_tag __P((cardbus_chipset_tag_t, int, int, int)); 135 static void pccbb_free_tag __P((cardbus_chipset_tag_t, cardbustag_t)); 136 static cardbusreg_t pccbb_conf_read __P((cardbus_chipset_tag_t, cardbustag_t, int)); 137 static void pccbb_conf_write __P((cardbus_chipset_tag_t, cardbustag_t, int, cardbusreg_t)); 138 static void pccbb_chipinit __P((struct pccbb_softc *)); 139 140 141 STATIC int pccbb_pcmcia_mem_alloc __P((pcmcia_chipset_handle_t, bus_size_t, 142 struct pcmcia_mem_handle *)); 143 STATIC void pccbb_pcmcia_mem_free __P((pcmcia_chipset_handle_t, 144 struct pcmcia_mem_handle *)); 145 STATIC int pccbb_pcmcia_mem_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 146 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *)); 147 STATIC void pccbb_pcmcia_mem_unmap __P((pcmcia_chipset_handle_t, int)); 148 STATIC int pccbb_pcmcia_io_alloc __P((pcmcia_chipset_handle_t, bus_addr_t, 149 bus_size_t, bus_size_t, struct pcmcia_io_handle *)); 150 STATIC void pccbb_pcmcia_io_free __P((pcmcia_chipset_handle_t, 151 struct pcmcia_io_handle *)); 152 STATIC int pccbb_pcmcia_io_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 153 bus_size_t, struct pcmcia_io_handle *, int *)); 154 STATIC void pccbb_pcmcia_io_unmap __P((pcmcia_chipset_handle_t, int)); 155 STATIC void *pccbb_pcmcia_intr_establish __P((pcmcia_chipset_handle_t, 156 struct pcmcia_function *, int, int (*) (void *), void *)); 157 STATIC void pccbb_pcmcia_intr_disestablish __P((pcmcia_chipset_handle_t, void *)); 158 STATIC void pccbb_pcmcia_socket_enable __P((pcmcia_chipset_handle_t)); 159 STATIC void pccbb_pcmcia_socket_disable __P((pcmcia_chipset_handle_t)); 160 STATIC int pccbb_pcmcia_card_detect __P((pcmcia_chipset_handle_t pch)); 161 162 static void pccbb_pcmcia_do_io_map __P((struct pcic_handle *, int)); 163 static void pccbb_pcmcia_wait_ready __P((struct pcic_handle *)); 164 static void pccbb_pcmcia_do_mem_map __P((struct pcic_handle *, int)); 165 166 /* bus-space allocation and disallocation functions */ 167 #if rbus 168 169 static int pccbb_rbus_cb_space_alloc __P((cardbus_chipset_tag_t, rbus_tag_t, 170 bus_addr_t addr, bus_size_t size, 171 bus_addr_t mask, bus_size_t align, 172 int flags, bus_addr_t *addrp, 173 bus_space_handle_t *bshp)); 174 static int pccbb_rbus_cb_space_free __P((cardbus_chipset_tag_t, rbus_tag_t, 175 bus_space_handle_t, bus_size_t)); 176 177 #endif /* rbus */ 178 179 #if rbus 180 181 static int pccbb_open_win __P((struct pccbb_softc *, bus_space_tag_t, bus_addr_t, bus_size_t, bus_space_handle_t, int flags)); 182 static int pccbb_close_win __P((struct pccbb_softc *, bus_space_tag_t, bus_space_handle_t, bus_size_t)); 183 static int pccbb_winlist_insert __P((struct pccbb_win_chain **, bus_addr_t, 184 bus_size_t, bus_space_handle_t, int)); 185 static int pccbb_winlist_delete __P((struct pccbb_win_chain **, 186 bus_space_handle_t, bus_size_t)); 187 static void pccbb_winset __P((bus_addr_t align, struct pccbb_softc *, 188 bus_space_tag_t)); 189 void pccbb_winlist_show(struct pccbb_win_chain *); 190 191 #endif /* rbus */ 192 193 /* for config_defer */ 194 static void pccbb_pci_callback __P((struct device *)); 195 196 197 #if defined SHOW_REGS 198 static void cb_show_regs __P((pci_chipset_tag_t pc, pcitag_t tag, bus_space_tag_t memt, bus_space_handle_t memh)); 199 #endif 200 201 202 203 struct cfattach cbb_pci_ca = { 204 sizeof(struct pccbb_softc), pcicbbmatch, pccbbattach 205 }; 206 207 208 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 209 pccbb_pcmcia_mem_alloc, 210 pccbb_pcmcia_mem_free, 211 pccbb_pcmcia_mem_map, 212 pccbb_pcmcia_mem_unmap, 213 pccbb_pcmcia_io_alloc, 214 pccbb_pcmcia_io_free, 215 pccbb_pcmcia_io_map, 216 pccbb_pcmcia_io_unmap, 217 pccbb_pcmcia_intr_establish, 218 pccbb_pcmcia_intr_disestablish, 219 pccbb_pcmcia_socket_enable, 220 pccbb_pcmcia_socket_disable, 221 pccbb_pcmcia_card_detect 222 }; 223 224 #if rbus 225 static struct cardbus_functions pccbb_funcs = { 226 pccbb_rbus_cb_space_alloc, 227 pccbb_rbus_cb_space_free, 228 pccbb_intr_establish, 229 pccbb_intr_disestablish, 230 pccbb_ctrl, 231 pccbb_power, 232 pccbb_make_tag, 233 pccbb_free_tag, 234 pccbb_conf_read, 235 pccbb_conf_write, 236 }; 237 #else 238 static struct cardbus_functions pccbb_funcs = { 239 pccbb_ctrl, 240 pccbb_power, 241 pccbb_mem_open, 242 pccbb_mem_close, 243 pccbb_io_open, 244 pccbb_io_close, 245 pccbb_intr_establish, 246 pccbb_intr_disestablish, 247 pccbb_make_tag, 248 pccbb_conf_read, 249 pccbb_conf_write, 250 }; 251 #endif 252 253 254 255 256 int 257 pcicbbmatch(parent, match, aux) 258 struct device *parent; 259 #ifdef __BROKEN_INDIRECT_CONFIG 260 void *match; 261 #else 262 struct cfdata *match; 263 #endif 264 void *aux; 265 { 266 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 267 268 if(PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 269 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 270 PCI_INTERFACE(pa->pa_class) == 0) { 271 return 1; 272 } 273 274 return 0; 275 } 276 277 278 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 279 | ((prod) << PCI_PRODUCT_SHIFT)) 280 281 282 struct yenta_chipinfo { 283 pcireg_t yc_id; /* vendor tag | product tag */ 284 const char *yc_name; 285 int yc_chiptype; 286 int yc_flags; 287 } yc_chipsets[] = { 288 /* Texas Instruments chips */ 289 {MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), "TI1130", CB_TI113X, 290 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 291 {MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), "TI1131", CB_TI113X, 292 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 293 294 {MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), "TI1250", CB_TI12XX, 295 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 296 {MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), "TI1220", CB_TI12XX, 297 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 298 {MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), "TI1221", CB_TI12XX, 299 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 300 {MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), "TI1225", CB_TI12XX, 301 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 302 {MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), "TI1251", CB_TI12XX, 303 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 304 {MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), "TI1251B", CB_TI12XX, 305 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 306 {MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), "TI1211", CB_TI12XX, 307 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 308 {MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), "TI1420", CB_TI12XX, 309 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 310 {MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), "TI1450", CB_TI12XX, 311 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 312 {MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI2030), "TI2030", CB_UNKNOWN, 313 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 314 315 /* Ricoh chips */ 316 {MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), "Rx5C475", 317 CB_RX5C47X, PCCBB_PCMCIA_MEM_32}, 318 {MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), "RL5C476", 319 CB_RX5C47X, PCCBB_PCMCIA_MEM_32}, 320 {MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), "Rx5C477", 321 CB_RX5C47X, PCCBB_PCMCIA_MEM_32}, 322 {MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), "Rx5C478", 323 CB_RX5C47X, PCCBB_PCMCIA_MEM_32}, 324 325 {MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), "Rx5C465", 326 CB_RX5C46X, PCCBB_PCMCIA_MEM_32}, 327 {MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), "Rx5C466", 328 CB_RX5C46X, PCCBB_PCMCIA_MEM_32}, 329 330 /* Toshiba products */ 331 {MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), "ToPIC95", 332 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 333 {MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), "ToPIC95B", 334 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 335 {MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), "ToPIC97", 336 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 337 {MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), "ToPIC100", 338 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 339 340 /* Cirrus Logic products */ 341 {MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), "CL-PD683X", 342 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 343 {MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), "CL-PD683X", 344 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 345 346 /* sentinel, or Generic chip */ 347 {0 /* null id */, "unknown", CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 348 }; 349 350 351 352 static int 353 cb_chipset(pci_id, namep, flagp) 354 u_int32_t pci_id; 355 char const **namep; 356 int *flagp; 357 { 358 int loopend = sizeof(yc_chipsets)/sizeof(yc_chipsets[0]); 359 struct yenta_chipinfo *ycp, *ycend; 360 361 ycend = yc_chipsets + loopend; 362 363 for (ycp =yc_chipsets; ycp < ycend && pci_id != ycp->yc_id; ++ycp); 364 365 if (ycp == ycend) { 366 /* not found */ 367 ycp = yc_chipsets + loopend - 1; /* to point the sentinel */ 368 } 369 370 if (namep != NULL) { 371 *namep = ycp->yc_name; 372 } 373 374 if (flagp != NULL) { 375 *flagp = ycp->yc_flags; 376 } 377 378 return ycp->yc_chiptype; 379 } 380 381 382 383 static void 384 pccbb_shutdown(void *arg) 385 { 386 struct pccbb_softc *sc = arg; 387 pcireg_t command; 388 389 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 390 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 0); 391 392 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 393 394 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 395 PCI_COMMAND_MASTER_ENABLE); 396 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 397 398 } 399 400 void 401 pccbbattach(parent, self, aux) 402 struct device *parent; 403 struct device *self; 404 void *aux; 405 { 406 struct pccbb_softc *sc = (void *)self; 407 struct pci_attach_args *pa = aux; 408 pci_chipset_tag_t pc = pa->pa_pc; 409 pcireg_t sock_base, busreg; 410 bus_addr_t sockbase; 411 char const *name; 412 int flags; 413 414 sc->sc_chipset = cb_chipset(pa->pa_id, &name, &flags); 415 printf(" (%s), chipflags %d\n", name, flags); 416 417 #if rbus 418 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 419 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 420 #endif /* rbus */ 421 422 sc->sc_base_memh = 0; 423 424 /* 425 * MAP socket registers and ExCA registers on memory-space 426 * When no valid address is set on socket base registers (on pci 427 * config space), get it not polite way. 428 */ 429 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 430 431 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 432 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 433 /* The address must be valid. */ 434 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 435 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 436 NULL)) { 437 printf("%s: can't map socket base address 0x%x\n", sc->sc_dev.dv_xname, 438 sock_base); 439 /* I think it's funny: socket base registers must be mapped on 440 memory space, but ... */ 441 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 0, 442 &sc->sc_base_memt, &sc->sc_base_memh, 443 &sockbase, NULL)) { 444 printf("%s: can't map socket base address 0x%lx: io mode\n", 445 sc->sc_dev.dv_xname, sockbase); 446 /* give up... allocate register space via rbus. */ 447 sc->sc_base_memh = 0; 448 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 449 } 450 } else { 451 DPRINTF(("%s: socket base address 0x%lx\n", 452 sc->sc_dev.dv_xname, sockbase)); 453 } 454 } 455 456 457 sc->sc_mem_start = 0; /* XXX */ 458 sc->sc_mem_end = 0xffffffff; /* XXX */ 459 460 /* 461 * When interrupt isn't routed correctly, give up probing cbb and do 462 * not kill pcic-compatible port. 463 */ 464 if ((0 == pa->pa_intrline) || (255 == pa->pa_intrline)) { 465 printf(" Do not use %s because of intr unconfig.\n", sc->sc_dev.dv_xname); 466 return; 467 } 468 469 /* 470 * When bus number isn't set correctly, give up using 32-bit CardBus 471 * mode. 472 */ 473 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 474 #if notyet 475 if (((busreg >> 8) & 0xff) == 0) { 476 printf(" CardBus on %s will not be configured, because of bus no unconfig.\n", sc->sc_dev.dv_xname); 477 flags |= PCCBB_PCMCIA_16BITONLY; 478 } 479 #endif 480 481 /* pccbb_machdep.c end */ 482 483 484 #if defined CBB_DEBUG 485 { 486 static char *intrname[5] = {"NON", "A", "B", "C", "D"}; 487 printf(" intrpin %s, intrtag %d\n", intrname[pa->pa_intrpin], 488 pa->pa_intrline); 489 } 490 #endif 491 492 493 /* setup softc */ 494 sc->sc_pc = pc; 495 sc->sc_iot = pa->pa_iot; 496 sc->sc_memt = pa->pa_memt; 497 sc->sc_dmat = pa->pa_dmat; 498 sc->sc_tag = pa->pa_tag; 499 sc->sc_function = pa->pa_function; 500 501 sc->sc_intrline = pa->pa_intrline; 502 sc->sc_intrtag = pa->pa_intrtag; 503 sc->sc_intrpin = pa->pa_intrpin; 504 505 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 506 507 /* bus bridge initialisation */ 508 pccbb_chipinit(sc); 509 510 shutdownhook_establish(pccbb_shutdown, sc); 511 512 #if __NetBSD_Version__ > 103060000 513 config_defer(self, pccbb_pci_callback); 514 #else 515 pccbb_pci_callback(self); 516 #endif 517 } 518 519 520 521 522 static void 523 pccbb_pci_callback(self) 524 struct device *self; 525 { 526 struct pccbb_softc *sc = (void *)self; 527 pci_chipset_tag_t pc = sc->sc_pc; 528 bus_space_tag_t base_memt; 529 bus_space_handle_t base_memh; 530 u_int32_t maskreg; 531 pci_intr_handle_t ih; 532 const char *intrstr = NULL; 533 bus_addr_t sockbase; 534 struct cbslot_attach_args cba; 535 struct pcmciabus_attach_args paa; 536 struct cardslot_attach_args caa; 537 struct cardslot_softc *csc; 538 539 if (0 == sc->sc_base_memh) { 540 /* The socket registers aren't mapped correctly. */ 541 #if rbus 542 if (rbus_space_alloc(sc->sc_rbus_memt, 543 0, /* address: I don't mind where it is mapped */ 544 0x1000, /* size */ 545 0x0fff, /* mask */ 546 (sc->sc_chipset == CB_RX5C47X || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, /* align */ 547 0, /* flags */ 548 &sockbase, &sc->sc_base_memh)) { 549 return; 550 } 551 sc->sc_base_memt = sc->sc_memt; 552 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 553 DPRINTF(("%s: CardBus resister address 0x%lx -> 0x%x\n", 554 sc->sc_dev.dv_xname, sockbase, pci_conf_read(pc, sc->sc_tag, PCI_SOCKBASE))); 555 #else 556 sc->sc_base_memt = sc->sc_memt; 557 #if !defined CBB_PCI_BASE 558 #define CBB_PCI_BASE 0x20000000 559 #endif 560 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 561 0x1000, /* size */ 562 0x1000, /* alignment */ 563 0, /* boundary */ 564 0, /* flags */ 565 &sockbase, &sc->sc_base_memh)) { 566 /* cannot allocate memory space */ 567 return; 568 } 569 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 570 DPRINTF(("%s: CardBus resister address 0x%x -> 0x%x\n",sc->sc_dev.dv_xname, 571 sock_base, pci_conf_read(pc, sc->sc_tag, PCI_SOCKBASE))); 572 #endif 573 } 574 575 base_memt = sc->sc_base_memt; /* socket regs memory tag */ 576 base_memh = sc->sc_base_memh; /* socket regs memory handle */ 577 578 579 /* CSC Interrupt: Card detect interrupt on */ 580 maskreg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 581 maskreg |= CB_SOCKET_MASK_CD; /* Card detect intr is turned on. */ 582 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, maskreg); 583 /* reset interrupt */ 584 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, 585 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT)); 586 587 588 /* Map and establish the interrupt. */ 589 if (pci_intr_map(pc, sc->sc_intrtag, sc->sc_intrpin, 590 sc->sc_intrline, &ih)) { 591 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 592 return; 593 } 594 intrstr = pci_intr_string(pc, ih); 595 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 596 597 if (sc->sc_ih == NULL) { 598 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 599 if (intrstr != NULL) { 600 printf(" at %s", intrstr); 601 } 602 printf("\n"); 603 return; 604 } 605 606 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 607 608 { 609 u_int32_t sockstat = bus_space_read_4(base_memt,base_memh, CB_SOCKET_STAT); 610 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { /* card exist */ 611 sc->sc_flags |= CBB_CARDEXIST; 612 } 613 } 614 615 /* 616 * attach cardbus 617 */ 618 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 619 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 620 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 621 622 /* initialise cbslot_attach */ 623 cba.cba_busname = "cardbus"; 624 cba.cba_iot = sc->sc_iot; 625 cba.cba_memt = sc->sc_memt; 626 cba.cba_dmat = sc->sc_dmat; 627 cba.cba_function = 0; 628 cba.cba_bus = (busreg >> 8) & 0x0ff; 629 cba.cba_cc = (void *)sc; 630 cba.cba_cf = &pccbb_funcs; 631 cba.cba_intrline = sc->sc_intrline; 632 633 #if rbus 634 cba.cba_rbus_iot = sc->sc_rbus_iot; 635 cba.cba_rbus_memt = sc->sc_rbus_memt; 636 #endif 637 638 cba.cba_cacheline = PCI_CACHELINE(bhlc); 639 cba.cba_lattimer = PCI_CB_LATENCY(busreg); 640 641 printf("%s: cacheline 0x%x lattimer 0x%x\n", sc->sc_dev.dv_xname, 642 cba.cba_cacheline, cba.cba_lattimer); 643 printf("%s: bhlc 0x%x lscp 0x%x\n", sc->sc_dev.dv_xname, 644 bhlc, busreg); 645 #if defined SHOW_REGS 646 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, sc->sc_base_memh); 647 #endif 648 } 649 650 pccbb_pcmcia_attach_setup(sc, &paa); 651 caa.caa_cb_attach = NULL; 652 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 653 caa.caa_cb_attach = &cba; 654 } 655 caa.caa_16_attach = &paa; 656 caa.caa_ph = &sc->sc_pcmcia_h; 657 658 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 659 DPRINTF(("pccbbattach: found cardslot\n")); 660 sc->sc_csc = csc; 661 } 662 663 return; 664 } 665 666 667 668 static void 669 pccbb_chipinit(sc) 670 struct pccbb_softc *sc; 671 { 672 pci_chipset_tag_t pc = sc->sc_pc; 673 pcitag_t tag = sc->sc_tag; 674 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory tag */ 675 bus_space_handle_t base_memh = sc->sc_base_memh; /* socket regs memory handle */ 676 pcireg_t cbctrl; 677 678 /* 679 * Set PCI command reg. 680 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 681 */ 682 { 683 pcireg_t command = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 684 685 /* I believe it is harmless. */ 686 command |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 687 PCI_COMMAND_MASTER_ENABLE); 688 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, command); 689 } 690 691 /* 692 * Set CardBus latency timer 693 */ 694 { 695 pcireg_t pci_lscp = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 696 if (PCI_CB_LATENCY(pci_lscp) < 0x20) { 697 pci_lscp &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 698 pci_lscp |= (0x20 << PCI_CB_LATENCY_SHIFT); 699 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, pci_lscp); 700 } 701 DPRINTF(("CardBus latency timer 0x%x (%x)\n", PCI_CB_LATENCY(pci_lscp), 702 pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 703 } 704 705 /* 706 * Set PCI latency timer 707 */ 708 { 709 pcireg_t pci_bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG); 710 if (PCI_LATTIMER(pci_bhlc) < 0x10) { 711 pci_bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 712 pci_bhlc |= (0x10 << PCI_LATTIMER_SHIFT); 713 pci_conf_write(pc, tag, PCI_BHLC_REG, pci_bhlc); 714 } 715 DPRINTF(("PCI latency timer 0x%x (%x)\n", PCI_LATTIMER(pci_bhlc), 716 pci_conf_read(pc, tag, PCI_BHLC_REG))); 717 } 718 719 /* disable Legacy IO */ 720 721 switch (sc->sc_chipset) { 722 case CB_RX5C46X: /* fallthrogh */ 723 #if 0 724 case CB_RX5C47X: 725 #endif 726 /* 727 * The legacy pcic io-port on Ricoh CardBus bridges cannot be 728 * disabled by substituting 0 into PCI_LEGACY register. Ricoh 729 * CardBus bridges have special bits on Bridge control reg (addr 730 * 0x3e on PCI config space). 731 */ 732 { 733 pcireg_t bcri = pci_conf_read(pc, tag, PCI_BCR_INTR); 734 bcri &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 735 pci_conf_write(pc, tag, PCI_BCR_INTR, bcri); 736 } 737 break; 738 default: 739 /* XXX: I don't know proper way to kill Legacy IO properly. */ 740 pci_conf_write(pc, tag, PCI_LEGACY, 0x0); 741 break; 742 } 743 744 745 746 /* 747 * Interrupt routing: use PCI interrupt 748 */ 749 { 750 u_int32_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 751 bcr &= ~CB_BCR_INTR_IREQ_ENABLE; /* use PCI Intr */ 752 bcr |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 753 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 754 } 755 756 if (CB_TI113X == sc->sc_chipset) { 757 cbctrl = pci_conf_read(pc, tag, PCI_CBCTRL); 758 if (0 == sc->sc_function) { 759 cbctrl |= PCI113X_CBCTRL_PCI_IRQ_ENA; 760 } 761 cbctrl |= PCI113X_CBCTRL_PCI_IRQ_ENA; /* XXX: bug in PCI113X */ 762 cbctrl |= PCI113X_CBCTRL_PCI_CSC; /* CSC intr enable */ 763 cbctrl &= ~PCI113X_CBCTRL_PCI_INTR; /* functional intr prohibit */ 764 cbctrl &= ~PCI113X_CBCTRL_INT_MASK; /* prohibit ISA routing */ 765 pci_conf_write(pc, tag, PCI_CBCTRL, cbctrl); 766 767 /* set ExCA regs: PCI113X required to be set bit 4 at Interrupt 768 and General Register, which is IRQ Enable Register, and clear 769 bit 3:0 to zero in order to route CSC interrupt to PCI 770 interrupt pin. */ 771 bus_space_write_1(base_memt, base_memh, 0x0803, 0x10); 772 /* set ExCA regs: prohibit all pcmcia-style CSC intr. */ 773 bus_space_write_1(base_memt, base_memh, 0x0805, 0x00); 774 #if 1 775 DPRINTF(("ExCA regs:")); 776 DPRINTF((" 0x803: %02x", bus_space_read_1(base_memt, base_memh, 0x803))); 777 DPRINTF((" 0x805: %02x", bus_space_read_1(base_memt, base_memh, 0x805))); 778 DPRINTF((" 0x81e: %02x\n", bus_space_read_1(base_memt,base_memh,0x81e))); 779 #endif 780 } else if (sc->sc_chipset == CB_TI12XX) { 781 cbctrl = pci_conf_read(pc, tag, PCI_CBCTRL); 782 cbctrl &= ~PCI12XX_CBCTRL_INT_MASK; /* intr routing reset */ 783 pci_conf_write(pc, tag, PCI_CBCTRL, cbctrl); 784 /* 785 * set ExCA regs: PCI12XX required to be set bit 4 at Interrupt 786 * and General Register, which is IRQ Enable Register, and clear 787 * bit 3:0 to zero in order to route CSC interrupt to PCI 788 * interrupt pin. 789 */ 790 bus_space_write_1(base_memt, base_memh, 0x0803, 0x10); 791 /* set ExCA regs: prohibit all pcmcia-style CSC intr. */ 792 bus_space_write_1(base_memt, base_memh, 0x0805, 0x00); 793 } else if (sc->sc_chipset == CB_TOPIC95B) { 794 cardbusreg_t sock_ctrl, slot_ctrl; 795 796 sock_ctrl = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 797 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, 798 sock_ctrl | TOPIC_SOCKET_CTRL_SCR_IRQSEL); 799 800 slot_ctrl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 801 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", sc->sc_dev.dv_xname, 802 slot_ctrl)); 803 slot_ctrl |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 804 TOPIC_SLOT_CTRL_ID_LOCK); 805 slot_ctrl |= TOPIC_SLOT_CTRL_CARDBUS; 806 slot_ctrl &= ~TOPIC_SLOT_CTRL_SWDETECT; 807 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slot_ctrl); 808 DPRINTF(("0x%x\n", slot_ctrl)); 809 } 810 811 /* close all memory and io windows */ 812 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 813 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 814 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 815 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 816 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 817 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 818 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 819 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 820 821 return; 822 } 823 824 825 826 /* 827 * attach pccard bus 828 */ 829 STATIC void 830 pccbb_pcmcia_attach_setup(sc, paa) 831 struct pccbb_softc *sc; 832 struct pcmciabus_attach_args *paa; 833 { 834 struct pcic_handle *ph = &sc->sc_pcmcia_h; 835 #if rbus 836 rbus_tag_t rb; 837 #endif 838 839 /* initialise pcmcia part in pccbb_softc */ 840 ph->ph_parent = (struct device *)sc; 841 ph->sock = sc->sc_function; 842 ph->flags = 0; 843 ph->shutdown = 0; 844 ph->ih_irq = sc->sc_intrline; 845 ph->ph_bus_t = sc->sc_base_memt; 846 ph->ph_bus_h = sc->sc_base_memh; 847 ph->ph_read = pccbb_pcmcia_read; 848 ph->ph_write = pccbb_pcmcia_write; 849 sc->sc_pct = &pccbb_pcmcia_funcs; 850 851 Pcic_write(ph, PCIC_CSC_INTR, 0); 852 Pcic_read(ph, PCIC_CSC); 853 854 /* initialise pcmcia bus attachment */ 855 paa->paa_busname = "pcmcia"; 856 paa->pct = sc->sc_pct; 857 paa->pch = ph; 858 paa->iobase = 0; /* I don't use them */ 859 paa->iosize = 0; 860 #if rbus 861 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 862 paa->iobase = rb->rb_start + rb->rb_offset; 863 paa->iosize = rb->rb_end - rb->rb_start; 864 #endif 865 866 return; 867 } 868 869 870 #if 0 871 STATIC void 872 pccbb_pcmcia_attach_card(ph) 873 struct pcic_handle *ph; 874 { 875 if (ph->flags & PCIC_FLAG_CARDP) { 876 panic("pccbb_pcmcia_attach_card: already attached"); 877 } 878 879 /* call the MI attach function */ 880 pcmcia_card_attach(ph->pcmcia); 881 882 ph->flags |= PCIC_FLAG_CARDP; 883 } 884 885 886 STATIC void 887 pccbb_pcmcia_detach_card(ph, flags) 888 struct pcic_handle *ph; 889 int flags; 890 { 891 if (!(ph->flags & PCIC_FLAG_CARDP)) { 892 panic("pccbb_pcmcia_detach_card: already detached"); 893 } 894 895 ph->flags &= ~PCIC_FLAG_CARDP; 896 897 /* call the MI detach function */ 898 pcmcia_card_detach(ph->pcmcia, flags); 899 } 900 #endif 901 902 903 904 905 /* 906 * int pccbbintr(arg) 907 * void *arg; 908 * This routine handles the interrupt from Yenta PCI-CardBus bridge 909 * itself. 910 */ 911 int 912 pccbbintr(arg) 913 void *arg; 914 { 915 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 916 u_int32_t sockevent; 917 bus_space_tag_t memt = sc->sc_base_memt; 918 bus_space_handle_t memh = sc->sc_base_memh; 919 u_int32_t sockstate; 920 921 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 922 if (0 == sockevent) { /* not for me */ 923 return 0; 924 } else { 925 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); /* reset bit */ 926 } 927 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 928 929 if (sockevent & CB_SOCKET_EVENT_CD) { 930 if (CB_SOCKET_STAT_CD == (sockstate & CB_SOCKET_STAT_CD)) { 931 /* A card should be removed. */ 932 if (sc->sc_flags & CBB_CARDEXIST) { 933 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 934 DPRINTF((" card removed, 0x%08x\n", sockstate)); 935 sc->sc_flags &= ~CBB_CARDEXIST; 936 if (sc->sc_csc->sc_status & CARDSLOT_STATUS_CARD_16) { 937 #if 0 938 struct pcic_handle *ph = &sc->sc_pcmcia_h; 939 940 pcmcia_card_deactivate(ph->pcmcia); 941 pccbb_pcmcia_socket_disable(ph); 942 pccbb_pcmcia_detach_card(ph, DETACH_FORCE); 943 #endif 944 cardslot_event_throw(sc->sc_csc, CARDSLOT_EVENT_REMOVAL_16); 945 } else if (sc->sc_csc->sc_status & CARDSLOT_STATUS_CARD_CB) { 946 /* Cardbus intr removed */ 947 cardslot_event_throw(sc->sc_csc, CARDSLOT_EVENT_REMOVAL_CB); 948 } 949 } 950 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD)) { 951 if (sc->sc_flags & CBB_INSERTING) { 952 untimeout(pci113x_insert, sc); 953 } 954 timeout(pci113x_insert, sc, hz/10); 955 sc->sc_flags |= CBB_INSERTING; 956 } 957 } else { 958 DPRINTF(("%s: sockevent = %b\n", 959 sc->sc_dev.dv_xname, sockevent, PCCBB_SOCKEVENT_BITS)); 960 DPRINTF(("%s: sockstate = %b\n", 961 sc->sc_dev.dv_xname, 962 sockstate, PCCBB_SOCKSTATE_BITS)); 963 } 964 965 return 1; 966 } 967 968 969 970 static void 971 pci113x_insert(arg) 972 void *arg; 973 { 974 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 975 u_int32_t sockevent, sockstate; 976 977 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 978 CB_SOCKET_EVENT); 979 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 980 CB_SOCKET_STAT); 981 982 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 983 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 984 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 985 sc->sc_flags |= CBB_CARDEXIST; 986 /* call pccard intterupt handler here */ 987 if (sockstate & CB_SOCKET_STAT_16BIT) { 988 /* 16-bit card found */ 989 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 990 cardslot_event_throw(sc->sc_csc, CARDSLOT_EVENT_INSERTION_16); 991 } else if (sockstate & CB_SOCKET_STAT_CB) { 992 /* cardbus card fuond */ 993 /* cardbus_attach_card(sc->sc_csc); */ 994 cardslot_event_throw(sc->sc_csc, CARDSLOT_EVENT_INSERTION_CB); 995 } else { 996 /* who are you? */ 997 } 998 } else { 999 timeout(pci113x_insert, sc, hz/10); 1000 } 1001 } 1002 1003 1004 1005 1006 #define PCCBB_PCMCIA_OFFSET 0x800 1007 static u_int8_t 1008 pccbb_pcmcia_read(ph, reg) 1009 struct pcic_handle *ph; 1010 int reg; 1011 { 1012 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg); 1013 } 1014 1015 1016 1017 static void 1018 pccbb_pcmcia_write(ph, reg, val) 1019 struct pcic_handle *ph; 1020 int reg; 1021 u_int8_t val; 1022 { 1023 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, val); 1024 1025 return; 1026 } 1027 1028 1029 1030 1031 /* 1032 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1033 */ 1034 STATIC int 1035 pccbb_ctrl(ct, command) 1036 cardbus_chipset_tag_t ct; 1037 int command; 1038 { 1039 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1040 1041 switch(command) { 1042 case CARDBUS_CD: 1043 if (2 == pccbb_detect_card(sc)) { 1044 int retval = 0; 1045 int status = cb_detect_voltage(sc); 1046 if (PCCARD_VCC_5V & status) { 1047 retval |= CARDBUS_5V_CARD; 1048 } 1049 if (PCCARD_VCC_3V & status) { 1050 retval |= CARDBUS_3V_CARD; 1051 } 1052 if (PCCARD_VCC_XV & status) { 1053 retval |= CARDBUS_XV_CARD; 1054 } 1055 if (PCCARD_VCC_YV & status) { 1056 retval |= CARDBUS_YV_CARD; 1057 } 1058 return retval; 1059 } else { 1060 return 0; 1061 } 1062 break; 1063 case CARDBUS_RESET: 1064 return cb_reset(sc); 1065 break; 1066 case CARDBUS_IO_ENABLE: /* fallthrough */ 1067 case CARDBUS_IO_DISABLE: /* fallthrough */ 1068 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1069 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1070 case CARDBUS_BM_ENABLE: /* fallthrough */ 1071 case CARDBUS_BM_DISABLE: /* fallthrough */ 1072 return pccbb_cardenable(sc, command); 1073 break; 1074 } 1075 1076 return 0; 1077 } 1078 1079 1080 1081 /* 1082 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1083 * This function returns true when it succeeds and returns false when 1084 * it fails. 1085 */ 1086 STATIC int 1087 pccbb_power(ct, command) 1088 cardbus_chipset_tag_t ct; 1089 int command; 1090 { 1091 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1092 1093 u_int32_t status, sock_ctrl; 1094 bus_space_tag_t memt = sc->sc_base_memt; 1095 bus_space_handle_t memh = sc->sc_base_memh; 1096 1097 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1098 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1099 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1100 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1101 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1102 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1103 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1104 "UNKNOWN", 1105 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1106 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1107 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1108 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1109 "UNKNOWN", 1110 command)); 1111 1112 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1113 sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1114 1115 switch (command & CARDBUS_VCCMASK) { 1116 case CARDBUS_VCC_UC: 1117 break; 1118 case CARDBUS_VCC_5V: 1119 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1120 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1121 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1122 } else { 1123 printf("%s: BAD voltage request: no 5 V card\n", sc->sc_dev.dv_xname); 1124 } 1125 break; 1126 case CARDBUS_VCC_3V: 1127 if (CB_SOCKET_STAT_3VCARD & status) { 1128 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1129 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1130 } else { 1131 printf("%s: BAD voltage request: no 3.3 V card\n", sc->sc_dev.dv_xname); 1132 } 1133 break; 1134 case CARDBUS_VCC_0V: 1135 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1136 break; 1137 default: 1138 return 0; /* power NEVER changed */ 1139 break; 1140 } 1141 1142 switch (command & CARDBUS_VPPMASK) { 1143 case CARDBUS_VPP_UC: 1144 break; 1145 case CARDBUS_VPP_0V: 1146 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1147 break; 1148 case CARDBUS_VPP_VCC: 1149 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1150 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1151 break; 1152 case CARDBUS_VPP_12V: 1153 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1154 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1155 break; 1156 } 1157 1158 #if 0 1159 DPRINTF(("sock_ctrl: %x\n", sock_ctrl)); 1160 #endif 1161 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1162 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1163 1164 delay(20*1000); /* wait 20 ms: Vcc setup time */ 1165 /* XXX 1166 delay 200 ms: though the standard defines that the Vcc set-up time 1167 is 20 ms, some PC-Card bridge requires longer duration. 1168 */ 1169 delay(200*1000); 1170 1171 1172 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1173 printf("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1174 sc->sc_dev.dv_xname, sock_ctrl ,status); 1175 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1176 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1177 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V": 1178 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V": 1179 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV": 1180 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV": 1181 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V": 1182 "UNKNOWN", 1183 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC": 1184 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ?"CARDBUS_VPP_12V": 1185 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ?"CARDBUS_VPP_VCC": 1186 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1187 "UNKNOWN", 1188 command)); 1189 #if 0 1190 if (command == (CARDBUS_VCC_0V | CARDBUS_VPP_0V)) { 1191 u_int32_t force = bus_space_read_4(memt, memh, CB_SOCKET_FORCE); 1192 /* Reset Bad Vcc request */ 1193 force &= ~CB_SOCKET_FORCE_BADVCC; 1194 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, force); 1195 printf("new status 0x%x\n", bus_space_read_4(memt, memh,CB_SOCKET_STAT)); 1196 return 1; 1197 } 1198 #endif 1199 return 0; 1200 } 1201 return 1; /* power changed correctly */ 1202 } 1203 1204 1205 1206 1207 1208 1209 #if defined CB_PCMCIA_POLL 1210 struct cb_poll_str { 1211 void *arg; 1212 int (* func) __P((void *)); 1213 int level; 1214 pccard_chipset_tag_t ct; 1215 int count; 1216 }; 1217 1218 static struct cb_poll_str cb_poll[10]; 1219 static int cb_poll_n = 0; 1220 1221 static void cb_pcmcia_poll __P((void *arg)); 1222 1223 static void 1224 cb_pcmcia_poll(arg) 1225 void *arg; 1226 { 1227 struct cb_poll_str *poll = arg; 1228 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1229 struct pccbb_softc *sc = psc->cpc_parent; 1230 int s; 1231 u_int32_t spsr; /* socket present-state reg */ 1232 1233 timeout(cb_pcmcia_poll, arg, hz/10); 1234 switch (poll->level) { 1235 case IPL_NET: 1236 s = splnet(); 1237 break; 1238 case IPL_BIO: 1239 s = splbio(); 1240 break; 1241 case IPL_TTY: /* fallthrough */ 1242 default: 1243 s = spltty(); 1244 break; 1245 } 1246 1247 spsr = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_STAT); 1248 1249 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1250 if (!(spsr & 0x40)) { /* CINT low */ 1251 #else 1252 if (1) { 1253 #endif 1254 if ((*poll->func)(poll->arg) == 1) { 1255 ++poll->count; 1256 printf("intr: reported from poller, 0x%x\n", spsr); 1257 #if defined LEVEL2 1258 } else { 1259 printf("intr: miss! 0x%x\n", spsr); 1260 #endif 1261 } 1262 } 1263 splx(s); 1264 } 1265 #endif /* defined CB_PCMCIA_POLL */ 1266 1267 1268 1269 1270 /* 1271 * static int pccbb_detect_card(struct pccbb_softc *sc) 1272 * return value: 0 if no card exists. 1273 * 1 if 16-bit card exists. 1274 * 2 if cardbus card exists. 1275 */ 1276 static int 1277 pccbb_detect_card(sc) 1278 struct pccbb_softc *sc; 1279 { 1280 bus_space_handle_t base_memh = sc->sc_base_memh; 1281 bus_space_tag_t base_memt = sc->sc_base_memt; 1282 u_int32_t sockstat = bus_space_read_4(base_memt,base_memh, CB_SOCKET_STAT); 1283 int retval = 0; 1284 1285 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { /* CD1 and CD2 asserted */ 1286 /* card must be present */ 1287 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { /* NOTACARD DEASSERTED */ 1288 if (CB_SOCKET_STAT_CB & sockstat) { /* CardBus mode */ 1289 retval = 2; 1290 } else if (CB_SOCKET_STAT_16BIT & sockstat) { /* 16-bit mode */ 1291 retval = 1; 1292 } 1293 } 1294 } 1295 return retval; 1296 } 1297 1298 1299 1300 1301 /* 1302 * STATIC int cb_reset(struct pccbb_softc *sc) 1303 * This function resets CardBus card. 1304 */ 1305 STATIC int 1306 cb_reset(sc) 1307 struct pccbb_softc *sc; 1308 { 1309 /* 1310 * Reset Assert at least 20 ms 1311 * Some machines request longer duration. 1312 */ 1313 int reset_duration = (sc->sc_chipset == CB_RX5C47X ? 400*1000 : 40*1000); 1314 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1315 1316 bcr |= (0x40 << 16); /* Reset bit Assert (bit 6 at 0x3E) */ 1317 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1318 delay(reset_duration); 1319 1320 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1321 bcr &= ~(0x40 << 16); /* Reset bit Deassert (bit 6 at 0x3E) */ 1322 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1323 delay(reset_duration); 1324 } 1325 /* No card found on the slot. Keep Reset. */ 1326 return 1; 1327 } 1328 1329 1330 1331 1332 /* 1333 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1334 * This function detect card Voltage. 1335 */ 1336 STATIC int 1337 cb_detect_voltage(sc) 1338 struct pccbb_softc *sc; 1339 { 1340 u_int32_t psr; /* socket present-state reg */ 1341 bus_space_tag_t iot = sc->sc_base_memt; 1342 bus_space_handle_t ioh = sc->sc_base_memh; 1343 int vol = PCCARD_VCC_UKN; /* set 0 */ 1344 1345 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1346 1347 if (0x400u & psr) { 1348 vol |= PCCARD_VCC_5V; 1349 } 1350 if (0x800u & psr) { 1351 vol |= PCCARD_VCC_3V; 1352 } 1353 1354 return vol; 1355 } 1356 1357 1358 1359 1360 1361 1362 STATIC int 1363 cbbprint(aux, pcic) 1364 void *aux; 1365 const char *pcic; 1366 { 1367 /* 1368 struct cbslot_attach_args *cba = aux; 1369 1370 if (cba->cba_slot >= 0) { 1371 printf(" slot %d", cba->cba_slot); 1372 } 1373 */ 1374 return UNCONF; 1375 } 1376 1377 1378 1379 1380 /* 1381 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1382 * This function enables and disables the card 1383 */ 1384 STATIC int 1385 pccbb_cardenable(sc, function) 1386 struct pccbb_softc *sc; 1387 int function; 1388 { 1389 u_int32_t command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1390 1391 DPRINTF(("pccbb_cardenable:")); 1392 switch (function) { 1393 case CARDBUS_IO_ENABLE: 1394 command |= PCI_COMMAND_IO_ENABLE; 1395 break; 1396 case CARDBUS_IO_DISABLE: 1397 command &= ~PCI_COMMAND_IO_ENABLE; 1398 break; 1399 case CARDBUS_MEM_ENABLE: 1400 command |= PCI_COMMAND_MEM_ENABLE; 1401 break; 1402 case CARDBUS_MEM_DISABLE: 1403 command &= ~PCI_COMMAND_MEM_ENABLE; 1404 break; 1405 case CARDBUS_BM_ENABLE: 1406 command |= PCI_COMMAND_MASTER_ENABLE; 1407 break; 1408 case CARDBUS_BM_DISABLE: 1409 command &= ~PCI_COMMAND_MASTER_ENABLE; 1410 break; 1411 default: 1412 return 0; 1413 } 1414 1415 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1416 DPRINTF((" command reg 0x%x\n", command)); 1417 return 1; 1418 } 1419 1420 1421 1422 1423 1424 1425 #if !rbus 1426 /* 1427 * int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1428 */ 1429 static int 1430 pccbb_io_open(ct, win, start, end) 1431 cardbus_chipset_tag_t ct; 1432 int win; 1433 u_int32_t start, end; 1434 { 1435 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1436 int basereg; 1437 int limitreg; 1438 1439 if ((win < 0) || (win > 2)) { 1440 #if defined DIAGNOSTIC 1441 printf("cardbus_io_open: window out of range %d\n", win); 1442 #endif 1443 return 0; 1444 } 1445 1446 basereg = win*8 + 0x2c; 1447 limitreg = win*8 + 0x30; 1448 1449 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1450 start, basereg, end, limitreg)); 1451 1452 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1453 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1454 return 1; 1455 } 1456 1457 /* 1458 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1459 */ 1460 static int 1461 pccbb_io_close(ct, win) 1462 cardbus_chipset_tag_t ct; 1463 int win; 1464 { 1465 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1466 int basereg; 1467 int limitreg; 1468 1469 if ((win < 0) || (win > 2)) { 1470 #if defined DIAGNOSTIC 1471 printf("cardbus_io_close: window out of range %d\n", win); 1472 #endif 1473 return 0; 1474 } 1475 1476 basereg = win*8 + 0x2c; 1477 limitreg = win*8 + 0x30; 1478 1479 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1480 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1481 return 1; 1482 } 1483 1484 /* 1485 * int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1486 */ 1487 static int 1488 pccbb_mem_open(ct, win, start, end) 1489 cardbus_chipset_tag_t ct; 1490 int win; 1491 u_int32_t start, end; 1492 { 1493 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1494 int basereg; 1495 int limitreg; 1496 1497 if ((win < 0) || (win > 2)) { 1498 #if defined DIAGNOSTIC 1499 printf("cardbus_mem_open: window out of range %d\n", win); 1500 #endif 1501 return 0; 1502 } 1503 1504 basereg = win*8 + 0x1c; 1505 limitreg = win*8 + 0x20; 1506 1507 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1508 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1509 return 1; 1510 } 1511 1512 1513 /* 1514 * int pccbb_mem_close(cardbus_chipset_tag_t, int) 1515 */ 1516 static int 1517 pccbb_mem_close(ct, win) 1518 cardbus_chipset_tag_t ct; 1519 int win; 1520 { 1521 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1522 int basereg; 1523 int limitreg; 1524 1525 if ((win < 0) || (win > 2)) { 1526 #if defined DIAGNOSTIC 1527 printf("cardbus_mem_close: window out of range %d\n", win); 1528 #endif 1529 return 0; 1530 } 1531 1532 basereg = win*8 + 0x1c; 1533 limitreg = win*8 + 0x20; 1534 1535 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1536 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1537 return 1; 1538 } 1539 #endif 1540 1541 1542 1543 static void * 1544 pccbb_intr_establish(ct, irq, level, func, arg) 1545 cardbus_chipset_tag_t ct; 1546 int irq, level; 1547 int (* func) __P((void *)); 1548 void *arg; 1549 { 1550 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1551 1552 switch (sc->sc_chipset) { 1553 case CB_TI113X: 1554 { 1555 pcireg_t cbctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1556 cbctrl |= PCI113X_CBCTRL_PCI_INTR; /* functional intr enabled */ 1557 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, cbctrl); 1558 } 1559 break; 1560 default: 1561 break; 1562 } 1563 1564 return pci_intr_establish(sc->sc_pc, irq, level, func, arg); 1565 } 1566 1567 1568 1569 1570 static void 1571 pccbb_intr_disestablish(ct, ih) 1572 cardbus_chipset_tag_t ct; 1573 void *ih; 1574 { 1575 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1576 1577 switch (sc->sc_chipset) { 1578 case CB_TI113X: 1579 { 1580 pcireg_t cbctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1581 cbctrl &= ~PCI113X_CBCTRL_PCI_INTR; /* functional intr disabled */ 1582 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, cbctrl); 1583 } 1584 break; 1585 default: 1586 break; 1587 } 1588 1589 pci_intr_disestablish(sc->sc_pc, ih); 1590 } 1591 1592 1593 1594 1595 1596 #if defined SHOW_REGS 1597 static void 1598 cb_show_regs(pc, tag, memt, memh) 1599 pci_chipset_tag_t pc; 1600 pcitag_t tag; 1601 bus_space_tag_t memt; 1602 bus_space_handle_t memh; 1603 { 1604 int i; 1605 printf("PCI config regs:"); 1606 for (i = 0; i < 0x50; i += 4) { 1607 if (i % 16 == 0) { 1608 printf("\n 0x%02x:", i); 1609 } 1610 printf(" %08x", pci_conf_read(pc, tag, i)); 1611 } 1612 for (i = 0x80; i < 0xb0; i += 4) { 1613 if (i % 16 == 0) { 1614 printf("\n 0x%02x:", i); 1615 } 1616 printf(" %08x", pci_conf_read(pc, tag, i)); 1617 } 1618 1619 if (memh == 0) { 1620 printf("\n"); 1621 return; 1622 } 1623 1624 printf("\nsocket regs:"); 1625 for (i = 0; i <= 0x10; i += 0x04) { 1626 printf(" %08x", bus_space_read_4(memt, memh, i)); 1627 } 1628 printf("\nExCA regs:"); 1629 for (i = 0; i < 0x08; ++i) { 1630 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1631 } 1632 printf("\n"); 1633 return; 1634 } 1635 #endif 1636 1637 1638 1639 /* 1640 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1641 * int busno, int devno, int function) 1642 * This is the function to make a tag to access config space of 1643 * a CardBus Card. It works same as pci_conf_read. 1644 */ 1645 static cardbustag_t 1646 pccbb_make_tag(cc, busno, devno, function) 1647 cardbus_chipset_tag_t cc; 1648 int busno, devno, function; 1649 { 1650 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1651 1652 return pci_make_tag(sc->sc_pc, busno, devno, function); 1653 } 1654 1655 1656 static void 1657 pccbb_free_tag(cc, tag) 1658 cardbus_chipset_tag_t cc; 1659 cardbustag_t tag; 1660 { 1661 } 1662 1663 1664 /* 1665 * static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t cc, 1666 * cardbustag_t tag, int offset) 1667 * This is the function to read the config space of a CardBus Card. 1668 * It works same as pci_conf_read. 1669 */ 1670 static cardbusreg_t 1671 pccbb_conf_read(cc, tag, offset) 1672 cardbus_chipset_tag_t cc; 1673 cardbustag_t tag; 1674 int offset; /* register offset */ 1675 { 1676 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1677 1678 return pci_conf_read(sc->sc_pc, tag, offset); 1679 } 1680 1681 1682 1683 /* 1684 * static void pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, 1685 * int offs, cardbusreg_t val) 1686 * This is the function to write the config space of a CardBus Card. 1687 * It works same as pci_conf_write. 1688 */ 1689 static void 1690 pccbb_conf_write(cc, tag, reg, val) 1691 cardbus_chipset_tag_t cc; 1692 cardbustag_t tag; 1693 int reg; /* register offset */ 1694 cardbusreg_t val; 1695 { 1696 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1697 1698 pci_conf_write(sc->sc_pc, tag, reg, val); 1699 } 1700 1701 1702 1703 1704 1705 #if 0 1706 STATIC int 1707 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1708 bus_addr_t start, bus_size_t size, 1709 bus_size_t align, bus_addr_t mask, /* address line width */ 1710 int speed, int flags, /* bus width */ 1711 bus_space_handle_t *iohp) 1712 #endif 1713 1714 1715 /* 1716 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1717 * bus_addr_t start, bus_size_t size, 1718 * bus_size_t align, 1719 * struct pcmcia_io_handle *pcihp 1720 * 1721 * This function only allocates I/O region for pccard. This function 1722 * never maps the allcated region to pccard I/O area. 1723 * 1724 * XXX: The interface of this function is not very good, I believe. 1725 */ 1726 STATIC int 1727 pccbb_pcmcia_io_alloc(pch, start, size, align, pcihp) 1728 pcmcia_chipset_handle_t pch; 1729 bus_addr_t start; /* start address */ 1730 bus_size_t size; 1731 bus_size_t align; 1732 struct pcmcia_io_handle *pcihp; 1733 { 1734 struct pcic_handle *ph = (struct pcic_handle *)pch; 1735 bus_addr_t ioaddr; 1736 int flags = 0; 1737 bus_space_tag_t iot; 1738 bus_space_handle_t ioh; 1739 #if rbus 1740 rbus_tag_t rb; 1741 #endif 1742 if (align == 0) { 1743 align = size; /* XXX: funny??? */ 1744 } 1745 1746 1747 /* 1748 * Allocate some arbitrary I/O space. 1749 */ 1750 1751 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 1752 1753 #if rbus 1754 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 1755 if (rbus_space_alloc(rb, start, size, 0x3ff /* XXX: I assume all card decode lower 10 bits by its hardware */, 1756 align, 0, &ioaddr, &ioh)) { 1757 return 1; 1758 } 1759 #else 1760 if (start) { 1761 ioaddr = start; 1762 if (bus_space_map(iot, start, size, 0, &ioh)) { 1763 return 1; 1764 } 1765 DPRINTF(("pccbb_pcmcia_io_alloc map port %lx+%lx\n", 1766 (u_long) ioaddr, (u_long) size)); 1767 } else { 1768 flags |= PCMCIA_IO_ALLOCATED; 1769 if (bus_space_alloc(iot, 0x700/* ph->sc->sc_iobase */, 1770 0x800/* ph->sc->sc_iobase + ph->sc->sc_iosize*/, 1771 size, align, 0, 0, &ioaddr, &ioh)) { 1772 /* No room be able to be get. */ 1773 return 1; 1774 } 1775 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 1776 (u_long) ioaddr, (u_long) size)); 1777 } 1778 #endif 1779 1780 pcihp->iot = iot; 1781 pcihp->ioh = ioh; 1782 pcihp->addr = ioaddr; 1783 pcihp->size = size; 1784 pcihp->flags = flags; 1785 1786 return 0; 1787 } 1788 1789 1790 1791 1792 1793 /* 1794 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 1795 * struct pcmcia_io_handle *pcihp) 1796 * 1797 * This function only frees I/O region for pccard. 1798 * 1799 * XXX: The interface of this function is not very good, I believe. 1800 */ 1801 void 1802 pccbb_pcmcia_io_free(pch, pcihp) 1803 pcmcia_chipset_handle_t pch; 1804 struct pcmcia_io_handle *pcihp; 1805 { 1806 #if !rbus 1807 bus_space_tag_t iot = pcihp->iot; 1808 #endif 1809 bus_space_handle_t ioh = pcihp->ioh; 1810 bus_size_t size = pcihp->size; 1811 1812 #if rbus 1813 struct pccbb_softc *sc = (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 1814 rbus_tag_t rb = sc->sc_rbus_iot; 1815 1816 rbus_space_free(rb, ioh, size, NULL); 1817 #else 1818 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 1819 bus_space_free(iot, ioh, size); 1820 else 1821 bus_space_unmap(iot, ioh, size); 1822 #endif 1823 } 1824 1825 1826 1827 /* 1828 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 1829 * bus_addr_t offset, bus_size_t size, 1830 * struct pcmcia_io_handle *pcihp, 1831 * int *windowp) 1832 * 1833 * This function maps the allocated I/O region to pccard. This function 1834 * never allocates any I/O region for pccard I/O area. I don't 1835 * understand why the original authors of pcmciabus separated alloc and 1836 * map. I believe the two must be unite. 1837 * 1838 * XXX: no wait timing control? 1839 */ 1840 int 1841 pccbb_pcmcia_io_map(pch, width, offset, size, pcihp, windowp) 1842 pcmcia_chipset_handle_t pch; 1843 int width; 1844 bus_addr_t offset; 1845 bus_size_t size; 1846 struct pcmcia_io_handle *pcihp; 1847 int *windowp; 1848 { 1849 struct pcic_handle *ph = (struct pcic_handle *) pch; 1850 bus_addr_t ioaddr = pcihp->addr + offset; 1851 int i, win; 1852 #if defined CBB_DEBUG 1853 static char *width_names[] = { "dynamic", "io8", "io16" }; 1854 #endif 1855 1856 /* Sanity check I/O handle. */ 1857 1858 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 1859 panic("pccbb_pcmcia_io_map iot is bogus"); 1860 } 1861 1862 /* XXX Sanity check offset/size. */ 1863 1864 win = -1; 1865 for (i = 0; i < PCIC_IO_WINS; i++) { 1866 if ((ph->ioalloc & (1 << i)) == 0) { 1867 win = i; 1868 ph->ioalloc |= (1 << i); 1869 break; 1870 } 1871 } 1872 1873 if (win == -1) { 1874 return 1; 1875 } 1876 1877 *windowp = win; 1878 1879 /* XXX this is pretty gross */ 1880 1881 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 1882 win, width_names[width], (u_long) ioaddr, (u_long) size)); 1883 1884 /* XXX wtf is this doing here? */ 1885 1886 #if 0 1887 printf(" port 0x%lx", (u_long) ioaddr); 1888 if (size > 1) { 1889 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 1890 } 1891 #endif 1892 1893 ph->io[win].addr = ioaddr; 1894 ph->io[win].size = size; 1895 ph->io[win].width = width; 1896 1897 /* actual dirty register-value changing in the function below. */ 1898 pccbb_pcmcia_do_io_map(ph, win); 1899 1900 return 0; 1901 } 1902 1903 1904 1905 /* 1906 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 1907 * 1908 * This function changes register-value to map I/O region for pccard. 1909 */ 1910 static void 1911 pccbb_pcmcia_do_io_map(ph, win) 1912 struct pcic_handle *ph; 1913 int win; 1914 { 1915 static u_int8_t pcic_iowidth[3] = { 1916 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 1917 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | PCIC_IOCTL_IO0_DATASIZE_8BIT, 1918 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | PCIC_IOCTL_IO0_DATASIZE_16BIT, 1919 }; 1920 1921 #define PCIC_SIA_START_LOW 0 1922 #define PCIC_SIA_START_HIGH 1 1923 #define PCIC_SIA_STOP_LOW 2 1924 #define PCIC_SIA_STOP_HIGH 3 1925 1926 int regbase_win = 0x8 + win*0x04; 1927 u_int8_t ioctl, enable; 1928 1929 DPRINTF(("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx width %d\n", 1930 win, (long) ph->io[win].addr, (long) ph->io[win].size, 1931 ph->io[win].width * 8)); 1932 1933 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 1934 ph->io[win].addr & 0xff); 1935 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 1936 (ph->io[win].addr >> 8) & 0xff); 1937 1938 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 1939 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 1940 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 1941 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 1942 1943 ioctl = Pcic_read(ph, PCIC_IOCTL); 1944 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 1945 switch (win) { 1946 case 0: 1947 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 1948 PCIC_IOCTL_IO0_IOCS16SRC_MASK | PCIC_IOCTL_IO0_DATASIZE_MASK); 1949 ioctl |= pcic_iowidth[ph->io[win].width]; 1950 enable |= PCIC_ADDRWIN_ENABLE_IO0; 1951 break; 1952 case 1: 1953 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 1954 PCIC_IOCTL_IO1_IOCS16SRC_MASK | PCIC_IOCTL_IO1_DATASIZE_MASK); 1955 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 1956 enable |= PCIC_ADDRWIN_ENABLE_IO1; 1957 break; 1958 } 1959 Pcic_write(ph, PCIC_IOCTL, ioctl); 1960 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 1961 #if defined CBB_DEBUG 1962 { 1963 u_int8_t start_low = Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 1964 u_int8_t start_high = Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 1965 u_int8_t stop_low = Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 1966 u_int8_t stop_high = Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 1967 printf(" start %02x %02x, stop %02x %02x, ioctl %02x enable %02x\n", 1968 start_low, start_high, stop_low, stop_high, ioctl, enable); 1969 } 1970 #endif 1971 } 1972 1973 1974 1975 /* 1976 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 1977 * 1978 * This function unmapss I/O region. No return value. 1979 */ 1980 STATIC void 1981 pccbb_pcmcia_io_unmap(pch, win) 1982 pcmcia_chipset_handle_t pch; 1983 int win; 1984 { 1985 struct pcic_handle *ph = (struct pcic_handle *)pch; 1986 int reg; 1987 1988 if (win >= PCIC_IO_WINS || win < 0) { 1989 panic("pccbb_pcmcia_io_unmap: window out of range"); 1990 } 1991 1992 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 1993 switch (win) { 1994 case 0: 1995 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 1996 break; 1997 case 1: 1998 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 1999 break; 2000 } 2001 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2002 2003 ph->ioalloc &= ~(1 << win); 2004 } 2005 2006 2007 2008 2009 2010 /* 2011 * static void pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 2012 * 2013 * This function enables the card. All information is stored in 2014 * the first argument, pcmcia_chipset_handle_t. 2015 */ 2016 static void 2017 pccbb_pcmcia_wait_ready(ph) 2018 struct pcic_handle *ph; 2019 { 2020 int i; 2021 2022 DPRINTF(("pccbb_pcmcia_wait_ready: status 0x%02x\n", 2023 Pcic_read(ph, PCIC_IF_STATUS))); 2024 2025 for (i = 0; i < 10000; i++) { 2026 if (Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) { 2027 return; 2028 } 2029 delay(500); 2030 #ifdef CBB_DEBUG 2031 if ((i > 5000) && (i%100 == 99)) 2032 printf("."); 2033 #endif 2034 } 2035 2036 #ifdef DIAGNOSTIC 2037 printf("pcic_wait_ready: ready never happened, status = %02x\n", 2038 Pcic_read(ph, PCIC_IF_STATUS)); 2039 #endif 2040 } 2041 2042 2043 2044 /* 2045 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2046 * 2047 * This function enables the card. All information is stored in 2048 * the first argument, pcmcia_chipset_handle_t. 2049 */ 2050 STATIC void 2051 pccbb_pcmcia_socket_enable(pch) 2052 pcmcia_chipset_handle_t pch; 2053 { 2054 struct pcic_handle *ph = (struct pcic_handle *)pch; 2055 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2056 int cardtype, win; 2057 u_int8_t power, intr; 2058 pcireg_t spsr; 2059 int voltage; 2060 #define PCIC_INTR_PCI PCIC_INTR_ENABLE 2061 2062 /* this bit is mostly stolen from pcic_attach_card */ 2063 2064 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2065 2066 /* get card Vcc info */ 2067 2068 spsr = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_STAT); 2069 if (spsr & CB_SOCKET_STAT_5VCARD) { 2070 DPRINTF(("5V card\n")); 2071 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2072 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2073 DPRINTF(("3V card\n")); 2074 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2075 } else { 2076 printf("?V card, 0x%x\n", spsr); /* XXX */ 2077 return; 2078 } 2079 2080 /* assert reset bit */ 2081 2082 intr = Pcic_read(ph, PCIC_INTR); 2083 intr &= ~PCIC_INTR_RESET; 2084 intr |= PCIC_INTR_PCI; /* XXX */ 2085 Pcic_write(ph, PCIC_INTR, intr); 2086 2087 /* disable socket i/o: negate output enable bit */ 2088 2089 power = Pcic_read(ph, PCIC_PWRCTL); 2090 power &= ~PCIC_PWRCTL_OE; 2091 Pcic_write(ph, PCIC_PWRCTL, power); 2092 2093 /* power down the socket to reset it, clear the card reset pin */ 2094 2095 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2096 2097 /* 2098 * wait 200ms until power fails (Tpf). Then, wait 100ms since 2099 * we are changing Vcc (Toff). 2100 */ 2101 /* delay(300*1000); too much */ 2102 2103 /* power up the socket */ 2104 pccbb_power(sc, voltage); 2105 2106 /* 2107 * wait 100ms until power raise (Tpr) and 20ms to become 2108 * stable (Tsu(Vcc)). 2109 * 2110 * some machines require some more time to be settled 2111 * (another 200ms is added here). 2112 */ 2113 /* delay((100 + 20 + 200)*1000); too much */ 2114 2115 power = Pcic_read(ph, PCIC_PWRCTL); 2116 Pcic_write(ph, PCIC_PWRCTL, power | PCIC_PWRCTL_OE); 2117 2118 /* 2119 * hold RESET at least 10us. 2120 */ 2121 delay(10); 2122 delay(2*1000); /* XXX: TI1130 requires it. */ 2123 delay(20*1000); /* XXX: TI1130 requires it. */ 2124 2125 /* clear the reset flag */ 2126 2127 intr = Pcic_read(ph, PCIC_INTR); 2128 Pcic_write(ph, PCIC_INTR, intr | PCIC_INTR_RESET); 2129 2130 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 2131 2132 delay(20000); 2133 2134 /* wait for the chip to finish initializing */ 2135 2136 pccbb_pcmcia_wait_ready(ph); 2137 2138 /* zero out the address windows */ 2139 2140 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2141 2142 /* set the card type */ 2143 2144 cardtype = pcmcia_card_gettype(ph->pcmcia); 2145 2146 intr = Pcic_read(ph, PCIC_INTR); 2147 intr &= ~PCIC_INTR_CARDTYPE_MASK; 2148 intr |= ((cardtype == PCMCIA_IFTYPE_IO) ? 2149 PCIC_INTR_CARDTYPE_IO : 2150 PCIC_INTR_CARDTYPE_MEM); 2151 Pcic_write(ph, PCIC_INTR, intr); 2152 2153 DPRINTF(("%s: pccbb_pcmcia_socket_enable %02x cardtype %s %02x\n", 2154 ph->ph_parent->dv_xname, ph->sock, 2155 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2156 2157 /* reinstall all the memory and io mappings */ 2158 2159 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2160 if (ph->memalloc & (1 << win)) { 2161 pccbb_pcmcia_do_mem_map(ph, win); 2162 } 2163 } 2164 2165 for (win = 0; win < PCIC_IO_WINS; ++win) { 2166 if (ph->ioalloc & (1 << win)) { 2167 pccbb_pcmcia_do_io_map(ph, win); 2168 } 2169 } 2170 } 2171 2172 2173 2174 /* 2175 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2176 * 2177 * This function disables the card. All information is stored in 2178 * the first argument, pcmcia_chipset_handle_t. 2179 */ 2180 STATIC void 2181 pccbb_pcmcia_socket_disable(pch) 2182 pcmcia_chipset_handle_t pch; 2183 { 2184 struct pcic_handle *ph = (struct pcic_handle *)pch; 2185 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2186 u_int8_t power, intr; 2187 2188 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2189 2190 /* reset signal asserting... */ 2191 2192 intr = Pcic_read(ph, PCIC_INTR); 2193 intr &= ~PCIC_INTR_RESET; 2194 Pcic_write(ph, PCIC_INTR, intr); 2195 delay(2*1000); 2196 2197 /* power down the socket */ 2198 power = Pcic_read(ph, PCIC_PWRCTL); 2199 power &= ~PCIC_PWRCTL_OE; 2200 Pcic_write(ph, PCIC_PWRCTL, power); 2201 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2202 /* 2203 * wait 300ms until power fails (Tpf). 2204 */ 2205 delay(300 * 1000); 2206 } 2207 2208 2209 2210 /* 2211 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2212 * 2213 * This function detects whether a card is in the slot or not. 2214 * If a card is inserted, return 1. Otherwise, return 0. 2215 */ 2216 STATIC int 2217 pccbb_pcmcia_card_detect(pch) 2218 pcmcia_chipset_handle_t pch; 2219 { 2220 struct pcic_handle *ph = (struct pcic_handle *)pch; 2221 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2222 2223 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2224 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2225 } 2226 2227 2228 2229 #if 0 2230 STATIC int 2231 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2232 bus_addr_t start, bus_size_t size, 2233 bus_size_t align, 2234 int speed, int flags, /* bus width */ 2235 bus_space_tag_t *memtp 2236 bus_space_handle_t *memhp) 2237 #endif 2238 2239 2240 /* 2241 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2242 * bus_size_t size, 2243 * struct pcmcia_mem_handle *pcmhp) 2244 * 2245 * This function only allocates memory region for pccard. This 2246 * function never maps the allcated region to pccard memory area. 2247 * 2248 * XXX: Why the argument of start address is not in? 2249 */ 2250 STATIC int 2251 pccbb_pcmcia_mem_alloc(pch, size, pcmhp) 2252 pcmcia_chipset_handle_t pch; 2253 bus_size_t size; 2254 struct pcmcia_mem_handle *pcmhp; 2255 { 2256 struct pcic_handle *ph = (struct pcic_handle *)pch; 2257 bus_space_handle_t memh; 2258 bus_addr_t addr; 2259 bus_size_t sizepg; 2260 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2261 #if rbus 2262 rbus_tag_t rb; 2263 #endif 2264 2265 /* out of sc->memh, allocate as many pages as necessary */ 2266 2267 /* convert size to PCIC pages */ 2268 /* 2269 This is not enough; when the requested region is on the 2270 page boundaries, this may calculate wrong result. 2271 */ 2272 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2273 #if 0 2274 if (sizepg > PCIC_MAX_MEM_PAGES) { 2275 return 1; 2276 } 2277 #endif 2278 2279 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2280 return 1; 2281 } 2282 2283 addr = 0; /* XXX gcc -Wuninitialized */ 2284 2285 #if rbus 2286 rb = sc->sc_rbus_memt; 2287 if (rbus_space_alloc(rb, 0, sizepg*PCIC_MEM_PAGESIZE, 2288 sizepg*PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 2289 0, &addr, &memh)) { 2290 return 1; 2291 } 2292 2293 #else 2294 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2295 sizepg*PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2296 0 /* boundary */, 0 /* flags */, 2297 &addr, &memh)) { 2298 return 1; 2299 } 2300 #endif 2301 2302 DPRINTF(("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, realsize 0x%lx\n", 2303 addr, size, sizepg*PCIC_MEM_PAGESIZE)); 2304 2305 pcmhp->memt = sc->sc_memt; 2306 pcmhp->memh = memh; 2307 pcmhp->addr = addr; 2308 pcmhp->size = size; 2309 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2310 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2311 pcmhp->mhandle = 0; 2312 /* No offset??? Funny. */ 2313 2314 return 0; 2315 } 2316 2317 2318 2319 2320 /* 2321 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2322 * struct pcmcia_mem_handle *pcmhp) 2323 * 2324 * This function release the memory space allocated by the fuction 2325 * pccbb_pcmcia_mem_alloc(). 2326 */ 2327 STATIC void 2328 pccbb_pcmcia_mem_free(pch, pcmhp) 2329 pcmcia_chipset_handle_t pch; 2330 struct pcmcia_mem_handle *pcmhp; 2331 { 2332 #if rbus 2333 struct pcic_handle *ph = (struct pcic_handle *)pch; 2334 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2335 2336 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2337 #else 2338 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2339 #endif 2340 } 2341 2342 2343 2344 2345 /* 2346 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2347 * 2348 * This function release the memory space allocated by the fuction 2349 * pccbb_pcmcia_mem_alloc(). 2350 */ 2351 STATIC void 2352 pccbb_pcmcia_do_mem_map(ph, win) 2353 struct pcic_handle *ph; 2354 int win; 2355 { 2356 int regbase_win; 2357 bus_addr_t phys_addr; 2358 bus_addr_t phys_end; 2359 2360 #define PCIC_SMM_START_LOW 0 2361 #define PCIC_SMM_START_HIGH 1 2362 #define PCIC_SMM_STOP_LOW 2 2363 #define PCIC_SMM_STOP_HIGH 3 2364 #define PCIC_CMA_LOW 4 2365 #define PCIC_CMA_HIGH 5 2366 2367 u_int8_t start_low, start_high = 0; 2368 u_int8_t stop_low, stop_high; 2369 u_int8_t off_low, off_high; 2370 u_int8_t mem_window; 2371 int reg; 2372 2373 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2374 int mem8 = (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8; 2375 2376 regbase_win = 0x10 + win*0x08; 2377 2378 phys_addr = ph->mem[win].addr; 2379 phys_end = phys_addr + ph->mem[win].size; 2380 2381 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2382 phys_addr, phys_end, ph->mem[win].offset)); 2383 2384 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2385 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2386 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2387 2388 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; /* bit 19:12 */ 2389 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) /* bit 23:20 */ 2390 | mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT; /* bit 7 on */ 2391 /* bit 31:24, for 32-bit address */ 2392 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; /* bit 31:24 */ 2393 2394 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2395 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2396 2397 if (((struct pccbb_softc *)ph->ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2398 Pcic_write(ph, 0x40 + win, mem_window); 2399 } 2400 2401 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2402 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2403 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2404 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2405 2406 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2407 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2408 2409 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2410 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2411 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2412 | ((kind == PCMCIA_MEM_ATTR) ? 2413 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2414 2415 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2416 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2417 2418 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2419 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2420 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2421 2422 #if defined CBB_DEBUG 2423 { 2424 int r1, r2, r3, r4, r5, r6, r7 = 0; 2425 2426 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2427 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2428 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2429 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2430 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2431 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2432 if (((struct pccbb_softc *)(ph->ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2433 r7 = Pcic_read(ph, 0x40 + win); 2434 } 2435 2436 DPRINTF(("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2437 "%02x%02x", win, r1, r2, r3, r4, r5, r6)); 2438 if (((struct pccbb_softc *)(ph->ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2439 DPRINTF((" %02x",r7)); 2440 } 2441 DPRINTF(("\n")); 2442 } 2443 #endif 2444 } 2445 2446 2447 2448 2449 /* 2450 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2451 * bus_addr_t card_addr, bus_size_t size, 2452 * struct pcmcia_mem_handle *pcmhp, 2453 * bus_addr_t *offsetp, int *windowp) 2454 * 2455 * This function maps memory space allocated by the fuction 2456 * pccbb_pcmcia_mem_alloc(). 2457 */ 2458 STATIC int 2459 pccbb_pcmcia_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 2460 pcmcia_chipset_handle_t pch; 2461 int kind; 2462 bus_addr_t card_addr; 2463 bus_size_t size; 2464 struct pcmcia_mem_handle *pcmhp; 2465 bus_addr_t *offsetp; 2466 int *windowp; 2467 { 2468 struct pcic_handle *ph = (struct pcic_handle *)pch; 2469 bus_addr_t busaddr; 2470 long card_offset; 2471 int win; 2472 2473 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2474 if ((ph->memalloc & (1 << win)) == 0) { 2475 ph->memalloc |= (1 << win); 2476 break; 2477 } 2478 } 2479 2480 if (win == PCIC_MEM_WINS) { 2481 return 1; 2482 } 2483 2484 *windowp = win; 2485 2486 /* XXX this is pretty gross */ 2487 2488 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2489 panic("pccbb_pcmcia_mem_map memt is bogus"); 2490 } 2491 2492 busaddr = pcmhp->addr; 2493 2494 /* 2495 * compute the address offset to the pcmcia address space for the 2496 * pcic. this is intentionally signed. The masks and shifts below 2497 * will cause TRT to happen in the pcic registers. Deal with making 2498 * sure the address is aligned, and return the alignment offset. 2499 */ 2500 2501 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2502 card_addr -= *offsetp; 2503 2504 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2505 "%lx\n", win, (u_long)busaddr, (u_long)*offsetp, (u_long)size, 2506 (u_long)card_addr)); 2507 2508 /* 2509 * include the offset in the size, and decrement size by one, since 2510 * the hw wants start/stop 2511 */ 2512 size += *offsetp - 1; 2513 2514 card_offset = (((long) card_addr) - ((long) busaddr)); 2515 2516 ph->mem[win].addr = busaddr; 2517 ph->mem[win].size = size; 2518 ph->mem[win].offset = card_offset; 2519 ph->mem[win].kind = kind; 2520 2521 pccbb_pcmcia_do_mem_map(ph, win); 2522 2523 return 0; 2524 } 2525 2526 2527 2528 /* 2529 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2530 * int window) 2531 * 2532 * This function unmaps memory space which mapped by the fuction 2533 * pccbb_pcmcia_mem_map(). 2534 */ 2535 STATIC void 2536 pccbb_pcmcia_mem_unmap(pch, window) 2537 pcmcia_chipset_handle_t pch; 2538 int window; 2539 { 2540 struct pcic_handle *ph = (struct pcic_handle *)pch; 2541 int reg; 2542 2543 if (window >= PCIC_MEM_WINS) { 2544 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2545 } 2546 2547 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2548 reg &= ~(1 << window); 2549 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2550 2551 ph->memalloc &= ~(1 << window); 2552 } 2553 2554 2555 2556 #if defined PCCBB_PCMCIA_POLL 2557 struct pccbb_poll_str { 2558 void *arg; 2559 int (* func) __P((void *)); 2560 int level; 2561 struct pcic_handle *ph; 2562 int count; 2563 int num; 2564 }; 2565 2566 static struct pccbb_poll_str pccbb_poll[10]; 2567 static int pccbb_poll_n = 0; 2568 2569 static void pccbb_pcmcia_poll __P((void *arg)); 2570 2571 static void 2572 pccbb_pcmcia_poll(arg) 2573 void *arg; 2574 { 2575 struct pccbb_poll_str *poll = arg; 2576 struct pcic_handle *ph = poll->ph; 2577 struct pccbb_softc *sc = ph->sc; 2578 int s; 2579 u_int32_t spsr; /* socket present-state reg */ 2580 2581 timeout(pccbb_pcmcia_poll, arg, hz*2); 2582 switch (poll->level) { 2583 case IPL_NET: 2584 s = splnet(); 2585 break; 2586 case IPL_BIO: 2587 s = splbio(); 2588 break; 2589 case IPL_TTY: /* fallthrough */ 2590 default: 2591 s = spltty(); 2592 break; 2593 } 2594 2595 spsr = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_STAT); 2596 2597 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2598 if (!(spsr & 0x40)) /* CINT low */ 2599 #else 2600 if (1) 2601 #endif 2602 { 2603 if ((*poll->func)(poll->arg) > 0) { 2604 ++poll->count; 2605 // printf("intr: reported from poller, 0x%x\n", spsr); 2606 #if defined LEVEL2 2607 } else { 2608 printf("intr: miss! 0x%x\n", spsr); 2609 #endif 2610 } 2611 } 2612 splx(s); 2613 } 2614 #endif /* defined CB_PCMCIA_POLL */ 2615 2616 2617 2618 /* 2619 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2620 * struct pcmcia_function *pf, 2621 * int ipl, 2622 * int (*func)(void *), 2623 * void *arg); 2624 * 2625 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2626 */ 2627 STATIC void * 2628 pccbb_pcmcia_intr_establish(pch, pf, ipl, func, arg) 2629 pcmcia_chipset_handle_t pch; 2630 struct pcmcia_function *pf; 2631 int ipl; 2632 int (*func) __P((void *)); 2633 void *arg; 2634 { 2635 struct pcic_handle *ph = (struct pcic_handle *)pch; 2636 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2637 pci_intr_handle_t handle; 2638 void *ih; 2639 2640 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2641 /* what should I do? */ 2642 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2643 DPRINTF(("%s does not provide edge nor pulse interrupt\n", 2644 sc->sc_dev.dv_xname)); 2645 return NULL; 2646 } 2647 /* 2648 * XXX Noooooo! The interrupt flag must set properly!! 2649 * dumb pcmcia driver!! 2650 */ 2651 } 2652 2653 if (pci_intr_map(sc->sc_pc, sc->sc_intrtag, sc->sc_intrpin, 2654 sc->sc_intrline, &handle)) { 2655 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 2656 return NULL; 2657 } 2658 DPRINTF(("pccbb_pcmcia_intr_establish: line %d, handle %d\n", 2659 sc->sc_intrline, handle)); 2660 2661 if (NULL != (ih = pci_intr_establish(sc->sc_pc, handle, ipl, func, arg))) 2662 { 2663 u_int32_t cbctrl; 2664 2665 if ((CB_TI113X == sc->sc_chipset)) { 2666 cbctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 2667 cbctrl |= PCI113X_CBCTRL_PCI_INTR; /* PCI functional intr req */ 2668 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, cbctrl); 2669 } 2670 } 2671 #if defined PCCBB_PCMCIA_POLL 2672 if (pccbb_poll_n < 10) { 2673 pccbb_poll[pccbb_poll_n].arg = arg; 2674 pccbb_poll[pccbb_poll_n].func = func; 2675 pccbb_poll[pccbb_poll_n].level = ipl; 2676 pccbb_poll[pccbb_poll_n].count = 0; 2677 pccbb_poll[pccbb_poll_n].num = pccbb_poll_n; 2678 pccbb_poll[pccbb_poll_n].ph = ph; 2679 timeout(pccbb_pcmcia_poll, &pccbb_poll[pccbb_poll_n++], hz*2); 2680 printf("polling set\n"); 2681 } 2682 #endif 2683 #if defined SHOW_REGS 2684 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, sc->sc_base_memh); 2685 #endif 2686 2687 return ih; 2688 } 2689 2690 2691 2692 2693 /* 2694 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2695 * void *ih) 2696 * 2697 * This function disables PC-Card interrupt. 2698 */ 2699 STATIC void 2700 pccbb_pcmcia_intr_disestablish(pch, ih) 2701 pcmcia_chipset_handle_t pch; 2702 void *ih; 2703 { 2704 struct pcic_handle *ph = (struct pcic_handle *)pch; 2705 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2706 2707 pci_intr_disestablish(sc->sc_pc, ih); 2708 } 2709 2710 2711 2712 2713 #if rbus 2714 /* 2715 * static int 2716 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2717 * bus_addr_t addr, bus_size_t size, 2718 * bus_addr_t mask, bus_size_t align, 2719 * int flags, bus_addr_t *addrp; 2720 * bus_space_handle_t *bshp) 2721 * 2722 * This function allocates a portion of memory or io space for 2723 * clients. This function is called from CardBus card drivers. 2724 */ 2725 static int 2726 pccbb_rbus_cb_space_alloc(ct, rb, addr, size, mask, align, flags, addrp, bshp) 2727 cardbus_chipset_tag_t ct; 2728 rbus_tag_t rb; 2729 bus_addr_t addr; 2730 bus_size_t size; 2731 bus_addr_t mask; 2732 bus_size_t align; 2733 int flags; 2734 bus_addr_t *addrp; 2735 bus_space_handle_t *bshp; 2736 { 2737 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2738 2739 DPRINTF(("pccbb_rbus_cb_space_alloc: adr %lx, size %lx, mask %lx, align %lx\n", addr, size, mask, align)); 2740 2741 if (align == 0) { 2742 align = size; 2743 } 2744 2745 if (rb->rb_bt == sc->sc_memt) { 2746 if (align < 16) { 2747 return 1; 2748 } 2749 } else if (rb->rb_bt == sc->sc_iot) { 2750 if (align < 4) { 2751 return 1; 2752 } 2753 } else { 2754 DPRINTF(("pccbb_rbus_cb_space_alloc: Bus space tag %x is NOT used.\n", 2755 rb->rb_bt)); 2756 return 1; 2757 /* XXX: panic here? */ 2758 } 2759 2760 /* XXX: hack for avoiding ISA image */ 2761 if (mask < 0x3ff) { 2762 mask = 0x3ff; 2763 addr = 0x300; 2764 } 2765 2766 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 2767 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 2768 return 1; 2769 } 2770 2771 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 2772 2773 return 0; 2774 } 2775 2776 2777 2778 2779 2780 /* 2781 * static int 2782 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 2783 * bus_space_handle_t *bshp, bus_size_t size); 2784 * 2785 * This function is called from CardBus card drivers. 2786 */ 2787 static int 2788 pccbb_rbus_cb_space_free(ct, rb, bsh, size) 2789 cardbus_chipset_tag_t ct; 2790 rbus_tag_t rb; 2791 bus_space_handle_t bsh; 2792 bus_size_t size; 2793 { 2794 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2795 bus_space_tag_t bt = rb->rb_bt; 2796 2797 pccbb_close_win(sc, bt, bsh, size); 2798 2799 if (bt == sc->sc_memt) { 2800 } else if (bt == sc->sc_iot) { 2801 } else { 2802 return 1; 2803 /* XXX: panic here? */ 2804 } 2805 2806 return rbus_space_free(rb, bsh, size, NULL); 2807 } 2808 #endif /* rbus */ 2809 2810 2811 #if rbus 2812 2813 static int 2814 pccbb_open_win(sc, bst, addr, size, bsh, flags) 2815 struct pccbb_softc *sc; 2816 bus_space_tag_t bst; 2817 bus_addr_t addr; 2818 bus_size_t size; 2819 bus_space_handle_t bsh; 2820 int flags; 2821 { 2822 struct pccbb_win_chain **top; 2823 bus_addr_t align; 2824 2825 top = &sc->sc_iowindow; 2826 align = 0x04; 2827 if (sc->sc_memt == bst) { 2828 top = &sc->sc_memwindow; 2829 align = 0x1000; 2830 DPRINTF(("using memory window, %x %x %x\n\n", 2831 sc->sc_iot, sc->sc_memt, bst)); 2832 } 2833 2834 if (pccbb_winlist_insert(top, addr, size, bsh, flags)) { 2835 printf("winlist insert fails:\n"); 2836 } 2837 pccbb_winset(align, sc, bst); 2838 2839 return 0; 2840 } 2841 2842 2843 2844 static int 2845 pccbb_close_win(sc, bst, bsh, size) 2846 struct pccbb_softc *sc; 2847 bus_space_tag_t bst; 2848 bus_space_handle_t bsh; 2849 bus_size_t size; 2850 { 2851 struct pccbb_win_chain **top; 2852 bus_addr_t align; 2853 2854 top = &sc->sc_iowindow; 2855 align = 0x04; 2856 if (sc->sc_memt == bst) { 2857 top = &sc->sc_memwindow; 2858 align = 0x1000; 2859 } 2860 2861 if (pccbb_winlist_delete(top, bsh, size)) { 2862 printf("winlist delete fails:\n"); 2863 } 2864 pccbb_winset(align, sc, bst); 2865 2866 return 0; 2867 } 2868 2869 2870 static int 2871 pccbb_winlist_insert(top, start, size, bsh, flags) 2872 struct pccbb_win_chain **top; 2873 bus_addr_t start; 2874 bus_size_t size; 2875 bus_space_handle_t bsh; 2876 int flags; 2877 { 2878 struct pccbb_win_chain *chainp = *top; 2879 struct pccbb_win_chain *before = *top; 2880 struct pccbb_win_chain *elem; 2881 2882 if (*top == NULL) { 2883 if (NULL == (elem = (struct pccbb_win_chain *)malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, M_NOWAIT))) { 2884 return 1; /* fail */ 2885 } 2886 2887 elem->wc_start = start; 2888 elem->wc_end = start + size - 1; 2889 elem->wc_handle = bsh; 2890 elem->wc_flags = flags; 2891 2892 *top = elem; 2893 elem->wc_next = NULL; 2894 return 0; 2895 } 2896 2897 for(; chainp && chainp->wc_start <= start; chainp = chainp->wc_next) { 2898 before = chainp; 2899 } 2900 2901 if (chainp != NULL) { 2902 if (chainp->wc_start < start + size) { 2903 printf("fatal! 0x%lx 0x%lx\n", chainp->wc_start, start+size); 2904 return 1; 2905 } 2906 } 2907 if ((before != *top) && (before->wc_end >= start)) { 2908 printf("fatal!! 0x%lx 0x%lx\n", before->wc_end, start); 2909 return 1; 2910 } 2911 2912 if (NULL == (elem = (struct pccbb_win_chain *)malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, M_NOWAIT))) { 2913 return 1; /* fail */ 2914 } 2915 2916 elem->wc_start = start; 2917 elem->wc_end = start + size - 1; 2918 elem->wc_handle = bsh; 2919 elem->wc_flags = flags; 2920 2921 elem->wc_next = chainp; 2922 if (chainp == *top) { 2923 *top = elem; 2924 } else { 2925 before->wc_next = elem; 2926 } 2927 return 0; 2928 } 2929 2930 2931 2932 2933 static int 2934 pccbb_winlist_delete(top, bsh, size) 2935 struct pccbb_win_chain **top; 2936 bus_space_handle_t bsh; 2937 bus_size_t size; 2938 { 2939 struct pccbb_win_chain *chainp = *top; 2940 struct pccbb_win_chain **before = top; 2941 2942 for (; chainp && chainp->wc_handle != bsh; chainp = chainp->wc_next) { 2943 before = &chainp->wc_next; 2944 } 2945 2946 if (chainp == NULL) { 2947 return 1; /* fail: no candidate to remove */ 2948 } 2949 2950 if (chainp->wc_end - chainp->wc_start != size - 1) { 2951 printf("fatal!!! 0x%lx\n", chainp->wc_start); 2952 return 1; /* fail: no candidate to remove */ 2953 } 2954 2955 *before = chainp->wc_next; 2956 free(chainp, M_DEVBUF); 2957 2958 return 0; 2959 } 2960 2961 2962 2963 static void 2964 pccbb_winset(align, sc, bst) 2965 bus_addr_t align; 2966 struct pccbb_softc *sc; 2967 bus_space_tag_t bst; 2968 { 2969 pci_chipset_tag_t pc; 2970 pcitag_t tag; 2971 bus_addr_t mask = ~(align - 1); 2972 struct { 2973 cardbusreg_t win_start; 2974 cardbusreg_t win_limit; 2975 int win_flags; 2976 } win[2]; 2977 struct pccbb_win_chain *chainp; 2978 int offs; 2979 2980 win[0].win_start = 0xffffffff; 2981 win[0].win_limit = 0; 2982 win[1].win_start = 0xffffffff; 2983 win[1].win_limit = 0; 2984 2985 chainp = sc->sc_iowindow; 2986 offs = 0x2c; 2987 if (sc->sc_memt == bst) { 2988 chainp = sc->sc_memwindow; 2989 offs = 0x1c; 2990 } 2991 2992 if (chainp) { 2993 win[0].win_start = chainp->wc_start & mask; 2994 win[0].win_limit = chainp->wc_end & mask; 2995 win[0].win_flags = chainp->wc_flags; 2996 chainp = chainp->wc_next; 2997 } 2998 2999 for(; chainp; chainp = chainp->wc_next) { 3000 if (win[1].win_start == 0xffffffff) { 3001 /* window 1 is not used */ 3002 if ((win[0].win_flags == chainp->wc_flags) && 3003 (win[0].win_limit + align >= (chainp->wc_start & mask))) { 3004 /* concatinate */ 3005 win[0].win_limit = chainp->wc_end & mask; 3006 } else { 3007 /* make new window */ 3008 win[1].win_start = chainp->wc_start & mask; 3009 win[1].win_limit = chainp->wc_end & mask; 3010 win[1].win_flags = chainp->wc_flags; 3011 } 3012 continue; 3013 } 3014 3015 /* Both windows are engagad. */ 3016 if (win[0].win_flags == win[1].win_flags) { 3017 /* same flags */ 3018 if (win[0].win_flags == chainp->wc_flags) { 3019 if (win[1].win_start - (win[0].win_limit + align) 3020 < (chainp->wc_start & mask) - ((chainp->wc_end & mask) + align)) { 3021 /* merge window 0 and 1, and set win1 to chainp */ 3022 win[0].win_limit = win[1].win_limit; 3023 win[1].win_start = chainp->wc_start & mask; 3024 win[1].win_limit = chainp->wc_end & mask; 3025 } else { 3026 win[1].win_limit = chainp->wc_end & mask; 3027 } 3028 } else { 3029 /* different flags */ 3030 3031 /* concatinate win0 and win1 */ 3032 win[0].win_limit = win[1].win_limit; 3033 /* allocate win[1] to new space */ 3034 win[1].win_start = chainp->wc_start & mask; 3035 win[1].win_limit = chainp->wc_end & mask; 3036 win[1].win_flags = chainp->wc_flags; 3037 } 3038 } else { 3039 /* the flags of win[0] and win[1] is different */ 3040 if (win[0].win_flags == chainp->wc_flags) { 3041 win[0].win_limit = chainp->wc_end & mask; 3042 /* XXX this creates overlapping windows, so what should the 3043 poor bridge do if one is cachable, and the other is not? */ 3044 printf("%s: overlapping windows\n", sc->sc_dev.dv_xname); 3045 } else { 3046 win[1].win_limit = chainp->wc_end & mask; 3047 } 3048 } 3049 } 3050 3051 pc = sc->sc_pc; 3052 tag = sc->sc_tag; 3053 pci_conf_write(pc, tag, offs, win[0].win_start); 3054 pci_conf_write(pc, tag, offs+4, win[0].win_limit); 3055 pci_conf_write(pc, tag, offs+8, win[1].win_start); 3056 pci_conf_write(pc, tag, offs+12, win[1].win_limit); 3057 DPRINTF(("--pccbb_winset: win0 [%x, %lx), win1 [%x, %lx)\n", 3058 pci_conf_read(pc, tag, offs), 3059 pci_conf_read(pc, tag, offs+4) + align, 3060 pci_conf_read(pc, tag, offs+8), 3061 pci_conf_read(pc, tag, offs+12) + align)); 3062 3063 if (bst == sc->sc_memt) { 3064 if (win[0].win_flags & PCCBB_MEM_CACHABLE) { 3065 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3066 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3067 pci_conf_write(pc,tag, PCI_BCR_INTR, bcr); 3068 } 3069 if (win[1].win_flags & PCCBB_MEM_CACHABLE) { 3070 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3071 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3072 pci_conf_write(pc,tag, PCI_BCR_INTR, bcr); 3073 } 3074 } 3075 } 3076 3077 #endif /* rbus */ 3078
Indexes created Fri Sep 26 20:09:58 GMT 2025