pccbb.c revision 1.141
1 /* $NetBSD: pccbb.c,v 1.141 2007/02/04 04:59:39 dyoung Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: pccbb.c,v 1.141 2007/02/04 04:59:39 dyoung Exp $"); 35 36 /* 37 #define CBB_DEBUG 38 #define SHOW_REGS 39 */ 40 41 /* 42 * BROKEN! 43 #define PCCBB_PCMCIA_POLL 44 #define CB_PCMCIA_POLL 45 #define CB_PCMCIA_POLL_ONLY 46 #define LEVEL2 47 */ 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/kernel.h> 52 #include <sys/errno.h> 53 #include <sys/ioctl.h> 54 #include <sys/reboot.h> /* for bootverbose */ 55 #include <sys/syslog.h> 56 #include <sys/device.h> 57 #include <sys/malloc.h> 58 #include <sys/proc.h> 59 60 #include <machine/intr.h> 61 #include <machine/bus.h> 62 63 #include <dev/pci/pcivar.h> 64 #include <dev/pci/pcireg.h> 65 #include <dev/pci/pcidevs.h> 66 67 #include <dev/pci/pccbbreg.h> 68 69 #include <dev/cardbus/cardslotvar.h> 70 71 #include <dev/cardbus/cardbusvar.h> 72 73 #include <dev/pcmcia/pcmciareg.h> 74 #include <dev/pcmcia/pcmciavar.h> 75 76 #include <dev/ic/i82365reg.h> 77 #include <dev/ic/i82365var.h> 78 #include <dev/pci/pccbbvar.h> 79 80 #include "locators.h" 81 82 #if defined(__i386__) 83 #include "ioapic.h" 84 #include "acpi.h" 85 #endif 86 87 #ifndef __NetBSD_Version__ 88 struct cfdriver cbb_cd = { 89 NULL, "cbb", DV_DULL 90 }; 91 #endif 92 93 #ifdef CBB_DEBUG 94 #define DPRINTF(x) printf x 95 #define STATIC 96 #else 97 #define DPRINTF(x) 98 #define STATIC static 99 #endif 100 101 /* 102 * DELAY_MS() is wait in milliseconds. It should be used instead 103 * of delay() if you want to wait more than 1 ms. 104 */ 105 #define DELAY_MS(time, param) \ 106 do { \ 107 if (cold == 0) { \ 108 int xtick = (hz*(time))/1000; \ 109 \ 110 if (xtick <= 1) { \ 111 xtick = 2; \ 112 } \ 113 tsleep((void *)(param), PWAIT, "pccbb", xtick); \ 114 } else { \ 115 delay((time)*1000); \ 116 } \ 117 } while (/*CONSTCOND*/0) 118 119 int pcicbbmatch(struct device *, struct cfdata *, void *); 120 void pccbbattach(struct device *, struct device *, void *); 121 int pccbbintr(void *); 122 static void pci113x_insert(void *); 123 static int pccbbintr_function(struct pccbb_softc *); 124 125 static int pccbb_detect_card(struct pccbb_softc *); 126 127 static void pccbb_pcmcia_write(struct pcic_handle *, int, u_int8_t); 128 static u_int8_t pccbb_pcmcia_read(struct pcic_handle *, int); 129 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 130 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 131 132 STATIC int cb_reset(struct pccbb_softc *); 133 STATIC int cb_detect_voltage(struct pccbb_softc *); 134 STATIC int cbbprint(void *, const char *); 135 136 static int cb_chipset(u_int32_t, int *); 137 STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *, 138 struct pcmciabus_attach_args *); 139 #if 0 140 STATIC void pccbb_pcmcia_attach_card(struct pcic_handle *); 141 STATIC void pccbb_pcmcia_detach_card(struct pcic_handle *, int); 142 STATIC void pccbb_pcmcia_deactivate_card(struct pcic_handle *); 143 #endif 144 145 STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int); 146 STATIC int pccbb_power(cardbus_chipset_tag_t, int); 147 STATIC int pccbb_cardenable(struct pccbb_softc * sc, int function); 148 #if !rbus 149 static int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 150 static int pccbb_io_close(cardbus_chipset_tag_t, int); 151 static int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 152 static int pccbb_mem_close(cardbus_chipset_tag_t, int); 153 #endif /* !rbus */ 154 static void *pccbb_intr_establish(struct pccbb_softc *, int irq, 155 int level, int (*ih) (void *), void *sc); 156 static void pccbb_intr_disestablish(struct pccbb_softc *, void *ih); 157 158 static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t, int irq, 159 int level, int (*ih) (void *), void *sc); 160 static void pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih); 161 162 static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t, int, int); 163 static void pccbb_free_tag(cardbus_chipset_tag_t, cardbustag_t); 164 static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t, cardbustag_t, int); 165 static void pccbb_conf_write(cardbus_chipset_tag_t, cardbustag_t, int, 166 cardbusreg_t); 167 static void pccbb_chipinit(struct pccbb_softc *); 168 169 STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 170 struct pcmcia_mem_handle *); 171 STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t, 172 struct pcmcia_mem_handle *); 173 STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 174 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *); 175 STATIC void pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t, int); 176 STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 177 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 178 STATIC void pccbb_pcmcia_io_free(pcmcia_chipset_handle_t, 179 struct pcmcia_io_handle *); 180 STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 181 bus_size_t, struct pcmcia_io_handle *, int *); 182 STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t, int); 183 STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t, 184 struct pcmcia_function *, int, int (*)(void *), void *); 185 STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t, void *); 186 STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t); 187 STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t); 188 STATIC void pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t, int); 189 STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch); 190 191 static int pccbb_pcmcia_wait_ready(struct pcic_handle *); 192 static void pccbb_pcmcia_delay(struct pcic_handle *, int, const char *); 193 194 static void pccbb_pcmcia_do_io_map(struct pcic_handle *, int); 195 static void pccbb_pcmcia_do_mem_map(struct pcic_handle *, int); 196 static void pccbb_powerhook(int, void *); 197 198 /* bus-space allocation and deallocation functions */ 199 #if rbus 200 201 static int pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t, rbus_tag_t, 202 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 203 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp); 204 static int pccbb_rbus_cb_space_free(cardbus_chipset_tag_t, rbus_tag_t, 205 bus_space_handle_t, bus_size_t); 206 207 #endif /* rbus */ 208 209 #if rbus 210 211 static int pccbb_open_win(struct pccbb_softc *, bus_space_tag_t, 212 bus_addr_t, bus_size_t, bus_space_handle_t, int flags); 213 static int pccbb_close_win(struct pccbb_softc *, bus_space_tag_t, 214 bus_space_handle_t, bus_size_t); 215 static int pccbb_winlist_insert(struct pccbb_win_chain_head *, bus_addr_t, 216 bus_size_t, bus_space_handle_t, int); 217 static int pccbb_winlist_delete(struct pccbb_win_chain_head *, 218 bus_space_handle_t, bus_size_t); 219 static void pccbb_winset(bus_addr_t align, struct pccbb_softc *, 220 bus_space_tag_t); 221 void pccbb_winlist_show(struct pccbb_win_chain *); 222 223 #endif /* rbus */ 224 225 /* for config_defer */ 226 static void pccbb_pci_callback(struct device *); 227 228 #if defined SHOW_REGS 229 static void cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, 230 bus_space_tag_t memt, bus_space_handle_t memh); 231 #endif 232 233 CFATTACH_DECL(cbb_pci, sizeof(struct pccbb_softc), 234 pcicbbmatch, pccbbattach, NULL, NULL); 235 236 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 237 pccbb_pcmcia_mem_alloc, 238 pccbb_pcmcia_mem_free, 239 pccbb_pcmcia_mem_map, 240 pccbb_pcmcia_mem_unmap, 241 pccbb_pcmcia_io_alloc, 242 pccbb_pcmcia_io_free, 243 pccbb_pcmcia_io_map, 244 pccbb_pcmcia_io_unmap, 245 pccbb_pcmcia_intr_establish, 246 pccbb_pcmcia_intr_disestablish, 247 pccbb_pcmcia_socket_enable, 248 pccbb_pcmcia_socket_disable, 249 pccbb_pcmcia_socket_settype, 250 pccbb_pcmcia_card_detect 251 }; 252 253 #if rbus 254 static struct cardbus_functions pccbb_funcs = { 255 pccbb_rbus_cb_space_alloc, 256 pccbb_rbus_cb_space_free, 257 pccbb_cb_intr_establish, 258 pccbb_cb_intr_disestablish, 259 pccbb_ctrl, 260 pccbb_power, 261 pccbb_make_tag, 262 pccbb_free_tag, 263 pccbb_conf_read, 264 pccbb_conf_write, 265 }; 266 #else 267 static struct cardbus_functions pccbb_funcs = { 268 pccbb_ctrl, 269 pccbb_power, 270 pccbb_mem_open, 271 pccbb_mem_close, 272 pccbb_io_open, 273 pccbb_io_close, 274 pccbb_cb_intr_establish, 275 pccbb_cb_intr_disestablish, 276 pccbb_make_tag, 277 pccbb_conf_read, 278 pccbb_conf_write, 279 }; 280 #endif 281 282 int 283 pcicbbmatch(struct device *parent, struct cfdata *match, 284 void *aux) 285 { 286 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 287 288 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 289 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 290 PCI_INTERFACE(pa->pa_class) == 0) { 291 return 1; 292 } 293 294 return 0; 295 } 296 297 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 298 | ((prod) << PCI_PRODUCT_SHIFT)) 299 300 const struct yenta_chipinfo { 301 pcireg_t yc_id; /* vendor tag | product tag */ 302 int yc_chiptype; 303 int yc_flags; 304 } yc_chipsets[] = { 305 /* Texas Instruments chips */ 306 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 307 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 308 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 309 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 310 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI125X, 311 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 312 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 313 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 314 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 315 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 316 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 317 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 318 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI125X, 319 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 320 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI125X, 321 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 322 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 323 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 324 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 325 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 326 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 327 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 328 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI125X, 329 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 330 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 331 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 332 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1520), CB_TI12XX, 333 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 334 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4410YENTA), CB_TI12XX, 335 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 336 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4520YENTA), CB_TI12XX, 337 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 338 339 /* Ricoh chips */ 340 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 341 PCCBB_PCMCIA_MEM_32}, 342 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 343 PCCBB_PCMCIA_MEM_32}, 344 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 345 PCCBB_PCMCIA_MEM_32}, 346 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 347 PCCBB_PCMCIA_MEM_32}, 348 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 349 PCCBB_PCMCIA_MEM_32}, 350 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 351 PCCBB_PCMCIA_MEM_32}, 352 353 /* Toshiba products */ 354 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 355 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 356 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 357 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 358 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 359 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 360 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 361 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 362 363 /* Cirrus Logic products */ 364 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 365 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 366 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 367 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 368 369 /* sentinel, or Generic chip */ 370 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 371 }; 372 373 static int 374 cb_chipset(pci_id, flagp) 375 u_int32_t pci_id; 376 int *flagp; 377 { 378 const struct yenta_chipinfo *yc; 379 380 /* Loop over except the last default entry. */ 381 for (yc = yc_chipsets; yc < yc_chipsets + 382 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 383 if (pci_id == yc->yc_id) 384 break; 385 386 if (flagp != NULL) 387 *flagp = yc->yc_flags; 388 389 return (yc->yc_chiptype); 390 } 391 392 static void 393 pccbb_shutdown(void *arg) 394 { 395 struct pccbb_softc *sc = arg; 396 pcireg_t command; 397 398 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 399 400 /* 401 * turn off power 402 * 403 * XXX - do not turn off power if chipset is TI 113X because 404 * only TI 1130 with PowerMac 2400 hangs in pccbb_power(). 405 */ 406 if (sc->sc_chipset != CB_TI113X) { 407 pccbb_power((cardbus_chipset_tag_t)sc, 408 CARDBUS_VCC_0V | CARDBUS_VPP_0V); 409 } 410 411 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 412 0); 413 414 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 415 416 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 417 PCI_COMMAND_MASTER_ENABLE); 418 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 419 420 } 421 422 void 423 pccbbattach(struct device *parent, struct device *self, void *aux) 424 { 425 struct pccbb_softc *sc = (void *)self; 426 struct pci_attach_args *pa = aux; 427 pci_chipset_tag_t pc = pa->pa_pc; 428 pcireg_t busreg, reg, sock_base; 429 bus_addr_t sockbase; 430 char devinfo[256]; 431 int flags; 432 int pwrmgt_offs; 433 434 #ifdef __HAVE_PCCBB_ATTACH_HOOK 435 pccbb_attach_hook(parent, self, pa); 436 #endif 437 438 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 439 440 pci_devinfo(pa->pa_id, 0, 0, devinfo, sizeof(devinfo)); 441 printf(": %s (rev. 0x%02x)", devinfo, PCI_REVISION(pa->pa_class)); 442 DPRINTF((" (chipflags %x)", flags)); 443 printf("\n"); 444 445 TAILQ_INIT(&sc->sc_memwindow); 446 TAILQ_INIT(&sc->sc_iowindow); 447 448 #if rbus 449 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 450 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 451 452 #if 0 453 printf("pa->pa_memt: %08x vs rbus_mem->rb_bt: %08x\n", 454 pa->pa_memt, sc->sc_rbus_memt->rb_bt); 455 #endif 456 #endif /* rbus */ 457 458 sc->sc_flags &= ~CBB_MEMHMAPPED; 459 460 /* power management: set D0 state */ 461 sc->sc_pwrmgt_offs = 0; 462 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, 463 &pwrmgt_offs, 0)) { 464 reg = pci_conf_read(pc, pa->pa_tag, pwrmgt_offs + PCI_PMCSR); 465 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 466 reg & 0x100 /* PCI_PMCSR_PME_EN */) { 467 reg &= ~PCI_PMCSR_STATE_MASK; 468 reg |= PCI_PMCSR_STATE_D0; 469 reg &= ~(0x100 /* PCI_PMCSR_PME_EN */); 470 pci_conf_write(pc, pa->pa_tag, 471 pwrmgt_offs + PCI_PMCSR, reg); 472 } 473 474 sc->sc_pwrmgt_offs = pwrmgt_offs; 475 } 476 477 /* 478 * MAP socket registers and ExCA registers on memory-space 479 * When no valid address is set on socket base registers (on pci 480 * config space), get it not polite way. 481 */ 482 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 483 484 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 485 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 486 /* The address must be valid. */ 487 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 488 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL)) { 489 printf("%s: can't map socket base address 0x%lx\n", 490 sc->sc_dev.dv_xname, (unsigned long)sock_base); 491 /* 492 * I think it's funny: socket base registers must be 493 * mapped on memory space, but ... 494 */ 495 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 496 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 497 NULL)) { 498 printf("%s: can't map socket base address" 499 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 500 (unsigned long)sockbase); 501 /* give up... allocate reg space via rbus. */ 502 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 503 } else 504 sc->sc_flags |= CBB_MEMHMAPPED; 505 } else { 506 DPRINTF(("%s: socket base address 0x%lx\n", 507 sc->sc_dev.dv_xname, (unsigned long)sockbase)); 508 sc->sc_flags |= CBB_MEMHMAPPED; 509 } 510 } 511 512 sc->sc_mem_start = 0; /* XXX */ 513 sc->sc_mem_end = 0xffffffff; /* XXX */ 514 515 /* 516 * When interrupt isn't routed correctly, give up probing cbb and do 517 * not kill pcic-compatible port. 518 * 519 * However, if we are using an ioapic, avoid this check -- pa_intrline 520 * may well be zero, with the interrupt routed through the apic. 521 */ 522 523 #if NIOAPIC == 0 && NACPI == 0 524 if ((0 == pa->pa_intrline) || (255 == pa->pa_intrline)) { 525 printf("%s: NOT USED because of unconfigured interrupt\n", 526 sc->sc_dev.dv_xname); 527 return; 528 } 529 #endif 530 531 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 532 533 /* pccbb_machdep.c end */ 534 535 #if defined CBB_DEBUG 536 { 537 static const char *intrname[] = { "NON", "A", "B", "C", "D" }; 538 printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname, 539 intrname[pa->pa_intrpin], pa->pa_intrline); 540 } 541 #endif 542 543 /* setup softc */ 544 sc->sc_pc = pc; 545 sc->sc_iot = pa->pa_iot; 546 sc->sc_memt = pa->pa_memt; 547 sc->sc_dmat = pa->pa_dmat; 548 sc->sc_tag = pa->pa_tag; 549 sc->sc_function = pa->pa_function; 550 sc->sc_sockbase = sock_base; 551 sc->sc_busnum = busreg; 552 553 memcpy(&sc->sc_pa, pa, sizeof(*pa)); 554 555 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 556 557 shutdownhook_establish(pccbb_shutdown, sc); 558 559 /* Disable legacy register mapping. */ 560 switch (sc->sc_chipset) { 561 case CB_RX5C46X: /* fallthrough */ 562 #if 0 563 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 564 case CB_RX5C47X: 565 #endif 566 /* 567 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 568 * cannot be disabled by substituting 0 into PCI_LEGACY 569 * register. Ricoh CardBus bridges have special bits on Bridge 570 * control reg (addr 0x3e on PCI config space). 571 */ 572 reg = pci_conf_read(pc, pa->pa_tag, PCI_BCR_INTR); 573 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 574 pci_conf_write(pc, pa->pa_tag, PCI_BCR_INTR, reg); 575 break; 576 577 default: 578 /* XXX I don't know proper way to kill legacy I/O. */ 579 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 580 break; 581 } 582 583 config_defer(self, pccbb_pci_callback); 584 } 585 586 587 588 589 /* 590 * static void pccbb_pci_callback(struct device *self) 591 * 592 * The actual attach routine: get memory space for YENTA register 593 * space, setup YENTA register and route interrupt. 594 * 595 * This function should be deferred because this device may obtain 596 * memory space dynamically. This function must avoid obtaining 597 * memory area which has already kept for another device. 598 */ 599 static void 600 pccbb_pci_callback(self) 601 struct device *self; 602 { 603 struct pccbb_softc *sc = (void *)self; 604 pci_chipset_tag_t pc = sc->sc_pc; 605 pci_intr_handle_t ih; 606 const char *intrstr = NULL; 607 bus_addr_t sockbase; 608 struct cbslot_attach_args cba; 609 struct pcmciabus_attach_args paa; 610 struct cardslot_attach_args caa; 611 struct cardslot_softc *csc; 612 613 if (!(sc->sc_flags & CBB_MEMHMAPPED)) { 614 /* The socket registers aren't mapped correctly. */ 615 #if rbus 616 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 617 (sc->sc_chipset == CB_RX5C47X 618 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 619 0, &sockbase, &sc->sc_base_memh)) { 620 return; 621 } 622 sc->sc_base_memt = sc->sc_memt; 623 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 624 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 625 sc->sc_dev.dv_xname, (unsigned long)sockbase, 626 (unsigned long)pci_conf_read(pc, sc->sc_tag, 627 PCI_SOCKBASE))); 628 #else 629 sc->sc_base_memt = sc->sc_memt; 630 #if !defined CBB_PCI_BASE 631 #define CBB_PCI_BASE 0x20000000 632 #endif 633 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 634 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 635 /* cannot allocate memory space */ 636 return; 637 } 638 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 639 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 640 sc->sc_dev.dv_xname, (unsigned long)sock_base, 641 (unsigned long)pci_conf_read(pc, 642 sc->sc_tag, PCI_SOCKBASE))); 643 sc->sc_sockbase = sockbase; 644 #endif 645 sc->sc_flags |= CBB_MEMHMAPPED; 646 } 647 648 /* bus bridge initialization */ 649 pccbb_chipinit(sc); 650 651 /* clear data structure for child device interrupt handlers */ 652 LIST_INIT(&sc->sc_pil); 653 sc->sc_pil_intr_enable = 1; 654 655 /* Map and establish the interrupt. */ 656 if (pci_intr_map(&sc->sc_pa, &ih)) { 657 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 658 return; 659 } 660 intrstr = pci_intr_string(pc, ih); 661 662 /* 663 * XXX pccbbintr should be called under the priority lower 664 * than any other hard interupts. 665 */ 666 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 667 668 if (sc->sc_ih == NULL) { 669 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 670 if (intrstr != NULL) { 671 printf(" at %s", intrstr); 672 } 673 printf("\n"); 674 return; 675 } 676 677 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 678 powerhook_establish(sc->sc_dev.dv_xname, pccbb_powerhook, sc); 679 680 { 681 u_int32_t sockstat; 682 683 sockstat = bus_space_read_4(sc->sc_base_memt, 684 sc->sc_base_memh, CB_SOCKET_STAT); 685 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 686 sc->sc_flags |= CBB_CARDEXIST; 687 } 688 } 689 690 /* 691 * attach cardbus 692 */ 693 { 694 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 695 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 696 697 /* initialize cbslot_attach */ 698 cba.cba_busname = "cardbus"; 699 cba.cba_iot = sc->sc_iot; 700 cba.cba_memt = sc->sc_memt; 701 cba.cba_dmat = sc->sc_dmat; 702 cba.cba_bus = (busreg >> 8) & 0x0ff; 703 cba.cba_cc = (void *)sc; 704 cba.cba_cf = &pccbb_funcs; 705 cba.cba_intrline = sc->sc_pa.pa_intrline; 706 707 #if rbus 708 cba.cba_rbus_iot = sc->sc_rbus_iot; 709 cba.cba_rbus_memt = sc->sc_rbus_memt; 710 #endif 711 712 cba.cba_cacheline = PCI_CACHELINE(bhlc); 713 cba.cba_lattimer = PCI_CB_LATENCY(busreg); 714 715 if (bootverbose) { 716 printf("%s: cacheline 0x%x lattimer 0x%x\n", 717 sc->sc_dev.dv_xname, cba.cba_cacheline, 718 cba.cba_lattimer); 719 printf("%s: bhlc 0x%x lscp 0x%x\n", 720 sc->sc_dev.dv_xname, bhlc, busreg); 721 } 722 #if defined SHOW_REGS 723 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 724 sc->sc_base_memh); 725 #endif 726 } 727 728 pccbb_pcmcia_attach_setup(sc, &paa); 729 caa.caa_cb_attach = NULL; 730 if (cba.cba_bus == 0) 731 printf("%s: secondary bus number uninitialized; try PCI_BUS_FIXUP\n", sc->sc_dev.dv_xname); 732 else 733 caa.caa_cb_attach = &cba; 734 caa.caa_16_attach = &paa; 735 caa.caa_ph = &sc->sc_pcmcia_h; 736 737 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 738 DPRINTF(("%s: found cardslot\n", __func__)); 739 sc->sc_csc = csc; 740 } 741 742 return; 743 } 744 745 746 747 748 749 /* 750 * static void pccbb_chipinit(struct pccbb_softc *sc) 751 * 752 * This function initialize YENTA chip registers listed below: 753 * 1) PCI command reg, 754 * 2) PCI and CardBus latency timer, 755 * 3) route PCI interrupt, 756 * 4) close all memory and io windows. 757 * 5) turn off bus power. 758 * 6) card detect and power cycle interrupts on. 759 * 7) clear interrupt 760 */ 761 static void 762 pccbb_chipinit(sc) 763 struct pccbb_softc *sc; 764 { 765 pci_chipset_tag_t pc = sc->sc_pc; 766 pcitag_t tag = sc->sc_tag; 767 bus_space_tag_t bmt = sc->sc_base_memt; 768 bus_space_handle_t bmh = sc->sc_base_memh; 769 pcireg_t reg; 770 771 /* 772 * Set PCI command reg. 773 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 774 */ 775 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 776 /* I believe it is harmless. */ 777 reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 778 PCI_COMMAND_MASTER_ENABLE); 779 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg); 780 781 /* 782 * Set CardBus latency timer. 783 */ 784 reg = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 785 if (PCI_CB_LATENCY(reg) < 0x20) { 786 reg &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 787 reg |= (0x20 << PCI_CB_LATENCY_SHIFT); 788 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, reg); 789 } 790 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 791 PCI_CB_LATENCY(reg), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 792 793 /* 794 * Set PCI latency timer. 795 */ 796 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 797 if (PCI_LATTIMER(reg) < 0x10) { 798 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 799 reg |= (0x10 << PCI_LATTIMER_SHIFT); 800 pci_conf_write(pc, tag, PCI_BHLC_REG, reg); 801 } 802 DPRINTF(("PCI latency timer 0x%x (%x)\n", 803 PCI_LATTIMER(reg), pci_conf_read(pc, tag, PCI_BHLC_REG))); 804 805 806 /* Route functional interrupts to PCI. */ 807 reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 808 reg |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 809 reg |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 810 reg |= CB_BCR_RESET_ENABLE; /* assert reset */ 811 pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 812 813 switch (sc->sc_chipset) { 814 case CB_TI113X: 815 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 816 /* This bit is shared, but may read as 0 on some chips, so set 817 it explicitly on both functions. */ 818 reg |= PCI113X_CBCTRL_PCI_IRQ_ENA; 819 /* CSC intr enable */ 820 reg |= PCI113X_CBCTRL_PCI_CSC; 821 /* functional intr prohibit | prohibit ISA routing */ 822 reg &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 823 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 824 break; 825 826 case CB_TI12XX: 827 /* 828 * Some TI 12xx (and [14][45]xx) based pci cards 829 * sometimes have issues with the MFUNC register not 830 * being initialized due to a bad EEPROM on board. 831 * Laptops that this matters on have this register 832 * properly initialized. 833 * 834 * The TI125X parts have a different register. 835 */ 836 reg = pci_conf_read(pc, tag, PCI12XX_MFUNC); 837 if (reg == 0) { 838 reg &= ~PCI12XX_MFUNC_PIN0; 839 reg |= PCI12XX_MFUNC_PIN0_INTA; 840 if ((pci_conf_read(pc, tag, PCI_SYSCTRL) & 841 PCI12XX_SYSCTRL_INTRTIE) == 0) { 842 reg &= ~PCI12XX_MFUNC_PIN1; 843 reg |= PCI12XX_MFUNC_PIN1_INTB; 844 } 845 pci_conf_write(pc, tag, PCI12XX_MFUNC, reg); 846 } 847 /* fallthrough */ 848 849 case CB_TI125X: 850 /* 851 * Disable zoom video. Some machines initialize this 852 * improperly and experience has shown that this helps 853 * prevent strange behavior. 854 */ 855 pci_conf_write(pc, tag, PCI12XX_MMCTRL, 0); 856 857 reg = pci_conf_read(pc, tag, PCI_SYSCTRL); 858 reg |= PCI12XX_SYSCTRL_VCCPROT; 859 pci_conf_write(pc, tag, PCI_SYSCTRL, reg); 860 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 861 reg |= PCI12XX_CBCTRL_CSC; 862 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 863 break; 864 865 case CB_TOPIC95B: 866 reg = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 867 reg |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 868 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, reg); 869 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 870 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 871 sc->sc_dev.dv_xname, reg)); 872 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 873 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 874 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 875 DPRINTF(("0x%x\n", reg)); 876 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 877 break; 878 879 case CB_TOPIC97: 880 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 881 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 882 sc->sc_dev.dv_xname, reg)); 883 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 884 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 885 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 886 reg |= TOPIC97_SLOT_CTRL_PCIINT; 887 reg &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 888 DPRINTF(("0x%x\n", reg)); 889 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 890 /* make sure to assert LV card support bits */ 891 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 892 0x800 + 0x3e, 893 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 894 0x800 + 0x3e) | 0x03); 895 break; 896 } 897 898 /* Close all memory and I/O windows. */ 899 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 900 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 901 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 902 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 903 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 904 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 905 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 906 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 907 908 /* reset 16-bit pcmcia bus */ 909 bus_space_write_1(bmt, bmh, 0x800 + PCIC_INTR, 910 bus_space_read_1(bmt, bmh, 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 911 912 /* turn off power */ 913 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 914 915 /* CSC Interrupt: Card detect and power cycle interrupts on */ 916 reg = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 917 reg |= CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; 918 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, reg); 919 /* reset interrupt */ 920 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 921 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 922 } 923 924 925 926 927 /* 928 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 929 * struct pcmciabus_attach_args *paa) 930 * 931 * This function attaches 16-bit PCcard bus. 932 */ 933 STATIC void 934 pccbb_pcmcia_attach_setup(sc, paa) 935 struct pccbb_softc *sc; 936 struct pcmciabus_attach_args *paa; 937 { 938 struct pcic_handle *ph = &sc->sc_pcmcia_h; 939 #if rbus 940 rbus_tag_t rb; 941 #endif 942 943 /* initialize pcmcia part in pccbb_softc */ 944 ph->ph_parent = (struct device *)sc; 945 ph->sock = sc->sc_function; 946 ph->flags = 0; 947 ph->shutdown = 0; 948 ph->ih_irq = sc->sc_pa.pa_intrline; 949 ph->ph_bus_t = sc->sc_base_memt; 950 ph->ph_bus_h = sc->sc_base_memh; 951 ph->ph_read = pccbb_pcmcia_read; 952 ph->ph_write = pccbb_pcmcia_write; 953 sc->sc_pct = &pccbb_pcmcia_funcs; 954 955 /* 956 * We need to do a few things here: 957 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 958 * setting the IRQ numbers to 0. 959 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 960 * routing of CSC interrupts (e.g. card removal) to PCI while in 961 * PCMCIA mode. We just leave this set all the time. 962 * 3) Enable card insertion/removal interrupts in case the chip also 963 * needs that while in PCMCIA mode. 964 * 4) Clear any pending CSC interrupt. 965 */ 966 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE); 967 if (sc->sc_chipset == CB_TI113X) { 968 Pcic_write(ph, PCIC_CSC_INTR, 0); 969 } else { 970 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 971 Pcic_read(ph, PCIC_CSC); 972 } 973 974 /* initialize pcmcia bus attachment */ 975 paa->paa_busname = "pcmcia"; 976 paa->pct = sc->sc_pct; 977 paa->pch = ph; 978 paa->iobase = 0; /* I don't use them */ 979 paa->iosize = 0; 980 #if rbus 981 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 982 paa->iobase = rb->rb_start + rb->rb_offset; 983 paa->iosize = rb->rb_end - rb->rb_start; 984 #endif 985 986 return; 987 } 988 989 #if 0 990 STATIC void 991 pccbb_pcmcia_attach_card(ph) 992 struct pcic_handle *ph; 993 { 994 if (ph->flags & PCIC_FLAG_CARDP) { 995 panic("pccbb_pcmcia_attach_card: already attached"); 996 } 997 998 /* call the MI attach function */ 999 pcmcia_card_attach(ph->pcmcia); 1000 1001 ph->flags |= PCIC_FLAG_CARDP; 1002 } 1003 1004 STATIC void 1005 pccbb_pcmcia_detach_card(ph, flags) 1006 struct pcic_handle *ph; 1007 int flags; 1008 { 1009 if (!(ph->flags & PCIC_FLAG_CARDP)) { 1010 panic("pccbb_pcmcia_detach_card: already detached"); 1011 } 1012 1013 ph->flags &= ~PCIC_FLAG_CARDP; 1014 1015 /* call the MI detach function */ 1016 pcmcia_card_detach(ph->pcmcia, flags); 1017 } 1018 #endif 1019 1020 /* 1021 * int pccbbintr(arg) 1022 * void *arg; 1023 * This routine handles the interrupt from Yenta PCI-CardBus bridge 1024 * itself. 1025 */ 1026 int 1027 pccbbintr(arg) 1028 void *arg; 1029 { 1030 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1031 u_int32_t sockevent, sockstate; 1032 bus_space_tag_t memt = sc->sc_base_memt; 1033 bus_space_handle_t memh = sc->sc_base_memh; 1034 struct pcic_handle *ph = &sc->sc_pcmcia_h; 1035 1036 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 1037 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 1038 Pcic_read(ph, PCIC_CSC); 1039 1040 if (sockevent == 0) { 1041 /* This intr is not for me: it may be for my child devices. */ 1042 if (sc->sc_pil_intr_enable) { 1043 return pccbbintr_function(sc); 1044 } else { 1045 return 0; 1046 } 1047 } 1048 1049 if (sockevent & CB_SOCKET_EVENT_CD) { 1050 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1051 if (0x00 != (sockstate & CB_SOCKET_STAT_CD)) { 1052 /* A card should be removed. */ 1053 if (sc->sc_flags & CBB_CARDEXIST) { 1054 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 1055 sockevent)); 1056 DPRINTF((" card removed, 0x%08x\n", sockstate)); 1057 sc->sc_flags &= ~CBB_CARDEXIST; 1058 if (sc->sc_csc->sc_status & 1059 CARDSLOT_STATUS_CARD_16) { 1060 #if 0 1061 struct pcic_handle *ph = 1062 &sc->sc_pcmcia_h; 1063 1064 pcmcia_card_deactivate(ph->pcmcia); 1065 pccbb_pcmcia_socket_disable(ph); 1066 pccbb_pcmcia_detach_card(ph, 1067 DETACH_FORCE); 1068 #endif 1069 cardslot_event_throw(sc->sc_csc, 1070 CARDSLOT_EVENT_REMOVAL_16); 1071 } else if (sc->sc_csc->sc_status & 1072 CARDSLOT_STATUS_CARD_CB) { 1073 /* Cardbus intr removed */ 1074 cardslot_event_throw(sc->sc_csc, 1075 CARDSLOT_EVENT_REMOVAL_CB); 1076 } 1077 } else if (sc->sc_flags & CBB_INSERTING) { 1078 sc->sc_flags &= ~CBB_INSERTING; 1079 callout_stop(&sc->sc_insert_ch); 1080 } 1081 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 1082 /* 1083 * The pccbbintr may called from powerdown hook when 1084 * the system resumed, to detect the card 1085 * insertion/removal during suspension. 1086 */ 1087 (sc->sc_flags & CBB_CARDEXIST) == 0) { 1088 if (sc->sc_flags & CBB_INSERTING) { 1089 callout_stop(&sc->sc_insert_ch); 1090 } 1091 callout_reset(&sc->sc_insert_ch, hz / 5, 1092 pci113x_insert, sc); 1093 sc->sc_flags |= CBB_INSERTING; 1094 } 1095 } 1096 1097 if (sockevent & CB_SOCKET_EVENT_POWER) { 1098 DPRINTF(("Powercycling because of socket event\n")); 1099 /* XXX: Does not happen when attaching a 16-bit card */ 1100 sc->sc_pwrcycle++; 1101 wakeup(&sc->sc_pwrcycle); 1102 } 1103 1104 return (1); 1105 } 1106 1107 /* 1108 * static int pccbbintr_function(struct pccbb_softc *sc) 1109 * 1110 * This function calls each interrupt handler registered at the 1111 * bridge. The interrupt handlers are called in registered order. 1112 */ 1113 static int 1114 pccbbintr_function(sc) 1115 struct pccbb_softc *sc; 1116 { 1117 int retval = 0, val; 1118 struct pccbb_intrhand_list *pil; 1119 int s; 1120 1121 for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1122 pil = LIST_NEXT(pil, pil_next)) { 1123 s = splraiseipl(pil->pil_icookie); 1124 val = (*pil->pil_func)(pil->pil_arg); 1125 splx(s); 1126 1127 retval = retval == 1 ? 1 : 1128 retval == 0 ? val : val != 0 ? val : retval; 1129 } 1130 1131 return retval; 1132 } 1133 1134 static void 1135 pci113x_insert(arg) 1136 void *arg; 1137 { 1138 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1139 u_int32_t sockevent, sockstate; 1140 1141 if (!(sc->sc_flags & CBB_INSERTING)) { 1142 /* We add a card only under inserting state. */ 1143 return; 1144 } 1145 sc->sc_flags &= ~CBB_INSERTING; 1146 1147 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1148 CB_SOCKET_EVENT); 1149 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1150 CB_SOCKET_STAT); 1151 1152 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1153 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1154 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1155 sc->sc_flags |= CBB_CARDEXIST; 1156 /* call pccard interrupt handler here */ 1157 if (sockstate & CB_SOCKET_STAT_16BIT) { 1158 /* 16-bit card found */ 1159 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1160 cardslot_event_throw(sc->sc_csc, 1161 CARDSLOT_EVENT_INSERTION_16); 1162 } else if (sockstate & CB_SOCKET_STAT_CB) { 1163 /* cardbus card found */ 1164 /* cardbus_attach_card(sc->sc_csc); */ 1165 cardslot_event_throw(sc->sc_csc, 1166 CARDSLOT_EVENT_INSERTION_CB); 1167 } else { 1168 /* who are you? */ 1169 } 1170 } else { 1171 callout_reset(&sc->sc_insert_ch, hz / 10, 1172 pci113x_insert, sc); 1173 } 1174 } 1175 1176 #define PCCBB_PCMCIA_OFFSET 0x800 1177 static u_int8_t 1178 pccbb_pcmcia_read(ph, reg) 1179 struct pcic_handle *ph; 1180 int reg; 1181 { 1182 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1183 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1184 1185 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1186 PCCBB_PCMCIA_OFFSET + reg); 1187 } 1188 1189 static void 1190 pccbb_pcmcia_write(ph, reg, val) 1191 struct pcic_handle *ph; 1192 int reg; 1193 u_int8_t val; 1194 { 1195 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1196 val); 1197 1198 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1199 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1200 } 1201 1202 /* 1203 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1204 */ 1205 STATIC int 1206 pccbb_ctrl(ct, command) 1207 cardbus_chipset_tag_t ct; 1208 int command; 1209 { 1210 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1211 1212 switch (command) { 1213 case CARDBUS_CD: 1214 if (2 == pccbb_detect_card(sc)) { 1215 int retval = 0; 1216 int status = cb_detect_voltage(sc); 1217 if (PCCARD_VCC_5V & status) { 1218 retval |= CARDBUS_5V_CARD; 1219 } 1220 if (PCCARD_VCC_3V & status) { 1221 retval |= CARDBUS_3V_CARD; 1222 } 1223 if (PCCARD_VCC_XV & status) { 1224 retval |= CARDBUS_XV_CARD; 1225 } 1226 if (PCCARD_VCC_YV & status) { 1227 retval |= CARDBUS_YV_CARD; 1228 } 1229 return retval; 1230 } else { 1231 return 0; 1232 } 1233 case CARDBUS_RESET: 1234 return cb_reset(sc); 1235 case CARDBUS_IO_ENABLE: /* fallthrough */ 1236 case CARDBUS_IO_DISABLE: /* fallthrough */ 1237 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1238 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1239 case CARDBUS_BM_ENABLE: /* fallthrough */ 1240 case CARDBUS_BM_DISABLE: /* fallthrough */ 1241 /* XXX: I think we don't need to call this function below. */ 1242 return pccbb_cardenable(sc, command); 1243 } 1244 1245 return 0; 1246 } 1247 1248 /* 1249 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1250 * This function returns true when it succeeds and returns false when 1251 * it fails. 1252 */ 1253 STATIC int 1254 pccbb_power(ct, command) 1255 cardbus_chipset_tag_t ct; 1256 int command; 1257 { 1258 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1259 u_int32_t status, sock_ctrl, reg_ctrl; 1260 bus_space_tag_t memt = sc->sc_base_memt; 1261 bus_space_handle_t memh = sc->sc_base_memh; 1262 int on = 0, pwrcycle; 1263 1264 DPRINTF(("pccbb_power: %s and %s [0x%x]\n", 1265 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1266 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1267 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1268 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1269 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1270 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1271 "UNKNOWN", 1272 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1273 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1274 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1275 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1276 "UNKNOWN", command)); 1277 1278 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1279 sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1280 1281 switch (command & CARDBUS_VCCMASK) { 1282 case CARDBUS_VCC_UC: 1283 break; 1284 case CARDBUS_VCC_5V: 1285 on++; 1286 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1287 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1288 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1289 } else { 1290 printf("%s: BAD voltage request: no 5 V card\n", 1291 sc->sc_dev.dv_xname); 1292 return 0; 1293 } 1294 break; 1295 case CARDBUS_VCC_3V: 1296 on++; 1297 if (CB_SOCKET_STAT_3VCARD & status) { 1298 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1299 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1300 } else { 1301 printf("%s: BAD voltage request: no 3.3 V card\n", 1302 sc->sc_dev.dv_xname); 1303 return 0; 1304 } 1305 break; 1306 case CARDBUS_VCC_0V: 1307 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1308 break; 1309 default: 1310 return 0; /* power NEVER changed */ 1311 } 1312 1313 switch (command & CARDBUS_VPPMASK) { 1314 case CARDBUS_VPP_UC: 1315 break; 1316 case CARDBUS_VPP_0V: 1317 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1318 break; 1319 case CARDBUS_VPP_VCC: 1320 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1321 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1322 break; 1323 case CARDBUS_VPP_12V: 1324 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1325 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1326 break; 1327 } 1328 1329 pwrcycle = sc->sc_pwrcycle; 1330 1331 #if 0 1332 DPRINTF(("sock_ctrl: 0x%x\n", sock_ctrl)); 1333 #endif 1334 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1335 1336 if (on) { 1337 int s, error = 0; 1338 struct timeval before, after, diff; 1339 1340 DPRINTF(("Waiting for bridge to power up\n")); 1341 microtime(&before); 1342 s = splbio(); 1343 while (pwrcycle == sc->sc_pwrcycle) { 1344 /* 1345 * XXX: Set timeout to 200ms because power cycle event 1346 * will never happen when attaching a 16-bit card. 1347 */ 1348 if ((error = tsleep(&sc->sc_pwrcycle, PWAIT, "pccpwr", 1349 hz / 5)) == EWOULDBLOCK) 1350 break; 1351 } 1352 splx(s); 1353 microtime(&after); 1354 timersub(&after, &before, &diff); 1355 aprint_debug("%s: wait took%s %ld.%06lds\n", 1356 sc->sc_dev.dv_xname, 1357 error == EWOULDBLOCK ? " too long" : "", 1358 diff.tv_sec, diff.tv_usec); 1359 1360 /* 1361 * Ok, wait a bit longer for things to settle. 1362 */ 1363 if (sc->sc_chipset == CB_TOPIC95B) 1364 DELAY_MS(100, sc); 1365 } 1366 1367 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1368 1369 if (on && sc->sc_chipset != CB_TOPIC95B) { 1370 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0) 1371 printf("%s: power on failed?\n", sc->sc_dev.dv_xname); 1372 } 1373 1374 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1375 printf("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1376 sc->sc_dev.dv_xname, sock_ctrl, status); 1377 printf("%s: disabling socket\n", sc->sc_dev.dv_xname); 1378 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1379 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1380 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1381 status &= ~CB_SOCKET_STAT_BADVCC; 1382 bus_space_write_4(memt, memh, CB_SOCKET_STAT, status); 1383 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1384 CB_SOCKET_STAT)); 1385 return 0; 1386 } 1387 1388 if (sc->sc_chipset == CB_TOPIC97) { 1389 reg_ctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL); 1390 reg_ctrl &= ~TOPIC97_REG_CTRL_TESTMODE; 1391 if ((command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V) 1392 reg_ctrl &= ~TOPIC97_REG_CTRL_CLKRUN_ENA; 1393 else 1394 reg_ctrl |= TOPIC97_REG_CTRL_CLKRUN_ENA; 1395 pci_conf_write(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL, reg_ctrl); 1396 } 1397 1398 return 1; /* power changed correctly */ 1399 } 1400 1401 #if defined CB_PCMCIA_POLL 1402 struct cb_poll_str { 1403 void *arg; 1404 int (*func)(void *); 1405 int level; 1406 pccard_chipset_tag_t ct; 1407 int count; 1408 struct callout poll_ch; 1409 }; 1410 1411 static struct cb_poll_str cb_poll[10]; 1412 static int cb_poll_n = 0; 1413 1414 static void cb_pcmcia_poll(void *arg); 1415 1416 static void 1417 cb_pcmcia_poll(arg) 1418 void *arg; 1419 { 1420 struct cb_poll_str *poll = arg; 1421 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1422 struct pccbb_softc *sc = psc->cpc_parent; 1423 int s; 1424 u_int32_t spsr; /* socket present-state reg */ 1425 1426 callout_reset(&poll->poll_ch, hz / 10, cb_pcmcia_poll, poll); 1427 switch (poll->level) { 1428 case IPL_NET: 1429 s = splnet(); 1430 break; 1431 case IPL_BIO: 1432 s = splbio(); 1433 break; 1434 case IPL_TTY: /* fallthrough */ 1435 default: 1436 s = spltty(); 1437 break; 1438 } 1439 1440 spsr = 1441 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1442 CB_SOCKET_STAT); 1443 1444 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1445 if (!(spsr & 0x40)) { /* CINT low */ 1446 #else 1447 if (1) { 1448 #endif 1449 if ((*poll->func) (poll->arg) == 1) { 1450 ++poll->count; 1451 printf("intr: reported from poller, 0x%x\n", spsr); 1452 #if defined LEVEL2 1453 } else { 1454 printf("intr: miss! 0x%x\n", spsr); 1455 #endif 1456 } 1457 } 1458 splx(s); 1459 } 1460 #endif /* defined CB_PCMCIA_POLL */ 1461 1462 /* 1463 * static int pccbb_detect_card(struct pccbb_softc *sc) 1464 * return value: 0 if no card exists. 1465 * 1 if 16-bit card exists. 1466 * 2 if cardbus card exists. 1467 */ 1468 static int 1469 pccbb_detect_card(sc) 1470 struct pccbb_softc *sc; 1471 { 1472 bus_space_handle_t base_memh = sc->sc_base_memh; 1473 bus_space_tag_t base_memt = sc->sc_base_memt; 1474 u_int32_t sockstat = 1475 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1476 int retval = 0; 1477 1478 /* CD1 and CD2 asserted */ 1479 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1480 /* card must be present */ 1481 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1482 /* NOTACARD DEASSERTED */ 1483 if (CB_SOCKET_STAT_CB & sockstat) { 1484 /* CardBus mode */ 1485 retval = 2; 1486 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1487 /* 16-bit mode */ 1488 retval = 1; 1489 } 1490 } 1491 } 1492 return retval; 1493 } 1494 1495 /* 1496 * STATIC int cb_reset(struct pccbb_softc *sc) 1497 * This function resets CardBus card. 1498 */ 1499 STATIC int 1500 cb_reset(sc) 1501 struct pccbb_softc *sc; 1502 { 1503 /* 1504 * Reset Assert at least 20 ms 1505 * Some machines request longer duration. 1506 */ 1507 int reset_duration = 1508 (sc->sc_chipset == CB_RX5C47X ? 400 : 50); 1509 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1510 1511 /* Reset bit Assert (bit 6 at 0x3E) */ 1512 bcr |= CB_BCR_RESET_ENABLE; 1513 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1514 DELAY_MS(reset_duration, sc); 1515 1516 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1517 /* Reset bit Deassert (bit 6 at 0x3E) */ 1518 bcr &= ~CB_BCR_RESET_ENABLE; 1519 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1520 DELAY_MS(reset_duration, sc); 1521 } 1522 /* No card found on the slot. Keep Reset. */ 1523 return 1; 1524 } 1525 1526 /* 1527 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1528 * This function detect card Voltage. 1529 */ 1530 STATIC int 1531 cb_detect_voltage(sc) 1532 struct pccbb_softc *sc; 1533 { 1534 u_int32_t psr; /* socket present-state reg */ 1535 bus_space_tag_t iot = sc->sc_base_memt; 1536 bus_space_handle_t ioh = sc->sc_base_memh; 1537 int vol = PCCARD_VCC_UKN; /* set 0 */ 1538 1539 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1540 1541 if (0x400u & psr) { 1542 vol |= PCCARD_VCC_5V; 1543 } 1544 if (0x800u & psr) { 1545 vol |= PCCARD_VCC_3V; 1546 } 1547 1548 return vol; 1549 } 1550 1551 STATIC int 1552 cbbprint(void *aux, const char *pcic) 1553 { 1554 #if 0 1555 struct cbslot_attach_args *cba = aux; 1556 1557 if (cba->cba_slot >= 0) { 1558 aprint_normal(" slot %d", cba->cba_slot); 1559 } 1560 #endif 1561 return UNCONF; 1562 } 1563 1564 /* 1565 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1566 * This function enables and disables the card 1567 */ 1568 STATIC int 1569 pccbb_cardenable(sc, function) 1570 struct pccbb_softc *sc; 1571 int function; 1572 { 1573 u_int32_t command = 1574 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1575 1576 DPRINTF(("pccbb_cardenable:")); 1577 switch (function) { 1578 case CARDBUS_IO_ENABLE: 1579 command |= PCI_COMMAND_IO_ENABLE; 1580 break; 1581 case CARDBUS_IO_DISABLE: 1582 command &= ~PCI_COMMAND_IO_ENABLE; 1583 break; 1584 case CARDBUS_MEM_ENABLE: 1585 command |= PCI_COMMAND_MEM_ENABLE; 1586 break; 1587 case CARDBUS_MEM_DISABLE: 1588 command &= ~PCI_COMMAND_MEM_ENABLE; 1589 break; 1590 case CARDBUS_BM_ENABLE: 1591 command |= PCI_COMMAND_MASTER_ENABLE; 1592 break; 1593 case CARDBUS_BM_DISABLE: 1594 command &= ~PCI_COMMAND_MASTER_ENABLE; 1595 break; 1596 default: 1597 return 0; 1598 } 1599 1600 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1601 DPRINTF((" command reg 0x%x\n", command)); 1602 return 1; 1603 } 1604 1605 #if !rbus 1606 /* 1607 * int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1608 */ 1609 static int 1610 pccbb_io_open(ct, win, start, end) 1611 cardbus_chipset_tag_t ct; 1612 int win; 1613 u_int32_t start, end; 1614 { 1615 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1616 int basereg; 1617 int limitreg; 1618 1619 if ((win < 0) || (win > 2)) { 1620 #if defined DIAGNOSTIC 1621 printf("cardbus_io_open: window out of range %d\n", win); 1622 #endif 1623 return 0; 1624 } 1625 1626 basereg = win * 8 + 0x2c; 1627 limitreg = win * 8 + 0x30; 1628 1629 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1630 start, basereg, end, limitreg)); 1631 1632 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1633 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1634 return 1; 1635 } 1636 1637 /* 1638 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1639 */ 1640 static int 1641 pccbb_io_close(ct, win) 1642 cardbus_chipset_tag_t ct; 1643 int win; 1644 { 1645 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1646 int basereg; 1647 int limitreg; 1648 1649 if ((win < 0) || (win > 2)) { 1650 #if defined DIAGNOSTIC 1651 printf("cardbus_io_close: window out of range %d\n", win); 1652 #endif 1653 return 0; 1654 } 1655 1656 basereg = win * 8 + 0x2c; 1657 limitreg = win * 8 + 0x30; 1658 1659 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1660 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1661 return 1; 1662 } 1663 1664 /* 1665 * int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1666 */ 1667 static int 1668 pccbb_mem_open(ct, win, start, end) 1669 cardbus_chipset_tag_t ct; 1670 int win; 1671 u_int32_t start, end; 1672 { 1673 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1674 int basereg; 1675 int limitreg; 1676 1677 if ((win < 0) || (win > 2)) { 1678 #if defined DIAGNOSTIC 1679 printf("cardbus_mem_open: window out of range %d\n", win); 1680 #endif 1681 return 0; 1682 } 1683 1684 basereg = win * 8 + 0x1c; 1685 limitreg = win * 8 + 0x20; 1686 1687 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1688 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1689 return 1; 1690 } 1691 1692 /* 1693 * int pccbb_mem_close(cardbus_chipset_tag_t, int) 1694 */ 1695 static int 1696 pccbb_mem_close(ct, win) 1697 cardbus_chipset_tag_t ct; 1698 int win; 1699 { 1700 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1701 int basereg; 1702 int limitreg; 1703 1704 if ((win < 0) || (win > 2)) { 1705 #if defined DIAGNOSTIC 1706 printf("cardbus_mem_close: window out of range %d\n", win); 1707 #endif 1708 return 0; 1709 } 1710 1711 basereg = win * 8 + 0x1c; 1712 limitreg = win * 8 + 0x20; 1713 1714 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1715 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1716 return 1; 1717 } 1718 #endif 1719 1720 /* 1721 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1722 * int irq, 1723 * int level, 1724 * int (* func)(void *), 1725 * void *arg) 1726 * 1727 * This function registers an interrupt handler at the bridge, in 1728 * order not to call the interrupt handlers of child devices when 1729 * a card-deletion interrupt occurs. 1730 * 1731 * The arguments irq and level are not used. 1732 */ 1733 static void * 1734 pccbb_cb_intr_establish(ct, irq, level, func, arg) 1735 cardbus_chipset_tag_t ct; 1736 int irq, level; 1737 int (*func)(void *); 1738 void *arg; 1739 { 1740 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1741 1742 return pccbb_intr_establish(sc, irq, level, func, arg); 1743 } 1744 1745 1746 /* 1747 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1748 * void *ih) 1749 * 1750 * This function removes an interrupt handler pointed by ih. 1751 */ 1752 static void 1753 pccbb_cb_intr_disestablish(ct, ih) 1754 cardbus_chipset_tag_t ct; 1755 void *ih; 1756 { 1757 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1758 1759 pccbb_intr_disestablish(sc, ih); 1760 } 1761 1762 1763 void 1764 pccbb_intr_route(sc) 1765 struct pccbb_softc *sc; 1766 { 1767 pcireg_t reg; 1768 1769 /* initialize bridge intr routing */ 1770 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1771 reg &= ~CB_BCR_INTR_IREQ_ENABLE; 1772 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1773 1774 switch (sc->sc_chipset) { 1775 case CB_TI113X: 1776 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1777 /* functional intr enabled */ 1778 reg |= PCI113X_CBCTRL_PCI_INTR; 1779 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1780 break; 1781 default: 1782 break; 1783 } 1784 } 1785 1786 /* 1787 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1788 * int irq, 1789 * int level, 1790 * int (* func)(void *), 1791 * void *arg) 1792 * 1793 * This function registers an interrupt handler at the bridge, in 1794 * order not to call the interrupt handlers of child devices when 1795 * a card-deletion interrupt occurs. 1796 * 1797 * The arguments irq is not used because pccbb selects intr vector. 1798 */ 1799 static void * 1800 pccbb_intr_establish(struct pccbb_softc *sc, int irq, int level, 1801 int (*func)(void *), void *arg) 1802 { 1803 struct pccbb_intrhand_list *pil, *newpil; 1804 1805 DPRINTF(("pccbb_intr_establish start. %p\n", LIST_FIRST(&sc->sc_pil))); 1806 1807 if (LIST_EMPTY(&sc->sc_pil)) { 1808 pccbb_intr_route(sc); 1809 } 1810 1811 /* 1812 * Allocate a room for interrupt handler structure. 1813 */ 1814 if (NULL == (newpil = 1815 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1816 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1817 return NULL; 1818 } 1819 1820 newpil->pil_func = func; 1821 newpil->pil_arg = arg; 1822 newpil->pil_icookie = makeiplcookie(level); 1823 1824 if (LIST_EMPTY(&sc->sc_pil)) { 1825 LIST_INSERT_HEAD(&sc->sc_pil, newpil, pil_next); 1826 } else { 1827 for (pil = LIST_FIRST(&sc->sc_pil); 1828 LIST_NEXT(pil, pil_next) != NULL; 1829 pil = LIST_NEXT(pil, pil_next)); 1830 LIST_INSERT_AFTER(pil, newpil, pil_next); 1831 } 1832 1833 DPRINTF(("pccbb_intr_establish add pil. %p\n", 1834 LIST_FIRST(&sc->sc_pil))); 1835 1836 return newpil; 1837 } 1838 1839 /* 1840 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1841 * void *ih) 1842 * 1843 * This function removes an interrupt handler pointed by ih. ih 1844 * should be the value returned by cardbus_intr_establish() or 1845 * NULL. 1846 * 1847 * When ih is NULL, this function will do nothing. 1848 */ 1849 static void 1850 pccbb_intr_disestablish(sc, ih) 1851 struct pccbb_softc *sc; 1852 void *ih; 1853 { 1854 struct pccbb_intrhand_list *pil; 1855 pcireg_t reg; 1856 1857 DPRINTF(("pccbb_intr_disestablish start. %p\n", 1858 LIST_FIRST(&sc->sc_pil))); 1859 1860 if (ih == NULL) { 1861 /* intr handler is not set */ 1862 DPRINTF(("pccbb_intr_disestablish: no ih\n")); 1863 return; 1864 } 1865 1866 #ifdef DIAGNOSTIC 1867 for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1868 pil = LIST_NEXT(pil, pil_next)) { 1869 DPRINTF(("pccbb_intr_disestablish: pil %p\n", pil)); 1870 if (pil == ih) { 1871 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1872 break; 1873 } 1874 } 1875 if (pil == NULL) { 1876 panic("pccbb_intr_disestablish: %s cannot find pil %p", 1877 sc->sc_dev.dv_xname, ih); 1878 } 1879 #endif 1880 1881 pil = (struct pccbb_intrhand_list *)ih; 1882 LIST_REMOVE(pil, pil_next); 1883 free(pil, M_DEVBUF); 1884 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1885 1886 if (LIST_EMPTY(&sc->sc_pil)) { 1887 /* No interrupt handlers */ 1888 1889 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1890 1891 /* stop routing PCI intr */ 1892 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1893 reg |= CB_BCR_INTR_IREQ_ENABLE; 1894 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1895 1896 switch (sc->sc_chipset) { 1897 case CB_TI113X: 1898 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1899 /* functional intr disabled */ 1900 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1901 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1902 break; 1903 default: 1904 break; 1905 } 1906 } 1907 } 1908 1909 #if defined SHOW_REGS 1910 static void 1911 cb_show_regs(pc, tag, memt, memh) 1912 pci_chipset_tag_t pc; 1913 pcitag_t tag; 1914 bus_space_tag_t memt; 1915 bus_space_handle_t memh; 1916 { 1917 int i; 1918 printf("PCI config regs:"); 1919 for (i = 0; i < 0x50; i += 4) { 1920 if (i % 16 == 0) { 1921 printf("\n 0x%02x:", i); 1922 } 1923 printf(" %08x", pci_conf_read(pc, tag, i)); 1924 } 1925 for (i = 0x80; i < 0xb0; i += 4) { 1926 if (i % 16 == 0) { 1927 printf("\n 0x%02x:", i); 1928 } 1929 printf(" %08x", pci_conf_read(pc, tag, i)); 1930 } 1931 1932 if (memh == 0) { 1933 printf("\n"); 1934 return; 1935 } 1936 1937 printf("\nsocket regs:"); 1938 for (i = 0; i <= 0x10; i += 0x04) { 1939 printf(" %08x", bus_space_read_4(memt, memh, i)); 1940 } 1941 printf("\nExCA regs:"); 1942 for (i = 0; i < 0x08; ++i) { 1943 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1944 } 1945 printf("\n"); 1946 return; 1947 } 1948 #endif 1949 1950 /* 1951 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1952 * int busno, int function) 1953 * This is the function to make a tag to access config space of 1954 * a CardBus Card. It works same as pci_conf_read. 1955 */ 1956 static cardbustag_t 1957 pccbb_make_tag(cc, busno, function) 1958 cardbus_chipset_tag_t cc; 1959 int busno, function; 1960 { 1961 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1962 1963 return pci_make_tag(sc->sc_pc, busno, 0, function); 1964 } 1965 1966 static void 1967 pccbb_free_tag(cardbus_chipset_tag_t cc, cardbustag_t tag) 1968 { 1969 } 1970 1971 /* 1972 * static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t cc, 1973 * cardbustag_t tag, int offset) 1974 * This is the function to read the config space of a CardBus Card. 1975 * It works same as pci_conf_read. 1976 */ 1977 static cardbusreg_t 1978 pccbb_conf_read(cc, tag, offset) 1979 cardbus_chipset_tag_t cc; 1980 cardbustag_t tag; 1981 int offset; /* register offset */ 1982 { 1983 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1984 1985 return pci_conf_read(sc->sc_pc, tag, offset); 1986 } 1987 1988 /* 1989 * static void pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, 1990 * int offs, cardbusreg_t val) 1991 * This is the function to write the config space of a CardBus Card. 1992 * It works same as pci_conf_write. 1993 */ 1994 static void 1995 pccbb_conf_write(cc, tag, reg, val) 1996 cardbus_chipset_tag_t cc; 1997 cardbustag_t tag; 1998 int reg; /* register offset */ 1999 cardbusreg_t val; 2000 { 2001 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 2002 2003 pci_conf_write(sc->sc_pc, tag, reg, val); 2004 } 2005 2006 #if 0 2007 STATIC int 2008 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 2009 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 2010 int speed, int flags, 2011 bus_space_handle_t * iohp) 2012 #endif 2013 /* 2014 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 2015 * bus_addr_t start, bus_size_t size, 2016 * bus_size_t align, 2017 * struct pcmcia_io_handle *pcihp 2018 * 2019 * This function only allocates I/O region for pccard. This function 2020 * never maps the allocated region to pccard I/O area. 2021 * 2022 * XXX: The interface of this function is not very good, I believe. 2023 */ 2024 STATIC int 2025 pccbb_pcmcia_io_alloc(pch, start, size, align, pcihp) 2026 pcmcia_chipset_handle_t pch; 2027 bus_addr_t start; /* start address */ 2028 bus_size_t size; 2029 bus_size_t align; 2030 struct pcmcia_io_handle *pcihp; 2031 { 2032 struct pcic_handle *ph = (struct pcic_handle *)pch; 2033 bus_addr_t ioaddr; 2034 int flags = 0; 2035 bus_space_tag_t iot; 2036 bus_space_handle_t ioh; 2037 bus_addr_t mask; 2038 #if rbus 2039 rbus_tag_t rb; 2040 #endif 2041 if (align == 0) { 2042 align = size; /* XXX: funny??? */ 2043 } 2044 2045 if (start != 0) { 2046 /* XXX: assume all card decode lower 10 bits by its hardware */ 2047 mask = 0x3ff; 2048 /* enforce to use only masked address */ 2049 start &= mask; 2050 } else { 2051 /* 2052 * calculate mask: 2053 * 1. get the most significant bit of size (call it msb). 2054 * 2. compare msb with the value of size. 2055 * 3. if size is larger, shift msb left once. 2056 * 4. obtain mask value to decrement msb. 2057 */ 2058 bus_size_t size_tmp = size; 2059 int shifts = 0; 2060 2061 mask = 1; 2062 while (size_tmp) { 2063 ++shifts; 2064 size_tmp >>= 1; 2065 } 2066 mask = (1 << shifts); 2067 if (mask < size) { 2068 mask <<= 1; 2069 } 2070 --mask; 2071 } 2072 2073 /* 2074 * Allocate some arbitrary I/O space. 2075 */ 2076 2077 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 2078 2079 #if rbus 2080 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 2081 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 2082 return 1; 2083 } 2084 DPRINTF(("pccbb_pcmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2085 (u_long) ioaddr, (u_long) size)); 2086 #else 2087 if (start) { 2088 ioaddr = start; 2089 if (bus_space_map(iot, start, size, 0, &ioh)) { 2090 return 1; 2091 } 2092 DPRINTF(("pccbb_pcmcia_io_alloc map port 0x%lx+0x%lx\n", 2093 (u_long) ioaddr, (u_long) size)); 2094 } else { 2095 flags |= PCMCIA_IO_ALLOCATED; 2096 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 2097 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 2098 size, align, 0, 0, &ioaddr, &ioh)) { 2099 /* No room be able to be get. */ 2100 return 1; 2101 } 2102 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2103 (u_long) ioaddr, (u_long) size)); 2104 } 2105 #endif 2106 2107 pcihp->iot = iot; 2108 pcihp->ioh = ioh; 2109 pcihp->addr = ioaddr; 2110 pcihp->size = size; 2111 pcihp->flags = flags; 2112 2113 return 0; 2114 } 2115 2116 /* 2117 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2118 * struct pcmcia_io_handle *pcihp) 2119 * 2120 * This function only frees I/O region for pccard. 2121 * 2122 * XXX: The interface of this function is not very good, I believe. 2123 */ 2124 void 2125 pccbb_pcmcia_io_free(pch, pcihp) 2126 pcmcia_chipset_handle_t pch; 2127 struct pcmcia_io_handle *pcihp; 2128 { 2129 #if !rbus 2130 bus_space_tag_t iot = pcihp->iot; 2131 #endif 2132 bus_space_handle_t ioh = pcihp->ioh; 2133 bus_size_t size = pcihp->size; 2134 2135 #if rbus 2136 struct pccbb_softc *sc = 2137 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 2138 rbus_tag_t rb = sc->sc_rbus_iot; 2139 2140 rbus_space_free(rb, ioh, size, NULL); 2141 #else 2142 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 2143 bus_space_free(iot, ioh, size); 2144 else 2145 bus_space_unmap(iot, ioh, size); 2146 #endif 2147 } 2148 2149 /* 2150 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 2151 * bus_addr_t offset, bus_size_t size, 2152 * struct pcmcia_io_handle *pcihp, 2153 * int *windowp) 2154 * 2155 * This function maps the allocated I/O region to pccard. This function 2156 * never allocates any I/O region for pccard I/O area. I don't 2157 * understand why the original authors of pcmciabus separated alloc and 2158 * map. I believe the two must be unite. 2159 * 2160 * XXX: no wait timing control? 2161 */ 2162 int 2163 pccbb_pcmcia_io_map(pch, width, offset, size, pcihp, windowp) 2164 pcmcia_chipset_handle_t pch; 2165 int width; 2166 bus_addr_t offset; 2167 bus_size_t size; 2168 struct pcmcia_io_handle *pcihp; 2169 int *windowp; 2170 { 2171 struct pcic_handle *ph = (struct pcic_handle *)pch; 2172 bus_addr_t ioaddr = pcihp->addr + offset; 2173 int i, win; 2174 #if defined CBB_DEBUG 2175 static const char *width_names[] = { "dynamic", "io8", "io16" }; 2176 #endif 2177 2178 /* Sanity check I/O handle. */ 2179 2180 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 2181 panic("pccbb_pcmcia_io_map iot is bogus"); 2182 } 2183 2184 /* XXX Sanity check offset/size. */ 2185 2186 win = -1; 2187 for (i = 0; i < PCIC_IO_WINS; i++) { 2188 if ((ph->ioalloc & (1 << i)) == 0) { 2189 win = i; 2190 ph->ioalloc |= (1 << i); 2191 break; 2192 } 2193 } 2194 2195 if (win == -1) { 2196 return 1; 2197 } 2198 2199 *windowp = win; 2200 2201 /* XXX this is pretty gross */ 2202 2203 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2204 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2205 2206 /* XXX wtf is this doing here? */ 2207 2208 #if 0 2209 printf(" port 0x%lx", (u_long) ioaddr); 2210 if (size > 1) { 2211 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2212 } 2213 #endif 2214 2215 ph->io[win].addr = ioaddr; 2216 ph->io[win].size = size; 2217 ph->io[win].width = width; 2218 2219 /* actual dirty register-value changing in the function below. */ 2220 pccbb_pcmcia_do_io_map(ph, win); 2221 2222 return 0; 2223 } 2224 2225 /* 2226 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2227 * 2228 * This function changes register-value to map I/O region for pccard. 2229 */ 2230 static void 2231 pccbb_pcmcia_do_io_map(ph, win) 2232 struct pcic_handle *ph; 2233 int win; 2234 { 2235 static u_int8_t pcic_iowidth[3] = { 2236 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2237 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2238 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2239 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2240 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2241 }; 2242 2243 #define PCIC_SIA_START_LOW 0 2244 #define PCIC_SIA_START_HIGH 1 2245 #define PCIC_SIA_STOP_LOW 2 2246 #define PCIC_SIA_STOP_HIGH 3 2247 2248 int regbase_win = 0x8 + win * 0x04; 2249 u_int8_t ioctl, enable; 2250 2251 DPRINTF(("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx " 2252 "width %d\n", win, (unsigned long)ph->io[win].addr, 2253 (unsigned long)ph->io[win].size, ph->io[win].width * 8)); 2254 2255 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2256 ph->io[win].addr & 0xff); 2257 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2258 (ph->io[win].addr >> 8) & 0xff); 2259 2260 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2261 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2262 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2263 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2264 2265 ioctl = Pcic_read(ph, PCIC_IOCTL); 2266 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2267 switch (win) { 2268 case 0: 2269 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2270 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2271 PCIC_IOCTL_IO0_DATASIZE_MASK); 2272 ioctl |= pcic_iowidth[ph->io[win].width]; 2273 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2274 break; 2275 case 1: 2276 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2277 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2278 PCIC_IOCTL_IO1_DATASIZE_MASK); 2279 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2280 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2281 break; 2282 } 2283 Pcic_write(ph, PCIC_IOCTL, ioctl); 2284 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2285 #if defined(CBB_DEBUG) 2286 { 2287 u_int8_t start_low = 2288 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2289 u_int8_t start_high = 2290 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2291 u_int8_t stop_low = 2292 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2293 u_int8_t stop_high = 2294 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2295 printf("pccbb_pcmcia_do_io_map start %02x %02x, " 2296 "stop %02x %02x, ioctl %02x enable %02x\n", 2297 start_low, start_high, stop_low, stop_high, ioctl, enable); 2298 } 2299 #endif 2300 } 2301 2302 /* 2303 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2304 * 2305 * This function unmaps I/O region. No return value. 2306 */ 2307 STATIC void 2308 pccbb_pcmcia_io_unmap(pch, win) 2309 pcmcia_chipset_handle_t pch; 2310 int win; 2311 { 2312 struct pcic_handle *ph = (struct pcic_handle *)pch; 2313 int reg; 2314 2315 if (win >= PCIC_IO_WINS || win < 0) { 2316 panic("pccbb_pcmcia_io_unmap: window out of range"); 2317 } 2318 2319 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2320 switch (win) { 2321 case 0: 2322 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2323 break; 2324 case 1: 2325 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2326 break; 2327 } 2328 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2329 2330 ph->ioalloc &= ~(1 << win); 2331 } 2332 2333 static int 2334 pccbb_pcmcia_wait_ready(ph) 2335 struct pcic_handle *ph; 2336 { 2337 u_int8_t stat; 2338 int i; 2339 2340 /* wait an initial 10ms for quick cards */ 2341 stat = Pcic_read(ph, PCIC_IF_STATUS); 2342 if (stat & PCIC_IF_STATUS_READY) 2343 return (0); 2344 pccbb_pcmcia_delay(ph, 10, "pccwr0"); 2345 for (i = 0; i < 50; i++) { 2346 stat = Pcic_read(ph, PCIC_IF_STATUS); 2347 if (stat & PCIC_IF_STATUS_READY) 2348 return (0); 2349 if ((stat & PCIC_IF_STATUS_CARDDETECT_MASK) != 2350 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2351 return (ENXIO); 2352 /* wait .1s (100ms) each iteration now */ 2353 pccbb_pcmcia_delay(ph, 100, "pccwr1"); 2354 } 2355 2356 printf("pccbb_pcmcia_wait_ready: ready never happened, status=%02x\n", stat); 2357 return (EWOULDBLOCK); 2358 } 2359 2360 /* 2361 * Perform long (msec order) delay. 2362 */ 2363 static void 2364 pccbb_pcmcia_delay( 2365 struct pcic_handle *ph, 2366 int timo, /* in ms. must not be zero */ 2367 const char *wmesg 2368 ) 2369 { 2370 #ifdef DIAGNOSTIC 2371 if (timo <= 0) 2372 panic("pccbb_pcmcia_delay: called with timeout %d", timo); 2373 if (!curlwp) 2374 panic("pccbb_pcmcia_delay: called in interrupt context"); 2375 #if 0 2376 if (!ph->event_thread) 2377 panic("pccbb_pcmcia_delay: no event thread"); 2378 #endif 2379 #endif 2380 DPRINTF(("pccbb_pcmcia_delay: \"%s\" %p, sleep %d ms\n", 2381 wmesg, ph->event_thread, timo)); 2382 tsleep(pccbb_pcmcia_delay, PWAIT, wmesg, roundup(timo * hz, 1000) / 1000); 2383 } 2384 2385 /* 2386 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2387 * 2388 * This function enables the card. All information is stored in 2389 * the first argument, pcmcia_chipset_handle_t. 2390 */ 2391 STATIC void 2392 pccbb_pcmcia_socket_enable(pch) 2393 pcmcia_chipset_handle_t pch; 2394 { 2395 struct pcic_handle *ph = (struct pcic_handle *)pch; 2396 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2397 pcireg_t spsr; 2398 int voltage; 2399 int win; 2400 u_int8_t power, intr; 2401 #ifdef DIAGNOSTIC 2402 int reg; 2403 #endif 2404 2405 /* this bit is mostly stolen from pcic_attach_card */ 2406 2407 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2408 2409 /* get card Vcc info */ 2410 spsr = 2411 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2412 CB_SOCKET_STAT); 2413 if (spsr & CB_SOCKET_STAT_5VCARD) { 2414 DPRINTF(("5V card\n")); 2415 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2416 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2417 DPRINTF(("3V card\n")); 2418 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2419 } else { 2420 DPRINTF(("?V card, 0x%x\n", spsr)); /* XXX */ 2421 return; 2422 } 2423 2424 /* disable interrupts; assert RESET */ 2425 intr = Pcic_read(ph, PCIC_INTR); 2426 intr &= PCIC_INTR_ENABLE; 2427 Pcic_write(ph, PCIC_INTR, intr); 2428 2429 /* zero out the address windows */ 2430 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2431 2432 /* power down the socket to reset it, clear the card reset pin */ 2433 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2434 2435 /* power off; assert output enable bit */ 2436 power = PCIC_PWRCTL_OE; 2437 Pcic_write(ph, PCIC_PWRCTL, power); 2438 2439 /* power up the socket */ 2440 if (pccbb_power(sc, voltage) == 0) 2441 return; 2442 2443 /* 2444 * Table 4-18 and figure 4-6 of the PC Card specifiction say: 2445 * Vcc Rising Time (Tpr) = 100ms (handled in pccbb_power() above) 2446 * RESET Width (Th (Hi-z RESET)) = 1ms 2447 * RESET Width (Tw (RESET)) = 10us 2448 * 2449 * some machines require some more time to be settled 2450 * for example old toshiba topic bridges! 2451 * (100ms is added here). 2452 */ 2453 pccbb_pcmcia_delay(ph, 200 + 1, "pccen1"); 2454 2455 /* negate RESET */ 2456 intr |= PCIC_INTR_RESET; 2457 Pcic_write(ph, PCIC_INTR, intr); 2458 2459 /* 2460 * RESET Setup Time (Tsu (RESET)) = 20ms 2461 */ 2462 pccbb_pcmcia_delay(ph, 20, "pccen2"); 2463 2464 #ifdef DIAGNOSTIC 2465 reg = Pcic_read(ph, PCIC_IF_STATUS); 2466 if ((reg & PCIC_IF_STATUS_POWERACTIVE) == 0) 2467 printf("pccbb_pcmcia_socket_enable: no power, status=%x\n", reg); 2468 #endif 2469 2470 /* wait for the chip to finish initializing */ 2471 if (pccbb_pcmcia_wait_ready(ph)) { 2472 #ifdef DIAGNOSTIC 2473 printf("pccbb_pcmcia_socket_enable: never became ready\n"); 2474 #endif 2475 /* XXX return a failure status?? */ 2476 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2477 Pcic_write(ph, PCIC_PWRCTL, 0); 2478 return; 2479 } 2480 2481 /* reinstall all the memory and io mappings */ 2482 for (win = 0; win < PCIC_MEM_WINS; ++win) 2483 if (ph->memalloc & (1 << win)) 2484 pccbb_pcmcia_do_mem_map(ph, win); 2485 for (win = 0; win < PCIC_IO_WINS; ++win) 2486 if (ph->ioalloc & (1 << win)) 2487 pccbb_pcmcia_do_io_map(ph, win); 2488 } 2489 2490 /* 2491 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2492 * 2493 * This function disables the card. All information is stored in 2494 * the first argument, pcmcia_chipset_handle_t. 2495 */ 2496 STATIC void 2497 pccbb_pcmcia_socket_disable(pch) 2498 pcmcia_chipset_handle_t pch; 2499 { 2500 struct pcic_handle *ph = (struct pcic_handle *)pch; 2501 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2502 u_int8_t intr; 2503 2504 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2505 2506 /* disable interrupts; assert RESET */ 2507 intr = Pcic_read(ph, PCIC_INTR); 2508 intr &= PCIC_INTR_ENABLE; 2509 Pcic_write(ph, PCIC_INTR, intr); 2510 2511 /* zero out the address windows */ 2512 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2513 2514 /* power down the socket to reset it, clear the card reset pin */ 2515 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2516 2517 /* disable socket: negate output enable bit and power off */ 2518 Pcic_write(ph, PCIC_PWRCTL, 0); 2519 2520 /* 2521 * Vcc Falling Time (Tpf) = 300ms 2522 */ 2523 pccbb_pcmcia_delay(ph, 300, "pccwr1"); 2524 } 2525 2526 STATIC void 2527 pccbb_pcmcia_socket_settype(pch, type) 2528 pcmcia_chipset_handle_t pch; 2529 int type; 2530 { 2531 struct pcic_handle *ph = (struct pcic_handle *)pch; 2532 u_int8_t intr; 2533 2534 /* set the card type */ 2535 2536 intr = Pcic_read(ph, PCIC_INTR); 2537 intr &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_CARDTYPE_MASK); 2538 if (type == PCMCIA_IFTYPE_IO) 2539 intr |= PCIC_INTR_CARDTYPE_IO; 2540 else 2541 intr |= PCIC_INTR_CARDTYPE_MEM; 2542 Pcic_write(ph, PCIC_INTR, intr); 2543 2544 DPRINTF(("%s: pccbb_pcmcia_socket_settype %02x type %s %02x\n", 2545 ph->ph_parent->dv_xname, ph->sock, 2546 ((type == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2547 } 2548 2549 /* 2550 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2551 * 2552 * This function detects whether a card is in the slot or not. 2553 * If a card is inserted, return 1. Otherwise, return 0. 2554 */ 2555 STATIC int 2556 pccbb_pcmcia_card_detect(pch) 2557 pcmcia_chipset_handle_t pch; 2558 { 2559 struct pcic_handle *ph = (struct pcic_handle *)pch; 2560 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2561 2562 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2563 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2564 } 2565 2566 #if 0 2567 STATIC int 2568 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2569 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2570 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2571 #endif 2572 /* 2573 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2574 * bus_size_t size, 2575 * struct pcmcia_mem_handle *pcmhp) 2576 * 2577 * This function only allocates memory region for pccard. This 2578 * function never maps the allocated region to pccard memory area. 2579 * 2580 * XXX: Why the argument of start address is not in? 2581 */ 2582 STATIC int 2583 pccbb_pcmcia_mem_alloc(pch, size, pcmhp) 2584 pcmcia_chipset_handle_t pch; 2585 bus_size_t size; 2586 struct pcmcia_mem_handle *pcmhp; 2587 { 2588 struct pcic_handle *ph = (struct pcic_handle *)pch; 2589 bus_space_handle_t memh; 2590 bus_addr_t addr; 2591 bus_size_t sizepg; 2592 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2593 #if rbus 2594 rbus_tag_t rb; 2595 #endif 2596 2597 /* Check that the card is still there. */ 2598 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2599 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2600 return 1; 2601 2602 /* out of sc->memh, allocate as many pages as necessary */ 2603 2604 /* convert size to PCIC pages */ 2605 /* 2606 * This is not enough; when the requested region is on the page 2607 * boundaries, this may calculate wrong result. 2608 */ 2609 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2610 #if 0 2611 if (sizepg > PCIC_MAX_MEM_PAGES) { 2612 return 1; 2613 } 2614 #endif 2615 2616 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2617 return 1; 2618 } 2619 2620 addr = 0; /* XXX gcc -Wuninitialized */ 2621 2622 #if rbus 2623 rb = sc->sc_rbus_memt; 2624 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2625 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2626 &addr, &memh)) { 2627 return 1; 2628 } 2629 #else 2630 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2631 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2632 0, /* boundary */ 2633 0, /* flags */ 2634 &addr, &memh)) { 2635 return 1; 2636 } 2637 #endif 2638 2639 DPRINTF(("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, " 2640 "realsize 0x%lx\n", (unsigned long)addr, (unsigned long)size, 2641 (unsigned long)sizepg * PCIC_MEM_PAGESIZE)); 2642 2643 pcmhp->memt = sc->sc_memt; 2644 pcmhp->memh = memh; 2645 pcmhp->addr = addr; 2646 pcmhp->size = size; 2647 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2648 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2649 pcmhp->mhandle = 0; 2650 /* No offset??? Funny. */ 2651 2652 return 0; 2653 } 2654 2655 /* 2656 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2657 * struct pcmcia_mem_handle *pcmhp) 2658 * 2659 * This function release the memory space allocated by the function 2660 * pccbb_pcmcia_mem_alloc(). 2661 */ 2662 STATIC void 2663 pccbb_pcmcia_mem_free(pch, pcmhp) 2664 pcmcia_chipset_handle_t pch; 2665 struct pcmcia_mem_handle *pcmhp; 2666 { 2667 #if rbus 2668 struct pcic_handle *ph = (struct pcic_handle *)pch; 2669 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2670 2671 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2672 #else 2673 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2674 #endif 2675 } 2676 2677 /* 2678 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2679 * 2680 * This function release the memory space allocated by the function 2681 * pccbb_pcmcia_mem_alloc(). 2682 */ 2683 STATIC void 2684 pccbb_pcmcia_do_mem_map(ph, win) 2685 struct pcic_handle *ph; 2686 int win; 2687 { 2688 int regbase_win; 2689 bus_addr_t phys_addr; 2690 bus_addr_t phys_end; 2691 2692 #define PCIC_SMM_START_LOW 0 2693 #define PCIC_SMM_START_HIGH 1 2694 #define PCIC_SMM_STOP_LOW 2 2695 #define PCIC_SMM_STOP_HIGH 3 2696 #define PCIC_CMA_LOW 4 2697 #define PCIC_CMA_HIGH 5 2698 2699 u_int8_t start_low, start_high = 0; 2700 u_int8_t stop_low, stop_high; 2701 u_int8_t off_low, off_high; 2702 u_int8_t mem_window; 2703 int reg; 2704 2705 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2706 int mem8 = 2707 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2708 || (kind == PCMCIA_MEM_ATTR); 2709 2710 regbase_win = 0x10 + win * 0x08; 2711 2712 phys_addr = ph->mem[win].addr; 2713 phys_end = phys_addr + ph->mem[win].size; 2714 2715 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2716 (unsigned long)phys_addr, (unsigned long)phys_end, 2717 (unsigned long)ph->mem[win].offset)); 2718 2719 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2720 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2721 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2722 2723 /* bit 19:12 */ 2724 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2725 /* bit 23:20 and bit 7 on */ 2726 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2727 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2728 /* bit 31:24, for 32-bit address */ 2729 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2730 2731 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2732 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2733 2734 if (((struct pccbb_softc *)ph-> 2735 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2736 Pcic_write(ph, 0x40 + win, mem_window); 2737 } 2738 2739 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2740 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2741 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2742 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2743 2744 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2745 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2746 2747 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2748 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2749 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2750 | ((kind == PCMCIA_MEM_ATTR) ? 2751 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2752 2753 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2754 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2755 2756 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2757 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2758 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2759 2760 #if defined(CBB_DEBUG) 2761 { 2762 int r1, r2, r3, r4, r5, r6, r7 = 0; 2763 2764 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2765 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2766 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2767 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2768 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2769 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2770 if (((struct pccbb_softc *)(ph-> 2771 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2772 r7 = Pcic_read(ph, 0x40 + win); 2773 } 2774 2775 printf("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2776 "%02x%02x", win, r1, r2, r3, r4, r5, r6); 2777 if (((struct pccbb_softc *)(ph-> 2778 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2779 printf(" %02x", r7); 2780 } 2781 printf("\n"); 2782 } 2783 #endif 2784 } 2785 2786 /* 2787 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2788 * bus_addr_t card_addr, bus_size_t size, 2789 * struct pcmcia_mem_handle *pcmhp, 2790 * bus_addr_t *offsetp, int *windowp) 2791 * 2792 * This function maps memory space allocated by the function 2793 * pccbb_pcmcia_mem_alloc(). 2794 */ 2795 STATIC int 2796 pccbb_pcmcia_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 2797 pcmcia_chipset_handle_t pch; 2798 int kind; 2799 bus_addr_t card_addr; 2800 bus_size_t size; 2801 struct pcmcia_mem_handle *pcmhp; 2802 bus_addr_t *offsetp; 2803 int *windowp; 2804 { 2805 struct pcic_handle *ph = (struct pcic_handle *)pch; 2806 bus_addr_t busaddr; 2807 long card_offset; 2808 int win; 2809 2810 /* Check that the card is still there. */ 2811 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2812 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2813 return 1; 2814 2815 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2816 if ((ph->memalloc & (1 << win)) == 0) { 2817 ph->memalloc |= (1 << win); 2818 break; 2819 } 2820 } 2821 2822 if (win == PCIC_MEM_WINS) { 2823 return 1; 2824 } 2825 2826 *windowp = win; 2827 2828 /* XXX this is pretty gross */ 2829 2830 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2831 panic("pccbb_pcmcia_mem_map memt is bogus"); 2832 } 2833 2834 busaddr = pcmhp->addr; 2835 2836 /* 2837 * compute the address offset to the pcmcia address space for the 2838 * pcic. this is intentionally signed. The masks and shifts below 2839 * will cause TRT to happen in the pcic registers. Deal with making 2840 * sure the address is aligned, and return the alignment offset. 2841 */ 2842 2843 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2844 card_addr -= *offsetp; 2845 2846 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2847 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2848 (u_long) card_addr)); 2849 2850 /* 2851 * include the offset in the size, and decrement size by one, since 2852 * the hw wants start/stop 2853 */ 2854 size += *offsetp - 1; 2855 2856 card_offset = (((long)card_addr) - ((long)busaddr)); 2857 2858 ph->mem[win].addr = busaddr; 2859 ph->mem[win].size = size; 2860 ph->mem[win].offset = card_offset; 2861 ph->mem[win].kind = kind; 2862 2863 pccbb_pcmcia_do_mem_map(ph, win); 2864 2865 return 0; 2866 } 2867 2868 /* 2869 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2870 * int window) 2871 * 2872 * This function unmaps memory space which mapped by the function 2873 * pccbb_pcmcia_mem_map(). 2874 */ 2875 STATIC void 2876 pccbb_pcmcia_mem_unmap(pch, window) 2877 pcmcia_chipset_handle_t pch; 2878 int window; 2879 { 2880 struct pcic_handle *ph = (struct pcic_handle *)pch; 2881 int reg; 2882 2883 if (window >= PCIC_MEM_WINS) { 2884 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2885 } 2886 2887 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2888 reg &= ~(1 << window); 2889 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2890 2891 ph->memalloc &= ~(1 << window); 2892 } 2893 2894 #if defined PCCBB_PCMCIA_POLL 2895 struct pccbb_poll_str { 2896 void *arg; 2897 int (*func)(void *); 2898 int level; 2899 struct pcic_handle *ph; 2900 int count; 2901 int num; 2902 struct callout poll_ch; 2903 }; 2904 2905 static struct pccbb_poll_str pccbb_poll[10]; 2906 static int pccbb_poll_n = 0; 2907 2908 static void pccbb_pcmcia_poll(void *arg); 2909 2910 static void 2911 pccbb_pcmcia_poll(arg) 2912 void *arg; 2913 { 2914 struct pccbb_poll_str *poll = arg; 2915 struct pcic_handle *ph = poll->ph; 2916 struct pccbb_softc *sc = ph->sc; 2917 int s; 2918 u_int32_t spsr; /* socket present-state reg */ 2919 2920 callout_reset(&poll->poll_ch, hz * 2, pccbb_pcmcia_poll, arg); 2921 switch (poll->level) { 2922 case IPL_NET: 2923 s = splnet(); 2924 break; 2925 case IPL_BIO: 2926 s = splbio(); 2927 break; 2928 case IPL_TTY: /* fallthrough */ 2929 default: 2930 s = spltty(); 2931 break; 2932 } 2933 2934 spsr = 2935 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2936 CB_SOCKET_STAT); 2937 2938 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2939 if (!(spsr & 0x40)) /* CINT low */ 2940 #else 2941 if (1) 2942 #endif 2943 { 2944 if ((*poll->func) (poll->arg) > 0) { 2945 ++poll->count; 2946 /* printf("intr: reported from poller, 0x%x\n", spsr); */ 2947 #if defined LEVEL2 2948 } else { 2949 printf("intr: miss! 0x%x\n", spsr); 2950 #endif 2951 } 2952 } 2953 splx(s); 2954 } 2955 #endif /* defined CB_PCMCIA_POLL */ 2956 2957 /* 2958 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2959 * struct pcmcia_function *pf, 2960 * int ipl, 2961 * int (*func)(void *), 2962 * void *arg); 2963 * 2964 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2965 */ 2966 STATIC void * 2967 pccbb_pcmcia_intr_establish(pch, pf, ipl, func, arg) 2968 pcmcia_chipset_handle_t pch; 2969 struct pcmcia_function *pf; 2970 int ipl; 2971 int (*func)(void *); 2972 void *arg; 2973 { 2974 struct pcic_handle *ph = (struct pcic_handle *)pch; 2975 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2976 2977 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2978 /* what should I do? */ 2979 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2980 DPRINTF(("%s does not provide edge nor pulse " 2981 "interrupt\n", sc->sc_dev.dv_xname)); 2982 return NULL; 2983 } 2984 /* 2985 * XXX Noooooo! The interrupt flag must set properly!! 2986 * dumb pcmcia driver!! 2987 */ 2988 } 2989 2990 return pccbb_intr_establish(sc, 0, ipl, func, arg); 2991 } 2992 2993 /* 2994 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2995 * void *ih) 2996 * 2997 * This function disables PC-Card interrupt. 2998 */ 2999 STATIC void 3000 pccbb_pcmcia_intr_disestablish(pch, ih) 3001 pcmcia_chipset_handle_t pch; 3002 void *ih; 3003 { 3004 struct pcic_handle *ph = (struct pcic_handle *)pch; 3005 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 3006 3007 pccbb_intr_disestablish(sc, ih); 3008 } 3009 3010 #if rbus 3011 /* 3012 * static int 3013 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 3014 * bus_addr_t addr, bus_size_t size, 3015 * bus_addr_t mask, bus_size_t align, 3016 * int flags, bus_addr_t *addrp; 3017 * bus_space_handle_t *bshp) 3018 * 3019 * This function allocates a portion of memory or io space for 3020 * clients. This function is called from CardBus card drivers. 3021 */ 3022 static int 3023 pccbb_rbus_cb_space_alloc(ct, rb, addr, size, mask, align, flags, addrp, bshp) 3024 cardbus_chipset_tag_t ct; 3025 rbus_tag_t rb; 3026 bus_addr_t addr; 3027 bus_size_t size; 3028 bus_addr_t mask; 3029 bus_size_t align; 3030 int flags; 3031 bus_addr_t *addrp; 3032 bus_space_handle_t *bshp; 3033 { 3034 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 3035 3036 DPRINTF(("pccbb_rbus_cb_space_alloc: addr 0x%lx, size 0x%lx, " 3037 "mask 0x%lx, align 0x%lx\n", (unsigned long)addr, 3038 (unsigned long)size, (unsigned long)mask, (unsigned long)align)); 3039 3040 if (align == 0) { 3041 align = size; 3042 } 3043 3044 if (rb->rb_bt == sc->sc_memt) { 3045 if (align < 16) { 3046 return 1; 3047 } 3048 /* 3049 * XXX: align more than 0x1000 to avoid overwrapping 3050 * memory windows for two or more devices. 0x1000 3051 * means memory window's granularity. 3052 * 3053 * Two or more devices should be able to share same 3054 * memory window region. However, overrapping memory 3055 * window is not good because some devices, such as 3056 * 3Com 3C575[BC], have a broken address decoder and 3057 * intrude other's memory region. 3058 */ 3059 if (align < 0x1000) { 3060 align = 0x1000; 3061 } 3062 } else if (rb->rb_bt == sc->sc_iot) { 3063 if (align < 4) { 3064 return 1; 3065 } 3066 /* XXX: hack for avoiding ISA image */ 3067 if (mask < 0x0100) { 3068 mask = 0x3ff; 3069 addr = 0x300; 3070 } 3071 3072 } else { 3073 DPRINTF(("pccbb_rbus_cb_space_alloc: Bus space tag 0x%lx is " 3074 "NOT used. io: 0x%lx, mem: 0x%lx\n", 3075 (unsigned long)rb->rb_bt, (unsigned long)sc->sc_iot, 3076 (unsigned long)sc->sc_memt)); 3077 return 1; 3078 /* XXX: panic here? */ 3079 } 3080 3081 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 3082 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 3083 return 1; 3084 } 3085 3086 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 3087 3088 return 0; 3089 } 3090 3091 /* 3092 * static int 3093 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 3094 * bus_space_handle_t *bshp, bus_size_t size); 3095 * 3096 * This function is called from CardBus card drivers. 3097 */ 3098 static int 3099 pccbb_rbus_cb_space_free(ct, rb, bsh, size) 3100 cardbus_chipset_tag_t ct; 3101 rbus_tag_t rb; 3102 bus_space_handle_t bsh; 3103 bus_size_t size; 3104 { 3105 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 3106 bus_space_tag_t bt = rb->rb_bt; 3107 3108 pccbb_close_win(sc, bt, bsh, size); 3109 3110 if (bt == sc->sc_memt) { 3111 } else if (bt == sc->sc_iot) { 3112 } else { 3113 return 1; 3114 /* XXX: panic here? */ 3115 } 3116 3117 return rbus_space_free(rb, bsh, size, NULL); 3118 } 3119 #endif /* rbus */ 3120 3121 #if rbus 3122 3123 static int 3124 pccbb_open_win(sc, bst, addr, size, bsh, flags) 3125 struct pccbb_softc *sc; 3126 bus_space_tag_t bst; 3127 bus_addr_t addr; 3128 bus_size_t size; 3129 bus_space_handle_t bsh; 3130 int flags; 3131 { 3132 struct pccbb_win_chain_head *head; 3133 bus_addr_t align; 3134 3135 head = &sc->sc_iowindow; 3136 align = 0x04; 3137 if (sc->sc_memt == bst) { 3138 head = &sc->sc_memwindow; 3139 align = 0x1000; 3140 DPRINTF(("using memory window, 0x%lx 0x%lx 0x%lx\n\n", 3141 (unsigned long)sc->sc_iot, (unsigned long)sc->sc_memt, 3142 (unsigned long)bst)); 3143 } 3144 3145 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 3146 printf("%s: pccbb_open_win: %s winlist insert failed\n", 3147 sc->sc_dev.dv_xname, 3148 (head == &sc->sc_memwindow) ? "mem" : "io"); 3149 } 3150 pccbb_winset(align, sc, bst); 3151 3152 return 0; 3153 } 3154 3155 static int 3156 pccbb_close_win(sc, bst, bsh, size) 3157 struct pccbb_softc *sc; 3158 bus_space_tag_t bst; 3159 bus_space_handle_t bsh; 3160 bus_size_t size; 3161 { 3162 struct pccbb_win_chain_head *head; 3163 bus_addr_t align; 3164 3165 head = &sc->sc_iowindow; 3166 align = 0x04; 3167 if (sc->sc_memt == bst) { 3168 head = &sc->sc_memwindow; 3169 align = 0x1000; 3170 } 3171 3172 if (pccbb_winlist_delete(head, bsh, size)) { 3173 printf("%s: pccbb_close_win: %s winlist delete failed\n", 3174 sc->sc_dev.dv_xname, 3175 (head == &sc->sc_memwindow) ? "mem" : "io"); 3176 } 3177 pccbb_winset(align, sc, bst); 3178 3179 return 0; 3180 } 3181 3182 static int 3183 pccbb_winlist_insert(head, start, size, bsh, flags) 3184 struct pccbb_win_chain_head *head; 3185 bus_addr_t start; 3186 bus_size_t size; 3187 bus_space_handle_t bsh; 3188 int flags; 3189 { 3190 struct pccbb_win_chain *chainp, *elem; 3191 3192 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 3193 M_NOWAIT)) == NULL) 3194 return (1); /* fail */ 3195 3196 elem->wc_start = start; 3197 elem->wc_end = start + (size - 1); 3198 elem->wc_handle = bsh; 3199 elem->wc_flags = flags; 3200 3201 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3202 chainp = TAILQ_NEXT(chainp, wc_list)) { 3203 if (chainp->wc_end < start) 3204 continue; 3205 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 3206 return (0); 3207 } 3208 3209 TAILQ_INSERT_TAIL(head, elem, wc_list); 3210 return (0); 3211 } 3212 3213 static int 3214 pccbb_winlist_delete(head, bsh, size) 3215 struct pccbb_win_chain_head *head; 3216 bus_space_handle_t bsh; 3217 bus_size_t size; 3218 { 3219 struct pccbb_win_chain *chainp; 3220 3221 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3222 chainp = TAILQ_NEXT(chainp, wc_list)) { 3223 if (memcmp(&chainp->wc_handle, &bsh, sizeof(bsh))) 3224 continue; 3225 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 3226 printf("pccbb_winlist_delete: window 0x%lx size " 3227 "inconsistent: 0x%lx, 0x%lx\n", 3228 (unsigned long)chainp->wc_start, 3229 (unsigned long)(chainp->wc_end - chainp->wc_start), 3230 (unsigned long)(size - 1)); 3231 return 1; 3232 } 3233 3234 TAILQ_REMOVE(head, chainp, wc_list); 3235 free(chainp, M_DEVBUF); 3236 3237 return 0; 3238 } 3239 3240 return 1; /* fail: no candidate to remove */ 3241 } 3242 3243 static void 3244 pccbb_winset(align, sc, bst) 3245 bus_addr_t align; 3246 struct pccbb_softc *sc; 3247 bus_space_tag_t bst; 3248 { 3249 pci_chipset_tag_t pc; 3250 pcitag_t tag; 3251 bus_addr_t mask = ~(align - 1); 3252 struct { 3253 cardbusreg_t win_start; 3254 cardbusreg_t win_limit; 3255 int win_flags; 3256 } win[2]; 3257 struct pccbb_win_chain *chainp; 3258 int offs; 3259 3260 win[0].win_start = win[1].win_start = 0xffffffff; 3261 win[0].win_limit = win[1].win_limit = 0; 3262 win[0].win_flags = win[1].win_flags = 0; 3263 3264 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3265 offs = 0x2c; 3266 if (sc->sc_memt == bst) { 3267 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3268 offs = 0x1c; 3269 } 3270 3271 if (chainp != NULL) { 3272 win[0].win_start = chainp->wc_start & mask; 3273 win[0].win_limit = chainp->wc_end & mask; 3274 win[0].win_flags = chainp->wc_flags; 3275 chainp = TAILQ_NEXT(chainp, wc_list); 3276 } 3277 3278 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3279 if (win[1].win_start == 0xffffffff) { 3280 /* window 1 is not used */ 3281 if ((win[0].win_flags == chainp->wc_flags) && 3282 (win[0].win_limit + align >= 3283 (chainp->wc_start & mask))) { 3284 /* concatenate */ 3285 win[0].win_limit = chainp->wc_end & mask; 3286 } else { 3287 /* make new window */ 3288 win[1].win_start = chainp->wc_start & mask; 3289 win[1].win_limit = chainp->wc_end & mask; 3290 win[1].win_flags = chainp->wc_flags; 3291 } 3292 continue; 3293 } 3294 3295 /* Both windows are engaged. */ 3296 if (win[0].win_flags == win[1].win_flags) { 3297 /* same flags */ 3298 if (win[0].win_flags == chainp->wc_flags) { 3299 if (win[1].win_start - (win[0].win_limit + 3300 align) < 3301 (chainp->wc_start & mask) - 3302 ((chainp->wc_end & mask) + align)) { 3303 /* 3304 * merge window 0 and 1, and set win1 3305 * to chainp 3306 */ 3307 win[0].win_limit = win[1].win_limit; 3308 win[1].win_start = 3309 chainp->wc_start & mask; 3310 win[1].win_limit = 3311 chainp->wc_end & mask; 3312 } else { 3313 win[1].win_limit = 3314 chainp->wc_end & mask; 3315 } 3316 } else { 3317 /* different flags */ 3318 3319 /* concatenate win0 and win1 */ 3320 win[0].win_limit = win[1].win_limit; 3321 /* allocate win[1] to new space */ 3322 win[1].win_start = chainp->wc_start & mask; 3323 win[1].win_limit = chainp->wc_end & mask; 3324 win[1].win_flags = chainp->wc_flags; 3325 } 3326 } else { 3327 /* the flags of win[0] and win[1] is different */ 3328 if (win[0].win_flags == chainp->wc_flags) { 3329 win[0].win_limit = chainp->wc_end & mask; 3330 /* 3331 * XXX this creates overlapping windows, so 3332 * what should the poor bridge do if one is 3333 * cachable, and the other is not? 3334 */ 3335 printf("%s: overlapping windows\n", 3336 sc->sc_dev.dv_xname); 3337 } else { 3338 win[1].win_limit = chainp->wc_end & mask; 3339 } 3340 } 3341 } 3342 3343 pc = sc->sc_pc; 3344 tag = sc->sc_tag; 3345 pci_conf_write(pc, tag, offs, win[0].win_start); 3346 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3347 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3348 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3349 DPRINTF(("--pccbb_winset: win0 [0x%lx, 0x%lx), win1 [0x%lx, 0x%lx)\n", 3350 (unsigned long)pci_conf_read(pc, tag, offs), 3351 (unsigned long)pci_conf_read(pc, tag, offs + 4) + align, 3352 (unsigned long)pci_conf_read(pc, tag, offs + 8), 3353 (unsigned long)pci_conf_read(pc, tag, offs + 12) + align)); 3354 3355 if (bst == sc->sc_memt) { 3356 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3357 3358 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 3359 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 3360 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3361 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 3362 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3363 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3364 } 3365 } 3366 3367 #endif /* rbus */ 3368 3369 static void 3370 pccbb_powerhook(why, arg) 3371 int why; 3372 void *arg; 3373 { 3374 struct pccbb_softc *sc = arg; 3375 pcireg_t reg; 3376 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3377 bus_space_handle_t base_memh = sc->sc_base_memh; 3378 3379 DPRINTF(("%s: power: why %d\n", sc->sc_dev.dv_xname, why)); 3380 3381 if (why == PWR_SUSPEND || why == PWR_STANDBY) { 3382 DPRINTF(("%s: power: why %d stopping intr\n", 3383 sc->sc_dev.dv_xname, why)); 3384 if (sc->sc_pil_intr_enable) { 3385 (void)pccbbintr_function(sc); 3386 } 3387 sc->sc_pil_intr_enable = 0; 3388 3389 pci_conf_capture(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf); 3390 3391 if (sc->sc_chipset == CB_RX5C47X) 3392 sc->sc_ricoh_misc_ctrl = pci_conf_read(sc->sc_pc, 3393 sc->sc_tag, 3394 RICOH_PCI_MISC_CTRL); 3395 3396 /* ToDo: deactivate or suspend child devices */ 3397 } 3398 3399 if (why == PWR_RESUME) { 3400 if (sc->sc_pwrmgt_offs != 0) { 3401 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, 3402 sc->sc_pwrmgt_offs + PCI_PMCSR); 3403 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 3404 reg & PCI_PMCSR_PME_EN) { 3405 /* powrstate != D0 */ 3406 3407 printf("%s going back to D0 mode\n", 3408 sc->sc_dev.dv_xname); 3409 reg &= ~PCI_PMCSR_STATE_MASK; 3410 reg |= PCI_PMCSR_STATE_D0; 3411 reg &= ~PCI_PMCSR_PME_EN; 3412 pci_conf_write(sc->sc_pc, sc->sc_tag, 3413 sc->sc_pwrmgt_offs + PCI_PMCSR, reg); 3414 3415 pci_conf_write(sc->sc_pc, sc->sc_tag, 3416 PCI_SOCKBASE, sc->sc_sockbase); 3417 pci_conf_write(sc->sc_pc, sc->sc_tag, 3418 PCI_BUSNUM, sc->sc_busnum); 3419 pccbb_chipinit(sc); 3420 /* setup memory and io space window for CB */ 3421 pccbb_winset(0x1000, sc, sc->sc_memt); 3422 pccbb_winset(0x04, sc, sc->sc_iot); 3423 goto norestore; 3424 } 3425 } 3426 3427 norestore: 3428 pci_conf_restore(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf); 3429 if (sc->sc_chipset == CB_RX5C47X) { 3430 pci_conf_write(sc->sc_pc, sc->sc_tag, 3431 RICOH_PCI_MISC_CTRL, sc->sc_ricoh_misc_ctrl); 3432 } 3433 3434 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_SOCKBASE) == 0) 3435 /* BIOS did not recover this register */ 3436 pci_conf_write (sc->sc_pc, sc->sc_tag, 3437 PCI_SOCKBASE, sc->sc_sockbase); 3438 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_BUSNUM) == 0) 3439 /* BIOS did not recover this register */ 3440 pci_conf_write (sc->sc_pc, sc->sc_tag, 3441 PCI_BUSNUM, sc->sc_busnum); 3442 /* CSC Interrupt: Card detect interrupt on */ 3443 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3444 /* Card detect intr is turned on. */ 3445 reg |= CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; 3446 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3447 /* reset interrupt */ 3448 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3449 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3450 3451 /* 3452 * check for card insertion or removal during suspend period. 3453 * XXX: the code can't cope with card swap (remove then 3454 * insert). how can we detect such situation? 3455 */ 3456 (void)pccbbintr(sc); 3457 3458 sc->sc_pil_intr_enable = 1; 3459 DPRINTF(("%s: power: RESUME enabling intr\n", 3460 sc->sc_dev.dv_xname)); 3461 3462 /* ToDo: activate or wakeup child devices */ 3463 } 3464 } 3465
Indexes created Thu Sep 25 16:09:42 GMT 2025