pccbb.c revision 1.142
1 /* $NetBSD: pccbb.c,v 1.142 2007/02/04 05:08:18 dyoung Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: pccbb.c,v 1.142 2007/02/04 05:08:18 dyoung Exp $"); 35 36 /* 37 #define CBB_DEBUG 38 #define SHOW_REGS 39 */ 40 41 /* 42 * BROKEN! 43 #define PCCBB_PCMCIA_POLL 44 #define CB_PCMCIA_POLL 45 #define CB_PCMCIA_POLL_ONLY 46 #define LEVEL2 47 */ 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/kernel.h> 52 #include <sys/errno.h> 53 #include <sys/ioctl.h> 54 #include <sys/reboot.h> /* for bootverbose */ 55 #include <sys/syslog.h> 56 #include <sys/device.h> 57 #include <sys/malloc.h> 58 #include <sys/proc.h> 59 60 #include <machine/intr.h> 61 #include <machine/bus.h> 62 63 #include <dev/pci/pcivar.h> 64 #include <dev/pci/pcireg.h> 65 #include <dev/pci/pcidevs.h> 66 67 #include <dev/pci/pccbbreg.h> 68 69 #include <dev/cardbus/cardslotvar.h> 70 71 #include <dev/cardbus/cardbusvar.h> 72 73 #include <dev/pcmcia/pcmciareg.h> 74 #include <dev/pcmcia/pcmciavar.h> 75 76 #include <dev/ic/i82365reg.h> 77 #include <dev/ic/i82365var.h> 78 #include <dev/pci/pccbbvar.h> 79 80 #include "locators.h" 81 82 #if defined(__i386__) 83 #include "ioapic.h" 84 #include "acpi.h" 85 #endif 86 87 #ifndef __NetBSD_Version__ 88 struct cfdriver cbb_cd = { 89 NULL, "cbb", DV_DULL 90 }; 91 #endif 92 93 #ifdef CBB_DEBUG 94 #define DPRINTF(x) printf x 95 #define STATIC 96 #else 97 #define DPRINTF(x) 98 #define STATIC static 99 #endif 100 101 /* 102 * delay_ms() is wait in milliseconds. It should be used instead 103 * of delay() if you want to wait more than 1 ms. 104 */ 105 static inline void 106 delay_ms(int millis, void *param) 107 { 108 if (cold) 109 delay(millis * 1000); 110 else 111 tsleep(param, PWAIT, "pccbb", MAX(2, hz * millis / 1000)); 112 } 113 114 int pcicbbmatch(struct device *, struct cfdata *, void *); 115 void pccbbattach(struct device *, struct device *, void *); 116 int pccbbintr(void *); 117 static void pci113x_insert(void *); 118 static int pccbbintr_function(struct pccbb_softc *); 119 120 static int pccbb_detect_card(struct pccbb_softc *); 121 122 static void pccbb_pcmcia_write(struct pcic_handle *, int, u_int8_t); 123 static u_int8_t pccbb_pcmcia_read(struct pcic_handle *, int); 124 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 125 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 126 127 STATIC int cb_reset(struct pccbb_softc *); 128 STATIC int cb_detect_voltage(struct pccbb_softc *); 129 STATIC int cbbprint(void *, const char *); 130 131 static int cb_chipset(u_int32_t, int *); 132 STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *, 133 struct pcmciabus_attach_args *); 134 #if 0 135 STATIC void pccbb_pcmcia_attach_card(struct pcic_handle *); 136 STATIC void pccbb_pcmcia_detach_card(struct pcic_handle *, int); 137 STATIC void pccbb_pcmcia_deactivate_card(struct pcic_handle *); 138 #endif 139 140 STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int); 141 STATIC int pccbb_power(cardbus_chipset_tag_t, int); 142 STATIC int pccbb_cardenable(struct pccbb_softc * sc, int function); 143 #if !rbus 144 static int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 145 static int pccbb_io_close(cardbus_chipset_tag_t, int); 146 static int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 147 static int pccbb_mem_close(cardbus_chipset_tag_t, int); 148 #endif /* !rbus */ 149 static void *pccbb_intr_establish(struct pccbb_softc *, int irq, 150 int level, int (*ih) (void *), void *sc); 151 static void pccbb_intr_disestablish(struct pccbb_softc *, void *ih); 152 153 static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t, int irq, 154 int level, int (*ih) (void *), void *sc); 155 static void pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih); 156 157 static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t, int, int); 158 static void pccbb_free_tag(cardbus_chipset_tag_t, cardbustag_t); 159 static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t, cardbustag_t, int); 160 static void pccbb_conf_write(cardbus_chipset_tag_t, cardbustag_t, int, 161 cardbusreg_t); 162 static void pccbb_chipinit(struct pccbb_softc *); 163 164 STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 165 struct pcmcia_mem_handle *); 166 STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t, 167 struct pcmcia_mem_handle *); 168 STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 169 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *); 170 STATIC void pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t, int); 171 STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 172 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 173 STATIC void pccbb_pcmcia_io_free(pcmcia_chipset_handle_t, 174 struct pcmcia_io_handle *); 175 STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 176 bus_size_t, struct pcmcia_io_handle *, int *); 177 STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t, int); 178 STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t, 179 struct pcmcia_function *, int, int (*)(void *), void *); 180 STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t, void *); 181 STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t); 182 STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t); 183 STATIC void pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t, int); 184 STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch); 185 186 static int pccbb_pcmcia_wait_ready(struct pcic_handle *); 187 static void pccbb_pcmcia_delay(struct pcic_handle *, int, const char *); 188 189 static void pccbb_pcmcia_do_io_map(struct pcic_handle *, int); 190 static void pccbb_pcmcia_do_mem_map(struct pcic_handle *, int); 191 static void pccbb_powerhook(int, void *); 192 193 /* bus-space allocation and deallocation functions */ 194 #if rbus 195 196 static int pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t, rbus_tag_t, 197 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 198 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp); 199 static int pccbb_rbus_cb_space_free(cardbus_chipset_tag_t, rbus_tag_t, 200 bus_space_handle_t, bus_size_t); 201 202 #endif /* rbus */ 203 204 #if rbus 205 206 static int pccbb_open_win(struct pccbb_softc *, bus_space_tag_t, 207 bus_addr_t, bus_size_t, bus_space_handle_t, int flags); 208 static int pccbb_close_win(struct pccbb_softc *, bus_space_tag_t, 209 bus_space_handle_t, bus_size_t); 210 static int pccbb_winlist_insert(struct pccbb_win_chain_head *, bus_addr_t, 211 bus_size_t, bus_space_handle_t, int); 212 static int pccbb_winlist_delete(struct pccbb_win_chain_head *, 213 bus_space_handle_t, bus_size_t); 214 static void pccbb_winset(bus_addr_t align, struct pccbb_softc *, 215 bus_space_tag_t); 216 void pccbb_winlist_show(struct pccbb_win_chain *); 217 218 #endif /* rbus */ 219 220 /* for config_defer */ 221 static void pccbb_pci_callback(struct device *); 222 223 #if defined SHOW_REGS 224 static void cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, 225 bus_space_tag_t memt, bus_space_handle_t memh); 226 #endif 227 228 CFATTACH_DECL(cbb_pci, sizeof(struct pccbb_softc), 229 pcicbbmatch, pccbbattach, NULL, NULL); 230 231 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 232 pccbb_pcmcia_mem_alloc, 233 pccbb_pcmcia_mem_free, 234 pccbb_pcmcia_mem_map, 235 pccbb_pcmcia_mem_unmap, 236 pccbb_pcmcia_io_alloc, 237 pccbb_pcmcia_io_free, 238 pccbb_pcmcia_io_map, 239 pccbb_pcmcia_io_unmap, 240 pccbb_pcmcia_intr_establish, 241 pccbb_pcmcia_intr_disestablish, 242 pccbb_pcmcia_socket_enable, 243 pccbb_pcmcia_socket_disable, 244 pccbb_pcmcia_socket_settype, 245 pccbb_pcmcia_card_detect 246 }; 247 248 #if rbus 249 static struct cardbus_functions pccbb_funcs = { 250 pccbb_rbus_cb_space_alloc, 251 pccbb_rbus_cb_space_free, 252 pccbb_cb_intr_establish, 253 pccbb_cb_intr_disestablish, 254 pccbb_ctrl, 255 pccbb_power, 256 pccbb_make_tag, 257 pccbb_free_tag, 258 pccbb_conf_read, 259 pccbb_conf_write, 260 }; 261 #else 262 static struct cardbus_functions pccbb_funcs = { 263 pccbb_ctrl, 264 pccbb_power, 265 pccbb_mem_open, 266 pccbb_mem_close, 267 pccbb_io_open, 268 pccbb_io_close, 269 pccbb_cb_intr_establish, 270 pccbb_cb_intr_disestablish, 271 pccbb_make_tag, 272 pccbb_conf_read, 273 pccbb_conf_write, 274 }; 275 #endif 276 277 int 278 pcicbbmatch(struct device *parent, struct cfdata *match, 279 void *aux) 280 { 281 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 282 283 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 284 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 285 PCI_INTERFACE(pa->pa_class) == 0) { 286 return 1; 287 } 288 289 return 0; 290 } 291 292 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 293 | ((prod) << PCI_PRODUCT_SHIFT)) 294 295 const struct yenta_chipinfo { 296 pcireg_t yc_id; /* vendor tag | product tag */ 297 int yc_chiptype; 298 int yc_flags; 299 } yc_chipsets[] = { 300 /* Texas Instruments chips */ 301 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 302 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 303 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 304 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 305 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI125X, 306 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 307 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 308 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 309 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 310 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 311 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 312 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 313 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI125X, 314 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 315 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI125X, 316 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 317 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 318 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 319 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 320 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 321 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 322 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 323 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI125X, 324 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 325 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 326 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 327 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1520), CB_TI12XX, 328 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 329 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4410YENTA), CB_TI12XX, 330 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 331 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4520YENTA), CB_TI12XX, 332 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 333 334 /* Ricoh chips */ 335 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 336 PCCBB_PCMCIA_MEM_32}, 337 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 338 PCCBB_PCMCIA_MEM_32}, 339 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 340 PCCBB_PCMCIA_MEM_32}, 341 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 342 PCCBB_PCMCIA_MEM_32}, 343 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 344 PCCBB_PCMCIA_MEM_32}, 345 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 346 PCCBB_PCMCIA_MEM_32}, 347 348 /* Toshiba products */ 349 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 350 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 351 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 352 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 353 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 354 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 355 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 356 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 357 358 /* Cirrus Logic products */ 359 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 360 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 361 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 362 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 363 364 /* sentinel, or Generic chip */ 365 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 366 }; 367 368 static int 369 cb_chipset(pci_id, flagp) 370 u_int32_t pci_id; 371 int *flagp; 372 { 373 const struct yenta_chipinfo *yc; 374 375 /* Loop over except the last default entry. */ 376 for (yc = yc_chipsets; yc < yc_chipsets + 377 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 378 if (pci_id == yc->yc_id) 379 break; 380 381 if (flagp != NULL) 382 *flagp = yc->yc_flags; 383 384 return (yc->yc_chiptype); 385 } 386 387 static void 388 pccbb_shutdown(void *arg) 389 { 390 struct pccbb_softc *sc = arg; 391 pcireg_t command; 392 393 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 394 395 /* 396 * turn off power 397 * 398 * XXX - do not turn off power if chipset is TI 113X because 399 * only TI 1130 with PowerMac 2400 hangs in pccbb_power(). 400 */ 401 if (sc->sc_chipset != CB_TI113X) { 402 pccbb_power((cardbus_chipset_tag_t)sc, 403 CARDBUS_VCC_0V | CARDBUS_VPP_0V); 404 } 405 406 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 407 0); 408 409 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 410 411 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 412 PCI_COMMAND_MASTER_ENABLE); 413 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 414 415 } 416 417 void 418 pccbbattach(struct device *parent, struct device *self, void *aux) 419 { 420 struct pccbb_softc *sc = (void *)self; 421 struct pci_attach_args *pa = aux; 422 pci_chipset_tag_t pc = pa->pa_pc; 423 pcireg_t busreg, reg, sock_base; 424 bus_addr_t sockbase; 425 char devinfo[256]; 426 int flags; 427 int pwrmgt_offs; 428 429 #ifdef __HAVE_PCCBB_ATTACH_HOOK 430 pccbb_attach_hook(parent, self, pa); 431 #endif 432 433 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 434 435 pci_devinfo(pa->pa_id, 0, 0, devinfo, sizeof(devinfo)); 436 printf(": %s (rev. 0x%02x)", devinfo, PCI_REVISION(pa->pa_class)); 437 DPRINTF((" (chipflags %x)", flags)); 438 printf("\n"); 439 440 TAILQ_INIT(&sc->sc_memwindow); 441 TAILQ_INIT(&sc->sc_iowindow); 442 443 #if rbus 444 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 445 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 446 447 #if 0 448 printf("pa->pa_memt: %08x vs rbus_mem->rb_bt: %08x\n", 449 pa->pa_memt, sc->sc_rbus_memt->rb_bt); 450 #endif 451 #endif /* rbus */ 452 453 sc->sc_flags &= ~CBB_MEMHMAPPED; 454 455 /* power management: set D0 state */ 456 sc->sc_pwrmgt_offs = 0; 457 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, 458 &pwrmgt_offs, 0)) { 459 reg = pci_conf_read(pc, pa->pa_tag, pwrmgt_offs + PCI_PMCSR); 460 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 461 reg & 0x100 /* PCI_PMCSR_PME_EN */) { 462 reg &= ~PCI_PMCSR_STATE_MASK; 463 reg |= PCI_PMCSR_STATE_D0; 464 reg &= ~(0x100 /* PCI_PMCSR_PME_EN */); 465 pci_conf_write(pc, pa->pa_tag, 466 pwrmgt_offs + PCI_PMCSR, reg); 467 } 468 469 sc->sc_pwrmgt_offs = pwrmgt_offs; 470 } 471 472 /* 473 * MAP socket registers and ExCA registers on memory-space 474 * When no valid address is set on socket base registers (on pci 475 * config space), get it not polite way. 476 */ 477 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 478 479 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 480 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 481 /* The address must be valid. */ 482 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 483 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL)) { 484 printf("%s: can't map socket base address 0x%lx\n", 485 sc->sc_dev.dv_xname, (unsigned long)sock_base); 486 /* 487 * I think it's funny: socket base registers must be 488 * mapped on memory space, but ... 489 */ 490 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 491 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 492 NULL)) { 493 printf("%s: can't map socket base address" 494 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 495 (unsigned long)sockbase); 496 /* give up... allocate reg space via rbus. */ 497 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 498 } else 499 sc->sc_flags |= CBB_MEMHMAPPED; 500 } else { 501 DPRINTF(("%s: socket base address 0x%lx\n", 502 sc->sc_dev.dv_xname, (unsigned long)sockbase)); 503 sc->sc_flags |= CBB_MEMHMAPPED; 504 } 505 } 506 507 sc->sc_mem_start = 0; /* XXX */ 508 sc->sc_mem_end = 0xffffffff; /* XXX */ 509 510 /* 511 * When interrupt isn't routed correctly, give up probing cbb and do 512 * not kill pcic-compatible port. 513 * 514 * However, if we are using an ioapic, avoid this check -- pa_intrline 515 * may well be zero, with the interrupt routed through the apic. 516 */ 517 518 #if NIOAPIC == 0 && NACPI == 0 519 if ((0 == pa->pa_intrline) || (255 == pa->pa_intrline)) { 520 printf("%s: NOT USED because of unconfigured interrupt\n", 521 sc->sc_dev.dv_xname); 522 return; 523 } 524 #endif 525 526 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 527 528 /* pccbb_machdep.c end */ 529 530 #if defined CBB_DEBUG 531 { 532 static const char *intrname[] = { "NON", "A", "B", "C", "D" }; 533 printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname, 534 intrname[pa->pa_intrpin], pa->pa_intrline); 535 } 536 #endif 537 538 /* setup softc */ 539 sc->sc_pc = pc; 540 sc->sc_iot = pa->pa_iot; 541 sc->sc_memt = pa->pa_memt; 542 sc->sc_dmat = pa->pa_dmat; 543 sc->sc_tag = pa->pa_tag; 544 sc->sc_function = pa->pa_function; 545 sc->sc_sockbase = sock_base; 546 sc->sc_busnum = busreg; 547 548 memcpy(&sc->sc_pa, pa, sizeof(*pa)); 549 550 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 551 552 shutdownhook_establish(pccbb_shutdown, sc); 553 554 /* Disable legacy register mapping. */ 555 switch (sc->sc_chipset) { 556 case CB_RX5C46X: /* fallthrough */ 557 #if 0 558 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 559 case CB_RX5C47X: 560 #endif 561 /* 562 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 563 * cannot be disabled by substituting 0 into PCI_LEGACY 564 * register. Ricoh CardBus bridges have special bits on Bridge 565 * control reg (addr 0x3e on PCI config space). 566 */ 567 reg = pci_conf_read(pc, pa->pa_tag, PCI_BCR_INTR); 568 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 569 pci_conf_write(pc, pa->pa_tag, PCI_BCR_INTR, reg); 570 break; 571 572 default: 573 /* XXX I don't know proper way to kill legacy I/O. */ 574 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 575 break; 576 } 577 578 config_defer(self, pccbb_pci_callback); 579 } 580 581 582 583 584 /* 585 * static void pccbb_pci_callback(struct device *self) 586 * 587 * The actual attach routine: get memory space for YENTA register 588 * space, setup YENTA register and route interrupt. 589 * 590 * This function should be deferred because this device may obtain 591 * memory space dynamically. This function must avoid obtaining 592 * memory area which has already kept for another device. 593 */ 594 static void 595 pccbb_pci_callback(self) 596 struct device *self; 597 { 598 struct pccbb_softc *sc = (void *)self; 599 pci_chipset_tag_t pc = sc->sc_pc; 600 pci_intr_handle_t ih; 601 const char *intrstr = NULL; 602 bus_addr_t sockbase; 603 struct cbslot_attach_args cba; 604 struct pcmciabus_attach_args paa; 605 struct cardslot_attach_args caa; 606 struct cardslot_softc *csc; 607 608 if (!(sc->sc_flags & CBB_MEMHMAPPED)) { 609 /* The socket registers aren't mapped correctly. */ 610 #if rbus 611 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 612 (sc->sc_chipset == CB_RX5C47X 613 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 614 0, &sockbase, &sc->sc_base_memh)) { 615 return; 616 } 617 sc->sc_base_memt = sc->sc_memt; 618 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 619 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 620 sc->sc_dev.dv_xname, (unsigned long)sockbase, 621 (unsigned long)pci_conf_read(pc, sc->sc_tag, 622 PCI_SOCKBASE))); 623 #else 624 sc->sc_base_memt = sc->sc_memt; 625 #if !defined CBB_PCI_BASE 626 #define CBB_PCI_BASE 0x20000000 627 #endif 628 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 629 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 630 /* cannot allocate memory space */ 631 return; 632 } 633 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 634 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 635 sc->sc_dev.dv_xname, (unsigned long)sock_base, 636 (unsigned long)pci_conf_read(pc, 637 sc->sc_tag, PCI_SOCKBASE))); 638 sc->sc_sockbase = sockbase; 639 #endif 640 sc->sc_flags |= CBB_MEMHMAPPED; 641 } 642 643 /* bus bridge initialization */ 644 pccbb_chipinit(sc); 645 646 /* clear data structure for child device interrupt handlers */ 647 LIST_INIT(&sc->sc_pil); 648 sc->sc_pil_intr_enable = 1; 649 650 /* Map and establish the interrupt. */ 651 if (pci_intr_map(&sc->sc_pa, &ih)) { 652 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 653 return; 654 } 655 intrstr = pci_intr_string(pc, ih); 656 657 /* 658 * XXX pccbbintr should be called under the priority lower 659 * than any other hard interupts. 660 */ 661 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 662 663 if (sc->sc_ih == NULL) { 664 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 665 if (intrstr != NULL) { 666 printf(" at %s", intrstr); 667 } 668 printf("\n"); 669 return; 670 } 671 672 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 673 powerhook_establish(sc->sc_dev.dv_xname, pccbb_powerhook, sc); 674 675 { 676 u_int32_t sockstat; 677 678 sockstat = bus_space_read_4(sc->sc_base_memt, 679 sc->sc_base_memh, CB_SOCKET_STAT); 680 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 681 sc->sc_flags |= CBB_CARDEXIST; 682 } 683 } 684 685 /* 686 * attach cardbus 687 */ 688 { 689 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 690 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 691 692 /* initialize cbslot_attach */ 693 cba.cba_busname = "cardbus"; 694 cba.cba_iot = sc->sc_iot; 695 cba.cba_memt = sc->sc_memt; 696 cba.cba_dmat = sc->sc_dmat; 697 cba.cba_bus = (busreg >> 8) & 0x0ff; 698 cba.cba_cc = (void *)sc; 699 cba.cba_cf = &pccbb_funcs; 700 cba.cba_intrline = sc->sc_pa.pa_intrline; 701 702 #if rbus 703 cba.cba_rbus_iot = sc->sc_rbus_iot; 704 cba.cba_rbus_memt = sc->sc_rbus_memt; 705 #endif 706 707 cba.cba_cacheline = PCI_CACHELINE(bhlc); 708 cba.cba_lattimer = PCI_CB_LATENCY(busreg); 709 710 if (bootverbose) { 711 printf("%s: cacheline 0x%x lattimer 0x%x\n", 712 sc->sc_dev.dv_xname, cba.cba_cacheline, 713 cba.cba_lattimer); 714 printf("%s: bhlc 0x%x lscp 0x%x\n", 715 sc->sc_dev.dv_xname, bhlc, busreg); 716 } 717 #if defined SHOW_REGS 718 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 719 sc->sc_base_memh); 720 #endif 721 } 722 723 pccbb_pcmcia_attach_setup(sc, &paa); 724 caa.caa_cb_attach = NULL; 725 if (cba.cba_bus == 0) 726 printf("%s: secondary bus number uninitialized; try PCI_BUS_FIXUP\n", sc->sc_dev.dv_xname); 727 else 728 caa.caa_cb_attach = &cba; 729 caa.caa_16_attach = &paa; 730 caa.caa_ph = &sc->sc_pcmcia_h; 731 732 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 733 DPRINTF(("%s: found cardslot\n", __func__)); 734 sc->sc_csc = csc; 735 } 736 737 return; 738 } 739 740 741 742 743 744 /* 745 * static void pccbb_chipinit(struct pccbb_softc *sc) 746 * 747 * This function initialize YENTA chip registers listed below: 748 * 1) PCI command reg, 749 * 2) PCI and CardBus latency timer, 750 * 3) route PCI interrupt, 751 * 4) close all memory and io windows. 752 * 5) turn off bus power. 753 * 6) card detect and power cycle interrupts on. 754 * 7) clear interrupt 755 */ 756 static void 757 pccbb_chipinit(sc) 758 struct pccbb_softc *sc; 759 { 760 pci_chipset_tag_t pc = sc->sc_pc; 761 pcitag_t tag = sc->sc_tag; 762 bus_space_tag_t bmt = sc->sc_base_memt; 763 bus_space_handle_t bmh = sc->sc_base_memh; 764 pcireg_t reg; 765 766 /* 767 * Set PCI command reg. 768 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 769 */ 770 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 771 /* I believe it is harmless. */ 772 reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 773 PCI_COMMAND_MASTER_ENABLE); 774 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg); 775 776 /* 777 * Set CardBus latency timer. 778 */ 779 reg = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 780 if (PCI_CB_LATENCY(reg) < 0x20) { 781 reg &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 782 reg |= (0x20 << PCI_CB_LATENCY_SHIFT); 783 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, reg); 784 } 785 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 786 PCI_CB_LATENCY(reg), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 787 788 /* 789 * Set PCI latency timer. 790 */ 791 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 792 if (PCI_LATTIMER(reg) < 0x10) { 793 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 794 reg |= (0x10 << PCI_LATTIMER_SHIFT); 795 pci_conf_write(pc, tag, PCI_BHLC_REG, reg); 796 } 797 DPRINTF(("PCI latency timer 0x%x (%x)\n", 798 PCI_LATTIMER(reg), pci_conf_read(pc, tag, PCI_BHLC_REG))); 799 800 801 /* Route functional interrupts to PCI. */ 802 reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 803 reg |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 804 reg |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 805 reg |= CB_BCR_RESET_ENABLE; /* assert reset */ 806 pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 807 808 switch (sc->sc_chipset) { 809 case CB_TI113X: 810 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 811 /* This bit is shared, but may read as 0 on some chips, so set 812 it explicitly on both functions. */ 813 reg |= PCI113X_CBCTRL_PCI_IRQ_ENA; 814 /* CSC intr enable */ 815 reg |= PCI113X_CBCTRL_PCI_CSC; 816 /* functional intr prohibit | prohibit ISA routing */ 817 reg &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 818 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 819 break; 820 821 case CB_TI12XX: 822 /* 823 * Some TI 12xx (and [14][45]xx) based pci cards 824 * sometimes have issues with the MFUNC register not 825 * being initialized due to a bad EEPROM on board. 826 * Laptops that this matters on have this register 827 * properly initialized. 828 * 829 * The TI125X parts have a different register. 830 */ 831 reg = pci_conf_read(pc, tag, PCI12XX_MFUNC); 832 if (reg == 0) { 833 reg &= ~PCI12XX_MFUNC_PIN0; 834 reg |= PCI12XX_MFUNC_PIN0_INTA; 835 if ((pci_conf_read(pc, tag, PCI_SYSCTRL) & 836 PCI12XX_SYSCTRL_INTRTIE) == 0) { 837 reg &= ~PCI12XX_MFUNC_PIN1; 838 reg |= PCI12XX_MFUNC_PIN1_INTB; 839 } 840 pci_conf_write(pc, tag, PCI12XX_MFUNC, reg); 841 } 842 /* fallthrough */ 843 844 case CB_TI125X: 845 /* 846 * Disable zoom video. Some machines initialize this 847 * improperly and experience has shown that this helps 848 * prevent strange behavior. 849 */ 850 pci_conf_write(pc, tag, PCI12XX_MMCTRL, 0); 851 852 reg = pci_conf_read(pc, tag, PCI_SYSCTRL); 853 reg |= PCI12XX_SYSCTRL_VCCPROT; 854 pci_conf_write(pc, tag, PCI_SYSCTRL, reg); 855 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 856 reg |= PCI12XX_CBCTRL_CSC; 857 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 858 break; 859 860 case CB_TOPIC95B: 861 reg = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 862 reg |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 863 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, reg); 864 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 865 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 866 sc->sc_dev.dv_xname, reg)); 867 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 868 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 869 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 870 DPRINTF(("0x%x\n", reg)); 871 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 872 break; 873 874 case CB_TOPIC97: 875 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 876 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 877 sc->sc_dev.dv_xname, reg)); 878 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 879 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 880 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 881 reg |= TOPIC97_SLOT_CTRL_PCIINT; 882 reg &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 883 DPRINTF(("0x%x\n", reg)); 884 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 885 /* make sure to assert LV card support bits */ 886 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 887 0x800 + 0x3e, 888 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 889 0x800 + 0x3e) | 0x03); 890 break; 891 } 892 893 /* Close all memory and I/O windows. */ 894 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 895 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 896 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 897 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 898 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 899 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 900 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 901 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 902 903 /* reset 16-bit pcmcia bus */ 904 bus_space_write_1(bmt, bmh, 0x800 + PCIC_INTR, 905 bus_space_read_1(bmt, bmh, 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 906 907 /* turn off power */ 908 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 909 910 /* CSC Interrupt: Card detect and power cycle interrupts on */ 911 reg = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 912 reg |= CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; 913 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, reg); 914 /* reset interrupt */ 915 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 916 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 917 } 918 919 920 921 922 /* 923 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 924 * struct pcmciabus_attach_args *paa) 925 * 926 * This function attaches 16-bit PCcard bus. 927 */ 928 STATIC void 929 pccbb_pcmcia_attach_setup(sc, paa) 930 struct pccbb_softc *sc; 931 struct pcmciabus_attach_args *paa; 932 { 933 struct pcic_handle *ph = &sc->sc_pcmcia_h; 934 #if rbus 935 rbus_tag_t rb; 936 #endif 937 938 /* initialize pcmcia part in pccbb_softc */ 939 ph->ph_parent = (struct device *)sc; 940 ph->sock = sc->sc_function; 941 ph->flags = 0; 942 ph->shutdown = 0; 943 ph->ih_irq = sc->sc_pa.pa_intrline; 944 ph->ph_bus_t = sc->sc_base_memt; 945 ph->ph_bus_h = sc->sc_base_memh; 946 ph->ph_read = pccbb_pcmcia_read; 947 ph->ph_write = pccbb_pcmcia_write; 948 sc->sc_pct = &pccbb_pcmcia_funcs; 949 950 /* 951 * We need to do a few things here: 952 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 953 * setting the IRQ numbers to 0. 954 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 955 * routing of CSC interrupts (e.g. card removal) to PCI while in 956 * PCMCIA mode. We just leave this set all the time. 957 * 3) Enable card insertion/removal interrupts in case the chip also 958 * needs that while in PCMCIA mode. 959 * 4) Clear any pending CSC interrupt. 960 */ 961 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE); 962 if (sc->sc_chipset == CB_TI113X) { 963 Pcic_write(ph, PCIC_CSC_INTR, 0); 964 } else { 965 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 966 Pcic_read(ph, PCIC_CSC); 967 } 968 969 /* initialize pcmcia bus attachment */ 970 paa->paa_busname = "pcmcia"; 971 paa->pct = sc->sc_pct; 972 paa->pch = ph; 973 paa->iobase = 0; /* I don't use them */ 974 paa->iosize = 0; 975 #if rbus 976 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 977 paa->iobase = rb->rb_start + rb->rb_offset; 978 paa->iosize = rb->rb_end - rb->rb_start; 979 #endif 980 981 return; 982 } 983 984 #if 0 985 STATIC void 986 pccbb_pcmcia_attach_card(ph) 987 struct pcic_handle *ph; 988 { 989 if (ph->flags & PCIC_FLAG_CARDP) { 990 panic("pccbb_pcmcia_attach_card: already attached"); 991 } 992 993 /* call the MI attach function */ 994 pcmcia_card_attach(ph->pcmcia); 995 996 ph->flags |= PCIC_FLAG_CARDP; 997 } 998 999 STATIC void 1000 pccbb_pcmcia_detach_card(ph, flags) 1001 struct pcic_handle *ph; 1002 int flags; 1003 { 1004 if (!(ph->flags & PCIC_FLAG_CARDP)) { 1005 panic("pccbb_pcmcia_detach_card: already detached"); 1006 } 1007 1008 ph->flags &= ~PCIC_FLAG_CARDP; 1009 1010 /* call the MI detach function */ 1011 pcmcia_card_detach(ph->pcmcia, flags); 1012 } 1013 #endif 1014 1015 /* 1016 * int pccbbintr(arg) 1017 * void *arg; 1018 * This routine handles the interrupt from Yenta PCI-CardBus bridge 1019 * itself. 1020 */ 1021 int 1022 pccbbintr(arg) 1023 void *arg; 1024 { 1025 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1026 u_int32_t sockevent, sockstate; 1027 bus_space_tag_t memt = sc->sc_base_memt; 1028 bus_space_handle_t memh = sc->sc_base_memh; 1029 struct pcic_handle *ph = &sc->sc_pcmcia_h; 1030 1031 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 1032 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 1033 Pcic_read(ph, PCIC_CSC); 1034 1035 if (sockevent == 0) { 1036 /* This intr is not for me: it may be for my child devices. */ 1037 if (sc->sc_pil_intr_enable) { 1038 return pccbbintr_function(sc); 1039 } else { 1040 return 0; 1041 } 1042 } 1043 1044 if (sockevent & CB_SOCKET_EVENT_CD) { 1045 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1046 if (0x00 != (sockstate & CB_SOCKET_STAT_CD)) { 1047 /* A card should be removed. */ 1048 if (sc->sc_flags & CBB_CARDEXIST) { 1049 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 1050 sockevent)); 1051 DPRINTF((" card removed, 0x%08x\n", sockstate)); 1052 sc->sc_flags &= ~CBB_CARDEXIST; 1053 if (sc->sc_csc->sc_status & 1054 CARDSLOT_STATUS_CARD_16) { 1055 #if 0 1056 struct pcic_handle *ph = 1057 &sc->sc_pcmcia_h; 1058 1059 pcmcia_card_deactivate(ph->pcmcia); 1060 pccbb_pcmcia_socket_disable(ph); 1061 pccbb_pcmcia_detach_card(ph, 1062 DETACH_FORCE); 1063 #endif 1064 cardslot_event_throw(sc->sc_csc, 1065 CARDSLOT_EVENT_REMOVAL_16); 1066 } else if (sc->sc_csc->sc_status & 1067 CARDSLOT_STATUS_CARD_CB) { 1068 /* Cardbus intr removed */ 1069 cardslot_event_throw(sc->sc_csc, 1070 CARDSLOT_EVENT_REMOVAL_CB); 1071 } 1072 } else if (sc->sc_flags & CBB_INSERTING) { 1073 sc->sc_flags &= ~CBB_INSERTING; 1074 callout_stop(&sc->sc_insert_ch); 1075 } 1076 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 1077 /* 1078 * The pccbbintr may called from powerdown hook when 1079 * the system resumed, to detect the card 1080 * insertion/removal during suspension. 1081 */ 1082 (sc->sc_flags & CBB_CARDEXIST) == 0) { 1083 if (sc->sc_flags & CBB_INSERTING) { 1084 callout_stop(&sc->sc_insert_ch); 1085 } 1086 callout_reset(&sc->sc_insert_ch, hz / 5, 1087 pci113x_insert, sc); 1088 sc->sc_flags |= CBB_INSERTING; 1089 } 1090 } 1091 1092 if (sockevent & CB_SOCKET_EVENT_POWER) { 1093 DPRINTF(("Powercycling because of socket event\n")); 1094 /* XXX: Does not happen when attaching a 16-bit card */ 1095 sc->sc_pwrcycle++; 1096 wakeup(&sc->sc_pwrcycle); 1097 } 1098 1099 return (1); 1100 } 1101 1102 /* 1103 * static int pccbbintr_function(struct pccbb_softc *sc) 1104 * 1105 * This function calls each interrupt handler registered at the 1106 * bridge. The interrupt handlers are called in registered order. 1107 */ 1108 static int 1109 pccbbintr_function(sc) 1110 struct pccbb_softc *sc; 1111 { 1112 int retval = 0, val; 1113 struct pccbb_intrhand_list *pil; 1114 int s; 1115 1116 for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1117 pil = LIST_NEXT(pil, pil_next)) { 1118 s = splraiseipl(pil->pil_icookie); 1119 val = (*pil->pil_func)(pil->pil_arg); 1120 splx(s); 1121 1122 retval = retval == 1 ? 1 : 1123 retval == 0 ? val : val != 0 ? val : retval; 1124 } 1125 1126 return retval; 1127 } 1128 1129 static void 1130 pci113x_insert(arg) 1131 void *arg; 1132 { 1133 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1134 u_int32_t sockevent, sockstate; 1135 1136 if (!(sc->sc_flags & CBB_INSERTING)) { 1137 /* We add a card only under inserting state. */ 1138 return; 1139 } 1140 sc->sc_flags &= ~CBB_INSERTING; 1141 1142 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1143 CB_SOCKET_EVENT); 1144 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1145 CB_SOCKET_STAT); 1146 1147 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1148 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1149 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1150 sc->sc_flags |= CBB_CARDEXIST; 1151 /* call pccard interrupt handler here */ 1152 if (sockstate & CB_SOCKET_STAT_16BIT) { 1153 /* 16-bit card found */ 1154 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1155 cardslot_event_throw(sc->sc_csc, 1156 CARDSLOT_EVENT_INSERTION_16); 1157 } else if (sockstate & CB_SOCKET_STAT_CB) { 1158 /* cardbus card found */ 1159 /* cardbus_attach_card(sc->sc_csc); */ 1160 cardslot_event_throw(sc->sc_csc, 1161 CARDSLOT_EVENT_INSERTION_CB); 1162 } else { 1163 /* who are you? */ 1164 } 1165 } else { 1166 callout_reset(&sc->sc_insert_ch, hz / 10, 1167 pci113x_insert, sc); 1168 } 1169 } 1170 1171 #define PCCBB_PCMCIA_OFFSET 0x800 1172 static u_int8_t 1173 pccbb_pcmcia_read(ph, reg) 1174 struct pcic_handle *ph; 1175 int reg; 1176 { 1177 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1178 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1179 1180 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1181 PCCBB_PCMCIA_OFFSET + reg); 1182 } 1183 1184 static void 1185 pccbb_pcmcia_write(ph, reg, val) 1186 struct pcic_handle *ph; 1187 int reg; 1188 u_int8_t val; 1189 { 1190 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1191 val); 1192 1193 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1194 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1195 } 1196 1197 /* 1198 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1199 */ 1200 STATIC int 1201 pccbb_ctrl(ct, command) 1202 cardbus_chipset_tag_t ct; 1203 int command; 1204 { 1205 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1206 1207 switch (command) { 1208 case CARDBUS_CD: 1209 if (2 == pccbb_detect_card(sc)) { 1210 int retval = 0; 1211 int status = cb_detect_voltage(sc); 1212 if (PCCARD_VCC_5V & status) { 1213 retval |= CARDBUS_5V_CARD; 1214 } 1215 if (PCCARD_VCC_3V & status) { 1216 retval |= CARDBUS_3V_CARD; 1217 } 1218 if (PCCARD_VCC_XV & status) { 1219 retval |= CARDBUS_XV_CARD; 1220 } 1221 if (PCCARD_VCC_YV & status) { 1222 retval |= CARDBUS_YV_CARD; 1223 } 1224 return retval; 1225 } else { 1226 return 0; 1227 } 1228 case CARDBUS_RESET: 1229 return cb_reset(sc); 1230 case CARDBUS_IO_ENABLE: /* fallthrough */ 1231 case CARDBUS_IO_DISABLE: /* fallthrough */ 1232 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1233 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1234 case CARDBUS_BM_ENABLE: /* fallthrough */ 1235 case CARDBUS_BM_DISABLE: /* fallthrough */ 1236 /* XXX: I think we don't need to call this function below. */ 1237 return pccbb_cardenable(sc, command); 1238 } 1239 1240 return 0; 1241 } 1242 1243 /* 1244 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1245 * This function returns true when it succeeds and returns false when 1246 * it fails. 1247 */ 1248 STATIC int 1249 pccbb_power(ct, command) 1250 cardbus_chipset_tag_t ct; 1251 int command; 1252 { 1253 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1254 u_int32_t status, sock_ctrl, reg_ctrl; 1255 bus_space_tag_t memt = sc->sc_base_memt; 1256 bus_space_handle_t memh = sc->sc_base_memh; 1257 int on = 0, pwrcycle; 1258 1259 DPRINTF(("pccbb_power: %s and %s [0x%x]\n", 1260 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1261 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1262 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1263 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1264 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1265 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1266 "UNKNOWN", 1267 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1268 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1269 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1270 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1271 "UNKNOWN", command)); 1272 1273 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1274 sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1275 1276 switch (command & CARDBUS_VCCMASK) { 1277 case CARDBUS_VCC_UC: 1278 break; 1279 case CARDBUS_VCC_5V: 1280 on++; 1281 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1282 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1283 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1284 } else { 1285 printf("%s: BAD voltage request: no 5 V card\n", 1286 sc->sc_dev.dv_xname); 1287 return 0; 1288 } 1289 break; 1290 case CARDBUS_VCC_3V: 1291 on++; 1292 if (CB_SOCKET_STAT_3VCARD & status) { 1293 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1294 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1295 } else { 1296 printf("%s: BAD voltage request: no 3.3 V card\n", 1297 sc->sc_dev.dv_xname); 1298 return 0; 1299 } 1300 break; 1301 case CARDBUS_VCC_0V: 1302 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1303 break; 1304 default: 1305 return 0; /* power NEVER changed */ 1306 } 1307 1308 switch (command & CARDBUS_VPPMASK) { 1309 case CARDBUS_VPP_UC: 1310 break; 1311 case CARDBUS_VPP_0V: 1312 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1313 break; 1314 case CARDBUS_VPP_VCC: 1315 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1316 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1317 break; 1318 case CARDBUS_VPP_12V: 1319 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1320 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1321 break; 1322 } 1323 1324 pwrcycle = sc->sc_pwrcycle; 1325 1326 #if 0 1327 DPRINTF(("sock_ctrl: 0x%x\n", sock_ctrl)); 1328 #endif 1329 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1330 1331 if (on) { 1332 int s, error = 0; 1333 struct timeval before, after, diff; 1334 1335 DPRINTF(("Waiting for bridge to power up\n")); 1336 microtime(&before); 1337 s = splbio(); 1338 while (pwrcycle == sc->sc_pwrcycle) { 1339 /* 1340 * XXX: Set timeout to 200ms because power cycle event 1341 * will never happen when attaching a 16-bit card. 1342 */ 1343 if ((error = tsleep(&sc->sc_pwrcycle, PWAIT, "pccpwr", 1344 hz / 5)) == EWOULDBLOCK) 1345 break; 1346 } 1347 splx(s); 1348 microtime(&after); 1349 timersub(&after, &before, &diff); 1350 aprint_debug("%s: wait took%s %ld.%06lds\n", 1351 sc->sc_dev.dv_xname, 1352 error == EWOULDBLOCK ? " too long" : "", 1353 diff.tv_sec, diff.tv_usec); 1354 1355 /* 1356 * Ok, wait a bit longer for things to settle. 1357 */ 1358 if (sc->sc_chipset == CB_TOPIC95B) 1359 delay_ms(100, sc); 1360 } 1361 1362 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1363 1364 if (on && sc->sc_chipset != CB_TOPIC95B) { 1365 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0) 1366 printf("%s: power on failed?\n", sc->sc_dev.dv_xname); 1367 } 1368 1369 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1370 printf("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1371 sc->sc_dev.dv_xname, sock_ctrl, status); 1372 printf("%s: disabling socket\n", sc->sc_dev.dv_xname); 1373 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1374 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1375 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1376 status &= ~CB_SOCKET_STAT_BADVCC; 1377 bus_space_write_4(memt, memh, CB_SOCKET_STAT, status); 1378 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1379 CB_SOCKET_STAT)); 1380 return 0; 1381 } 1382 1383 if (sc->sc_chipset == CB_TOPIC97) { 1384 reg_ctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL); 1385 reg_ctrl &= ~TOPIC97_REG_CTRL_TESTMODE; 1386 if ((command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V) 1387 reg_ctrl &= ~TOPIC97_REG_CTRL_CLKRUN_ENA; 1388 else 1389 reg_ctrl |= TOPIC97_REG_CTRL_CLKRUN_ENA; 1390 pci_conf_write(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL, reg_ctrl); 1391 } 1392 1393 return 1; /* power changed correctly */ 1394 } 1395 1396 #if defined CB_PCMCIA_POLL 1397 struct cb_poll_str { 1398 void *arg; 1399 int (*func)(void *); 1400 int level; 1401 pccard_chipset_tag_t ct; 1402 int count; 1403 struct callout poll_ch; 1404 }; 1405 1406 static struct cb_poll_str cb_poll[10]; 1407 static int cb_poll_n = 0; 1408 1409 static void cb_pcmcia_poll(void *arg); 1410 1411 static void 1412 cb_pcmcia_poll(arg) 1413 void *arg; 1414 { 1415 struct cb_poll_str *poll = arg; 1416 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1417 struct pccbb_softc *sc = psc->cpc_parent; 1418 int s; 1419 u_int32_t spsr; /* socket present-state reg */ 1420 1421 callout_reset(&poll->poll_ch, hz / 10, cb_pcmcia_poll, poll); 1422 switch (poll->level) { 1423 case IPL_NET: 1424 s = splnet(); 1425 break; 1426 case IPL_BIO: 1427 s = splbio(); 1428 break; 1429 case IPL_TTY: /* fallthrough */ 1430 default: 1431 s = spltty(); 1432 break; 1433 } 1434 1435 spsr = 1436 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1437 CB_SOCKET_STAT); 1438 1439 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1440 if (!(spsr & 0x40)) { /* CINT low */ 1441 #else 1442 if (1) { 1443 #endif 1444 if ((*poll->func) (poll->arg) == 1) { 1445 ++poll->count; 1446 printf("intr: reported from poller, 0x%x\n", spsr); 1447 #if defined LEVEL2 1448 } else { 1449 printf("intr: miss! 0x%x\n", spsr); 1450 #endif 1451 } 1452 } 1453 splx(s); 1454 } 1455 #endif /* defined CB_PCMCIA_POLL */ 1456 1457 /* 1458 * static int pccbb_detect_card(struct pccbb_softc *sc) 1459 * return value: 0 if no card exists. 1460 * 1 if 16-bit card exists. 1461 * 2 if cardbus card exists. 1462 */ 1463 static int 1464 pccbb_detect_card(sc) 1465 struct pccbb_softc *sc; 1466 { 1467 bus_space_handle_t base_memh = sc->sc_base_memh; 1468 bus_space_tag_t base_memt = sc->sc_base_memt; 1469 u_int32_t sockstat = 1470 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1471 int retval = 0; 1472 1473 /* CD1 and CD2 asserted */ 1474 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1475 /* card must be present */ 1476 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1477 /* NOTACARD DEASSERTED */ 1478 if (CB_SOCKET_STAT_CB & sockstat) { 1479 /* CardBus mode */ 1480 retval = 2; 1481 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1482 /* 16-bit mode */ 1483 retval = 1; 1484 } 1485 } 1486 } 1487 return retval; 1488 } 1489 1490 /* 1491 * STATIC int cb_reset(struct pccbb_softc *sc) 1492 * This function resets CardBus card. 1493 */ 1494 STATIC int 1495 cb_reset(sc) 1496 struct pccbb_softc *sc; 1497 { 1498 /* 1499 * Reset Assert at least 20 ms 1500 * Some machines request longer duration. 1501 */ 1502 int reset_duration = 1503 (sc->sc_chipset == CB_RX5C47X ? 400 : 50); 1504 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1505 1506 /* Reset bit Assert (bit 6 at 0x3E) */ 1507 bcr |= CB_BCR_RESET_ENABLE; 1508 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1509 delay_ms(reset_duration, sc); 1510 1511 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1512 /* Reset bit Deassert (bit 6 at 0x3E) */ 1513 bcr &= ~CB_BCR_RESET_ENABLE; 1514 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1515 delay_ms(reset_duration, sc); 1516 } 1517 /* No card found on the slot. Keep Reset. */ 1518 return 1; 1519 } 1520 1521 /* 1522 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1523 * This function detect card Voltage. 1524 */ 1525 STATIC int 1526 cb_detect_voltage(sc) 1527 struct pccbb_softc *sc; 1528 { 1529 u_int32_t psr; /* socket present-state reg */ 1530 bus_space_tag_t iot = sc->sc_base_memt; 1531 bus_space_handle_t ioh = sc->sc_base_memh; 1532 int vol = PCCARD_VCC_UKN; /* set 0 */ 1533 1534 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1535 1536 if (0x400u & psr) { 1537 vol |= PCCARD_VCC_5V; 1538 } 1539 if (0x800u & psr) { 1540 vol |= PCCARD_VCC_3V; 1541 } 1542 1543 return vol; 1544 } 1545 1546 STATIC int 1547 cbbprint(void *aux, const char *pcic) 1548 { 1549 #if 0 1550 struct cbslot_attach_args *cba = aux; 1551 1552 if (cba->cba_slot >= 0) { 1553 aprint_normal(" slot %d", cba->cba_slot); 1554 } 1555 #endif 1556 return UNCONF; 1557 } 1558 1559 /* 1560 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1561 * This function enables and disables the card 1562 */ 1563 STATIC int 1564 pccbb_cardenable(sc, function) 1565 struct pccbb_softc *sc; 1566 int function; 1567 { 1568 u_int32_t command = 1569 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1570 1571 DPRINTF(("pccbb_cardenable:")); 1572 switch (function) { 1573 case CARDBUS_IO_ENABLE: 1574 command |= PCI_COMMAND_IO_ENABLE; 1575 break; 1576 case CARDBUS_IO_DISABLE: 1577 command &= ~PCI_COMMAND_IO_ENABLE; 1578 break; 1579 case CARDBUS_MEM_ENABLE: 1580 command |= PCI_COMMAND_MEM_ENABLE; 1581 break; 1582 case CARDBUS_MEM_DISABLE: 1583 command &= ~PCI_COMMAND_MEM_ENABLE; 1584 break; 1585 case CARDBUS_BM_ENABLE: 1586 command |= PCI_COMMAND_MASTER_ENABLE; 1587 break; 1588 case CARDBUS_BM_DISABLE: 1589 command &= ~PCI_COMMAND_MASTER_ENABLE; 1590 break; 1591 default: 1592 return 0; 1593 } 1594 1595 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1596 DPRINTF((" command reg 0x%x\n", command)); 1597 return 1; 1598 } 1599 1600 #if !rbus 1601 /* 1602 * int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1603 */ 1604 static int 1605 pccbb_io_open(ct, win, start, end) 1606 cardbus_chipset_tag_t ct; 1607 int win; 1608 u_int32_t start, end; 1609 { 1610 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1611 int basereg; 1612 int limitreg; 1613 1614 if ((win < 0) || (win > 2)) { 1615 #if defined DIAGNOSTIC 1616 printf("cardbus_io_open: window out of range %d\n", win); 1617 #endif 1618 return 0; 1619 } 1620 1621 basereg = win * 8 + 0x2c; 1622 limitreg = win * 8 + 0x30; 1623 1624 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1625 start, basereg, end, limitreg)); 1626 1627 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1628 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1629 return 1; 1630 } 1631 1632 /* 1633 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1634 */ 1635 static int 1636 pccbb_io_close(ct, win) 1637 cardbus_chipset_tag_t ct; 1638 int win; 1639 { 1640 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1641 int basereg; 1642 int limitreg; 1643 1644 if ((win < 0) || (win > 2)) { 1645 #if defined DIAGNOSTIC 1646 printf("cardbus_io_close: window out of range %d\n", win); 1647 #endif 1648 return 0; 1649 } 1650 1651 basereg = win * 8 + 0x2c; 1652 limitreg = win * 8 + 0x30; 1653 1654 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1655 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1656 return 1; 1657 } 1658 1659 /* 1660 * int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1661 */ 1662 static int 1663 pccbb_mem_open(ct, win, start, end) 1664 cardbus_chipset_tag_t ct; 1665 int win; 1666 u_int32_t start, end; 1667 { 1668 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1669 int basereg; 1670 int limitreg; 1671 1672 if ((win < 0) || (win > 2)) { 1673 #if defined DIAGNOSTIC 1674 printf("cardbus_mem_open: window out of range %d\n", win); 1675 #endif 1676 return 0; 1677 } 1678 1679 basereg = win * 8 + 0x1c; 1680 limitreg = win * 8 + 0x20; 1681 1682 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1683 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1684 return 1; 1685 } 1686 1687 /* 1688 * int pccbb_mem_close(cardbus_chipset_tag_t, int) 1689 */ 1690 static int 1691 pccbb_mem_close(ct, win) 1692 cardbus_chipset_tag_t ct; 1693 int win; 1694 { 1695 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1696 int basereg; 1697 int limitreg; 1698 1699 if ((win < 0) || (win > 2)) { 1700 #if defined DIAGNOSTIC 1701 printf("cardbus_mem_close: window out of range %d\n", win); 1702 #endif 1703 return 0; 1704 } 1705 1706 basereg = win * 8 + 0x1c; 1707 limitreg = win * 8 + 0x20; 1708 1709 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1710 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1711 return 1; 1712 } 1713 #endif 1714 1715 /* 1716 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1717 * int irq, 1718 * int level, 1719 * int (* func)(void *), 1720 * void *arg) 1721 * 1722 * This function registers an interrupt handler at the bridge, in 1723 * order not to call the interrupt handlers of child devices when 1724 * a card-deletion interrupt occurs. 1725 * 1726 * The arguments irq and level are not used. 1727 */ 1728 static void * 1729 pccbb_cb_intr_establish(ct, irq, level, func, arg) 1730 cardbus_chipset_tag_t ct; 1731 int irq, level; 1732 int (*func)(void *); 1733 void *arg; 1734 { 1735 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1736 1737 return pccbb_intr_establish(sc, irq, level, func, arg); 1738 } 1739 1740 1741 /* 1742 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1743 * void *ih) 1744 * 1745 * This function removes an interrupt handler pointed by ih. 1746 */ 1747 static void 1748 pccbb_cb_intr_disestablish(ct, ih) 1749 cardbus_chipset_tag_t ct; 1750 void *ih; 1751 { 1752 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1753 1754 pccbb_intr_disestablish(sc, ih); 1755 } 1756 1757 1758 void 1759 pccbb_intr_route(sc) 1760 struct pccbb_softc *sc; 1761 { 1762 pcireg_t reg; 1763 1764 /* initialize bridge intr routing */ 1765 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1766 reg &= ~CB_BCR_INTR_IREQ_ENABLE; 1767 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1768 1769 switch (sc->sc_chipset) { 1770 case CB_TI113X: 1771 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1772 /* functional intr enabled */ 1773 reg |= PCI113X_CBCTRL_PCI_INTR; 1774 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1775 break; 1776 default: 1777 break; 1778 } 1779 } 1780 1781 /* 1782 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1783 * int irq, 1784 * int level, 1785 * int (* func)(void *), 1786 * void *arg) 1787 * 1788 * This function registers an interrupt handler at the bridge, in 1789 * order not to call the interrupt handlers of child devices when 1790 * a card-deletion interrupt occurs. 1791 * 1792 * The arguments irq is not used because pccbb selects intr vector. 1793 */ 1794 static void * 1795 pccbb_intr_establish(struct pccbb_softc *sc, int irq, int level, 1796 int (*func)(void *), void *arg) 1797 { 1798 struct pccbb_intrhand_list *pil, *newpil; 1799 1800 DPRINTF(("pccbb_intr_establish start. %p\n", LIST_FIRST(&sc->sc_pil))); 1801 1802 if (LIST_EMPTY(&sc->sc_pil)) { 1803 pccbb_intr_route(sc); 1804 } 1805 1806 /* 1807 * Allocate a room for interrupt handler structure. 1808 */ 1809 if (NULL == (newpil = 1810 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1811 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1812 return NULL; 1813 } 1814 1815 newpil->pil_func = func; 1816 newpil->pil_arg = arg; 1817 newpil->pil_icookie = makeiplcookie(level); 1818 1819 if (LIST_EMPTY(&sc->sc_pil)) { 1820 LIST_INSERT_HEAD(&sc->sc_pil, newpil, pil_next); 1821 } else { 1822 for (pil = LIST_FIRST(&sc->sc_pil); 1823 LIST_NEXT(pil, pil_next) != NULL; 1824 pil = LIST_NEXT(pil, pil_next)); 1825 LIST_INSERT_AFTER(pil, newpil, pil_next); 1826 } 1827 1828 DPRINTF(("pccbb_intr_establish add pil. %p\n", 1829 LIST_FIRST(&sc->sc_pil))); 1830 1831 return newpil; 1832 } 1833 1834 /* 1835 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1836 * void *ih) 1837 * 1838 * This function removes an interrupt handler pointed by ih. ih 1839 * should be the value returned by cardbus_intr_establish() or 1840 * NULL. 1841 * 1842 * When ih is NULL, this function will do nothing. 1843 */ 1844 static void 1845 pccbb_intr_disestablish(sc, ih) 1846 struct pccbb_softc *sc; 1847 void *ih; 1848 { 1849 struct pccbb_intrhand_list *pil; 1850 pcireg_t reg; 1851 1852 DPRINTF(("pccbb_intr_disestablish start. %p\n", 1853 LIST_FIRST(&sc->sc_pil))); 1854 1855 if (ih == NULL) { 1856 /* intr handler is not set */ 1857 DPRINTF(("pccbb_intr_disestablish: no ih\n")); 1858 return; 1859 } 1860 1861 #ifdef DIAGNOSTIC 1862 for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1863 pil = LIST_NEXT(pil, pil_next)) { 1864 DPRINTF(("pccbb_intr_disestablish: pil %p\n", pil)); 1865 if (pil == ih) { 1866 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1867 break; 1868 } 1869 } 1870 if (pil == NULL) { 1871 panic("pccbb_intr_disestablish: %s cannot find pil %p", 1872 sc->sc_dev.dv_xname, ih); 1873 } 1874 #endif 1875 1876 pil = (struct pccbb_intrhand_list *)ih; 1877 LIST_REMOVE(pil, pil_next); 1878 free(pil, M_DEVBUF); 1879 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1880 1881 if (LIST_EMPTY(&sc->sc_pil)) { 1882 /* No interrupt handlers */ 1883 1884 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1885 1886 /* stop routing PCI intr */ 1887 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1888 reg |= CB_BCR_INTR_IREQ_ENABLE; 1889 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1890 1891 switch (sc->sc_chipset) { 1892 case CB_TI113X: 1893 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1894 /* functional intr disabled */ 1895 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1896 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1897 break; 1898 default: 1899 break; 1900 } 1901 } 1902 } 1903 1904 #if defined SHOW_REGS 1905 static void 1906 cb_show_regs(pc, tag, memt, memh) 1907 pci_chipset_tag_t pc; 1908 pcitag_t tag; 1909 bus_space_tag_t memt; 1910 bus_space_handle_t memh; 1911 { 1912 int i; 1913 printf("PCI config regs:"); 1914 for (i = 0; i < 0x50; i += 4) { 1915 if (i % 16 == 0) { 1916 printf("\n 0x%02x:", i); 1917 } 1918 printf(" %08x", pci_conf_read(pc, tag, i)); 1919 } 1920 for (i = 0x80; i < 0xb0; i += 4) { 1921 if (i % 16 == 0) { 1922 printf("\n 0x%02x:", i); 1923 } 1924 printf(" %08x", pci_conf_read(pc, tag, i)); 1925 } 1926 1927 if (memh == 0) { 1928 printf("\n"); 1929 return; 1930 } 1931 1932 printf("\nsocket regs:"); 1933 for (i = 0; i <= 0x10; i += 0x04) { 1934 printf(" %08x", bus_space_read_4(memt, memh, i)); 1935 } 1936 printf("\nExCA regs:"); 1937 for (i = 0; i < 0x08; ++i) { 1938 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1939 } 1940 printf("\n"); 1941 return; 1942 } 1943 #endif 1944 1945 /* 1946 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1947 * int busno, int function) 1948 * This is the function to make a tag to access config space of 1949 * a CardBus Card. It works same as pci_conf_read. 1950 */ 1951 static cardbustag_t 1952 pccbb_make_tag(cc, busno, function) 1953 cardbus_chipset_tag_t cc; 1954 int busno, function; 1955 { 1956 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1957 1958 return pci_make_tag(sc->sc_pc, busno, 0, function); 1959 } 1960 1961 static void 1962 pccbb_free_tag(cardbus_chipset_tag_t cc, cardbustag_t tag) 1963 { 1964 } 1965 1966 /* 1967 * static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t cc, 1968 * cardbustag_t tag, int offset) 1969 * This is the function to read the config space of a CardBus Card. 1970 * It works same as pci_conf_read. 1971 */ 1972 static cardbusreg_t 1973 pccbb_conf_read(cc, tag, offset) 1974 cardbus_chipset_tag_t cc; 1975 cardbustag_t tag; 1976 int offset; /* register offset */ 1977 { 1978 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1979 1980 return pci_conf_read(sc->sc_pc, tag, offset); 1981 } 1982 1983 /* 1984 * static void pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, 1985 * int offs, cardbusreg_t val) 1986 * This is the function to write the config space of a CardBus Card. 1987 * It works same as pci_conf_write. 1988 */ 1989 static void 1990 pccbb_conf_write(cc, tag, reg, val) 1991 cardbus_chipset_tag_t cc; 1992 cardbustag_t tag; 1993 int reg; /* register offset */ 1994 cardbusreg_t val; 1995 { 1996 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1997 1998 pci_conf_write(sc->sc_pc, tag, reg, val); 1999 } 2000 2001 #if 0 2002 STATIC int 2003 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 2004 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 2005 int speed, int flags, 2006 bus_space_handle_t * iohp) 2007 #endif 2008 /* 2009 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 2010 * bus_addr_t start, bus_size_t size, 2011 * bus_size_t align, 2012 * struct pcmcia_io_handle *pcihp 2013 * 2014 * This function only allocates I/O region for pccard. This function 2015 * never maps the allocated region to pccard I/O area. 2016 * 2017 * XXX: The interface of this function is not very good, I believe. 2018 */ 2019 STATIC int 2020 pccbb_pcmcia_io_alloc(pch, start, size, align, pcihp) 2021 pcmcia_chipset_handle_t pch; 2022 bus_addr_t start; /* start address */ 2023 bus_size_t size; 2024 bus_size_t align; 2025 struct pcmcia_io_handle *pcihp; 2026 { 2027 struct pcic_handle *ph = (struct pcic_handle *)pch; 2028 bus_addr_t ioaddr; 2029 int flags = 0; 2030 bus_space_tag_t iot; 2031 bus_space_handle_t ioh; 2032 bus_addr_t mask; 2033 #if rbus 2034 rbus_tag_t rb; 2035 #endif 2036 if (align == 0) { 2037 align = size; /* XXX: funny??? */ 2038 } 2039 2040 if (start != 0) { 2041 /* XXX: assume all card decode lower 10 bits by its hardware */ 2042 mask = 0x3ff; 2043 /* enforce to use only masked address */ 2044 start &= mask; 2045 } else { 2046 /* 2047 * calculate mask: 2048 * 1. get the most significant bit of size (call it msb). 2049 * 2. compare msb with the value of size. 2050 * 3. if size is larger, shift msb left once. 2051 * 4. obtain mask value to decrement msb. 2052 */ 2053 bus_size_t size_tmp = size; 2054 int shifts = 0; 2055 2056 mask = 1; 2057 while (size_tmp) { 2058 ++shifts; 2059 size_tmp >>= 1; 2060 } 2061 mask = (1 << shifts); 2062 if (mask < size) { 2063 mask <<= 1; 2064 } 2065 --mask; 2066 } 2067 2068 /* 2069 * Allocate some arbitrary I/O space. 2070 */ 2071 2072 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 2073 2074 #if rbus 2075 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 2076 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 2077 return 1; 2078 } 2079 DPRINTF(("pccbb_pcmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2080 (u_long) ioaddr, (u_long) size)); 2081 #else 2082 if (start) { 2083 ioaddr = start; 2084 if (bus_space_map(iot, start, size, 0, &ioh)) { 2085 return 1; 2086 } 2087 DPRINTF(("pccbb_pcmcia_io_alloc map port 0x%lx+0x%lx\n", 2088 (u_long) ioaddr, (u_long) size)); 2089 } else { 2090 flags |= PCMCIA_IO_ALLOCATED; 2091 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 2092 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 2093 size, align, 0, 0, &ioaddr, &ioh)) { 2094 /* No room be able to be get. */ 2095 return 1; 2096 } 2097 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2098 (u_long) ioaddr, (u_long) size)); 2099 } 2100 #endif 2101 2102 pcihp->iot = iot; 2103 pcihp->ioh = ioh; 2104 pcihp->addr = ioaddr; 2105 pcihp->size = size; 2106 pcihp->flags = flags; 2107 2108 return 0; 2109 } 2110 2111 /* 2112 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2113 * struct pcmcia_io_handle *pcihp) 2114 * 2115 * This function only frees I/O region for pccard. 2116 * 2117 * XXX: The interface of this function is not very good, I believe. 2118 */ 2119 void 2120 pccbb_pcmcia_io_free(pch, pcihp) 2121 pcmcia_chipset_handle_t pch; 2122 struct pcmcia_io_handle *pcihp; 2123 { 2124 #if !rbus 2125 bus_space_tag_t iot = pcihp->iot; 2126 #endif 2127 bus_space_handle_t ioh = pcihp->ioh; 2128 bus_size_t size = pcihp->size; 2129 2130 #if rbus 2131 struct pccbb_softc *sc = 2132 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 2133 rbus_tag_t rb = sc->sc_rbus_iot; 2134 2135 rbus_space_free(rb, ioh, size, NULL); 2136 #else 2137 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 2138 bus_space_free(iot, ioh, size); 2139 else 2140 bus_space_unmap(iot, ioh, size); 2141 #endif 2142 } 2143 2144 /* 2145 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 2146 * bus_addr_t offset, bus_size_t size, 2147 * struct pcmcia_io_handle *pcihp, 2148 * int *windowp) 2149 * 2150 * This function maps the allocated I/O region to pccard. This function 2151 * never allocates any I/O region for pccard I/O area. I don't 2152 * understand why the original authors of pcmciabus separated alloc and 2153 * map. I believe the two must be unite. 2154 * 2155 * XXX: no wait timing control? 2156 */ 2157 int 2158 pccbb_pcmcia_io_map(pch, width, offset, size, pcihp, windowp) 2159 pcmcia_chipset_handle_t pch; 2160 int width; 2161 bus_addr_t offset; 2162 bus_size_t size; 2163 struct pcmcia_io_handle *pcihp; 2164 int *windowp; 2165 { 2166 struct pcic_handle *ph = (struct pcic_handle *)pch; 2167 bus_addr_t ioaddr = pcihp->addr + offset; 2168 int i, win; 2169 #if defined CBB_DEBUG 2170 static const char *width_names[] = { "dynamic", "io8", "io16" }; 2171 #endif 2172 2173 /* Sanity check I/O handle. */ 2174 2175 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 2176 panic("pccbb_pcmcia_io_map iot is bogus"); 2177 } 2178 2179 /* XXX Sanity check offset/size. */ 2180 2181 win = -1; 2182 for (i = 0; i < PCIC_IO_WINS; i++) { 2183 if ((ph->ioalloc & (1 << i)) == 0) { 2184 win = i; 2185 ph->ioalloc |= (1 << i); 2186 break; 2187 } 2188 } 2189 2190 if (win == -1) { 2191 return 1; 2192 } 2193 2194 *windowp = win; 2195 2196 /* XXX this is pretty gross */ 2197 2198 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2199 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2200 2201 /* XXX wtf is this doing here? */ 2202 2203 #if 0 2204 printf(" port 0x%lx", (u_long) ioaddr); 2205 if (size > 1) { 2206 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2207 } 2208 #endif 2209 2210 ph->io[win].addr = ioaddr; 2211 ph->io[win].size = size; 2212 ph->io[win].width = width; 2213 2214 /* actual dirty register-value changing in the function below. */ 2215 pccbb_pcmcia_do_io_map(ph, win); 2216 2217 return 0; 2218 } 2219 2220 /* 2221 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2222 * 2223 * This function changes register-value to map I/O region for pccard. 2224 */ 2225 static void 2226 pccbb_pcmcia_do_io_map(ph, win) 2227 struct pcic_handle *ph; 2228 int win; 2229 { 2230 static u_int8_t pcic_iowidth[3] = { 2231 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2232 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2233 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2234 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2235 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2236 }; 2237 2238 #define PCIC_SIA_START_LOW 0 2239 #define PCIC_SIA_START_HIGH 1 2240 #define PCIC_SIA_STOP_LOW 2 2241 #define PCIC_SIA_STOP_HIGH 3 2242 2243 int regbase_win = 0x8 + win * 0x04; 2244 u_int8_t ioctl, enable; 2245 2246 DPRINTF(("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx " 2247 "width %d\n", win, (unsigned long)ph->io[win].addr, 2248 (unsigned long)ph->io[win].size, ph->io[win].width * 8)); 2249 2250 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2251 ph->io[win].addr & 0xff); 2252 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2253 (ph->io[win].addr >> 8) & 0xff); 2254 2255 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2256 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2257 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2258 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2259 2260 ioctl = Pcic_read(ph, PCIC_IOCTL); 2261 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2262 switch (win) { 2263 case 0: 2264 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2265 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2266 PCIC_IOCTL_IO0_DATASIZE_MASK); 2267 ioctl |= pcic_iowidth[ph->io[win].width]; 2268 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2269 break; 2270 case 1: 2271 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2272 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2273 PCIC_IOCTL_IO1_DATASIZE_MASK); 2274 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2275 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2276 break; 2277 } 2278 Pcic_write(ph, PCIC_IOCTL, ioctl); 2279 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2280 #if defined(CBB_DEBUG) 2281 { 2282 u_int8_t start_low = 2283 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2284 u_int8_t start_high = 2285 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2286 u_int8_t stop_low = 2287 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2288 u_int8_t stop_high = 2289 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2290 printf("pccbb_pcmcia_do_io_map start %02x %02x, " 2291 "stop %02x %02x, ioctl %02x enable %02x\n", 2292 start_low, start_high, stop_low, stop_high, ioctl, enable); 2293 } 2294 #endif 2295 } 2296 2297 /* 2298 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2299 * 2300 * This function unmaps I/O region. No return value. 2301 */ 2302 STATIC void 2303 pccbb_pcmcia_io_unmap(pch, win) 2304 pcmcia_chipset_handle_t pch; 2305 int win; 2306 { 2307 struct pcic_handle *ph = (struct pcic_handle *)pch; 2308 int reg; 2309 2310 if (win >= PCIC_IO_WINS || win < 0) { 2311 panic("pccbb_pcmcia_io_unmap: window out of range"); 2312 } 2313 2314 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2315 switch (win) { 2316 case 0: 2317 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2318 break; 2319 case 1: 2320 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2321 break; 2322 } 2323 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2324 2325 ph->ioalloc &= ~(1 << win); 2326 } 2327 2328 static int 2329 pccbb_pcmcia_wait_ready(ph) 2330 struct pcic_handle *ph; 2331 { 2332 u_int8_t stat; 2333 int i; 2334 2335 /* wait an initial 10ms for quick cards */ 2336 stat = Pcic_read(ph, PCIC_IF_STATUS); 2337 if (stat & PCIC_IF_STATUS_READY) 2338 return (0); 2339 pccbb_pcmcia_delay(ph, 10, "pccwr0"); 2340 for (i = 0; i < 50; i++) { 2341 stat = Pcic_read(ph, PCIC_IF_STATUS); 2342 if (stat & PCIC_IF_STATUS_READY) 2343 return (0); 2344 if ((stat & PCIC_IF_STATUS_CARDDETECT_MASK) != 2345 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2346 return (ENXIO); 2347 /* wait .1s (100ms) each iteration now */ 2348 pccbb_pcmcia_delay(ph, 100, "pccwr1"); 2349 } 2350 2351 printf("pccbb_pcmcia_wait_ready: ready never happened, status=%02x\n", stat); 2352 return (EWOULDBLOCK); 2353 } 2354 2355 /* 2356 * Perform long (msec order) delay. 2357 */ 2358 static void 2359 pccbb_pcmcia_delay( 2360 struct pcic_handle *ph, 2361 int timo, /* in ms. must not be zero */ 2362 const char *wmesg 2363 ) 2364 { 2365 #ifdef DIAGNOSTIC 2366 if (timo <= 0) 2367 panic("pccbb_pcmcia_delay: called with timeout %d", timo); 2368 if (!curlwp) 2369 panic("pccbb_pcmcia_delay: called in interrupt context"); 2370 #if 0 2371 if (!ph->event_thread) 2372 panic("pccbb_pcmcia_delay: no event thread"); 2373 #endif 2374 #endif 2375 DPRINTF(("pccbb_pcmcia_delay: \"%s\" %p, sleep %d ms\n", 2376 wmesg, ph->event_thread, timo)); 2377 tsleep(pccbb_pcmcia_delay, PWAIT, wmesg, roundup(timo * hz, 1000) / 1000); 2378 } 2379 2380 /* 2381 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2382 * 2383 * This function enables the card. All information is stored in 2384 * the first argument, pcmcia_chipset_handle_t. 2385 */ 2386 STATIC void 2387 pccbb_pcmcia_socket_enable(pch) 2388 pcmcia_chipset_handle_t pch; 2389 { 2390 struct pcic_handle *ph = (struct pcic_handle *)pch; 2391 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2392 pcireg_t spsr; 2393 int voltage; 2394 int win; 2395 u_int8_t power, intr; 2396 #ifdef DIAGNOSTIC 2397 int reg; 2398 #endif 2399 2400 /* this bit is mostly stolen from pcic_attach_card */ 2401 2402 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2403 2404 /* get card Vcc info */ 2405 spsr = 2406 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2407 CB_SOCKET_STAT); 2408 if (spsr & CB_SOCKET_STAT_5VCARD) { 2409 DPRINTF(("5V card\n")); 2410 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2411 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2412 DPRINTF(("3V card\n")); 2413 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2414 } else { 2415 DPRINTF(("?V card, 0x%x\n", spsr)); /* XXX */ 2416 return; 2417 } 2418 2419 /* disable interrupts; assert RESET */ 2420 intr = Pcic_read(ph, PCIC_INTR); 2421 intr &= PCIC_INTR_ENABLE; 2422 Pcic_write(ph, PCIC_INTR, intr); 2423 2424 /* zero out the address windows */ 2425 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2426 2427 /* power down the socket to reset it, clear the card reset pin */ 2428 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2429 2430 /* power off; assert output enable bit */ 2431 power = PCIC_PWRCTL_OE; 2432 Pcic_write(ph, PCIC_PWRCTL, power); 2433 2434 /* power up the socket */ 2435 if (pccbb_power(sc, voltage) == 0) 2436 return; 2437 2438 /* 2439 * Table 4-18 and figure 4-6 of the PC Card specifiction say: 2440 * Vcc Rising Time (Tpr) = 100ms (handled in pccbb_power() above) 2441 * RESET Width (Th (Hi-z RESET)) = 1ms 2442 * RESET Width (Tw (RESET)) = 10us 2443 * 2444 * some machines require some more time to be settled 2445 * for example old toshiba topic bridges! 2446 * (100ms is added here). 2447 */ 2448 pccbb_pcmcia_delay(ph, 200 + 1, "pccen1"); 2449 2450 /* negate RESET */ 2451 intr |= PCIC_INTR_RESET; 2452 Pcic_write(ph, PCIC_INTR, intr); 2453 2454 /* 2455 * RESET Setup Time (Tsu (RESET)) = 20ms 2456 */ 2457 pccbb_pcmcia_delay(ph, 20, "pccen2"); 2458 2459 #ifdef DIAGNOSTIC 2460 reg = Pcic_read(ph, PCIC_IF_STATUS); 2461 if ((reg & PCIC_IF_STATUS_POWERACTIVE) == 0) 2462 printf("pccbb_pcmcia_socket_enable: no power, status=%x\n", reg); 2463 #endif 2464 2465 /* wait for the chip to finish initializing */ 2466 if (pccbb_pcmcia_wait_ready(ph)) { 2467 #ifdef DIAGNOSTIC 2468 printf("pccbb_pcmcia_socket_enable: never became ready\n"); 2469 #endif 2470 /* XXX return a failure status?? */ 2471 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2472 Pcic_write(ph, PCIC_PWRCTL, 0); 2473 return; 2474 } 2475 2476 /* reinstall all the memory and io mappings */ 2477 for (win = 0; win < PCIC_MEM_WINS; ++win) 2478 if (ph->memalloc & (1 << win)) 2479 pccbb_pcmcia_do_mem_map(ph, win); 2480 for (win = 0; win < PCIC_IO_WINS; ++win) 2481 if (ph->ioalloc & (1 << win)) 2482 pccbb_pcmcia_do_io_map(ph, win); 2483 } 2484 2485 /* 2486 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2487 * 2488 * This function disables the card. All information is stored in 2489 * the first argument, pcmcia_chipset_handle_t. 2490 */ 2491 STATIC void 2492 pccbb_pcmcia_socket_disable(pch) 2493 pcmcia_chipset_handle_t pch; 2494 { 2495 struct pcic_handle *ph = (struct pcic_handle *)pch; 2496 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2497 u_int8_t intr; 2498 2499 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2500 2501 /* disable interrupts; assert RESET */ 2502 intr = Pcic_read(ph, PCIC_INTR); 2503 intr &= PCIC_INTR_ENABLE; 2504 Pcic_write(ph, PCIC_INTR, intr); 2505 2506 /* zero out the address windows */ 2507 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2508 2509 /* power down the socket to reset it, clear the card reset pin */ 2510 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2511 2512 /* disable socket: negate output enable bit and power off */ 2513 Pcic_write(ph, PCIC_PWRCTL, 0); 2514 2515 /* 2516 * Vcc Falling Time (Tpf) = 300ms 2517 */ 2518 pccbb_pcmcia_delay(ph, 300, "pccwr1"); 2519 } 2520 2521 STATIC void 2522 pccbb_pcmcia_socket_settype(pch, type) 2523 pcmcia_chipset_handle_t pch; 2524 int type; 2525 { 2526 struct pcic_handle *ph = (struct pcic_handle *)pch; 2527 u_int8_t intr; 2528 2529 /* set the card type */ 2530 2531 intr = Pcic_read(ph, PCIC_INTR); 2532 intr &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_CARDTYPE_MASK); 2533 if (type == PCMCIA_IFTYPE_IO) 2534 intr |= PCIC_INTR_CARDTYPE_IO; 2535 else 2536 intr |= PCIC_INTR_CARDTYPE_MEM; 2537 Pcic_write(ph, PCIC_INTR, intr); 2538 2539 DPRINTF(("%s: pccbb_pcmcia_socket_settype %02x type %s %02x\n", 2540 ph->ph_parent->dv_xname, ph->sock, 2541 ((type == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2542 } 2543 2544 /* 2545 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2546 * 2547 * This function detects whether a card is in the slot or not. 2548 * If a card is inserted, return 1. Otherwise, return 0. 2549 */ 2550 STATIC int 2551 pccbb_pcmcia_card_detect(pch) 2552 pcmcia_chipset_handle_t pch; 2553 { 2554 struct pcic_handle *ph = (struct pcic_handle *)pch; 2555 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2556 2557 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2558 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2559 } 2560 2561 #if 0 2562 STATIC int 2563 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2564 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2565 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2566 #endif 2567 /* 2568 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2569 * bus_size_t size, 2570 * struct pcmcia_mem_handle *pcmhp) 2571 * 2572 * This function only allocates memory region for pccard. This 2573 * function never maps the allocated region to pccard memory area. 2574 * 2575 * XXX: Why the argument of start address is not in? 2576 */ 2577 STATIC int 2578 pccbb_pcmcia_mem_alloc(pch, size, pcmhp) 2579 pcmcia_chipset_handle_t pch; 2580 bus_size_t size; 2581 struct pcmcia_mem_handle *pcmhp; 2582 { 2583 struct pcic_handle *ph = (struct pcic_handle *)pch; 2584 bus_space_handle_t memh; 2585 bus_addr_t addr; 2586 bus_size_t sizepg; 2587 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2588 #if rbus 2589 rbus_tag_t rb; 2590 #endif 2591 2592 /* Check that the card is still there. */ 2593 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2594 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2595 return 1; 2596 2597 /* out of sc->memh, allocate as many pages as necessary */ 2598 2599 /* convert size to PCIC pages */ 2600 /* 2601 * This is not enough; when the requested region is on the page 2602 * boundaries, this may calculate wrong result. 2603 */ 2604 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2605 #if 0 2606 if (sizepg > PCIC_MAX_MEM_PAGES) { 2607 return 1; 2608 } 2609 #endif 2610 2611 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2612 return 1; 2613 } 2614 2615 addr = 0; /* XXX gcc -Wuninitialized */ 2616 2617 #if rbus 2618 rb = sc->sc_rbus_memt; 2619 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2620 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2621 &addr, &memh)) { 2622 return 1; 2623 } 2624 #else 2625 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2626 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2627 0, /* boundary */ 2628 0, /* flags */ 2629 &addr, &memh)) { 2630 return 1; 2631 } 2632 #endif 2633 2634 DPRINTF(("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, " 2635 "realsize 0x%lx\n", (unsigned long)addr, (unsigned long)size, 2636 (unsigned long)sizepg * PCIC_MEM_PAGESIZE)); 2637 2638 pcmhp->memt = sc->sc_memt; 2639 pcmhp->memh = memh; 2640 pcmhp->addr = addr; 2641 pcmhp->size = size; 2642 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2643 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2644 pcmhp->mhandle = 0; 2645 /* No offset??? Funny. */ 2646 2647 return 0; 2648 } 2649 2650 /* 2651 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2652 * struct pcmcia_mem_handle *pcmhp) 2653 * 2654 * This function release the memory space allocated by the function 2655 * pccbb_pcmcia_mem_alloc(). 2656 */ 2657 STATIC void 2658 pccbb_pcmcia_mem_free(pch, pcmhp) 2659 pcmcia_chipset_handle_t pch; 2660 struct pcmcia_mem_handle *pcmhp; 2661 { 2662 #if rbus 2663 struct pcic_handle *ph = (struct pcic_handle *)pch; 2664 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2665 2666 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2667 #else 2668 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2669 #endif 2670 } 2671 2672 /* 2673 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2674 * 2675 * This function release the memory space allocated by the function 2676 * pccbb_pcmcia_mem_alloc(). 2677 */ 2678 STATIC void 2679 pccbb_pcmcia_do_mem_map(ph, win) 2680 struct pcic_handle *ph; 2681 int win; 2682 { 2683 int regbase_win; 2684 bus_addr_t phys_addr; 2685 bus_addr_t phys_end; 2686 2687 #define PCIC_SMM_START_LOW 0 2688 #define PCIC_SMM_START_HIGH 1 2689 #define PCIC_SMM_STOP_LOW 2 2690 #define PCIC_SMM_STOP_HIGH 3 2691 #define PCIC_CMA_LOW 4 2692 #define PCIC_CMA_HIGH 5 2693 2694 u_int8_t start_low, start_high = 0; 2695 u_int8_t stop_low, stop_high; 2696 u_int8_t off_low, off_high; 2697 u_int8_t mem_window; 2698 int reg; 2699 2700 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2701 int mem8 = 2702 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2703 || (kind == PCMCIA_MEM_ATTR); 2704 2705 regbase_win = 0x10 + win * 0x08; 2706 2707 phys_addr = ph->mem[win].addr; 2708 phys_end = phys_addr + ph->mem[win].size; 2709 2710 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2711 (unsigned long)phys_addr, (unsigned long)phys_end, 2712 (unsigned long)ph->mem[win].offset)); 2713 2714 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2715 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2716 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2717 2718 /* bit 19:12 */ 2719 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2720 /* bit 23:20 and bit 7 on */ 2721 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2722 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2723 /* bit 31:24, for 32-bit address */ 2724 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2725 2726 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2727 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2728 2729 if (((struct pccbb_softc *)ph-> 2730 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2731 Pcic_write(ph, 0x40 + win, mem_window); 2732 } 2733 2734 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2735 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2736 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2737 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2738 2739 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2740 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2741 2742 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2743 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2744 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2745 | ((kind == PCMCIA_MEM_ATTR) ? 2746 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2747 2748 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2749 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2750 2751 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2752 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2753 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2754 2755 #if defined(CBB_DEBUG) 2756 { 2757 int r1, r2, r3, r4, r5, r6, r7 = 0; 2758 2759 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2760 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2761 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2762 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2763 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2764 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2765 if (((struct pccbb_softc *)(ph-> 2766 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2767 r7 = Pcic_read(ph, 0x40 + win); 2768 } 2769 2770 printf("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2771 "%02x%02x", win, r1, r2, r3, r4, r5, r6); 2772 if (((struct pccbb_softc *)(ph-> 2773 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2774 printf(" %02x", r7); 2775 } 2776 printf("\n"); 2777 } 2778 #endif 2779 } 2780 2781 /* 2782 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2783 * bus_addr_t card_addr, bus_size_t size, 2784 * struct pcmcia_mem_handle *pcmhp, 2785 * bus_addr_t *offsetp, int *windowp) 2786 * 2787 * This function maps memory space allocated by the function 2788 * pccbb_pcmcia_mem_alloc(). 2789 */ 2790 STATIC int 2791 pccbb_pcmcia_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 2792 pcmcia_chipset_handle_t pch; 2793 int kind; 2794 bus_addr_t card_addr; 2795 bus_size_t size; 2796 struct pcmcia_mem_handle *pcmhp; 2797 bus_addr_t *offsetp; 2798 int *windowp; 2799 { 2800 struct pcic_handle *ph = (struct pcic_handle *)pch; 2801 bus_addr_t busaddr; 2802 long card_offset; 2803 int win; 2804 2805 /* Check that the card is still there. */ 2806 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2807 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2808 return 1; 2809 2810 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2811 if ((ph->memalloc & (1 << win)) == 0) { 2812 ph->memalloc |= (1 << win); 2813 break; 2814 } 2815 } 2816 2817 if (win == PCIC_MEM_WINS) { 2818 return 1; 2819 } 2820 2821 *windowp = win; 2822 2823 /* XXX this is pretty gross */ 2824 2825 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2826 panic("pccbb_pcmcia_mem_map memt is bogus"); 2827 } 2828 2829 busaddr = pcmhp->addr; 2830 2831 /* 2832 * compute the address offset to the pcmcia address space for the 2833 * pcic. this is intentionally signed. The masks and shifts below 2834 * will cause TRT to happen in the pcic registers. Deal with making 2835 * sure the address is aligned, and return the alignment offset. 2836 */ 2837 2838 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2839 card_addr -= *offsetp; 2840 2841 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2842 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2843 (u_long) card_addr)); 2844 2845 /* 2846 * include the offset in the size, and decrement size by one, since 2847 * the hw wants start/stop 2848 */ 2849 size += *offsetp - 1; 2850 2851 card_offset = (((long)card_addr) - ((long)busaddr)); 2852 2853 ph->mem[win].addr = busaddr; 2854 ph->mem[win].size = size; 2855 ph->mem[win].offset = card_offset; 2856 ph->mem[win].kind = kind; 2857 2858 pccbb_pcmcia_do_mem_map(ph, win); 2859 2860 return 0; 2861 } 2862 2863 /* 2864 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2865 * int window) 2866 * 2867 * This function unmaps memory space which mapped by the function 2868 * pccbb_pcmcia_mem_map(). 2869 */ 2870 STATIC void 2871 pccbb_pcmcia_mem_unmap(pch, window) 2872 pcmcia_chipset_handle_t pch; 2873 int window; 2874 { 2875 struct pcic_handle *ph = (struct pcic_handle *)pch; 2876 int reg; 2877 2878 if (window >= PCIC_MEM_WINS) { 2879 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2880 } 2881 2882 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2883 reg &= ~(1 << window); 2884 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2885 2886 ph->memalloc &= ~(1 << window); 2887 } 2888 2889 #if defined PCCBB_PCMCIA_POLL 2890 struct pccbb_poll_str { 2891 void *arg; 2892 int (*func)(void *); 2893 int level; 2894 struct pcic_handle *ph; 2895 int count; 2896 int num; 2897 struct callout poll_ch; 2898 }; 2899 2900 static struct pccbb_poll_str pccbb_poll[10]; 2901 static int pccbb_poll_n = 0; 2902 2903 static void pccbb_pcmcia_poll(void *arg); 2904 2905 static void 2906 pccbb_pcmcia_poll(arg) 2907 void *arg; 2908 { 2909 struct pccbb_poll_str *poll = arg; 2910 struct pcic_handle *ph = poll->ph; 2911 struct pccbb_softc *sc = ph->sc; 2912 int s; 2913 u_int32_t spsr; /* socket present-state reg */ 2914 2915 callout_reset(&poll->poll_ch, hz * 2, pccbb_pcmcia_poll, arg); 2916 switch (poll->level) { 2917 case IPL_NET: 2918 s = splnet(); 2919 break; 2920 case IPL_BIO: 2921 s = splbio(); 2922 break; 2923 case IPL_TTY: /* fallthrough */ 2924 default: 2925 s = spltty(); 2926 break; 2927 } 2928 2929 spsr = 2930 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2931 CB_SOCKET_STAT); 2932 2933 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2934 if (!(spsr & 0x40)) /* CINT low */ 2935 #else 2936 if (1) 2937 #endif 2938 { 2939 if ((*poll->func) (poll->arg) > 0) { 2940 ++poll->count; 2941 /* printf("intr: reported from poller, 0x%x\n", spsr); */ 2942 #if defined LEVEL2 2943 } else { 2944 printf("intr: miss! 0x%x\n", spsr); 2945 #endif 2946 } 2947 } 2948 splx(s); 2949 } 2950 #endif /* defined CB_PCMCIA_POLL */ 2951 2952 /* 2953 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2954 * struct pcmcia_function *pf, 2955 * int ipl, 2956 * int (*func)(void *), 2957 * void *arg); 2958 * 2959 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2960 */ 2961 STATIC void * 2962 pccbb_pcmcia_intr_establish(pch, pf, ipl, func, arg) 2963 pcmcia_chipset_handle_t pch; 2964 struct pcmcia_function *pf; 2965 int ipl; 2966 int (*func)(void *); 2967 void *arg; 2968 { 2969 struct pcic_handle *ph = (struct pcic_handle *)pch; 2970 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2971 2972 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2973 /* what should I do? */ 2974 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2975 DPRINTF(("%s does not provide edge nor pulse " 2976 "interrupt\n", sc->sc_dev.dv_xname)); 2977 return NULL; 2978 } 2979 /* 2980 * XXX Noooooo! The interrupt flag must set properly!! 2981 * dumb pcmcia driver!! 2982 */ 2983 } 2984 2985 return pccbb_intr_establish(sc, 0, ipl, func, arg); 2986 } 2987 2988 /* 2989 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2990 * void *ih) 2991 * 2992 * This function disables PC-Card interrupt. 2993 */ 2994 STATIC void 2995 pccbb_pcmcia_intr_disestablish(pch, ih) 2996 pcmcia_chipset_handle_t pch; 2997 void *ih; 2998 { 2999 struct pcic_handle *ph = (struct pcic_handle *)pch; 3000 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 3001 3002 pccbb_intr_disestablish(sc, ih); 3003 } 3004 3005 #if rbus 3006 /* 3007 * static int 3008 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 3009 * bus_addr_t addr, bus_size_t size, 3010 * bus_addr_t mask, bus_size_t align, 3011 * int flags, bus_addr_t *addrp; 3012 * bus_space_handle_t *bshp) 3013 * 3014 * This function allocates a portion of memory or io space for 3015 * clients. This function is called from CardBus card drivers. 3016 */ 3017 static int 3018 pccbb_rbus_cb_space_alloc(ct, rb, addr, size, mask, align, flags, addrp, bshp) 3019 cardbus_chipset_tag_t ct; 3020 rbus_tag_t rb; 3021 bus_addr_t addr; 3022 bus_size_t size; 3023 bus_addr_t mask; 3024 bus_size_t align; 3025 int flags; 3026 bus_addr_t *addrp; 3027 bus_space_handle_t *bshp; 3028 { 3029 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 3030 3031 DPRINTF(("pccbb_rbus_cb_space_alloc: addr 0x%lx, size 0x%lx, " 3032 "mask 0x%lx, align 0x%lx\n", (unsigned long)addr, 3033 (unsigned long)size, (unsigned long)mask, (unsigned long)align)); 3034 3035 if (align == 0) { 3036 align = size; 3037 } 3038 3039 if (rb->rb_bt == sc->sc_memt) { 3040 if (align < 16) { 3041 return 1; 3042 } 3043 /* 3044 * XXX: align more than 0x1000 to avoid overwrapping 3045 * memory windows for two or more devices. 0x1000 3046 * means memory window's granularity. 3047 * 3048 * Two or more devices should be able to share same 3049 * memory window region. However, overrapping memory 3050 * window is not good because some devices, such as 3051 * 3Com 3C575[BC], have a broken address decoder and 3052 * intrude other's memory region. 3053 */ 3054 if (align < 0x1000) { 3055 align = 0x1000; 3056 } 3057 } else if (rb->rb_bt == sc->sc_iot) { 3058 if (align < 4) { 3059 return 1; 3060 } 3061 /* XXX: hack for avoiding ISA image */ 3062 if (mask < 0x0100) { 3063 mask = 0x3ff; 3064 addr = 0x300; 3065 } 3066 3067 } else { 3068 DPRINTF(("pccbb_rbus_cb_space_alloc: Bus space tag 0x%lx is " 3069 "NOT used. io: 0x%lx, mem: 0x%lx\n", 3070 (unsigned long)rb->rb_bt, (unsigned long)sc->sc_iot, 3071 (unsigned long)sc->sc_memt)); 3072 return 1; 3073 /* XXX: panic here? */ 3074 } 3075 3076 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 3077 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 3078 return 1; 3079 } 3080 3081 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 3082 3083 return 0; 3084 } 3085 3086 /* 3087 * static int 3088 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 3089 * bus_space_handle_t *bshp, bus_size_t size); 3090 * 3091 * This function is called from CardBus card drivers. 3092 */ 3093 static int 3094 pccbb_rbus_cb_space_free(ct, rb, bsh, size) 3095 cardbus_chipset_tag_t ct; 3096 rbus_tag_t rb; 3097 bus_space_handle_t bsh; 3098 bus_size_t size; 3099 { 3100 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 3101 bus_space_tag_t bt = rb->rb_bt; 3102 3103 pccbb_close_win(sc, bt, bsh, size); 3104 3105 if (bt == sc->sc_memt) { 3106 } else if (bt == sc->sc_iot) { 3107 } else { 3108 return 1; 3109 /* XXX: panic here? */ 3110 } 3111 3112 return rbus_space_free(rb, bsh, size, NULL); 3113 } 3114 #endif /* rbus */ 3115 3116 #if rbus 3117 3118 static int 3119 pccbb_open_win(sc, bst, addr, size, bsh, flags) 3120 struct pccbb_softc *sc; 3121 bus_space_tag_t bst; 3122 bus_addr_t addr; 3123 bus_size_t size; 3124 bus_space_handle_t bsh; 3125 int flags; 3126 { 3127 struct pccbb_win_chain_head *head; 3128 bus_addr_t align; 3129 3130 head = &sc->sc_iowindow; 3131 align = 0x04; 3132 if (sc->sc_memt == bst) { 3133 head = &sc->sc_memwindow; 3134 align = 0x1000; 3135 DPRINTF(("using memory window, 0x%lx 0x%lx 0x%lx\n\n", 3136 (unsigned long)sc->sc_iot, (unsigned long)sc->sc_memt, 3137 (unsigned long)bst)); 3138 } 3139 3140 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 3141 printf("%s: pccbb_open_win: %s winlist insert failed\n", 3142 sc->sc_dev.dv_xname, 3143 (head == &sc->sc_memwindow) ? "mem" : "io"); 3144 } 3145 pccbb_winset(align, sc, bst); 3146 3147 return 0; 3148 } 3149 3150 static int 3151 pccbb_close_win(sc, bst, bsh, size) 3152 struct pccbb_softc *sc; 3153 bus_space_tag_t bst; 3154 bus_space_handle_t bsh; 3155 bus_size_t size; 3156 { 3157 struct pccbb_win_chain_head *head; 3158 bus_addr_t align; 3159 3160 head = &sc->sc_iowindow; 3161 align = 0x04; 3162 if (sc->sc_memt == bst) { 3163 head = &sc->sc_memwindow; 3164 align = 0x1000; 3165 } 3166 3167 if (pccbb_winlist_delete(head, bsh, size)) { 3168 printf("%s: pccbb_close_win: %s winlist delete failed\n", 3169 sc->sc_dev.dv_xname, 3170 (head == &sc->sc_memwindow) ? "mem" : "io"); 3171 } 3172 pccbb_winset(align, sc, bst); 3173 3174 return 0; 3175 } 3176 3177 static int 3178 pccbb_winlist_insert(head, start, size, bsh, flags) 3179 struct pccbb_win_chain_head *head; 3180 bus_addr_t start; 3181 bus_size_t size; 3182 bus_space_handle_t bsh; 3183 int flags; 3184 { 3185 struct pccbb_win_chain *chainp, *elem; 3186 3187 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 3188 M_NOWAIT)) == NULL) 3189 return (1); /* fail */ 3190 3191 elem->wc_start = start; 3192 elem->wc_end = start + (size - 1); 3193 elem->wc_handle = bsh; 3194 elem->wc_flags = flags; 3195 3196 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3197 chainp = TAILQ_NEXT(chainp, wc_list)) { 3198 if (chainp->wc_end < start) 3199 continue; 3200 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 3201 return (0); 3202 } 3203 3204 TAILQ_INSERT_TAIL(head, elem, wc_list); 3205 return (0); 3206 } 3207 3208 static int 3209 pccbb_winlist_delete(head, bsh, size) 3210 struct pccbb_win_chain_head *head; 3211 bus_space_handle_t bsh; 3212 bus_size_t size; 3213 { 3214 struct pccbb_win_chain *chainp; 3215 3216 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3217 chainp = TAILQ_NEXT(chainp, wc_list)) { 3218 if (memcmp(&chainp->wc_handle, &bsh, sizeof(bsh))) 3219 continue; 3220 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 3221 printf("pccbb_winlist_delete: window 0x%lx size " 3222 "inconsistent: 0x%lx, 0x%lx\n", 3223 (unsigned long)chainp->wc_start, 3224 (unsigned long)(chainp->wc_end - chainp->wc_start), 3225 (unsigned long)(size - 1)); 3226 return 1; 3227 } 3228 3229 TAILQ_REMOVE(head, chainp, wc_list); 3230 free(chainp, M_DEVBUF); 3231 3232 return 0; 3233 } 3234 3235 return 1; /* fail: no candidate to remove */ 3236 } 3237 3238 static void 3239 pccbb_winset(align, sc, bst) 3240 bus_addr_t align; 3241 struct pccbb_softc *sc; 3242 bus_space_tag_t bst; 3243 { 3244 pci_chipset_tag_t pc; 3245 pcitag_t tag; 3246 bus_addr_t mask = ~(align - 1); 3247 struct { 3248 cardbusreg_t win_start; 3249 cardbusreg_t win_limit; 3250 int win_flags; 3251 } win[2]; 3252 struct pccbb_win_chain *chainp; 3253 int offs; 3254 3255 win[0].win_start = win[1].win_start = 0xffffffff; 3256 win[0].win_limit = win[1].win_limit = 0; 3257 win[0].win_flags = win[1].win_flags = 0; 3258 3259 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3260 offs = 0x2c; 3261 if (sc->sc_memt == bst) { 3262 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3263 offs = 0x1c; 3264 } 3265 3266 if (chainp != NULL) { 3267 win[0].win_start = chainp->wc_start & mask; 3268 win[0].win_limit = chainp->wc_end & mask; 3269 win[0].win_flags = chainp->wc_flags; 3270 chainp = TAILQ_NEXT(chainp, wc_list); 3271 } 3272 3273 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3274 if (win[1].win_start == 0xffffffff) { 3275 /* window 1 is not used */ 3276 if ((win[0].win_flags == chainp->wc_flags) && 3277 (win[0].win_limit + align >= 3278 (chainp->wc_start & mask))) { 3279 /* concatenate */ 3280 win[0].win_limit = chainp->wc_end & mask; 3281 } else { 3282 /* make new window */ 3283 win[1].win_start = chainp->wc_start & mask; 3284 win[1].win_limit = chainp->wc_end & mask; 3285 win[1].win_flags = chainp->wc_flags; 3286 } 3287 continue; 3288 } 3289 3290 /* Both windows are engaged. */ 3291 if (win[0].win_flags == win[1].win_flags) { 3292 /* same flags */ 3293 if (win[0].win_flags == chainp->wc_flags) { 3294 if (win[1].win_start - (win[0].win_limit + 3295 align) < 3296 (chainp->wc_start & mask) - 3297 ((chainp->wc_end & mask) + align)) { 3298 /* 3299 * merge window 0 and 1, and set win1 3300 * to chainp 3301 */ 3302 win[0].win_limit = win[1].win_limit; 3303 win[1].win_start = 3304 chainp->wc_start & mask; 3305 win[1].win_limit = 3306 chainp->wc_end & mask; 3307 } else { 3308 win[1].win_limit = 3309 chainp->wc_end & mask; 3310 } 3311 } else { 3312 /* different flags */ 3313 3314 /* concatenate win0 and win1 */ 3315 win[0].win_limit = win[1].win_limit; 3316 /* allocate win[1] to new space */ 3317 win[1].win_start = chainp->wc_start & mask; 3318 win[1].win_limit = chainp->wc_end & mask; 3319 win[1].win_flags = chainp->wc_flags; 3320 } 3321 } else { 3322 /* the flags of win[0] and win[1] is different */ 3323 if (win[0].win_flags == chainp->wc_flags) { 3324 win[0].win_limit = chainp->wc_end & mask; 3325 /* 3326 * XXX this creates overlapping windows, so 3327 * what should the poor bridge do if one is 3328 * cachable, and the other is not? 3329 */ 3330 printf("%s: overlapping windows\n", 3331 sc->sc_dev.dv_xname); 3332 } else { 3333 win[1].win_limit = chainp->wc_end & mask; 3334 } 3335 } 3336 } 3337 3338 pc = sc->sc_pc; 3339 tag = sc->sc_tag; 3340 pci_conf_write(pc, tag, offs, win[0].win_start); 3341 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3342 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3343 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3344 DPRINTF(("--pccbb_winset: win0 [0x%lx, 0x%lx), win1 [0x%lx, 0x%lx)\n", 3345 (unsigned long)pci_conf_read(pc, tag, offs), 3346 (unsigned long)pci_conf_read(pc, tag, offs + 4) + align, 3347 (unsigned long)pci_conf_read(pc, tag, offs + 8), 3348 (unsigned long)pci_conf_read(pc, tag, offs + 12) + align)); 3349 3350 if (bst == sc->sc_memt) { 3351 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3352 3353 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 3354 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 3355 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3356 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 3357 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3358 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3359 } 3360 } 3361 3362 #endif /* rbus */ 3363 3364 static void 3365 pccbb_powerhook(why, arg) 3366 int why; 3367 void *arg; 3368 { 3369 struct pccbb_softc *sc = arg; 3370 pcireg_t reg; 3371 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3372 bus_space_handle_t base_memh = sc->sc_base_memh; 3373 3374 DPRINTF(("%s: power: why %d\n", sc->sc_dev.dv_xname, why)); 3375 3376 if (why == PWR_SUSPEND || why == PWR_STANDBY) { 3377 DPRINTF(("%s: power: why %d stopping intr\n", 3378 sc->sc_dev.dv_xname, why)); 3379 if (sc->sc_pil_intr_enable) { 3380 (void)pccbbintr_function(sc); 3381 } 3382 sc->sc_pil_intr_enable = 0; 3383 3384 pci_conf_capture(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf); 3385 3386 if (sc->sc_chipset == CB_RX5C47X) 3387 sc->sc_ricoh_misc_ctrl = pci_conf_read(sc->sc_pc, 3388 sc->sc_tag, 3389 RICOH_PCI_MISC_CTRL); 3390 3391 /* ToDo: deactivate or suspend child devices */ 3392 } 3393 3394 if (why == PWR_RESUME) { 3395 if (sc->sc_pwrmgt_offs != 0) { 3396 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, 3397 sc->sc_pwrmgt_offs + PCI_PMCSR); 3398 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 3399 reg & PCI_PMCSR_PME_EN) { 3400 /* powrstate != D0 */ 3401 3402 printf("%s going back to D0 mode\n", 3403 sc->sc_dev.dv_xname); 3404 reg &= ~PCI_PMCSR_STATE_MASK; 3405 reg |= PCI_PMCSR_STATE_D0; 3406 reg &= ~PCI_PMCSR_PME_EN; 3407 pci_conf_write(sc->sc_pc, sc->sc_tag, 3408 sc->sc_pwrmgt_offs + PCI_PMCSR, reg); 3409 3410 pci_conf_write(sc->sc_pc, sc->sc_tag, 3411 PCI_SOCKBASE, sc->sc_sockbase); 3412 pci_conf_write(sc->sc_pc, sc->sc_tag, 3413 PCI_BUSNUM, sc->sc_busnum); 3414 pccbb_chipinit(sc); 3415 /* setup memory and io space window for CB */ 3416 pccbb_winset(0x1000, sc, sc->sc_memt); 3417 pccbb_winset(0x04, sc, sc->sc_iot); 3418 goto norestore; 3419 } 3420 } 3421 3422 norestore: 3423 pci_conf_restore(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf); 3424 if (sc->sc_chipset == CB_RX5C47X) { 3425 pci_conf_write(sc->sc_pc, sc->sc_tag, 3426 RICOH_PCI_MISC_CTRL, sc->sc_ricoh_misc_ctrl); 3427 } 3428 3429 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_SOCKBASE) == 0) 3430 /* BIOS did not recover this register */ 3431 pci_conf_write (sc->sc_pc, sc->sc_tag, 3432 PCI_SOCKBASE, sc->sc_sockbase); 3433 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_BUSNUM) == 0) 3434 /* BIOS did not recover this register */ 3435 pci_conf_write (sc->sc_pc, sc->sc_tag, 3436 PCI_BUSNUM, sc->sc_busnum); 3437 /* CSC Interrupt: Card detect interrupt on */ 3438 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3439 /* Card detect intr is turned on. */ 3440 reg |= CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; 3441 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3442 /* reset interrupt */ 3443 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3444 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3445 3446 /* 3447 * check for card insertion or removal during suspend period. 3448 * XXX: the code can't cope with card swap (remove then 3449 * insert). how can we detect such situation? 3450 */ 3451 (void)pccbbintr(sc); 3452 3453 sc->sc_pil_intr_enable = 1; 3454 DPRINTF(("%s: power: RESUME enabling intr\n", 3455 sc->sc_dev.dv_xname)); 3456 3457 /* ToDo: activate or wakeup child devices */ 3458 } 3459 } 3460
Indexes created Fri Sep 26 20:09:58 GMT 2025