pccbb.c revision 1.143
1 /* $NetBSD: pccbb.c,v 1.143 2007/02/04 05:34:38 dyoung Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: pccbb.c,v 1.143 2007/02/04 05:34:38 dyoung Exp $"); 35 36 /* 37 #define CBB_DEBUG 38 #define SHOW_REGS 39 */ 40 41 /* 42 * BROKEN! 43 #define PCCBB_PCMCIA_POLL 44 #define CB_PCMCIA_POLL 45 #define CB_PCMCIA_POLL_ONLY 46 #define LEVEL2 47 */ 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/kernel.h> 52 #include <sys/errno.h> 53 #include <sys/ioctl.h> 54 #include <sys/reboot.h> /* for bootverbose */ 55 #include <sys/syslog.h> 56 #include <sys/device.h> 57 #include <sys/malloc.h> 58 #include <sys/proc.h> 59 60 #include <machine/intr.h> 61 #include <machine/bus.h> 62 63 #include <dev/pci/pcivar.h> 64 #include <dev/pci/pcireg.h> 65 #include <dev/pci/pcidevs.h> 66 67 #include <dev/pci/pccbbreg.h> 68 69 #include <dev/cardbus/cardslotvar.h> 70 71 #include <dev/cardbus/cardbusvar.h> 72 73 #include <dev/pcmcia/pcmciareg.h> 74 #include <dev/pcmcia/pcmciavar.h> 75 76 #include <dev/ic/i82365reg.h> 77 #include <dev/ic/i82365var.h> 78 #include <dev/pci/pccbbvar.h> 79 80 #include "locators.h" 81 82 #if defined(__i386__) 83 #include "ioapic.h" 84 #include "acpi.h" 85 #endif 86 87 #ifndef __NetBSD_Version__ 88 struct cfdriver cbb_cd = { 89 NULL, "cbb", DV_DULL 90 }; 91 #endif 92 93 #ifdef CBB_DEBUG 94 #define DPRINTF(x) printf x 95 #define STATIC 96 #else 97 #define DPRINTF(x) 98 #define STATIC static 99 #endif 100 101 /* 102 * delay_ms() is wait in milliseconds. It should be used instead 103 * of delay() if you want to wait more than 1 ms. 104 */ 105 static inline void 106 delay_ms(int millis, void *param) 107 { 108 if (cold) 109 delay(millis * 1000); 110 else 111 tsleep(param, PWAIT, "pccbb", MAX(2, hz * millis / 1000)); 112 } 113 114 int pcicbbmatch(struct device *, struct cfdata *, void *); 115 void pccbbattach(struct device *, struct device *, void *); 116 int pccbbintr(void *); 117 static void pci113x_insert(void *); 118 static int pccbbintr_function(struct pccbb_softc *); 119 120 static int pccbb_detect_card(struct pccbb_softc *); 121 122 static void pccbb_pcmcia_write(struct pcic_handle *, int, u_int8_t); 123 static u_int8_t pccbb_pcmcia_read(struct pcic_handle *, int); 124 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 125 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 126 127 STATIC int cb_reset(struct pccbb_softc *); 128 STATIC int cb_detect_voltage(struct pccbb_softc *); 129 STATIC int cbbprint(void *, const char *); 130 131 static int cb_chipset(u_int32_t, int *); 132 STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *, 133 struct pcmciabus_attach_args *); 134 #if 0 135 STATIC void pccbb_pcmcia_attach_card(struct pcic_handle *); 136 STATIC void pccbb_pcmcia_detach_card(struct pcic_handle *, int); 137 STATIC void pccbb_pcmcia_deactivate_card(struct pcic_handle *); 138 #endif 139 140 STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int); 141 STATIC int pccbb_power(cardbus_chipset_tag_t, int); 142 STATIC int pccbb_cardenable(struct pccbb_softc * sc, int function); 143 #if !rbus 144 static int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 145 static int pccbb_io_close(cardbus_chipset_tag_t, int); 146 static int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 147 static int pccbb_mem_close(cardbus_chipset_tag_t, int); 148 #endif /* !rbus */ 149 static void *pccbb_intr_establish(struct pccbb_softc *, int irq, 150 int level, int (*ih) (void *), void *sc); 151 static void pccbb_intr_disestablish(struct pccbb_softc *, void *ih); 152 153 static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t, int irq, 154 int level, int (*ih) (void *), void *sc); 155 static void pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih); 156 157 static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t, int, int); 158 static void pccbb_free_tag(cardbus_chipset_tag_t, cardbustag_t); 159 static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t, cardbustag_t, int); 160 static void pccbb_conf_write(cardbus_chipset_tag_t, cardbustag_t, int, 161 cardbusreg_t); 162 static void pccbb_chipinit(struct pccbb_softc *); 163 164 STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 165 struct pcmcia_mem_handle *); 166 STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t, 167 struct pcmcia_mem_handle *); 168 STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 169 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *); 170 STATIC void pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t, int); 171 STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 172 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 173 STATIC void pccbb_pcmcia_io_free(pcmcia_chipset_handle_t, 174 struct pcmcia_io_handle *); 175 STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 176 bus_size_t, struct pcmcia_io_handle *, int *); 177 STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t, int); 178 STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t, 179 struct pcmcia_function *, int, int (*)(void *), void *); 180 STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t, void *); 181 STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t); 182 STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t); 183 STATIC void pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t, int); 184 STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch); 185 186 static int pccbb_pcmcia_wait_ready(struct pcic_handle *); 187 static void pccbb_pcmcia_delay(struct pcic_handle *, int, const char *); 188 189 static void pccbb_pcmcia_do_io_map(struct pcic_handle *, int); 190 static void pccbb_pcmcia_do_mem_map(struct pcic_handle *, int); 191 static void pccbb_powerhook(int, void *); 192 193 /* bus-space allocation and deallocation functions */ 194 #if rbus 195 196 static int pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t, rbus_tag_t, 197 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 198 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp); 199 static int pccbb_rbus_cb_space_free(cardbus_chipset_tag_t, rbus_tag_t, 200 bus_space_handle_t, bus_size_t); 201 202 #endif /* rbus */ 203 204 #if rbus 205 206 static int pccbb_open_win(struct pccbb_softc *, bus_space_tag_t, 207 bus_addr_t, bus_size_t, bus_space_handle_t, int flags); 208 static int pccbb_close_win(struct pccbb_softc *, bus_space_tag_t, 209 bus_space_handle_t, bus_size_t); 210 static int pccbb_winlist_insert(struct pccbb_win_chain_head *, bus_addr_t, 211 bus_size_t, bus_space_handle_t, int); 212 static int pccbb_winlist_delete(struct pccbb_win_chain_head *, 213 bus_space_handle_t, bus_size_t); 214 static void pccbb_winset(bus_addr_t align, struct pccbb_softc *, 215 bus_space_tag_t); 216 void pccbb_winlist_show(struct pccbb_win_chain *); 217 218 #endif /* rbus */ 219 220 /* for config_defer */ 221 static void pccbb_pci_callback(struct device *); 222 223 #if defined SHOW_REGS 224 static void cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, 225 bus_space_tag_t memt, bus_space_handle_t memh); 226 #endif 227 228 CFATTACH_DECL(cbb_pci, sizeof(struct pccbb_softc), 229 pcicbbmatch, pccbbattach, NULL, NULL); 230 231 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 232 pccbb_pcmcia_mem_alloc, 233 pccbb_pcmcia_mem_free, 234 pccbb_pcmcia_mem_map, 235 pccbb_pcmcia_mem_unmap, 236 pccbb_pcmcia_io_alloc, 237 pccbb_pcmcia_io_free, 238 pccbb_pcmcia_io_map, 239 pccbb_pcmcia_io_unmap, 240 pccbb_pcmcia_intr_establish, 241 pccbb_pcmcia_intr_disestablish, 242 pccbb_pcmcia_socket_enable, 243 pccbb_pcmcia_socket_disable, 244 pccbb_pcmcia_socket_settype, 245 pccbb_pcmcia_card_detect 246 }; 247 248 #if rbus 249 static struct cardbus_functions pccbb_funcs = { 250 pccbb_rbus_cb_space_alloc, 251 pccbb_rbus_cb_space_free, 252 pccbb_cb_intr_establish, 253 pccbb_cb_intr_disestablish, 254 pccbb_ctrl, 255 pccbb_power, 256 pccbb_make_tag, 257 pccbb_free_tag, 258 pccbb_conf_read, 259 pccbb_conf_write, 260 }; 261 #else 262 static struct cardbus_functions pccbb_funcs = { 263 pccbb_ctrl, 264 pccbb_power, 265 pccbb_mem_open, 266 pccbb_mem_close, 267 pccbb_io_open, 268 pccbb_io_close, 269 pccbb_cb_intr_establish, 270 pccbb_cb_intr_disestablish, 271 pccbb_make_tag, 272 pccbb_conf_read, 273 pccbb_conf_write, 274 }; 275 #endif 276 277 int 278 pcicbbmatch(struct device *parent, struct cfdata *match, void *aux) 279 { 280 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 281 282 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 283 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 284 PCI_INTERFACE(pa->pa_class) == 0) { 285 return 1; 286 } 287 288 return 0; 289 } 290 291 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 292 | ((prod) << PCI_PRODUCT_SHIFT)) 293 294 const struct yenta_chipinfo { 295 pcireg_t yc_id; /* vendor tag | product tag */ 296 int yc_chiptype; 297 int yc_flags; 298 } yc_chipsets[] = { 299 /* Texas Instruments chips */ 300 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 301 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 302 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 303 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 304 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI125X, 305 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 306 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 307 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 308 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 309 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 310 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 311 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 312 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI125X, 313 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 314 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI125X, 315 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 316 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 317 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 318 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 319 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 320 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 321 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 322 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI125X, 323 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 324 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 325 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 326 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1520), CB_TI12XX, 327 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 328 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4410YENTA), CB_TI12XX, 329 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 330 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4520YENTA), CB_TI12XX, 331 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 332 333 /* Ricoh chips */ 334 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 335 PCCBB_PCMCIA_MEM_32}, 336 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 337 PCCBB_PCMCIA_MEM_32}, 338 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 339 PCCBB_PCMCIA_MEM_32}, 340 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 341 PCCBB_PCMCIA_MEM_32}, 342 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 343 PCCBB_PCMCIA_MEM_32}, 344 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 345 PCCBB_PCMCIA_MEM_32}, 346 347 /* Toshiba products */ 348 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 349 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 350 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 351 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 352 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 353 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 354 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 355 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 356 357 /* Cirrus Logic products */ 358 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 359 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 360 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 361 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 362 363 /* sentinel, or Generic chip */ 364 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 365 }; 366 367 static int 368 cb_chipset(u_int32_t pci_id, int *flagp) 369 { 370 const struct yenta_chipinfo *yc; 371 372 /* Loop over except the last default entry. */ 373 for (yc = yc_chipsets; yc < yc_chipsets + 374 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 375 if (pci_id == yc->yc_id) 376 break; 377 378 if (flagp != NULL) 379 *flagp = yc->yc_flags; 380 381 return (yc->yc_chiptype); 382 } 383 384 static void 385 pccbb_shutdown(void *arg) 386 { 387 struct pccbb_softc *sc = arg; 388 pcireg_t command; 389 390 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 391 392 /* 393 * turn off power 394 * 395 * XXX - do not turn off power if chipset is TI 113X because 396 * only TI 1130 with PowerMac 2400 hangs in pccbb_power(). 397 */ 398 if (sc->sc_chipset != CB_TI113X) { 399 pccbb_power((cardbus_chipset_tag_t)sc, 400 CARDBUS_VCC_0V | CARDBUS_VPP_0V); 401 } 402 403 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 404 0); 405 406 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 407 408 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 409 PCI_COMMAND_MASTER_ENABLE); 410 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 411 412 } 413 414 void 415 pccbbattach(struct device *parent, struct device *self, void *aux) 416 { 417 struct pccbb_softc *sc = (void *)self; 418 struct pci_attach_args *pa = aux; 419 pci_chipset_tag_t pc = pa->pa_pc; 420 pcireg_t busreg, reg, sock_base; 421 bus_addr_t sockbase; 422 char devinfo[256]; 423 int flags; 424 int pwrmgt_offs; 425 426 #ifdef __HAVE_PCCBB_ATTACH_HOOK 427 pccbb_attach_hook(parent, self, pa); 428 #endif 429 430 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 431 432 pci_devinfo(pa->pa_id, 0, 0, devinfo, sizeof(devinfo)); 433 printf(": %s (rev. 0x%02x)", devinfo, PCI_REVISION(pa->pa_class)); 434 DPRINTF((" (chipflags %x)", flags)); 435 printf("\n"); 436 437 TAILQ_INIT(&sc->sc_memwindow); 438 TAILQ_INIT(&sc->sc_iowindow); 439 440 #if rbus 441 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 442 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 443 444 #if 0 445 printf("pa->pa_memt: %08x vs rbus_mem->rb_bt: %08x\n", 446 pa->pa_memt, sc->sc_rbus_memt->rb_bt); 447 #endif 448 #endif /* rbus */ 449 450 sc->sc_flags &= ~CBB_MEMHMAPPED; 451 452 /* power management: set D0 state */ 453 sc->sc_pwrmgt_offs = 0; 454 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, 455 &pwrmgt_offs, 0)) { 456 reg = pci_conf_read(pc, pa->pa_tag, pwrmgt_offs + PCI_PMCSR); 457 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 458 reg & 0x100 /* PCI_PMCSR_PME_EN */) { 459 reg &= ~PCI_PMCSR_STATE_MASK; 460 reg |= PCI_PMCSR_STATE_D0; 461 reg &= ~(0x100 /* PCI_PMCSR_PME_EN */); 462 pci_conf_write(pc, pa->pa_tag, 463 pwrmgt_offs + PCI_PMCSR, reg); 464 } 465 466 sc->sc_pwrmgt_offs = pwrmgt_offs; 467 } 468 469 /* 470 * MAP socket registers and ExCA registers on memory-space 471 * When no valid address is set on socket base registers (on pci 472 * config space), get it not polite way. 473 */ 474 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 475 476 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 477 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 478 /* The address must be valid. */ 479 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 480 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL)) { 481 printf("%s: can't map socket base address 0x%lx\n", 482 sc->sc_dev.dv_xname, (unsigned long)sock_base); 483 /* 484 * I think it's funny: socket base registers must be 485 * mapped on memory space, but ... 486 */ 487 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 488 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 489 NULL)) { 490 printf("%s: can't map socket base address" 491 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 492 (unsigned long)sockbase); 493 /* give up... allocate reg space via rbus. */ 494 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 495 } else 496 sc->sc_flags |= CBB_MEMHMAPPED; 497 } else { 498 DPRINTF(("%s: socket base address 0x%lx\n", 499 sc->sc_dev.dv_xname, (unsigned long)sockbase)); 500 sc->sc_flags |= CBB_MEMHMAPPED; 501 } 502 } 503 504 sc->sc_mem_start = 0; /* XXX */ 505 sc->sc_mem_end = 0xffffffff; /* XXX */ 506 507 /* 508 * When interrupt isn't routed correctly, give up probing cbb and do 509 * not kill pcic-compatible port. 510 * 511 * However, if we are using an ioapic, avoid this check -- pa_intrline 512 * may well be zero, with the interrupt routed through the apic. 513 */ 514 515 #if NIOAPIC == 0 && NACPI == 0 516 if ((0 == pa->pa_intrline) || (255 == pa->pa_intrline)) { 517 printf("%s: NOT USED because of unconfigured interrupt\n", 518 sc->sc_dev.dv_xname); 519 return; 520 } 521 #endif 522 523 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 524 525 /* pccbb_machdep.c end */ 526 527 #if defined CBB_DEBUG 528 { 529 static const char *intrname[] = { "NON", "A", "B", "C", "D" }; 530 printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname, 531 intrname[pa->pa_intrpin], pa->pa_intrline); 532 } 533 #endif 534 535 /* setup softc */ 536 sc->sc_pc = pc; 537 sc->sc_iot = pa->pa_iot; 538 sc->sc_memt = pa->pa_memt; 539 sc->sc_dmat = pa->pa_dmat; 540 sc->sc_tag = pa->pa_tag; 541 sc->sc_function = pa->pa_function; 542 sc->sc_sockbase = sock_base; 543 sc->sc_busnum = busreg; 544 545 memcpy(&sc->sc_pa, pa, sizeof(*pa)); 546 547 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 548 549 shutdownhook_establish(pccbb_shutdown, sc); 550 551 /* Disable legacy register mapping. */ 552 switch (sc->sc_chipset) { 553 case CB_RX5C46X: /* fallthrough */ 554 #if 0 555 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 556 case CB_RX5C47X: 557 #endif 558 /* 559 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 560 * cannot be disabled by substituting 0 into PCI_LEGACY 561 * register. Ricoh CardBus bridges have special bits on Bridge 562 * control reg (addr 0x3e on PCI config space). 563 */ 564 reg = pci_conf_read(pc, pa->pa_tag, PCI_BCR_INTR); 565 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 566 pci_conf_write(pc, pa->pa_tag, PCI_BCR_INTR, reg); 567 break; 568 569 default: 570 /* XXX I don't know proper way to kill legacy I/O. */ 571 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 572 break; 573 } 574 575 config_defer(self, pccbb_pci_callback); 576 } 577 578 579 580 581 /* 582 * static void pccbb_pci_callback(struct device *self) 583 * 584 * The actual attach routine: get memory space for YENTA register 585 * space, setup YENTA register and route interrupt. 586 * 587 * This function should be deferred because this device may obtain 588 * memory space dynamically. This function must avoid obtaining 589 * memory area which has already kept for another device. 590 */ 591 static void 592 pccbb_pci_callback(struct device *self) 593 { 594 struct pccbb_softc *sc = (void *)self; 595 pci_chipset_tag_t pc = sc->sc_pc; 596 pci_intr_handle_t ih; 597 const char *intrstr = NULL; 598 bus_addr_t sockbase; 599 struct cbslot_attach_args cba; 600 struct pcmciabus_attach_args paa; 601 struct cardslot_attach_args caa; 602 struct cardslot_softc *csc; 603 604 if (!(sc->sc_flags & CBB_MEMHMAPPED)) { 605 /* The socket registers aren't mapped correctly. */ 606 #if rbus 607 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 608 (sc->sc_chipset == CB_RX5C47X 609 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 610 0, &sockbase, &sc->sc_base_memh)) { 611 return; 612 } 613 sc->sc_base_memt = sc->sc_memt; 614 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 615 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 616 sc->sc_dev.dv_xname, (unsigned long)sockbase, 617 (unsigned long)pci_conf_read(pc, sc->sc_tag, 618 PCI_SOCKBASE))); 619 #else 620 sc->sc_base_memt = sc->sc_memt; 621 #if !defined CBB_PCI_BASE 622 #define CBB_PCI_BASE 0x20000000 623 #endif 624 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 625 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 626 /* cannot allocate memory space */ 627 return; 628 } 629 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 630 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 631 sc->sc_dev.dv_xname, (unsigned long)sock_base, 632 (unsigned long)pci_conf_read(pc, 633 sc->sc_tag, PCI_SOCKBASE))); 634 sc->sc_sockbase = sockbase; 635 #endif 636 sc->sc_flags |= CBB_MEMHMAPPED; 637 } 638 639 /* bus bridge initialization */ 640 pccbb_chipinit(sc); 641 642 /* clear data structure for child device interrupt handlers */ 643 LIST_INIT(&sc->sc_pil); 644 sc->sc_pil_intr_enable = 1; 645 646 /* Map and establish the interrupt. */ 647 if (pci_intr_map(&sc->sc_pa, &ih)) { 648 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 649 return; 650 } 651 intrstr = pci_intr_string(pc, ih); 652 653 /* 654 * XXX pccbbintr should be called under the priority lower 655 * than any other hard interupts. 656 */ 657 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 658 659 if (sc->sc_ih == NULL) { 660 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 661 if (intrstr != NULL) { 662 printf(" at %s", intrstr); 663 } 664 printf("\n"); 665 return; 666 } 667 668 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 669 powerhook_establish(sc->sc_dev.dv_xname, pccbb_powerhook, sc); 670 671 { 672 u_int32_t sockstat; 673 674 sockstat = bus_space_read_4(sc->sc_base_memt, 675 sc->sc_base_memh, CB_SOCKET_STAT); 676 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 677 sc->sc_flags |= CBB_CARDEXIST; 678 } 679 } 680 681 /* 682 * attach cardbus 683 */ 684 { 685 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 686 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 687 688 /* initialize cbslot_attach */ 689 cba.cba_busname = "cardbus"; 690 cba.cba_iot = sc->sc_iot; 691 cba.cba_memt = sc->sc_memt; 692 cba.cba_dmat = sc->sc_dmat; 693 cba.cba_bus = (busreg >> 8) & 0x0ff; 694 cba.cba_cc = (void *)sc; 695 cba.cba_cf = &pccbb_funcs; 696 cba.cba_intrline = sc->sc_pa.pa_intrline; 697 698 #if rbus 699 cba.cba_rbus_iot = sc->sc_rbus_iot; 700 cba.cba_rbus_memt = sc->sc_rbus_memt; 701 #endif 702 703 cba.cba_cacheline = PCI_CACHELINE(bhlc); 704 cba.cba_lattimer = PCI_CB_LATENCY(busreg); 705 706 if (bootverbose) { 707 printf("%s: cacheline 0x%x lattimer 0x%x\n", 708 sc->sc_dev.dv_xname, cba.cba_cacheline, 709 cba.cba_lattimer); 710 printf("%s: bhlc 0x%x lscp 0x%x\n", 711 sc->sc_dev.dv_xname, bhlc, busreg); 712 } 713 #if defined SHOW_REGS 714 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 715 sc->sc_base_memh); 716 #endif 717 } 718 719 pccbb_pcmcia_attach_setup(sc, &paa); 720 caa.caa_cb_attach = NULL; 721 if (cba.cba_bus == 0) 722 printf("%s: secondary bus number uninitialized; try PCI_BUS_FIXUP\n", sc->sc_dev.dv_xname); 723 else 724 caa.caa_cb_attach = &cba; 725 caa.caa_16_attach = &paa; 726 caa.caa_ph = &sc->sc_pcmcia_h; 727 728 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 729 DPRINTF(("%s: found cardslot\n", __func__)); 730 sc->sc_csc = csc; 731 } 732 733 return; 734 } 735 736 737 738 739 740 /* 741 * static void pccbb_chipinit(struct pccbb_softc *sc) 742 * 743 * This function initialize YENTA chip registers listed below: 744 * 1) PCI command reg, 745 * 2) PCI and CardBus latency timer, 746 * 3) route PCI interrupt, 747 * 4) close all memory and io windows. 748 * 5) turn off bus power. 749 * 6) card detect and power cycle interrupts on. 750 * 7) clear interrupt 751 */ 752 static void 753 pccbb_chipinit(struct pccbb_softc *sc) 754 { 755 pci_chipset_tag_t pc = sc->sc_pc; 756 pcitag_t tag = sc->sc_tag; 757 bus_space_tag_t bmt = sc->sc_base_memt; 758 bus_space_handle_t bmh = sc->sc_base_memh; 759 pcireg_t reg; 760 761 /* 762 * Set PCI command reg. 763 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 764 */ 765 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 766 /* I believe it is harmless. */ 767 reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 768 PCI_COMMAND_MASTER_ENABLE); 769 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg); 770 771 /* 772 * Set CardBus latency timer. 773 */ 774 reg = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 775 if (PCI_CB_LATENCY(reg) < 0x20) { 776 reg &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 777 reg |= (0x20 << PCI_CB_LATENCY_SHIFT); 778 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, reg); 779 } 780 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 781 PCI_CB_LATENCY(reg), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 782 783 /* 784 * Set PCI latency timer. 785 */ 786 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 787 if (PCI_LATTIMER(reg) < 0x10) { 788 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 789 reg |= (0x10 << PCI_LATTIMER_SHIFT); 790 pci_conf_write(pc, tag, PCI_BHLC_REG, reg); 791 } 792 DPRINTF(("PCI latency timer 0x%x (%x)\n", 793 PCI_LATTIMER(reg), pci_conf_read(pc, tag, PCI_BHLC_REG))); 794 795 796 /* Route functional interrupts to PCI. */ 797 reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 798 reg |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 799 reg |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 800 reg |= CB_BCR_RESET_ENABLE; /* assert reset */ 801 pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 802 803 switch (sc->sc_chipset) { 804 case CB_TI113X: 805 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 806 /* This bit is shared, but may read as 0 on some chips, so set 807 it explicitly on both functions. */ 808 reg |= PCI113X_CBCTRL_PCI_IRQ_ENA; 809 /* CSC intr enable */ 810 reg |= PCI113X_CBCTRL_PCI_CSC; 811 /* functional intr prohibit | prohibit ISA routing */ 812 reg &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 813 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 814 break; 815 816 case CB_TI12XX: 817 /* 818 * Some TI 12xx (and [14][45]xx) based pci cards 819 * sometimes have issues with the MFUNC register not 820 * being initialized due to a bad EEPROM on board. 821 * Laptops that this matters on have this register 822 * properly initialized. 823 * 824 * The TI125X parts have a different register. 825 */ 826 reg = pci_conf_read(pc, tag, PCI12XX_MFUNC); 827 if (reg == 0) { 828 reg &= ~PCI12XX_MFUNC_PIN0; 829 reg |= PCI12XX_MFUNC_PIN0_INTA; 830 if ((pci_conf_read(pc, tag, PCI_SYSCTRL) & 831 PCI12XX_SYSCTRL_INTRTIE) == 0) { 832 reg &= ~PCI12XX_MFUNC_PIN1; 833 reg |= PCI12XX_MFUNC_PIN1_INTB; 834 } 835 pci_conf_write(pc, tag, PCI12XX_MFUNC, reg); 836 } 837 /* fallthrough */ 838 839 case CB_TI125X: 840 /* 841 * Disable zoom video. Some machines initialize this 842 * improperly and experience has shown that this helps 843 * prevent strange behavior. 844 */ 845 pci_conf_write(pc, tag, PCI12XX_MMCTRL, 0); 846 847 reg = pci_conf_read(pc, tag, PCI_SYSCTRL); 848 reg |= PCI12XX_SYSCTRL_VCCPROT; 849 pci_conf_write(pc, tag, PCI_SYSCTRL, reg); 850 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 851 reg |= PCI12XX_CBCTRL_CSC; 852 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 853 break; 854 855 case CB_TOPIC95B: 856 reg = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 857 reg |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 858 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, reg); 859 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 860 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 861 sc->sc_dev.dv_xname, reg)); 862 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 863 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 864 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 865 DPRINTF(("0x%x\n", reg)); 866 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 867 break; 868 869 case CB_TOPIC97: 870 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 871 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 872 sc->sc_dev.dv_xname, reg)); 873 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 874 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 875 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 876 reg |= TOPIC97_SLOT_CTRL_PCIINT; 877 reg &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 878 DPRINTF(("0x%x\n", reg)); 879 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 880 /* make sure to assert LV card support bits */ 881 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 882 0x800 + 0x3e, 883 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 884 0x800 + 0x3e) | 0x03); 885 break; 886 } 887 888 /* Close all memory and I/O windows. */ 889 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 890 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 891 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 892 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 893 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 894 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 895 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 896 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 897 898 /* reset 16-bit pcmcia bus */ 899 bus_space_write_1(bmt, bmh, 0x800 + PCIC_INTR, 900 bus_space_read_1(bmt, bmh, 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 901 902 /* turn off power */ 903 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 904 905 /* CSC Interrupt: Card detect and power cycle interrupts on */ 906 reg = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 907 reg |= CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; 908 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, reg); 909 /* reset interrupt */ 910 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 911 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 912 } 913 914 915 916 917 /* 918 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 919 * struct pcmciabus_attach_args *paa) 920 * 921 * This function attaches 16-bit PCcard bus. 922 */ 923 STATIC void 924 pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 925 struct pcmciabus_attach_args *paa) 926 { 927 struct pcic_handle *ph = &sc->sc_pcmcia_h; 928 #if rbus 929 rbus_tag_t rb; 930 #endif 931 932 /* initialize pcmcia part in pccbb_softc */ 933 ph->ph_parent = (struct device *)sc; 934 ph->sock = sc->sc_function; 935 ph->flags = 0; 936 ph->shutdown = 0; 937 ph->ih_irq = sc->sc_pa.pa_intrline; 938 ph->ph_bus_t = sc->sc_base_memt; 939 ph->ph_bus_h = sc->sc_base_memh; 940 ph->ph_read = pccbb_pcmcia_read; 941 ph->ph_write = pccbb_pcmcia_write; 942 sc->sc_pct = &pccbb_pcmcia_funcs; 943 944 /* 945 * We need to do a few things here: 946 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 947 * setting the IRQ numbers to 0. 948 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 949 * routing of CSC interrupts (e.g. card removal) to PCI while in 950 * PCMCIA mode. We just leave this set all the time. 951 * 3) Enable card insertion/removal interrupts in case the chip also 952 * needs that while in PCMCIA mode. 953 * 4) Clear any pending CSC interrupt. 954 */ 955 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE); 956 if (sc->sc_chipset == CB_TI113X) { 957 Pcic_write(ph, PCIC_CSC_INTR, 0); 958 } else { 959 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 960 Pcic_read(ph, PCIC_CSC); 961 } 962 963 /* initialize pcmcia bus attachment */ 964 paa->paa_busname = "pcmcia"; 965 paa->pct = sc->sc_pct; 966 paa->pch = ph; 967 paa->iobase = 0; /* I don't use them */ 968 paa->iosize = 0; 969 #if rbus 970 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 971 paa->iobase = rb->rb_start + rb->rb_offset; 972 paa->iosize = rb->rb_end - rb->rb_start; 973 #endif 974 975 return; 976 } 977 978 #if 0 979 STATIC void 980 pccbb_pcmcia_attach_card(struct pcic_handle *ph) 981 { 982 if (ph->flags & PCIC_FLAG_CARDP) { 983 panic("pccbb_pcmcia_attach_card: already attached"); 984 } 985 986 /* call the MI attach function */ 987 pcmcia_card_attach(ph->pcmcia); 988 989 ph->flags |= PCIC_FLAG_CARDP; 990 } 991 992 STATIC void 993 pccbb_pcmcia_detach_card(struct pcic_handle *ph, int flags) 994 { 995 if (!(ph->flags & PCIC_FLAG_CARDP)) { 996 panic("pccbb_pcmcia_detach_card: already detached"); 997 } 998 999 ph->flags &= ~PCIC_FLAG_CARDP; 1000 1001 /* call the MI detach function */ 1002 pcmcia_card_detach(ph->pcmcia, flags); 1003 } 1004 #endif 1005 1006 /* 1007 * int pccbbintr(arg) 1008 * void *arg; 1009 * This routine handles the interrupt from Yenta PCI-CardBus bridge 1010 * itself. 1011 */ 1012 int 1013 pccbbintr(void *arg) 1014 { 1015 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1016 u_int32_t sockevent, sockstate; 1017 bus_space_tag_t memt = sc->sc_base_memt; 1018 bus_space_handle_t memh = sc->sc_base_memh; 1019 struct pcic_handle *ph = &sc->sc_pcmcia_h; 1020 1021 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 1022 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 1023 Pcic_read(ph, PCIC_CSC); 1024 1025 if (sockevent == 0) { 1026 /* This intr is not for me: it may be for my child devices. */ 1027 if (sc->sc_pil_intr_enable) { 1028 return pccbbintr_function(sc); 1029 } else { 1030 return 0; 1031 } 1032 } 1033 1034 if (sockevent & CB_SOCKET_EVENT_CD) { 1035 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1036 if (0x00 != (sockstate & CB_SOCKET_STAT_CD)) { 1037 /* A card should be removed. */ 1038 if (sc->sc_flags & CBB_CARDEXIST) { 1039 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 1040 sockevent)); 1041 DPRINTF((" card removed, 0x%08x\n", sockstate)); 1042 sc->sc_flags &= ~CBB_CARDEXIST; 1043 if (sc->sc_csc->sc_status & 1044 CARDSLOT_STATUS_CARD_16) { 1045 #if 0 1046 struct pcic_handle *ph = 1047 &sc->sc_pcmcia_h; 1048 1049 pcmcia_card_deactivate(ph->pcmcia); 1050 pccbb_pcmcia_socket_disable(ph); 1051 pccbb_pcmcia_detach_card(ph, 1052 DETACH_FORCE); 1053 #endif 1054 cardslot_event_throw(sc->sc_csc, 1055 CARDSLOT_EVENT_REMOVAL_16); 1056 } else if (sc->sc_csc->sc_status & 1057 CARDSLOT_STATUS_CARD_CB) { 1058 /* Cardbus intr removed */ 1059 cardslot_event_throw(sc->sc_csc, 1060 CARDSLOT_EVENT_REMOVAL_CB); 1061 } 1062 } else if (sc->sc_flags & CBB_INSERTING) { 1063 sc->sc_flags &= ~CBB_INSERTING; 1064 callout_stop(&sc->sc_insert_ch); 1065 } 1066 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 1067 /* 1068 * The pccbbintr may called from powerdown hook when 1069 * the system resumed, to detect the card 1070 * insertion/removal during suspension. 1071 */ 1072 (sc->sc_flags & CBB_CARDEXIST) == 0) { 1073 if (sc->sc_flags & CBB_INSERTING) { 1074 callout_stop(&sc->sc_insert_ch); 1075 } 1076 callout_reset(&sc->sc_insert_ch, hz / 5, 1077 pci113x_insert, sc); 1078 sc->sc_flags |= CBB_INSERTING; 1079 } 1080 } 1081 1082 if (sockevent & CB_SOCKET_EVENT_POWER) { 1083 DPRINTF(("Powercycling because of socket event\n")); 1084 /* XXX: Does not happen when attaching a 16-bit card */ 1085 sc->sc_pwrcycle++; 1086 wakeup(&sc->sc_pwrcycle); 1087 } 1088 1089 return (1); 1090 } 1091 1092 /* 1093 * static int pccbbintr_function(struct pccbb_softc *sc) 1094 * 1095 * This function calls each interrupt handler registered at the 1096 * bridge. The interrupt handlers are called in registered order. 1097 */ 1098 static int 1099 pccbbintr_function(struct pccbb_softc *sc) 1100 { 1101 int retval = 0, val; 1102 struct pccbb_intrhand_list *pil; 1103 int s; 1104 1105 for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1106 pil = LIST_NEXT(pil, pil_next)) { 1107 s = splraiseipl(pil->pil_icookie); 1108 val = (*pil->pil_func)(pil->pil_arg); 1109 splx(s); 1110 1111 retval = retval == 1 ? 1 : 1112 retval == 0 ? val : val != 0 ? val : retval; 1113 } 1114 1115 return retval; 1116 } 1117 1118 static void 1119 pci113x_insert(void *arg) 1120 { 1121 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1122 u_int32_t sockevent, sockstate; 1123 1124 if (!(sc->sc_flags & CBB_INSERTING)) { 1125 /* We add a card only under inserting state. */ 1126 return; 1127 } 1128 sc->sc_flags &= ~CBB_INSERTING; 1129 1130 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1131 CB_SOCKET_EVENT); 1132 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1133 CB_SOCKET_STAT); 1134 1135 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1136 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1137 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1138 sc->sc_flags |= CBB_CARDEXIST; 1139 /* call pccard interrupt handler here */ 1140 if (sockstate & CB_SOCKET_STAT_16BIT) { 1141 /* 16-bit card found */ 1142 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1143 cardslot_event_throw(sc->sc_csc, 1144 CARDSLOT_EVENT_INSERTION_16); 1145 } else if (sockstate & CB_SOCKET_STAT_CB) { 1146 /* cardbus card found */ 1147 /* cardbus_attach_card(sc->sc_csc); */ 1148 cardslot_event_throw(sc->sc_csc, 1149 CARDSLOT_EVENT_INSERTION_CB); 1150 } else { 1151 /* who are you? */ 1152 } 1153 } else { 1154 callout_reset(&sc->sc_insert_ch, hz / 10, 1155 pci113x_insert, sc); 1156 } 1157 } 1158 1159 #define PCCBB_PCMCIA_OFFSET 0x800 1160 static u_int8_t 1161 pccbb_pcmcia_read(struct pcic_handle *ph, int reg) 1162 { 1163 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1164 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1165 1166 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1167 PCCBB_PCMCIA_OFFSET + reg); 1168 } 1169 1170 static void 1171 pccbb_pcmcia_write(struct pcic_handle *ph, int reg, u_int8_t val) 1172 { 1173 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1174 val); 1175 1176 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1177 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1178 } 1179 1180 /* 1181 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1182 */ 1183 STATIC int 1184 pccbb_ctrl(cardbus_chipset_tag_t ct, int command) 1185 { 1186 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1187 1188 switch (command) { 1189 case CARDBUS_CD: 1190 if (2 == pccbb_detect_card(sc)) { 1191 int retval = 0; 1192 int status = cb_detect_voltage(sc); 1193 if (PCCARD_VCC_5V & status) { 1194 retval |= CARDBUS_5V_CARD; 1195 } 1196 if (PCCARD_VCC_3V & status) { 1197 retval |= CARDBUS_3V_CARD; 1198 } 1199 if (PCCARD_VCC_XV & status) { 1200 retval |= CARDBUS_XV_CARD; 1201 } 1202 if (PCCARD_VCC_YV & status) { 1203 retval |= CARDBUS_YV_CARD; 1204 } 1205 return retval; 1206 } else { 1207 return 0; 1208 } 1209 case CARDBUS_RESET: 1210 return cb_reset(sc); 1211 case CARDBUS_IO_ENABLE: /* fallthrough */ 1212 case CARDBUS_IO_DISABLE: /* fallthrough */ 1213 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1214 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1215 case CARDBUS_BM_ENABLE: /* fallthrough */ 1216 case CARDBUS_BM_DISABLE: /* fallthrough */ 1217 /* XXX: I think we don't need to call this function below. */ 1218 return pccbb_cardenable(sc, command); 1219 } 1220 1221 return 0; 1222 } 1223 1224 /* 1225 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1226 * This function returns true when it succeeds and returns false when 1227 * it fails. 1228 */ 1229 STATIC int 1230 pccbb_power(cardbus_chipset_tag_t ct, int command) 1231 { 1232 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1233 u_int32_t status, sock_ctrl, reg_ctrl; 1234 bus_space_tag_t memt = sc->sc_base_memt; 1235 bus_space_handle_t memh = sc->sc_base_memh; 1236 int on = 0, pwrcycle; 1237 1238 DPRINTF(("pccbb_power: %s and %s [0x%x]\n", 1239 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1240 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1241 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1242 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1243 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1244 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1245 "UNKNOWN", 1246 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1247 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1248 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1249 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1250 "UNKNOWN", command)); 1251 1252 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1253 sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1254 1255 switch (command & CARDBUS_VCCMASK) { 1256 case CARDBUS_VCC_UC: 1257 break; 1258 case CARDBUS_VCC_5V: 1259 on++; 1260 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1261 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1262 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1263 } else { 1264 printf("%s: BAD voltage request: no 5 V card\n", 1265 sc->sc_dev.dv_xname); 1266 return 0; 1267 } 1268 break; 1269 case CARDBUS_VCC_3V: 1270 on++; 1271 if (CB_SOCKET_STAT_3VCARD & status) { 1272 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1273 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1274 } else { 1275 printf("%s: BAD voltage request: no 3.3 V card\n", 1276 sc->sc_dev.dv_xname); 1277 return 0; 1278 } 1279 break; 1280 case CARDBUS_VCC_0V: 1281 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1282 break; 1283 default: 1284 return 0; /* power NEVER changed */ 1285 } 1286 1287 switch (command & CARDBUS_VPPMASK) { 1288 case CARDBUS_VPP_UC: 1289 break; 1290 case CARDBUS_VPP_0V: 1291 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1292 break; 1293 case CARDBUS_VPP_VCC: 1294 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1295 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1296 break; 1297 case CARDBUS_VPP_12V: 1298 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1299 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1300 break; 1301 } 1302 1303 pwrcycle = sc->sc_pwrcycle; 1304 1305 #if 0 1306 DPRINTF(("sock_ctrl: 0x%x\n", sock_ctrl)); 1307 #endif 1308 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1309 1310 if (on) { 1311 int s, error = 0; 1312 struct timeval before, after, diff; 1313 1314 DPRINTF(("Waiting for bridge to power up\n")); 1315 microtime(&before); 1316 s = splbio(); 1317 while (pwrcycle == sc->sc_pwrcycle) { 1318 /* 1319 * XXX: Set timeout to 200ms because power cycle event 1320 * will never happen when attaching a 16-bit card. 1321 */ 1322 if ((error = tsleep(&sc->sc_pwrcycle, PWAIT, "pccpwr", 1323 hz / 5)) == EWOULDBLOCK) 1324 break; 1325 } 1326 splx(s); 1327 microtime(&after); 1328 timersub(&after, &before, &diff); 1329 aprint_debug("%s: wait took%s %ld.%06lds\n", 1330 sc->sc_dev.dv_xname, 1331 error == EWOULDBLOCK ? " too long" : "", 1332 diff.tv_sec, diff.tv_usec); 1333 1334 /* 1335 * Ok, wait a bit longer for things to settle. 1336 */ 1337 if (sc->sc_chipset == CB_TOPIC95B) 1338 delay_ms(100, sc); 1339 } 1340 1341 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1342 1343 if (on && sc->sc_chipset != CB_TOPIC95B) { 1344 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0) 1345 printf("%s: power on failed?\n", sc->sc_dev.dv_xname); 1346 } 1347 1348 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1349 printf("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1350 sc->sc_dev.dv_xname, sock_ctrl, status); 1351 printf("%s: disabling socket\n", sc->sc_dev.dv_xname); 1352 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1353 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1354 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1355 status &= ~CB_SOCKET_STAT_BADVCC; 1356 bus_space_write_4(memt, memh, CB_SOCKET_STAT, status); 1357 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1358 CB_SOCKET_STAT)); 1359 return 0; 1360 } 1361 1362 if (sc->sc_chipset == CB_TOPIC97) { 1363 reg_ctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL); 1364 reg_ctrl &= ~TOPIC97_REG_CTRL_TESTMODE; 1365 if ((command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V) 1366 reg_ctrl &= ~TOPIC97_REG_CTRL_CLKRUN_ENA; 1367 else 1368 reg_ctrl |= TOPIC97_REG_CTRL_CLKRUN_ENA; 1369 pci_conf_write(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL, reg_ctrl); 1370 } 1371 1372 return 1; /* power changed correctly */ 1373 } 1374 1375 #if defined CB_PCMCIA_POLL 1376 struct cb_poll_str { 1377 void *arg; 1378 int (*func)(void *); 1379 int level; 1380 pccard_chipset_tag_t ct; 1381 int count; 1382 struct callout poll_ch; 1383 }; 1384 1385 static struct cb_poll_str cb_poll[10]; 1386 static int cb_poll_n = 0; 1387 1388 static void cb_pcmcia_poll(void *arg); 1389 1390 static void 1391 cb_pcmcia_poll(void *arg) 1392 { 1393 struct cb_poll_str *poll = arg; 1394 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1395 struct pccbb_softc *sc = psc->cpc_parent; 1396 int s; 1397 u_int32_t spsr; /* socket present-state reg */ 1398 1399 callout_reset(&poll->poll_ch, hz / 10, cb_pcmcia_poll, poll); 1400 switch (poll->level) { 1401 case IPL_NET: 1402 s = splnet(); 1403 break; 1404 case IPL_BIO: 1405 s = splbio(); 1406 break; 1407 case IPL_TTY: /* fallthrough */ 1408 default: 1409 s = spltty(); 1410 break; 1411 } 1412 1413 spsr = 1414 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1415 CB_SOCKET_STAT); 1416 1417 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1418 if (!(spsr & 0x40)) { /* CINT low */ 1419 #else 1420 if (1) { 1421 #endif 1422 if ((*poll->func) (poll->arg) == 1) { 1423 ++poll->count; 1424 printf("intr: reported from poller, 0x%x\n", spsr); 1425 #if defined LEVEL2 1426 } else { 1427 printf("intr: miss! 0x%x\n", spsr); 1428 #endif 1429 } 1430 } 1431 splx(s); 1432 } 1433 #endif /* defined CB_PCMCIA_POLL */ 1434 1435 /* 1436 * static int pccbb_detect_card(struct pccbb_softc *sc) 1437 * return value: 0 if no card exists. 1438 * 1 if 16-bit card exists. 1439 * 2 if cardbus card exists. 1440 */ 1441 static int 1442 pccbb_detect_card(struct pccbb_softc *sc) 1443 { 1444 bus_space_handle_t base_memh = sc->sc_base_memh; 1445 bus_space_tag_t base_memt = sc->sc_base_memt; 1446 u_int32_t sockstat = 1447 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1448 int retval = 0; 1449 1450 /* CD1 and CD2 asserted */ 1451 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1452 /* card must be present */ 1453 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1454 /* NOTACARD DEASSERTED */ 1455 if (CB_SOCKET_STAT_CB & sockstat) { 1456 /* CardBus mode */ 1457 retval = 2; 1458 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1459 /* 16-bit mode */ 1460 retval = 1; 1461 } 1462 } 1463 } 1464 return retval; 1465 } 1466 1467 /* 1468 * STATIC int cb_reset(struct pccbb_softc *sc) 1469 * This function resets CardBus card. 1470 */ 1471 STATIC int 1472 cb_reset(struct pccbb_softc *sc) 1473 { 1474 /* 1475 * Reset Assert at least 20 ms 1476 * Some machines request longer duration. 1477 */ 1478 int reset_duration = 1479 (sc->sc_chipset == CB_RX5C47X ? 400 : 50); 1480 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1481 1482 /* Reset bit Assert (bit 6 at 0x3E) */ 1483 bcr |= CB_BCR_RESET_ENABLE; 1484 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1485 delay_ms(reset_duration, sc); 1486 1487 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1488 /* Reset bit Deassert (bit 6 at 0x3E) */ 1489 bcr &= ~CB_BCR_RESET_ENABLE; 1490 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1491 delay_ms(reset_duration, sc); 1492 } 1493 /* No card found on the slot. Keep Reset. */ 1494 return 1; 1495 } 1496 1497 /* 1498 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1499 * This function detect card Voltage. 1500 */ 1501 STATIC int 1502 cb_detect_voltage(struct pccbb_softc *sc) 1503 { 1504 u_int32_t psr; /* socket present-state reg */ 1505 bus_space_tag_t iot = sc->sc_base_memt; 1506 bus_space_handle_t ioh = sc->sc_base_memh; 1507 int vol = PCCARD_VCC_UKN; /* set 0 */ 1508 1509 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1510 1511 if (0x400u & psr) { 1512 vol |= PCCARD_VCC_5V; 1513 } 1514 if (0x800u & psr) { 1515 vol |= PCCARD_VCC_3V; 1516 } 1517 1518 return vol; 1519 } 1520 1521 STATIC int 1522 cbbprint(void *aux, const char *pcic) 1523 { 1524 #if 0 1525 struct cbslot_attach_args *cba = aux; 1526 1527 if (cba->cba_slot >= 0) { 1528 aprint_normal(" slot %d", cba->cba_slot); 1529 } 1530 #endif 1531 return UNCONF; 1532 } 1533 1534 /* 1535 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1536 * This function enables and disables the card 1537 */ 1538 STATIC int 1539 pccbb_cardenable(struct pccbb_softc *sc, int function) 1540 { 1541 u_int32_t command = 1542 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1543 1544 DPRINTF(("pccbb_cardenable:")); 1545 switch (function) { 1546 case CARDBUS_IO_ENABLE: 1547 command |= PCI_COMMAND_IO_ENABLE; 1548 break; 1549 case CARDBUS_IO_DISABLE: 1550 command &= ~PCI_COMMAND_IO_ENABLE; 1551 break; 1552 case CARDBUS_MEM_ENABLE: 1553 command |= PCI_COMMAND_MEM_ENABLE; 1554 break; 1555 case CARDBUS_MEM_DISABLE: 1556 command &= ~PCI_COMMAND_MEM_ENABLE; 1557 break; 1558 case CARDBUS_BM_ENABLE: 1559 command |= PCI_COMMAND_MASTER_ENABLE; 1560 break; 1561 case CARDBUS_BM_DISABLE: 1562 command &= ~PCI_COMMAND_MASTER_ENABLE; 1563 break; 1564 default: 1565 return 0; 1566 } 1567 1568 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1569 DPRINTF((" command reg 0x%x\n", command)); 1570 return 1; 1571 } 1572 1573 #if !rbus 1574 static int 1575 pccbb_io_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 1576 { 1577 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1578 int basereg; 1579 int limitreg; 1580 1581 if ((win < 0) || (win > 2)) { 1582 #if defined DIAGNOSTIC 1583 printf("cardbus_io_open: window out of range %d\n", win); 1584 #endif 1585 return 0; 1586 } 1587 1588 basereg = win * 8 + 0x2c; 1589 limitreg = win * 8 + 0x30; 1590 1591 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1592 start, basereg, end, limitreg)); 1593 1594 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1595 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1596 return 1; 1597 } 1598 1599 /* 1600 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1601 */ 1602 static int 1603 pccbb_io_close(cardbus_chipset_tag_t ct, int win) 1604 { 1605 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1606 int basereg; 1607 int limitreg; 1608 1609 if ((win < 0) || (win > 2)) { 1610 #if defined DIAGNOSTIC 1611 printf("cardbus_io_close: window out of range %d\n", win); 1612 #endif 1613 return 0; 1614 } 1615 1616 basereg = win * 8 + 0x2c; 1617 limitreg = win * 8 + 0x30; 1618 1619 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1620 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1621 return 1; 1622 } 1623 1624 static int 1625 pccbb_mem_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 1626 { 1627 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1628 int basereg; 1629 int limitreg; 1630 1631 if ((win < 0) || (win > 2)) { 1632 #if defined DIAGNOSTIC 1633 printf("cardbus_mem_open: window out of range %d\n", win); 1634 #endif 1635 return 0; 1636 } 1637 1638 basereg = win * 8 + 0x1c; 1639 limitreg = win * 8 + 0x20; 1640 1641 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1642 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1643 return 1; 1644 } 1645 1646 static int 1647 pccbb_mem_close(cardbus_chipset_tag_t ct, int win) 1648 { 1649 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1650 int basereg; 1651 int limitreg; 1652 1653 if ((win < 0) || (win > 2)) { 1654 #if defined DIAGNOSTIC 1655 printf("cardbus_mem_close: window out of range %d\n", win); 1656 #endif 1657 return 0; 1658 } 1659 1660 basereg = win * 8 + 0x1c; 1661 limitreg = win * 8 + 0x20; 1662 1663 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1664 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1665 return 1; 1666 } 1667 #endif 1668 1669 /* 1670 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1671 * int irq, 1672 * int level, 1673 * int (* func)(void *), 1674 * void *arg) 1675 * 1676 * This function registers an interrupt handler at the bridge, in 1677 * order not to call the interrupt handlers of child devices when 1678 * a card-deletion interrupt occurs. 1679 * 1680 * The arguments irq and level are not used. 1681 */ 1682 static void * 1683 pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, int irq, int level, 1684 int (*func)(void *), void *arg) 1685 { 1686 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1687 1688 return pccbb_intr_establish(sc, irq, level, func, arg); 1689 } 1690 1691 1692 /* 1693 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1694 * void *ih) 1695 * 1696 * This function removes an interrupt handler pointed by ih. 1697 */ 1698 static void 1699 pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih) 1700 { 1701 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1702 1703 pccbb_intr_disestablish(sc, ih); 1704 } 1705 1706 1707 void 1708 pccbb_intr_route(struct pccbb_softc *sc) 1709 { 1710 pcireg_t bcr, cbctrl; 1711 1712 /* initialize bridge intr routing */ 1713 bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1714 bcr &= ~CB_BCR_INTR_IREQ_ENABLE; 1715 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1716 1717 switch (sc->sc_chipset) { 1718 case CB_TI113X: 1719 cbctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1720 /* functional intr enabled */ 1721 cbctrl |= PCI113X_CBCTRL_PCI_INTR; 1722 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, cbctrl); 1723 break; 1724 default: 1725 break; 1726 } 1727 } 1728 1729 /* 1730 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1731 * int irq, 1732 * int level, 1733 * int (* func)(void *), 1734 * void *arg) 1735 * 1736 * This function registers an interrupt handler at the bridge, in 1737 * order not to call the interrupt handlers of child devices when 1738 * a card-deletion interrupt occurs. 1739 * 1740 * The arguments irq is not used because pccbb selects intr vector. 1741 */ 1742 static void * 1743 pccbb_intr_establish(struct pccbb_softc *sc, int irq, int level, 1744 int (*func)(void *), void *arg) 1745 { 1746 struct pccbb_intrhand_list *pil, *newpil; 1747 1748 DPRINTF(("pccbb_intr_establish start. %p\n", LIST_FIRST(&sc->sc_pil))); 1749 1750 if (LIST_EMPTY(&sc->sc_pil)) { 1751 pccbb_intr_route(sc); 1752 } 1753 1754 /* 1755 * Allocate a room for interrupt handler structure. 1756 */ 1757 if (NULL == (newpil = 1758 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1759 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1760 return NULL; 1761 } 1762 1763 newpil->pil_func = func; 1764 newpil->pil_arg = arg; 1765 newpil->pil_icookie = makeiplcookie(level); 1766 1767 if (LIST_EMPTY(&sc->sc_pil)) { 1768 LIST_INSERT_HEAD(&sc->sc_pil, newpil, pil_next); 1769 } else { 1770 for (pil = LIST_FIRST(&sc->sc_pil); 1771 LIST_NEXT(pil, pil_next) != NULL; 1772 pil = LIST_NEXT(pil, pil_next)); 1773 LIST_INSERT_AFTER(pil, newpil, pil_next); 1774 } 1775 1776 DPRINTF(("pccbb_intr_establish add pil. %p\n", 1777 LIST_FIRST(&sc->sc_pil))); 1778 1779 return newpil; 1780 } 1781 1782 /* 1783 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1784 * void *ih) 1785 * 1786 * This function removes an interrupt handler pointed by ih. ih 1787 * should be the value returned by cardbus_intr_establish() or 1788 * NULL. 1789 * 1790 * When ih is NULL, this function will do nothing. 1791 */ 1792 static void 1793 pccbb_intr_disestablish(struct pccbb_softc *sc, void *ih) 1794 { 1795 struct pccbb_intrhand_list *pil; 1796 pcireg_t reg; 1797 1798 DPRINTF(("pccbb_intr_disestablish start. %p\n", 1799 LIST_FIRST(&sc->sc_pil))); 1800 1801 if (ih == NULL) { 1802 /* intr handler is not set */ 1803 DPRINTF(("pccbb_intr_disestablish: no ih\n")); 1804 return; 1805 } 1806 1807 #ifdef DIAGNOSTIC 1808 for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1809 pil = LIST_NEXT(pil, pil_next)) { 1810 DPRINTF(("pccbb_intr_disestablish: pil %p\n", pil)); 1811 if (pil == ih) { 1812 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1813 break; 1814 } 1815 } 1816 if (pil == NULL) { 1817 panic("pccbb_intr_disestablish: %s cannot find pil %p", 1818 sc->sc_dev.dv_xname, ih); 1819 } 1820 #endif 1821 1822 pil = (struct pccbb_intrhand_list *)ih; 1823 LIST_REMOVE(pil, pil_next); 1824 free(pil, M_DEVBUF); 1825 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1826 1827 if (LIST_EMPTY(&sc->sc_pil)) { 1828 /* No interrupt handlers */ 1829 1830 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1831 1832 /* stop routing PCI intr */ 1833 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1834 reg |= CB_BCR_INTR_IREQ_ENABLE; 1835 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1836 1837 switch (sc->sc_chipset) { 1838 case CB_TI113X: 1839 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1840 /* functional intr disabled */ 1841 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1842 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1843 break; 1844 default: 1845 break; 1846 } 1847 } 1848 } 1849 1850 #if defined SHOW_REGS 1851 static void 1852 cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, bus_space_tag_t memt, 1853 bus_space_handle_t memh) 1854 { 1855 int i; 1856 printf("PCI config regs:"); 1857 for (i = 0; i < 0x50; i += 4) { 1858 if (i % 16 == 0) 1859 printf("\n 0x%02x:", i); 1860 printf(" %08x", pci_conf_read(pc, tag, i)); 1861 } 1862 for (i = 0x80; i < 0xb0; i += 4) { 1863 if (i % 16 == 0) 1864 printf("\n 0x%02x:", i); 1865 printf(" %08x", pci_conf_read(pc, tag, i)); 1866 } 1867 1868 if (memh == 0) { 1869 printf("\n"); 1870 return; 1871 } 1872 1873 printf("\nsocket regs:"); 1874 for (i = 0; i <= 0x10; i += 0x04) 1875 printf(" %08x", bus_space_read_4(memt, memh, i)); 1876 printf("\nExCA regs:"); 1877 for (i = 0; i < 0x08; ++i) 1878 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1879 printf("\n"); 1880 return; 1881 } 1882 #endif 1883 1884 /* 1885 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1886 * int busno, int function) 1887 * This is the function to make a tag to access config space of 1888 * a CardBus Card. It works same as pci_conf_read. 1889 */ 1890 static cardbustag_t 1891 pccbb_make_tag(cardbus_chipset_tag_t cc, int busno, int function) 1892 { 1893 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1894 1895 return pci_make_tag(sc->sc_pc, busno, 0, function); 1896 } 1897 1898 static void 1899 pccbb_free_tag(cardbus_chipset_tag_t cc, cardbustag_t tag) 1900 { 1901 } 1902 1903 /* 1904 * pccbb_conf_read 1905 * 1906 * This is the function to read the config space of a CardBus card. 1907 * It works the same as pci_conf_read(9). 1908 */ 1909 static cardbusreg_t 1910 pccbb_conf_read(cardbus_chipset_tag_t cc, cardbustag_t tag, int offset) 1911 { 1912 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1913 1914 return pci_conf_read(sc->sc_pc, tag, offset); 1915 } 1916 1917 /* 1918 * pccbb_conf_write 1919 * 1920 * This is the function to write the config space of a CardBus 1921 * card. It works the same as pci_conf_write(9). 1922 */ 1923 static void 1924 pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, int reg, 1925 cardbusreg_t val) 1926 { 1927 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1928 1929 pci_conf_write(sc->sc_pc, tag, reg, val); 1930 } 1931 1932 #if 0 1933 STATIC int 1934 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1935 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 1936 int speed, int flags, 1937 bus_space_handle_t * iohp) 1938 #endif 1939 /* 1940 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1941 * bus_addr_t start, bus_size_t size, 1942 * bus_size_t align, 1943 * struct pcmcia_io_handle *pcihp 1944 * 1945 * This function only allocates I/O region for pccard. This function 1946 * never maps the allocated region to pccard I/O area. 1947 * 1948 * XXX: The interface of this function is not very good, I believe. 1949 */ 1950 STATIC int 1951 pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, 1952 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 1953 { 1954 struct pcic_handle *ph = (struct pcic_handle *)pch; 1955 bus_addr_t ioaddr; 1956 int flags = 0; 1957 bus_space_tag_t iot; 1958 bus_space_handle_t ioh; 1959 bus_addr_t mask; 1960 #if rbus 1961 rbus_tag_t rb; 1962 #endif 1963 if (align == 0) { 1964 align = size; /* XXX: funny??? */ 1965 } 1966 1967 if (start != 0) { 1968 /* XXX: assume all card decode lower 10 bits by its hardware */ 1969 mask = 0x3ff; 1970 /* enforce to use only masked address */ 1971 start &= mask; 1972 } else { 1973 /* 1974 * calculate mask: 1975 * 1. get the most significant bit of size (call it msb). 1976 * 2. compare msb with the value of size. 1977 * 3. if size is larger, shift msb left once. 1978 * 4. obtain mask value to decrement msb. 1979 */ 1980 bus_size_t size_tmp = size; 1981 int shifts = 0; 1982 1983 mask = 1; 1984 while (size_tmp) { 1985 ++shifts; 1986 size_tmp >>= 1; 1987 } 1988 mask = (1 << shifts); 1989 if (mask < size) { 1990 mask <<= 1; 1991 } 1992 --mask; 1993 } 1994 1995 /* 1996 * Allocate some arbitrary I/O space. 1997 */ 1998 1999 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 2000 2001 #if rbus 2002 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 2003 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 2004 return 1; 2005 } 2006 DPRINTF(("pccbb_pcmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2007 (u_long) ioaddr, (u_long) size)); 2008 #else 2009 if (start) { 2010 ioaddr = start; 2011 if (bus_space_map(iot, start, size, 0, &ioh)) { 2012 return 1; 2013 } 2014 DPRINTF(("pccbb_pcmcia_io_alloc map port 0x%lx+0x%lx\n", 2015 (u_long) ioaddr, (u_long) size)); 2016 } else { 2017 flags |= PCMCIA_IO_ALLOCATED; 2018 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 2019 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 2020 size, align, 0, 0, &ioaddr, &ioh)) { 2021 /* No room be able to be get. */ 2022 return 1; 2023 } 2024 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2025 (u_long) ioaddr, (u_long) size)); 2026 } 2027 #endif 2028 2029 pcihp->iot = iot; 2030 pcihp->ioh = ioh; 2031 pcihp->addr = ioaddr; 2032 pcihp->size = size; 2033 pcihp->flags = flags; 2034 2035 return 0; 2036 } 2037 2038 /* 2039 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2040 * struct pcmcia_io_handle *pcihp) 2041 * 2042 * This function only frees I/O region for pccard. 2043 * 2044 * XXX: The interface of this function is not very good, I believe. 2045 */ 2046 void 2047 pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2048 struct pcmcia_io_handle *pcihp) 2049 { 2050 #if !rbus 2051 bus_space_tag_t iot = pcihp->iot; 2052 #endif 2053 bus_space_handle_t ioh = pcihp->ioh; 2054 bus_size_t size = pcihp->size; 2055 2056 #if rbus 2057 struct pccbb_softc *sc = 2058 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 2059 rbus_tag_t rb = sc->sc_rbus_iot; 2060 2061 rbus_space_free(rb, ioh, size, NULL); 2062 #else 2063 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 2064 bus_space_free(iot, ioh, size); 2065 else 2066 bus_space_unmap(iot, ioh, size); 2067 #endif 2068 } 2069 2070 /* 2071 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 2072 * bus_addr_t offset, bus_size_t size, 2073 * struct pcmcia_io_handle *pcihp, 2074 * int *windowp) 2075 * 2076 * This function maps the allocated I/O region to pccard. This function 2077 * never allocates any I/O region for pccard I/O area. I don't 2078 * understand why the original authors of pcmciabus separated alloc and 2079 * map. I believe the two must be unite. 2080 * 2081 * XXX: no wait timing control? 2082 */ 2083 int 2084 pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, bus_addr_t offset, 2085 bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp) 2086 { 2087 struct pcic_handle *ph = (struct pcic_handle *)pch; 2088 bus_addr_t ioaddr = pcihp->addr + offset; 2089 int i, win; 2090 #if defined CBB_DEBUG 2091 static const char *width_names[] = { "dynamic", "io8", "io16" }; 2092 #endif 2093 2094 /* Sanity check I/O handle. */ 2095 2096 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 2097 panic("pccbb_pcmcia_io_map iot is bogus"); 2098 } 2099 2100 /* XXX Sanity check offset/size. */ 2101 2102 win = -1; 2103 for (i = 0; i < PCIC_IO_WINS; i++) { 2104 if ((ph->ioalloc & (1 << i)) == 0) { 2105 win = i; 2106 ph->ioalloc |= (1 << i); 2107 break; 2108 } 2109 } 2110 2111 if (win == -1) { 2112 return 1; 2113 } 2114 2115 *windowp = win; 2116 2117 /* XXX this is pretty gross */ 2118 2119 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2120 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2121 2122 /* XXX wtf is this doing here? */ 2123 2124 #if 0 2125 printf(" port 0x%lx", (u_long) ioaddr); 2126 if (size > 1) { 2127 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2128 } 2129 #endif 2130 2131 ph->io[win].addr = ioaddr; 2132 ph->io[win].size = size; 2133 ph->io[win].width = width; 2134 2135 /* actual dirty register-value changing in the function below. */ 2136 pccbb_pcmcia_do_io_map(ph, win); 2137 2138 return 0; 2139 } 2140 2141 /* 2142 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2143 * 2144 * This function changes register-value to map I/O region for pccard. 2145 */ 2146 static void 2147 pccbb_pcmcia_do_io_map(struct pcic_handle *ph, int win) 2148 { 2149 static u_int8_t pcic_iowidth[3] = { 2150 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2151 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2152 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2153 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2154 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2155 }; 2156 2157 #define PCIC_SIA_START_LOW 0 2158 #define PCIC_SIA_START_HIGH 1 2159 #define PCIC_SIA_STOP_LOW 2 2160 #define PCIC_SIA_STOP_HIGH 3 2161 2162 int regbase_win = 0x8 + win * 0x04; 2163 u_int8_t ioctl, enable; 2164 2165 DPRINTF(("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx " 2166 "width %d\n", win, (unsigned long)ph->io[win].addr, 2167 (unsigned long)ph->io[win].size, ph->io[win].width * 8)); 2168 2169 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2170 ph->io[win].addr & 0xff); 2171 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2172 (ph->io[win].addr >> 8) & 0xff); 2173 2174 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2175 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2176 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2177 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2178 2179 ioctl = Pcic_read(ph, PCIC_IOCTL); 2180 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2181 switch (win) { 2182 case 0: 2183 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2184 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2185 PCIC_IOCTL_IO0_DATASIZE_MASK); 2186 ioctl |= pcic_iowidth[ph->io[win].width]; 2187 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2188 break; 2189 case 1: 2190 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2191 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2192 PCIC_IOCTL_IO1_DATASIZE_MASK); 2193 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2194 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2195 break; 2196 } 2197 Pcic_write(ph, PCIC_IOCTL, ioctl); 2198 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2199 #if defined(CBB_DEBUG) 2200 { 2201 u_int8_t start_low = 2202 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2203 u_int8_t start_high = 2204 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2205 u_int8_t stop_low = 2206 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2207 u_int8_t stop_high = 2208 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2209 printf("pccbb_pcmcia_do_io_map start %02x %02x, " 2210 "stop %02x %02x, ioctl %02x enable %02x\n", 2211 start_low, start_high, stop_low, stop_high, ioctl, enable); 2212 } 2213 #endif 2214 } 2215 2216 /* 2217 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2218 * 2219 * This function unmaps I/O region. No return value. 2220 */ 2221 STATIC void 2222 pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t pch, int win) 2223 { 2224 struct pcic_handle *ph = (struct pcic_handle *)pch; 2225 int reg; 2226 2227 if (win >= PCIC_IO_WINS || win < 0) { 2228 panic("pccbb_pcmcia_io_unmap: window out of range"); 2229 } 2230 2231 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2232 switch (win) { 2233 case 0: 2234 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2235 break; 2236 case 1: 2237 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2238 break; 2239 } 2240 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2241 2242 ph->ioalloc &= ~(1 << win); 2243 } 2244 2245 static int 2246 pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 2247 { 2248 u_int8_t stat; 2249 int i; 2250 2251 /* wait an initial 10ms for quick cards */ 2252 stat = Pcic_read(ph, PCIC_IF_STATUS); 2253 if (stat & PCIC_IF_STATUS_READY) 2254 return (0); 2255 pccbb_pcmcia_delay(ph, 10, "pccwr0"); 2256 for (i = 0; i < 50; i++) { 2257 stat = Pcic_read(ph, PCIC_IF_STATUS); 2258 if (stat & PCIC_IF_STATUS_READY) 2259 return (0); 2260 if ((stat & PCIC_IF_STATUS_CARDDETECT_MASK) != 2261 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2262 return (ENXIO); 2263 /* wait .1s (100ms) each iteration now */ 2264 pccbb_pcmcia_delay(ph, 100, "pccwr1"); 2265 } 2266 2267 printf("pccbb_pcmcia_wait_ready: ready never happened, status=%02x\n", stat); 2268 return (EWOULDBLOCK); 2269 } 2270 2271 /* 2272 * Perform long (msec order) delay. timo is in milliseconds. 2273 */ 2274 static void 2275 pccbb_pcmcia_delay(struct pcic_handle *ph, int timo, const char *wmesg) 2276 { 2277 #ifdef DIAGNOSTIC 2278 if (timo <= 0) 2279 panic("pccbb_pcmcia_delay: called with timeout %d", timo); 2280 if (!curlwp) 2281 panic("pccbb_pcmcia_delay: called in interrupt context"); 2282 #if 0 2283 if (!ph->event_thread) 2284 panic("pccbb_pcmcia_delay: no event thread"); 2285 #endif 2286 #endif 2287 DPRINTF(("pccbb_pcmcia_delay: \"%s\" %p, sleep %d ms\n", 2288 wmesg, ph->event_thread, timo)); 2289 tsleep(pccbb_pcmcia_delay, PWAIT, wmesg, roundup(timo * hz, 1000) / 1000); 2290 } 2291 2292 /* 2293 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2294 * 2295 * This function enables the card. All information is stored in 2296 * the first argument, pcmcia_chipset_handle_t. 2297 */ 2298 STATIC void 2299 pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2300 { 2301 struct pcic_handle *ph = (struct pcic_handle *)pch; 2302 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2303 pcireg_t spsr; 2304 int voltage; 2305 int win; 2306 u_int8_t power, intr; 2307 #ifdef DIAGNOSTIC 2308 int reg; 2309 #endif 2310 2311 /* this bit is mostly stolen from pcic_attach_card */ 2312 2313 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2314 2315 /* get card Vcc info */ 2316 spsr = 2317 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2318 CB_SOCKET_STAT); 2319 if (spsr & CB_SOCKET_STAT_5VCARD) { 2320 DPRINTF(("5V card\n")); 2321 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2322 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2323 DPRINTF(("3V card\n")); 2324 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2325 } else { 2326 DPRINTF(("?V card, 0x%x\n", spsr)); /* XXX */ 2327 return; 2328 } 2329 2330 /* disable interrupts; assert RESET */ 2331 intr = Pcic_read(ph, PCIC_INTR); 2332 intr &= PCIC_INTR_ENABLE; 2333 Pcic_write(ph, PCIC_INTR, intr); 2334 2335 /* zero out the address windows */ 2336 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2337 2338 /* power down the socket to reset it, clear the card reset pin */ 2339 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2340 2341 /* power off; assert output enable bit */ 2342 power = PCIC_PWRCTL_OE; 2343 Pcic_write(ph, PCIC_PWRCTL, power); 2344 2345 /* power up the socket */ 2346 if (pccbb_power(sc, voltage) == 0) 2347 return; 2348 2349 /* 2350 * Table 4-18 and figure 4-6 of the PC Card specifiction say: 2351 * Vcc Rising Time (Tpr) = 100ms (handled in pccbb_power() above) 2352 * RESET Width (Th (Hi-z RESET)) = 1ms 2353 * RESET Width (Tw (RESET)) = 10us 2354 * 2355 * some machines require some more time to be settled 2356 * for example old toshiba topic bridges! 2357 * (100ms is added here). 2358 */ 2359 pccbb_pcmcia_delay(ph, 200 + 1, "pccen1"); 2360 2361 /* negate RESET */ 2362 intr |= PCIC_INTR_RESET; 2363 Pcic_write(ph, PCIC_INTR, intr); 2364 2365 /* 2366 * RESET Setup Time (Tsu (RESET)) = 20ms 2367 */ 2368 pccbb_pcmcia_delay(ph, 20, "pccen2"); 2369 2370 #ifdef DIAGNOSTIC 2371 reg = Pcic_read(ph, PCIC_IF_STATUS); 2372 if ((reg & PCIC_IF_STATUS_POWERACTIVE) == 0) 2373 printf("pccbb_pcmcia_socket_enable: no power, status=%x\n", reg); 2374 #endif 2375 2376 /* wait for the chip to finish initializing */ 2377 if (pccbb_pcmcia_wait_ready(ph)) { 2378 #ifdef DIAGNOSTIC 2379 printf("pccbb_pcmcia_socket_enable: never became ready\n"); 2380 #endif 2381 /* XXX return a failure status?? */ 2382 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2383 Pcic_write(ph, PCIC_PWRCTL, 0); 2384 return; 2385 } 2386 2387 /* reinstall all the memory and io mappings */ 2388 for (win = 0; win < PCIC_MEM_WINS; ++win) 2389 if (ph->memalloc & (1 << win)) 2390 pccbb_pcmcia_do_mem_map(ph, win); 2391 for (win = 0; win < PCIC_IO_WINS; ++win) 2392 if (ph->ioalloc & (1 << win)) 2393 pccbb_pcmcia_do_io_map(ph, win); 2394 } 2395 2396 /* 2397 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2398 * 2399 * This function disables the card. All information is stored in 2400 * the first argument, pcmcia_chipset_handle_t. 2401 */ 2402 STATIC void 2403 pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t pch) 2404 { 2405 struct pcic_handle *ph = (struct pcic_handle *)pch; 2406 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2407 u_int8_t intr; 2408 2409 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2410 2411 /* disable interrupts; assert RESET */ 2412 intr = Pcic_read(ph, PCIC_INTR); 2413 intr &= PCIC_INTR_ENABLE; 2414 Pcic_write(ph, PCIC_INTR, intr); 2415 2416 /* zero out the address windows */ 2417 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2418 2419 /* power down the socket to reset it, clear the card reset pin */ 2420 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2421 2422 /* disable socket: negate output enable bit and power off */ 2423 Pcic_write(ph, PCIC_PWRCTL, 0); 2424 2425 /* 2426 * Vcc Falling Time (Tpf) = 300ms 2427 */ 2428 pccbb_pcmcia_delay(ph, 300, "pccwr1"); 2429 } 2430 2431 STATIC void 2432 pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t pch, int type) 2433 { 2434 struct pcic_handle *ph = (struct pcic_handle *)pch; 2435 u_int8_t intr; 2436 2437 /* set the card type */ 2438 2439 intr = Pcic_read(ph, PCIC_INTR); 2440 intr &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_CARDTYPE_MASK); 2441 if (type == PCMCIA_IFTYPE_IO) 2442 intr |= PCIC_INTR_CARDTYPE_IO; 2443 else 2444 intr |= PCIC_INTR_CARDTYPE_MEM; 2445 Pcic_write(ph, PCIC_INTR, intr); 2446 2447 DPRINTF(("%s: pccbb_pcmcia_socket_settype %02x type %s %02x\n", 2448 ph->ph_parent->dv_xname, ph->sock, 2449 ((type == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2450 } 2451 2452 /* 2453 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2454 * 2455 * This function detects whether a card is in the slot or not. 2456 * If a card is inserted, return 1. Otherwise, return 0. 2457 */ 2458 STATIC int 2459 pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch) 2460 { 2461 struct pcic_handle *ph = (struct pcic_handle *)pch; 2462 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2463 2464 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2465 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2466 } 2467 2468 #if 0 2469 STATIC int 2470 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2471 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2472 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2473 #endif 2474 /* 2475 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2476 * bus_size_t size, 2477 * struct pcmcia_mem_handle *pcmhp) 2478 * 2479 * This function only allocates memory region for pccard. This 2480 * function never maps the allocated region to pccard memory area. 2481 * 2482 * XXX: Why the argument of start address is not in? 2483 */ 2484 STATIC int 2485 pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 2486 struct pcmcia_mem_handle *pcmhp) 2487 { 2488 struct pcic_handle *ph = (struct pcic_handle *)pch; 2489 bus_space_handle_t memh; 2490 bus_addr_t addr; 2491 bus_size_t sizepg; 2492 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2493 #if rbus 2494 rbus_tag_t rb; 2495 #endif 2496 2497 /* Check that the card is still there. */ 2498 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2499 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2500 return 1; 2501 2502 /* out of sc->memh, allocate as many pages as necessary */ 2503 2504 /* convert size to PCIC pages */ 2505 /* 2506 * This is not enough; when the requested region is on the page 2507 * boundaries, this may calculate wrong result. 2508 */ 2509 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2510 #if 0 2511 if (sizepg > PCIC_MAX_MEM_PAGES) { 2512 return 1; 2513 } 2514 #endif 2515 2516 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2517 return 1; 2518 } 2519 2520 addr = 0; /* XXX gcc -Wuninitialized */ 2521 2522 #if rbus 2523 rb = sc->sc_rbus_memt; 2524 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2525 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2526 &addr, &memh)) { 2527 return 1; 2528 } 2529 #else 2530 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2531 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2532 0, /* boundary */ 2533 0, /* flags */ 2534 &addr, &memh)) { 2535 return 1; 2536 } 2537 #endif 2538 2539 DPRINTF(("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, " 2540 "realsize 0x%lx\n", (unsigned long)addr, (unsigned long)size, 2541 (unsigned long)sizepg * PCIC_MEM_PAGESIZE)); 2542 2543 pcmhp->memt = sc->sc_memt; 2544 pcmhp->memh = memh; 2545 pcmhp->addr = addr; 2546 pcmhp->size = size; 2547 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2548 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2549 pcmhp->mhandle = 0; 2550 /* No offset??? Funny. */ 2551 2552 return 0; 2553 } 2554 2555 /* 2556 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2557 * struct pcmcia_mem_handle *pcmhp) 2558 * 2559 * This function release the memory space allocated by the function 2560 * pccbb_pcmcia_mem_alloc(). 2561 */ 2562 STATIC void 2563 pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2564 struct pcmcia_mem_handle *pcmhp) 2565 { 2566 #if rbus 2567 struct pcic_handle *ph = (struct pcic_handle *)pch; 2568 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2569 2570 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2571 #else 2572 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2573 #endif 2574 } 2575 2576 /* 2577 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2578 * 2579 * This function release the memory space allocated by the function 2580 * pccbb_pcmcia_mem_alloc(). 2581 */ 2582 STATIC void 2583 pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2584 { 2585 int regbase_win; 2586 bus_addr_t phys_addr; 2587 bus_addr_t phys_end; 2588 2589 #define PCIC_SMM_START_LOW 0 2590 #define PCIC_SMM_START_HIGH 1 2591 #define PCIC_SMM_STOP_LOW 2 2592 #define PCIC_SMM_STOP_HIGH 3 2593 #define PCIC_CMA_LOW 4 2594 #define PCIC_CMA_HIGH 5 2595 2596 u_int8_t start_low, start_high = 0; 2597 u_int8_t stop_low, stop_high; 2598 u_int8_t off_low, off_high; 2599 u_int8_t mem_window; 2600 int reg; 2601 2602 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2603 int mem8 = 2604 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2605 || (kind == PCMCIA_MEM_ATTR); 2606 2607 regbase_win = 0x10 + win * 0x08; 2608 2609 phys_addr = ph->mem[win].addr; 2610 phys_end = phys_addr + ph->mem[win].size; 2611 2612 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2613 (unsigned long)phys_addr, (unsigned long)phys_end, 2614 (unsigned long)ph->mem[win].offset)); 2615 2616 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2617 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2618 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2619 2620 /* bit 19:12 */ 2621 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2622 /* bit 23:20 and bit 7 on */ 2623 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2624 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2625 /* bit 31:24, for 32-bit address */ 2626 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2627 2628 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2629 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2630 2631 if (((struct pccbb_softc *)ph-> 2632 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2633 Pcic_write(ph, 0x40 + win, mem_window); 2634 } 2635 2636 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2637 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2638 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2639 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2640 2641 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2642 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2643 2644 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2645 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2646 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2647 | ((kind == PCMCIA_MEM_ATTR) ? 2648 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2649 2650 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2651 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2652 2653 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2654 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2655 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2656 2657 #if defined(CBB_DEBUG) 2658 { 2659 int r1, r2, r3, r4, r5, r6, r7 = 0; 2660 2661 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2662 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2663 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2664 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2665 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2666 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2667 if (((struct pccbb_softc *)(ph-> 2668 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2669 r7 = Pcic_read(ph, 0x40 + win); 2670 } 2671 2672 printf("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2673 "%02x%02x", win, r1, r2, r3, r4, r5, r6); 2674 if (((struct pccbb_softc *)(ph-> 2675 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2676 printf(" %02x", r7); 2677 } 2678 printf("\n"); 2679 } 2680 #endif 2681 } 2682 2683 /* 2684 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2685 * bus_addr_t card_addr, bus_size_t size, 2686 * struct pcmcia_mem_handle *pcmhp, 2687 * bus_addr_t *offsetp, int *windowp) 2688 * 2689 * This function maps memory space allocated by the function 2690 * pccbb_pcmcia_mem_alloc(). 2691 */ 2692 STATIC int 2693 pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2694 bus_addr_t card_addr, bus_size_t size, struct pcmcia_mem_handle *pcmhp, 2695 bus_addr_t *offsetp, int *windowp) 2696 { 2697 struct pcic_handle *ph = (struct pcic_handle *)pch; 2698 bus_addr_t busaddr; 2699 long card_offset; 2700 int win; 2701 2702 /* Check that the card is still there. */ 2703 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2704 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2705 return 1; 2706 2707 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2708 if ((ph->memalloc & (1 << win)) == 0) { 2709 ph->memalloc |= (1 << win); 2710 break; 2711 } 2712 } 2713 2714 if (win == PCIC_MEM_WINS) { 2715 return 1; 2716 } 2717 2718 *windowp = win; 2719 2720 /* XXX this is pretty gross */ 2721 2722 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2723 panic("pccbb_pcmcia_mem_map memt is bogus"); 2724 } 2725 2726 busaddr = pcmhp->addr; 2727 2728 /* 2729 * compute the address offset to the pcmcia address space for the 2730 * pcic. this is intentionally signed. The masks and shifts below 2731 * will cause TRT to happen in the pcic registers. Deal with making 2732 * sure the address is aligned, and return the alignment offset. 2733 */ 2734 2735 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2736 card_addr -= *offsetp; 2737 2738 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2739 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2740 (u_long) card_addr)); 2741 2742 /* 2743 * include the offset in the size, and decrement size by one, since 2744 * the hw wants start/stop 2745 */ 2746 size += *offsetp - 1; 2747 2748 card_offset = (((long)card_addr) - ((long)busaddr)); 2749 2750 ph->mem[win].addr = busaddr; 2751 ph->mem[win].size = size; 2752 ph->mem[win].offset = card_offset; 2753 ph->mem[win].kind = kind; 2754 2755 pccbb_pcmcia_do_mem_map(ph, win); 2756 2757 return 0; 2758 } 2759 2760 /* 2761 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2762 * int window) 2763 * 2764 * This function unmaps memory space which mapped by the function 2765 * pccbb_pcmcia_mem_map(). 2766 */ 2767 STATIC void 2768 pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, int window) 2769 { 2770 struct pcic_handle *ph = (struct pcic_handle *)pch; 2771 int reg; 2772 2773 if (window >= PCIC_MEM_WINS) { 2774 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2775 } 2776 2777 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2778 reg &= ~(1 << window); 2779 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2780 2781 ph->memalloc &= ~(1 << window); 2782 } 2783 2784 #if defined PCCBB_PCMCIA_POLL 2785 struct pccbb_poll_str { 2786 void *arg; 2787 int (*func)(void *); 2788 int level; 2789 struct pcic_handle *ph; 2790 int count; 2791 int num; 2792 struct callout poll_ch; 2793 }; 2794 2795 static struct pccbb_poll_str pccbb_poll[10]; 2796 static int pccbb_poll_n = 0; 2797 2798 static void pccbb_pcmcia_poll(void *arg); 2799 2800 static void 2801 pccbb_pcmcia_poll(void *arg) 2802 { 2803 struct pccbb_poll_str *poll = arg; 2804 struct pcic_handle *ph = poll->ph; 2805 struct pccbb_softc *sc = ph->sc; 2806 int s; 2807 u_int32_t spsr; /* socket present-state reg */ 2808 2809 callout_reset(&poll->poll_ch, hz * 2, pccbb_pcmcia_poll, arg); 2810 switch (poll->level) { 2811 case IPL_NET: 2812 s = splnet(); 2813 break; 2814 case IPL_BIO: 2815 s = splbio(); 2816 break; 2817 case IPL_TTY: /* fallthrough */ 2818 default: 2819 s = spltty(); 2820 break; 2821 } 2822 2823 spsr = 2824 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2825 CB_SOCKET_STAT); 2826 2827 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2828 if (!(spsr & 0x40)) /* CINT low */ 2829 #else 2830 if (1) 2831 #endif 2832 { 2833 if ((*poll->func) (poll->arg) > 0) { 2834 ++poll->count; 2835 /* printf("intr: reported from poller, 0x%x\n", spsr); */ 2836 #if defined LEVEL2 2837 } else { 2838 printf("intr: miss! 0x%x\n", spsr); 2839 #endif 2840 } 2841 } 2842 splx(s); 2843 } 2844 #endif /* defined CB_PCMCIA_POLL */ 2845 2846 /* 2847 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2848 * struct pcmcia_function *pf, 2849 * int ipl, 2850 * int (*func)(void *), 2851 * void *arg); 2852 * 2853 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2854 */ 2855 STATIC void * 2856 pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2857 struct pcmcia_function *pf, int ipl, int (*func)(void *), void *arg) 2858 { 2859 struct pcic_handle *ph = (struct pcic_handle *)pch; 2860 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2861 2862 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2863 /* what should I do? */ 2864 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2865 DPRINTF(("%s does not provide edge nor pulse " 2866 "interrupt\n", sc->sc_dev.dv_xname)); 2867 return NULL; 2868 } 2869 /* 2870 * XXX Noooooo! The interrupt flag must set properly!! 2871 * dumb pcmcia driver!! 2872 */ 2873 } 2874 2875 return pccbb_intr_establish(sc, 0, ipl, func, arg); 2876 } 2877 2878 /* 2879 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2880 * void *ih) 2881 * 2882 * This function disables PC-Card interrupt. 2883 */ 2884 STATIC void 2885 pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 2886 { 2887 struct pcic_handle *ph = (struct pcic_handle *)pch; 2888 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2889 2890 pccbb_intr_disestablish(sc, ih); 2891 } 2892 2893 #if rbus 2894 /* 2895 * static int 2896 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2897 * bus_addr_t addr, bus_size_t size, 2898 * bus_addr_t mask, bus_size_t align, 2899 * int flags, bus_addr_t *addrp; 2900 * bus_space_handle_t *bshp) 2901 * 2902 * This function allocates a portion of memory or io space for 2903 * clients. This function is called from CardBus card drivers. 2904 */ 2905 static int 2906 pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2907 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 2908 int flags, bus_addr_t *addrp, bus_space_handle_t *bshp) 2909 { 2910 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2911 2912 DPRINTF(("pccbb_rbus_cb_space_alloc: addr 0x%lx, size 0x%lx, " 2913 "mask 0x%lx, align 0x%lx\n", (unsigned long)addr, 2914 (unsigned long)size, (unsigned long)mask, (unsigned long)align)); 2915 2916 if (align == 0) { 2917 align = size; 2918 } 2919 2920 if (rb->rb_bt == sc->sc_memt) { 2921 if (align < 16) { 2922 return 1; 2923 } 2924 /* 2925 * XXX: align more than 0x1000 to avoid overwrapping 2926 * memory windows for two or more devices. 0x1000 2927 * means memory window's granularity. 2928 * 2929 * Two or more devices should be able to share same 2930 * memory window region. However, overrapping memory 2931 * window is not good because some devices, such as 2932 * 3Com 3C575[BC], have a broken address decoder and 2933 * intrude other's memory region. 2934 */ 2935 if (align < 0x1000) { 2936 align = 0x1000; 2937 } 2938 } else if (rb->rb_bt == sc->sc_iot) { 2939 if (align < 4) { 2940 return 1; 2941 } 2942 /* XXX: hack for avoiding ISA image */ 2943 if (mask < 0x0100) { 2944 mask = 0x3ff; 2945 addr = 0x300; 2946 } 2947 2948 } else { 2949 DPRINTF(("pccbb_rbus_cb_space_alloc: Bus space tag 0x%lx is " 2950 "NOT used. io: 0x%lx, mem: 0x%lx\n", 2951 (unsigned long)rb->rb_bt, (unsigned long)sc->sc_iot, 2952 (unsigned long)sc->sc_memt)); 2953 return 1; 2954 /* XXX: panic here? */ 2955 } 2956 2957 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 2958 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 2959 return 1; 2960 } 2961 2962 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 2963 2964 return 0; 2965 } 2966 2967 /* 2968 * static int 2969 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 2970 * bus_space_handle_t *bshp, bus_size_t size); 2971 * 2972 * This function is called from CardBus card drivers. 2973 */ 2974 static int 2975 pccbb_rbus_cb_space_free(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2976 bus_space_handle_t bsh, bus_size_t size) 2977 { 2978 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2979 bus_space_tag_t bt = rb->rb_bt; 2980 2981 pccbb_close_win(sc, bt, bsh, size); 2982 2983 if (bt == sc->sc_memt) { 2984 } else if (bt == sc->sc_iot) { 2985 } else { 2986 return 1; 2987 /* XXX: panic here? */ 2988 } 2989 2990 return rbus_space_free(rb, bsh, size, NULL); 2991 } 2992 #endif /* rbus */ 2993 2994 #if rbus 2995 2996 static int 2997 pccbb_open_win(struct pccbb_softc *sc, bus_space_tag_t bst, bus_addr_t addr, 2998 bus_size_t size, bus_space_handle_t bsh, int flags) 2999 { 3000 struct pccbb_win_chain_head *head; 3001 bus_addr_t align; 3002 3003 head = &sc->sc_iowindow; 3004 align = 0x04; 3005 if (sc->sc_memt == bst) { 3006 head = &sc->sc_memwindow; 3007 align = 0x1000; 3008 DPRINTF(("using memory window, 0x%lx 0x%lx 0x%lx\n\n", 3009 (unsigned long)sc->sc_iot, (unsigned long)sc->sc_memt, 3010 (unsigned long)bst)); 3011 } 3012 3013 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 3014 printf("%s: pccbb_open_win: %s winlist insert failed\n", 3015 sc->sc_dev.dv_xname, 3016 (head == &sc->sc_memwindow) ? "mem" : "io"); 3017 } 3018 pccbb_winset(align, sc, bst); 3019 3020 return 0; 3021 } 3022 3023 static int 3024 pccbb_close_win(struct pccbb_softc *sc, bus_space_tag_t bst, 3025 bus_space_handle_t bsh, bus_size_t size) 3026 { 3027 struct pccbb_win_chain_head *head; 3028 bus_addr_t align; 3029 3030 head = &sc->sc_iowindow; 3031 align = 0x04; 3032 if (sc->sc_memt == bst) { 3033 head = &sc->sc_memwindow; 3034 align = 0x1000; 3035 } 3036 3037 if (pccbb_winlist_delete(head, bsh, size)) { 3038 printf("%s: pccbb_close_win: %s winlist delete failed\n", 3039 sc->sc_dev.dv_xname, 3040 (head == &sc->sc_memwindow) ? "mem" : "io"); 3041 } 3042 pccbb_winset(align, sc, bst); 3043 3044 return 0; 3045 } 3046 3047 static int 3048 pccbb_winlist_insert(struct pccbb_win_chain_head *head, bus_addr_t start, 3049 bus_size_t size, bus_space_handle_t bsh, int flags) 3050 { 3051 struct pccbb_win_chain *chainp, *elem; 3052 3053 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 3054 M_NOWAIT)) == NULL) 3055 return (1); /* fail */ 3056 3057 elem->wc_start = start; 3058 elem->wc_end = start + (size - 1); 3059 elem->wc_handle = bsh; 3060 elem->wc_flags = flags; 3061 3062 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3063 chainp = TAILQ_NEXT(chainp, wc_list)) { 3064 if (chainp->wc_end < start) 3065 continue; 3066 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 3067 return (0); 3068 } 3069 3070 TAILQ_INSERT_TAIL(head, elem, wc_list); 3071 return (0); 3072 } 3073 3074 static int 3075 pccbb_winlist_delete(struct pccbb_win_chain_head *head, bus_space_handle_t bsh, 3076 bus_size_t size) 3077 { 3078 struct pccbb_win_chain *chainp; 3079 3080 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3081 chainp = TAILQ_NEXT(chainp, wc_list)) { 3082 if (memcmp(&chainp->wc_handle, &bsh, sizeof(bsh))) 3083 continue; 3084 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 3085 printf("pccbb_winlist_delete: window 0x%lx size " 3086 "inconsistent: 0x%lx, 0x%lx\n", 3087 (unsigned long)chainp->wc_start, 3088 (unsigned long)(chainp->wc_end - chainp->wc_start), 3089 (unsigned long)(size - 1)); 3090 return 1; 3091 } 3092 3093 TAILQ_REMOVE(head, chainp, wc_list); 3094 free(chainp, M_DEVBUF); 3095 3096 return 0; 3097 } 3098 3099 return 1; /* fail: no candidate to remove */ 3100 } 3101 3102 static void 3103 pccbb_winset(bus_addr_t align, struct pccbb_softc *sc, bus_space_tag_t bst) 3104 { 3105 pci_chipset_tag_t pc; 3106 pcitag_t tag; 3107 bus_addr_t mask = ~(align - 1); 3108 struct { 3109 cardbusreg_t win_start; 3110 cardbusreg_t win_limit; 3111 int win_flags; 3112 } win[2]; 3113 struct pccbb_win_chain *chainp; 3114 int offs; 3115 3116 win[0].win_start = win[1].win_start = 0xffffffff; 3117 win[0].win_limit = win[1].win_limit = 0; 3118 win[0].win_flags = win[1].win_flags = 0; 3119 3120 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3121 offs = 0x2c; 3122 if (sc->sc_memt == bst) { 3123 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3124 offs = 0x1c; 3125 } 3126 3127 if (chainp != NULL) { 3128 win[0].win_start = chainp->wc_start & mask; 3129 win[0].win_limit = chainp->wc_end & mask; 3130 win[0].win_flags = chainp->wc_flags; 3131 chainp = TAILQ_NEXT(chainp, wc_list); 3132 } 3133 3134 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3135 if (win[1].win_start == 0xffffffff) { 3136 /* window 1 is not used */ 3137 if ((win[0].win_flags == chainp->wc_flags) && 3138 (win[0].win_limit + align >= 3139 (chainp->wc_start & mask))) { 3140 /* concatenate */ 3141 win[0].win_limit = chainp->wc_end & mask; 3142 } else { 3143 /* make new window */ 3144 win[1].win_start = chainp->wc_start & mask; 3145 win[1].win_limit = chainp->wc_end & mask; 3146 win[1].win_flags = chainp->wc_flags; 3147 } 3148 continue; 3149 } 3150 3151 /* Both windows are engaged. */ 3152 if (win[0].win_flags == win[1].win_flags) { 3153 /* same flags */ 3154 if (win[0].win_flags == chainp->wc_flags) { 3155 if (win[1].win_start - (win[0].win_limit + 3156 align) < 3157 (chainp->wc_start & mask) - 3158 ((chainp->wc_end & mask) + align)) { 3159 /* 3160 * merge window 0 and 1, and set win1 3161 * to chainp 3162 */ 3163 win[0].win_limit = win[1].win_limit; 3164 win[1].win_start = 3165 chainp->wc_start & mask; 3166 win[1].win_limit = 3167 chainp->wc_end & mask; 3168 } else { 3169 win[1].win_limit = 3170 chainp->wc_end & mask; 3171 } 3172 } else { 3173 /* different flags */ 3174 3175 /* concatenate win0 and win1 */ 3176 win[0].win_limit = win[1].win_limit; 3177 /* allocate win[1] to new space */ 3178 win[1].win_start = chainp->wc_start & mask; 3179 win[1].win_limit = chainp->wc_end & mask; 3180 win[1].win_flags = chainp->wc_flags; 3181 } 3182 } else { 3183 /* the flags of win[0] and win[1] is different */ 3184 if (win[0].win_flags == chainp->wc_flags) { 3185 win[0].win_limit = chainp->wc_end & mask; 3186 /* 3187 * XXX this creates overlapping windows, so 3188 * what should the poor bridge do if one is 3189 * cachable, and the other is not? 3190 */ 3191 printf("%s: overlapping windows\n", 3192 sc->sc_dev.dv_xname); 3193 } else { 3194 win[1].win_limit = chainp->wc_end & mask; 3195 } 3196 } 3197 } 3198 3199 pc = sc->sc_pc; 3200 tag = sc->sc_tag; 3201 pci_conf_write(pc, tag, offs, win[0].win_start); 3202 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3203 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3204 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3205 DPRINTF(("--pccbb_winset: win0 [0x%lx, 0x%lx), win1 [0x%lx, 0x%lx)\n", 3206 (unsigned long)pci_conf_read(pc, tag, offs), 3207 (unsigned long)pci_conf_read(pc, tag, offs + 4) + align, 3208 (unsigned long)pci_conf_read(pc, tag, offs + 8), 3209 (unsigned long)pci_conf_read(pc, tag, offs + 12) + align)); 3210 3211 if (bst == sc->sc_memt) { 3212 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3213 3214 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 3215 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 3216 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3217 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 3218 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3219 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3220 } 3221 } 3222 3223 #endif /* rbus */ 3224 3225 static void 3226 pccbb_powerhook(int why, void *arg) 3227 { 3228 struct pccbb_softc *sc = arg; 3229 pcireg_t reg; 3230 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3231 bus_space_handle_t base_memh = sc->sc_base_memh; 3232 3233 DPRINTF(("%s: power: why %d\n", sc->sc_dev.dv_xname, why)); 3234 3235 if (why == PWR_SUSPEND || why == PWR_STANDBY) { 3236 DPRINTF(("%s: power: why %d stopping intr\n", 3237 sc->sc_dev.dv_xname, why)); 3238 if (sc->sc_pil_intr_enable) { 3239 (void)pccbbintr_function(sc); 3240 } 3241 sc->sc_pil_intr_enable = 0; 3242 3243 pci_conf_capture(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf); 3244 3245 if (sc->sc_chipset == CB_RX5C47X) 3246 sc->sc_ricoh_misc_ctrl = pci_conf_read(sc->sc_pc, 3247 sc->sc_tag, 3248 RICOH_PCI_MISC_CTRL); 3249 3250 /* ToDo: deactivate or suspend child devices */ 3251 } 3252 3253 if (why == PWR_RESUME) { 3254 if (sc->sc_pwrmgt_offs != 0) { 3255 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, 3256 sc->sc_pwrmgt_offs + PCI_PMCSR); 3257 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 3258 reg & PCI_PMCSR_PME_EN) { 3259 /* powrstate != D0 */ 3260 3261 printf("%s going back to D0 mode\n", 3262 sc->sc_dev.dv_xname); 3263 reg &= ~PCI_PMCSR_STATE_MASK; 3264 reg |= PCI_PMCSR_STATE_D0; 3265 reg &= ~PCI_PMCSR_PME_EN; 3266 pci_conf_write(sc->sc_pc, sc->sc_tag, 3267 sc->sc_pwrmgt_offs + PCI_PMCSR, reg); 3268 3269 pci_conf_write(sc->sc_pc, sc->sc_tag, 3270 PCI_SOCKBASE, sc->sc_sockbase); 3271 pci_conf_write(sc->sc_pc, sc->sc_tag, 3272 PCI_BUSNUM, sc->sc_busnum); 3273 pccbb_chipinit(sc); 3274 /* setup memory and io space window for CB */ 3275 pccbb_winset(0x1000, sc, sc->sc_memt); 3276 pccbb_winset(0x04, sc, sc->sc_iot); 3277 goto norestore; 3278 } 3279 } 3280 3281 norestore: 3282 pci_conf_restore(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf); 3283 if (sc->sc_chipset == CB_RX5C47X) { 3284 pci_conf_write(sc->sc_pc, sc->sc_tag, 3285 RICOH_PCI_MISC_CTRL, sc->sc_ricoh_misc_ctrl); 3286 } 3287 3288 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_SOCKBASE) == 0) 3289 /* BIOS did not recover this register */ 3290 pci_conf_write (sc->sc_pc, sc->sc_tag, 3291 PCI_SOCKBASE, sc->sc_sockbase); 3292 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_BUSNUM) == 0) 3293 /* BIOS did not recover this register */ 3294 pci_conf_write (sc->sc_pc, sc->sc_tag, 3295 PCI_BUSNUM, sc->sc_busnum); 3296 /* CSC Interrupt: Card detect interrupt on */ 3297 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3298 /* Card detect intr is turned on. */ 3299 reg |= CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; 3300 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3301 /* reset interrupt */ 3302 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3303 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3304 3305 /* 3306 * check for card insertion or removal during suspend period. 3307 * XXX: the code can't cope with card swap (remove then 3308 * insert). how can we detect such situation? 3309 */ 3310 (void)pccbbintr(sc); 3311 3312 sc->sc_pil_intr_enable = 1; 3313 DPRINTF(("%s: power: RESUME enabling intr\n", 3314 sc->sc_dev.dv_xname)); 3315 3316 /* ToDo: activate or wakeup child devices */ 3317 } 3318 } 3319
Indexes created Fri Sep 26 08:10:20 GMT 2025