pccbb.c revision 1.144
1 /* $NetBSD: pccbb.c,v 1.144 2007/02/04 21:04:37 dyoung Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: pccbb.c,v 1.144 2007/02/04 21:04:37 dyoung Exp $"); 35 36 /* 37 #define CBB_DEBUG 38 #define SHOW_REGS 39 */ 40 41 /* 42 * BROKEN! 43 #define PCCBB_PCMCIA_POLL 44 #define CB_PCMCIA_POLL 45 #define CB_PCMCIA_POLL_ONLY 46 #define LEVEL2 47 */ 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/kernel.h> 52 #include <sys/errno.h> 53 #include <sys/ioctl.h> 54 #include <sys/reboot.h> /* for bootverbose */ 55 #include <sys/syslog.h> 56 #include <sys/device.h> 57 #include <sys/malloc.h> 58 #include <sys/proc.h> 59 60 #include <machine/intr.h> 61 #include <machine/bus.h> 62 63 #include <dev/pci/pcivar.h> 64 #include <dev/pci/pcireg.h> 65 #include <dev/pci/pcidevs.h> 66 67 #include <dev/pci/pccbbreg.h> 68 69 #include <dev/cardbus/cardslotvar.h> 70 71 #include <dev/cardbus/cardbusvar.h> 72 73 #include <dev/pcmcia/pcmciareg.h> 74 #include <dev/pcmcia/pcmciavar.h> 75 76 #include <dev/ic/i82365reg.h> 77 #include <dev/ic/i82365var.h> 78 #include <dev/pci/pccbbvar.h> 79 80 #include "locators.h" 81 82 #if defined(__i386__) 83 #include "ioapic.h" 84 #include "acpi.h" 85 #endif 86 87 #ifndef __NetBSD_Version__ 88 struct cfdriver cbb_cd = { 89 NULL, "cbb", DV_DULL 90 }; 91 #endif 92 93 #ifdef CBB_DEBUG 94 #define DPRINTF(x) printf x 95 #define STATIC 96 #else 97 #define DPRINTF(x) 98 #define STATIC static 99 #endif 100 101 /* 102 * delay_ms() is wait in milliseconds. It should be used instead 103 * of delay() if you want to wait more than 1 ms. 104 */ 105 static inline void 106 delay_ms(int millis, void *param) 107 { 108 if (cold) 109 delay(millis * 1000); 110 else 111 tsleep(param, PWAIT, "pccbb", MAX(2, hz * millis / 1000)); 112 } 113 114 int pcicbbmatch(struct device *, struct cfdata *, void *); 115 void pccbbattach(struct device *, struct device *, void *); 116 int pccbbintr(void *); 117 static void pci113x_insert(void *); 118 static int pccbbintr_function(struct pccbb_softc *); 119 120 static int pccbb_detect_card(struct pccbb_softc *); 121 122 static void pccbb_pcmcia_write(struct pcic_handle *, int, u_int8_t); 123 static u_int8_t pccbb_pcmcia_read(struct pcic_handle *, int); 124 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 125 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 126 127 STATIC int cb_reset(struct pccbb_softc *); 128 STATIC int cb_detect_voltage(struct pccbb_softc *); 129 STATIC int cbbprint(void *, const char *); 130 131 static int cb_chipset(u_int32_t, int *); 132 STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *, 133 struct pcmciabus_attach_args *); 134 #if 0 135 STATIC void pccbb_pcmcia_attach_card(struct pcic_handle *); 136 STATIC void pccbb_pcmcia_detach_card(struct pcic_handle *, int); 137 STATIC void pccbb_pcmcia_deactivate_card(struct pcic_handle *); 138 #endif 139 140 STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int); 141 STATIC int pccbb_power(cardbus_chipset_tag_t, int); 142 STATIC int pccbb_cardenable(struct pccbb_softc * sc, int function); 143 #if !rbus 144 static int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 145 static int pccbb_io_close(cardbus_chipset_tag_t, int); 146 static int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 147 static int pccbb_mem_close(cardbus_chipset_tag_t, int); 148 #endif /* !rbus */ 149 static void *pccbb_intr_establish(struct pccbb_softc *, int irq, 150 int level, int (*ih) (void *), void *sc); 151 static void pccbb_intr_disestablish(struct pccbb_softc *, void *ih); 152 153 static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t, int irq, 154 int level, int (*ih) (void *), void *sc); 155 static void pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih); 156 157 static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t, int, int); 158 static void pccbb_free_tag(cardbus_chipset_tag_t, cardbustag_t); 159 static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t, cardbustag_t, int); 160 static void pccbb_conf_write(cardbus_chipset_tag_t, cardbustag_t, int, 161 cardbusreg_t); 162 static void pccbb_chipinit(struct pccbb_softc *); 163 164 STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 165 struct pcmcia_mem_handle *); 166 STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t, 167 struct pcmcia_mem_handle *); 168 STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 169 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *); 170 STATIC void pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t, int); 171 STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 172 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 173 STATIC void pccbb_pcmcia_io_free(pcmcia_chipset_handle_t, 174 struct pcmcia_io_handle *); 175 STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 176 bus_size_t, struct pcmcia_io_handle *, int *); 177 STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t, int); 178 STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t, 179 struct pcmcia_function *, int, int (*)(void *), void *); 180 STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t, void *); 181 STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t); 182 STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t); 183 STATIC void pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t, int); 184 STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch); 185 186 static int pccbb_pcmcia_wait_ready(struct pcic_handle *); 187 static void pccbb_pcmcia_delay(struct pcic_handle *, int, const char *); 188 189 static void pccbb_pcmcia_do_io_map(struct pcic_handle *, int); 190 static void pccbb_pcmcia_do_mem_map(struct pcic_handle *, int); 191 static void pccbb_powerhook(int, void *); 192 193 /* bus-space allocation and deallocation functions */ 194 #if rbus 195 196 static int pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t, rbus_tag_t, 197 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 198 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp); 199 static int pccbb_rbus_cb_space_free(cardbus_chipset_tag_t, rbus_tag_t, 200 bus_space_handle_t, bus_size_t); 201 202 #endif /* rbus */ 203 204 #if rbus 205 206 static int pccbb_open_win(struct pccbb_softc *, bus_space_tag_t, 207 bus_addr_t, bus_size_t, bus_space_handle_t, int flags); 208 static int pccbb_close_win(struct pccbb_softc *, bus_space_tag_t, 209 bus_space_handle_t, bus_size_t); 210 static int pccbb_winlist_insert(struct pccbb_win_chain_head *, bus_addr_t, 211 bus_size_t, bus_space_handle_t, int); 212 static int pccbb_winlist_delete(struct pccbb_win_chain_head *, 213 bus_space_handle_t, bus_size_t); 214 static void pccbb_winset(bus_addr_t align, struct pccbb_softc *, 215 bus_space_tag_t); 216 void pccbb_winlist_show(struct pccbb_win_chain *); 217 218 #endif /* rbus */ 219 220 /* for config_defer */ 221 static void pccbb_pci_callback(struct device *); 222 223 #if defined SHOW_REGS 224 static void cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, 225 bus_space_tag_t memt, bus_space_handle_t memh); 226 #endif 227 228 CFATTACH_DECL(cbb_pci, sizeof(struct pccbb_softc), 229 pcicbbmatch, pccbbattach, NULL, NULL); 230 231 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 232 pccbb_pcmcia_mem_alloc, 233 pccbb_pcmcia_mem_free, 234 pccbb_pcmcia_mem_map, 235 pccbb_pcmcia_mem_unmap, 236 pccbb_pcmcia_io_alloc, 237 pccbb_pcmcia_io_free, 238 pccbb_pcmcia_io_map, 239 pccbb_pcmcia_io_unmap, 240 pccbb_pcmcia_intr_establish, 241 pccbb_pcmcia_intr_disestablish, 242 pccbb_pcmcia_socket_enable, 243 pccbb_pcmcia_socket_disable, 244 pccbb_pcmcia_socket_settype, 245 pccbb_pcmcia_card_detect 246 }; 247 248 #if rbus 249 static struct cardbus_functions pccbb_funcs = { 250 pccbb_rbus_cb_space_alloc, 251 pccbb_rbus_cb_space_free, 252 pccbb_cb_intr_establish, 253 pccbb_cb_intr_disestablish, 254 pccbb_ctrl, 255 pccbb_power, 256 pccbb_make_tag, 257 pccbb_free_tag, 258 pccbb_conf_read, 259 pccbb_conf_write, 260 }; 261 #else 262 static struct cardbus_functions pccbb_funcs = { 263 pccbb_ctrl, 264 pccbb_power, 265 pccbb_mem_open, 266 pccbb_mem_close, 267 pccbb_io_open, 268 pccbb_io_close, 269 pccbb_cb_intr_establish, 270 pccbb_cb_intr_disestablish, 271 pccbb_make_tag, 272 pccbb_conf_read, 273 pccbb_conf_write, 274 }; 275 #endif 276 277 int 278 pcicbbmatch(struct device *parent, struct cfdata *match, void *aux) 279 { 280 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 281 282 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 283 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 284 PCI_INTERFACE(pa->pa_class) == 0) { 285 return 1; 286 } 287 288 return 0; 289 } 290 291 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 292 | ((prod) << PCI_PRODUCT_SHIFT)) 293 294 const struct yenta_chipinfo { 295 pcireg_t yc_id; /* vendor tag | product tag */ 296 int yc_chiptype; 297 int yc_flags; 298 } yc_chipsets[] = { 299 /* Texas Instruments chips */ 300 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 301 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 302 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 303 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 304 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI125X, 305 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 306 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 307 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 308 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 309 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 310 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 311 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 312 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI125X, 313 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 314 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI125X, 315 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 316 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 317 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 318 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 319 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 320 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 321 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 322 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI125X, 323 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 324 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 325 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 326 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1520), CB_TI12XX, 327 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 328 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4410YENTA), CB_TI12XX, 329 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 330 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4520YENTA), CB_TI12XX, 331 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 332 333 /* Ricoh chips */ 334 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 335 PCCBB_PCMCIA_MEM_32}, 336 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 337 PCCBB_PCMCIA_MEM_32}, 338 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 339 PCCBB_PCMCIA_MEM_32}, 340 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 341 PCCBB_PCMCIA_MEM_32}, 342 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 343 PCCBB_PCMCIA_MEM_32}, 344 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 345 PCCBB_PCMCIA_MEM_32}, 346 347 /* Toshiba products */ 348 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 349 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 350 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 351 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 352 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 353 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 354 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 355 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 356 357 /* Cirrus Logic products */ 358 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 359 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 360 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 361 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 362 363 /* sentinel, or Generic chip */ 364 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 365 }; 366 367 static int 368 cb_chipset(u_int32_t pci_id, int *flagp) 369 { 370 const struct yenta_chipinfo *yc; 371 372 /* Loop over except the last default entry. */ 373 for (yc = yc_chipsets; yc < yc_chipsets + 374 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 375 if (pci_id == yc->yc_id) 376 break; 377 378 if (flagp != NULL) 379 *flagp = yc->yc_flags; 380 381 return (yc->yc_chiptype); 382 } 383 384 static void 385 pccbb_shutdown(void *arg) 386 { 387 struct pccbb_softc *sc = arg; 388 pcireg_t command; 389 390 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 391 392 /* 393 * turn off power 394 * 395 * XXX - do not turn off power if chipset is TI 113X because 396 * only TI 1130 with PowerMac 2400 hangs in pccbb_power(). 397 */ 398 if (sc->sc_chipset != CB_TI113X) { 399 pccbb_power((cardbus_chipset_tag_t)sc, 400 CARDBUS_VCC_0V | CARDBUS_VPP_0V); 401 } 402 403 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 404 0); 405 406 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 407 408 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 409 PCI_COMMAND_MASTER_ENABLE); 410 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 411 412 } 413 414 void 415 pccbbattach(struct device *parent, struct device *self, void *aux) 416 { 417 struct pccbb_softc *sc = (void *)self; 418 struct pci_attach_args *pa = aux; 419 pci_chipset_tag_t pc = pa->pa_pc; 420 pcireg_t busreg, reg, sock_base; 421 bus_addr_t sockbase; 422 char devinfo[256]; 423 int flags; 424 int pwrmgt_offs; 425 426 #ifdef __HAVE_PCCBB_ATTACH_HOOK 427 pccbb_attach_hook(parent, self, pa); 428 #endif 429 430 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 431 432 pci_devinfo(pa->pa_id, 0, 0, devinfo, sizeof(devinfo)); 433 printf(": %s (rev. 0x%02x)", devinfo, PCI_REVISION(pa->pa_class)); 434 DPRINTF((" (chipflags %x)", flags)); 435 printf("\n"); 436 437 TAILQ_INIT(&sc->sc_memwindow); 438 TAILQ_INIT(&sc->sc_iowindow); 439 440 #if rbus 441 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 442 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 443 444 #if 0 445 printf("pa->pa_memt: %08x vs rbus_mem->rb_bt: %08x\n", 446 pa->pa_memt, sc->sc_rbus_memt->rb_bt); 447 #endif 448 #endif /* rbus */ 449 450 sc->sc_flags &= ~CBB_MEMHMAPPED; 451 452 /* power management: set D0 state */ 453 sc->sc_pwrmgt_offs = 0; 454 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, 455 &pwrmgt_offs, 0)) { 456 reg = pci_conf_read(pc, pa->pa_tag, pwrmgt_offs + PCI_PMCSR); 457 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 458 reg & 0x100 /* PCI_PMCSR_PME_EN */) { 459 reg &= ~PCI_PMCSR_STATE_MASK; 460 reg |= PCI_PMCSR_STATE_D0; 461 reg &= ~(0x100 /* PCI_PMCSR_PME_EN */); 462 pci_conf_write(pc, pa->pa_tag, 463 pwrmgt_offs + PCI_PMCSR, reg); 464 } 465 466 sc->sc_pwrmgt_offs = pwrmgt_offs; 467 } 468 469 /* 470 * MAP socket registers and ExCA registers on memory-space 471 * When no valid address is set on socket base registers (on pci 472 * config space), get it not polite way. 473 */ 474 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 475 476 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 477 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 478 /* The address must be valid. */ 479 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 480 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL)) { 481 printf("%s: can't map socket base address 0x%lx\n", 482 sc->sc_dev.dv_xname, (unsigned long)sock_base); 483 /* 484 * I think it's funny: socket base registers must be 485 * mapped on memory space, but ... 486 */ 487 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 488 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 489 NULL)) { 490 printf("%s: can't map socket base address" 491 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 492 (unsigned long)sockbase); 493 /* give up... allocate reg space via rbus. */ 494 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 495 } else 496 sc->sc_flags |= CBB_MEMHMAPPED; 497 } else { 498 DPRINTF(("%s: socket base address 0x%lx\n", 499 sc->sc_dev.dv_xname, (unsigned long)sockbase)); 500 sc->sc_flags |= CBB_MEMHMAPPED; 501 } 502 } 503 504 sc->sc_mem_start = 0; /* XXX */ 505 sc->sc_mem_end = 0xffffffff; /* XXX */ 506 507 /* 508 * When interrupt isn't routed correctly, give up probing cbb and do 509 * not kill pcic-compatible port. 510 * 511 * However, if we are using an ioapic, avoid this check -- pa_intrline 512 * may well be zero, with the interrupt routed through the apic. 513 */ 514 515 #if NIOAPIC == 0 && NACPI == 0 516 if ((0 == pa->pa_intrline) || (255 == pa->pa_intrline)) { 517 printf("%s: NOT USED because of unconfigured interrupt\n", 518 sc->sc_dev.dv_xname); 519 return; 520 } 521 #endif 522 523 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 524 525 /* pccbb_machdep.c end */ 526 527 #if defined CBB_DEBUG 528 { 529 static const char *intrname[] = { "NON", "A", "B", "C", "D" }; 530 printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname, 531 intrname[pa->pa_intrpin], pa->pa_intrline); 532 } 533 #endif 534 535 /* setup softc */ 536 sc->sc_pc = pc; 537 sc->sc_iot = pa->pa_iot; 538 sc->sc_memt = pa->pa_memt; 539 sc->sc_dmat = pa->pa_dmat; 540 sc->sc_tag = pa->pa_tag; 541 sc->sc_function = pa->pa_function; 542 sc->sc_sockbase = sock_base; 543 sc->sc_busnum = busreg; 544 545 memcpy(&sc->sc_pa, pa, sizeof(*pa)); 546 547 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 548 549 shutdownhook_establish(pccbb_shutdown, sc); 550 551 /* Disable legacy register mapping. */ 552 switch (sc->sc_chipset) { 553 case CB_RX5C46X: /* fallthrough */ 554 #if 0 555 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 556 case CB_RX5C47X: 557 #endif 558 /* 559 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 560 * cannot be disabled by substituting 0 into PCI_LEGACY 561 * register. Ricoh CardBus bridges have special bits on Bridge 562 * control reg (addr 0x3e on PCI config space). 563 */ 564 reg = pci_conf_read(pc, pa->pa_tag, PCI_BCR_INTR); 565 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 566 pci_conf_write(pc, pa->pa_tag, PCI_BCR_INTR, reg); 567 break; 568 569 default: 570 /* XXX I don't know proper way to kill legacy I/O. */ 571 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 572 break; 573 } 574 575 config_defer(self, pccbb_pci_callback); 576 } 577 578 579 580 581 /* 582 * static void pccbb_pci_callback(struct device *self) 583 * 584 * The actual attach routine: get memory space for YENTA register 585 * space, setup YENTA register and route interrupt. 586 * 587 * This function should be deferred because this device may obtain 588 * memory space dynamically. This function must avoid obtaining 589 * memory area which has already kept for another device. 590 */ 591 static void 592 pccbb_pci_callback(struct device *self) 593 { 594 struct pccbb_softc *sc = (void *)self; 595 pci_chipset_tag_t pc = sc->sc_pc; 596 pci_intr_handle_t ih; 597 const char *intrstr = NULL; 598 bus_addr_t sockbase; 599 struct cbslot_attach_args cba; 600 struct pcmciabus_attach_args paa; 601 struct cardslot_attach_args caa; 602 struct cardslot_softc *csc; 603 604 if (!(sc->sc_flags & CBB_MEMHMAPPED)) { 605 /* The socket registers aren't mapped correctly. */ 606 #if rbus 607 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 608 (sc->sc_chipset == CB_RX5C47X 609 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 610 0, &sockbase, &sc->sc_base_memh)) { 611 return; 612 } 613 sc->sc_base_memt = sc->sc_memt; 614 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 615 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 616 sc->sc_dev.dv_xname, (unsigned long)sockbase, 617 (unsigned long)pci_conf_read(pc, sc->sc_tag, 618 PCI_SOCKBASE))); 619 #else 620 sc->sc_base_memt = sc->sc_memt; 621 #if !defined CBB_PCI_BASE 622 #define CBB_PCI_BASE 0x20000000 623 #endif 624 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 625 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 626 /* cannot allocate memory space */ 627 return; 628 } 629 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 630 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 631 sc->sc_dev.dv_xname, (unsigned long)sock_base, 632 (unsigned long)pci_conf_read(pc, 633 sc->sc_tag, PCI_SOCKBASE))); 634 sc->sc_sockbase = sockbase; 635 #endif 636 sc->sc_flags |= CBB_MEMHMAPPED; 637 } 638 639 /* bus bridge initialization */ 640 pccbb_chipinit(sc); 641 642 /* clear data structure for child device interrupt handlers */ 643 LIST_INIT(&sc->sc_pil); 644 sc->sc_pil_intr_enable = 1; 645 646 /* Map and establish the interrupt. */ 647 if (pci_intr_map(&sc->sc_pa, &ih)) { 648 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 649 return; 650 } 651 intrstr = pci_intr_string(pc, ih); 652 653 /* 654 * XXX pccbbintr should be called under the priority lower 655 * than any other hard interupts. 656 */ 657 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 658 659 if (sc->sc_ih == NULL) { 660 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 661 if (intrstr != NULL) { 662 printf(" at %s", intrstr); 663 } 664 printf("\n"); 665 return; 666 } 667 668 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 669 powerhook_establish(sc->sc_dev.dv_xname, pccbb_powerhook, sc); 670 671 { 672 u_int32_t sockstat; 673 674 sockstat = bus_space_read_4(sc->sc_base_memt, 675 sc->sc_base_memh, CB_SOCKET_STAT); 676 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 677 sc->sc_flags |= CBB_CARDEXIST; 678 } 679 } 680 681 /* 682 * attach cardbus 683 */ 684 { 685 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 686 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 687 688 /* initialize cbslot_attach */ 689 cba.cba_busname = "cardbus"; 690 cba.cba_iot = sc->sc_iot; 691 cba.cba_memt = sc->sc_memt; 692 cba.cba_dmat = sc->sc_dmat; 693 cba.cba_bus = (busreg >> 8) & 0x0ff; 694 cba.cba_cc = (void *)sc; 695 cba.cba_cf = &pccbb_funcs; 696 cba.cba_intrline = sc->sc_pa.pa_intrline; 697 698 #if rbus 699 cba.cba_rbus_iot = sc->sc_rbus_iot; 700 cba.cba_rbus_memt = sc->sc_rbus_memt; 701 #endif 702 703 cba.cba_cacheline = PCI_CACHELINE(bhlc); 704 cba.cba_lattimer = PCI_CB_LATENCY(busreg); 705 706 if (bootverbose) { 707 printf("%s: cacheline 0x%x lattimer 0x%x\n", 708 sc->sc_dev.dv_xname, cba.cba_cacheline, 709 cba.cba_lattimer); 710 printf("%s: bhlc 0x%x lscp 0x%x\n", 711 sc->sc_dev.dv_xname, bhlc, busreg); 712 } 713 #if defined SHOW_REGS 714 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 715 sc->sc_base_memh); 716 #endif 717 } 718 719 pccbb_pcmcia_attach_setup(sc, &paa); 720 caa.caa_cb_attach = NULL; 721 if (cba.cba_bus == 0) 722 printf("%s: secondary bus number uninitialized; try PCI_BUS_FIXUP\n", sc->sc_dev.dv_xname); 723 else 724 caa.caa_cb_attach = &cba; 725 caa.caa_16_attach = &paa; 726 caa.caa_ph = &sc->sc_pcmcia_h; 727 728 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 729 DPRINTF(("%s: found cardslot\n", __func__)); 730 sc->sc_csc = csc; 731 } 732 733 return; 734 } 735 736 737 738 739 740 /* 741 * static void pccbb_chipinit(struct pccbb_softc *sc) 742 * 743 * This function initialize YENTA chip registers listed below: 744 * 1) PCI command reg, 745 * 2) PCI and CardBus latency timer, 746 * 3) route PCI interrupt, 747 * 4) close all memory and io windows. 748 * 5) turn off bus power. 749 * 6) card detect and power cycle interrupts on. 750 * 7) clear interrupt 751 */ 752 static void 753 pccbb_chipinit(struct pccbb_softc *sc) 754 { 755 pci_chipset_tag_t pc = sc->sc_pc; 756 pcitag_t tag = sc->sc_tag; 757 bus_space_tag_t bmt = sc->sc_base_memt; 758 bus_space_handle_t bmh = sc->sc_base_memh; 759 pcireg_t reg; 760 761 /* 762 * Set PCI command reg. 763 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 764 */ 765 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 766 /* I believe it is harmless. */ 767 reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 768 PCI_COMMAND_MASTER_ENABLE); 769 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg); 770 771 /* 772 * Set CardBus latency timer. 773 */ 774 reg = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 775 if (PCI_CB_LATENCY(reg) < 0x20) { 776 reg &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 777 reg |= (0x20 << PCI_CB_LATENCY_SHIFT); 778 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, reg); 779 } 780 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 781 PCI_CB_LATENCY(reg), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 782 783 /* 784 * Set PCI latency timer. 785 */ 786 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 787 if (PCI_LATTIMER(reg) < 0x10) { 788 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 789 reg |= (0x10 << PCI_LATTIMER_SHIFT); 790 pci_conf_write(pc, tag, PCI_BHLC_REG, reg); 791 } 792 DPRINTF(("PCI latency timer 0x%x (%x)\n", 793 PCI_LATTIMER(reg), pci_conf_read(pc, tag, PCI_BHLC_REG))); 794 795 796 /* Route functional interrupts to PCI. */ 797 reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 798 reg |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 799 reg |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 800 reg |= CB_BCR_RESET_ENABLE; /* assert reset */ 801 pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 802 803 switch (sc->sc_chipset) { 804 case CB_TI113X: 805 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 806 /* This bit is shared, but may read as 0 on some chips, so set 807 it explicitly on both functions. */ 808 reg |= PCI113X_CBCTRL_PCI_IRQ_ENA; 809 /* CSC intr enable */ 810 reg |= PCI113X_CBCTRL_PCI_CSC; 811 /* functional intr prohibit | prohibit ISA routing */ 812 reg &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 813 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 814 break; 815 816 case CB_TI12XX: 817 /* 818 * Some TI 12xx (and [14][45]xx) based pci cards 819 * sometimes have issues with the MFUNC register not 820 * being initialized due to a bad EEPROM on board. 821 * Laptops that this matters on have this register 822 * properly initialized. 823 * 824 * The TI125X parts have a different register. 825 */ 826 reg = pci_conf_read(pc, tag, PCI12XX_MFUNC); 827 if (reg == 0) { 828 reg &= ~PCI12XX_MFUNC_PIN0; 829 reg |= PCI12XX_MFUNC_PIN0_INTA; 830 if ((pci_conf_read(pc, tag, PCI_SYSCTRL) & 831 PCI12XX_SYSCTRL_INTRTIE) == 0) { 832 reg &= ~PCI12XX_MFUNC_PIN1; 833 reg |= PCI12XX_MFUNC_PIN1_INTB; 834 } 835 pci_conf_write(pc, tag, PCI12XX_MFUNC, reg); 836 } 837 /* fallthrough */ 838 839 case CB_TI125X: 840 /* 841 * Disable zoom video. Some machines initialize this 842 * improperly and experience has shown that this helps 843 * prevent strange behavior. 844 */ 845 pci_conf_write(pc, tag, PCI12XX_MMCTRL, 0); 846 847 reg = pci_conf_read(pc, tag, PCI_SYSCTRL); 848 reg |= PCI12XX_SYSCTRL_VCCPROT; 849 pci_conf_write(pc, tag, PCI_SYSCTRL, reg); 850 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 851 reg |= PCI12XX_CBCTRL_CSC; 852 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 853 break; 854 855 case CB_TOPIC95B: 856 reg = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 857 reg |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 858 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, reg); 859 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 860 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 861 sc->sc_dev.dv_xname, reg)); 862 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 863 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 864 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 865 DPRINTF(("0x%x\n", reg)); 866 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 867 break; 868 869 case CB_TOPIC97: 870 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 871 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 872 sc->sc_dev.dv_xname, reg)); 873 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 874 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 875 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 876 reg |= TOPIC97_SLOT_CTRL_PCIINT; 877 reg &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 878 DPRINTF(("0x%x\n", reg)); 879 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 880 /* make sure to assert LV card support bits */ 881 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 882 0x800 + 0x3e, 883 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 884 0x800 + 0x3e) | 0x03); 885 break; 886 } 887 888 /* Close all memory and I/O windows. */ 889 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 890 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 891 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 892 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 893 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 894 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 895 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 896 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 897 898 /* reset 16-bit pcmcia bus */ 899 bus_space_write_1(bmt, bmh, 0x800 + PCIC_INTR, 900 bus_space_read_1(bmt, bmh, 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 901 902 /* turn off power */ 903 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 904 905 /* CSC Interrupt: Card detect and power cycle interrupts on */ 906 reg = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 907 reg |= CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; 908 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, reg); 909 /* reset interrupt */ 910 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 911 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 912 } 913 914 915 916 917 /* 918 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 919 * struct pcmciabus_attach_args *paa) 920 * 921 * This function attaches 16-bit PCcard bus. 922 */ 923 STATIC void 924 pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 925 struct pcmciabus_attach_args *paa) 926 { 927 struct pcic_handle *ph = &sc->sc_pcmcia_h; 928 #if rbus 929 rbus_tag_t rb; 930 #endif 931 932 /* initialize pcmcia part in pccbb_softc */ 933 ph->ph_parent = (struct device *)sc; 934 ph->sock = sc->sc_function; 935 ph->flags = 0; 936 ph->shutdown = 0; 937 ph->ih_irq = sc->sc_pa.pa_intrline; 938 ph->ph_bus_t = sc->sc_base_memt; 939 ph->ph_bus_h = sc->sc_base_memh; 940 ph->ph_read = pccbb_pcmcia_read; 941 ph->ph_write = pccbb_pcmcia_write; 942 sc->sc_pct = &pccbb_pcmcia_funcs; 943 944 /* 945 * We need to do a few things here: 946 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 947 * setting the IRQ numbers to 0. 948 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 949 * routing of CSC interrupts (e.g. card removal) to PCI while in 950 * PCMCIA mode. We just leave this set all the time. 951 * 3) Enable card insertion/removal interrupts in case the chip also 952 * needs that while in PCMCIA mode. 953 * 4) Clear any pending CSC interrupt. 954 */ 955 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE); 956 if (sc->sc_chipset == CB_TI113X) { 957 Pcic_write(ph, PCIC_CSC_INTR, 0); 958 } else { 959 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 960 Pcic_read(ph, PCIC_CSC); 961 } 962 963 /* initialize pcmcia bus attachment */ 964 paa->paa_busname = "pcmcia"; 965 paa->pct = sc->sc_pct; 966 paa->pch = ph; 967 paa->iobase = 0; /* I don't use them */ 968 paa->iosize = 0; 969 #if rbus 970 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 971 paa->iobase = rb->rb_start + rb->rb_offset; 972 paa->iosize = rb->rb_end - rb->rb_start; 973 #endif 974 975 return; 976 } 977 978 #if 0 979 STATIC void 980 pccbb_pcmcia_attach_card(struct pcic_handle *ph) 981 { 982 if (ph->flags & PCIC_FLAG_CARDP) { 983 panic("pccbb_pcmcia_attach_card: already attached"); 984 } 985 986 /* call the MI attach function */ 987 pcmcia_card_attach(ph->pcmcia); 988 989 ph->flags |= PCIC_FLAG_CARDP; 990 } 991 992 STATIC void 993 pccbb_pcmcia_detach_card(struct pcic_handle *ph, int flags) 994 { 995 if (!(ph->flags & PCIC_FLAG_CARDP)) { 996 panic("pccbb_pcmcia_detach_card: already detached"); 997 } 998 999 ph->flags &= ~PCIC_FLAG_CARDP; 1000 1001 /* call the MI detach function */ 1002 pcmcia_card_detach(ph->pcmcia, flags); 1003 } 1004 #endif 1005 1006 /* 1007 * int pccbbintr(arg) 1008 * void *arg; 1009 * This routine handles the interrupt from Yenta PCI-CardBus bridge 1010 * itself. 1011 */ 1012 int 1013 pccbbintr(void *arg) 1014 { 1015 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1016 u_int32_t sockevent, sockstate; 1017 bus_space_tag_t memt = sc->sc_base_memt; 1018 bus_space_handle_t memh = sc->sc_base_memh; 1019 struct pcic_handle *ph = &sc->sc_pcmcia_h; 1020 1021 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 1022 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 1023 Pcic_read(ph, PCIC_CSC); 1024 1025 if (sockevent == 0) { 1026 /* This intr is not for me: it may be for my child devices. */ 1027 if (sc->sc_pil_intr_enable) { 1028 return pccbbintr_function(sc); 1029 } else { 1030 return 0; 1031 } 1032 } 1033 1034 aprint_debug("%s: enter sockevent %" PRIx32 "\n", __func__, sockevent); 1035 1036 if (sockevent & CB_SOCKET_EVENT_CD) { 1037 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1038 if (0x00 != (sockstate & CB_SOCKET_STAT_CD)) { 1039 /* A card should be removed. */ 1040 if (sc->sc_flags & CBB_CARDEXIST) { 1041 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 1042 sockevent)); 1043 DPRINTF((" card removed, 0x%08x\n", sockstate)); 1044 sc->sc_flags &= ~CBB_CARDEXIST; 1045 if (sc->sc_csc->sc_status & 1046 CARDSLOT_STATUS_CARD_16) { 1047 #if 0 1048 struct pcic_handle *ph = 1049 &sc->sc_pcmcia_h; 1050 1051 pcmcia_card_deactivate(ph->pcmcia); 1052 pccbb_pcmcia_socket_disable(ph); 1053 pccbb_pcmcia_detach_card(ph, 1054 DETACH_FORCE); 1055 #endif 1056 cardslot_event_throw(sc->sc_csc, 1057 CARDSLOT_EVENT_REMOVAL_16); 1058 } else if (sc->sc_csc->sc_status & 1059 CARDSLOT_STATUS_CARD_CB) { 1060 /* Cardbus intr removed */ 1061 cardslot_event_throw(sc->sc_csc, 1062 CARDSLOT_EVENT_REMOVAL_CB); 1063 } 1064 } else if (sc->sc_flags & CBB_INSERTING) { 1065 sc->sc_flags &= ~CBB_INSERTING; 1066 callout_stop(&sc->sc_insert_ch); 1067 } 1068 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 1069 /* 1070 * The pccbbintr may called from powerdown hook when 1071 * the system resumed, to detect the card 1072 * insertion/removal during suspension. 1073 */ 1074 (sc->sc_flags & CBB_CARDEXIST) == 0) { 1075 if (sc->sc_flags & CBB_INSERTING) { 1076 callout_stop(&sc->sc_insert_ch); 1077 } 1078 callout_reset(&sc->sc_insert_ch, hz / 5, 1079 pci113x_insert, sc); 1080 sc->sc_flags |= CBB_INSERTING; 1081 } 1082 } 1083 1084 if (sockevent & CB_SOCKET_EVENT_POWER) { 1085 DPRINTF(("Powercycling because of socket event\n")); 1086 /* XXX: Does not happen when attaching a 16-bit card */ 1087 sc->sc_pwrcycle++; 1088 wakeup(&sc->sc_pwrcycle); 1089 } 1090 1091 return (1); 1092 } 1093 1094 /* 1095 * static int pccbbintr_function(struct pccbb_softc *sc) 1096 * 1097 * This function calls each interrupt handler registered at the 1098 * bridge. The interrupt handlers are called in registered order. 1099 */ 1100 static int 1101 pccbbintr_function(struct pccbb_softc *sc) 1102 { 1103 int retval = 0, val; 1104 struct pccbb_intrhand_list *pil; 1105 int s; 1106 1107 for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1108 pil = LIST_NEXT(pil, pil_next)) { 1109 s = splraiseipl(pil->pil_icookie); 1110 val = (*pil->pil_func)(pil->pil_arg); 1111 splx(s); 1112 1113 retval = retval == 1 ? 1 : 1114 retval == 0 ? val : val != 0 ? val : retval; 1115 } 1116 1117 return retval; 1118 } 1119 1120 static void 1121 pci113x_insert(void *arg) 1122 { 1123 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1124 u_int32_t sockevent, sockstate; 1125 1126 if (!(sc->sc_flags & CBB_INSERTING)) { 1127 /* We add a card only under inserting state. */ 1128 return; 1129 } 1130 sc->sc_flags &= ~CBB_INSERTING; 1131 1132 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1133 CB_SOCKET_EVENT); 1134 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1135 CB_SOCKET_STAT); 1136 1137 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1138 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1139 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1140 sc->sc_flags |= CBB_CARDEXIST; 1141 /* call pccard interrupt handler here */ 1142 if (sockstate & CB_SOCKET_STAT_16BIT) { 1143 /* 16-bit card found */ 1144 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1145 cardslot_event_throw(sc->sc_csc, 1146 CARDSLOT_EVENT_INSERTION_16); 1147 } else if (sockstate & CB_SOCKET_STAT_CB) { 1148 /* cardbus card found */ 1149 /* cardbus_attach_card(sc->sc_csc); */ 1150 cardslot_event_throw(sc->sc_csc, 1151 CARDSLOT_EVENT_INSERTION_CB); 1152 } else { 1153 /* who are you? */ 1154 } 1155 } else { 1156 callout_reset(&sc->sc_insert_ch, hz / 10, 1157 pci113x_insert, sc); 1158 } 1159 } 1160 1161 #define PCCBB_PCMCIA_OFFSET 0x800 1162 static u_int8_t 1163 pccbb_pcmcia_read(struct pcic_handle *ph, int reg) 1164 { 1165 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1166 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1167 1168 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1169 PCCBB_PCMCIA_OFFSET + reg); 1170 } 1171 1172 static void 1173 pccbb_pcmcia_write(struct pcic_handle *ph, int reg, u_int8_t val) 1174 { 1175 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1176 val); 1177 1178 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1179 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1180 } 1181 1182 /* 1183 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1184 */ 1185 STATIC int 1186 pccbb_ctrl(cardbus_chipset_tag_t ct, int command) 1187 { 1188 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1189 1190 switch (command) { 1191 case CARDBUS_CD: 1192 if (2 == pccbb_detect_card(sc)) { 1193 int retval = 0; 1194 int status = cb_detect_voltage(sc); 1195 if (PCCARD_VCC_5V & status) { 1196 retval |= CARDBUS_5V_CARD; 1197 } 1198 if (PCCARD_VCC_3V & status) { 1199 retval |= CARDBUS_3V_CARD; 1200 } 1201 if (PCCARD_VCC_XV & status) { 1202 retval |= CARDBUS_XV_CARD; 1203 } 1204 if (PCCARD_VCC_YV & status) { 1205 retval |= CARDBUS_YV_CARD; 1206 } 1207 return retval; 1208 } else { 1209 return 0; 1210 } 1211 case CARDBUS_RESET: 1212 return cb_reset(sc); 1213 case CARDBUS_IO_ENABLE: /* fallthrough */ 1214 case CARDBUS_IO_DISABLE: /* fallthrough */ 1215 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1216 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1217 case CARDBUS_BM_ENABLE: /* fallthrough */ 1218 case CARDBUS_BM_DISABLE: /* fallthrough */ 1219 /* XXX: I think we don't need to call this function below. */ 1220 return pccbb_cardenable(sc, command); 1221 } 1222 1223 return 0; 1224 } 1225 1226 /* 1227 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1228 * This function returns true when it succeeds and returns false when 1229 * it fails. 1230 */ 1231 STATIC int 1232 pccbb_power(cardbus_chipset_tag_t ct, int command) 1233 { 1234 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1235 u_int32_t status, osock_ctrl, sock_ctrl, reg_ctrl; 1236 bus_space_tag_t memt = sc->sc_base_memt; 1237 bus_space_handle_t memh = sc->sc_base_memh; 1238 int on = 0, pwrcycle, s, times; 1239 struct timeval before, after, diff; 1240 1241 DPRINTF(("pccbb_power: %s and %s [0x%x]\n", 1242 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1243 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1244 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1245 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1246 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1247 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1248 "UNKNOWN", 1249 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1250 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1251 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1252 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1253 "UNKNOWN", command)); 1254 1255 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1256 osock_ctrl = sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1257 1258 switch (command & CARDBUS_VCCMASK) { 1259 case CARDBUS_VCC_UC: 1260 break; 1261 case CARDBUS_VCC_5V: 1262 on++; 1263 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1264 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1265 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1266 } else { 1267 printf("%s: BAD voltage request: no 5 V card\n", 1268 sc->sc_dev.dv_xname); 1269 return 0; 1270 } 1271 break; 1272 case CARDBUS_VCC_3V: 1273 on++; 1274 if (CB_SOCKET_STAT_3VCARD & status) { 1275 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1276 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1277 } else { 1278 printf("%s: BAD voltage request: no 3.3 V card\n", 1279 sc->sc_dev.dv_xname); 1280 return 0; 1281 } 1282 break; 1283 case CARDBUS_VCC_0V: 1284 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1285 break; 1286 default: 1287 return 0; /* power NEVER changed */ 1288 } 1289 1290 switch (command & CARDBUS_VPPMASK) { 1291 case CARDBUS_VPP_UC: 1292 break; 1293 case CARDBUS_VPP_0V: 1294 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1295 break; 1296 case CARDBUS_VPP_VCC: 1297 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1298 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1299 break; 1300 case CARDBUS_VPP_12V: 1301 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1302 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1303 break; 1304 } 1305 1306 pwrcycle = sc->sc_pwrcycle; 1307 aprint_debug("%s: osock_ctrl %#" PRIx32 " sock_ctrl %#" PRIx32 "\n", 1308 device_xname(&sc->sc_dev), osock_ctrl, sock_ctrl); 1309 1310 microtime(&before); 1311 s = splbio(); 1312 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1313 1314 /* 1315 * Wait as long as 200ms for a power-cycle interrupt. If 1316 * interrupts are enabled, but the socket has already 1317 * changed to the desired status, keep waiting for the 1318 * interrupt. "Consuming" the interrupt in this way keeps 1319 * the interrupt from prematurely waking some subsequent 1320 * pccbb_power call. 1321 * 1322 * XXX Not every bridge interrupts on the ->OFF transition. 1323 * XXX That's ok, we will time-out after 200ms. 1324 * 1325 * XXX The power cycle event will never happen when attaching 1326 * XXX a 16-bit card. That's ok, we will time-out after 1327 * XXX 200ms. 1328 */ 1329 for (times = 5; --times >= 0; ) { 1330 if (cold) 1331 DELAY(40 * 1000); 1332 else { 1333 (void)tsleep(&sc->sc_pwrcycle, PWAIT, "pccpwr", 1334 hz / 25); 1335 if (pwrcycle == sc->sc_pwrcycle) 1336 continue; 1337 } 1338 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1339 if ((status & CB_SOCKET_STAT_PWRCYCLE) != 0 && on) 1340 break; 1341 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0 && !on) 1342 break; 1343 } 1344 splx(s); 1345 microtime(&after); 1346 timersub(&after, &before, &diff); 1347 aprint_debug("%s: wait took%s %ld.%06lds\n", sc->sc_dev.dv_xname, 1348 (on && times < 0) ? " too long" : "", diff.tv_sec, diff.tv_usec); 1349 1350 /* 1351 * Ok, wait a bit longer for things to settle. 1352 */ 1353 if (on && sc->sc_chipset == CB_TOPIC95B) 1354 delay_ms(100, sc); 1355 1356 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1357 1358 if (on && sc->sc_chipset != CB_TOPIC95B) { 1359 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0) 1360 printf("%s: power on failed?\n", sc->sc_dev.dv_xname); 1361 } 1362 1363 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1364 printf("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1365 sc->sc_dev.dv_xname, sock_ctrl, status); 1366 printf("%s: disabling socket\n", sc->sc_dev.dv_xname); 1367 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1368 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1369 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1370 status &= ~CB_SOCKET_STAT_BADVCC; 1371 bus_space_write_4(memt, memh, CB_SOCKET_STAT, status); 1372 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1373 CB_SOCKET_STAT)); 1374 return 0; 1375 } 1376 1377 if (sc->sc_chipset == CB_TOPIC97) { 1378 reg_ctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL); 1379 reg_ctrl &= ~TOPIC97_REG_CTRL_TESTMODE; 1380 if ((command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V) 1381 reg_ctrl &= ~TOPIC97_REG_CTRL_CLKRUN_ENA; 1382 else 1383 reg_ctrl |= TOPIC97_REG_CTRL_CLKRUN_ENA; 1384 pci_conf_write(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL, reg_ctrl); 1385 } 1386 1387 return 1; /* power changed correctly */ 1388 } 1389 1390 #if defined CB_PCMCIA_POLL 1391 struct cb_poll_str { 1392 void *arg; 1393 int (*func)(void *); 1394 int level; 1395 pccard_chipset_tag_t ct; 1396 int count; 1397 struct callout poll_ch; 1398 }; 1399 1400 static struct cb_poll_str cb_poll[10]; 1401 static int cb_poll_n = 0; 1402 1403 static void cb_pcmcia_poll(void *arg); 1404 1405 static void 1406 cb_pcmcia_poll(void *arg) 1407 { 1408 struct cb_poll_str *poll = arg; 1409 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1410 struct pccbb_softc *sc = psc->cpc_parent; 1411 int s; 1412 u_int32_t spsr; /* socket present-state reg */ 1413 1414 callout_reset(&poll->poll_ch, hz / 10, cb_pcmcia_poll, poll); 1415 switch (poll->level) { 1416 case IPL_NET: 1417 s = splnet(); 1418 break; 1419 case IPL_BIO: 1420 s = splbio(); 1421 break; 1422 case IPL_TTY: /* fallthrough */ 1423 default: 1424 s = spltty(); 1425 break; 1426 } 1427 1428 spsr = 1429 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1430 CB_SOCKET_STAT); 1431 1432 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1433 if (!(spsr & 0x40)) { /* CINT low */ 1434 #else 1435 if (1) { 1436 #endif 1437 if ((*poll->func) (poll->arg) == 1) { 1438 ++poll->count; 1439 printf("intr: reported from poller, 0x%x\n", spsr); 1440 #if defined LEVEL2 1441 } else { 1442 printf("intr: miss! 0x%x\n", spsr); 1443 #endif 1444 } 1445 } 1446 splx(s); 1447 } 1448 #endif /* defined CB_PCMCIA_POLL */ 1449 1450 /* 1451 * static int pccbb_detect_card(struct pccbb_softc *sc) 1452 * return value: 0 if no card exists. 1453 * 1 if 16-bit card exists. 1454 * 2 if cardbus card exists. 1455 */ 1456 static int 1457 pccbb_detect_card(struct pccbb_softc *sc) 1458 { 1459 bus_space_handle_t base_memh = sc->sc_base_memh; 1460 bus_space_tag_t base_memt = sc->sc_base_memt; 1461 u_int32_t sockstat = 1462 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1463 int retval = 0; 1464 1465 /* CD1 and CD2 asserted */ 1466 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1467 /* card must be present */ 1468 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1469 /* NOTACARD DEASSERTED */ 1470 if (CB_SOCKET_STAT_CB & sockstat) { 1471 /* CardBus mode */ 1472 retval = 2; 1473 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1474 /* 16-bit mode */ 1475 retval = 1; 1476 } 1477 } 1478 } 1479 return retval; 1480 } 1481 1482 /* 1483 * STATIC int cb_reset(struct pccbb_softc *sc) 1484 * This function resets CardBus card. 1485 */ 1486 STATIC int 1487 cb_reset(struct pccbb_softc *sc) 1488 { 1489 /* 1490 * Reset Assert at least 20 ms 1491 * Some machines request longer duration. 1492 */ 1493 int reset_duration = 1494 (sc->sc_chipset == CB_RX5C47X ? 400 : 50); 1495 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1496 1497 /* Reset bit Assert (bit 6 at 0x3E) */ 1498 bcr |= CB_BCR_RESET_ENABLE; 1499 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1500 delay_ms(reset_duration, sc); 1501 1502 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1503 /* Reset bit Deassert (bit 6 at 0x3E) */ 1504 bcr &= ~CB_BCR_RESET_ENABLE; 1505 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1506 delay_ms(reset_duration, sc); 1507 } 1508 /* No card found on the slot. Keep Reset. */ 1509 return 1; 1510 } 1511 1512 /* 1513 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1514 * This function detect card Voltage. 1515 */ 1516 STATIC int 1517 cb_detect_voltage(struct pccbb_softc *sc) 1518 { 1519 u_int32_t psr; /* socket present-state reg */ 1520 bus_space_tag_t iot = sc->sc_base_memt; 1521 bus_space_handle_t ioh = sc->sc_base_memh; 1522 int vol = PCCARD_VCC_UKN; /* set 0 */ 1523 1524 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1525 1526 if (0x400u & psr) { 1527 vol |= PCCARD_VCC_5V; 1528 } 1529 if (0x800u & psr) { 1530 vol |= PCCARD_VCC_3V; 1531 } 1532 1533 return vol; 1534 } 1535 1536 STATIC int 1537 cbbprint(void *aux, const char *pcic) 1538 { 1539 #if 0 1540 struct cbslot_attach_args *cba = aux; 1541 1542 if (cba->cba_slot >= 0) { 1543 aprint_normal(" slot %d", cba->cba_slot); 1544 } 1545 #endif 1546 return UNCONF; 1547 } 1548 1549 /* 1550 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1551 * This function enables and disables the card 1552 */ 1553 STATIC int 1554 pccbb_cardenable(struct pccbb_softc *sc, int function) 1555 { 1556 u_int32_t command = 1557 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1558 1559 DPRINTF(("pccbb_cardenable:")); 1560 switch (function) { 1561 case CARDBUS_IO_ENABLE: 1562 command |= PCI_COMMAND_IO_ENABLE; 1563 break; 1564 case CARDBUS_IO_DISABLE: 1565 command &= ~PCI_COMMAND_IO_ENABLE; 1566 break; 1567 case CARDBUS_MEM_ENABLE: 1568 command |= PCI_COMMAND_MEM_ENABLE; 1569 break; 1570 case CARDBUS_MEM_DISABLE: 1571 command &= ~PCI_COMMAND_MEM_ENABLE; 1572 break; 1573 case CARDBUS_BM_ENABLE: 1574 command |= PCI_COMMAND_MASTER_ENABLE; 1575 break; 1576 case CARDBUS_BM_DISABLE: 1577 command &= ~PCI_COMMAND_MASTER_ENABLE; 1578 break; 1579 default: 1580 return 0; 1581 } 1582 1583 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1584 DPRINTF((" command reg 0x%x\n", command)); 1585 return 1; 1586 } 1587 1588 #if !rbus 1589 static int 1590 pccbb_io_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 1591 { 1592 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1593 int basereg; 1594 int limitreg; 1595 1596 if ((win < 0) || (win > 2)) { 1597 #if defined DIAGNOSTIC 1598 printf("cardbus_io_open: window out of range %d\n", win); 1599 #endif 1600 return 0; 1601 } 1602 1603 basereg = win * 8 + 0x2c; 1604 limitreg = win * 8 + 0x30; 1605 1606 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1607 start, basereg, end, limitreg)); 1608 1609 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1610 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1611 return 1; 1612 } 1613 1614 /* 1615 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1616 */ 1617 static int 1618 pccbb_io_close(cardbus_chipset_tag_t ct, int win) 1619 { 1620 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1621 int basereg; 1622 int limitreg; 1623 1624 if ((win < 0) || (win > 2)) { 1625 #if defined DIAGNOSTIC 1626 printf("cardbus_io_close: window out of range %d\n", win); 1627 #endif 1628 return 0; 1629 } 1630 1631 basereg = win * 8 + 0x2c; 1632 limitreg = win * 8 + 0x30; 1633 1634 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1635 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1636 return 1; 1637 } 1638 1639 static int 1640 pccbb_mem_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 1641 { 1642 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1643 int basereg; 1644 int limitreg; 1645 1646 if ((win < 0) || (win > 2)) { 1647 #if defined DIAGNOSTIC 1648 printf("cardbus_mem_open: window out of range %d\n", win); 1649 #endif 1650 return 0; 1651 } 1652 1653 basereg = win * 8 + 0x1c; 1654 limitreg = win * 8 + 0x20; 1655 1656 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1657 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1658 return 1; 1659 } 1660 1661 static int 1662 pccbb_mem_close(cardbus_chipset_tag_t ct, int win) 1663 { 1664 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1665 int basereg; 1666 int limitreg; 1667 1668 if ((win < 0) || (win > 2)) { 1669 #if defined DIAGNOSTIC 1670 printf("cardbus_mem_close: window out of range %d\n", win); 1671 #endif 1672 return 0; 1673 } 1674 1675 basereg = win * 8 + 0x1c; 1676 limitreg = win * 8 + 0x20; 1677 1678 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1679 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1680 return 1; 1681 } 1682 #endif 1683 1684 /* 1685 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1686 * int irq, 1687 * int level, 1688 * int (* func)(void *), 1689 * void *arg) 1690 * 1691 * This function registers an interrupt handler at the bridge, in 1692 * order not to call the interrupt handlers of child devices when 1693 * a card-deletion interrupt occurs. 1694 * 1695 * The arguments irq and level are not used. 1696 */ 1697 static void * 1698 pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, int irq, int level, 1699 int (*func)(void *), void *arg) 1700 { 1701 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1702 1703 return pccbb_intr_establish(sc, irq, level, func, arg); 1704 } 1705 1706 1707 /* 1708 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1709 * void *ih) 1710 * 1711 * This function removes an interrupt handler pointed by ih. 1712 */ 1713 static void 1714 pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih) 1715 { 1716 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1717 1718 pccbb_intr_disestablish(sc, ih); 1719 } 1720 1721 1722 void 1723 pccbb_intr_route(struct pccbb_softc *sc) 1724 { 1725 pcireg_t bcr, cbctrl; 1726 1727 /* initialize bridge intr routing */ 1728 bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1729 bcr &= ~CB_BCR_INTR_IREQ_ENABLE; 1730 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1731 1732 switch (sc->sc_chipset) { 1733 case CB_TI113X: 1734 cbctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1735 /* functional intr enabled */ 1736 cbctrl |= PCI113X_CBCTRL_PCI_INTR; 1737 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, cbctrl); 1738 break; 1739 default: 1740 break; 1741 } 1742 } 1743 1744 /* 1745 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1746 * int irq, 1747 * int level, 1748 * int (* func)(void *), 1749 * void *arg) 1750 * 1751 * This function registers an interrupt handler at the bridge, in 1752 * order not to call the interrupt handlers of child devices when 1753 * a card-deletion interrupt occurs. 1754 * 1755 * The arguments irq is not used because pccbb selects intr vector. 1756 */ 1757 static void * 1758 pccbb_intr_establish(struct pccbb_softc *sc, int irq, int level, 1759 int (*func)(void *), void *arg) 1760 { 1761 struct pccbb_intrhand_list *pil, *newpil; 1762 1763 DPRINTF(("pccbb_intr_establish start. %p\n", LIST_FIRST(&sc->sc_pil))); 1764 1765 if (LIST_EMPTY(&sc->sc_pil)) { 1766 pccbb_intr_route(sc); 1767 } 1768 1769 /* 1770 * Allocate a room for interrupt handler structure. 1771 */ 1772 if (NULL == (newpil = 1773 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1774 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1775 return NULL; 1776 } 1777 1778 newpil->pil_func = func; 1779 newpil->pil_arg = arg; 1780 newpil->pil_icookie = makeiplcookie(level); 1781 1782 if (LIST_EMPTY(&sc->sc_pil)) { 1783 LIST_INSERT_HEAD(&sc->sc_pil, newpil, pil_next); 1784 } else { 1785 for (pil = LIST_FIRST(&sc->sc_pil); 1786 LIST_NEXT(pil, pil_next) != NULL; 1787 pil = LIST_NEXT(pil, pil_next)); 1788 LIST_INSERT_AFTER(pil, newpil, pil_next); 1789 } 1790 1791 DPRINTF(("pccbb_intr_establish add pil. %p\n", 1792 LIST_FIRST(&sc->sc_pil))); 1793 1794 return newpil; 1795 } 1796 1797 /* 1798 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1799 * void *ih) 1800 * 1801 * This function removes an interrupt handler pointed by ih. ih 1802 * should be the value returned by cardbus_intr_establish() or 1803 * NULL. 1804 * 1805 * When ih is NULL, this function will do nothing. 1806 */ 1807 static void 1808 pccbb_intr_disestablish(struct pccbb_softc *sc, void *ih) 1809 { 1810 struct pccbb_intrhand_list *pil; 1811 pcireg_t reg; 1812 1813 DPRINTF(("pccbb_intr_disestablish start. %p\n", 1814 LIST_FIRST(&sc->sc_pil))); 1815 1816 if (ih == NULL) { 1817 /* intr handler is not set */ 1818 DPRINTF(("pccbb_intr_disestablish: no ih\n")); 1819 return; 1820 } 1821 1822 #ifdef DIAGNOSTIC 1823 for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1824 pil = LIST_NEXT(pil, pil_next)) { 1825 DPRINTF(("pccbb_intr_disestablish: pil %p\n", pil)); 1826 if (pil == ih) { 1827 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1828 break; 1829 } 1830 } 1831 if (pil == NULL) { 1832 panic("pccbb_intr_disestablish: %s cannot find pil %p", 1833 sc->sc_dev.dv_xname, ih); 1834 } 1835 #endif 1836 1837 pil = (struct pccbb_intrhand_list *)ih; 1838 LIST_REMOVE(pil, pil_next); 1839 free(pil, M_DEVBUF); 1840 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1841 1842 if (LIST_EMPTY(&sc->sc_pil)) { 1843 /* No interrupt handlers */ 1844 1845 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1846 1847 /* stop routing PCI intr */ 1848 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1849 reg |= CB_BCR_INTR_IREQ_ENABLE; 1850 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1851 1852 switch (sc->sc_chipset) { 1853 case CB_TI113X: 1854 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1855 /* functional intr disabled */ 1856 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1857 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1858 break; 1859 default: 1860 break; 1861 } 1862 } 1863 } 1864 1865 #if defined SHOW_REGS 1866 static void 1867 cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, bus_space_tag_t memt, 1868 bus_space_handle_t memh) 1869 { 1870 int i; 1871 printf("PCI config regs:"); 1872 for (i = 0; i < 0x50; i += 4) { 1873 if (i % 16 == 0) 1874 printf("\n 0x%02x:", i); 1875 printf(" %08x", pci_conf_read(pc, tag, i)); 1876 } 1877 for (i = 0x80; i < 0xb0; i += 4) { 1878 if (i % 16 == 0) 1879 printf("\n 0x%02x:", i); 1880 printf(" %08x", pci_conf_read(pc, tag, i)); 1881 } 1882 1883 if (memh == 0) { 1884 printf("\n"); 1885 return; 1886 } 1887 1888 printf("\nsocket regs:"); 1889 for (i = 0; i <= 0x10; i += 0x04) 1890 printf(" %08x", bus_space_read_4(memt, memh, i)); 1891 printf("\nExCA regs:"); 1892 for (i = 0; i < 0x08; ++i) 1893 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1894 printf("\n"); 1895 return; 1896 } 1897 #endif 1898 1899 /* 1900 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1901 * int busno, int function) 1902 * This is the function to make a tag to access config space of 1903 * a CardBus Card. It works same as pci_conf_read. 1904 */ 1905 static cardbustag_t 1906 pccbb_make_tag(cardbus_chipset_tag_t cc, int busno, int function) 1907 { 1908 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1909 1910 return pci_make_tag(sc->sc_pc, busno, 0, function); 1911 } 1912 1913 static void 1914 pccbb_free_tag(cardbus_chipset_tag_t cc, cardbustag_t tag) 1915 { 1916 } 1917 1918 /* 1919 * pccbb_conf_read 1920 * 1921 * This is the function to read the config space of a CardBus card. 1922 * It works the same as pci_conf_read(9). 1923 */ 1924 static cardbusreg_t 1925 pccbb_conf_read(cardbus_chipset_tag_t cc, cardbustag_t tag, int offset) 1926 { 1927 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1928 1929 return pci_conf_read(sc->sc_pc, tag, offset); 1930 } 1931 1932 /* 1933 * pccbb_conf_write 1934 * 1935 * This is the function to write the config space of a CardBus 1936 * card. It works the same as pci_conf_write(9). 1937 */ 1938 static void 1939 pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, int reg, 1940 cardbusreg_t val) 1941 { 1942 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1943 1944 pci_conf_write(sc->sc_pc, tag, reg, val); 1945 } 1946 1947 #if 0 1948 STATIC int 1949 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1950 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 1951 int speed, int flags, 1952 bus_space_handle_t * iohp) 1953 #endif 1954 /* 1955 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1956 * bus_addr_t start, bus_size_t size, 1957 * bus_size_t align, 1958 * struct pcmcia_io_handle *pcihp 1959 * 1960 * This function only allocates I/O region for pccard. This function 1961 * never maps the allocated region to pccard I/O area. 1962 * 1963 * XXX: The interface of this function is not very good, I believe. 1964 */ 1965 STATIC int 1966 pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, 1967 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 1968 { 1969 struct pcic_handle *ph = (struct pcic_handle *)pch; 1970 bus_addr_t ioaddr; 1971 int flags = 0; 1972 bus_space_tag_t iot; 1973 bus_space_handle_t ioh; 1974 bus_addr_t mask; 1975 #if rbus 1976 rbus_tag_t rb; 1977 #endif 1978 if (align == 0) { 1979 align = size; /* XXX: funny??? */ 1980 } 1981 1982 if (start != 0) { 1983 /* XXX: assume all card decode lower 10 bits by its hardware */ 1984 mask = 0x3ff; 1985 /* enforce to use only masked address */ 1986 start &= mask; 1987 } else { 1988 /* 1989 * calculate mask: 1990 * 1. get the most significant bit of size (call it msb). 1991 * 2. compare msb with the value of size. 1992 * 3. if size is larger, shift msb left once. 1993 * 4. obtain mask value to decrement msb. 1994 */ 1995 bus_size_t size_tmp = size; 1996 int shifts = 0; 1997 1998 mask = 1; 1999 while (size_tmp) { 2000 ++shifts; 2001 size_tmp >>= 1; 2002 } 2003 mask = (1 << shifts); 2004 if (mask < size) { 2005 mask <<= 1; 2006 } 2007 --mask; 2008 } 2009 2010 /* 2011 * Allocate some arbitrary I/O space. 2012 */ 2013 2014 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 2015 2016 #if rbus 2017 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 2018 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 2019 return 1; 2020 } 2021 DPRINTF(("pccbb_pcmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2022 (u_long) ioaddr, (u_long) size)); 2023 #else 2024 if (start) { 2025 ioaddr = start; 2026 if (bus_space_map(iot, start, size, 0, &ioh)) { 2027 return 1; 2028 } 2029 DPRINTF(("pccbb_pcmcia_io_alloc map port 0x%lx+0x%lx\n", 2030 (u_long) ioaddr, (u_long) size)); 2031 } else { 2032 flags |= PCMCIA_IO_ALLOCATED; 2033 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 2034 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 2035 size, align, 0, 0, &ioaddr, &ioh)) { 2036 /* No room be able to be get. */ 2037 return 1; 2038 } 2039 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2040 (u_long) ioaddr, (u_long) size)); 2041 } 2042 #endif 2043 2044 pcihp->iot = iot; 2045 pcihp->ioh = ioh; 2046 pcihp->addr = ioaddr; 2047 pcihp->size = size; 2048 pcihp->flags = flags; 2049 2050 return 0; 2051 } 2052 2053 /* 2054 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2055 * struct pcmcia_io_handle *pcihp) 2056 * 2057 * This function only frees I/O region for pccard. 2058 * 2059 * XXX: The interface of this function is not very good, I believe. 2060 */ 2061 void 2062 pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2063 struct pcmcia_io_handle *pcihp) 2064 { 2065 #if !rbus 2066 bus_space_tag_t iot = pcihp->iot; 2067 #endif 2068 bus_space_handle_t ioh = pcihp->ioh; 2069 bus_size_t size = pcihp->size; 2070 2071 #if rbus 2072 struct pccbb_softc *sc = 2073 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 2074 rbus_tag_t rb = sc->sc_rbus_iot; 2075 2076 rbus_space_free(rb, ioh, size, NULL); 2077 #else 2078 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 2079 bus_space_free(iot, ioh, size); 2080 else 2081 bus_space_unmap(iot, ioh, size); 2082 #endif 2083 } 2084 2085 /* 2086 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 2087 * bus_addr_t offset, bus_size_t size, 2088 * struct pcmcia_io_handle *pcihp, 2089 * int *windowp) 2090 * 2091 * This function maps the allocated I/O region to pccard. This function 2092 * never allocates any I/O region for pccard I/O area. I don't 2093 * understand why the original authors of pcmciabus separated alloc and 2094 * map. I believe the two must be unite. 2095 * 2096 * XXX: no wait timing control? 2097 */ 2098 int 2099 pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, bus_addr_t offset, 2100 bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp) 2101 { 2102 struct pcic_handle *ph = (struct pcic_handle *)pch; 2103 bus_addr_t ioaddr = pcihp->addr + offset; 2104 int i, win; 2105 #if defined CBB_DEBUG 2106 static const char *width_names[] = { "dynamic", "io8", "io16" }; 2107 #endif 2108 2109 /* Sanity check I/O handle. */ 2110 2111 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 2112 panic("pccbb_pcmcia_io_map iot is bogus"); 2113 } 2114 2115 /* XXX Sanity check offset/size. */ 2116 2117 win = -1; 2118 for (i = 0; i < PCIC_IO_WINS; i++) { 2119 if ((ph->ioalloc & (1 << i)) == 0) { 2120 win = i; 2121 ph->ioalloc |= (1 << i); 2122 break; 2123 } 2124 } 2125 2126 if (win == -1) { 2127 return 1; 2128 } 2129 2130 *windowp = win; 2131 2132 /* XXX this is pretty gross */ 2133 2134 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2135 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2136 2137 /* XXX wtf is this doing here? */ 2138 2139 #if 0 2140 printf(" port 0x%lx", (u_long) ioaddr); 2141 if (size > 1) { 2142 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2143 } 2144 #endif 2145 2146 ph->io[win].addr = ioaddr; 2147 ph->io[win].size = size; 2148 ph->io[win].width = width; 2149 2150 /* actual dirty register-value changing in the function below. */ 2151 pccbb_pcmcia_do_io_map(ph, win); 2152 2153 return 0; 2154 } 2155 2156 /* 2157 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2158 * 2159 * This function changes register-value to map I/O region for pccard. 2160 */ 2161 static void 2162 pccbb_pcmcia_do_io_map(struct pcic_handle *ph, int win) 2163 { 2164 static u_int8_t pcic_iowidth[3] = { 2165 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2166 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2167 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2168 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2169 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2170 }; 2171 2172 #define PCIC_SIA_START_LOW 0 2173 #define PCIC_SIA_START_HIGH 1 2174 #define PCIC_SIA_STOP_LOW 2 2175 #define PCIC_SIA_STOP_HIGH 3 2176 2177 int regbase_win = 0x8 + win * 0x04; 2178 u_int8_t ioctl, enable; 2179 2180 DPRINTF(("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx " 2181 "width %d\n", win, (unsigned long)ph->io[win].addr, 2182 (unsigned long)ph->io[win].size, ph->io[win].width * 8)); 2183 2184 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2185 ph->io[win].addr & 0xff); 2186 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2187 (ph->io[win].addr >> 8) & 0xff); 2188 2189 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2190 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2191 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2192 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2193 2194 ioctl = Pcic_read(ph, PCIC_IOCTL); 2195 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2196 switch (win) { 2197 case 0: 2198 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2199 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2200 PCIC_IOCTL_IO0_DATASIZE_MASK); 2201 ioctl |= pcic_iowidth[ph->io[win].width]; 2202 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2203 break; 2204 case 1: 2205 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2206 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2207 PCIC_IOCTL_IO1_DATASIZE_MASK); 2208 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2209 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2210 break; 2211 } 2212 Pcic_write(ph, PCIC_IOCTL, ioctl); 2213 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2214 #if defined(CBB_DEBUG) 2215 { 2216 u_int8_t start_low = 2217 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2218 u_int8_t start_high = 2219 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2220 u_int8_t stop_low = 2221 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2222 u_int8_t stop_high = 2223 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2224 printf("pccbb_pcmcia_do_io_map start %02x %02x, " 2225 "stop %02x %02x, ioctl %02x enable %02x\n", 2226 start_low, start_high, stop_low, stop_high, ioctl, enable); 2227 } 2228 #endif 2229 } 2230 2231 /* 2232 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2233 * 2234 * This function unmaps I/O region. No return value. 2235 */ 2236 STATIC void 2237 pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t pch, int win) 2238 { 2239 struct pcic_handle *ph = (struct pcic_handle *)pch; 2240 int reg; 2241 2242 if (win >= PCIC_IO_WINS || win < 0) { 2243 panic("pccbb_pcmcia_io_unmap: window out of range"); 2244 } 2245 2246 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2247 switch (win) { 2248 case 0: 2249 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2250 break; 2251 case 1: 2252 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2253 break; 2254 } 2255 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2256 2257 ph->ioalloc &= ~(1 << win); 2258 } 2259 2260 static int 2261 pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 2262 { 2263 u_int8_t stat; 2264 int i; 2265 2266 /* wait an initial 10ms for quick cards */ 2267 stat = Pcic_read(ph, PCIC_IF_STATUS); 2268 if (stat & PCIC_IF_STATUS_READY) 2269 return (0); 2270 pccbb_pcmcia_delay(ph, 10, "pccwr0"); 2271 for (i = 0; i < 50; i++) { 2272 stat = Pcic_read(ph, PCIC_IF_STATUS); 2273 if (stat & PCIC_IF_STATUS_READY) 2274 return (0); 2275 if ((stat & PCIC_IF_STATUS_CARDDETECT_MASK) != 2276 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2277 return (ENXIO); 2278 /* wait .1s (100ms) each iteration now */ 2279 pccbb_pcmcia_delay(ph, 100, "pccwr1"); 2280 } 2281 2282 printf("pccbb_pcmcia_wait_ready: ready never happened, status=%02x\n", stat); 2283 return (EWOULDBLOCK); 2284 } 2285 2286 /* 2287 * Perform long (msec order) delay. timo is in milliseconds. 2288 */ 2289 static void 2290 pccbb_pcmcia_delay(struct pcic_handle *ph, int timo, const char *wmesg) 2291 { 2292 #ifdef DIAGNOSTIC 2293 if (timo <= 0) 2294 panic("pccbb_pcmcia_delay: called with timeout %d", timo); 2295 if (!curlwp) 2296 panic("pccbb_pcmcia_delay: called in interrupt context"); 2297 #if 0 2298 if (!ph->event_thread) 2299 panic("pccbb_pcmcia_delay: no event thread"); 2300 #endif 2301 #endif 2302 DPRINTF(("pccbb_pcmcia_delay: \"%s\" %p, sleep %d ms\n", 2303 wmesg, ph->event_thread, timo)); 2304 tsleep(pccbb_pcmcia_delay, PWAIT, wmesg, roundup(timo * hz, 1000) / 1000); 2305 } 2306 2307 /* 2308 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2309 * 2310 * This function enables the card. All information is stored in 2311 * the first argument, pcmcia_chipset_handle_t. 2312 */ 2313 STATIC void 2314 pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2315 { 2316 struct pcic_handle *ph = (struct pcic_handle *)pch; 2317 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2318 pcireg_t spsr; 2319 int voltage; 2320 int win; 2321 u_int8_t power, intr; 2322 #ifdef DIAGNOSTIC 2323 int reg; 2324 #endif 2325 2326 /* this bit is mostly stolen from pcic_attach_card */ 2327 2328 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2329 2330 /* get card Vcc info */ 2331 spsr = 2332 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2333 CB_SOCKET_STAT); 2334 if (spsr & CB_SOCKET_STAT_5VCARD) { 2335 DPRINTF(("5V card\n")); 2336 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2337 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2338 DPRINTF(("3V card\n")); 2339 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2340 } else { 2341 DPRINTF(("?V card, 0x%x\n", spsr)); /* XXX */ 2342 return; 2343 } 2344 2345 /* disable interrupts; assert RESET */ 2346 intr = Pcic_read(ph, PCIC_INTR); 2347 intr &= PCIC_INTR_ENABLE; 2348 Pcic_write(ph, PCIC_INTR, intr); 2349 2350 /* zero out the address windows */ 2351 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2352 2353 /* power down the socket to reset it, clear the card reset pin */ 2354 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2355 2356 /* power off; assert output enable bit */ 2357 power = PCIC_PWRCTL_OE; 2358 Pcic_write(ph, PCIC_PWRCTL, power); 2359 2360 /* power up the socket */ 2361 if (pccbb_power(sc, voltage) == 0) 2362 return; 2363 2364 /* 2365 * Table 4-18 and figure 4-6 of the PC Card specifiction say: 2366 * Vcc Rising Time (Tpr) = 100ms (handled in pccbb_power() above) 2367 * RESET Width (Th (Hi-z RESET)) = 1ms 2368 * RESET Width (Tw (RESET)) = 10us 2369 * 2370 * some machines require some more time to be settled 2371 * for example old toshiba topic bridges! 2372 * (100ms is added here). 2373 */ 2374 pccbb_pcmcia_delay(ph, 200 + 1, "pccen1"); 2375 2376 /* negate RESET */ 2377 intr |= PCIC_INTR_RESET; 2378 Pcic_write(ph, PCIC_INTR, intr); 2379 2380 /* 2381 * RESET Setup Time (Tsu (RESET)) = 20ms 2382 */ 2383 pccbb_pcmcia_delay(ph, 20, "pccen2"); 2384 2385 #ifdef DIAGNOSTIC 2386 reg = Pcic_read(ph, PCIC_IF_STATUS); 2387 if ((reg & PCIC_IF_STATUS_POWERACTIVE) == 0) 2388 printf("pccbb_pcmcia_socket_enable: no power, status=%x\n", reg); 2389 #endif 2390 2391 /* wait for the chip to finish initializing */ 2392 if (pccbb_pcmcia_wait_ready(ph)) { 2393 #ifdef DIAGNOSTIC 2394 printf("pccbb_pcmcia_socket_enable: never became ready\n"); 2395 #endif 2396 /* XXX return a failure status?? */ 2397 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2398 Pcic_write(ph, PCIC_PWRCTL, 0); 2399 return; 2400 } 2401 2402 /* reinstall all the memory and io mappings */ 2403 for (win = 0; win < PCIC_MEM_WINS; ++win) 2404 if (ph->memalloc & (1 << win)) 2405 pccbb_pcmcia_do_mem_map(ph, win); 2406 for (win = 0; win < PCIC_IO_WINS; ++win) 2407 if (ph->ioalloc & (1 << win)) 2408 pccbb_pcmcia_do_io_map(ph, win); 2409 } 2410 2411 /* 2412 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2413 * 2414 * This function disables the card. All information is stored in 2415 * the first argument, pcmcia_chipset_handle_t. 2416 */ 2417 STATIC void 2418 pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t pch) 2419 { 2420 struct pcic_handle *ph = (struct pcic_handle *)pch; 2421 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2422 u_int8_t intr; 2423 2424 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2425 2426 /* disable interrupts; assert RESET */ 2427 intr = Pcic_read(ph, PCIC_INTR); 2428 intr &= PCIC_INTR_ENABLE; 2429 Pcic_write(ph, PCIC_INTR, intr); 2430 2431 /* zero out the address windows */ 2432 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2433 2434 /* power down the socket to reset it, clear the card reset pin */ 2435 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2436 2437 /* disable socket: negate output enable bit and power off */ 2438 Pcic_write(ph, PCIC_PWRCTL, 0); 2439 2440 /* 2441 * Vcc Falling Time (Tpf) = 300ms 2442 */ 2443 pccbb_pcmcia_delay(ph, 300, "pccwr1"); 2444 } 2445 2446 STATIC void 2447 pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t pch, int type) 2448 { 2449 struct pcic_handle *ph = (struct pcic_handle *)pch; 2450 u_int8_t intr; 2451 2452 /* set the card type */ 2453 2454 intr = Pcic_read(ph, PCIC_INTR); 2455 intr &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_CARDTYPE_MASK); 2456 if (type == PCMCIA_IFTYPE_IO) 2457 intr |= PCIC_INTR_CARDTYPE_IO; 2458 else 2459 intr |= PCIC_INTR_CARDTYPE_MEM; 2460 Pcic_write(ph, PCIC_INTR, intr); 2461 2462 DPRINTF(("%s: pccbb_pcmcia_socket_settype %02x type %s %02x\n", 2463 ph->ph_parent->dv_xname, ph->sock, 2464 ((type == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2465 } 2466 2467 /* 2468 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2469 * 2470 * This function detects whether a card is in the slot or not. 2471 * If a card is inserted, return 1. Otherwise, return 0. 2472 */ 2473 STATIC int 2474 pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch) 2475 { 2476 struct pcic_handle *ph = (struct pcic_handle *)pch; 2477 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2478 2479 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2480 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2481 } 2482 2483 #if 0 2484 STATIC int 2485 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2486 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2487 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2488 #endif 2489 /* 2490 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2491 * bus_size_t size, 2492 * struct pcmcia_mem_handle *pcmhp) 2493 * 2494 * This function only allocates memory region for pccard. This 2495 * function never maps the allocated region to pccard memory area. 2496 * 2497 * XXX: Why the argument of start address is not in? 2498 */ 2499 STATIC int 2500 pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 2501 struct pcmcia_mem_handle *pcmhp) 2502 { 2503 struct pcic_handle *ph = (struct pcic_handle *)pch; 2504 bus_space_handle_t memh; 2505 bus_addr_t addr; 2506 bus_size_t sizepg; 2507 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2508 #if rbus 2509 rbus_tag_t rb; 2510 #endif 2511 2512 /* Check that the card is still there. */ 2513 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2514 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2515 return 1; 2516 2517 /* out of sc->memh, allocate as many pages as necessary */ 2518 2519 /* convert size to PCIC pages */ 2520 /* 2521 * This is not enough; when the requested region is on the page 2522 * boundaries, this may calculate wrong result. 2523 */ 2524 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2525 #if 0 2526 if (sizepg > PCIC_MAX_MEM_PAGES) { 2527 return 1; 2528 } 2529 #endif 2530 2531 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2532 return 1; 2533 } 2534 2535 addr = 0; /* XXX gcc -Wuninitialized */ 2536 2537 #if rbus 2538 rb = sc->sc_rbus_memt; 2539 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2540 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2541 &addr, &memh)) { 2542 return 1; 2543 } 2544 #else 2545 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2546 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2547 0, /* boundary */ 2548 0, /* flags */ 2549 &addr, &memh)) { 2550 return 1; 2551 } 2552 #endif 2553 2554 DPRINTF(("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, " 2555 "realsize 0x%lx\n", (unsigned long)addr, (unsigned long)size, 2556 (unsigned long)sizepg * PCIC_MEM_PAGESIZE)); 2557 2558 pcmhp->memt = sc->sc_memt; 2559 pcmhp->memh = memh; 2560 pcmhp->addr = addr; 2561 pcmhp->size = size; 2562 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2563 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2564 pcmhp->mhandle = 0; 2565 /* No offset??? Funny. */ 2566 2567 return 0; 2568 } 2569 2570 /* 2571 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2572 * struct pcmcia_mem_handle *pcmhp) 2573 * 2574 * This function release the memory space allocated by the function 2575 * pccbb_pcmcia_mem_alloc(). 2576 */ 2577 STATIC void 2578 pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2579 struct pcmcia_mem_handle *pcmhp) 2580 { 2581 #if rbus 2582 struct pcic_handle *ph = (struct pcic_handle *)pch; 2583 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2584 2585 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2586 #else 2587 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2588 #endif 2589 } 2590 2591 /* 2592 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2593 * 2594 * This function release the memory space allocated by the function 2595 * pccbb_pcmcia_mem_alloc(). 2596 */ 2597 STATIC void 2598 pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2599 { 2600 int regbase_win; 2601 bus_addr_t phys_addr; 2602 bus_addr_t phys_end; 2603 2604 #define PCIC_SMM_START_LOW 0 2605 #define PCIC_SMM_START_HIGH 1 2606 #define PCIC_SMM_STOP_LOW 2 2607 #define PCIC_SMM_STOP_HIGH 3 2608 #define PCIC_CMA_LOW 4 2609 #define PCIC_CMA_HIGH 5 2610 2611 u_int8_t start_low, start_high = 0; 2612 u_int8_t stop_low, stop_high; 2613 u_int8_t off_low, off_high; 2614 u_int8_t mem_window; 2615 int reg; 2616 2617 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2618 int mem8 = 2619 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2620 || (kind == PCMCIA_MEM_ATTR); 2621 2622 regbase_win = 0x10 + win * 0x08; 2623 2624 phys_addr = ph->mem[win].addr; 2625 phys_end = phys_addr + ph->mem[win].size; 2626 2627 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2628 (unsigned long)phys_addr, (unsigned long)phys_end, 2629 (unsigned long)ph->mem[win].offset)); 2630 2631 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2632 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2633 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2634 2635 /* bit 19:12 */ 2636 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2637 /* bit 23:20 and bit 7 on */ 2638 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2639 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2640 /* bit 31:24, for 32-bit address */ 2641 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2642 2643 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2644 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2645 2646 if (((struct pccbb_softc *)ph-> 2647 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2648 Pcic_write(ph, 0x40 + win, mem_window); 2649 } 2650 2651 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2652 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2653 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2654 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2655 2656 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2657 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2658 2659 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2660 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2661 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2662 | ((kind == PCMCIA_MEM_ATTR) ? 2663 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2664 2665 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2666 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2667 2668 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2669 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2670 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2671 2672 #if defined(CBB_DEBUG) 2673 { 2674 int r1, r2, r3, r4, r5, r6, r7 = 0; 2675 2676 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2677 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2678 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2679 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2680 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2681 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2682 if (((struct pccbb_softc *)(ph-> 2683 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2684 r7 = Pcic_read(ph, 0x40 + win); 2685 } 2686 2687 printf("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2688 "%02x%02x", win, r1, r2, r3, r4, r5, r6); 2689 if (((struct pccbb_softc *)(ph-> 2690 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2691 printf(" %02x", r7); 2692 } 2693 printf("\n"); 2694 } 2695 #endif 2696 } 2697 2698 /* 2699 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2700 * bus_addr_t card_addr, bus_size_t size, 2701 * struct pcmcia_mem_handle *pcmhp, 2702 * bus_addr_t *offsetp, int *windowp) 2703 * 2704 * This function maps memory space allocated by the function 2705 * pccbb_pcmcia_mem_alloc(). 2706 */ 2707 STATIC int 2708 pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2709 bus_addr_t card_addr, bus_size_t size, struct pcmcia_mem_handle *pcmhp, 2710 bus_addr_t *offsetp, int *windowp) 2711 { 2712 struct pcic_handle *ph = (struct pcic_handle *)pch; 2713 bus_addr_t busaddr; 2714 long card_offset; 2715 int win; 2716 2717 /* Check that the card is still there. */ 2718 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2719 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2720 return 1; 2721 2722 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2723 if ((ph->memalloc & (1 << win)) == 0) { 2724 ph->memalloc |= (1 << win); 2725 break; 2726 } 2727 } 2728 2729 if (win == PCIC_MEM_WINS) { 2730 return 1; 2731 } 2732 2733 *windowp = win; 2734 2735 /* XXX this is pretty gross */ 2736 2737 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2738 panic("pccbb_pcmcia_mem_map memt is bogus"); 2739 } 2740 2741 busaddr = pcmhp->addr; 2742 2743 /* 2744 * compute the address offset to the pcmcia address space for the 2745 * pcic. this is intentionally signed. The masks and shifts below 2746 * will cause TRT to happen in the pcic registers. Deal with making 2747 * sure the address is aligned, and return the alignment offset. 2748 */ 2749 2750 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2751 card_addr -= *offsetp; 2752 2753 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2754 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2755 (u_long) card_addr)); 2756 2757 /* 2758 * include the offset in the size, and decrement size by one, since 2759 * the hw wants start/stop 2760 */ 2761 size += *offsetp - 1; 2762 2763 card_offset = (((long)card_addr) - ((long)busaddr)); 2764 2765 ph->mem[win].addr = busaddr; 2766 ph->mem[win].size = size; 2767 ph->mem[win].offset = card_offset; 2768 ph->mem[win].kind = kind; 2769 2770 pccbb_pcmcia_do_mem_map(ph, win); 2771 2772 return 0; 2773 } 2774 2775 /* 2776 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2777 * int window) 2778 * 2779 * This function unmaps memory space which mapped by the function 2780 * pccbb_pcmcia_mem_map(). 2781 */ 2782 STATIC void 2783 pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, int window) 2784 { 2785 struct pcic_handle *ph = (struct pcic_handle *)pch; 2786 int reg; 2787 2788 if (window >= PCIC_MEM_WINS) { 2789 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2790 } 2791 2792 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2793 reg &= ~(1 << window); 2794 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2795 2796 ph->memalloc &= ~(1 << window); 2797 } 2798 2799 #if defined PCCBB_PCMCIA_POLL 2800 struct pccbb_poll_str { 2801 void *arg; 2802 int (*func)(void *); 2803 int level; 2804 struct pcic_handle *ph; 2805 int count; 2806 int num; 2807 struct callout poll_ch; 2808 }; 2809 2810 static struct pccbb_poll_str pccbb_poll[10]; 2811 static int pccbb_poll_n = 0; 2812 2813 static void pccbb_pcmcia_poll(void *arg); 2814 2815 static void 2816 pccbb_pcmcia_poll(void *arg) 2817 { 2818 struct pccbb_poll_str *poll = arg; 2819 struct pcic_handle *ph = poll->ph; 2820 struct pccbb_softc *sc = ph->sc; 2821 int s; 2822 u_int32_t spsr; /* socket present-state reg */ 2823 2824 callout_reset(&poll->poll_ch, hz * 2, pccbb_pcmcia_poll, arg); 2825 switch (poll->level) { 2826 case IPL_NET: 2827 s = splnet(); 2828 break; 2829 case IPL_BIO: 2830 s = splbio(); 2831 break; 2832 case IPL_TTY: /* fallthrough */ 2833 default: 2834 s = spltty(); 2835 break; 2836 } 2837 2838 spsr = 2839 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2840 CB_SOCKET_STAT); 2841 2842 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2843 if (!(spsr & 0x40)) /* CINT low */ 2844 #else 2845 if (1) 2846 #endif 2847 { 2848 if ((*poll->func) (poll->arg) > 0) { 2849 ++poll->count; 2850 /* printf("intr: reported from poller, 0x%x\n", spsr); */ 2851 #if defined LEVEL2 2852 } else { 2853 printf("intr: miss! 0x%x\n", spsr); 2854 #endif 2855 } 2856 } 2857 splx(s); 2858 } 2859 #endif /* defined CB_PCMCIA_POLL */ 2860 2861 /* 2862 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2863 * struct pcmcia_function *pf, 2864 * int ipl, 2865 * int (*func)(void *), 2866 * void *arg); 2867 * 2868 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2869 */ 2870 STATIC void * 2871 pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2872 struct pcmcia_function *pf, int ipl, int (*func)(void *), void *arg) 2873 { 2874 struct pcic_handle *ph = (struct pcic_handle *)pch; 2875 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2876 2877 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2878 /* what should I do? */ 2879 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2880 DPRINTF(("%s does not provide edge nor pulse " 2881 "interrupt\n", sc->sc_dev.dv_xname)); 2882 return NULL; 2883 } 2884 /* 2885 * XXX Noooooo! The interrupt flag must set properly!! 2886 * dumb pcmcia driver!! 2887 */ 2888 } 2889 2890 return pccbb_intr_establish(sc, 0, ipl, func, arg); 2891 } 2892 2893 /* 2894 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2895 * void *ih) 2896 * 2897 * This function disables PC-Card interrupt. 2898 */ 2899 STATIC void 2900 pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 2901 { 2902 struct pcic_handle *ph = (struct pcic_handle *)pch; 2903 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2904 2905 pccbb_intr_disestablish(sc, ih); 2906 } 2907 2908 #if rbus 2909 /* 2910 * static int 2911 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2912 * bus_addr_t addr, bus_size_t size, 2913 * bus_addr_t mask, bus_size_t align, 2914 * int flags, bus_addr_t *addrp; 2915 * bus_space_handle_t *bshp) 2916 * 2917 * This function allocates a portion of memory or io space for 2918 * clients. This function is called from CardBus card drivers. 2919 */ 2920 static int 2921 pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2922 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 2923 int flags, bus_addr_t *addrp, bus_space_handle_t *bshp) 2924 { 2925 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2926 2927 DPRINTF(("pccbb_rbus_cb_space_alloc: addr 0x%lx, size 0x%lx, " 2928 "mask 0x%lx, align 0x%lx\n", (unsigned long)addr, 2929 (unsigned long)size, (unsigned long)mask, (unsigned long)align)); 2930 2931 if (align == 0) { 2932 align = size; 2933 } 2934 2935 if (rb->rb_bt == sc->sc_memt) { 2936 if (align < 16) { 2937 return 1; 2938 } 2939 /* 2940 * XXX: align more than 0x1000 to avoid overwrapping 2941 * memory windows for two or more devices. 0x1000 2942 * means memory window's granularity. 2943 * 2944 * Two or more devices should be able to share same 2945 * memory window region. However, overrapping memory 2946 * window is not good because some devices, such as 2947 * 3Com 3C575[BC], have a broken address decoder and 2948 * intrude other's memory region. 2949 */ 2950 if (align < 0x1000) { 2951 align = 0x1000; 2952 } 2953 } else if (rb->rb_bt == sc->sc_iot) { 2954 if (align < 4) { 2955 return 1; 2956 } 2957 /* XXX: hack for avoiding ISA image */ 2958 if (mask < 0x0100) { 2959 mask = 0x3ff; 2960 addr = 0x300; 2961 } 2962 2963 } else { 2964 DPRINTF(("pccbb_rbus_cb_space_alloc: Bus space tag 0x%lx is " 2965 "NOT used. io: 0x%lx, mem: 0x%lx\n", 2966 (unsigned long)rb->rb_bt, (unsigned long)sc->sc_iot, 2967 (unsigned long)sc->sc_memt)); 2968 return 1; 2969 /* XXX: panic here? */ 2970 } 2971 2972 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 2973 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 2974 return 1; 2975 } 2976 2977 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 2978 2979 return 0; 2980 } 2981 2982 /* 2983 * static int 2984 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 2985 * bus_space_handle_t *bshp, bus_size_t size); 2986 * 2987 * This function is called from CardBus card drivers. 2988 */ 2989 static int 2990 pccbb_rbus_cb_space_free(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2991 bus_space_handle_t bsh, bus_size_t size) 2992 { 2993 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2994 bus_space_tag_t bt = rb->rb_bt; 2995 2996 pccbb_close_win(sc, bt, bsh, size); 2997 2998 if (bt == sc->sc_memt) { 2999 } else if (bt == sc->sc_iot) { 3000 } else { 3001 return 1; 3002 /* XXX: panic here? */ 3003 } 3004 3005 return rbus_space_free(rb, bsh, size, NULL); 3006 } 3007 #endif /* rbus */ 3008 3009 #if rbus 3010 3011 static int 3012 pccbb_open_win(struct pccbb_softc *sc, bus_space_tag_t bst, bus_addr_t addr, 3013 bus_size_t size, bus_space_handle_t bsh, int flags) 3014 { 3015 struct pccbb_win_chain_head *head; 3016 bus_addr_t align; 3017 3018 head = &sc->sc_iowindow; 3019 align = 0x04; 3020 if (sc->sc_memt == bst) { 3021 head = &sc->sc_memwindow; 3022 align = 0x1000; 3023 DPRINTF(("using memory window, 0x%lx 0x%lx 0x%lx\n\n", 3024 (unsigned long)sc->sc_iot, (unsigned long)sc->sc_memt, 3025 (unsigned long)bst)); 3026 } 3027 3028 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 3029 printf("%s: pccbb_open_win: %s winlist insert failed\n", 3030 sc->sc_dev.dv_xname, 3031 (head == &sc->sc_memwindow) ? "mem" : "io"); 3032 } 3033 pccbb_winset(align, sc, bst); 3034 3035 return 0; 3036 } 3037 3038 static int 3039 pccbb_close_win(struct pccbb_softc *sc, bus_space_tag_t bst, 3040 bus_space_handle_t bsh, bus_size_t size) 3041 { 3042 struct pccbb_win_chain_head *head; 3043 bus_addr_t align; 3044 3045 head = &sc->sc_iowindow; 3046 align = 0x04; 3047 if (sc->sc_memt == bst) { 3048 head = &sc->sc_memwindow; 3049 align = 0x1000; 3050 } 3051 3052 if (pccbb_winlist_delete(head, bsh, size)) { 3053 printf("%s: pccbb_close_win: %s winlist delete failed\n", 3054 sc->sc_dev.dv_xname, 3055 (head == &sc->sc_memwindow) ? "mem" : "io"); 3056 } 3057 pccbb_winset(align, sc, bst); 3058 3059 return 0; 3060 } 3061 3062 static int 3063 pccbb_winlist_insert(struct pccbb_win_chain_head *head, bus_addr_t start, 3064 bus_size_t size, bus_space_handle_t bsh, int flags) 3065 { 3066 struct pccbb_win_chain *chainp, *elem; 3067 3068 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 3069 M_NOWAIT)) == NULL) 3070 return (1); /* fail */ 3071 3072 elem->wc_start = start; 3073 elem->wc_end = start + (size - 1); 3074 elem->wc_handle = bsh; 3075 elem->wc_flags = flags; 3076 3077 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3078 chainp = TAILQ_NEXT(chainp, wc_list)) { 3079 if (chainp->wc_end < start) 3080 continue; 3081 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 3082 return (0); 3083 } 3084 3085 TAILQ_INSERT_TAIL(head, elem, wc_list); 3086 return (0); 3087 } 3088 3089 static int 3090 pccbb_winlist_delete(struct pccbb_win_chain_head *head, bus_space_handle_t bsh, 3091 bus_size_t size) 3092 { 3093 struct pccbb_win_chain *chainp; 3094 3095 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3096 chainp = TAILQ_NEXT(chainp, wc_list)) { 3097 if (memcmp(&chainp->wc_handle, &bsh, sizeof(bsh))) 3098 continue; 3099 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 3100 printf("pccbb_winlist_delete: window 0x%lx size " 3101 "inconsistent: 0x%lx, 0x%lx\n", 3102 (unsigned long)chainp->wc_start, 3103 (unsigned long)(chainp->wc_end - chainp->wc_start), 3104 (unsigned long)(size - 1)); 3105 return 1; 3106 } 3107 3108 TAILQ_REMOVE(head, chainp, wc_list); 3109 free(chainp, M_DEVBUF); 3110 3111 return 0; 3112 } 3113 3114 return 1; /* fail: no candidate to remove */ 3115 } 3116 3117 static void 3118 pccbb_winset(bus_addr_t align, struct pccbb_softc *sc, bus_space_tag_t bst) 3119 { 3120 pci_chipset_tag_t pc; 3121 pcitag_t tag; 3122 bus_addr_t mask = ~(align - 1); 3123 struct { 3124 cardbusreg_t win_start; 3125 cardbusreg_t win_limit; 3126 int win_flags; 3127 } win[2]; 3128 struct pccbb_win_chain *chainp; 3129 int offs; 3130 3131 win[0].win_start = win[1].win_start = 0xffffffff; 3132 win[0].win_limit = win[1].win_limit = 0; 3133 win[0].win_flags = win[1].win_flags = 0; 3134 3135 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3136 offs = 0x2c; 3137 if (sc->sc_memt == bst) { 3138 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3139 offs = 0x1c; 3140 } 3141 3142 if (chainp != NULL) { 3143 win[0].win_start = chainp->wc_start & mask; 3144 win[0].win_limit = chainp->wc_end & mask; 3145 win[0].win_flags = chainp->wc_flags; 3146 chainp = TAILQ_NEXT(chainp, wc_list); 3147 } 3148 3149 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3150 if (win[1].win_start == 0xffffffff) { 3151 /* window 1 is not used */ 3152 if ((win[0].win_flags == chainp->wc_flags) && 3153 (win[0].win_limit + align >= 3154 (chainp->wc_start & mask))) { 3155 /* concatenate */ 3156 win[0].win_limit = chainp->wc_end & mask; 3157 } else { 3158 /* make new window */ 3159 win[1].win_start = chainp->wc_start & mask; 3160 win[1].win_limit = chainp->wc_end & mask; 3161 win[1].win_flags = chainp->wc_flags; 3162 } 3163 continue; 3164 } 3165 3166 /* Both windows are engaged. */ 3167 if (win[0].win_flags == win[1].win_flags) { 3168 /* same flags */ 3169 if (win[0].win_flags == chainp->wc_flags) { 3170 if (win[1].win_start - (win[0].win_limit + 3171 align) < 3172 (chainp->wc_start & mask) - 3173 ((chainp->wc_end & mask) + align)) { 3174 /* 3175 * merge window 0 and 1, and set win1 3176 * to chainp 3177 */ 3178 win[0].win_limit = win[1].win_limit; 3179 win[1].win_start = 3180 chainp->wc_start & mask; 3181 win[1].win_limit = 3182 chainp->wc_end & mask; 3183 } else { 3184 win[1].win_limit = 3185 chainp->wc_end & mask; 3186 } 3187 } else { 3188 /* different flags */ 3189 3190 /* concatenate win0 and win1 */ 3191 win[0].win_limit = win[1].win_limit; 3192 /* allocate win[1] to new space */ 3193 win[1].win_start = chainp->wc_start & mask; 3194 win[1].win_limit = chainp->wc_end & mask; 3195 win[1].win_flags = chainp->wc_flags; 3196 } 3197 } else { 3198 /* the flags of win[0] and win[1] is different */ 3199 if (win[0].win_flags == chainp->wc_flags) { 3200 win[0].win_limit = chainp->wc_end & mask; 3201 /* 3202 * XXX this creates overlapping windows, so 3203 * what should the poor bridge do if one is 3204 * cachable, and the other is not? 3205 */ 3206 printf("%s: overlapping windows\n", 3207 sc->sc_dev.dv_xname); 3208 } else { 3209 win[1].win_limit = chainp->wc_end & mask; 3210 } 3211 } 3212 } 3213 3214 pc = sc->sc_pc; 3215 tag = sc->sc_tag; 3216 pci_conf_write(pc, tag, offs, win[0].win_start); 3217 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3218 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3219 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3220 DPRINTF(("--pccbb_winset: win0 [0x%lx, 0x%lx), win1 [0x%lx, 0x%lx)\n", 3221 (unsigned long)pci_conf_read(pc, tag, offs), 3222 (unsigned long)pci_conf_read(pc, tag, offs + 4) + align, 3223 (unsigned long)pci_conf_read(pc, tag, offs + 8), 3224 (unsigned long)pci_conf_read(pc, tag, offs + 12) + align)); 3225 3226 if (bst == sc->sc_memt) { 3227 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3228 3229 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 3230 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 3231 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3232 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 3233 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3234 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3235 } 3236 } 3237 3238 #endif /* rbus */ 3239 3240 static void 3241 pccbb_powerhook(int why, void *arg) 3242 { 3243 struct pccbb_softc *sc = arg; 3244 pcireg_t reg; 3245 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3246 bus_space_handle_t base_memh = sc->sc_base_memh; 3247 3248 DPRINTF(("%s: power: why %d\n", sc->sc_dev.dv_xname, why)); 3249 3250 if (why == PWR_SUSPEND || why == PWR_STANDBY) { 3251 DPRINTF(("%s: power: why %d stopping intr\n", 3252 sc->sc_dev.dv_xname, why)); 3253 if (sc->sc_pil_intr_enable) { 3254 (void)pccbbintr_function(sc); 3255 } 3256 sc->sc_pil_intr_enable = 0; 3257 3258 pci_conf_capture(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf); 3259 3260 if (sc->sc_chipset == CB_RX5C47X) 3261 sc->sc_ricoh_misc_ctrl = pci_conf_read(sc->sc_pc, 3262 sc->sc_tag, 3263 RICOH_PCI_MISC_CTRL); 3264 3265 /* ToDo: deactivate or suspend child devices */ 3266 } 3267 3268 if (why == PWR_RESUME) { 3269 if (sc->sc_pwrmgt_offs != 0) { 3270 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, 3271 sc->sc_pwrmgt_offs + PCI_PMCSR); 3272 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 3273 reg & PCI_PMCSR_PME_EN) { 3274 /* powrstate != D0 */ 3275 3276 printf("%s going back to D0 mode\n", 3277 sc->sc_dev.dv_xname); 3278 reg &= ~PCI_PMCSR_STATE_MASK; 3279 reg |= PCI_PMCSR_STATE_D0; 3280 reg &= ~PCI_PMCSR_PME_EN; 3281 pci_conf_write(sc->sc_pc, sc->sc_tag, 3282 sc->sc_pwrmgt_offs + PCI_PMCSR, reg); 3283 3284 pci_conf_write(sc->sc_pc, sc->sc_tag, 3285 PCI_SOCKBASE, sc->sc_sockbase); 3286 pci_conf_write(sc->sc_pc, sc->sc_tag, 3287 PCI_BUSNUM, sc->sc_busnum); 3288 pccbb_chipinit(sc); 3289 /* setup memory and io space window for CB */ 3290 pccbb_winset(0x1000, sc, sc->sc_memt); 3291 pccbb_winset(0x04, sc, sc->sc_iot); 3292 goto norestore; 3293 } 3294 } 3295 3296 norestore: 3297 pci_conf_restore(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf); 3298 if (sc->sc_chipset == CB_RX5C47X) { 3299 pci_conf_write(sc->sc_pc, sc->sc_tag, 3300 RICOH_PCI_MISC_CTRL, sc->sc_ricoh_misc_ctrl); 3301 } 3302 3303 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_SOCKBASE) == 0) 3304 /* BIOS did not recover this register */ 3305 pci_conf_write (sc->sc_pc, sc->sc_tag, 3306 PCI_SOCKBASE, sc->sc_sockbase); 3307 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_BUSNUM) == 0) 3308 /* BIOS did not recover this register */ 3309 pci_conf_write (sc->sc_pc, sc->sc_tag, 3310 PCI_BUSNUM, sc->sc_busnum); 3311 /* CSC Interrupt: Card detect interrupt on */ 3312 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3313 /* Card detect intr is turned on. */ 3314 reg |= CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; 3315 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3316 /* reset interrupt */ 3317 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3318 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3319 3320 /* 3321 * check for card insertion or removal during suspend period. 3322 * XXX: the code can't cope with card swap (remove then 3323 * insert). how can we detect such situation? 3324 */ 3325 (void)pccbbintr(sc); 3326 3327 sc->sc_pil_intr_enable = 1; 3328 DPRINTF(("%s: power: RESUME enabling intr\n", 3329 sc->sc_dev.dv_xname)); 3330 3331 /* ToDo: activate or wakeup child devices */ 3332 } 3333 } 3334
Indexes created Thu Sep 25 16:09:42 GMT 2025