pccbb.c revision 1.145.6.4
1 /* $NetBSD: pccbb.c,v 1.145.6.4 2007/11/06 14:27:27 joerg Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: pccbb.c,v 1.145.6.4 2007/11/06 14:27:27 joerg Exp $"); 35 36 /* 37 #define CBB_DEBUG 38 #define SHOW_REGS 39 */ 40 41 /* 42 * BROKEN! 43 #define PCCBB_PCMCIA_POLL 44 #define CB_PCMCIA_POLL 45 #define CB_PCMCIA_POLL_ONLY 46 #define LEVEL2 47 */ 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/kernel.h> 52 #include <sys/errno.h> 53 #include <sys/ioctl.h> 54 #include <sys/reboot.h> /* for bootverbose */ 55 #include <sys/syslog.h> 56 #include <sys/device.h> 57 #include <sys/malloc.h> 58 #include <sys/proc.h> 59 60 #include <sys/intr.h> 61 #include <sys/bus.h> 62 63 #include <dev/pci/pcivar.h> 64 #include <dev/pci/pcireg.h> 65 #include <dev/pci/pcidevs.h> 66 67 #include <dev/pci/pccbbreg.h> 68 69 #include <dev/cardbus/cardslotvar.h> 70 71 #include <dev/cardbus/cardbusvar.h> 72 73 #include <dev/pcmcia/pcmciareg.h> 74 #include <dev/pcmcia/pcmciavar.h> 75 76 #include <dev/ic/i82365reg.h> 77 #include <dev/ic/i82365var.h> 78 #include <dev/pci/pccbbvar.h> 79 80 #include "locators.h" 81 82 #ifndef __NetBSD_Version__ 83 struct cfdriver cbb_cd = { 84 NULL, "cbb", DV_DULL 85 }; 86 #endif 87 88 #ifdef CBB_DEBUG 89 #define DPRINTF(x) printf x 90 #define STATIC 91 #else 92 #define DPRINTF(x) 93 #define STATIC static 94 #endif 95 96 /* 97 * delay_ms() is wait in milliseconds. It should be used instead 98 * of delay() if you want to wait more than 1 ms. 99 */ 100 static inline void 101 delay_ms(int millis, void *param) 102 { 103 if (cold) 104 delay(millis * 1000); 105 else 106 tsleep(param, PWAIT, "pccbb", MAX(2, hz * millis / 1000)); 107 } 108 109 int pcicbbmatch(struct device *, struct cfdata *, void *); 110 void pccbbattach(struct device *, struct device *, void *); 111 int pccbbintr(void *); 112 static void pci113x_insert(void *); 113 static int pccbbintr_function(struct pccbb_softc *); 114 115 static int pccbb_detect_card(struct pccbb_softc *); 116 117 static void pccbb_pcmcia_write(struct pcic_handle *, int, u_int8_t); 118 static u_int8_t pccbb_pcmcia_read(struct pcic_handle *, int); 119 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 120 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 121 122 STATIC int cb_reset(struct pccbb_softc *); 123 STATIC int cb_detect_voltage(struct pccbb_softc *); 124 STATIC int cbbprint(void *, const char *); 125 126 static int cb_chipset(u_int32_t, int *); 127 STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *, 128 struct pcmciabus_attach_args *); 129 #if 0 130 STATIC void pccbb_pcmcia_attach_card(struct pcic_handle *); 131 STATIC void pccbb_pcmcia_detach_card(struct pcic_handle *, int); 132 STATIC void pccbb_pcmcia_deactivate_card(struct pcic_handle *); 133 #endif 134 135 STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int); 136 STATIC int pccbb_power(cardbus_chipset_tag_t, int); 137 STATIC int pccbb_cardenable(struct pccbb_softc * sc, int function); 138 #if !rbus 139 static int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 140 static int pccbb_io_close(cardbus_chipset_tag_t, int); 141 static int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 142 static int pccbb_mem_close(cardbus_chipset_tag_t, int); 143 #endif /* !rbus */ 144 static void *pccbb_intr_establish(struct pccbb_softc *, int irq, 145 int level, int (*ih) (void *), void *sc); 146 static void pccbb_intr_disestablish(struct pccbb_softc *, void *ih); 147 148 static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t, int irq, 149 int level, int (*ih) (void *), void *sc); 150 static void pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih); 151 152 static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t, int, int); 153 static void pccbb_free_tag(cardbus_chipset_tag_t, cardbustag_t); 154 static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t, cardbustag_t, int); 155 static void pccbb_conf_write(cardbus_chipset_tag_t, cardbustag_t, int, 156 cardbusreg_t); 157 static void pccbb_chipinit(struct pccbb_softc *); 158 159 STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 160 struct pcmcia_mem_handle *); 161 STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t, 162 struct pcmcia_mem_handle *); 163 STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 164 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *); 165 STATIC void pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t, int); 166 STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 167 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 168 STATIC void pccbb_pcmcia_io_free(pcmcia_chipset_handle_t, 169 struct pcmcia_io_handle *); 170 STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 171 bus_size_t, struct pcmcia_io_handle *, int *); 172 STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t, int); 173 STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t, 174 struct pcmcia_function *, int, int (*)(void *), void *); 175 STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t, void *); 176 STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t); 177 STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t); 178 STATIC void pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t, int); 179 STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch); 180 181 static int pccbb_pcmcia_wait_ready(struct pcic_handle *); 182 static void pccbb_pcmcia_delay(struct pcic_handle *, int, const char *); 183 184 static void pccbb_pcmcia_do_io_map(struct pcic_handle *, int); 185 static void pccbb_pcmcia_do_mem_map(struct pcic_handle *, int); 186 187 /* bus-space allocation and deallocation functions */ 188 #if rbus 189 190 static int pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t, rbus_tag_t, 191 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 192 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp); 193 static int pccbb_rbus_cb_space_free(cardbus_chipset_tag_t, rbus_tag_t, 194 bus_space_handle_t, bus_size_t); 195 196 #endif /* rbus */ 197 198 #if rbus 199 200 static int pccbb_open_win(struct pccbb_softc *, bus_space_tag_t, 201 bus_addr_t, bus_size_t, bus_space_handle_t, int flags); 202 static int pccbb_close_win(struct pccbb_softc *, bus_space_tag_t, 203 bus_space_handle_t, bus_size_t); 204 static int pccbb_winlist_insert(struct pccbb_win_chain_head *, bus_addr_t, 205 bus_size_t, bus_space_handle_t, int); 206 static int pccbb_winlist_delete(struct pccbb_win_chain_head *, 207 bus_space_handle_t, bus_size_t); 208 static void pccbb_winset(bus_addr_t align, struct pccbb_softc *, 209 bus_space_tag_t); 210 void pccbb_winlist_show(struct pccbb_win_chain *); 211 212 #endif /* rbus */ 213 214 /* for config_defer */ 215 static void pccbb_pci_callback(struct device *); 216 217 static bool pccbb_suspend(device_t); 218 static bool pccbb_resume(device_t); 219 220 #if defined SHOW_REGS 221 static void cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, 222 bus_space_tag_t memt, bus_space_handle_t memh); 223 #endif 224 225 CFATTACH_DECL(cbb_pci, sizeof(struct pccbb_softc), 226 pcicbbmatch, pccbbattach, NULL, NULL); 227 228 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 229 pccbb_pcmcia_mem_alloc, 230 pccbb_pcmcia_mem_free, 231 pccbb_pcmcia_mem_map, 232 pccbb_pcmcia_mem_unmap, 233 pccbb_pcmcia_io_alloc, 234 pccbb_pcmcia_io_free, 235 pccbb_pcmcia_io_map, 236 pccbb_pcmcia_io_unmap, 237 pccbb_pcmcia_intr_establish, 238 pccbb_pcmcia_intr_disestablish, 239 pccbb_pcmcia_socket_enable, 240 pccbb_pcmcia_socket_disable, 241 pccbb_pcmcia_socket_settype, 242 pccbb_pcmcia_card_detect 243 }; 244 245 #if rbus 246 static struct cardbus_functions pccbb_funcs = { 247 pccbb_rbus_cb_space_alloc, 248 pccbb_rbus_cb_space_free, 249 pccbb_cb_intr_establish, 250 pccbb_cb_intr_disestablish, 251 pccbb_ctrl, 252 pccbb_power, 253 pccbb_make_tag, 254 pccbb_free_tag, 255 pccbb_conf_read, 256 pccbb_conf_write, 257 }; 258 #else 259 static struct cardbus_functions pccbb_funcs = { 260 pccbb_ctrl, 261 pccbb_power, 262 pccbb_mem_open, 263 pccbb_mem_close, 264 pccbb_io_open, 265 pccbb_io_close, 266 pccbb_cb_intr_establish, 267 pccbb_cb_intr_disestablish, 268 pccbb_make_tag, 269 pccbb_conf_read, 270 pccbb_conf_write, 271 }; 272 #endif 273 274 int 275 pcicbbmatch(struct device *parent, struct cfdata *match, void *aux) 276 { 277 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 278 279 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 280 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 281 PCI_INTERFACE(pa->pa_class) == 0) { 282 return 1; 283 } 284 285 return 0; 286 } 287 288 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 289 | ((prod) << PCI_PRODUCT_SHIFT)) 290 291 const struct yenta_chipinfo { 292 pcireg_t yc_id; /* vendor tag | product tag */ 293 int yc_chiptype; 294 int yc_flags; 295 } yc_chipsets[] = { 296 /* Texas Instruments chips */ 297 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 298 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 299 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 300 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 301 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI125X, 302 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 303 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 304 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 305 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 306 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 307 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 308 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 309 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI125X, 310 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 311 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI125X, 312 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 313 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 314 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 315 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 316 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 317 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 318 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 319 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI125X, 320 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 321 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 322 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 323 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1520), CB_TI12XX, 324 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 325 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4410YENTA), CB_TI12XX, 326 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 327 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4520YENTA), CB_TI12XX, 328 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 329 330 /* Ricoh chips */ 331 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 332 PCCBB_PCMCIA_MEM_32}, 333 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 334 PCCBB_PCMCIA_MEM_32}, 335 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 336 PCCBB_PCMCIA_MEM_32}, 337 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 338 PCCBB_PCMCIA_MEM_32}, 339 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 340 PCCBB_PCMCIA_MEM_32}, 341 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 342 PCCBB_PCMCIA_MEM_32}, 343 344 /* Toshiba products */ 345 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 346 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 347 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 348 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 349 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 350 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 351 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 352 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 353 354 /* Cirrus Logic products */ 355 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 356 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 357 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 358 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 359 360 /* sentinel, or Generic chip */ 361 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 362 }; 363 364 static int 365 cb_chipset(u_int32_t pci_id, int *flagp) 366 { 367 const struct yenta_chipinfo *yc; 368 369 /* Loop over except the last default entry. */ 370 for (yc = yc_chipsets; yc < yc_chipsets + 371 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 372 if (pci_id == yc->yc_id) 373 break; 374 375 if (flagp != NULL) 376 *flagp = yc->yc_flags; 377 378 return (yc->yc_chiptype); 379 } 380 381 void 382 pccbbattach(struct device *parent, struct device *self, void *aux) 383 { 384 struct pccbb_softc *sc = (void *)self; 385 struct pci_attach_args *pa = aux; 386 pci_chipset_tag_t pc = pa->pa_pc; 387 pcireg_t busreg, reg, sock_base; 388 bus_addr_t sockbase; 389 char devinfo[256]; 390 int flags; 391 392 #ifdef __HAVE_PCCBB_ATTACH_HOOK 393 pccbb_attach_hook(parent, self, pa); 394 #endif 395 396 callout_init(&sc->sc_insert_ch, 0); 397 callout_setfunc(&sc->sc_insert_ch, pci113x_insert, sc); 398 399 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 400 401 pci_devinfo(pa->pa_id, 0, 0, devinfo, sizeof(devinfo)); 402 printf(": %s (rev. 0x%02x)", devinfo, PCI_REVISION(pa->pa_class)); 403 DPRINTF((" (chipflags %x)", flags)); 404 printf("\n"); 405 406 TAILQ_INIT(&sc->sc_memwindow); 407 TAILQ_INIT(&sc->sc_iowindow); 408 409 #if rbus 410 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 411 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 412 413 #if 0 414 printf("pa->pa_memt: %08x vs rbus_mem->rb_bt: %08x\n", 415 pa->pa_memt, sc->sc_rbus_memt->rb_bt); 416 #endif 417 #endif /* rbus */ 418 419 sc->sc_flags &= ~CBB_MEMHMAPPED; 420 421 /* 422 * MAP socket registers and ExCA registers on memory-space 423 * When no valid address is set on socket base registers (on pci 424 * config space), get it not polite way. 425 */ 426 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 427 428 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 429 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 430 /* The address must be valid. */ 431 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 432 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL)) { 433 printf("%s: can't map socket base address 0x%lx\n", 434 sc->sc_dev.dv_xname, (unsigned long)sock_base); 435 /* 436 * I think it's funny: socket base registers must be 437 * mapped on memory space, but ... 438 */ 439 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 440 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 441 NULL)) { 442 printf("%s: can't map socket base address" 443 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 444 (unsigned long)sockbase); 445 /* give up... allocate reg space via rbus. */ 446 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 447 } else 448 sc->sc_flags |= CBB_MEMHMAPPED; 449 } else { 450 DPRINTF(("%s: socket base address 0x%lx\n", 451 sc->sc_dev.dv_xname, (unsigned long)sockbase)); 452 sc->sc_flags |= CBB_MEMHMAPPED; 453 } 454 } 455 456 sc->sc_mem_start = 0; /* XXX */ 457 sc->sc_mem_end = 0xffffffff; /* XXX */ 458 459 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 460 461 /* pccbb_machdep.c end */ 462 463 #if defined CBB_DEBUG 464 { 465 static const char *intrname[] = { "NON", "A", "B", "C", "D" }; 466 printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname, 467 intrname[pa->pa_intrpin], pa->pa_intrline); 468 } 469 #endif 470 471 /* setup softc */ 472 sc->sc_pc = pc; 473 sc->sc_iot = pa->pa_iot; 474 sc->sc_memt = pa->pa_memt; 475 sc->sc_dmat = pa->pa_dmat; 476 sc->sc_tag = pa->pa_tag; 477 sc->sc_function = pa->pa_function; 478 479 memcpy(&sc->sc_pa, pa, sizeof(*pa)); 480 481 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 482 483 /* Disable legacy register mapping. */ 484 switch (sc->sc_chipset) { 485 case CB_RX5C46X: /* fallthrough */ 486 #if 0 487 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 488 case CB_RX5C47X: 489 #endif 490 /* 491 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 492 * cannot be disabled by substituting 0 into PCI_LEGACY 493 * register. Ricoh CardBus bridges have special bits on Bridge 494 * control reg (addr 0x3e on PCI config space). 495 */ 496 reg = pci_conf_read(pc, pa->pa_tag, PCI_BRIDGE_CONTROL_REG); 497 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 498 pci_conf_write(pc, pa->pa_tag, PCI_BRIDGE_CONTROL_REG, reg); 499 break; 500 501 default: 502 /* XXX I don't know proper way to kill legacy I/O. */ 503 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 504 break; 505 } 506 507 if (!pnp_device_register(self, pccbb_suspend, pccbb_resume)) 508 aprint_error_dev(self, "couldn't establish power handler\n"); 509 510 config_defer(self, pccbb_pci_callback); 511 } 512 513 514 515 516 /* 517 * static void pccbb_pci_callback(struct device *self) 518 * 519 * The actual attach routine: get memory space for YENTA register 520 * space, setup YENTA register and route interrupt. 521 * 522 * This function should be deferred because this device may obtain 523 * memory space dynamically. This function must avoid obtaining 524 * memory area which has already kept for another device. 525 */ 526 static void 527 pccbb_pci_callback(struct device *self) 528 { 529 struct pccbb_softc *sc = (void *)self; 530 pci_chipset_tag_t pc = sc->sc_pc; 531 pci_intr_handle_t ih; 532 const char *intrstr = NULL; 533 bus_addr_t sockbase; 534 struct cbslot_attach_args cba; 535 struct pcmciabus_attach_args paa; 536 struct cardslot_attach_args caa; 537 struct cardslot_softc *csc; 538 539 if (!(sc->sc_flags & CBB_MEMHMAPPED)) { 540 /* The socket registers aren't mapped correctly. */ 541 #if rbus 542 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 543 (sc->sc_chipset == CB_RX5C47X 544 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 545 0, &sockbase, &sc->sc_base_memh)) { 546 return; 547 } 548 sc->sc_base_memt = sc->sc_memt; 549 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 550 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 551 sc->sc_dev.dv_xname, (unsigned long)sockbase, 552 (unsigned long)pci_conf_read(pc, sc->sc_tag, 553 PCI_SOCKBASE))); 554 #else 555 sc->sc_base_memt = sc->sc_memt; 556 #if !defined CBB_PCI_BASE 557 #define CBB_PCI_BASE 0x20000000 558 #endif 559 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 560 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 561 /* cannot allocate memory space */ 562 return; 563 } 564 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 565 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 566 sc->sc_dev.dv_xname, (unsigned long)sock_base, 567 (unsigned long)pci_conf_read(pc, 568 sc->sc_tag, PCI_SOCKBASE))); 569 #endif 570 sc->sc_flags |= CBB_MEMHMAPPED; 571 } 572 573 /* bus bridge initialization */ 574 pccbb_chipinit(sc); 575 576 /* clear data structure for child device interrupt handlers */ 577 LIST_INIT(&sc->sc_pil); 578 sc->sc_pil_intr_enable = 1; 579 580 /* Map and establish the interrupt. */ 581 if (pci_intr_map(&sc->sc_pa, &ih)) { 582 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 583 return; 584 } 585 intrstr = pci_intr_string(pc, ih); 586 587 /* 588 * XXX pccbbintr should be called under the priority lower 589 * than any other hard interupts. 590 */ 591 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 592 593 if (sc->sc_ih == NULL) { 594 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 595 if (intrstr != NULL) { 596 printf(" at %s", intrstr); 597 } 598 printf("\n"); 599 return; 600 } 601 602 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 603 604 { 605 u_int32_t sockstat; 606 607 sockstat = bus_space_read_4(sc->sc_base_memt, 608 sc->sc_base_memh, CB_SOCKET_STAT); 609 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 610 sc->sc_flags |= CBB_CARDEXIST; 611 } 612 } 613 614 /* 615 * attach cardbus 616 */ 617 { 618 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 619 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 620 621 /* initialize cbslot_attach */ 622 cba.cba_busname = "cardbus"; 623 cba.cba_iot = sc->sc_iot; 624 cba.cba_memt = sc->sc_memt; 625 cba.cba_dmat = sc->sc_dmat; 626 cba.cba_bus = (busreg >> 8) & 0x0ff; 627 cba.cba_cc = (void *)sc; 628 cba.cba_cf = &pccbb_funcs; 629 cba.cba_intrline = sc->sc_pa.pa_intrline; 630 631 #if rbus 632 cba.cba_rbus_iot = sc->sc_rbus_iot; 633 cba.cba_rbus_memt = sc->sc_rbus_memt; 634 #endif 635 636 cba.cba_cacheline = PCI_CACHELINE(bhlc); 637 cba.cba_lattimer = PCI_LATTIMER(bhlc); 638 639 if (bootverbose) { 640 printf("%s: cacheline 0x%x lattimer 0x%x\n", 641 sc->sc_dev.dv_xname, cba.cba_cacheline, 642 cba.cba_lattimer); 643 printf("%s: bhlc 0x%x\n", 644 device_xname(&sc->sc_dev), bhlc); 645 } 646 #if defined SHOW_REGS 647 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 648 sc->sc_base_memh); 649 #endif 650 } 651 652 pccbb_pcmcia_attach_setup(sc, &paa); 653 caa.caa_cb_attach = NULL; 654 if (cba.cba_bus == 0) 655 printf("%s: secondary bus number uninitialized; try PCI_BUS_FIXUP\n", sc->sc_dev.dv_xname); 656 else 657 caa.caa_cb_attach = &cba; 658 caa.caa_16_attach = &paa; 659 caa.caa_ph = &sc->sc_pcmcia_h; 660 661 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 662 DPRINTF(("%s: found cardslot\n", __func__)); 663 sc->sc_csc = csc; 664 } 665 666 return; 667 } 668 669 670 671 672 673 /* 674 * static void pccbb_chipinit(struct pccbb_softc *sc) 675 * 676 * This function initialize YENTA chip registers listed below: 677 * 1) PCI command reg, 678 * 2) PCI and CardBus latency timer, 679 * 3) route PCI interrupt, 680 * 4) close all memory and io windows. 681 * 5) turn off bus power. 682 * 6) card detect and power cycle interrupts on. 683 * 7) clear interrupt 684 */ 685 static void 686 pccbb_chipinit(struct pccbb_softc *sc) 687 { 688 pci_chipset_tag_t pc = sc->sc_pc; 689 pcitag_t tag = sc->sc_tag; 690 bus_space_tag_t bmt = sc->sc_base_memt; 691 bus_space_handle_t bmh = sc->sc_base_memh; 692 pcireg_t bcr, bhlc, cbctl, csr, lscp, mfunc, slotctl, sockctl, sockmask, 693 sysctrl; 694 695 /* 696 * Set PCI command reg. 697 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 698 */ 699 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 700 /* I believe it is harmless. */ 701 csr |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 702 PCI_COMMAND_MASTER_ENABLE); 703 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 704 705 /* 706 * Set CardBus latency timer. 707 */ 708 lscp = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 709 if (PCI_CB_LATENCY(lscp) < 0x20) { 710 lscp &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 711 lscp |= (0x20 << PCI_CB_LATENCY_SHIFT); 712 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, lscp); 713 } 714 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 715 PCI_CB_LATENCY(lscp), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 716 717 /* 718 * Set PCI latency timer. 719 */ 720 bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG); 721 if (PCI_LATTIMER(bhlc) < 0x10) { 722 bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 723 bhlc |= (0x10 << PCI_LATTIMER_SHIFT); 724 pci_conf_write(pc, tag, PCI_BHLC_REG, bhlc); 725 } 726 DPRINTF(("PCI latency timer 0x%x (%x)\n", 727 PCI_LATTIMER(bhlc), pci_conf_read(pc, tag, PCI_BHLC_REG))); 728 729 730 /* Route functional interrupts to PCI. */ 731 bcr = pci_conf_read(pc, tag, PCI_BRIDGE_CONTROL_REG); 732 bcr |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 733 bcr |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 734 /* assert reset */ 735 bcr |= PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT; 736 pci_conf_write(pc, tag, PCI_BRIDGE_CONTROL_REG, bcr); 737 738 switch (sc->sc_chipset) { 739 case CB_TI113X: 740 cbctl = pci_conf_read(pc, tag, PCI_CBCTRL); 741 /* This bit is shared, but may read as 0 on some chips, so set 742 it explicitly on both functions. */ 743 cbctl |= PCI113X_CBCTRL_PCI_IRQ_ENA; 744 /* CSC intr enable */ 745 cbctl |= PCI113X_CBCTRL_PCI_CSC; 746 /* functional intr prohibit | prohibit ISA routing */ 747 cbctl &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 748 pci_conf_write(pc, tag, PCI_CBCTRL, cbctl); 749 break; 750 751 case CB_TI12XX: 752 /* 753 * Some TI 12xx (and [14][45]xx) based pci cards 754 * sometimes have issues with the MFUNC register not 755 * being initialized due to a bad EEPROM on board. 756 * Laptops that this matters on have this register 757 * properly initialized. 758 * 759 * The TI125X parts have a different register. 760 */ 761 mfunc = pci_conf_read(pc, tag, PCI12XX_MFUNC); 762 if (mfunc == 0) { 763 mfunc &= ~PCI12XX_MFUNC_PIN0; 764 mfunc |= PCI12XX_MFUNC_PIN0_INTA; 765 if ((pci_conf_read(pc, tag, PCI_SYSCTRL) & 766 PCI12XX_SYSCTRL_INTRTIE) == 0) { 767 mfunc &= ~PCI12XX_MFUNC_PIN1; 768 mfunc |= PCI12XX_MFUNC_PIN1_INTB; 769 } 770 pci_conf_write(pc, tag, PCI12XX_MFUNC, mfunc); 771 } 772 /* fallthrough */ 773 774 case CB_TI125X: 775 /* 776 * Disable zoom video. Some machines initialize this 777 * improperly and experience has shown that this helps 778 * prevent strange behavior. 779 */ 780 pci_conf_write(pc, tag, PCI12XX_MMCTRL, 0); 781 782 sysctrl = pci_conf_read(pc, tag, PCI_SYSCTRL); 783 sysctrl |= PCI12XX_SYSCTRL_VCCPROT; 784 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 785 cbctl = pci_conf_read(pc, tag, PCI_CBCTRL); 786 cbctl |= PCI12XX_CBCTRL_CSC; 787 pci_conf_write(pc, tag, PCI_CBCTRL, cbctl); 788 break; 789 790 case CB_TOPIC95B: 791 sockctl = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 792 sockctl |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 793 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, sockctl); 794 slotctl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 795 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 796 sc->sc_dev.dv_xname, slotctl)); 797 slotctl |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 798 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 799 slotctl &= ~TOPIC_SLOT_CTRL_SWDETECT; 800 DPRINTF(("0x%x\n", slotctl)); 801 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slotctl); 802 break; 803 804 case CB_TOPIC97: 805 slotctl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 806 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 807 sc->sc_dev.dv_xname, slotctl)); 808 slotctl |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 809 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 810 slotctl &= ~TOPIC_SLOT_CTRL_SWDETECT; 811 slotctl |= TOPIC97_SLOT_CTRL_PCIINT; 812 slotctl &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 813 DPRINTF(("0x%x\n", slotctl)); 814 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slotctl); 815 /* make sure to assert LV card support bits */ 816 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 817 0x800 + 0x3e, 818 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 819 0x800 + 0x3e) | 0x03); 820 break; 821 } 822 823 /* Close all memory and I/O windows. */ 824 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 825 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 826 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 827 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 828 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 829 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 830 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 831 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 832 833 /* reset 16-bit pcmcia bus */ 834 bus_space_write_1(bmt, bmh, 0x800 + PCIC_INTR, 835 bus_space_read_1(bmt, bmh, 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 836 837 /* turn off power */ 838 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 839 840 /* CSC Interrupt: Card detect and power cycle interrupts on */ 841 sockmask = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 842 sockmask |= CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; 843 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, sockmask); 844 /* reset interrupt */ 845 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 846 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 847 } 848 849 850 851 852 /* 853 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 854 * struct pcmciabus_attach_args *paa) 855 * 856 * This function attaches 16-bit PCcard bus. 857 */ 858 STATIC void 859 pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 860 struct pcmciabus_attach_args *paa) 861 { 862 struct pcic_handle *ph = &sc->sc_pcmcia_h; 863 #if rbus 864 rbus_tag_t rb; 865 #endif 866 867 /* initialize pcmcia part in pccbb_softc */ 868 ph->ph_parent = (struct device *)sc; 869 ph->sock = sc->sc_function; 870 ph->flags = 0; 871 ph->shutdown = 0; 872 ph->ih_irq = sc->sc_pa.pa_intrline; 873 ph->ph_bus_t = sc->sc_base_memt; 874 ph->ph_bus_h = sc->sc_base_memh; 875 ph->ph_read = pccbb_pcmcia_read; 876 ph->ph_write = pccbb_pcmcia_write; 877 sc->sc_pct = &pccbb_pcmcia_funcs; 878 879 /* 880 * We need to do a few things here: 881 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 882 * setting the IRQ numbers to 0. 883 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 884 * routing of CSC interrupts (e.g. card removal) to PCI while in 885 * PCMCIA mode. We just leave this set all the time. 886 * 3) Enable card insertion/removal interrupts in case the chip also 887 * needs that while in PCMCIA mode. 888 * 4) Clear any pending CSC interrupt. 889 */ 890 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE); 891 if (sc->sc_chipset == CB_TI113X) { 892 Pcic_write(ph, PCIC_CSC_INTR, 0); 893 } else { 894 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 895 Pcic_read(ph, PCIC_CSC); 896 } 897 898 /* initialize pcmcia bus attachment */ 899 paa->paa_busname = "pcmcia"; 900 paa->pct = sc->sc_pct; 901 paa->pch = ph; 902 paa->iobase = 0; /* I don't use them */ 903 paa->iosize = 0; 904 #if rbus 905 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 906 paa->iobase = rb->rb_start + rb->rb_offset; 907 paa->iosize = rb->rb_end - rb->rb_start; 908 #endif 909 910 return; 911 } 912 913 #if 0 914 STATIC void 915 pccbb_pcmcia_attach_card(struct pcic_handle *ph) 916 { 917 if (ph->flags & PCIC_FLAG_CARDP) { 918 panic("pccbb_pcmcia_attach_card: already attached"); 919 } 920 921 /* call the MI attach function */ 922 pcmcia_card_attach(ph->pcmcia); 923 924 ph->flags |= PCIC_FLAG_CARDP; 925 } 926 927 STATIC void 928 pccbb_pcmcia_detach_card(struct pcic_handle *ph, int flags) 929 { 930 if (!(ph->flags & PCIC_FLAG_CARDP)) { 931 panic("pccbb_pcmcia_detach_card: already detached"); 932 } 933 934 ph->flags &= ~PCIC_FLAG_CARDP; 935 936 /* call the MI detach function */ 937 pcmcia_card_detach(ph->pcmcia, flags); 938 } 939 #endif 940 941 /* 942 * int pccbbintr(arg) 943 * void *arg; 944 * This routine handles the interrupt from Yenta PCI-CardBus bridge 945 * itself. 946 */ 947 int 948 pccbbintr(void *arg) 949 { 950 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 951 u_int32_t sockevent, sockstate; 952 bus_space_tag_t memt = sc->sc_base_memt; 953 bus_space_handle_t memh = sc->sc_base_memh; 954 struct pcic_handle *ph = &sc->sc_pcmcia_h; 955 956 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 957 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 958 Pcic_read(ph, PCIC_CSC); 959 960 if (sockevent == 0) { 961 /* This intr is not for me: it may be for my child devices. */ 962 if (sc->sc_pil_intr_enable) { 963 return pccbbintr_function(sc); 964 } else { 965 return 0; 966 } 967 } 968 969 aprint_debug("%s: enter sockevent %" PRIx32 "\n", __func__, sockevent); 970 971 if (sockevent & CB_SOCKET_EVENT_CD) { 972 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 973 if (0x00 != (sockstate & CB_SOCKET_STAT_CD)) { 974 /* A card should be removed. */ 975 if (sc->sc_flags & CBB_CARDEXIST) { 976 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 977 sockevent)); 978 DPRINTF((" card removed, 0x%08x\n", sockstate)); 979 sc->sc_flags &= ~CBB_CARDEXIST; 980 if (sc->sc_csc->sc_status & 981 CARDSLOT_STATUS_CARD_16) { 982 #if 0 983 struct pcic_handle *ph = 984 &sc->sc_pcmcia_h; 985 986 pcmcia_card_deactivate(ph->pcmcia); 987 pccbb_pcmcia_socket_disable(ph); 988 pccbb_pcmcia_detach_card(ph, 989 DETACH_FORCE); 990 #endif 991 cardslot_event_throw(sc->sc_csc, 992 CARDSLOT_EVENT_REMOVAL_16); 993 } else if (sc->sc_csc->sc_status & 994 CARDSLOT_STATUS_CARD_CB) { 995 /* Cardbus intr removed */ 996 cardslot_event_throw(sc->sc_csc, 997 CARDSLOT_EVENT_REMOVAL_CB); 998 } 999 } else if (sc->sc_flags & CBB_INSERTING) { 1000 sc->sc_flags &= ~CBB_INSERTING; 1001 callout_stop(&sc->sc_insert_ch); 1002 } 1003 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 1004 /* 1005 * The pccbbintr may called from powerdown hook when 1006 * the system resumed, to detect the card 1007 * insertion/removal during suspension. 1008 */ 1009 (sc->sc_flags & CBB_CARDEXIST) == 0) { 1010 if (sc->sc_flags & CBB_INSERTING) { 1011 callout_stop(&sc->sc_insert_ch); 1012 } 1013 callout_schedule(&sc->sc_insert_ch, hz / 5); 1014 sc->sc_flags |= CBB_INSERTING; 1015 } 1016 } 1017 1018 if (sockevent & CB_SOCKET_EVENT_POWER) { 1019 DPRINTF(("Powercycling because of socket event\n")); 1020 /* XXX: Does not happen when attaching a 16-bit card */ 1021 sc->sc_pwrcycle++; 1022 wakeup(&sc->sc_pwrcycle); 1023 } 1024 1025 return (1); 1026 } 1027 1028 /* 1029 * static int pccbbintr_function(struct pccbb_softc *sc) 1030 * 1031 * This function calls each interrupt handler registered at the 1032 * bridge. The interrupt handlers are called in registered order. 1033 */ 1034 static int 1035 pccbbintr_function(struct pccbb_softc *sc) 1036 { 1037 int retval = 0, val; 1038 struct pccbb_intrhand_list *pil; 1039 int s; 1040 1041 for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1042 pil = LIST_NEXT(pil, pil_next)) { 1043 s = splraiseipl(pil->pil_icookie); 1044 val = (*pil->pil_func)(pil->pil_arg); 1045 splx(s); 1046 1047 retval = retval == 1 ? 1 : 1048 retval == 0 ? val : val != 0 ? val : retval; 1049 } 1050 1051 return retval; 1052 } 1053 1054 static void 1055 pci113x_insert(void *arg) 1056 { 1057 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1058 u_int32_t sockevent, sockstate; 1059 1060 if (!(sc->sc_flags & CBB_INSERTING)) { 1061 /* We add a card only under inserting state. */ 1062 return; 1063 } 1064 sc->sc_flags &= ~CBB_INSERTING; 1065 1066 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1067 CB_SOCKET_EVENT); 1068 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1069 CB_SOCKET_STAT); 1070 1071 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1072 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1073 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1074 sc->sc_flags |= CBB_CARDEXIST; 1075 /* call pccard interrupt handler here */ 1076 if (sockstate & CB_SOCKET_STAT_16BIT) { 1077 /* 16-bit card found */ 1078 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1079 cardslot_event_throw(sc->sc_csc, 1080 CARDSLOT_EVENT_INSERTION_16); 1081 } else if (sockstate & CB_SOCKET_STAT_CB) { 1082 /* cardbus card found */ 1083 /* cardbus_attach_card(sc->sc_csc); */ 1084 cardslot_event_throw(sc->sc_csc, 1085 CARDSLOT_EVENT_INSERTION_CB); 1086 } else { 1087 /* who are you? */ 1088 } 1089 } else { 1090 callout_schedule(&sc->sc_insert_ch, hz / 10); 1091 } 1092 } 1093 1094 #define PCCBB_PCMCIA_OFFSET 0x800 1095 static u_int8_t 1096 pccbb_pcmcia_read(struct pcic_handle *ph, int reg) 1097 { 1098 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1099 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1100 1101 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1102 PCCBB_PCMCIA_OFFSET + reg); 1103 } 1104 1105 static void 1106 pccbb_pcmcia_write(struct pcic_handle *ph, int reg, u_int8_t val) 1107 { 1108 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1109 val); 1110 1111 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1112 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1113 } 1114 1115 /* 1116 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1117 */ 1118 STATIC int 1119 pccbb_ctrl(cardbus_chipset_tag_t ct, int command) 1120 { 1121 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1122 1123 switch (command) { 1124 case CARDBUS_CD: 1125 if (2 == pccbb_detect_card(sc)) { 1126 int retval = 0; 1127 int status = cb_detect_voltage(sc); 1128 if (PCCARD_VCC_5V & status) { 1129 retval |= CARDBUS_5V_CARD; 1130 } 1131 if (PCCARD_VCC_3V & status) { 1132 retval |= CARDBUS_3V_CARD; 1133 } 1134 if (PCCARD_VCC_XV & status) { 1135 retval |= CARDBUS_XV_CARD; 1136 } 1137 if (PCCARD_VCC_YV & status) { 1138 retval |= CARDBUS_YV_CARD; 1139 } 1140 return retval; 1141 } else { 1142 return 0; 1143 } 1144 case CARDBUS_RESET: 1145 return cb_reset(sc); 1146 case CARDBUS_IO_ENABLE: /* fallthrough */ 1147 case CARDBUS_IO_DISABLE: /* fallthrough */ 1148 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1149 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1150 case CARDBUS_BM_ENABLE: /* fallthrough */ 1151 case CARDBUS_BM_DISABLE: /* fallthrough */ 1152 /* XXX: I think we don't need to call this function below. */ 1153 return pccbb_cardenable(sc, command); 1154 } 1155 1156 return 0; 1157 } 1158 1159 /* 1160 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1161 * This function returns true when it succeeds and returns false when 1162 * it fails. 1163 */ 1164 STATIC int 1165 pccbb_power(cardbus_chipset_tag_t ct, int command) 1166 { 1167 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1168 u_int32_t status, osock_ctrl, sock_ctrl, reg_ctrl; 1169 bus_space_tag_t memt = sc->sc_base_memt; 1170 bus_space_handle_t memh = sc->sc_base_memh; 1171 int on = 0, pwrcycle, s, times; 1172 struct timeval before, after, diff; 1173 1174 DPRINTF(("pccbb_power: %s and %s [0x%x]\n", 1175 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1176 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1177 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1178 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1179 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1180 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1181 "UNKNOWN", 1182 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1183 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1184 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1185 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1186 "UNKNOWN", command)); 1187 1188 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1189 osock_ctrl = sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1190 1191 switch (command & CARDBUS_VCCMASK) { 1192 case CARDBUS_VCC_UC: 1193 break; 1194 case CARDBUS_VCC_5V: 1195 on++; 1196 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1197 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1198 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1199 } else { 1200 printf("%s: BAD voltage request: no 5 V card\n", 1201 sc->sc_dev.dv_xname); 1202 return 0; 1203 } 1204 break; 1205 case CARDBUS_VCC_3V: 1206 on++; 1207 if (CB_SOCKET_STAT_3VCARD & status) { 1208 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1209 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1210 } else { 1211 printf("%s: BAD voltage request: no 3.3 V card\n", 1212 sc->sc_dev.dv_xname); 1213 return 0; 1214 } 1215 break; 1216 case CARDBUS_VCC_0V: 1217 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1218 break; 1219 default: 1220 return 0; /* power NEVER changed */ 1221 } 1222 1223 switch (command & CARDBUS_VPPMASK) { 1224 case CARDBUS_VPP_UC: 1225 break; 1226 case CARDBUS_VPP_0V: 1227 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1228 break; 1229 case CARDBUS_VPP_VCC: 1230 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1231 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1232 break; 1233 case CARDBUS_VPP_12V: 1234 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1235 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1236 break; 1237 } 1238 1239 pwrcycle = sc->sc_pwrcycle; 1240 aprint_debug("%s: osock_ctrl %#" PRIx32 " sock_ctrl %#" PRIx32 "\n", 1241 device_xname(&sc->sc_dev), osock_ctrl, sock_ctrl); 1242 1243 microtime(&before); 1244 s = splbio(); 1245 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1246 1247 /* 1248 * Wait as long as 200ms for a power-cycle interrupt. If 1249 * interrupts are enabled, but the socket has already 1250 * changed to the desired status, keep waiting for the 1251 * interrupt. "Consuming" the interrupt in this way keeps 1252 * the interrupt from prematurely waking some subsequent 1253 * pccbb_power call. 1254 * 1255 * XXX Not every bridge interrupts on the ->OFF transition. 1256 * XXX That's ok, we will time-out after 200ms. 1257 * 1258 * XXX The power cycle event will never happen when attaching 1259 * XXX a 16-bit card. That's ok, we will time-out after 1260 * XXX 200ms. 1261 */ 1262 for (times = 5; --times >= 0; ) { 1263 if (cold) 1264 DELAY(40 * 1000); 1265 else { 1266 (void)tsleep(&sc->sc_pwrcycle, PWAIT, "pccpwr", 1267 hz / 25); 1268 if (pwrcycle == sc->sc_pwrcycle) 1269 continue; 1270 } 1271 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1272 if ((status & CB_SOCKET_STAT_PWRCYCLE) != 0 && on) 1273 break; 1274 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0 && !on) 1275 break; 1276 } 1277 splx(s); 1278 microtime(&after); 1279 timersub(&after, &before, &diff); 1280 aprint_debug("%s: wait took%s %ld.%06lds\n", sc->sc_dev.dv_xname, 1281 (on && times < 0) ? " too long" : "", diff.tv_sec, diff.tv_usec); 1282 1283 /* 1284 * Ok, wait a bit longer for things to settle. 1285 */ 1286 if (on && sc->sc_chipset == CB_TOPIC95B) 1287 delay_ms(100, sc); 1288 1289 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1290 1291 if (on && sc->sc_chipset != CB_TOPIC95B) { 1292 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0) 1293 printf("%s: power on failed?\n", sc->sc_dev.dv_xname); 1294 } 1295 1296 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1297 printf("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1298 sc->sc_dev.dv_xname, sock_ctrl, status); 1299 printf("%s: disabling socket\n", sc->sc_dev.dv_xname); 1300 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1301 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1302 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1303 status &= ~CB_SOCKET_STAT_BADVCC; 1304 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, status); 1305 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1306 CB_SOCKET_STAT)); 1307 return 0; 1308 } 1309 1310 if (sc->sc_chipset == CB_TOPIC97) { 1311 reg_ctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL); 1312 reg_ctrl &= ~TOPIC97_REG_CTRL_TESTMODE; 1313 if ((command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V) 1314 reg_ctrl &= ~TOPIC97_REG_CTRL_CLKRUN_ENA; 1315 else 1316 reg_ctrl |= TOPIC97_REG_CTRL_CLKRUN_ENA; 1317 pci_conf_write(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL, reg_ctrl); 1318 } 1319 1320 return 1; /* power changed correctly */ 1321 } 1322 1323 #if defined CB_PCMCIA_POLL 1324 struct cb_poll_str { 1325 void *arg; 1326 int (*func)(void *); 1327 int level; 1328 pccard_chipset_tag_t ct; 1329 int count; 1330 struct callout poll_ch; 1331 }; 1332 1333 static struct cb_poll_str cb_poll[10]; 1334 static int cb_poll_n = 0; 1335 1336 static void cb_pcmcia_poll(void *arg); 1337 1338 static void 1339 cb_pcmcia_poll(void *arg) 1340 { 1341 struct cb_poll_str *poll = arg; 1342 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1343 struct pccbb_softc *sc = psc->cpc_parent; 1344 int s; 1345 u_int32_t spsr; /* socket present-state reg */ 1346 1347 callout_reset(&poll->poll_ch, hz / 10, cb_pcmcia_poll, poll); 1348 switch (poll->level) { 1349 case IPL_NET: 1350 s = splnet(); 1351 break; 1352 case IPL_BIO: 1353 s = splbio(); 1354 break; 1355 case IPL_TTY: /* fallthrough */ 1356 default: 1357 s = spltty(); 1358 break; 1359 } 1360 1361 spsr = 1362 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1363 CB_SOCKET_STAT); 1364 1365 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1366 if (!(spsr & 0x40)) { /* CINT low */ 1367 #else 1368 if (1) { 1369 #endif 1370 if ((*poll->func) (poll->arg) == 1) { 1371 ++poll->count; 1372 printf("intr: reported from poller, 0x%x\n", spsr); 1373 #if defined LEVEL2 1374 } else { 1375 printf("intr: miss! 0x%x\n", spsr); 1376 #endif 1377 } 1378 } 1379 splx(s); 1380 } 1381 #endif /* defined CB_PCMCIA_POLL */ 1382 1383 /* 1384 * static int pccbb_detect_card(struct pccbb_softc *sc) 1385 * return value: 0 if no card exists. 1386 * 1 if 16-bit card exists. 1387 * 2 if cardbus card exists. 1388 */ 1389 static int 1390 pccbb_detect_card(struct pccbb_softc *sc) 1391 { 1392 bus_space_handle_t base_memh = sc->sc_base_memh; 1393 bus_space_tag_t base_memt = sc->sc_base_memt; 1394 u_int32_t sockstat = 1395 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1396 int retval = 0; 1397 1398 /* CD1 and CD2 asserted */ 1399 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1400 /* card must be present */ 1401 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1402 /* NOTACARD DEASSERTED */ 1403 if (CB_SOCKET_STAT_CB & sockstat) { 1404 /* CardBus mode */ 1405 retval = 2; 1406 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1407 /* 16-bit mode */ 1408 retval = 1; 1409 } 1410 } 1411 } 1412 return retval; 1413 } 1414 1415 /* 1416 * STATIC int cb_reset(struct pccbb_softc *sc) 1417 * This function resets CardBus card. 1418 */ 1419 STATIC int 1420 cb_reset(struct pccbb_softc *sc) 1421 { 1422 /* 1423 * Reset Assert at least 20 ms 1424 * Some machines request longer duration. 1425 */ 1426 int reset_duration = 1427 (sc->sc_chipset == CB_RX5C47X ? 400 : 50); 1428 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1429 1430 /* Reset bit Assert (bit 6 at 0x3E) */ 1431 bcr |= CB_BCR_RESET_ENABLE; 1432 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr); 1433 delay_ms(reset_duration, sc); 1434 1435 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1436 /* Reset bit Deassert (bit 6 at 0x3E) */ 1437 bcr &= ~CB_BCR_RESET_ENABLE; 1438 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr); 1439 delay_ms(reset_duration, sc); 1440 } 1441 /* No card found on the slot. Keep Reset. */ 1442 return 1; 1443 } 1444 1445 /* 1446 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1447 * This function detect card Voltage. 1448 */ 1449 STATIC int 1450 cb_detect_voltage(struct pccbb_softc *sc) 1451 { 1452 u_int32_t psr; /* socket present-state reg */ 1453 bus_space_tag_t iot = sc->sc_base_memt; 1454 bus_space_handle_t ioh = sc->sc_base_memh; 1455 int vol = PCCARD_VCC_UKN; /* set 0 */ 1456 1457 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1458 1459 if (0x400u & psr) { 1460 vol |= PCCARD_VCC_5V; 1461 } 1462 if (0x800u & psr) { 1463 vol |= PCCARD_VCC_3V; 1464 } 1465 1466 return vol; 1467 } 1468 1469 STATIC int 1470 cbbprint(void *aux, const char *pcic) 1471 { 1472 #if 0 1473 struct cbslot_attach_args *cba = aux; 1474 1475 if (cba->cba_slot >= 0) { 1476 aprint_normal(" slot %d", cba->cba_slot); 1477 } 1478 #endif 1479 return UNCONF; 1480 } 1481 1482 /* 1483 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1484 * This function enables and disables the card 1485 */ 1486 STATIC int 1487 pccbb_cardenable(struct pccbb_softc *sc, int function) 1488 { 1489 u_int32_t command = 1490 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1491 1492 DPRINTF(("pccbb_cardenable:")); 1493 switch (function) { 1494 case CARDBUS_IO_ENABLE: 1495 command |= PCI_COMMAND_IO_ENABLE; 1496 break; 1497 case CARDBUS_IO_DISABLE: 1498 command &= ~PCI_COMMAND_IO_ENABLE; 1499 break; 1500 case CARDBUS_MEM_ENABLE: 1501 command |= PCI_COMMAND_MEM_ENABLE; 1502 break; 1503 case CARDBUS_MEM_DISABLE: 1504 command &= ~PCI_COMMAND_MEM_ENABLE; 1505 break; 1506 case CARDBUS_BM_ENABLE: 1507 command |= PCI_COMMAND_MASTER_ENABLE; 1508 break; 1509 case CARDBUS_BM_DISABLE: 1510 command &= ~PCI_COMMAND_MASTER_ENABLE; 1511 break; 1512 default: 1513 return 0; 1514 } 1515 1516 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1517 DPRINTF((" command reg 0x%x\n", command)); 1518 return 1; 1519 } 1520 1521 #if !rbus 1522 static int 1523 pccbb_io_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 1524 { 1525 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1526 int basereg; 1527 int limitreg; 1528 1529 if ((win < 0) || (win > 2)) { 1530 #if defined DIAGNOSTIC 1531 printf("cardbus_io_open: window out of range %d\n", win); 1532 #endif 1533 return 0; 1534 } 1535 1536 basereg = win * 8 + 0x2c; 1537 limitreg = win * 8 + 0x30; 1538 1539 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1540 start, basereg, end, limitreg)); 1541 1542 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1543 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1544 return 1; 1545 } 1546 1547 /* 1548 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1549 */ 1550 static int 1551 pccbb_io_close(cardbus_chipset_tag_t ct, int win) 1552 { 1553 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1554 int basereg; 1555 int limitreg; 1556 1557 if ((win < 0) || (win > 2)) { 1558 #if defined DIAGNOSTIC 1559 printf("cardbus_io_close: window out of range %d\n", win); 1560 #endif 1561 return 0; 1562 } 1563 1564 basereg = win * 8 + 0x2c; 1565 limitreg = win * 8 + 0x30; 1566 1567 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1568 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1569 return 1; 1570 } 1571 1572 static int 1573 pccbb_mem_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 1574 { 1575 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1576 int basereg; 1577 int limitreg; 1578 1579 if ((win < 0) || (win > 2)) { 1580 #if defined DIAGNOSTIC 1581 printf("cardbus_mem_open: window out of range %d\n", win); 1582 #endif 1583 return 0; 1584 } 1585 1586 basereg = win * 8 + 0x1c; 1587 limitreg = win * 8 + 0x20; 1588 1589 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1590 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1591 return 1; 1592 } 1593 1594 static int 1595 pccbb_mem_close(cardbus_chipset_tag_t ct, int win) 1596 { 1597 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1598 int basereg; 1599 int limitreg; 1600 1601 if ((win < 0) || (win > 2)) { 1602 #if defined DIAGNOSTIC 1603 printf("cardbus_mem_close: window out of range %d\n", win); 1604 #endif 1605 return 0; 1606 } 1607 1608 basereg = win * 8 + 0x1c; 1609 limitreg = win * 8 + 0x20; 1610 1611 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1612 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1613 return 1; 1614 } 1615 #endif 1616 1617 /* 1618 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1619 * int irq, 1620 * int level, 1621 * int (* func)(void *), 1622 * void *arg) 1623 * 1624 * This function registers an interrupt handler at the bridge, in 1625 * order not to call the interrupt handlers of child devices when 1626 * a card-deletion interrupt occurs. 1627 * 1628 * The arguments irq and level are not used. 1629 */ 1630 static void * 1631 pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, int irq, int level, 1632 int (*func)(void *), void *arg) 1633 { 1634 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1635 1636 return pccbb_intr_establish(sc, irq, level, func, arg); 1637 } 1638 1639 1640 /* 1641 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1642 * void *ih) 1643 * 1644 * This function removes an interrupt handler pointed by ih. 1645 */ 1646 static void 1647 pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih) 1648 { 1649 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1650 1651 pccbb_intr_disestablish(sc, ih); 1652 } 1653 1654 1655 void 1656 pccbb_intr_route(struct pccbb_softc *sc) 1657 { 1658 pcireg_t bcr, cbctrl; 1659 1660 /* initialize bridge intr routing */ 1661 bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1662 bcr &= ~CB_BCR_INTR_IREQ_ENABLE; 1663 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr); 1664 1665 switch (sc->sc_chipset) { 1666 case CB_TI113X: 1667 cbctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1668 /* functional intr enabled */ 1669 cbctrl |= PCI113X_CBCTRL_PCI_INTR; 1670 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, cbctrl); 1671 break; 1672 default: 1673 break; 1674 } 1675 } 1676 1677 /* 1678 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1679 * int irq, 1680 * int level, 1681 * int (* func)(void *), 1682 * void *arg) 1683 * 1684 * This function registers an interrupt handler at the bridge, in 1685 * order not to call the interrupt handlers of child devices when 1686 * a card-deletion interrupt occurs. 1687 * 1688 * The arguments irq is not used because pccbb selects intr vector. 1689 */ 1690 static void * 1691 pccbb_intr_establish(struct pccbb_softc *sc, int irq, int level, 1692 int (*func)(void *), void *arg) 1693 { 1694 struct pccbb_intrhand_list *pil, *newpil; 1695 1696 DPRINTF(("pccbb_intr_establish start. %p\n", LIST_FIRST(&sc->sc_pil))); 1697 1698 if (LIST_EMPTY(&sc->sc_pil)) { 1699 pccbb_intr_route(sc); 1700 } 1701 1702 /* 1703 * Allocate a room for interrupt handler structure. 1704 */ 1705 if (NULL == (newpil = 1706 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1707 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1708 return NULL; 1709 } 1710 1711 newpil->pil_func = func; 1712 newpil->pil_arg = arg; 1713 newpil->pil_icookie = makeiplcookie(level); 1714 1715 if (LIST_EMPTY(&sc->sc_pil)) { 1716 LIST_INSERT_HEAD(&sc->sc_pil, newpil, pil_next); 1717 } else { 1718 for (pil = LIST_FIRST(&sc->sc_pil); 1719 LIST_NEXT(pil, pil_next) != NULL; 1720 pil = LIST_NEXT(pil, pil_next)); 1721 LIST_INSERT_AFTER(pil, newpil, pil_next); 1722 } 1723 1724 DPRINTF(("pccbb_intr_establish add pil. %p\n", 1725 LIST_FIRST(&sc->sc_pil))); 1726 1727 return newpil; 1728 } 1729 1730 /* 1731 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1732 * void *ih) 1733 * 1734 * This function removes an interrupt handler pointed by ih. ih 1735 * should be the value returned by cardbus_intr_establish() or 1736 * NULL. 1737 * 1738 * When ih is NULL, this function will do nothing. 1739 */ 1740 static void 1741 pccbb_intr_disestablish(struct pccbb_softc *sc, void *ih) 1742 { 1743 struct pccbb_intrhand_list *pil; 1744 pcireg_t reg; 1745 1746 DPRINTF(("pccbb_intr_disestablish start. %p\n", 1747 LIST_FIRST(&sc->sc_pil))); 1748 1749 if (ih == NULL) { 1750 /* intr handler is not set */ 1751 DPRINTF(("pccbb_intr_disestablish: no ih\n")); 1752 return; 1753 } 1754 1755 #ifdef DIAGNOSTIC 1756 for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1757 pil = LIST_NEXT(pil, pil_next)) { 1758 DPRINTF(("pccbb_intr_disestablish: pil %p\n", pil)); 1759 if (pil == ih) { 1760 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1761 break; 1762 } 1763 } 1764 if (pil == NULL) { 1765 panic("pccbb_intr_disestablish: %s cannot find pil %p", 1766 sc->sc_dev.dv_xname, ih); 1767 } 1768 #endif 1769 1770 pil = (struct pccbb_intrhand_list *)ih; 1771 LIST_REMOVE(pil, pil_next); 1772 free(pil, M_DEVBUF); 1773 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1774 1775 if (LIST_EMPTY(&sc->sc_pil)) { 1776 /* No interrupt handlers */ 1777 1778 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1779 1780 /* stop routing PCI intr */ 1781 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1782 reg |= CB_BCR_INTR_IREQ_ENABLE; 1783 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, reg); 1784 1785 switch (sc->sc_chipset) { 1786 case CB_TI113X: 1787 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1788 /* functional intr disabled */ 1789 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1790 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1791 break; 1792 default: 1793 break; 1794 } 1795 } 1796 } 1797 1798 #if defined SHOW_REGS 1799 static void 1800 cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, bus_space_tag_t memt, 1801 bus_space_handle_t memh) 1802 { 1803 int i; 1804 printf("PCI config regs:"); 1805 for (i = 0; i < 0x50; i += 4) { 1806 if (i % 16 == 0) 1807 printf("\n 0x%02x:", i); 1808 printf(" %08x", pci_conf_read(pc, tag, i)); 1809 } 1810 for (i = 0x80; i < 0xb0; i += 4) { 1811 if (i % 16 == 0) 1812 printf("\n 0x%02x:", i); 1813 printf(" %08x", pci_conf_read(pc, tag, i)); 1814 } 1815 1816 if (memh == 0) { 1817 printf("\n"); 1818 return; 1819 } 1820 1821 printf("\nsocket regs:"); 1822 for (i = 0; i <= 0x10; i += 0x04) 1823 printf(" %08x", bus_space_read_4(memt, memh, i)); 1824 printf("\nExCA regs:"); 1825 for (i = 0; i < 0x08; ++i) 1826 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1827 printf("\n"); 1828 return; 1829 } 1830 #endif 1831 1832 /* 1833 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1834 * int busno, int function) 1835 * This is the function to make a tag to access config space of 1836 * a CardBus Card. It works same as pci_conf_read. 1837 */ 1838 static cardbustag_t 1839 pccbb_make_tag(cardbus_chipset_tag_t cc, int busno, int function) 1840 { 1841 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1842 1843 return pci_make_tag(sc->sc_pc, busno, 0, function); 1844 } 1845 1846 static void 1847 pccbb_free_tag(cardbus_chipset_tag_t cc, cardbustag_t tag) 1848 { 1849 } 1850 1851 /* 1852 * pccbb_conf_read 1853 * 1854 * This is the function to read the config space of a CardBus card. 1855 * It works the same as pci_conf_read(9). 1856 */ 1857 static cardbusreg_t 1858 pccbb_conf_read(cardbus_chipset_tag_t cc, cardbustag_t tag, int offset) 1859 { 1860 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1861 1862 return pci_conf_read(sc->sc_pc, tag, offset); 1863 } 1864 1865 /* 1866 * pccbb_conf_write 1867 * 1868 * This is the function to write the config space of a CardBus 1869 * card. It works the same as pci_conf_write(9). 1870 */ 1871 static void 1872 pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, int reg, 1873 cardbusreg_t val) 1874 { 1875 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1876 1877 pci_conf_write(sc->sc_pc, tag, reg, val); 1878 } 1879 1880 #if 0 1881 STATIC int 1882 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1883 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 1884 int speed, int flags, 1885 bus_space_handle_t * iohp) 1886 #endif 1887 /* 1888 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1889 * bus_addr_t start, bus_size_t size, 1890 * bus_size_t align, 1891 * struct pcmcia_io_handle *pcihp 1892 * 1893 * This function only allocates I/O region for pccard. This function 1894 * never maps the allocated region to pccard I/O area. 1895 * 1896 * XXX: The interface of this function is not very good, I believe. 1897 */ 1898 STATIC int 1899 pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, 1900 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 1901 { 1902 struct pcic_handle *ph = (struct pcic_handle *)pch; 1903 bus_addr_t ioaddr; 1904 int flags = 0; 1905 bus_space_tag_t iot; 1906 bus_space_handle_t ioh; 1907 bus_addr_t mask; 1908 #if rbus 1909 rbus_tag_t rb; 1910 #endif 1911 if (align == 0) { 1912 align = size; /* XXX: funny??? */ 1913 } 1914 1915 if (start != 0) { 1916 /* XXX: assume all card decode lower 10 bits by its hardware */ 1917 mask = 0x3ff; 1918 /* enforce to use only masked address */ 1919 start &= mask; 1920 } else { 1921 /* 1922 * calculate mask: 1923 * 1. get the most significant bit of size (call it msb). 1924 * 2. compare msb with the value of size. 1925 * 3. if size is larger, shift msb left once. 1926 * 4. obtain mask value to decrement msb. 1927 */ 1928 bus_size_t size_tmp = size; 1929 int shifts = 0; 1930 1931 mask = 1; 1932 while (size_tmp) { 1933 ++shifts; 1934 size_tmp >>= 1; 1935 } 1936 mask = (1 << shifts); 1937 if (mask < size) { 1938 mask <<= 1; 1939 } 1940 --mask; 1941 } 1942 1943 /* 1944 * Allocate some arbitrary I/O space. 1945 */ 1946 1947 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 1948 1949 #if rbus 1950 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 1951 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 1952 return 1; 1953 } 1954 DPRINTF(("pccbb_pcmcia_io_alloc alloc port 0x%lx+0x%lx\n", 1955 (u_long) ioaddr, (u_long) size)); 1956 #else 1957 if (start) { 1958 ioaddr = start; 1959 if (bus_space_map(iot, start, size, 0, &ioh)) { 1960 return 1; 1961 } 1962 DPRINTF(("pccbb_pcmcia_io_alloc map port 0x%lx+0x%lx\n", 1963 (u_long) ioaddr, (u_long) size)); 1964 } else { 1965 flags |= PCMCIA_IO_ALLOCATED; 1966 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 1967 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 1968 size, align, 0, 0, &ioaddr, &ioh)) { 1969 /* No room be able to be get. */ 1970 return 1; 1971 } 1972 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 1973 (u_long) ioaddr, (u_long) size)); 1974 } 1975 #endif 1976 1977 pcihp->iot = iot; 1978 pcihp->ioh = ioh; 1979 pcihp->addr = ioaddr; 1980 pcihp->size = size; 1981 pcihp->flags = flags; 1982 1983 return 0; 1984 } 1985 1986 /* 1987 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 1988 * struct pcmcia_io_handle *pcihp) 1989 * 1990 * This function only frees I/O region for pccard. 1991 * 1992 * XXX: The interface of this function is not very good, I believe. 1993 */ 1994 void 1995 pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 1996 struct pcmcia_io_handle *pcihp) 1997 { 1998 #if !rbus 1999 bus_space_tag_t iot = pcihp->iot; 2000 #endif 2001 bus_space_handle_t ioh = pcihp->ioh; 2002 bus_size_t size = pcihp->size; 2003 2004 #if rbus 2005 struct pccbb_softc *sc = 2006 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 2007 rbus_tag_t rb = sc->sc_rbus_iot; 2008 2009 rbus_space_free(rb, ioh, size, NULL); 2010 #else 2011 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 2012 bus_space_free(iot, ioh, size); 2013 else 2014 bus_space_unmap(iot, ioh, size); 2015 #endif 2016 } 2017 2018 /* 2019 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 2020 * bus_addr_t offset, bus_size_t size, 2021 * struct pcmcia_io_handle *pcihp, 2022 * int *windowp) 2023 * 2024 * This function maps the allocated I/O region to pccard. This function 2025 * never allocates any I/O region for pccard I/O area. I don't 2026 * understand why the original authors of pcmciabus separated alloc and 2027 * map. I believe the two must be unite. 2028 * 2029 * XXX: no wait timing control? 2030 */ 2031 int 2032 pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, bus_addr_t offset, 2033 bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp) 2034 { 2035 struct pcic_handle *ph = (struct pcic_handle *)pch; 2036 bus_addr_t ioaddr = pcihp->addr + offset; 2037 int i, win; 2038 #if defined CBB_DEBUG 2039 static const char *width_names[] = { "dynamic", "io8", "io16" }; 2040 #endif 2041 2042 /* Sanity check I/O handle. */ 2043 2044 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 2045 panic("pccbb_pcmcia_io_map iot is bogus"); 2046 } 2047 2048 /* XXX Sanity check offset/size. */ 2049 2050 win = -1; 2051 for (i = 0; i < PCIC_IO_WINS; i++) { 2052 if ((ph->ioalloc & (1 << i)) == 0) { 2053 win = i; 2054 ph->ioalloc |= (1 << i); 2055 break; 2056 } 2057 } 2058 2059 if (win == -1) { 2060 return 1; 2061 } 2062 2063 *windowp = win; 2064 2065 /* XXX this is pretty gross */ 2066 2067 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2068 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2069 2070 /* XXX wtf is this doing here? */ 2071 2072 #if 0 2073 printf(" port 0x%lx", (u_long) ioaddr); 2074 if (size > 1) { 2075 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2076 } 2077 #endif 2078 2079 ph->io[win].addr = ioaddr; 2080 ph->io[win].size = size; 2081 ph->io[win].width = width; 2082 2083 /* actual dirty register-value changing in the function below. */ 2084 pccbb_pcmcia_do_io_map(ph, win); 2085 2086 return 0; 2087 } 2088 2089 /* 2090 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2091 * 2092 * This function changes register-value to map I/O region for pccard. 2093 */ 2094 static void 2095 pccbb_pcmcia_do_io_map(struct pcic_handle *ph, int win) 2096 { 2097 static u_int8_t pcic_iowidth[3] = { 2098 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2099 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2100 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2101 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2102 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2103 }; 2104 2105 #define PCIC_SIA_START_LOW 0 2106 #define PCIC_SIA_START_HIGH 1 2107 #define PCIC_SIA_STOP_LOW 2 2108 #define PCIC_SIA_STOP_HIGH 3 2109 2110 int regbase_win = 0x8 + win * 0x04; 2111 u_int8_t ioctl, enable; 2112 2113 DPRINTF(("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx " 2114 "width %d\n", win, (unsigned long)ph->io[win].addr, 2115 (unsigned long)ph->io[win].size, ph->io[win].width * 8)); 2116 2117 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2118 ph->io[win].addr & 0xff); 2119 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2120 (ph->io[win].addr >> 8) & 0xff); 2121 2122 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2123 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2124 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2125 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2126 2127 ioctl = Pcic_read(ph, PCIC_IOCTL); 2128 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2129 switch (win) { 2130 case 0: 2131 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2132 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2133 PCIC_IOCTL_IO0_DATASIZE_MASK); 2134 ioctl |= pcic_iowidth[ph->io[win].width]; 2135 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2136 break; 2137 case 1: 2138 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2139 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2140 PCIC_IOCTL_IO1_DATASIZE_MASK); 2141 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2142 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2143 break; 2144 } 2145 Pcic_write(ph, PCIC_IOCTL, ioctl); 2146 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2147 #if defined(CBB_DEBUG) 2148 { 2149 u_int8_t start_low = 2150 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2151 u_int8_t start_high = 2152 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2153 u_int8_t stop_low = 2154 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2155 u_int8_t stop_high = 2156 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2157 printf("pccbb_pcmcia_do_io_map start %02x %02x, " 2158 "stop %02x %02x, ioctl %02x enable %02x\n", 2159 start_low, start_high, stop_low, stop_high, ioctl, enable); 2160 } 2161 #endif 2162 } 2163 2164 /* 2165 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2166 * 2167 * This function unmaps I/O region. No return value. 2168 */ 2169 STATIC void 2170 pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t pch, int win) 2171 { 2172 struct pcic_handle *ph = (struct pcic_handle *)pch; 2173 int reg; 2174 2175 if (win >= PCIC_IO_WINS || win < 0) { 2176 panic("pccbb_pcmcia_io_unmap: window out of range"); 2177 } 2178 2179 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2180 switch (win) { 2181 case 0: 2182 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2183 break; 2184 case 1: 2185 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2186 break; 2187 } 2188 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2189 2190 ph->ioalloc &= ~(1 << win); 2191 } 2192 2193 static int 2194 pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 2195 { 2196 u_int8_t stat; 2197 int i; 2198 2199 /* wait an initial 10ms for quick cards */ 2200 stat = Pcic_read(ph, PCIC_IF_STATUS); 2201 if (stat & PCIC_IF_STATUS_READY) 2202 return (0); 2203 pccbb_pcmcia_delay(ph, 10, "pccwr0"); 2204 for (i = 0; i < 50; i++) { 2205 stat = Pcic_read(ph, PCIC_IF_STATUS); 2206 if (stat & PCIC_IF_STATUS_READY) 2207 return (0); 2208 if ((stat & PCIC_IF_STATUS_CARDDETECT_MASK) != 2209 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2210 return (ENXIO); 2211 /* wait .1s (100ms) each iteration now */ 2212 pccbb_pcmcia_delay(ph, 100, "pccwr1"); 2213 } 2214 2215 printf("pccbb_pcmcia_wait_ready: ready never happened, status=%02x\n", stat); 2216 return (EWOULDBLOCK); 2217 } 2218 2219 /* 2220 * Perform long (msec order) delay. timo is in milliseconds. 2221 */ 2222 static void 2223 pccbb_pcmcia_delay(struct pcic_handle *ph, int timo, const char *wmesg) 2224 { 2225 #ifdef DIAGNOSTIC 2226 if (timo <= 0) 2227 panic("pccbb_pcmcia_delay: called with timeout %d", timo); 2228 if (!curlwp) 2229 panic("pccbb_pcmcia_delay: called in interrupt context"); 2230 #if 0 2231 if (!ph->event_thread) 2232 panic("pccbb_pcmcia_delay: no event thread"); 2233 #endif 2234 #endif 2235 DPRINTF(("pccbb_pcmcia_delay: \"%s\" %p, sleep %d ms\n", 2236 wmesg, ph->event_thread, timo)); 2237 tsleep(pccbb_pcmcia_delay, PWAIT, wmesg, roundup(timo * hz, 1000) / 1000); 2238 } 2239 2240 /* 2241 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2242 * 2243 * This function enables the card. All information is stored in 2244 * the first argument, pcmcia_chipset_handle_t. 2245 */ 2246 STATIC void 2247 pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2248 { 2249 struct pcic_handle *ph = (struct pcic_handle *)pch; 2250 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2251 pcireg_t spsr; 2252 int voltage; 2253 int win; 2254 u_int8_t power, intr; 2255 #ifdef DIAGNOSTIC 2256 int reg; 2257 #endif 2258 2259 /* this bit is mostly stolen from pcic_attach_card */ 2260 2261 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2262 2263 /* get card Vcc info */ 2264 spsr = 2265 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2266 CB_SOCKET_STAT); 2267 if (spsr & CB_SOCKET_STAT_5VCARD) { 2268 DPRINTF(("5V card\n")); 2269 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2270 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2271 DPRINTF(("3V card\n")); 2272 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2273 } else { 2274 DPRINTF(("?V card, 0x%x\n", spsr)); /* XXX */ 2275 return; 2276 } 2277 2278 /* disable interrupts; assert RESET */ 2279 intr = Pcic_read(ph, PCIC_INTR); 2280 intr &= PCIC_INTR_ENABLE; 2281 Pcic_write(ph, PCIC_INTR, intr); 2282 2283 /* zero out the address windows */ 2284 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2285 2286 /* power down the socket to reset it, clear the card reset pin */ 2287 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2288 2289 /* power off; assert output enable bit */ 2290 power = PCIC_PWRCTL_OE; 2291 Pcic_write(ph, PCIC_PWRCTL, power); 2292 2293 /* power up the socket */ 2294 if (pccbb_power(sc, voltage) == 0) 2295 return; 2296 2297 /* 2298 * Table 4-18 and figure 4-6 of the PC Card specifiction say: 2299 * Vcc Rising Time (Tpr) = 100ms (handled in pccbb_power() above) 2300 * RESET Width (Th (Hi-z RESET)) = 1ms 2301 * RESET Width (Tw (RESET)) = 10us 2302 * 2303 * some machines require some more time to be settled 2304 * for example old toshiba topic bridges! 2305 * (100ms is added here). 2306 */ 2307 pccbb_pcmcia_delay(ph, 200 + 1, "pccen1"); 2308 2309 /* negate RESET */ 2310 intr |= PCIC_INTR_RESET; 2311 Pcic_write(ph, PCIC_INTR, intr); 2312 2313 /* 2314 * RESET Setup Time (Tsu (RESET)) = 20ms 2315 */ 2316 pccbb_pcmcia_delay(ph, 20, "pccen2"); 2317 2318 #ifdef DIAGNOSTIC 2319 reg = Pcic_read(ph, PCIC_IF_STATUS); 2320 if ((reg & PCIC_IF_STATUS_POWERACTIVE) == 0) 2321 printf("pccbb_pcmcia_socket_enable: no power, status=%x\n", reg); 2322 #endif 2323 2324 /* wait for the chip to finish initializing */ 2325 if (pccbb_pcmcia_wait_ready(ph)) { 2326 #ifdef DIAGNOSTIC 2327 printf("pccbb_pcmcia_socket_enable: never became ready\n"); 2328 #endif 2329 /* XXX return a failure status?? */ 2330 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2331 Pcic_write(ph, PCIC_PWRCTL, 0); 2332 return; 2333 } 2334 2335 /* reinstall all the memory and io mappings */ 2336 for (win = 0; win < PCIC_MEM_WINS; ++win) 2337 if (ph->memalloc & (1 << win)) 2338 pccbb_pcmcia_do_mem_map(ph, win); 2339 for (win = 0; win < PCIC_IO_WINS; ++win) 2340 if (ph->ioalloc & (1 << win)) 2341 pccbb_pcmcia_do_io_map(ph, win); 2342 } 2343 2344 /* 2345 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2346 * 2347 * This function disables the card. All information is stored in 2348 * the first argument, pcmcia_chipset_handle_t. 2349 */ 2350 STATIC void 2351 pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t pch) 2352 { 2353 struct pcic_handle *ph = (struct pcic_handle *)pch; 2354 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2355 u_int8_t intr; 2356 2357 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2358 2359 /* disable interrupts; assert RESET */ 2360 intr = Pcic_read(ph, PCIC_INTR); 2361 intr &= PCIC_INTR_ENABLE; 2362 Pcic_write(ph, PCIC_INTR, intr); 2363 2364 /* zero out the address windows */ 2365 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2366 2367 /* power down the socket to reset it, clear the card reset pin */ 2368 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2369 2370 /* disable socket: negate output enable bit and power off */ 2371 Pcic_write(ph, PCIC_PWRCTL, 0); 2372 2373 /* 2374 * Vcc Falling Time (Tpf) = 300ms 2375 */ 2376 pccbb_pcmcia_delay(ph, 300, "pccwr1"); 2377 } 2378 2379 STATIC void 2380 pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t pch, int type) 2381 { 2382 struct pcic_handle *ph = (struct pcic_handle *)pch; 2383 u_int8_t intr; 2384 2385 /* set the card type */ 2386 2387 intr = Pcic_read(ph, PCIC_INTR); 2388 intr &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_CARDTYPE_MASK); 2389 if (type == PCMCIA_IFTYPE_IO) 2390 intr |= PCIC_INTR_CARDTYPE_IO; 2391 else 2392 intr |= PCIC_INTR_CARDTYPE_MEM; 2393 Pcic_write(ph, PCIC_INTR, intr); 2394 2395 DPRINTF(("%s: pccbb_pcmcia_socket_settype %02x type %s %02x\n", 2396 ph->ph_parent->dv_xname, ph->sock, 2397 ((type == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2398 } 2399 2400 /* 2401 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2402 * 2403 * This function detects whether a card is in the slot or not. 2404 * If a card is inserted, return 1. Otherwise, return 0. 2405 */ 2406 STATIC int 2407 pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch) 2408 { 2409 struct pcic_handle *ph = (struct pcic_handle *)pch; 2410 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2411 2412 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2413 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2414 } 2415 2416 #if 0 2417 STATIC int 2418 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2419 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2420 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2421 #endif 2422 /* 2423 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2424 * bus_size_t size, 2425 * struct pcmcia_mem_handle *pcmhp) 2426 * 2427 * This function only allocates memory region for pccard. This 2428 * function never maps the allocated region to pccard memory area. 2429 * 2430 * XXX: Why the argument of start address is not in? 2431 */ 2432 STATIC int 2433 pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 2434 struct pcmcia_mem_handle *pcmhp) 2435 { 2436 struct pcic_handle *ph = (struct pcic_handle *)pch; 2437 bus_space_handle_t memh; 2438 bus_addr_t addr; 2439 bus_size_t sizepg; 2440 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2441 #if rbus 2442 rbus_tag_t rb; 2443 #endif 2444 2445 /* Check that the card is still there. */ 2446 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2447 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2448 return 1; 2449 2450 /* out of sc->memh, allocate as many pages as necessary */ 2451 2452 /* convert size to PCIC pages */ 2453 /* 2454 * This is not enough; when the requested region is on the page 2455 * boundaries, this may calculate wrong result. 2456 */ 2457 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2458 #if 0 2459 if (sizepg > PCIC_MAX_MEM_PAGES) { 2460 return 1; 2461 } 2462 #endif 2463 2464 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2465 return 1; 2466 } 2467 2468 addr = 0; /* XXX gcc -Wuninitialized */ 2469 2470 #if rbus 2471 rb = sc->sc_rbus_memt; 2472 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2473 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2474 &addr, &memh)) { 2475 return 1; 2476 } 2477 #else 2478 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2479 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2480 0, /* boundary */ 2481 0, /* flags */ 2482 &addr, &memh)) { 2483 return 1; 2484 } 2485 #endif 2486 2487 DPRINTF(("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, " 2488 "realsize 0x%lx\n", (unsigned long)addr, (unsigned long)size, 2489 (unsigned long)sizepg * PCIC_MEM_PAGESIZE)); 2490 2491 pcmhp->memt = sc->sc_memt; 2492 pcmhp->memh = memh; 2493 pcmhp->addr = addr; 2494 pcmhp->size = size; 2495 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2496 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2497 pcmhp->mhandle = 0; 2498 /* No offset??? Funny. */ 2499 2500 return 0; 2501 } 2502 2503 /* 2504 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2505 * struct pcmcia_mem_handle *pcmhp) 2506 * 2507 * This function release the memory space allocated by the function 2508 * pccbb_pcmcia_mem_alloc(). 2509 */ 2510 STATIC void 2511 pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2512 struct pcmcia_mem_handle *pcmhp) 2513 { 2514 #if rbus 2515 struct pcic_handle *ph = (struct pcic_handle *)pch; 2516 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2517 2518 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2519 #else 2520 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2521 #endif 2522 } 2523 2524 /* 2525 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2526 * 2527 * This function release the memory space allocated by the function 2528 * pccbb_pcmcia_mem_alloc(). 2529 */ 2530 STATIC void 2531 pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2532 { 2533 int regbase_win; 2534 bus_addr_t phys_addr; 2535 bus_addr_t phys_end; 2536 2537 #define PCIC_SMM_START_LOW 0 2538 #define PCIC_SMM_START_HIGH 1 2539 #define PCIC_SMM_STOP_LOW 2 2540 #define PCIC_SMM_STOP_HIGH 3 2541 #define PCIC_CMA_LOW 4 2542 #define PCIC_CMA_HIGH 5 2543 2544 u_int8_t start_low, start_high = 0; 2545 u_int8_t stop_low, stop_high; 2546 u_int8_t off_low, off_high; 2547 u_int8_t mem_window; 2548 int reg; 2549 2550 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2551 int mem8 = 2552 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2553 || (kind == PCMCIA_MEM_ATTR); 2554 2555 regbase_win = 0x10 + win * 0x08; 2556 2557 phys_addr = ph->mem[win].addr; 2558 phys_end = phys_addr + ph->mem[win].size; 2559 2560 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2561 (unsigned long)phys_addr, (unsigned long)phys_end, 2562 (unsigned long)ph->mem[win].offset)); 2563 2564 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2565 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2566 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2567 2568 /* bit 19:12 */ 2569 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2570 /* bit 23:20 and bit 7 on */ 2571 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2572 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2573 /* bit 31:24, for 32-bit address */ 2574 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2575 2576 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2577 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2578 2579 if (((struct pccbb_softc *)ph-> 2580 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2581 Pcic_write(ph, 0x40 + win, mem_window); 2582 } 2583 2584 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2585 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2586 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2587 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2588 2589 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2590 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2591 2592 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2593 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2594 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2595 | ((kind == PCMCIA_MEM_ATTR) ? 2596 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2597 2598 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2599 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2600 2601 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2602 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2603 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2604 2605 #if defined(CBB_DEBUG) 2606 { 2607 int r1, r2, r3, r4, r5, r6, r7 = 0; 2608 2609 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2610 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2611 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2612 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2613 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2614 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2615 if (((struct pccbb_softc *)(ph-> 2616 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2617 r7 = Pcic_read(ph, 0x40 + win); 2618 } 2619 2620 printf("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2621 "%02x%02x", win, r1, r2, r3, r4, r5, r6); 2622 if (((struct pccbb_softc *)(ph-> 2623 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2624 printf(" %02x", r7); 2625 } 2626 printf("\n"); 2627 } 2628 #endif 2629 } 2630 2631 /* 2632 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2633 * bus_addr_t card_addr, bus_size_t size, 2634 * struct pcmcia_mem_handle *pcmhp, 2635 * bus_addr_t *offsetp, int *windowp) 2636 * 2637 * This function maps memory space allocated by the function 2638 * pccbb_pcmcia_mem_alloc(). 2639 */ 2640 STATIC int 2641 pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2642 bus_addr_t card_addr, bus_size_t size, struct pcmcia_mem_handle *pcmhp, 2643 bus_addr_t *offsetp, int *windowp) 2644 { 2645 struct pcic_handle *ph = (struct pcic_handle *)pch; 2646 bus_addr_t busaddr; 2647 long card_offset; 2648 int win; 2649 2650 /* Check that the card is still there. */ 2651 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2652 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2653 return 1; 2654 2655 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2656 if ((ph->memalloc & (1 << win)) == 0) { 2657 ph->memalloc |= (1 << win); 2658 break; 2659 } 2660 } 2661 2662 if (win == PCIC_MEM_WINS) { 2663 return 1; 2664 } 2665 2666 *windowp = win; 2667 2668 /* XXX this is pretty gross */ 2669 2670 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2671 panic("pccbb_pcmcia_mem_map memt is bogus"); 2672 } 2673 2674 busaddr = pcmhp->addr; 2675 2676 /* 2677 * compute the address offset to the pcmcia address space for the 2678 * pcic. this is intentionally signed. The masks and shifts below 2679 * will cause TRT to happen in the pcic registers. Deal with making 2680 * sure the address is aligned, and return the alignment offset. 2681 */ 2682 2683 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2684 card_addr -= *offsetp; 2685 2686 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2687 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2688 (u_long) card_addr)); 2689 2690 /* 2691 * include the offset in the size, and decrement size by one, since 2692 * the hw wants start/stop 2693 */ 2694 size += *offsetp - 1; 2695 2696 card_offset = (((long)card_addr) - ((long)busaddr)); 2697 2698 ph->mem[win].addr = busaddr; 2699 ph->mem[win].size = size; 2700 ph->mem[win].offset = card_offset; 2701 ph->mem[win].kind = kind; 2702 2703 pccbb_pcmcia_do_mem_map(ph, win); 2704 2705 return 0; 2706 } 2707 2708 /* 2709 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2710 * int window) 2711 * 2712 * This function unmaps memory space which mapped by the function 2713 * pccbb_pcmcia_mem_map(). 2714 */ 2715 STATIC void 2716 pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, int window) 2717 { 2718 struct pcic_handle *ph = (struct pcic_handle *)pch; 2719 int reg; 2720 2721 if (window >= PCIC_MEM_WINS) { 2722 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2723 } 2724 2725 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2726 reg &= ~(1 << window); 2727 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2728 2729 ph->memalloc &= ~(1 << window); 2730 } 2731 2732 #if defined PCCBB_PCMCIA_POLL 2733 struct pccbb_poll_str { 2734 void *arg; 2735 int (*func)(void *); 2736 int level; 2737 struct pcic_handle *ph; 2738 int count; 2739 int num; 2740 struct callout poll_ch; 2741 }; 2742 2743 static struct pccbb_poll_str pccbb_poll[10]; 2744 static int pccbb_poll_n = 0; 2745 2746 static void pccbb_pcmcia_poll(void *arg); 2747 2748 static void 2749 pccbb_pcmcia_poll(void *arg) 2750 { 2751 struct pccbb_poll_str *poll = arg; 2752 struct pcic_handle *ph = poll->ph; 2753 struct pccbb_softc *sc = ph->sc; 2754 int s; 2755 u_int32_t spsr; /* socket present-state reg */ 2756 2757 callout_reset(&poll->poll_ch, hz * 2, pccbb_pcmcia_poll, arg); 2758 switch (poll->level) { 2759 case IPL_NET: 2760 s = splnet(); 2761 break; 2762 case IPL_BIO: 2763 s = splbio(); 2764 break; 2765 case IPL_TTY: /* fallthrough */ 2766 default: 2767 s = spltty(); 2768 break; 2769 } 2770 2771 spsr = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2772 CB_SOCKET_STAT); 2773 2774 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2775 if (!(spsr & 0x40)) /* CINT low */ 2776 #else 2777 if (1) 2778 #endif 2779 { 2780 if ((*poll->func) (poll->arg) > 0) { 2781 ++poll->count; 2782 /* printf("intr: reported from poller, 0x%x\n", spsr); */ 2783 #if defined LEVEL2 2784 } else { 2785 printf("intr: miss! 0x%x\n", spsr); 2786 #endif 2787 } 2788 } 2789 splx(s); 2790 } 2791 #endif /* defined CB_PCMCIA_POLL */ 2792 2793 /* 2794 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2795 * struct pcmcia_function *pf, 2796 * int ipl, 2797 * int (*func)(void *), 2798 * void *arg); 2799 * 2800 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2801 */ 2802 STATIC void * 2803 pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2804 struct pcmcia_function *pf, int ipl, int (*func)(void *), void *arg) 2805 { 2806 struct pcic_handle *ph = (struct pcic_handle *)pch; 2807 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2808 2809 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2810 /* what should I do? */ 2811 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2812 DPRINTF(("%s does not provide edge nor pulse " 2813 "interrupt\n", sc->sc_dev.dv_xname)); 2814 return NULL; 2815 } 2816 /* 2817 * XXX Noooooo! The interrupt flag must set properly!! 2818 * dumb pcmcia driver!! 2819 */ 2820 } 2821 2822 return pccbb_intr_establish(sc, 0, ipl, func, arg); 2823 } 2824 2825 /* 2826 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2827 * void *ih) 2828 * 2829 * This function disables PC-Card interrupt. 2830 */ 2831 STATIC void 2832 pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 2833 { 2834 struct pcic_handle *ph = (struct pcic_handle *)pch; 2835 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2836 2837 pccbb_intr_disestablish(sc, ih); 2838 } 2839 2840 #if rbus 2841 /* 2842 * static int 2843 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2844 * bus_addr_t addr, bus_size_t size, 2845 * bus_addr_t mask, bus_size_t align, 2846 * int flags, bus_addr_t *addrp; 2847 * bus_space_handle_t *bshp) 2848 * 2849 * This function allocates a portion of memory or io space for 2850 * clients. This function is called from CardBus card drivers. 2851 */ 2852 static int 2853 pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2854 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 2855 int flags, bus_addr_t *addrp, bus_space_handle_t *bshp) 2856 { 2857 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2858 2859 DPRINTF(("pccbb_rbus_cb_space_alloc: addr 0x%lx, size 0x%lx, " 2860 "mask 0x%lx, align 0x%lx\n", (unsigned long)addr, 2861 (unsigned long)size, (unsigned long)mask, (unsigned long)align)); 2862 2863 if (align == 0) { 2864 align = size; 2865 } 2866 2867 if (rb->rb_bt == sc->sc_memt) { 2868 if (align < 16) { 2869 return 1; 2870 } 2871 /* 2872 * XXX: align more than 0x1000 to avoid overwrapping 2873 * memory windows for two or more devices. 0x1000 2874 * means memory window's granularity. 2875 * 2876 * Two or more devices should be able to share same 2877 * memory window region. However, overrapping memory 2878 * window is not good because some devices, such as 2879 * 3Com 3C575[BC], have a broken address decoder and 2880 * intrude other's memory region. 2881 */ 2882 if (align < 0x1000) { 2883 align = 0x1000; 2884 } 2885 } else if (rb->rb_bt == sc->sc_iot) { 2886 if (align < 4) { 2887 return 1; 2888 } 2889 /* XXX: hack for avoiding ISA image */ 2890 if (mask < 0x0100) { 2891 mask = 0x3ff; 2892 addr = 0x300; 2893 } 2894 2895 } else { 2896 DPRINTF(("pccbb_rbus_cb_space_alloc: Bus space tag 0x%lx is " 2897 "NOT used. io: 0x%lx, mem: 0x%lx\n", 2898 (unsigned long)rb->rb_bt, (unsigned long)sc->sc_iot, 2899 (unsigned long)sc->sc_memt)); 2900 return 1; 2901 /* XXX: panic here? */ 2902 } 2903 2904 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 2905 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 2906 return 1; 2907 } 2908 2909 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 2910 2911 return 0; 2912 } 2913 2914 /* 2915 * static int 2916 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 2917 * bus_space_handle_t *bshp, bus_size_t size); 2918 * 2919 * This function is called from CardBus card drivers. 2920 */ 2921 static int 2922 pccbb_rbus_cb_space_free(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2923 bus_space_handle_t bsh, bus_size_t size) 2924 { 2925 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2926 bus_space_tag_t bt = rb->rb_bt; 2927 2928 pccbb_close_win(sc, bt, bsh, size); 2929 2930 if (bt == sc->sc_memt) { 2931 } else if (bt == sc->sc_iot) { 2932 } else { 2933 return 1; 2934 /* XXX: panic here? */ 2935 } 2936 2937 return rbus_space_free(rb, bsh, size, NULL); 2938 } 2939 #endif /* rbus */ 2940 2941 #if rbus 2942 2943 static int 2944 pccbb_open_win(struct pccbb_softc *sc, bus_space_tag_t bst, bus_addr_t addr, 2945 bus_size_t size, bus_space_handle_t bsh, int flags) 2946 { 2947 struct pccbb_win_chain_head *head; 2948 bus_addr_t align; 2949 2950 head = &sc->sc_iowindow; 2951 align = 0x04; 2952 if (sc->sc_memt == bst) { 2953 head = &sc->sc_memwindow; 2954 align = 0x1000; 2955 DPRINTF(("using memory window, 0x%lx 0x%lx 0x%lx\n\n", 2956 (unsigned long)sc->sc_iot, (unsigned long)sc->sc_memt, 2957 (unsigned long)bst)); 2958 } 2959 2960 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 2961 printf("%s: pccbb_open_win: %s winlist insert failed\n", 2962 sc->sc_dev.dv_xname, 2963 (head == &sc->sc_memwindow) ? "mem" : "io"); 2964 } 2965 pccbb_winset(align, sc, bst); 2966 2967 return 0; 2968 } 2969 2970 static int 2971 pccbb_close_win(struct pccbb_softc *sc, bus_space_tag_t bst, 2972 bus_space_handle_t bsh, bus_size_t size) 2973 { 2974 struct pccbb_win_chain_head *head; 2975 bus_addr_t align; 2976 2977 head = &sc->sc_iowindow; 2978 align = 0x04; 2979 if (sc->sc_memt == bst) { 2980 head = &sc->sc_memwindow; 2981 align = 0x1000; 2982 } 2983 2984 if (pccbb_winlist_delete(head, bsh, size)) { 2985 printf("%s: pccbb_close_win: %s winlist delete failed\n", 2986 sc->sc_dev.dv_xname, 2987 (head == &sc->sc_memwindow) ? "mem" : "io"); 2988 } 2989 pccbb_winset(align, sc, bst); 2990 2991 return 0; 2992 } 2993 2994 static int 2995 pccbb_winlist_insert(struct pccbb_win_chain_head *head, bus_addr_t start, 2996 bus_size_t size, bus_space_handle_t bsh, int flags) 2997 { 2998 struct pccbb_win_chain *chainp, *elem; 2999 3000 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 3001 M_NOWAIT)) == NULL) 3002 return (1); /* fail */ 3003 3004 elem->wc_start = start; 3005 elem->wc_end = start + (size - 1); 3006 elem->wc_handle = bsh; 3007 elem->wc_flags = flags; 3008 3009 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3010 chainp = TAILQ_NEXT(chainp, wc_list)) { 3011 if (chainp->wc_end < start) 3012 continue; 3013 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 3014 return (0); 3015 } 3016 3017 TAILQ_INSERT_TAIL(head, elem, wc_list); 3018 return (0); 3019 } 3020 3021 static int 3022 pccbb_winlist_delete(struct pccbb_win_chain_head *head, bus_space_handle_t bsh, 3023 bus_size_t size) 3024 { 3025 struct pccbb_win_chain *chainp; 3026 3027 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3028 chainp = TAILQ_NEXT(chainp, wc_list)) { 3029 if (memcmp(&chainp->wc_handle, &bsh, sizeof(bsh))) 3030 continue; 3031 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 3032 printf("pccbb_winlist_delete: window 0x%lx size " 3033 "inconsistent: 0x%lx, 0x%lx\n", 3034 (unsigned long)chainp->wc_start, 3035 (unsigned long)(chainp->wc_end - chainp->wc_start), 3036 (unsigned long)(size - 1)); 3037 return 1; 3038 } 3039 3040 TAILQ_REMOVE(head, chainp, wc_list); 3041 free(chainp, M_DEVBUF); 3042 3043 return 0; 3044 } 3045 3046 return 1; /* fail: no candidate to remove */ 3047 } 3048 3049 static void 3050 pccbb_winset(bus_addr_t align, struct pccbb_softc *sc, bus_space_tag_t bst) 3051 { 3052 pci_chipset_tag_t pc; 3053 pcitag_t tag; 3054 bus_addr_t mask = ~(align - 1); 3055 struct { 3056 cardbusreg_t win_start; 3057 cardbusreg_t win_limit; 3058 int win_flags; 3059 } win[2]; 3060 struct pccbb_win_chain *chainp; 3061 int offs; 3062 3063 win[0].win_start = win[1].win_start = 0xffffffff; 3064 win[0].win_limit = win[1].win_limit = 0; 3065 win[0].win_flags = win[1].win_flags = 0; 3066 3067 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3068 offs = 0x2c; 3069 if (sc->sc_memt == bst) { 3070 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3071 offs = 0x1c; 3072 } 3073 3074 if (chainp != NULL) { 3075 win[0].win_start = chainp->wc_start & mask; 3076 win[0].win_limit = chainp->wc_end & mask; 3077 win[0].win_flags = chainp->wc_flags; 3078 chainp = TAILQ_NEXT(chainp, wc_list); 3079 } 3080 3081 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3082 if (win[1].win_start == 0xffffffff) { 3083 /* window 1 is not used */ 3084 if ((win[0].win_flags == chainp->wc_flags) && 3085 (win[0].win_limit + align >= 3086 (chainp->wc_start & mask))) { 3087 /* concatenate */ 3088 win[0].win_limit = chainp->wc_end & mask; 3089 } else { 3090 /* make new window */ 3091 win[1].win_start = chainp->wc_start & mask; 3092 win[1].win_limit = chainp->wc_end & mask; 3093 win[1].win_flags = chainp->wc_flags; 3094 } 3095 continue; 3096 } 3097 3098 /* Both windows are engaged. */ 3099 if (win[0].win_flags == win[1].win_flags) { 3100 /* same flags */ 3101 if (win[0].win_flags == chainp->wc_flags) { 3102 if (win[1].win_start - (win[0].win_limit + 3103 align) < 3104 (chainp->wc_start & mask) - 3105 ((chainp->wc_end & mask) + align)) { 3106 /* 3107 * merge window 0 and 1, and set win1 3108 * to chainp 3109 */ 3110 win[0].win_limit = win[1].win_limit; 3111 win[1].win_start = 3112 chainp->wc_start & mask; 3113 win[1].win_limit = 3114 chainp->wc_end & mask; 3115 } else { 3116 win[1].win_limit = 3117 chainp->wc_end & mask; 3118 } 3119 } else { 3120 /* different flags */ 3121 3122 /* concatenate win0 and win1 */ 3123 win[0].win_limit = win[1].win_limit; 3124 /* allocate win[1] to new space */ 3125 win[1].win_start = chainp->wc_start & mask; 3126 win[1].win_limit = chainp->wc_end & mask; 3127 win[1].win_flags = chainp->wc_flags; 3128 } 3129 } else { 3130 /* the flags of win[0] and win[1] is different */ 3131 if (win[0].win_flags == chainp->wc_flags) { 3132 win[0].win_limit = chainp->wc_end & mask; 3133 /* 3134 * XXX this creates overlapping windows, so 3135 * what should the poor bridge do if one is 3136 * cachable, and the other is not? 3137 */ 3138 printf("%s: overlapping windows\n", 3139 sc->sc_dev.dv_xname); 3140 } else { 3141 win[1].win_limit = chainp->wc_end & mask; 3142 } 3143 } 3144 } 3145 3146 pc = sc->sc_pc; 3147 tag = sc->sc_tag; 3148 pci_conf_write(pc, tag, offs, win[0].win_start); 3149 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3150 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3151 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3152 DPRINTF(("--pccbb_winset: win0 [0x%lx, 0x%lx), win1 [0x%lx, 0x%lx)\n", 3153 (unsigned long)pci_conf_read(pc, tag, offs), 3154 (unsigned long)pci_conf_read(pc, tag, offs + 4) + align, 3155 (unsigned long)pci_conf_read(pc, tag, offs + 8), 3156 (unsigned long)pci_conf_read(pc, tag, offs + 12) + align)); 3157 3158 if (bst == sc->sc_memt) { 3159 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BRIDGE_CONTROL_REG); 3160 3161 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 3162 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 3163 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3164 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 3165 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3166 pci_conf_write(pc, tag, PCI_BRIDGE_CONTROL_REG, bcr); 3167 } 3168 } 3169 3170 #endif /* rbus */ 3171 3172 static bool 3173 pccbb_suspend(device_t dv) 3174 { 3175 struct pccbb_softc *sc = device_private(dv); 3176 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3177 bus_space_handle_t base_memh = sc->sc_base_memh; 3178 pcireg_t reg; 3179 3180 if (sc->sc_pil_intr_enable) 3181 (void)pccbbintr_function(sc); 3182 sc->sc_pil_intr_enable = 0; 3183 3184 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3185 /* Disable interrupts. */ 3186 reg &= ~(CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER); 3187 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3188 /* XXX joerg Disable power to the socket? */ 3189 3190 if (sc->sc_chipset == CB_RX5C47X) 3191 sc->sc_ricoh_misc_ctrl = pci_conf_read(sc->sc_pc, 3192 sc->sc_tag, RICOH_PCI_MISC_CTRL); 3193 3194 return true; 3195 } 3196 3197 static bool 3198 pccbb_resume(device_t dv) 3199 { 3200 struct pccbb_softc *sc = device_private(dv); 3201 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3202 bus_space_handle_t base_memh = sc->sc_base_memh; 3203 pcireg_t reg; 3204 3205 pccbb_chipinit(sc); 3206 /* setup memory and io space window for CB */ 3207 pccbb_winset(0x1000, sc, sc->sc_memt); 3208 pccbb_winset(0x04, sc, sc->sc_iot); 3209 if (sc->sc_chipset == CB_RX5C47X) 3210 pci_conf_write(sc->sc_pc, sc->sc_tag, 3211 RICOH_PCI_MISC_CTRL, sc->sc_ricoh_misc_ctrl); 3212 3213 /* CSC Interrupt: Card detect interrupt on */ 3214 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3215 /* Card detect intr is turned on. */ 3216 reg |= CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; 3217 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3218 /* reset interrupt */ 3219 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3220 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3221 3222 /* 3223 * check for card insertion or removal during suspend period. 3224 * XXX: the code can't cope with card swap (remove then 3225 * insert). how can we detect such situation? 3226 */ 3227 (void)pccbbintr(sc); 3228 3229 sc->sc_pil_intr_enable = 1; 3230 3231 return true; 3232 } 3233
Indexes created Tue Oct 14 21:09:58 GMT 2025