pccbb.c revision 1.145.6.5
1 /* $NetBSD: pccbb.c,v 1.145.6.5 2007/11/21 21:55:35 joerg Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: pccbb.c,v 1.145.6.5 2007/11/21 21:55:35 joerg Exp $"); 35 36 /* 37 #define CBB_DEBUG 38 #define SHOW_REGS 39 */ 40 41 /* 42 * BROKEN! 43 #define PCCBB_PCMCIA_POLL 44 #define CB_PCMCIA_POLL 45 #define CB_PCMCIA_POLL_ONLY 46 #define LEVEL2 47 */ 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/kernel.h> 52 #include <sys/errno.h> 53 #include <sys/ioctl.h> 54 #include <sys/reboot.h> /* for bootverbose */ 55 #include <sys/syslog.h> 56 #include <sys/device.h> 57 #include <sys/malloc.h> 58 #include <sys/proc.h> 59 60 #include <sys/intr.h> 61 #include <sys/bus.h> 62 63 #include <dev/pci/pcivar.h> 64 #include <dev/pci/pcireg.h> 65 #include <dev/pci/pcidevs.h> 66 67 #include <dev/pci/pccbbreg.h> 68 69 #include <dev/cardbus/cardslotvar.h> 70 71 #include <dev/cardbus/cardbusvar.h> 72 73 #include <dev/pcmcia/pcmciareg.h> 74 #include <dev/pcmcia/pcmciavar.h> 75 76 #include <dev/ic/i82365reg.h> 77 #include <dev/ic/i82365var.h> 78 #include <dev/pci/pccbbvar.h> 79 80 #include "locators.h" 81 82 #ifndef __NetBSD_Version__ 83 struct cfdriver cbb_cd = { 84 NULL, "cbb", DV_DULL 85 }; 86 #endif 87 88 #ifdef CBB_DEBUG 89 #define DPRINTF(x) printf x 90 #define STATIC 91 #else 92 #define DPRINTF(x) 93 #define STATIC static 94 #endif 95 96 int pccbb_burstup = 1; 97 98 /* 99 * delay_ms() is wait in milliseconds. It should be used instead 100 * of delay() if you want to wait more than 1 ms. 101 */ 102 static inline void 103 delay_ms(int millis, void *param) 104 { 105 if (cold) 106 delay(millis * 1000); 107 else 108 tsleep(param, PWAIT, "pccbb", MAX(2, hz * millis / 1000)); 109 } 110 111 int pcicbbmatch(struct device *, struct cfdata *, void *); 112 void pccbbattach(struct device *, struct device *, void *); 113 int pccbbintr(void *); 114 static void pci113x_insert(void *); 115 static int pccbbintr_function(struct pccbb_softc *); 116 117 static int pccbb_detect_card(struct pccbb_softc *); 118 119 static void pccbb_pcmcia_write(struct pcic_handle *, int, u_int8_t); 120 static u_int8_t pccbb_pcmcia_read(struct pcic_handle *, int); 121 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 122 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 123 124 STATIC int cb_reset(struct pccbb_softc *); 125 STATIC int cb_detect_voltage(struct pccbb_softc *); 126 STATIC int cbbprint(void *, const char *); 127 128 static int cb_chipset(u_int32_t, int *); 129 STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *, 130 struct pcmciabus_attach_args *); 131 #if 0 132 STATIC void pccbb_pcmcia_attach_card(struct pcic_handle *); 133 STATIC void pccbb_pcmcia_detach_card(struct pcic_handle *, int); 134 STATIC void pccbb_pcmcia_deactivate_card(struct pcic_handle *); 135 #endif 136 137 STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int); 138 STATIC int pccbb_power(cardbus_chipset_tag_t, int); 139 STATIC int pccbb_cardenable(struct pccbb_softc * sc, int function); 140 #if !rbus 141 static int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 142 static int pccbb_io_close(cardbus_chipset_tag_t, int); 143 static int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 144 static int pccbb_mem_close(cardbus_chipset_tag_t, int); 145 #endif /* !rbus */ 146 static void *pccbb_intr_establish(struct pccbb_softc *, int irq, 147 int level, int (*ih) (void *), void *sc); 148 static void pccbb_intr_disestablish(struct pccbb_softc *, void *ih); 149 150 static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t, int irq, 151 int level, int (*ih) (void *), void *sc); 152 static void pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih); 153 154 static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t, int, int); 155 static void pccbb_free_tag(cardbus_chipset_tag_t, cardbustag_t); 156 static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t, cardbustag_t, int); 157 static void pccbb_conf_write(cardbus_chipset_tag_t, cardbustag_t, int, 158 cardbusreg_t); 159 static void pccbb_chipinit(struct pccbb_softc *); 160 161 STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 162 struct pcmcia_mem_handle *); 163 STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t, 164 struct pcmcia_mem_handle *); 165 STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 166 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *); 167 STATIC void pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t, int); 168 STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 169 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 170 STATIC void pccbb_pcmcia_io_free(pcmcia_chipset_handle_t, 171 struct pcmcia_io_handle *); 172 STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 173 bus_size_t, struct pcmcia_io_handle *, int *); 174 STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t, int); 175 STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t, 176 struct pcmcia_function *, int, int (*)(void *), void *); 177 STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t, void *); 178 STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t); 179 STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t); 180 STATIC void pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t, int); 181 STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch); 182 183 static int pccbb_pcmcia_wait_ready(struct pcic_handle *); 184 static void pccbb_pcmcia_delay(struct pcic_handle *, int, const char *); 185 186 static void pccbb_pcmcia_do_io_map(struct pcic_handle *, int); 187 static void pccbb_pcmcia_do_mem_map(struct pcic_handle *, int); 188 189 /* bus-space allocation and deallocation functions */ 190 #if rbus 191 192 static int pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t, rbus_tag_t, 193 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 194 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp); 195 static int pccbb_rbus_cb_space_free(cardbus_chipset_tag_t, rbus_tag_t, 196 bus_space_handle_t, bus_size_t); 197 198 #endif /* rbus */ 199 200 #if rbus 201 202 static int pccbb_open_win(struct pccbb_softc *, bus_space_tag_t, 203 bus_addr_t, bus_size_t, bus_space_handle_t, int flags); 204 static int pccbb_close_win(struct pccbb_softc *, bus_space_tag_t, 205 bus_space_handle_t, bus_size_t); 206 static int pccbb_winlist_insert(struct pccbb_win_chain_head *, bus_addr_t, 207 bus_size_t, bus_space_handle_t, int); 208 static int pccbb_winlist_delete(struct pccbb_win_chain_head *, 209 bus_space_handle_t, bus_size_t); 210 static void pccbb_winset(bus_addr_t align, struct pccbb_softc *, 211 bus_space_tag_t); 212 void pccbb_winlist_show(struct pccbb_win_chain *); 213 214 #endif /* rbus */ 215 216 /* for config_defer */ 217 static void pccbb_pci_callback(struct device *); 218 219 static bool pccbb_suspend(device_t); 220 static bool pccbb_resume(device_t); 221 222 #if defined SHOW_REGS 223 static void cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, 224 bus_space_tag_t memt, bus_space_handle_t memh); 225 #endif 226 227 CFATTACH_DECL(cbb_pci, sizeof(struct pccbb_softc), 228 pcicbbmatch, pccbbattach, NULL, NULL); 229 230 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 231 pccbb_pcmcia_mem_alloc, 232 pccbb_pcmcia_mem_free, 233 pccbb_pcmcia_mem_map, 234 pccbb_pcmcia_mem_unmap, 235 pccbb_pcmcia_io_alloc, 236 pccbb_pcmcia_io_free, 237 pccbb_pcmcia_io_map, 238 pccbb_pcmcia_io_unmap, 239 pccbb_pcmcia_intr_establish, 240 pccbb_pcmcia_intr_disestablish, 241 pccbb_pcmcia_socket_enable, 242 pccbb_pcmcia_socket_disable, 243 pccbb_pcmcia_socket_settype, 244 pccbb_pcmcia_card_detect 245 }; 246 247 #if rbus 248 static struct cardbus_functions pccbb_funcs = { 249 pccbb_rbus_cb_space_alloc, 250 pccbb_rbus_cb_space_free, 251 pccbb_cb_intr_establish, 252 pccbb_cb_intr_disestablish, 253 pccbb_ctrl, 254 pccbb_power, 255 pccbb_make_tag, 256 pccbb_free_tag, 257 pccbb_conf_read, 258 pccbb_conf_write, 259 }; 260 #else 261 static struct cardbus_functions pccbb_funcs = { 262 pccbb_ctrl, 263 pccbb_power, 264 pccbb_mem_open, 265 pccbb_mem_close, 266 pccbb_io_open, 267 pccbb_io_close, 268 pccbb_cb_intr_establish, 269 pccbb_cb_intr_disestablish, 270 pccbb_make_tag, 271 pccbb_conf_read, 272 pccbb_conf_write, 273 }; 274 #endif 275 276 int 277 pcicbbmatch(struct device *parent, struct cfdata *match, void *aux) 278 { 279 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 280 281 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 282 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 283 PCI_INTERFACE(pa->pa_class) == 0) { 284 return 1; 285 } 286 287 return 0; 288 } 289 290 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 291 | ((prod) << PCI_PRODUCT_SHIFT)) 292 293 const struct yenta_chipinfo { 294 pcireg_t yc_id; /* vendor tag | product tag */ 295 int yc_chiptype; 296 int yc_flags; 297 } yc_chipsets[] = { 298 /* Texas Instruments chips */ 299 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 300 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 301 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 302 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 303 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI125X, 304 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 305 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 306 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 307 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 308 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 309 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 310 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 311 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI125X, 312 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 313 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI125X, 314 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 315 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 316 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 317 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 318 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 319 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI1420, 320 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 321 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI125X, 322 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 323 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 324 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 325 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1520), CB_TI12XX, 326 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 327 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4410YENTA), CB_TI12XX, 328 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 329 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4520YENTA), CB_TI12XX, 330 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 331 332 /* Ricoh chips */ 333 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 334 PCCBB_PCMCIA_MEM_32}, 335 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 336 PCCBB_PCMCIA_MEM_32}, 337 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 338 PCCBB_PCMCIA_MEM_32}, 339 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 340 PCCBB_PCMCIA_MEM_32}, 341 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 342 PCCBB_PCMCIA_MEM_32}, 343 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 344 PCCBB_PCMCIA_MEM_32}, 345 346 /* Toshiba products */ 347 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 348 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 349 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 350 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 351 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 352 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 353 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 354 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 355 356 /* Cirrus Logic products */ 357 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 358 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 359 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 360 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 361 362 /* sentinel, or Generic chip */ 363 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 364 }; 365 366 static int 367 cb_chipset(u_int32_t pci_id, int *flagp) 368 { 369 const struct yenta_chipinfo *yc; 370 371 /* Loop over except the last default entry. */ 372 for (yc = yc_chipsets; yc < yc_chipsets + 373 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 374 if (pci_id == yc->yc_id) 375 break; 376 377 if (flagp != NULL) 378 *flagp = yc->yc_flags; 379 380 return (yc->yc_chiptype); 381 } 382 383 void 384 pccbbattach(struct device *parent, struct device *self, void *aux) 385 { 386 struct pccbb_softc *sc = (void *)self; 387 struct pci_attach_args *pa = aux; 388 pci_chipset_tag_t pc = pa->pa_pc; 389 pcireg_t busreg, reg, sock_base; 390 bus_addr_t sockbase; 391 char devinfo[256]; 392 int flags; 393 394 #ifdef __HAVE_PCCBB_ATTACH_HOOK 395 pccbb_attach_hook(parent, self, pa); 396 #endif 397 398 callout_init(&sc->sc_insert_ch, 0); 399 callout_setfunc(&sc->sc_insert_ch, pci113x_insert, sc); 400 401 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 402 403 pci_devinfo(pa->pa_id, 0, 0, devinfo, sizeof(devinfo)); 404 printf(": %s (rev. 0x%02x)", devinfo, PCI_REVISION(pa->pa_class)); 405 DPRINTF((" (chipflags %x)", flags)); 406 printf("\n"); 407 408 TAILQ_INIT(&sc->sc_memwindow); 409 TAILQ_INIT(&sc->sc_iowindow); 410 411 #if rbus 412 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 413 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 414 415 #if 0 416 printf("pa->pa_memt: %08x vs rbus_mem->rb_bt: %08x\n", 417 pa->pa_memt, sc->sc_rbus_memt->rb_bt); 418 #endif 419 #endif /* rbus */ 420 421 sc->sc_flags &= ~CBB_MEMHMAPPED; 422 423 /* 424 * MAP socket registers and ExCA registers on memory-space 425 * When no valid address is set on socket base registers (on pci 426 * config space), get it not polite way. 427 */ 428 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 429 430 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 431 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 432 /* The address must be valid. */ 433 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 434 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL)) { 435 printf("%s: can't map socket base address 0x%lx\n", 436 sc->sc_dev.dv_xname, (unsigned long)sock_base); 437 /* 438 * I think it's funny: socket base registers must be 439 * mapped on memory space, but ... 440 */ 441 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 442 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 443 NULL)) { 444 printf("%s: can't map socket base address" 445 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 446 (unsigned long)sockbase); 447 /* give up... allocate reg space via rbus. */ 448 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 449 } else 450 sc->sc_flags |= CBB_MEMHMAPPED; 451 } else { 452 DPRINTF(("%s: socket base address 0x%lx\n", 453 sc->sc_dev.dv_xname, (unsigned long)sockbase)); 454 sc->sc_flags |= CBB_MEMHMAPPED; 455 } 456 } 457 458 sc->sc_mem_start = 0; /* XXX */ 459 sc->sc_mem_end = 0xffffffff; /* XXX */ 460 461 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 462 463 /* pccbb_machdep.c end */ 464 465 #if defined CBB_DEBUG 466 { 467 static const char *intrname[] = { "NON", "A", "B", "C", "D" }; 468 printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname, 469 intrname[pa->pa_intrpin], pa->pa_intrline); 470 } 471 #endif 472 473 /* setup softc */ 474 sc->sc_pc = pc; 475 sc->sc_iot = pa->pa_iot; 476 sc->sc_memt = pa->pa_memt; 477 sc->sc_dmat = pa->pa_dmat; 478 sc->sc_tag = pa->pa_tag; 479 sc->sc_function = pa->pa_function; 480 481 memcpy(&sc->sc_pa, pa, sizeof(*pa)); 482 483 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 484 485 /* Disable legacy register mapping. */ 486 switch (sc->sc_chipset) { 487 case CB_RX5C46X: /* fallthrough */ 488 #if 0 489 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 490 case CB_RX5C47X: 491 #endif 492 /* 493 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 494 * cannot be disabled by substituting 0 into PCI_LEGACY 495 * register. Ricoh CardBus bridges have special bits on Bridge 496 * control reg (addr 0x3e on PCI config space). 497 */ 498 reg = pci_conf_read(pc, pa->pa_tag, PCI_BRIDGE_CONTROL_REG); 499 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 500 pci_conf_write(pc, pa->pa_tag, PCI_BRIDGE_CONTROL_REG, reg); 501 break; 502 503 default: 504 /* XXX I don't know proper way to kill legacy I/O. */ 505 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 506 break; 507 } 508 509 if (!pnp_device_register(self, pccbb_suspend, pccbb_resume)) 510 aprint_error_dev(self, "couldn't establish power handler\n"); 511 512 config_defer(self, pccbb_pci_callback); 513 } 514 515 516 517 518 /* 519 * static void pccbb_pci_callback(struct device *self) 520 * 521 * The actual attach routine: get memory space for YENTA register 522 * space, setup YENTA register and route interrupt. 523 * 524 * This function should be deferred because this device may obtain 525 * memory space dynamically. This function must avoid obtaining 526 * memory area which has already kept for another device. 527 */ 528 static void 529 pccbb_pci_callback(struct device *self) 530 { 531 struct pccbb_softc *sc = (void *)self; 532 pci_chipset_tag_t pc = sc->sc_pc; 533 pci_intr_handle_t ih; 534 const char *intrstr = NULL; 535 bus_addr_t sockbase; 536 struct cbslot_attach_args cba; 537 struct pcmciabus_attach_args paa; 538 struct cardslot_attach_args caa; 539 struct cardslot_softc *csc; 540 541 if (!(sc->sc_flags & CBB_MEMHMAPPED)) { 542 /* The socket registers aren't mapped correctly. */ 543 #if rbus 544 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 545 (sc->sc_chipset == CB_RX5C47X 546 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 547 0, &sockbase, &sc->sc_base_memh)) { 548 return; 549 } 550 sc->sc_base_memt = sc->sc_memt; 551 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 552 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 553 sc->sc_dev.dv_xname, (unsigned long)sockbase, 554 (unsigned long)pci_conf_read(pc, sc->sc_tag, 555 PCI_SOCKBASE))); 556 #else 557 sc->sc_base_memt = sc->sc_memt; 558 #if !defined CBB_PCI_BASE 559 #define CBB_PCI_BASE 0x20000000 560 #endif 561 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 562 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 563 /* cannot allocate memory space */ 564 return; 565 } 566 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 567 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 568 sc->sc_dev.dv_xname, (unsigned long)sock_base, 569 (unsigned long)pci_conf_read(pc, 570 sc->sc_tag, PCI_SOCKBASE))); 571 #endif 572 sc->sc_flags |= CBB_MEMHMAPPED; 573 } 574 575 /* bus bridge initialization */ 576 pccbb_chipinit(sc); 577 578 /* clear data structure for child device interrupt handlers */ 579 LIST_INIT(&sc->sc_pil); 580 sc->sc_pil_intr_enable = 1; 581 582 /* Map and establish the interrupt. */ 583 if (pci_intr_map(&sc->sc_pa, &ih)) { 584 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 585 return; 586 } 587 intrstr = pci_intr_string(pc, ih); 588 589 /* 590 * XXX pccbbintr should be called under the priority lower 591 * than any other hard interupts. 592 */ 593 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 594 595 if (sc->sc_ih == NULL) { 596 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 597 if (intrstr != NULL) { 598 printf(" at %s", intrstr); 599 } 600 printf("\n"); 601 return; 602 } 603 604 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 605 606 { 607 u_int32_t sockstat; 608 609 sockstat = bus_space_read_4(sc->sc_base_memt, 610 sc->sc_base_memh, CB_SOCKET_STAT); 611 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 612 sc->sc_flags |= CBB_CARDEXIST; 613 } 614 } 615 616 /* 617 * attach cardbus 618 */ 619 { 620 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 621 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 622 623 /* initialize cbslot_attach */ 624 cba.cba_busname = "cardbus"; 625 cba.cba_iot = sc->sc_iot; 626 cba.cba_memt = sc->sc_memt; 627 cba.cba_dmat = sc->sc_dmat; 628 cba.cba_bus = (busreg >> 8) & 0x0ff; 629 cba.cba_cc = (void *)sc; 630 cba.cba_cf = &pccbb_funcs; 631 cba.cba_intrline = sc->sc_pa.pa_intrline; 632 633 #if rbus 634 cba.cba_rbus_iot = sc->sc_rbus_iot; 635 cba.cba_rbus_memt = sc->sc_rbus_memt; 636 #endif 637 638 cba.cba_cacheline = PCI_CACHELINE(bhlc); 639 cba.cba_max_lattimer = PCI_LATTIMER(bhlc); 640 641 if (bootverbose) { 642 printf("%s: cacheline 0x%x lattimer 0x%x\n", 643 sc->sc_dev.dv_xname, cba.cba_cacheline, 644 cba.cba_max_lattimer); 645 printf("%s: bhlc 0x%x\n", 646 device_xname(&sc->sc_dev), bhlc); 647 } 648 #if defined SHOW_REGS 649 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 650 sc->sc_base_memh); 651 #endif 652 } 653 654 pccbb_pcmcia_attach_setup(sc, &paa); 655 caa.caa_cb_attach = NULL; 656 if (cba.cba_bus == 0) 657 printf("%s: secondary bus number uninitialized; try PCI_BUS_FIXUP\n", sc->sc_dev.dv_xname); 658 else 659 caa.caa_cb_attach = &cba; 660 caa.caa_16_attach = &paa; 661 caa.caa_ph = &sc->sc_pcmcia_h; 662 663 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 664 DPRINTF(("%s: found cardslot\n", __func__)); 665 sc->sc_csc = csc; 666 } 667 668 return; 669 } 670 671 672 673 674 675 /* 676 * static void pccbb_chipinit(struct pccbb_softc *sc) 677 * 678 * This function initialize YENTA chip registers listed below: 679 * 1) PCI command reg, 680 * 2) PCI and CardBus latency timer, 681 * 3) route PCI interrupt, 682 * 4) close all memory and io windows. 683 * 5) turn off bus power. 684 * 6) card detect and power cycle interrupts on. 685 * 7) clear interrupt 686 */ 687 static void 688 pccbb_chipinit(struct pccbb_softc *sc) 689 { 690 pci_chipset_tag_t pc = sc->sc_pc; 691 pcitag_t tag = sc->sc_tag; 692 bus_space_tag_t bmt = sc->sc_base_memt; 693 bus_space_handle_t bmh = sc->sc_base_memh; 694 pcireg_t bcr, bhlc, cbctl, csr, lscp, mfunc, mrburst, slotctl, sockctl, 695 sockmask, sysctrl; 696 697 /* 698 * Set PCI command reg. 699 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 700 */ 701 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 702 /* I believe it is harmless. */ 703 csr |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 704 PCI_COMMAND_MASTER_ENABLE); 705 csr |= (PCI_COMMAND_PARITY_ENABLE|PCI_COMMAND_SERR_ENABLE); 706 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 707 708 /* 709 * Set CardBus latency timer. 710 */ 711 lscp = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 712 if (PCI_CB_LATENCY(lscp) < 0x20) { 713 lscp &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 714 lscp |= (0x20 << PCI_CB_LATENCY_SHIFT); 715 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, lscp); 716 } 717 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 718 PCI_CB_LATENCY(lscp), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 719 720 /* 721 * Set PCI latency timer. 722 */ 723 bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG); 724 if (PCI_LATTIMER(bhlc) < 0x10) { 725 bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 726 bhlc |= (0x10 << PCI_LATTIMER_SHIFT); 727 pci_conf_write(pc, tag, PCI_BHLC_REG, bhlc); 728 } 729 DPRINTF(("PCI latency timer 0x%x (%x)\n", 730 PCI_LATTIMER(bhlc), pci_conf_read(pc, tag, PCI_BHLC_REG))); 731 732 733 /* Route functional interrupts to PCI. */ 734 bcr = pci_conf_read(pc, tag, PCI_BRIDGE_CONTROL_REG); 735 bcr |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 736 bcr |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 737 /* assert reset */ 738 bcr |= PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT; 739 /* Set master abort mode to 1, forward SERR# from secondary 740 * to primary, and detect parity errors on secondary. 741 */ 742 bcr |= PCI_BRIDGE_CONTROL_MABRT << PCI_BRIDGE_CONTROL_SHIFT; 743 bcr |= PCI_BRIDGE_CONTROL_SERR << PCI_BRIDGE_CONTROL_SHIFT; 744 bcr |= PCI_BRIDGE_CONTROL_PERE << PCI_BRIDGE_CONTROL_SHIFT; 745 pci_conf_write(pc, tag, PCI_BRIDGE_CONTROL_REG, bcr); 746 747 switch (sc->sc_chipset) { 748 case CB_TI113X: 749 cbctl = pci_conf_read(pc, tag, PCI_CBCTRL); 750 /* This bit is shared, but may read as 0 on some chips, so set 751 it explicitly on both functions. */ 752 cbctl |= PCI113X_CBCTRL_PCI_IRQ_ENA; 753 /* CSC intr enable */ 754 cbctl |= PCI113X_CBCTRL_PCI_CSC; 755 /* functional intr prohibit | prohibit ISA routing */ 756 cbctl &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 757 pci_conf_write(pc, tag, PCI_CBCTRL, cbctl); 758 break; 759 760 case CB_TI1420: 761 sysctrl = pci_conf_read(pc, tag, PCI_SYSCTRL); 762 mrburst = pccbb_burstup 763 ? PCI1420_SYSCTRL_MRBURST : PCI1420_SYSCTRL_MRBURSTDN; 764 if ((sysctrl & PCI1420_SYSCTRL_MRBURST) == mrburst) { 765 printf("%s: %swrite bursts enabled\n", 766 device_xname(&sc->sc_dev), 767 pccbb_burstup ? "read/" : ""); 768 } else if (pccbb_burstup) { 769 printf("%s: enabling read/write bursts\n", 770 device_xname(&sc->sc_dev)); 771 sysctrl |= PCI1420_SYSCTRL_MRBURST; 772 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 773 } else { 774 printf("%s: disabling read bursts, " 775 "enabling write bursts\n", 776 device_xname(&sc->sc_dev)); 777 sysctrl |= PCI1420_SYSCTRL_MRBURSTDN; 778 sysctrl &= ~PCI1420_SYSCTRL_MRBURSTUP; 779 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 780 } 781 /*FALLTHROUGH*/ 782 case CB_TI12XX: 783 /* 784 * Some TI 12xx (and [14][45]xx) based pci cards 785 * sometimes have issues with the MFUNC register not 786 * being initialized due to a bad EEPROM on board. 787 * Laptops that this matters on have this register 788 * properly initialized. 789 * 790 * The TI125X parts have a different register. 791 */ 792 mfunc = pci_conf_read(pc, tag, PCI12XX_MFUNC); 793 if (mfunc == 0) { 794 mfunc &= ~PCI12XX_MFUNC_PIN0; 795 mfunc |= PCI12XX_MFUNC_PIN0_INTA; 796 if ((pci_conf_read(pc, tag, PCI_SYSCTRL) & 797 PCI12XX_SYSCTRL_INTRTIE) == 0) { 798 mfunc &= ~PCI12XX_MFUNC_PIN1; 799 mfunc |= PCI12XX_MFUNC_PIN1_INTB; 800 } 801 pci_conf_write(pc, tag, PCI12XX_MFUNC, mfunc); 802 } 803 /* fallthrough */ 804 805 case CB_TI125X: 806 /* 807 * Disable zoom video. Some machines initialize this 808 * improperly and experience has shown that this helps 809 * prevent strange behavior. 810 */ 811 pci_conf_write(pc, tag, PCI12XX_MMCTRL, 0); 812 813 sysctrl = pci_conf_read(pc, tag, PCI_SYSCTRL); 814 sysctrl |= PCI12XX_SYSCTRL_VCCPROT; 815 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 816 cbctl = pci_conf_read(pc, tag, PCI_CBCTRL); 817 cbctl |= PCI12XX_CBCTRL_CSC; 818 pci_conf_write(pc, tag, PCI_CBCTRL, cbctl); 819 break; 820 821 case CB_TOPIC95B: 822 sockctl = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 823 sockctl |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 824 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, sockctl); 825 slotctl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 826 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 827 sc->sc_dev.dv_xname, slotctl)); 828 slotctl |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 829 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 830 slotctl &= ~TOPIC_SLOT_CTRL_SWDETECT; 831 DPRINTF(("0x%x\n", slotctl)); 832 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slotctl); 833 break; 834 835 case CB_TOPIC97: 836 slotctl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 837 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 838 sc->sc_dev.dv_xname, slotctl)); 839 slotctl |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 840 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 841 slotctl &= ~TOPIC_SLOT_CTRL_SWDETECT; 842 slotctl |= TOPIC97_SLOT_CTRL_PCIINT; 843 slotctl &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 844 DPRINTF(("0x%x\n", slotctl)); 845 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slotctl); 846 /* make sure to assert LV card support bits */ 847 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 848 0x800 + 0x3e, 849 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 850 0x800 + 0x3e) | 0x03); 851 break; 852 } 853 854 /* Close all memory and I/O windows. */ 855 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 856 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 857 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 858 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 859 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 860 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 861 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 862 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 863 864 /* reset 16-bit pcmcia bus */ 865 bus_space_write_1(bmt, bmh, 0x800 + PCIC_INTR, 866 bus_space_read_1(bmt, bmh, 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 867 868 /* turn off power */ 869 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 870 871 /* CSC Interrupt: Card detect and power cycle interrupts on */ 872 sockmask = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 873 sockmask |= CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; 874 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, sockmask); 875 /* reset interrupt */ 876 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 877 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 878 } 879 880 881 882 883 /* 884 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 885 * struct pcmciabus_attach_args *paa) 886 * 887 * This function attaches 16-bit PCcard bus. 888 */ 889 STATIC void 890 pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 891 struct pcmciabus_attach_args *paa) 892 { 893 struct pcic_handle *ph = &sc->sc_pcmcia_h; 894 #if rbus 895 rbus_tag_t rb; 896 #endif 897 898 /* initialize pcmcia part in pccbb_softc */ 899 ph->ph_parent = (struct device *)sc; 900 ph->sock = sc->sc_function; 901 ph->flags = 0; 902 ph->shutdown = 0; 903 ph->ih_irq = sc->sc_pa.pa_intrline; 904 ph->ph_bus_t = sc->sc_base_memt; 905 ph->ph_bus_h = sc->sc_base_memh; 906 ph->ph_read = pccbb_pcmcia_read; 907 ph->ph_write = pccbb_pcmcia_write; 908 sc->sc_pct = &pccbb_pcmcia_funcs; 909 910 /* 911 * We need to do a few things here: 912 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 913 * setting the IRQ numbers to 0. 914 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 915 * routing of CSC interrupts (e.g. card removal) to PCI while in 916 * PCMCIA mode. We just leave this set all the time. 917 * 3) Enable card insertion/removal interrupts in case the chip also 918 * needs that while in PCMCIA mode. 919 * 4) Clear any pending CSC interrupt. 920 */ 921 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE); 922 if (sc->sc_chipset == CB_TI113X) { 923 Pcic_write(ph, PCIC_CSC_INTR, 0); 924 } else { 925 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 926 Pcic_read(ph, PCIC_CSC); 927 } 928 929 /* initialize pcmcia bus attachment */ 930 paa->paa_busname = "pcmcia"; 931 paa->pct = sc->sc_pct; 932 paa->pch = ph; 933 paa->iobase = 0; /* I don't use them */ 934 paa->iosize = 0; 935 #if rbus 936 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 937 paa->iobase = rb->rb_start + rb->rb_offset; 938 paa->iosize = rb->rb_end - rb->rb_start; 939 #endif 940 941 return; 942 } 943 944 #if 0 945 STATIC void 946 pccbb_pcmcia_attach_card(struct pcic_handle *ph) 947 { 948 if (ph->flags & PCIC_FLAG_CARDP) { 949 panic("pccbb_pcmcia_attach_card: already attached"); 950 } 951 952 /* call the MI attach function */ 953 pcmcia_card_attach(ph->pcmcia); 954 955 ph->flags |= PCIC_FLAG_CARDP; 956 } 957 958 STATIC void 959 pccbb_pcmcia_detach_card(struct pcic_handle *ph, int flags) 960 { 961 if (!(ph->flags & PCIC_FLAG_CARDP)) { 962 panic("pccbb_pcmcia_detach_card: already detached"); 963 } 964 965 ph->flags &= ~PCIC_FLAG_CARDP; 966 967 /* call the MI detach function */ 968 pcmcia_card_detach(ph->pcmcia, flags); 969 } 970 #endif 971 972 /* 973 * int pccbbintr(arg) 974 * void *arg; 975 * This routine handles the interrupt from Yenta PCI-CardBus bridge 976 * itself. 977 */ 978 int 979 pccbbintr(void *arg) 980 { 981 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 982 u_int32_t sockevent, sockstate; 983 bus_space_tag_t memt = sc->sc_base_memt; 984 bus_space_handle_t memh = sc->sc_base_memh; 985 struct pcic_handle *ph = &sc->sc_pcmcia_h; 986 987 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 988 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 989 Pcic_read(ph, PCIC_CSC); 990 991 if (sockevent != 0) { 992 aprint_debug("%s: enter sockevent %" PRIx32 "\n", __func__, 993 sockevent); 994 } 995 996 /* Sometimes a change of CSTSCHG# accompanies the first 997 * interrupt from an Atheros WLAN. That generates a 998 * CB_SOCKET_EVENT_CSTS event on the bridge. The event 999 * isn't interesting to pccbb(4), so we used to ignore the 1000 * interrupt. Now, let the child devices try to handle 1001 * the interrupt, instead. The Atheros NIC produces 1002 * interrupts more reliably, now: used to be that it would 1003 * only interrupt if the driver avoided powering down the 1004 * NIC's cardslot, and then the NIC would only work after 1005 * it was reset a second time. 1006 */ 1007 if (sockevent == 0 || 1008 (sockevent & ~(CB_SOCKET_EVENT_POWER|CB_SOCKET_EVENT_CD)) != 0) { 1009 /* This intr is not for me: it may be for my child devices. */ 1010 if (sc->sc_pil_intr_enable) { 1011 return pccbbintr_function(sc); 1012 } else { 1013 return 0; 1014 } 1015 } 1016 1017 if (sockevent & CB_SOCKET_EVENT_CD) { 1018 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1019 if (0x00 != (sockstate & CB_SOCKET_STAT_CD)) { 1020 /* A card should be removed. */ 1021 if (sc->sc_flags & CBB_CARDEXIST) { 1022 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 1023 sockevent)); 1024 DPRINTF((" card removed, 0x%08x\n", sockstate)); 1025 sc->sc_flags &= ~CBB_CARDEXIST; 1026 if (sc->sc_csc->sc_status & 1027 CARDSLOT_STATUS_CARD_16) { 1028 #if 0 1029 struct pcic_handle *ph = 1030 &sc->sc_pcmcia_h; 1031 1032 pcmcia_card_deactivate(ph->pcmcia); 1033 pccbb_pcmcia_socket_disable(ph); 1034 pccbb_pcmcia_detach_card(ph, 1035 DETACH_FORCE); 1036 #endif 1037 cardslot_event_throw(sc->sc_csc, 1038 CARDSLOT_EVENT_REMOVAL_16); 1039 } else if (sc->sc_csc->sc_status & 1040 CARDSLOT_STATUS_CARD_CB) { 1041 /* Cardbus intr removed */ 1042 cardslot_event_throw(sc->sc_csc, 1043 CARDSLOT_EVENT_REMOVAL_CB); 1044 } 1045 } else if (sc->sc_flags & CBB_INSERTING) { 1046 sc->sc_flags &= ~CBB_INSERTING; 1047 callout_stop(&sc->sc_insert_ch); 1048 } 1049 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 1050 /* 1051 * The pccbbintr may called from powerdown hook when 1052 * the system resumed, to detect the card 1053 * insertion/removal during suspension. 1054 */ 1055 (sc->sc_flags & CBB_CARDEXIST) == 0) { 1056 if (sc->sc_flags & CBB_INSERTING) { 1057 callout_stop(&sc->sc_insert_ch); 1058 } 1059 callout_schedule(&sc->sc_insert_ch, hz / 5); 1060 sc->sc_flags |= CBB_INSERTING; 1061 } 1062 } 1063 1064 if (sockevent & CB_SOCKET_EVENT_POWER) { 1065 DPRINTF(("Powercycling because of socket event\n")); 1066 /* XXX: Does not happen when attaching a 16-bit card */ 1067 sc->sc_pwrcycle++; 1068 wakeup(&sc->sc_pwrcycle); 1069 } 1070 1071 return (1); 1072 } 1073 1074 /* 1075 * static int pccbbintr_function(struct pccbb_softc *sc) 1076 * 1077 * This function calls each interrupt handler registered at the 1078 * bridge. The interrupt handlers are called in registered order. 1079 */ 1080 static int 1081 pccbbintr_function(struct pccbb_softc *sc) 1082 { 1083 int retval = 0, val; 1084 struct pccbb_intrhand_list *pil; 1085 int s; 1086 1087 for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1088 pil = LIST_NEXT(pil, pil_next)) { 1089 s = splraiseipl(pil->pil_icookie); 1090 val = (*pil->pil_func)(pil->pil_arg); 1091 splx(s); 1092 1093 retval = retval == 1 ? 1 : 1094 retval == 0 ? val : val != 0 ? val : retval; 1095 } 1096 1097 return retval; 1098 } 1099 1100 static void 1101 pci113x_insert(void *arg) 1102 { 1103 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1104 u_int32_t sockevent, sockstate; 1105 1106 if (!(sc->sc_flags & CBB_INSERTING)) { 1107 /* We add a card only under inserting state. */ 1108 return; 1109 } 1110 sc->sc_flags &= ~CBB_INSERTING; 1111 1112 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1113 CB_SOCKET_EVENT); 1114 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1115 CB_SOCKET_STAT); 1116 1117 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1118 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1119 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1120 sc->sc_flags |= CBB_CARDEXIST; 1121 /* call pccard interrupt handler here */ 1122 if (sockstate & CB_SOCKET_STAT_16BIT) { 1123 /* 16-bit card found */ 1124 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1125 cardslot_event_throw(sc->sc_csc, 1126 CARDSLOT_EVENT_INSERTION_16); 1127 } else if (sockstate & CB_SOCKET_STAT_CB) { 1128 /* cardbus card found */ 1129 /* cardbus_attach_card(sc->sc_csc); */ 1130 cardslot_event_throw(sc->sc_csc, 1131 CARDSLOT_EVENT_INSERTION_CB); 1132 } else { 1133 /* who are you? */ 1134 } 1135 } else { 1136 callout_schedule(&sc->sc_insert_ch, hz / 10); 1137 } 1138 } 1139 1140 #define PCCBB_PCMCIA_OFFSET 0x800 1141 static u_int8_t 1142 pccbb_pcmcia_read(struct pcic_handle *ph, int reg) 1143 { 1144 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1145 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1146 1147 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1148 PCCBB_PCMCIA_OFFSET + reg); 1149 } 1150 1151 static void 1152 pccbb_pcmcia_write(struct pcic_handle *ph, int reg, u_int8_t val) 1153 { 1154 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1155 val); 1156 1157 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1158 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1159 } 1160 1161 /* 1162 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1163 */ 1164 STATIC int 1165 pccbb_ctrl(cardbus_chipset_tag_t ct, int command) 1166 { 1167 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1168 1169 switch (command) { 1170 case CARDBUS_CD: 1171 if (2 == pccbb_detect_card(sc)) { 1172 int retval = 0; 1173 int status = cb_detect_voltage(sc); 1174 if (PCCARD_VCC_5V & status) { 1175 retval |= CARDBUS_5V_CARD; 1176 } 1177 if (PCCARD_VCC_3V & status) { 1178 retval |= CARDBUS_3V_CARD; 1179 } 1180 if (PCCARD_VCC_XV & status) { 1181 retval |= CARDBUS_XV_CARD; 1182 } 1183 if (PCCARD_VCC_YV & status) { 1184 retval |= CARDBUS_YV_CARD; 1185 } 1186 return retval; 1187 } else { 1188 return 0; 1189 } 1190 case CARDBUS_RESET: 1191 return cb_reset(sc); 1192 case CARDBUS_IO_ENABLE: /* fallthrough */ 1193 case CARDBUS_IO_DISABLE: /* fallthrough */ 1194 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1195 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1196 case CARDBUS_BM_ENABLE: /* fallthrough */ 1197 case CARDBUS_BM_DISABLE: /* fallthrough */ 1198 /* XXX: I think we don't need to call this function below. */ 1199 return pccbb_cardenable(sc, command); 1200 } 1201 1202 return 0; 1203 } 1204 1205 /* 1206 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1207 * This function returns true when it succeeds and returns false when 1208 * it fails. 1209 */ 1210 STATIC int 1211 pccbb_power(cardbus_chipset_tag_t ct, int command) 1212 { 1213 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1214 u_int32_t status, osock_ctrl, sock_ctrl, reg_ctrl; 1215 bus_space_tag_t memt = sc->sc_base_memt; 1216 bus_space_handle_t memh = sc->sc_base_memh; 1217 int on = 0, pwrcycle, s, times; 1218 struct timeval before, after, diff; 1219 1220 DPRINTF(("pccbb_power: %s and %s [0x%x]\n", 1221 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1222 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1223 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1224 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1225 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1226 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1227 "UNKNOWN", 1228 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1229 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1230 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1231 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1232 "UNKNOWN", command)); 1233 1234 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1235 osock_ctrl = sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1236 1237 switch (command & CARDBUS_VCCMASK) { 1238 case CARDBUS_VCC_UC: 1239 break; 1240 case CARDBUS_VCC_5V: 1241 on++; 1242 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1243 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1244 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1245 } else { 1246 printf("%s: BAD voltage request: no 5 V card\n", 1247 sc->sc_dev.dv_xname); 1248 return 0; 1249 } 1250 break; 1251 case CARDBUS_VCC_3V: 1252 on++; 1253 if (CB_SOCKET_STAT_3VCARD & status) { 1254 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1255 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1256 } else { 1257 printf("%s: BAD voltage request: no 3.3 V card\n", 1258 sc->sc_dev.dv_xname); 1259 return 0; 1260 } 1261 break; 1262 case CARDBUS_VCC_0V: 1263 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1264 break; 1265 default: 1266 return 0; /* power NEVER changed */ 1267 } 1268 1269 switch (command & CARDBUS_VPPMASK) { 1270 case CARDBUS_VPP_UC: 1271 break; 1272 case CARDBUS_VPP_0V: 1273 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1274 break; 1275 case CARDBUS_VPP_VCC: 1276 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1277 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1278 break; 1279 case CARDBUS_VPP_12V: 1280 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1281 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1282 break; 1283 } 1284 1285 pwrcycle = sc->sc_pwrcycle; 1286 aprint_debug("%s: osock_ctrl %#" PRIx32 " sock_ctrl %#" PRIx32 "\n", 1287 device_xname(&sc->sc_dev), osock_ctrl, sock_ctrl); 1288 1289 microtime(&before); 1290 s = splbio(); 1291 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1292 1293 /* 1294 * Wait as long as 200ms for a power-cycle interrupt. If 1295 * interrupts are enabled, but the socket has already 1296 * changed to the desired status, keep waiting for the 1297 * interrupt. "Consuming" the interrupt in this way keeps 1298 * the interrupt from prematurely waking some subsequent 1299 * pccbb_power call. 1300 * 1301 * XXX Not every bridge interrupts on the ->OFF transition. 1302 * XXX That's ok, we will time-out after 200ms. 1303 * 1304 * XXX The power cycle event will never happen when attaching 1305 * XXX a 16-bit card. That's ok, we will time-out after 1306 * XXX 200ms. 1307 */ 1308 for (times = 5; --times >= 0; ) { 1309 if (cold) 1310 DELAY(40 * 1000); 1311 else { 1312 (void)tsleep(&sc->sc_pwrcycle, PWAIT, "pccpwr", 1313 hz / 25); 1314 if (pwrcycle == sc->sc_pwrcycle) 1315 continue; 1316 } 1317 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1318 if ((status & CB_SOCKET_STAT_PWRCYCLE) != 0 && on) 1319 break; 1320 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0 && !on) 1321 break; 1322 } 1323 splx(s); 1324 microtime(&after); 1325 timersub(&after, &before, &diff); 1326 aprint_debug("%s: wait took%s %ld.%06lds\n", sc->sc_dev.dv_xname, 1327 (on && times < 0) ? " too long" : "", diff.tv_sec, diff.tv_usec); 1328 1329 /* 1330 * Ok, wait a bit longer for things to settle. 1331 */ 1332 if (on && sc->sc_chipset == CB_TOPIC95B) 1333 delay_ms(100, sc); 1334 1335 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1336 1337 if (on && sc->sc_chipset != CB_TOPIC95B) { 1338 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0) 1339 printf("%s: power on failed?\n", sc->sc_dev.dv_xname); 1340 } 1341 1342 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1343 printf("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1344 sc->sc_dev.dv_xname, sock_ctrl, status); 1345 printf("%s: disabling socket\n", sc->sc_dev.dv_xname); 1346 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1347 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1348 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1349 status &= ~CB_SOCKET_STAT_BADVCC; 1350 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, status); 1351 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1352 CB_SOCKET_STAT)); 1353 return 0; 1354 } 1355 1356 if (sc->sc_chipset == CB_TOPIC97) { 1357 reg_ctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL); 1358 reg_ctrl &= ~TOPIC97_REG_CTRL_TESTMODE; 1359 if ((command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V) 1360 reg_ctrl &= ~TOPIC97_REG_CTRL_CLKRUN_ENA; 1361 else 1362 reg_ctrl |= TOPIC97_REG_CTRL_CLKRUN_ENA; 1363 pci_conf_write(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL, reg_ctrl); 1364 } 1365 1366 return 1; /* power changed correctly */ 1367 } 1368 1369 #if defined CB_PCMCIA_POLL 1370 struct cb_poll_str { 1371 void *arg; 1372 int (*func)(void *); 1373 int level; 1374 pccard_chipset_tag_t ct; 1375 int count; 1376 struct callout poll_ch; 1377 }; 1378 1379 static struct cb_poll_str cb_poll[10]; 1380 static int cb_poll_n = 0; 1381 1382 static void cb_pcmcia_poll(void *arg); 1383 1384 static void 1385 cb_pcmcia_poll(void *arg) 1386 { 1387 struct cb_poll_str *poll = arg; 1388 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1389 struct pccbb_softc *sc = psc->cpc_parent; 1390 int s; 1391 u_int32_t spsr; /* socket present-state reg */ 1392 1393 callout_reset(&poll->poll_ch, hz / 10, cb_pcmcia_poll, poll); 1394 switch (poll->level) { 1395 case IPL_NET: 1396 s = splnet(); 1397 break; 1398 case IPL_BIO: 1399 s = splbio(); 1400 break; 1401 case IPL_TTY: /* fallthrough */ 1402 default: 1403 s = spltty(); 1404 break; 1405 } 1406 1407 spsr = 1408 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1409 CB_SOCKET_STAT); 1410 1411 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1412 if (!(spsr & 0x40)) { /* CINT low */ 1413 #else 1414 if (1) { 1415 #endif 1416 if ((*poll->func) (poll->arg) == 1) { 1417 ++poll->count; 1418 printf("intr: reported from poller, 0x%x\n", spsr); 1419 #if defined LEVEL2 1420 } else { 1421 printf("intr: miss! 0x%x\n", spsr); 1422 #endif 1423 } 1424 } 1425 splx(s); 1426 } 1427 #endif /* defined CB_PCMCIA_POLL */ 1428 1429 /* 1430 * static int pccbb_detect_card(struct pccbb_softc *sc) 1431 * return value: 0 if no card exists. 1432 * 1 if 16-bit card exists. 1433 * 2 if cardbus card exists. 1434 */ 1435 static int 1436 pccbb_detect_card(struct pccbb_softc *sc) 1437 { 1438 bus_space_handle_t base_memh = sc->sc_base_memh; 1439 bus_space_tag_t base_memt = sc->sc_base_memt; 1440 u_int32_t sockstat = 1441 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1442 int retval = 0; 1443 1444 /* CD1 and CD2 asserted */ 1445 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1446 /* card must be present */ 1447 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1448 /* NOTACARD DEASSERTED */ 1449 if (CB_SOCKET_STAT_CB & sockstat) { 1450 /* CardBus mode */ 1451 retval = 2; 1452 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1453 /* 16-bit mode */ 1454 retval = 1; 1455 } 1456 } 1457 } 1458 return retval; 1459 } 1460 1461 /* 1462 * STATIC int cb_reset(struct pccbb_softc *sc) 1463 * This function resets CardBus card. 1464 */ 1465 STATIC int 1466 cb_reset(struct pccbb_softc *sc) 1467 { 1468 /* 1469 * Reset Assert at least 20 ms 1470 * Some machines request longer duration. 1471 */ 1472 int reset_duration = 1473 (sc->sc_chipset == CB_RX5C47X ? 400 : 50); 1474 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1475 1476 /* Reset bit Assert (bit 6 at 0x3E) */ 1477 bcr |= CB_BCR_RESET_ENABLE; 1478 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr); 1479 delay_ms(reset_duration, sc); 1480 1481 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1482 /* Reset bit Deassert (bit 6 at 0x3E) */ 1483 bcr &= ~CB_BCR_RESET_ENABLE; 1484 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr); 1485 delay_ms(reset_duration, sc); 1486 } 1487 /* No card found on the slot. Keep Reset. */ 1488 return 1; 1489 } 1490 1491 /* 1492 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1493 * This function detect card Voltage. 1494 */ 1495 STATIC int 1496 cb_detect_voltage(struct pccbb_softc *sc) 1497 { 1498 u_int32_t psr; /* socket present-state reg */ 1499 bus_space_tag_t iot = sc->sc_base_memt; 1500 bus_space_handle_t ioh = sc->sc_base_memh; 1501 int vol = PCCARD_VCC_UKN; /* set 0 */ 1502 1503 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1504 1505 if (0x400u & psr) { 1506 vol |= PCCARD_VCC_5V; 1507 } 1508 if (0x800u & psr) { 1509 vol |= PCCARD_VCC_3V; 1510 } 1511 1512 return vol; 1513 } 1514 1515 STATIC int 1516 cbbprint(void *aux, const char *pcic) 1517 { 1518 #if 0 1519 struct cbslot_attach_args *cba = aux; 1520 1521 if (cba->cba_slot >= 0) { 1522 aprint_normal(" slot %d", cba->cba_slot); 1523 } 1524 #endif 1525 return UNCONF; 1526 } 1527 1528 /* 1529 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1530 * This function enables and disables the card 1531 */ 1532 STATIC int 1533 pccbb_cardenable(struct pccbb_softc *sc, int function) 1534 { 1535 u_int32_t command = 1536 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1537 1538 DPRINTF(("pccbb_cardenable:")); 1539 switch (function) { 1540 case CARDBUS_IO_ENABLE: 1541 command |= PCI_COMMAND_IO_ENABLE; 1542 break; 1543 case CARDBUS_IO_DISABLE: 1544 command &= ~PCI_COMMAND_IO_ENABLE; 1545 break; 1546 case CARDBUS_MEM_ENABLE: 1547 command |= PCI_COMMAND_MEM_ENABLE; 1548 break; 1549 case CARDBUS_MEM_DISABLE: 1550 command &= ~PCI_COMMAND_MEM_ENABLE; 1551 break; 1552 case CARDBUS_BM_ENABLE: 1553 command |= PCI_COMMAND_MASTER_ENABLE; 1554 break; 1555 case CARDBUS_BM_DISABLE: 1556 command &= ~PCI_COMMAND_MASTER_ENABLE; 1557 break; 1558 default: 1559 return 0; 1560 } 1561 1562 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1563 DPRINTF((" command reg 0x%x\n", command)); 1564 return 1; 1565 } 1566 1567 #if !rbus 1568 static int 1569 pccbb_io_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 1570 { 1571 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1572 int basereg; 1573 int limitreg; 1574 1575 if ((win < 0) || (win > 2)) { 1576 #if defined DIAGNOSTIC 1577 printf("cardbus_io_open: window out of range %d\n", win); 1578 #endif 1579 return 0; 1580 } 1581 1582 basereg = win * 8 + 0x2c; 1583 limitreg = win * 8 + 0x30; 1584 1585 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1586 start, basereg, end, limitreg)); 1587 1588 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1589 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1590 return 1; 1591 } 1592 1593 /* 1594 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1595 */ 1596 static int 1597 pccbb_io_close(cardbus_chipset_tag_t ct, int win) 1598 { 1599 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1600 int basereg; 1601 int limitreg; 1602 1603 if ((win < 0) || (win > 2)) { 1604 #if defined DIAGNOSTIC 1605 printf("cardbus_io_close: window out of range %d\n", win); 1606 #endif 1607 return 0; 1608 } 1609 1610 basereg = win * 8 + 0x2c; 1611 limitreg = win * 8 + 0x30; 1612 1613 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1614 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1615 return 1; 1616 } 1617 1618 static int 1619 pccbb_mem_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 1620 { 1621 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1622 int basereg; 1623 int limitreg; 1624 1625 if ((win < 0) || (win > 2)) { 1626 #if defined DIAGNOSTIC 1627 printf("cardbus_mem_open: window out of range %d\n", win); 1628 #endif 1629 return 0; 1630 } 1631 1632 basereg = win * 8 + 0x1c; 1633 limitreg = win * 8 + 0x20; 1634 1635 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1636 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1637 return 1; 1638 } 1639 1640 static int 1641 pccbb_mem_close(cardbus_chipset_tag_t ct, int win) 1642 { 1643 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1644 int basereg; 1645 int limitreg; 1646 1647 if ((win < 0) || (win > 2)) { 1648 #if defined DIAGNOSTIC 1649 printf("cardbus_mem_close: window out of range %d\n", win); 1650 #endif 1651 return 0; 1652 } 1653 1654 basereg = win * 8 + 0x1c; 1655 limitreg = win * 8 + 0x20; 1656 1657 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1658 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1659 return 1; 1660 } 1661 #endif 1662 1663 /* 1664 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1665 * int irq, 1666 * int level, 1667 * int (* func)(void *), 1668 * void *arg) 1669 * 1670 * This function registers an interrupt handler at the bridge, in 1671 * order not to call the interrupt handlers of child devices when 1672 * a card-deletion interrupt occurs. 1673 * 1674 * The arguments irq and level are not used. 1675 */ 1676 static void * 1677 pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, int irq, int level, 1678 int (*func)(void *), void *arg) 1679 { 1680 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1681 1682 return pccbb_intr_establish(sc, irq, level, func, arg); 1683 } 1684 1685 1686 /* 1687 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1688 * void *ih) 1689 * 1690 * This function removes an interrupt handler pointed by ih. 1691 */ 1692 static void 1693 pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih) 1694 { 1695 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1696 1697 pccbb_intr_disestablish(sc, ih); 1698 } 1699 1700 1701 void 1702 pccbb_intr_route(struct pccbb_softc *sc) 1703 { 1704 pcireg_t bcr, cbctrl; 1705 1706 /* initialize bridge intr routing */ 1707 bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1708 bcr &= ~CB_BCR_INTR_IREQ_ENABLE; 1709 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr); 1710 1711 switch (sc->sc_chipset) { 1712 case CB_TI113X: 1713 cbctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1714 /* functional intr enabled */ 1715 cbctrl |= PCI113X_CBCTRL_PCI_INTR; 1716 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, cbctrl); 1717 break; 1718 default: 1719 break; 1720 } 1721 } 1722 1723 /* 1724 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1725 * int irq, 1726 * int level, 1727 * int (* func)(void *), 1728 * void *arg) 1729 * 1730 * This function registers an interrupt handler at the bridge, in 1731 * order not to call the interrupt handlers of child devices when 1732 * a card-deletion interrupt occurs. 1733 * 1734 * The arguments irq is not used because pccbb selects intr vector. 1735 */ 1736 static void * 1737 pccbb_intr_establish(struct pccbb_softc *sc, int irq, int level, 1738 int (*func)(void *), void *arg) 1739 { 1740 struct pccbb_intrhand_list *pil, *newpil; 1741 1742 DPRINTF(("pccbb_intr_establish start. %p\n", LIST_FIRST(&sc->sc_pil))); 1743 1744 if (LIST_EMPTY(&sc->sc_pil)) { 1745 pccbb_intr_route(sc); 1746 } 1747 1748 /* 1749 * Allocate a room for interrupt handler structure. 1750 */ 1751 if (NULL == (newpil = 1752 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1753 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1754 return NULL; 1755 } 1756 1757 newpil->pil_func = func; 1758 newpil->pil_arg = arg; 1759 newpil->pil_icookie = makeiplcookie(level); 1760 1761 if (LIST_EMPTY(&sc->sc_pil)) { 1762 LIST_INSERT_HEAD(&sc->sc_pil, newpil, pil_next); 1763 } else { 1764 for (pil = LIST_FIRST(&sc->sc_pil); 1765 LIST_NEXT(pil, pil_next) != NULL; 1766 pil = LIST_NEXT(pil, pil_next)); 1767 LIST_INSERT_AFTER(pil, newpil, pil_next); 1768 } 1769 1770 DPRINTF(("pccbb_intr_establish add pil. %p\n", 1771 LIST_FIRST(&sc->sc_pil))); 1772 1773 return newpil; 1774 } 1775 1776 /* 1777 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1778 * void *ih) 1779 * 1780 * This function removes an interrupt handler pointed by ih. ih 1781 * should be the value returned by cardbus_intr_establish() or 1782 * NULL. 1783 * 1784 * When ih is NULL, this function will do nothing. 1785 */ 1786 static void 1787 pccbb_intr_disestablish(struct pccbb_softc *sc, void *ih) 1788 { 1789 struct pccbb_intrhand_list *pil; 1790 pcireg_t reg; 1791 1792 DPRINTF(("pccbb_intr_disestablish start. %p\n", 1793 LIST_FIRST(&sc->sc_pil))); 1794 1795 if (ih == NULL) { 1796 /* intr handler is not set */ 1797 DPRINTF(("pccbb_intr_disestablish: no ih\n")); 1798 return; 1799 } 1800 1801 #ifdef DIAGNOSTIC 1802 for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1803 pil = LIST_NEXT(pil, pil_next)) { 1804 DPRINTF(("pccbb_intr_disestablish: pil %p\n", pil)); 1805 if (pil == ih) { 1806 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1807 break; 1808 } 1809 } 1810 if (pil == NULL) { 1811 panic("pccbb_intr_disestablish: %s cannot find pil %p", 1812 sc->sc_dev.dv_xname, ih); 1813 } 1814 #endif 1815 1816 pil = (struct pccbb_intrhand_list *)ih; 1817 LIST_REMOVE(pil, pil_next); 1818 free(pil, M_DEVBUF); 1819 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1820 1821 if (LIST_EMPTY(&sc->sc_pil)) { 1822 /* No interrupt handlers */ 1823 1824 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1825 1826 /* stop routing PCI intr */ 1827 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1828 reg |= CB_BCR_INTR_IREQ_ENABLE; 1829 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, reg); 1830 1831 switch (sc->sc_chipset) { 1832 case CB_TI113X: 1833 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1834 /* functional intr disabled */ 1835 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1836 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1837 break; 1838 default: 1839 break; 1840 } 1841 } 1842 } 1843 1844 #if defined SHOW_REGS 1845 static void 1846 cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, bus_space_tag_t memt, 1847 bus_space_handle_t memh) 1848 { 1849 int i; 1850 printf("PCI config regs:"); 1851 for (i = 0; i < 0x50; i += 4) { 1852 if (i % 16 == 0) 1853 printf("\n 0x%02x:", i); 1854 printf(" %08x", pci_conf_read(pc, tag, i)); 1855 } 1856 for (i = 0x80; i < 0xb0; i += 4) { 1857 if (i % 16 == 0) 1858 printf("\n 0x%02x:", i); 1859 printf(" %08x", pci_conf_read(pc, tag, i)); 1860 } 1861 1862 if (memh == 0) { 1863 printf("\n"); 1864 return; 1865 } 1866 1867 printf("\nsocket regs:"); 1868 for (i = 0; i <= 0x10; i += 0x04) 1869 printf(" %08x", bus_space_read_4(memt, memh, i)); 1870 printf("\nExCA regs:"); 1871 for (i = 0; i < 0x08; ++i) 1872 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1873 printf("\n"); 1874 return; 1875 } 1876 #endif 1877 1878 /* 1879 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1880 * int busno, int function) 1881 * This is the function to make a tag to access config space of 1882 * a CardBus Card. It works same as pci_conf_read. 1883 */ 1884 static cardbustag_t 1885 pccbb_make_tag(cardbus_chipset_tag_t cc, int busno, int function) 1886 { 1887 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1888 1889 return pci_make_tag(sc->sc_pc, busno, 0, function); 1890 } 1891 1892 static void 1893 pccbb_free_tag(cardbus_chipset_tag_t cc, cardbustag_t tag) 1894 { 1895 } 1896 1897 /* 1898 * pccbb_conf_read 1899 * 1900 * This is the function to read the config space of a CardBus card. 1901 * It works the same as pci_conf_read(9). 1902 */ 1903 static cardbusreg_t 1904 pccbb_conf_read(cardbus_chipset_tag_t cc, cardbustag_t tag, int offset) 1905 { 1906 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1907 1908 return pci_conf_read(sc->sc_pc, tag, offset); 1909 } 1910 1911 /* 1912 * pccbb_conf_write 1913 * 1914 * This is the function to write the config space of a CardBus 1915 * card. It works the same as pci_conf_write(9). 1916 */ 1917 static void 1918 pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, int reg, 1919 cardbusreg_t val) 1920 { 1921 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1922 1923 pci_conf_write(sc->sc_pc, tag, reg, val); 1924 } 1925 1926 #if 0 1927 STATIC int 1928 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1929 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 1930 int speed, int flags, 1931 bus_space_handle_t * iohp) 1932 #endif 1933 /* 1934 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1935 * bus_addr_t start, bus_size_t size, 1936 * bus_size_t align, 1937 * struct pcmcia_io_handle *pcihp 1938 * 1939 * This function only allocates I/O region for pccard. This function 1940 * never maps the allocated region to pccard I/O area. 1941 * 1942 * XXX: The interface of this function is not very good, I believe. 1943 */ 1944 STATIC int 1945 pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, 1946 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 1947 { 1948 struct pcic_handle *ph = (struct pcic_handle *)pch; 1949 bus_addr_t ioaddr; 1950 int flags = 0; 1951 bus_space_tag_t iot; 1952 bus_space_handle_t ioh; 1953 bus_addr_t mask; 1954 #if rbus 1955 rbus_tag_t rb; 1956 #endif 1957 if (align == 0) { 1958 align = size; /* XXX: funny??? */ 1959 } 1960 1961 if (start != 0) { 1962 /* XXX: assume all card decode lower 10 bits by its hardware */ 1963 mask = 0x3ff; 1964 /* enforce to use only masked address */ 1965 start &= mask; 1966 } else { 1967 /* 1968 * calculate mask: 1969 * 1. get the most significant bit of size (call it msb). 1970 * 2. compare msb with the value of size. 1971 * 3. if size is larger, shift msb left once. 1972 * 4. obtain mask value to decrement msb. 1973 */ 1974 bus_size_t size_tmp = size; 1975 int shifts = 0; 1976 1977 mask = 1; 1978 while (size_tmp) { 1979 ++shifts; 1980 size_tmp >>= 1; 1981 } 1982 mask = (1 << shifts); 1983 if (mask < size) { 1984 mask <<= 1; 1985 } 1986 --mask; 1987 } 1988 1989 /* 1990 * Allocate some arbitrary I/O space. 1991 */ 1992 1993 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 1994 1995 #if rbus 1996 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 1997 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 1998 return 1; 1999 } 2000 DPRINTF(("pccbb_pcmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2001 (u_long) ioaddr, (u_long) size)); 2002 #else 2003 if (start) { 2004 ioaddr = start; 2005 if (bus_space_map(iot, start, size, 0, &ioh)) { 2006 return 1; 2007 } 2008 DPRINTF(("pccbb_pcmcia_io_alloc map port 0x%lx+0x%lx\n", 2009 (u_long) ioaddr, (u_long) size)); 2010 } else { 2011 flags |= PCMCIA_IO_ALLOCATED; 2012 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 2013 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 2014 size, align, 0, 0, &ioaddr, &ioh)) { 2015 /* No room be able to be get. */ 2016 return 1; 2017 } 2018 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2019 (u_long) ioaddr, (u_long) size)); 2020 } 2021 #endif 2022 2023 pcihp->iot = iot; 2024 pcihp->ioh = ioh; 2025 pcihp->addr = ioaddr; 2026 pcihp->size = size; 2027 pcihp->flags = flags; 2028 2029 return 0; 2030 } 2031 2032 /* 2033 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2034 * struct pcmcia_io_handle *pcihp) 2035 * 2036 * This function only frees I/O region for pccard. 2037 * 2038 * XXX: The interface of this function is not very good, I believe. 2039 */ 2040 void 2041 pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2042 struct pcmcia_io_handle *pcihp) 2043 { 2044 #if !rbus 2045 bus_space_tag_t iot = pcihp->iot; 2046 #endif 2047 bus_space_handle_t ioh = pcihp->ioh; 2048 bus_size_t size = pcihp->size; 2049 2050 #if rbus 2051 struct pccbb_softc *sc = 2052 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 2053 rbus_tag_t rb = sc->sc_rbus_iot; 2054 2055 rbus_space_free(rb, ioh, size, NULL); 2056 #else 2057 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 2058 bus_space_free(iot, ioh, size); 2059 else 2060 bus_space_unmap(iot, ioh, size); 2061 #endif 2062 } 2063 2064 /* 2065 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 2066 * bus_addr_t offset, bus_size_t size, 2067 * struct pcmcia_io_handle *pcihp, 2068 * int *windowp) 2069 * 2070 * This function maps the allocated I/O region to pccard. This function 2071 * never allocates any I/O region for pccard I/O area. I don't 2072 * understand why the original authors of pcmciabus separated alloc and 2073 * map. I believe the two must be unite. 2074 * 2075 * XXX: no wait timing control? 2076 */ 2077 int 2078 pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, bus_addr_t offset, 2079 bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp) 2080 { 2081 struct pcic_handle *ph = (struct pcic_handle *)pch; 2082 bus_addr_t ioaddr = pcihp->addr + offset; 2083 int i, win; 2084 #if defined CBB_DEBUG 2085 static const char *width_names[] = { "dynamic", "io8", "io16" }; 2086 #endif 2087 2088 /* Sanity check I/O handle. */ 2089 2090 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 2091 panic("pccbb_pcmcia_io_map iot is bogus"); 2092 } 2093 2094 /* XXX Sanity check offset/size. */ 2095 2096 win = -1; 2097 for (i = 0; i < PCIC_IO_WINS; i++) { 2098 if ((ph->ioalloc & (1 << i)) == 0) { 2099 win = i; 2100 ph->ioalloc |= (1 << i); 2101 break; 2102 } 2103 } 2104 2105 if (win == -1) { 2106 return 1; 2107 } 2108 2109 *windowp = win; 2110 2111 /* XXX this is pretty gross */ 2112 2113 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2114 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2115 2116 /* XXX wtf is this doing here? */ 2117 2118 #if 0 2119 printf(" port 0x%lx", (u_long) ioaddr); 2120 if (size > 1) { 2121 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2122 } 2123 #endif 2124 2125 ph->io[win].addr = ioaddr; 2126 ph->io[win].size = size; 2127 ph->io[win].width = width; 2128 2129 /* actual dirty register-value changing in the function below. */ 2130 pccbb_pcmcia_do_io_map(ph, win); 2131 2132 return 0; 2133 } 2134 2135 /* 2136 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2137 * 2138 * This function changes register-value to map I/O region for pccard. 2139 */ 2140 static void 2141 pccbb_pcmcia_do_io_map(struct pcic_handle *ph, int win) 2142 { 2143 static u_int8_t pcic_iowidth[3] = { 2144 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2145 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2146 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2147 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2148 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2149 }; 2150 2151 #define PCIC_SIA_START_LOW 0 2152 #define PCIC_SIA_START_HIGH 1 2153 #define PCIC_SIA_STOP_LOW 2 2154 #define PCIC_SIA_STOP_HIGH 3 2155 2156 int regbase_win = 0x8 + win * 0x04; 2157 u_int8_t ioctl, enable; 2158 2159 DPRINTF(("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx " 2160 "width %d\n", win, (unsigned long)ph->io[win].addr, 2161 (unsigned long)ph->io[win].size, ph->io[win].width * 8)); 2162 2163 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2164 ph->io[win].addr & 0xff); 2165 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2166 (ph->io[win].addr >> 8) & 0xff); 2167 2168 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2169 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2170 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2171 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2172 2173 ioctl = Pcic_read(ph, PCIC_IOCTL); 2174 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2175 switch (win) { 2176 case 0: 2177 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2178 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2179 PCIC_IOCTL_IO0_DATASIZE_MASK); 2180 ioctl |= pcic_iowidth[ph->io[win].width]; 2181 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2182 break; 2183 case 1: 2184 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2185 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2186 PCIC_IOCTL_IO1_DATASIZE_MASK); 2187 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2188 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2189 break; 2190 } 2191 Pcic_write(ph, PCIC_IOCTL, ioctl); 2192 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2193 #if defined(CBB_DEBUG) 2194 { 2195 u_int8_t start_low = 2196 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2197 u_int8_t start_high = 2198 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2199 u_int8_t stop_low = 2200 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2201 u_int8_t stop_high = 2202 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2203 printf("pccbb_pcmcia_do_io_map start %02x %02x, " 2204 "stop %02x %02x, ioctl %02x enable %02x\n", 2205 start_low, start_high, stop_low, stop_high, ioctl, enable); 2206 } 2207 #endif 2208 } 2209 2210 /* 2211 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2212 * 2213 * This function unmaps I/O region. No return value. 2214 */ 2215 STATIC void 2216 pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t pch, int win) 2217 { 2218 struct pcic_handle *ph = (struct pcic_handle *)pch; 2219 int reg; 2220 2221 if (win >= PCIC_IO_WINS || win < 0) { 2222 panic("pccbb_pcmcia_io_unmap: window out of range"); 2223 } 2224 2225 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2226 switch (win) { 2227 case 0: 2228 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2229 break; 2230 case 1: 2231 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2232 break; 2233 } 2234 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2235 2236 ph->ioalloc &= ~(1 << win); 2237 } 2238 2239 static int 2240 pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 2241 { 2242 u_int8_t stat; 2243 int i; 2244 2245 /* wait an initial 10ms for quick cards */ 2246 stat = Pcic_read(ph, PCIC_IF_STATUS); 2247 if (stat & PCIC_IF_STATUS_READY) 2248 return (0); 2249 pccbb_pcmcia_delay(ph, 10, "pccwr0"); 2250 for (i = 0; i < 50; i++) { 2251 stat = Pcic_read(ph, PCIC_IF_STATUS); 2252 if (stat & PCIC_IF_STATUS_READY) 2253 return (0); 2254 if ((stat & PCIC_IF_STATUS_CARDDETECT_MASK) != 2255 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2256 return (ENXIO); 2257 /* wait .1s (100ms) each iteration now */ 2258 pccbb_pcmcia_delay(ph, 100, "pccwr1"); 2259 } 2260 2261 printf("pccbb_pcmcia_wait_ready: ready never happened, status=%02x\n", stat); 2262 return (EWOULDBLOCK); 2263 } 2264 2265 /* 2266 * Perform long (msec order) delay. timo is in milliseconds. 2267 */ 2268 static void 2269 pccbb_pcmcia_delay(struct pcic_handle *ph, int timo, const char *wmesg) 2270 { 2271 #ifdef DIAGNOSTIC 2272 if (timo <= 0) 2273 panic("pccbb_pcmcia_delay: called with timeout %d", timo); 2274 if (!curlwp) 2275 panic("pccbb_pcmcia_delay: called in interrupt context"); 2276 #if 0 2277 if (!ph->event_thread) 2278 panic("pccbb_pcmcia_delay: no event thread"); 2279 #endif 2280 #endif 2281 DPRINTF(("pccbb_pcmcia_delay: \"%s\" %p, sleep %d ms\n", 2282 wmesg, ph->event_thread, timo)); 2283 tsleep(pccbb_pcmcia_delay, PWAIT, wmesg, roundup(timo * hz, 1000) / 1000); 2284 } 2285 2286 /* 2287 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2288 * 2289 * This function enables the card. All information is stored in 2290 * the first argument, pcmcia_chipset_handle_t. 2291 */ 2292 STATIC void 2293 pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2294 { 2295 struct pcic_handle *ph = (struct pcic_handle *)pch; 2296 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2297 pcireg_t spsr; 2298 int voltage; 2299 int win; 2300 u_int8_t power, intr; 2301 #ifdef DIAGNOSTIC 2302 int reg; 2303 #endif 2304 2305 /* this bit is mostly stolen from pcic_attach_card */ 2306 2307 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2308 2309 /* get card Vcc info */ 2310 spsr = 2311 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2312 CB_SOCKET_STAT); 2313 if (spsr & CB_SOCKET_STAT_5VCARD) { 2314 DPRINTF(("5V card\n")); 2315 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2316 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2317 DPRINTF(("3V card\n")); 2318 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2319 } else { 2320 DPRINTF(("?V card, 0x%x\n", spsr)); /* XXX */ 2321 return; 2322 } 2323 2324 /* disable interrupts; assert RESET */ 2325 intr = Pcic_read(ph, PCIC_INTR); 2326 intr &= PCIC_INTR_ENABLE; 2327 Pcic_write(ph, PCIC_INTR, intr); 2328 2329 /* zero out the address windows */ 2330 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2331 2332 /* power down the socket to reset it, clear the card reset pin */ 2333 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2334 2335 /* power off; assert output enable bit */ 2336 power = PCIC_PWRCTL_OE; 2337 Pcic_write(ph, PCIC_PWRCTL, power); 2338 2339 /* power up the socket */ 2340 if (pccbb_power(sc, voltage) == 0) 2341 return; 2342 2343 /* 2344 * Table 4-18 and figure 4-6 of the PC Card specifiction say: 2345 * Vcc Rising Time (Tpr) = 100ms (handled in pccbb_power() above) 2346 * RESET Width (Th (Hi-z RESET)) = 1ms 2347 * RESET Width (Tw (RESET)) = 10us 2348 * 2349 * some machines require some more time to be settled 2350 * for example old toshiba topic bridges! 2351 * (100ms is added here). 2352 */ 2353 pccbb_pcmcia_delay(ph, 200 + 1, "pccen1"); 2354 2355 /* negate RESET */ 2356 intr |= PCIC_INTR_RESET; 2357 Pcic_write(ph, PCIC_INTR, intr); 2358 2359 /* 2360 * RESET Setup Time (Tsu (RESET)) = 20ms 2361 */ 2362 pccbb_pcmcia_delay(ph, 20, "pccen2"); 2363 2364 #ifdef DIAGNOSTIC 2365 reg = Pcic_read(ph, PCIC_IF_STATUS); 2366 if ((reg & PCIC_IF_STATUS_POWERACTIVE) == 0) 2367 printf("pccbb_pcmcia_socket_enable: no power, status=%x\n", reg); 2368 #endif 2369 2370 /* wait for the chip to finish initializing */ 2371 if (pccbb_pcmcia_wait_ready(ph)) { 2372 #ifdef DIAGNOSTIC 2373 printf("pccbb_pcmcia_socket_enable: never became ready\n"); 2374 #endif 2375 /* XXX return a failure status?? */ 2376 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2377 Pcic_write(ph, PCIC_PWRCTL, 0); 2378 return; 2379 } 2380 2381 /* reinstall all the memory and io mappings */ 2382 for (win = 0; win < PCIC_MEM_WINS; ++win) 2383 if (ph->memalloc & (1 << win)) 2384 pccbb_pcmcia_do_mem_map(ph, win); 2385 for (win = 0; win < PCIC_IO_WINS; ++win) 2386 if (ph->ioalloc & (1 << win)) 2387 pccbb_pcmcia_do_io_map(ph, win); 2388 } 2389 2390 /* 2391 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2392 * 2393 * This function disables the card. All information is stored in 2394 * the first argument, pcmcia_chipset_handle_t. 2395 */ 2396 STATIC void 2397 pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t pch) 2398 { 2399 struct pcic_handle *ph = (struct pcic_handle *)pch; 2400 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2401 u_int8_t intr; 2402 2403 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2404 2405 /* disable interrupts; assert RESET */ 2406 intr = Pcic_read(ph, PCIC_INTR); 2407 intr &= PCIC_INTR_ENABLE; 2408 Pcic_write(ph, PCIC_INTR, intr); 2409 2410 /* zero out the address windows */ 2411 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2412 2413 /* power down the socket to reset it, clear the card reset pin */ 2414 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2415 2416 /* disable socket: negate output enable bit and power off */ 2417 Pcic_write(ph, PCIC_PWRCTL, 0); 2418 2419 /* 2420 * Vcc Falling Time (Tpf) = 300ms 2421 */ 2422 pccbb_pcmcia_delay(ph, 300, "pccwr1"); 2423 } 2424 2425 STATIC void 2426 pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t pch, int type) 2427 { 2428 struct pcic_handle *ph = (struct pcic_handle *)pch; 2429 u_int8_t intr; 2430 2431 /* set the card type */ 2432 2433 intr = Pcic_read(ph, PCIC_INTR); 2434 intr &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_CARDTYPE_MASK); 2435 if (type == PCMCIA_IFTYPE_IO) 2436 intr |= PCIC_INTR_CARDTYPE_IO; 2437 else 2438 intr |= PCIC_INTR_CARDTYPE_MEM; 2439 Pcic_write(ph, PCIC_INTR, intr); 2440 2441 DPRINTF(("%s: pccbb_pcmcia_socket_settype %02x type %s %02x\n", 2442 ph->ph_parent->dv_xname, ph->sock, 2443 ((type == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2444 } 2445 2446 /* 2447 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2448 * 2449 * This function detects whether a card is in the slot or not. 2450 * If a card is inserted, return 1. Otherwise, return 0. 2451 */ 2452 STATIC int 2453 pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch) 2454 { 2455 struct pcic_handle *ph = (struct pcic_handle *)pch; 2456 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2457 2458 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2459 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2460 } 2461 2462 #if 0 2463 STATIC int 2464 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2465 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2466 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2467 #endif 2468 /* 2469 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2470 * bus_size_t size, 2471 * struct pcmcia_mem_handle *pcmhp) 2472 * 2473 * This function only allocates memory region for pccard. This 2474 * function never maps the allocated region to pccard memory area. 2475 * 2476 * XXX: Why the argument of start address is not in? 2477 */ 2478 STATIC int 2479 pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 2480 struct pcmcia_mem_handle *pcmhp) 2481 { 2482 struct pcic_handle *ph = (struct pcic_handle *)pch; 2483 bus_space_handle_t memh; 2484 bus_addr_t addr; 2485 bus_size_t sizepg; 2486 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2487 #if rbus 2488 rbus_tag_t rb; 2489 #endif 2490 2491 /* Check that the card is still there. */ 2492 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2493 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2494 return 1; 2495 2496 /* out of sc->memh, allocate as many pages as necessary */ 2497 2498 /* convert size to PCIC pages */ 2499 /* 2500 * This is not enough; when the requested region is on the page 2501 * boundaries, this may calculate wrong result. 2502 */ 2503 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2504 #if 0 2505 if (sizepg > PCIC_MAX_MEM_PAGES) { 2506 return 1; 2507 } 2508 #endif 2509 2510 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2511 return 1; 2512 } 2513 2514 addr = 0; /* XXX gcc -Wuninitialized */ 2515 2516 #if rbus 2517 rb = sc->sc_rbus_memt; 2518 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2519 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2520 &addr, &memh)) { 2521 return 1; 2522 } 2523 #else 2524 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2525 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2526 0, /* boundary */ 2527 0, /* flags */ 2528 &addr, &memh)) { 2529 return 1; 2530 } 2531 #endif 2532 2533 DPRINTF(("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, " 2534 "realsize 0x%lx\n", (unsigned long)addr, (unsigned long)size, 2535 (unsigned long)sizepg * PCIC_MEM_PAGESIZE)); 2536 2537 pcmhp->memt = sc->sc_memt; 2538 pcmhp->memh = memh; 2539 pcmhp->addr = addr; 2540 pcmhp->size = size; 2541 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2542 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2543 pcmhp->mhandle = 0; 2544 /* No offset??? Funny. */ 2545 2546 return 0; 2547 } 2548 2549 /* 2550 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2551 * struct pcmcia_mem_handle *pcmhp) 2552 * 2553 * This function release the memory space allocated by the function 2554 * pccbb_pcmcia_mem_alloc(). 2555 */ 2556 STATIC void 2557 pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2558 struct pcmcia_mem_handle *pcmhp) 2559 { 2560 #if rbus 2561 struct pcic_handle *ph = (struct pcic_handle *)pch; 2562 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2563 2564 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2565 #else 2566 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2567 #endif 2568 } 2569 2570 /* 2571 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2572 * 2573 * This function release the memory space allocated by the function 2574 * pccbb_pcmcia_mem_alloc(). 2575 */ 2576 STATIC void 2577 pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2578 { 2579 int regbase_win; 2580 bus_addr_t phys_addr; 2581 bus_addr_t phys_end; 2582 2583 #define PCIC_SMM_START_LOW 0 2584 #define PCIC_SMM_START_HIGH 1 2585 #define PCIC_SMM_STOP_LOW 2 2586 #define PCIC_SMM_STOP_HIGH 3 2587 #define PCIC_CMA_LOW 4 2588 #define PCIC_CMA_HIGH 5 2589 2590 u_int8_t start_low, start_high = 0; 2591 u_int8_t stop_low, stop_high; 2592 u_int8_t off_low, off_high; 2593 u_int8_t mem_window; 2594 int reg; 2595 2596 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2597 int mem8 = 2598 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2599 || (kind == PCMCIA_MEM_ATTR); 2600 2601 regbase_win = 0x10 + win * 0x08; 2602 2603 phys_addr = ph->mem[win].addr; 2604 phys_end = phys_addr + ph->mem[win].size; 2605 2606 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2607 (unsigned long)phys_addr, (unsigned long)phys_end, 2608 (unsigned long)ph->mem[win].offset)); 2609 2610 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2611 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2612 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2613 2614 /* bit 19:12 */ 2615 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2616 /* bit 23:20 and bit 7 on */ 2617 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2618 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2619 /* bit 31:24, for 32-bit address */ 2620 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2621 2622 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2623 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2624 2625 if (((struct pccbb_softc *)ph-> 2626 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2627 Pcic_write(ph, 0x40 + win, mem_window); 2628 } 2629 2630 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2631 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2632 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2633 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2634 2635 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2636 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2637 2638 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2639 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2640 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2641 | ((kind == PCMCIA_MEM_ATTR) ? 2642 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2643 2644 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2645 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2646 2647 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2648 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2649 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2650 2651 #if defined(CBB_DEBUG) 2652 { 2653 int r1, r2, r3, r4, r5, r6, r7 = 0; 2654 2655 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2656 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2657 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2658 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2659 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2660 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2661 if (((struct pccbb_softc *)(ph-> 2662 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2663 r7 = Pcic_read(ph, 0x40 + win); 2664 } 2665 2666 printf("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2667 "%02x%02x", win, r1, r2, r3, r4, r5, r6); 2668 if (((struct pccbb_softc *)(ph-> 2669 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2670 printf(" %02x", r7); 2671 } 2672 printf("\n"); 2673 } 2674 #endif 2675 } 2676 2677 /* 2678 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2679 * bus_addr_t card_addr, bus_size_t size, 2680 * struct pcmcia_mem_handle *pcmhp, 2681 * bus_addr_t *offsetp, int *windowp) 2682 * 2683 * This function maps memory space allocated by the function 2684 * pccbb_pcmcia_mem_alloc(). 2685 */ 2686 STATIC int 2687 pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2688 bus_addr_t card_addr, bus_size_t size, struct pcmcia_mem_handle *pcmhp, 2689 bus_addr_t *offsetp, int *windowp) 2690 { 2691 struct pcic_handle *ph = (struct pcic_handle *)pch; 2692 bus_addr_t busaddr; 2693 long card_offset; 2694 int win; 2695 2696 /* Check that the card is still there. */ 2697 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2698 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2699 return 1; 2700 2701 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2702 if ((ph->memalloc & (1 << win)) == 0) { 2703 ph->memalloc |= (1 << win); 2704 break; 2705 } 2706 } 2707 2708 if (win == PCIC_MEM_WINS) { 2709 return 1; 2710 } 2711 2712 *windowp = win; 2713 2714 /* XXX this is pretty gross */ 2715 2716 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2717 panic("pccbb_pcmcia_mem_map memt is bogus"); 2718 } 2719 2720 busaddr = pcmhp->addr; 2721 2722 /* 2723 * compute the address offset to the pcmcia address space for the 2724 * pcic. this is intentionally signed. The masks and shifts below 2725 * will cause TRT to happen in the pcic registers. Deal with making 2726 * sure the address is aligned, and return the alignment offset. 2727 */ 2728 2729 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2730 card_addr -= *offsetp; 2731 2732 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2733 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2734 (u_long) card_addr)); 2735 2736 /* 2737 * include the offset in the size, and decrement size by one, since 2738 * the hw wants start/stop 2739 */ 2740 size += *offsetp - 1; 2741 2742 card_offset = (((long)card_addr) - ((long)busaddr)); 2743 2744 ph->mem[win].addr = busaddr; 2745 ph->mem[win].size = size; 2746 ph->mem[win].offset = card_offset; 2747 ph->mem[win].kind = kind; 2748 2749 pccbb_pcmcia_do_mem_map(ph, win); 2750 2751 return 0; 2752 } 2753 2754 /* 2755 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2756 * int window) 2757 * 2758 * This function unmaps memory space which mapped by the function 2759 * pccbb_pcmcia_mem_map(). 2760 */ 2761 STATIC void 2762 pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, int window) 2763 { 2764 struct pcic_handle *ph = (struct pcic_handle *)pch; 2765 int reg; 2766 2767 if (window >= PCIC_MEM_WINS) { 2768 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2769 } 2770 2771 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2772 reg &= ~(1 << window); 2773 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2774 2775 ph->memalloc &= ~(1 << window); 2776 } 2777 2778 #if defined PCCBB_PCMCIA_POLL 2779 struct pccbb_poll_str { 2780 void *arg; 2781 int (*func)(void *); 2782 int level; 2783 struct pcic_handle *ph; 2784 int count; 2785 int num; 2786 struct callout poll_ch; 2787 }; 2788 2789 static struct pccbb_poll_str pccbb_poll[10]; 2790 static int pccbb_poll_n = 0; 2791 2792 static void pccbb_pcmcia_poll(void *arg); 2793 2794 static void 2795 pccbb_pcmcia_poll(void *arg) 2796 { 2797 struct pccbb_poll_str *poll = arg; 2798 struct pcic_handle *ph = poll->ph; 2799 struct pccbb_softc *sc = ph->sc; 2800 int s; 2801 u_int32_t spsr; /* socket present-state reg */ 2802 2803 callout_reset(&poll->poll_ch, hz * 2, pccbb_pcmcia_poll, arg); 2804 switch (poll->level) { 2805 case IPL_NET: 2806 s = splnet(); 2807 break; 2808 case IPL_BIO: 2809 s = splbio(); 2810 break; 2811 case IPL_TTY: /* fallthrough */ 2812 default: 2813 s = spltty(); 2814 break; 2815 } 2816 2817 spsr = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2818 CB_SOCKET_STAT); 2819 2820 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2821 if (!(spsr & 0x40)) /* CINT low */ 2822 #else 2823 if (1) 2824 #endif 2825 { 2826 if ((*poll->func) (poll->arg) > 0) { 2827 ++poll->count; 2828 /* printf("intr: reported from poller, 0x%x\n", spsr); */ 2829 #if defined LEVEL2 2830 } else { 2831 printf("intr: miss! 0x%x\n", spsr); 2832 #endif 2833 } 2834 } 2835 splx(s); 2836 } 2837 #endif /* defined CB_PCMCIA_POLL */ 2838 2839 /* 2840 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2841 * struct pcmcia_function *pf, 2842 * int ipl, 2843 * int (*func)(void *), 2844 * void *arg); 2845 * 2846 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2847 */ 2848 STATIC void * 2849 pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2850 struct pcmcia_function *pf, int ipl, int (*func)(void *), void *arg) 2851 { 2852 struct pcic_handle *ph = (struct pcic_handle *)pch; 2853 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2854 2855 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2856 /* what should I do? */ 2857 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2858 DPRINTF(("%s does not provide edge nor pulse " 2859 "interrupt\n", sc->sc_dev.dv_xname)); 2860 return NULL; 2861 } 2862 /* 2863 * XXX Noooooo! The interrupt flag must set properly!! 2864 * dumb pcmcia driver!! 2865 */ 2866 } 2867 2868 return pccbb_intr_establish(sc, 0, ipl, func, arg); 2869 } 2870 2871 /* 2872 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2873 * void *ih) 2874 * 2875 * This function disables PC-Card interrupt. 2876 */ 2877 STATIC void 2878 pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 2879 { 2880 struct pcic_handle *ph = (struct pcic_handle *)pch; 2881 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2882 2883 pccbb_intr_disestablish(sc, ih); 2884 } 2885 2886 #if rbus 2887 /* 2888 * static int 2889 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2890 * bus_addr_t addr, bus_size_t size, 2891 * bus_addr_t mask, bus_size_t align, 2892 * int flags, bus_addr_t *addrp; 2893 * bus_space_handle_t *bshp) 2894 * 2895 * This function allocates a portion of memory or io space for 2896 * clients. This function is called from CardBus card drivers. 2897 */ 2898 static int 2899 pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2900 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 2901 int flags, bus_addr_t *addrp, bus_space_handle_t *bshp) 2902 { 2903 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2904 2905 DPRINTF(("pccbb_rbus_cb_space_alloc: addr 0x%lx, size 0x%lx, " 2906 "mask 0x%lx, align 0x%lx\n", (unsigned long)addr, 2907 (unsigned long)size, (unsigned long)mask, (unsigned long)align)); 2908 2909 if (align == 0) { 2910 align = size; 2911 } 2912 2913 if (rb->rb_bt == sc->sc_memt) { 2914 if (align < 16) { 2915 return 1; 2916 } 2917 /* 2918 * XXX: align more than 0x1000 to avoid overwrapping 2919 * memory windows for two or more devices. 0x1000 2920 * means memory window's granularity. 2921 * 2922 * Two or more devices should be able to share same 2923 * memory window region. However, overrapping memory 2924 * window is not good because some devices, such as 2925 * 3Com 3C575[BC], have a broken address decoder and 2926 * intrude other's memory region. 2927 */ 2928 if (align < 0x1000) { 2929 align = 0x1000; 2930 } 2931 } else if (rb->rb_bt == sc->sc_iot) { 2932 if (align < 4) { 2933 return 1; 2934 } 2935 /* XXX: hack for avoiding ISA image */ 2936 if (mask < 0x0100) { 2937 mask = 0x3ff; 2938 addr = 0x300; 2939 } 2940 2941 } else { 2942 DPRINTF(("pccbb_rbus_cb_space_alloc: Bus space tag 0x%lx is " 2943 "NOT used. io: 0x%lx, mem: 0x%lx\n", 2944 (unsigned long)rb->rb_bt, (unsigned long)sc->sc_iot, 2945 (unsigned long)sc->sc_memt)); 2946 return 1; 2947 /* XXX: panic here? */ 2948 } 2949 2950 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 2951 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 2952 return 1; 2953 } 2954 2955 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 2956 2957 return 0; 2958 } 2959 2960 /* 2961 * static int 2962 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 2963 * bus_space_handle_t *bshp, bus_size_t size); 2964 * 2965 * This function is called from CardBus card drivers. 2966 */ 2967 static int 2968 pccbb_rbus_cb_space_free(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2969 bus_space_handle_t bsh, bus_size_t size) 2970 { 2971 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2972 bus_space_tag_t bt = rb->rb_bt; 2973 2974 pccbb_close_win(sc, bt, bsh, size); 2975 2976 if (bt == sc->sc_memt) { 2977 } else if (bt == sc->sc_iot) { 2978 } else { 2979 return 1; 2980 /* XXX: panic here? */ 2981 } 2982 2983 return rbus_space_free(rb, bsh, size, NULL); 2984 } 2985 #endif /* rbus */ 2986 2987 #if rbus 2988 2989 static int 2990 pccbb_open_win(struct pccbb_softc *sc, bus_space_tag_t bst, bus_addr_t addr, 2991 bus_size_t size, bus_space_handle_t bsh, int flags) 2992 { 2993 struct pccbb_win_chain_head *head; 2994 bus_addr_t align; 2995 2996 head = &sc->sc_iowindow; 2997 align = 0x04; 2998 if (sc->sc_memt == bst) { 2999 head = &sc->sc_memwindow; 3000 align = 0x1000; 3001 DPRINTF(("using memory window, 0x%lx 0x%lx 0x%lx\n\n", 3002 (unsigned long)sc->sc_iot, (unsigned long)sc->sc_memt, 3003 (unsigned long)bst)); 3004 } 3005 3006 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 3007 printf("%s: pccbb_open_win: %s winlist insert failed\n", 3008 sc->sc_dev.dv_xname, 3009 (head == &sc->sc_memwindow) ? "mem" : "io"); 3010 } 3011 pccbb_winset(align, sc, bst); 3012 3013 return 0; 3014 } 3015 3016 static int 3017 pccbb_close_win(struct pccbb_softc *sc, bus_space_tag_t bst, 3018 bus_space_handle_t bsh, bus_size_t size) 3019 { 3020 struct pccbb_win_chain_head *head; 3021 bus_addr_t align; 3022 3023 head = &sc->sc_iowindow; 3024 align = 0x04; 3025 if (sc->sc_memt == bst) { 3026 head = &sc->sc_memwindow; 3027 align = 0x1000; 3028 } 3029 3030 if (pccbb_winlist_delete(head, bsh, size)) { 3031 printf("%s: pccbb_close_win: %s winlist delete failed\n", 3032 sc->sc_dev.dv_xname, 3033 (head == &sc->sc_memwindow) ? "mem" : "io"); 3034 } 3035 pccbb_winset(align, sc, bst); 3036 3037 return 0; 3038 } 3039 3040 static int 3041 pccbb_winlist_insert(struct pccbb_win_chain_head *head, bus_addr_t start, 3042 bus_size_t size, bus_space_handle_t bsh, int flags) 3043 { 3044 struct pccbb_win_chain *chainp, *elem; 3045 3046 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 3047 M_NOWAIT)) == NULL) 3048 return (1); /* fail */ 3049 3050 elem->wc_start = start; 3051 elem->wc_end = start + (size - 1); 3052 elem->wc_handle = bsh; 3053 elem->wc_flags = flags; 3054 3055 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3056 chainp = TAILQ_NEXT(chainp, wc_list)) { 3057 if (chainp->wc_end < start) 3058 continue; 3059 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 3060 return (0); 3061 } 3062 3063 TAILQ_INSERT_TAIL(head, elem, wc_list); 3064 return (0); 3065 } 3066 3067 static int 3068 pccbb_winlist_delete(struct pccbb_win_chain_head *head, bus_space_handle_t bsh, 3069 bus_size_t size) 3070 { 3071 struct pccbb_win_chain *chainp; 3072 3073 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3074 chainp = TAILQ_NEXT(chainp, wc_list)) { 3075 if (memcmp(&chainp->wc_handle, &bsh, sizeof(bsh))) 3076 continue; 3077 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 3078 printf("pccbb_winlist_delete: window 0x%lx size " 3079 "inconsistent: 0x%lx, 0x%lx\n", 3080 (unsigned long)chainp->wc_start, 3081 (unsigned long)(chainp->wc_end - chainp->wc_start), 3082 (unsigned long)(size - 1)); 3083 return 1; 3084 } 3085 3086 TAILQ_REMOVE(head, chainp, wc_list); 3087 free(chainp, M_DEVBUF); 3088 3089 return 0; 3090 } 3091 3092 return 1; /* fail: no candidate to remove */ 3093 } 3094 3095 static void 3096 pccbb_winset(bus_addr_t align, struct pccbb_softc *sc, bus_space_tag_t bst) 3097 { 3098 pci_chipset_tag_t pc; 3099 pcitag_t tag; 3100 bus_addr_t mask = ~(align - 1); 3101 struct { 3102 cardbusreg_t win_start; 3103 cardbusreg_t win_limit; 3104 int win_flags; 3105 } win[2]; 3106 struct pccbb_win_chain *chainp; 3107 int offs; 3108 3109 win[0].win_start = win[1].win_start = 0xffffffff; 3110 win[0].win_limit = win[1].win_limit = 0; 3111 win[0].win_flags = win[1].win_flags = 0; 3112 3113 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3114 offs = 0x2c; 3115 if (sc->sc_memt == bst) { 3116 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3117 offs = 0x1c; 3118 } 3119 3120 if (chainp != NULL) { 3121 win[0].win_start = chainp->wc_start & mask; 3122 win[0].win_limit = chainp->wc_end & mask; 3123 win[0].win_flags = chainp->wc_flags; 3124 chainp = TAILQ_NEXT(chainp, wc_list); 3125 } 3126 3127 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3128 if (win[1].win_start == 0xffffffff) { 3129 /* window 1 is not used */ 3130 if ((win[0].win_flags == chainp->wc_flags) && 3131 (win[0].win_limit + align >= 3132 (chainp->wc_start & mask))) { 3133 /* concatenate */ 3134 win[0].win_limit = chainp->wc_end & mask; 3135 } else { 3136 /* make new window */ 3137 win[1].win_start = chainp->wc_start & mask; 3138 win[1].win_limit = chainp->wc_end & mask; 3139 win[1].win_flags = chainp->wc_flags; 3140 } 3141 continue; 3142 } 3143 3144 /* Both windows are engaged. */ 3145 if (win[0].win_flags == win[1].win_flags) { 3146 /* same flags */ 3147 if (win[0].win_flags == chainp->wc_flags) { 3148 if (win[1].win_start - (win[0].win_limit + 3149 align) < 3150 (chainp->wc_start & mask) - 3151 ((chainp->wc_end & mask) + align)) { 3152 /* 3153 * merge window 0 and 1, and set win1 3154 * to chainp 3155 */ 3156 win[0].win_limit = win[1].win_limit; 3157 win[1].win_start = 3158 chainp->wc_start & mask; 3159 win[1].win_limit = 3160 chainp->wc_end & mask; 3161 } else { 3162 win[1].win_limit = 3163 chainp->wc_end & mask; 3164 } 3165 } else { 3166 /* different flags */ 3167 3168 /* concatenate win0 and win1 */ 3169 win[0].win_limit = win[1].win_limit; 3170 /* allocate win[1] to new space */ 3171 win[1].win_start = chainp->wc_start & mask; 3172 win[1].win_limit = chainp->wc_end & mask; 3173 win[1].win_flags = chainp->wc_flags; 3174 } 3175 } else { 3176 /* the flags of win[0] and win[1] is different */ 3177 if (win[0].win_flags == chainp->wc_flags) { 3178 win[0].win_limit = chainp->wc_end & mask; 3179 /* 3180 * XXX this creates overlapping windows, so 3181 * what should the poor bridge do if one is 3182 * cachable, and the other is not? 3183 */ 3184 printf("%s: overlapping windows\n", 3185 sc->sc_dev.dv_xname); 3186 } else { 3187 win[1].win_limit = chainp->wc_end & mask; 3188 } 3189 } 3190 } 3191 3192 pc = sc->sc_pc; 3193 tag = sc->sc_tag; 3194 pci_conf_write(pc, tag, offs, win[0].win_start); 3195 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3196 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3197 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3198 DPRINTF(("--pccbb_winset: win0 [0x%lx, 0x%lx), win1 [0x%lx, 0x%lx)\n", 3199 (unsigned long)pci_conf_read(pc, tag, offs), 3200 (unsigned long)pci_conf_read(pc, tag, offs + 4) + align, 3201 (unsigned long)pci_conf_read(pc, tag, offs + 8), 3202 (unsigned long)pci_conf_read(pc, tag, offs + 12) + align)); 3203 3204 if (bst == sc->sc_memt) { 3205 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BRIDGE_CONTROL_REG); 3206 3207 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 3208 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 3209 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3210 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 3211 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3212 pci_conf_write(pc, tag, PCI_BRIDGE_CONTROL_REG, bcr); 3213 } 3214 } 3215 3216 #endif /* rbus */ 3217 3218 static bool 3219 pccbb_suspend(device_t dv) 3220 { 3221 struct pccbb_softc *sc = device_private(dv); 3222 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3223 bus_space_handle_t base_memh = sc->sc_base_memh; 3224 pcireg_t reg; 3225 3226 if (sc->sc_pil_intr_enable) 3227 (void)pccbbintr_function(sc); 3228 sc->sc_pil_intr_enable = 0; 3229 3230 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3231 /* Disable interrupts. */ 3232 reg &= ~(CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER); 3233 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3234 /* XXX joerg Disable power to the socket? */ 3235 3236 if (sc->sc_chipset == CB_RX5C47X) 3237 sc->sc_ricoh_misc_ctrl = pci_conf_read(sc->sc_pc, 3238 sc->sc_tag, RICOH_PCI_MISC_CTRL); 3239 3240 return true; 3241 } 3242 3243 static bool 3244 pccbb_resume(device_t dv) 3245 { 3246 struct pccbb_softc *sc = device_private(dv); 3247 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3248 bus_space_handle_t base_memh = sc->sc_base_memh; 3249 pcireg_t reg; 3250 3251 pccbb_chipinit(sc); 3252 /* setup memory and io space window for CB */ 3253 pccbb_winset(0x1000, sc, sc->sc_memt); 3254 pccbb_winset(0x04, sc, sc->sc_iot); 3255 if (sc->sc_chipset == CB_RX5C47X) 3256 pci_conf_write(sc->sc_pc, sc->sc_tag, 3257 RICOH_PCI_MISC_CTRL, sc->sc_ricoh_misc_ctrl); 3258 3259 /* CSC Interrupt: Card detect interrupt on */ 3260 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3261 /* Card detect intr is turned on. */ 3262 reg |= CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; 3263 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3264 /* reset interrupt */ 3265 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3266 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3267 3268 /* 3269 * check for card insertion or removal during suspend period. 3270 * XXX: the code can't cope with card swap (remove then 3271 * insert). how can we detect such situation? 3272 */ 3273 (void)pccbbintr(sc); 3274 3275 sc->sc_pil_intr_enable = 1; 3276 3277 return true; 3278 } 3279
Indexes created Tue Oct 14 21:09:58 GMT 2025