pccbb.c revision 1.147.2.1
1 /* $NetBSD: pccbb.c,v 1.147.2.1 2007/11/06 23:29:22 matt Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: pccbb.c,v 1.147.2.1 2007/11/06 23:29:22 matt Exp $"); 35 36 /* 37 #define CBB_DEBUG 38 #define SHOW_REGS 39 */ 40 41 /* 42 * BROKEN! 43 #define PCCBB_PCMCIA_POLL 44 #define CB_PCMCIA_POLL 45 #define CB_PCMCIA_POLL_ONLY 46 #define LEVEL2 47 */ 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/kernel.h> 52 #include <sys/errno.h> 53 #include <sys/ioctl.h> 54 #include <sys/reboot.h> /* for bootverbose */ 55 #include <sys/syslog.h> 56 #include <sys/device.h> 57 #include <sys/malloc.h> 58 #include <sys/proc.h> 59 60 #include <sys/intr.h> 61 #include <sys/bus.h> 62 63 #include <dev/pci/pcivar.h> 64 #include <dev/pci/pcireg.h> 65 #include <dev/pci/pcidevs.h> 66 67 #include <dev/pci/pccbbreg.h> 68 69 #include <dev/cardbus/cardslotvar.h> 70 71 #include <dev/cardbus/cardbusvar.h> 72 73 #include <dev/pcmcia/pcmciareg.h> 74 #include <dev/pcmcia/pcmciavar.h> 75 76 #include <dev/ic/i82365reg.h> 77 #include <dev/ic/i82365var.h> 78 #include <dev/pci/pccbbvar.h> 79 80 #include "locators.h" 81 82 #ifndef __NetBSD_Version__ 83 struct cfdriver cbb_cd = { 84 NULL, "cbb", DV_DULL 85 }; 86 #endif 87 88 #ifdef CBB_DEBUG 89 #define DPRINTF(x) printf x 90 #define STATIC 91 #else 92 #define DPRINTF(x) 93 #define STATIC static 94 #endif 95 96 /* 97 * delay_ms() is wait in milliseconds. It should be used instead 98 * of delay() if you want to wait more than 1 ms. 99 */ 100 static inline void 101 delay_ms(int millis, void *param) 102 { 103 if (cold) 104 delay(millis * 1000); 105 else 106 tsleep(param, PWAIT, "pccbb", MAX(2, hz * millis / 1000)); 107 } 108 109 int pcicbbmatch(struct device *, struct cfdata *, void *); 110 void pccbbattach(struct device *, struct device *, void *); 111 int pccbbintr(void *); 112 static void pci113x_insert(void *); 113 static int pccbbintr_function(struct pccbb_softc *); 114 115 static int pccbb_detect_card(struct pccbb_softc *); 116 117 static void pccbb_pcmcia_write(struct pcic_handle *, int, u_int8_t); 118 static u_int8_t pccbb_pcmcia_read(struct pcic_handle *, int); 119 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 120 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 121 122 STATIC int cb_reset(struct pccbb_softc *); 123 STATIC int cb_detect_voltage(struct pccbb_softc *); 124 STATIC int cbbprint(void *, const char *); 125 126 static int cb_chipset(u_int32_t, int *); 127 STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *, 128 struct pcmciabus_attach_args *); 129 #if 0 130 STATIC void pccbb_pcmcia_attach_card(struct pcic_handle *); 131 STATIC void pccbb_pcmcia_detach_card(struct pcic_handle *, int); 132 STATIC void pccbb_pcmcia_deactivate_card(struct pcic_handle *); 133 #endif 134 135 STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int); 136 STATIC int pccbb_power(cardbus_chipset_tag_t, int); 137 STATIC int pccbb_cardenable(struct pccbb_softc * sc, int function); 138 #if !rbus 139 static int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 140 static int pccbb_io_close(cardbus_chipset_tag_t, int); 141 static int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 142 static int pccbb_mem_close(cardbus_chipset_tag_t, int); 143 #endif /* !rbus */ 144 static void *pccbb_intr_establish(struct pccbb_softc *, int irq, 145 int level, int (*ih) (void *), void *sc); 146 static void pccbb_intr_disestablish(struct pccbb_softc *, void *ih); 147 148 static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t, int irq, 149 int level, int (*ih) (void *), void *sc); 150 static void pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih); 151 152 static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t, int, int); 153 static void pccbb_free_tag(cardbus_chipset_tag_t, cardbustag_t); 154 static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t, cardbustag_t, int); 155 static void pccbb_conf_write(cardbus_chipset_tag_t, cardbustag_t, int, 156 cardbusreg_t); 157 static void pccbb_chipinit(struct pccbb_softc *); 158 159 STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 160 struct pcmcia_mem_handle *); 161 STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t, 162 struct pcmcia_mem_handle *); 163 STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 164 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *); 165 STATIC void pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t, int); 166 STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 167 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 168 STATIC void pccbb_pcmcia_io_free(pcmcia_chipset_handle_t, 169 struct pcmcia_io_handle *); 170 STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 171 bus_size_t, struct pcmcia_io_handle *, int *); 172 STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t, int); 173 STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t, 174 struct pcmcia_function *, int, int (*)(void *), void *); 175 STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t, void *); 176 STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t); 177 STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t); 178 STATIC void pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t, int); 179 STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch); 180 181 static int pccbb_pcmcia_wait_ready(struct pcic_handle *); 182 static void pccbb_pcmcia_delay(struct pcic_handle *, int, const char *); 183 184 static void pccbb_pcmcia_do_io_map(struct pcic_handle *, int); 185 static void pccbb_pcmcia_do_mem_map(struct pcic_handle *, int); 186 static void pccbb_powerhook(int, void *); 187 188 /* bus-space allocation and deallocation functions */ 189 #if rbus 190 191 static int pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t, rbus_tag_t, 192 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 193 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp); 194 static int pccbb_rbus_cb_space_free(cardbus_chipset_tag_t, rbus_tag_t, 195 bus_space_handle_t, bus_size_t); 196 197 #endif /* rbus */ 198 199 #if rbus 200 201 static int pccbb_open_win(struct pccbb_softc *, bus_space_tag_t, 202 bus_addr_t, bus_size_t, bus_space_handle_t, int flags); 203 static int pccbb_close_win(struct pccbb_softc *, bus_space_tag_t, 204 bus_space_handle_t, bus_size_t); 205 static int pccbb_winlist_insert(struct pccbb_win_chain_head *, bus_addr_t, 206 bus_size_t, bus_space_handle_t, int); 207 static int pccbb_winlist_delete(struct pccbb_win_chain_head *, 208 bus_space_handle_t, bus_size_t); 209 static void pccbb_winset(bus_addr_t align, struct pccbb_softc *, 210 bus_space_tag_t); 211 void pccbb_winlist_show(struct pccbb_win_chain *); 212 213 #endif /* rbus */ 214 215 /* for config_defer */ 216 static void pccbb_pci_callback(struct device *); 217 218 #if defined SHOW_REGS 219 static void cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, 220 bus_space_tag_t memt, bus_space_handle_t memh); 221 #endif 222 223 CFATTACH_DECL(cbb_pci, sizeof(struct pccbb_softc), 224 pcicbbmatch, pccbbattach, NULL, NULL); 225 226 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 227 pccbb_pcmcia_mem_alloc, 228 pccbb_pcmcia_mem_free, 229 pccbb_pcmcia_mem_map, 230 pccbb_pcmcia_mem_unmap, 231 pccbb_pcmcia_io_alloc, 232 pccbb_pcmcia_io_free, 233 pccbb_pcmcia_io_map, 234 pccbb_pcmcia_io_unmap, 235 pccbb_pcmcia_intr_establish, 236 pccbb_pcmcia_intr_disestablish, 237 pccbb_pcmcia_socket_enable, 238 pccbb_pcmcia_socket_disable, 239 pccbb_pcmcia_socket_settype, 240 pccbb_pcmcia_card_detect 241 }; 242 243 #if rbus 244 static struct cardbus_functions pccbb_funcs = { 245 pccbb_rbus_cb_space_alloc, 246 pccbb_rbus_cb_space_free, 247 pccbb_cb_intr_establish, 248 pccbb_cb_intr_disestablish, 249 pccbb_ctrl, 250 pccbb_power, 251 pccbb_make_tag, 252 pccbb_free_tag, 253 pccbb_conf_read, 254 pccbb_conf_write, 255 }; 256 #else 257 static struct cardbus_functions pccbb_funcs = { 258 pccbb_ctrl, 259 pccbb_power, 260 pccbb_mem_open, 261 pccbb_mem_close, 262 pccbb_io_open, 263 pccbb_io_close, 264 pccbb_cb_intr_establish, 265 pccbb_cb_intr_disestablish, 266 pccbb_make_tag, 267 pccbb_conf_read, 268 pccbb_conf_write, 269 }; 270 #endif 271 272 int 273 pcicbbmatch(struct device *parent, struct cfdata *match, void *aux) 274 { 275 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 276 277 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 278 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 279 PCI_INTERFACE(pa->pa_class) == 0) { 280 return 1; 281 } 282 283 return 0; 284 } 285 286 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 287 | ((prod) << PCI_PRODUCT_SHIFT)) 288 289 const struct yenta_chipinfo { 290 pcireg_t yc_id; /* vendor tag | product tag */ 291 int yc_chiptype; 292 int yc_flags; 293 } yc_chipsets[] = { 294 /* Texas Instruments chips */ 295 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 296 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 297 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 298 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 299 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI125X, 300 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 301 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 302 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 303 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 304 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 305 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 306 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 307 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI125X, 308 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 309 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI125X, 310 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 311 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 312 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 313 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 314 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 315 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 316 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 317 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI125X, 318 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 319 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 320 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 321 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1520), CB_TI12XX, 322 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 323 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4410YENTA), CB_TI12XX, 324 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 325 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4520YENTA), CB_TI12XX, 326 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 327 328 /* Ricoh chips */ 329 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 330 PCCBB_PCMCIA_MEM_32}, 331 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 332 PCCBB_PCMCIA_MEM_32}, 333 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 334 PCCBB_PCMCIA_MEM_32}, 335 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 336 PCCBB_PCMCIA_MEM_32}, 337 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 338 PCCBB_PCMCIA_MEM_32}, 339 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 340 PCCBB_PCMCIA_MEM_32}, 341 342 /* Toshiba products */ 343 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 344 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 345 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 346 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 347 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 348 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 349 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 350 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 351 352 /* Cirrus Logic products */ 353 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 354 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 355 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 356 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 357 358 /* sentinel, or Generic chip */ 359 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 360 }; 361 362 static int 363 cb_chipset(u_int32_t pci_id, int *flagp) 364 { 365 const struct yenta_chipinfo *yc; 366 367 /* Loop over except the last default entry. */ 368 for (yc = yc_chipsets; yc < yc_chipsets + 369 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 370 if (pci_id == yc->yc_id) 371 break; 372 373 if (flagp != NULL) 374 *flagp = yc->yc_flags; 375 376 return (yc->yc_chiptype); 377 } 378 379 static void 380 pccbb_shutdown(void *arg) 381 { 382 struct pccbb_softc *sc = arg; 383 pcireg_t command; 384 385 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 386 387 /* 388 * turn off power 389 * 390 * XXX - do not turn off power if chipset is TI 113X because 391 * only TI 1130 with PowerMac 2400 hangs in pccbb_power(). 392 */ 393 if (sc->sc_chipset != CB_TI113X) { 394 pccbb_power((cardbus_chipset_tag_t)sc, 395 CARDBUS_VCC_0V | CARDBUS_VPP_0V); 396 } 397 398 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 399 0); 400 401 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 402 403 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 404 PCI_COMMAND_MASTER_ENABLE); 405 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 406 407 } 408 409 void 410 pccbbattach(struct device *parent, struct device *self, void *aux) 411 { 412 struct pccbb_softc *sc = (void *)self; 413 struct pci_attach_args *pa = aux; 414 pci_chipset_tag_t pc = pa->pa_pc; 415 pcireg_t busreg, reg, sock_base; 416 bus_addr_t sockbase; 417 char devinfo[256]; 418 int flags; 419 int pwrmgt_offs; 420 421 #ifdef __HAVE_PCCBB_ATTACH_HOOK 422 pccbb_attach_hook(parent, self, pa); 423 #endif 424 425 callout_init(&sc->sc_insert_ch, 0); 426 callout_setfunc(&sc->sc_insert_ch, pci113x_insert, sc); 427 428 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 429 430 pci_devinfo(pa->pa_id, 0, 0, devinfo, sizeof(devinfo)); 431 printf(": %s (rev. 0x%02x)", devinfo, PCI_REVISION(pa->pa_class)); 432 DPRINTF((" (chipflags %x)", flags)); 433 printf("\n"); 434 435 TAILQ_INIT(&sc->sc_memwindow); 436 TAILQ_INIT(&sc->sc_iowindow); 437 438 #if rbus 439 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 440 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 441 442 #if 0 443 printf("pa->pa_memt: %08x vs rbus_mem->rb_bt: %08x\n", 444 pa->pa_memt, sc->sc_rbus_memt->rb_bt); 445 #endif 446 #endif /* rbus */ 447 448 sc->sc_flags &= ~CBB_MEMHMAPPED; 449 450 /* power management: set D0 state */ 451 sc->sc_pwrmgt_offs = 0; 452 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, 453 &pwrmgt_offs, 0)) { 454 reg = pci_conf_read(pc, pa->pa_tag, pwrmgt_offs + PCI_PMCSR); 455 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 456 reg & 0x100 /* PCI_PMCSR_PME_EN */) { 457 reg &= ~PCI_PMCSR_STATE_MASK; 458 reg |= PCI_PMCSR_STATE_D0; 459 reg &= ~(0x100 /* PCI_PMCSR_PME_EN */); 460 pci_conf_write(pc, pa->pa_tag, 461 pwrmgt_offs + PCI_PMCSR, reg); 462 } 463 464 sc->sc_pwrmgt_offs = pwrmgt_offs; 465 } 466 467 /* 468 * MAP socket registers and ExCA registers on memory-space 469 * When no valid address is set on socket base registers (on pci 470 * config space), get it not polite way. 471 */ 472 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 473 474 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 475 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 476 /* The address must be valid. */ 477 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 478 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL)) { 479 printf("%s: can't map socket base address 0x%lx\n", 480 sc->sc_dev.dv_xname, (unsigned long)sock_base); 481 /* 482 * I think it's funny: socket base registers must be 483 * mapped on memory space, but ... 484 */ 485 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 486 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 487 NULL)) { 488 printf("%s: can't map socket base address" 489 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 490 (unsigned long)sockbase); 491 /* give up... allocate reg space via rbus. */ 492 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 493 } else 494 sc->sc_flags |= CBB_MEMHMAPPED; 495 } else { 496 DPRINTF(("%s: socket base address 0x%lx\n", 497 sc->sc_dev.dv_xname, (unsigned long)sockbase)); 498 sc->sc_flags |= CBB_MEMHMAPPED; 499 } 500 } 501 502 sc->sc_mem_start = 0; /* XXX */ 503 sc->sc_mem_end = 0xffffffff; /* XXX */ 504 505 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 506 507 /* pccbb_machdep.c end */ 508 509 #if defined CBB_DEBUG 510 { 511 static const char *intrname[] = { "NON", "A", "B", "C", "D" }; 512 printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname, 513 intrname[pa->pa_intrpin], pa->pa_intrline); 514 } 515 #endif 516 517 /* setup softc */ 518 sc->sc_pc = pc; 519 sc->sc_iot = pa->pa_iot; 520 sc->sc_memt = pa->pa_memt; 521 sc->sc_dmat = pa->pa_dmat; 522 sc->sc_tag = pa->pa_tag; 523 sc->sc_function = pa->pa_function; 524 sc->sc_sockbase = sock_base; 525 sc->sc_busnum = busreg; 526 527 memcpy(&sc->sc_pa, pa, sizeof(*pa)); 528 529 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 530 531 shutdownhook_establish(pccbb_shutdown, sc); 532 533 /* Disable legacy register mapping. */ 534 switch (sc->sc_chipset) { 535 case CB_RX5C46X: /* fallthrough */ 536 #if 0 537 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 538 case CB_RX5C47X: 539 #endif 540 /* 541 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 542 * cannot be disabled by substituting 0 into PCI_LEGACY 543 * register. Ricoh CardBus bridges have special bits on Bridge 544 * control reg (addr 0x3e on PCI config space). 545 */ 546 reg = pci_conf_read(pc, pa->pa_tag, PCI_BRIDGE_CONTROL_REG); 547 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 548 pci_conf_write(pc, pa->pa_tag, PCI_BRIDGE_CONTROL_REG, reg); 549 break; 550 551 default: 552 /* XXX I don't know proper way to kill legacy I/O. */ 553 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 554 break; 555 } 556 557 config_defer(self, pccbb_pci_callback); 558 } 559 560 561 562 563 /* 564 * static void pccbb_pci_callback(struct device *self) 565 * 566 * The actual attach routine: get memory space for YENTA register 567 * space, setup YENTA register and route interrupt. 568 * 569 * This function should be deferred because this device may obtain 570 * memory space dynamically. This function must avoid obtaining 571 * memory area which has already kept for another device. 572 */ 573 static void 574 pccbb_pci_callback(struct device *self) 575 { 576 struct pccbb_softc *sc = (void *)self; 577 pci_chipset_tag_t pc = sc->sc_pc; 578 pci_intr_handle_t ih; 579 const char *intrstr = NULL; 580 bus_addr_t sockbase; 581 struct cbslot_attach_args cba; 582 struct pcmciabus_attach_args paa; 583 struct cardslot_attach_args caa; 584 struct cardslot_softc *csc; 585 586 if (!(sc->sc_flags & CBB_MEMHMAPPED)) { 587 /* The socket registers aren't mapped correctly. */ 588 #if rbus 589 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 590 (sc->sc_chipset == CB_RX5C47X 591 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 592 0, &sockbase, &sc->sc_base_memh)) { 593 return; 594 } 595 sc->sc_base_memt = sc->sc_memt; 596 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 597 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 598 sc->sc_dev.dv_xname, (unsigned long)sockbase, 599 (unsigned long)pci_conf_read(pc, sc->sc_tag, 600 PCI_SOCKBASE))); 601 #else 602 sc->sc_base_memt = sc->sc_memt; 603 #if !defined CBB_PCI_BASE 604 #define CBB_PCI_BASE 0x20000000 605 #endif 606 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 607 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 608 /* cannot allocate memory space */ 609 return; 610 } 611 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 612 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 613 sc->sc_dev.dv_xname, (unsigned long)sock_base, 614 (unsigned long)pci_conf_read(pc, 615 sc->sc_tag, PCI_SOCKBASE))); 616 sc->sc_sockbase = sockbase; 617 #endif 618 sc->sc_flags |= CBB_MEMHMAPPED; 619 } 620 621 /* bus bridge initialization */ 622 pccbb_chipinit(sc); 623 624 /* clear data structure for child device interrupt handlers */ 625 LIST_INIT(&sc->sc_pil); 626 sc->sc_pil_intr_enable = 1; 627 628 /* Map and establish the interrupt. */ 629 if (pci_intr_map(&sc->sc_pa, &ih)) { 630 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 631 return; 632 } 633 intrstr = pci_intr_string(pc, ih); 634 635 /* 636 * XXX pccbbintr should be called under the priority lower 637 * than any other hard interupts. 638 */ 639 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 640 641 if (sc->sc_ih == NULL) { 642 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 643 if (intrstr != NULL) { 644 printf(" at %s", intrstr); 645 } 646 printf("\n"); 647 return; 648 } 649 650 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 651 powerhook_establish(sc->sc_dev.dv_xname, pccbb_powerhook, sc); 652 653 { 654 u_int32_t sockstat; 655 656 sockstat = bus_space_read_4(sc->sc_base_memt, 657 sc->sc_base_memh, CB_SOCKET_STAT); 658 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 659 sc->sc_flags |= CBB_CARDEXIST; 660 } 661 } 662 663 /* 664 * attach cardbus 665 */ 666 { 667 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 668 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 669 670 /* initialize cbslot_attach */ 671 cba.cba_busname = "cardbus"; 672 cba.cba_iot = sc->sc_iot; 673 cba.cba_memt = sc->sc_memt; 674 cba.cba_dmat = sc->sc_dmat; 675 cba.cba_bus = (busreg >> 8) & 0x0ff; 676 cba.cba_cc = (void *)sc; 677 cba.cba_cf = &pccbb_funcs; 678 cba.cba_intrline = sc->sc_pa.pa_intrline; 679 680 #if rbus 681 cba.cba_rbus_iot = sc->sc_rbus_iot; 682 cba.cba_rbus_memt = sc->sc_rbus_memt; 683 #endif 684 685 cba.cba_cacheline = PCI_CACHELINE(bhlc); 686 cba.cba_lattimer = PCI_LATTIMER(bhlc); 687 688 if (bootverbose) { 689 printf("%s: cacheline 0x%x lattimer 0x%x\n", 690 sc->sc_dev.dv_xname, cba.cba_cacheline, 691 cba.cba_lattimer); 692 printf("%s: bhlc 0x%x\n", 693 device_xname(&sc->sc_dev), bhlc); 694 } 695 #if defined SHOW_REGS 696 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 697 sc->sc_base_memh); 698 #endif 699 } 700 701 pccbb_pcmcia_attach_setup(sc, &paa); 702 caa.caa_cb_attach = NULL; 703 if (cba.cba_bus == 0) 704 printf("%s: secondary bus number uninitialized; try PCI_BUS_FIXUP\n", sc->sc_dev.dv_xname); 705 else 706 caa.caa_cb_attach = &cba; 707 caa.caa_16_attach = &paa; 708 caa.caa_ph = &sc->sc_pcmcia_h; 709 710 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 711 DPRINTF(("%s: found cardslot\n", __func__)); 712 sc->sc_csc = csc; 713 } 714 715 return; 716 } 717 718 719 720 721 722 /* 723 * static void pccbb_chipinit(struct pccbb_softc *sc) 724 * 725 * This function initialize YENTA chip registers listed below: 726 * 1) PCI command reg, 727 * 2) PCI and CardBus latency timer, 728 * 3) route PCI interrupt, 729 * 4) close all memory and io windows. 730 * 5) turn off bus power. 731 * 6) card detect and power cycle interrupts on. 732 * 7) clear interrupt 733 */ 734 static void 735 pccbb_chipinit(struct pccbb_softc *sc) 736 { 737 pci_chipset_tag_t pc = sc->sc_pc; 738 pcitag_t tag = sc->sc_tag; 739 bus_space_tag_t bmt = sc->sc_base_memt; 740 bus_space_handle_t bmh = sc->sc_base_memh; 741 pcireg_t bcr, bhlc, cbctl, csr, lscp, mfunc, slotctl, sockctl, sockmask, 742 sysctrl; 743 744 /* 745 * Set PCI command reg. 746 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 747 */ 748 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 749 /* I believe it is harmless. */ 750 csr |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 751 PCI_COMMAND_MASTER_ENABLE); 752 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 753 754 /* 755 * Set CardBus latency timer. 756 */ 757 lscp = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 758 if (PCI_CB_LATENCY(lscp) < 0x20) { 759 lscp &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 760 lscp |= (0x20 << PCI_CB_LATENCY_SHIFT); 761 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, lscp); 762 } 763 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 764 PCI_CB_LATENCY(lscp), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 765 766 /* 767 * Set PCI latency timer. 768 */ 769 bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG); 770 if (PCI_LATTIMER(bhlc) < 0x10) { 771 bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 772 bhlc |= (0x10 << PCI_LATTIMER_SHIFT); 773 pci_conf_write(pc, tag, PCI_BHLC_REG, bhlc); 774 } 775 DPRINTF(("PCI latency timer 0x%x (%x)\n", 776 PCI_LATTIMER(bhlc), pci_conf_read(pc, tag, PCI_BHLC_REG))); 777 778 779 /* Route functional interrupts to PCI. */ 780 bcr = pci_conf_read(pc, tag, PCI_BRIDGE_CONTROL_REG); 781 bcr |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 782 bcr |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 783 /* assert reset */ 784 bcr |= PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT; 785 pci_conf_write(pc, tag, PCI_BRIDGE_CONTROL_REG, bcr); 786 787 switch (sc->sc_chipset) { 788 case CB_TI113X: 789 cbctl = pci_conf_read(pc, tag, PCI_CBCTRL); 790 /* This bit is shared, but may read as 0 on some chips, so set 791 it explicitly on both functions. */ 792 cbctl |= PCI113X_CBCTRL_PCI_IRQ_ENA; 793 /* CSC intr enable */ 794 cbctl |= PCI113X_CBCTRL_PCI_CSC; 795 /* functional intr prohibit | prohibit ISA routing */ 796 cbctl &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 797 pci_conf_write(pc, tag, PCI_CBCTRL, cbctl); 798 break; 799 800 case CB_TI12XX: 801 /* 802 * Some TI 12xx (and [14][45]xx) based pci cards 803 * sometimes have issues with the MFUNC register not 804 * being initialized due to a bad EEPROM on board. 805 * Laptops that this matters on have this register 806 * properly initialized. 807 * 808 * The TI125X parts have a different register. 809 */ 810 mfunc = pci_conf_read(pc, tag, PCI12XX_MFUNC); 811 if (mfunc == 0) { 812 mfunc &= ~PCI12XX_MFUNC_PIN0; 813 mfunc |= PCI12XX_MFUNC_PIN0_INTA; 814 if ((pci_conf_read(pc, tag, PCI_SYSCTRL) & 815 PCI12XX_SYSCTRL_INTRTIE) == 0) { 816 mfunc &= ~PCI12XX_MFUNC_PIN1; 817 mfunc |= PCI12XX_MFUNC_PIN1_INTB; 818 } 819 pci_conf_write(pc, tag, PCI12XX_MFUNC, mfunc); 820 } 821 /* fallthrough */ 822 823 case CB_TI125X: 824 /* 825 * Disable zoom video. Some machines initialize this 826 * improperly and experience has shown that this helps 827 * prevent strange behavior. 828 */ 829 pci_conf_write(pc, tag, PCI12XX_MMCTRL, 0); 830 831 sysctrl = pci_conf_read(pc, tag, PCI_SYSCTRL); 832 sysctrl |= PCI12XX_SYSCTRL_VCCPROT; 833 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 834 cbctl = pci_conf_read(pc, tag, PCI_CBCTRL); 835 cbctl |= PCI12XX_CBCTRL_CSC; 836 pci_conf_write(pc, tag, PCI_CBCTRL, cbctl); 837 break; 838 839 case CB_TOPIC95B: 840 sockctl = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 841 sockctl |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 842 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, sockctl); 843 slotctl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 844 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 845 sc->sc_dev.dv_xname, slotctl)); 846 slotctl |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 847 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 848 slotctl &= ~TOPIC_SLOT_CTRL_SWDETECT; 849 DPRINTF(("0x%x\n", slotctl)); 850 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slotctl); 851 break; 852 853 case CB_TOPIC97: 854 slotctl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 855 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 856 sc->sc_dev.dv_xname, slotctl)); 857 slotctl |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 858 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 859 slotctl &= ~TOPIC_SLOT_CTRL_SWDETECT; 860 slotctl |= TOPIC97_SLOT_CTRL_PCIINT; 861 slotctl &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 862 DPRINTF(("0x%x\n", slotctl)); 863 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slotctl); 864 /* make sure to assert LV card support bits */ 865 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 866 0x800 + 0x3e, 867 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 868 0x800 + 0x3e) | 0x03); 869 break; 870 } 871 872 /* Close all memory and I/O windows. */ 873 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 874 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 875 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 876 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 877 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 878 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 879 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 880 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 881 882 /* reset 16-bit pcmcia bus */ 883 bus_space_write_1(bmt, bmh, 0x800 + PCIC_INTR, 884 bus_space_read_1(bmt, bmh, 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 885 886 /* turn off power */ 887 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 888 889 /* CSC Interrupt: Card detect and power cycle interrupts on */ 890 sockmask = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 891 sockmask |= CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; 892 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, sockmask); 893 /* reset interrupt */ 894 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 895 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 896 } 897 898 899 900 901 /* 902 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 903 * struct pcmciabus_attach_args *paa) 904 * 905 * This function attaches 16-bit PCcard bus. 906 */ 907 STATIC void 908 pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 909 struct pcmciabus_attach_args *paa) 910 { 911 struct pcic_handle *ph = &sc->sc_pcmcia_h; 912 #if rbus 913 rbus_tag_t rb; 914 #endif 915 916 /* initialize pcmcia part in pccbb_softc */ 917 ph->ph_parent = (struct device *)sc; 918 ph->sock = sc->sc_function; 919 ph->flags = 0; 920 ph->shutdown = 0; 921 ph->ih_irq = sc->sc_pa.pa_intrline; 922 ph->ph_bus_t = sc->sc_base_memt; 923 ph->ph_bus_h = sc->sc_base_memh; 924 ph->ph_read = pccbb_pcmcia_read; 925 ph->ph_write = pccbb_pcmcia_write; 926 sc->sc_pct = &pccbb_pcmcia_funcs; 927 928 /* 929 * We need to do a few things here: 930 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 931 * setting the IRQ numbers to 0. 932 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 933 * routing of CSC interrupts (e.g. card removal) to PCI while in 934 * PCMCIA mode. We just leave this set all the time. 935 * 3) Enable card insertion/removal interrupts in case the chip also 936 * needs that while in PCMCIA mode. 937 * 4) Clear any pending CSC interrupt. 938 */ 939 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE); 940 if (sc->sc_chipset == CB_TI113X) { 941 Pcic_write(ph, PCIC_CSC_INTR, 0); 942 } else { 943 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 944 Pcic_read(ph, PCIC_CSC); 945 } 946 947 /* initialize pcmcia bus attachment */ 948 paa->paa_busname = "pcmcia"; 949 paa->pct = sc->sc_pct; 950 paa->pch = ph; 951 paa->iobase = 0; /* I don't use them */ 952 paa->iosize = 0; 953 #if rbus 954 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 955 paa->iobase = rb->rb_start + rb->rb_offset; 956 paa->iosize = rb->rb_end - rb->rb_start; 957 #endif 958 959 return; 960 } 961 962 #if 0 963 STATIC void 964 pccbb_pcmcia_attach_card(struct pcic_handle *ph) 965 { 966 if (ph->flags & PCIC_FLAG_CARDP) { 967 panic("pccbb_pcmcia_attach_card: already attached"); 968 } 969 970 /* call the MI attach function */ 971 pcmcia_card_attach(ph->pcmcia); 972 973 ph->flags |= PCIC_FLAG_CARDP; 974 } 975 976 STATIC void 977 pccbb_pcmcia_detach_card(struct pcic_handle *ph, int flags) 978 { 979 if (!(ph->flags & PCIC_FLAG_CARDP)) { 980 panic("pccbb_pcmcia_detach_card: already detached"); 981 } 982 983 ph->flags &= ~PCIC_FLAG_CARDP; 984 985 /* call the MI detach function */ 986 pcmcia_card_detach(ph->pcmcia, flags); 987 } 988 #endif 989 990 /* 991 * int pccbbintr(arg) 992 * void *arg; 993 * This routine handles the interrupt from Yenta PCI-CardBus bridge 994 * itself. 995 */ 996 int 997 pccbbintr(void *arg) 998 { 999 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1000 u_int32_t sockevent, sockstate; 1001 bus_space_tag_t memt = sc->sc_base_memt; 1002 bus_space_handle_t memh = sc->sc_base_memh; 1003 struct pcic_handle *ph = &sc->sc_pcmcia_h; 1004 1005 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 1006 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 1007 Pcic_read(ph, PCIC_CSC); 1008 1009 if (sockevent == 0) { 1010 /* This intr is not for me: it may be for my child devices. */ 1011 if (sc->sc_pil_intr_enable) { 1012 return pccbbintr_function(sc); 1013 } else { 1014 return 0; 1015 } 1016 } 1017 1018 aprint_debug("%s: enter sockevent %" PRIx32 "\n", __func__, sockevent); 1019 1020 if (sockevent & CB_SOCKET_EVENT_CD) { 1021 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1022 if (0x00 != (sockstate & CB_SOCKET_STAT_CD)) { 1023 /* A card should be removed. */ 1024 if (sc->sc_flags & CBB_CARDEXIST) { 1025 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 1026 sockevent)); 1027 DPRINTF((" card removed, 0x%08x\n", sockstate)); 1028 sc->sc_flags &= ~CBB_CARDEXIST; 1029 if (sc->sc_csc->sc_status & 1030 CARDSLOT_STATUS_CARD_16) { 1031 #if 0 1032 struct pcic_handle *ph = 1033 &sc->sc_pcmcia_h; 1034 1035 pcmcia_card_deactivate(ph->pcmcia); 1036 pccbb_pcmcia_socket_disable(ph); 1037 pccbb_pcmcia_detach_card(ph, 1038 DETACH_FORCE); 1039 #endif 1040 cardslot_event_throw(sc->sc_csc, 1041 CARDSLOT_EVENT_REMOVAL_16); 1042 } else if (sc->sc_csc->sc_status & 1043 CARDSLOT_STATUS_CARD_CB) { 1044 /* Cardbus intr removed */ 1045 cardslot_event_throw(sc->sc_csc, 1046 CARDSLOT_EVENT_REMOVAL_CB); 1047 } 1048 } else if (sc->sc_flags & CBB_INSERTING) { 1049 sc->sc_flags &= ~CBB_INSERTING; 1050 callout_stop(&sc->sc_insert_ch); 1051 } 1052 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 1053 /* 1054 * The pccbbintr may called from powerdown hook when 1055 * the system resumed, to detect the card 1056 * insertion/removal during suspension. 1057 */ 1058 (sc->sc_flags & CBB_CARDEXIST) == 0) { 1059 if (sc->sc_flags & CBB_INSERTING) { 1060 callout_stop(&sc->sc_insert_ch); 1061 } 1062 callout_schedule(&sc->sc_insert_ch, hz / 5); 1063 sc->sc_flags |= CBB_INSERTING; 1064 } 1065 } 1066 1067 if (sockevent & CB_SOCKET_EVENT_POWER) { 1068 DPRINTF(("Powercycling because of socket event\n")); 1069 /* XXX: Does not happen when attaching a 16-bit card */ 1070 sc->sc_pwrcycle++; 1071 wakeup(&sc->sc_pwrcycle); 1072 } 1073 1074 return (1); 1075 } 1076 1077 /* 1078 * static int pccbbintr_function(struct pccbb_softc *sc) 1079 * 1080 * This function calls each interrupt handler registered at the 1081 * bridge. The interrupt handlers are called in registered order. 1082 */ 1083 static int 1084 pccbbintr_function(struct pccbb_softc *sc) 1085 { 1086 int retval = 0, val; 1087 struct pccbb_intrhand_list *pil; 1088 int s; 1089 1090 for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1091 pil = LIST_NEXT(pil, pil_next)) { 1092 s = splraiseipl(pil->pil_icookie); 1093 val = (*pil->pil_func)(pil->pil_arg); 1094 splx(s); 1095 1096 retval = retval == 1 ? 1 : 1097 retval == 0 ? val : val != 0 ? val : retval; 1098 } 1099 1100 return retval; 1101 } 1102 1103 static void 1104 pci113x_insert(void *arg) 1105 { 1106 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1107 u_int32_t sockevent, sockstate; 1108 1109 if (!(sc->sc_flags & CBB_INSERTING)) { 1110 /* We add a card only under inserting state. */ 1111 return; 1112 } 1113 sc->sc_flags &= ~CBB_INSERTING; 1114 1115 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1116 CB_SOCKET_EVENT); 1117 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1118 CB_SOCKET_STAT); 1119 1120 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1121 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1122 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1123 sc->sc_flags |= CBB_CARDEXIST; 1124 /* call pccard interrupt handler here */ 1125 if (sockstate & CB_SOCKET_STAT_16BIT) { 1126 /* 16-bit card found */ 1127 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1128 cardslot_event_throw(sc->sc_csc, 1129 CARDSLOT_EVENT_INSERTION_16); 1130 } else if (sockstate & CB_SOCKET_STAT_CB) { 1131 /* cardbus card found */ 1132 /* cardbus_attach_card(sc->sc_csc); */ 1133 cardslot_event_throw(sc->sc_csc, 1134 CARDSLOT_EVENT_INSERTION_CB); 1135 } else { 1136 /* who are you? */ 1137 } 1138 } else { 1139 callout_schedule(&sc->sc_insert_ch, hz / 10); 1140 } 1141 } 1142 1143 #define PCCBB_PCMCIA_OFFSET 0x800 1144 static u_int8_t 1145 pccbb_pcmcia_read(struct pcic_handle *ph, int reg) 1146 { 1147 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1148 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1149 1150 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1151 PCCBB_PCMCIA_OFFSET + reg); 1152 } 1153 1154 static void 1155 pccbb_pcmcia_write(struct pcic_handle *ph, int reg, u_int8_t val) 1156 { 1157 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1158 val); 1159 1160 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1161 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1162 } 1163 1164 /* 1165 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1166 */ 1167 STATIC int 1168 pccbb_ctrl(cardbus_chipset_tag_t ct, int command) 1169 { 1170 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1171 1172 switch (command) { 1173 case CARDBUS_CD: 1174 if (2 == pccbb_detect_card(sc)) { 1175 int retval = 0; 1176 int status = cb_detect_voltage(sc); 1177 if (PCCARD_VCC_5V & status) { 1178 retval |= CARDBUS_5V_CARD; 1179 } 1180 if (PCCARD_VCC_3V & status) { 1181 retval |= CARDBUS_3V_CARD; 1182 } 1183 if (PCCARD_VCC_XV & status) { 1184 retval |= CARDBUS_XV_CARD; 1185 } 1186 if (PCCARD_VCC_YV & status) { 1187 retval |= CARDBUS_YV_CARD; 1188 } 1189 return retval; 1190 } else { 1191 return 0; 1192 } 1193 case CARDBUS_RESET: 1194 return cb_reset(sc); 1195 case CARDBUS_IO_ENABLE: /* fallthrough */ 1196 case CARDBUS_IO_DISABLE: /* fallthrough */ 1197 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1198 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1199 case CARDBUS_BM_ENABLE: /* fallthrough */ 1200 case CARDBUS_BM_DISABLE: /* fallthrough */ 1201 /* XXX: I think we don't need to call this function below. */ 1202 return pccbb_cardenable(sc, command); 1203 } 1204 1205 return 0; 1206 } 1207 1208 /* 1209 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1210 * This function returns true when it succeeds and returns false when 1211 * it fails. 1212 */ 1213 STATIC int 1214 pccbb_power(cardbus_chipset_tag_t ct, int command) 1215 { 1216 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1217 u_int32_t status, osock_ctrl, sock_ctrl, reg_ctrl; 1218 bus_space_tag_t memt = sc->sc_base_memt; 1219 bus_space_handle_t memh = sc->sc_base_memh; 1220 int on = 0, pwrcycle, s, times; 1221 struct timeval before, after, diff; 1222 1223 DPRINTF(("pccbb_power: %s and %s [0x%x]\n", 1224 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1225 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1226 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1227 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1228 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1229 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1230 "UNKNOWN", 1231 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1232 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1233 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1234 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1235 "UNKNOWN", command)); 1236 1237 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1238 osock_ctrl = sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1239 1240 switch (command & CARDBUS_VCCMASK) { 1241 case CARDBUS_VCC_UC: 1242 break; 1243 case CARDBUS_VCC_5V: 1244 on++; 1245 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1246 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1247 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1248 } else { 1249 printf("%s: BAD voltage request: no 5 V card\n", 1250 sc->sc_dev.dv_xname); 1251 return 0; 1252 } 1253 break; 1254 case CARDBUS_VCC_3V: 1255 on++; 1256 if (CB_SOCKET_STAT_3VCARD & status) { 1257 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1258 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1259 } else { 1260 printf("%s: BAD voltage request: no 3.3 V card\n", 1261 sc->sc_dev.dv_xname); 1262 return 0; 1263 } 1264 break; 1265 case CARDBUS_VCC_0V: 1266 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1267 break; 1268 default: 1269 return 0; /* power NEVER changed */ 1270 } 1271 1272 switch (command & CARDBUS_VPPMASK) { 1273 case CARDBUS_VPP_UC: 1274 break; 1275 case CARDBUS_VPP_0V: 1276 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1277 break; 1278 case CARDBUS_VPP_VCC: 1279 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1280 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1281 break; 1282 case CARDBUS_VPP_12V: 1283 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1284 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1285 break; 1286 } 1287 1288 pwrcycle = sc->sc_pwrcycle; 1289 aprint_debug("%s: osock_ctrl %#" PRIx32 " sock_ctrl %#" PRIx32 "\n", 1290 device_xname(&sc->sc_dev), osock_ctrl, sock_ctrl); 1291 1292 microtime(&before); 1293 s = splbio(); 1294 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1295 1296 /* 1297 * Wait as long as 200ms for a power-cycle interrupt. If 1298 * interrupts are enabled, but the socket has already 1299 * changed to the desired status, keep waiting for the 1300 * interrupt. "Consuming" the interrupt in this way keeps 1301 * the interrupt from prematurely waking some subsequent 1302 * pccbb_power call. 1303 * 1304 * XXX Not every bridge interrupts on the ->OFF transition. 1305 * XXX That's ok, we will time-out after 200ms. 1306 * 1307 * XXX The power cycle event will never happen when attaching 1308 * XXX a 16-bit card. That's ok, we will time-out after 1309 * XXX 200ms. 1310 */ 1311 for (times = 5; --times >= 0; ) { 1312 if (cold) 1313 DELAY(40 * 1000); 1314 else { 1315 (void)tsleep(&sc->sc_pwrcycle, PWAIT, "pccpwr", 1316 hz / 25); 1317 if (pwrcycle == sc->sc_pwrcycle) 1318 continue; 1319 } 1320 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1321 if ((status & CB_SOCKET_STAT_PWRCYCLE) != 0 && on) 1322 break; 1323 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0 && !on) 1324 break; 1325 } 1326 splx(s); 1327 microtime(&after); 1328 timersub(&after, &before, &diff); 1329 aprint_debug("%s: wait took%s %ld.%06lds\n", sc->sc_dev.dv_xname, 1330 (on && times < 0) ? " too long" : "", diff.tv_sec, diff.tv_usec); 1331 1332 /* 1333 * Ok, wait a bit longer for things to settle. 1334 */ 1335 if (on && sc->sc_chipset == CB_TOPIC95B) 1336 delay_ms(100, sc); 1337 1338 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1339 1340 if (on && sc->sc_chipset != CB_TOPIC95B) { 1341 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0) 1342 printf("%s: power on failed?\n", sc->sc_dev.dv_xname); 1343 } 1344 1345 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1346 printf("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1347 sc->sc_dev.dv_xname, sock_ctrl, status); 1348 printf("%s: disabling socket\n", sc->sc_dev.dv_xname); 1349 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1350 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1351 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1352 status &= ~CB_SOCKET_STAT_BADVCC; 1353 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, status); 1354 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1355 CB_SOCKET_STAT)); 1356 return 0; 1357 } 1358 1359 if (sc->sc_chipset == CB_TOPIC97) { 1360 reg_ctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL); 1361 reg_ctrl &= ~TOPIC97_REG_CTRL_TESTMODE; 1362 if ((command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V) 1363 reg_ctrl &= ~TOPIC97_REG_CTRL_CLKRUN_ENA; 1364 else 1365 reg_ctrl |= TOPIC97_REG_CTRL_CLKRUN_ENA; 1366 pci_conf_write(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL, reg_ctrl); 1367 } 1368 1369 return 1; /* power changed correctly */ 1370 } 1371 1372 #if defined CB_PCMCIA_POLL 1373 struct cb_poll_str { 1374 void *arg; 1375 int (*func)(void *); 1376 int level; 1377 pccard_chipset_tag_t ct; 1378 int count; 1379 struct callout poll_ch; 1380 }; 1381 1382 static struct cb_poll_str cb_poll[10]; 1383 static int cb_poll_n = 0; 1384 1385 static void cb_pcmcia_poll(void *arg); 1386 1387 static void 1388 cb_pcmcia_poll(void *arg) 1389 { 1390 struct cb_poll_str *poll = arg; 1391 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1392 struct pccbb_softc *sc = psc->cpc_parent; 1393 int s; 1394 u_int32_t spsr; /* socket present-state reg */ 1395 1396 callout_reset(&poll->poll_ch, hz / 10, cb_pcmcia_poll, poll); 1397 switch (poll->level) { 1398 case IPL_NET: 1399 s = splnet(); 1400 break; 1401 case IPL_BIO: 1402 s = splbio(); 1403 break; 1404 case IPL_TTY: /* fallthrough */ 1405 default: 1406 s = spltty(); 1407 break; 1408 } 1409 1410 spsr = 1411 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1412 CB_SOCKET_STAT); 1413 1414 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1415 if (!(spsr & 0x40)) { /* CINT low */ 1416 #else 1417 if (1) { 1418 #endif 1419 if ((*poll->func) (poll->arg) == 1) { 1420 ++poll->count; 1421 printf("intr: reported from poller, 0x%x\n", spsr); 1422 #if defined LEVEL2 1423 } else { 1424 printf("intr: miss! 0x%x\n", spsr); 1425 #endif 1426 } 1427 } 1428 splx(s); 1429 } 1430 #endif /* defined CB_PCMCIA_POLL */ 1431 1432 /* 1433 * static int pccbb_detect_card(struct pccbb_softc *sc) 1434 * return value: 0 if no card exists. 1435 * 1 if 16-bit card exists. 1436 * 2 if cardbus card exists. 1437 */ 1438 static int 1439 pccbb_detect_card(struct pccbb_softc *sc) 1440 { 1441 bus_space_handle_t base_memh = sc->sc_base_memh; 1442 bus_space_tag_t base_memt = sc->sc_base_memt; 1443 u_int32_t sockstat = 1444 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1445 int retval = 0; 1446 1447 /* CD1 and CD2 asserted */ 1448 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1449 /* card must be present */ 1450 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1451 /* NOTACARD DEASSERTED */ 1452 if (CB_SOCKET_STAT_CB & sockstat) { 1453 /* CardBus mode */ 1454 retval = 2; 1455 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1456 /* 16-bit mode */ 1457 retval = 1; 1458 } 1459 } 1460 } 1461 return retval; 1462 } 1463 1464 /* 1465 * STATIC int cb_reset(struct pccbb_softc *sc) 1466 * This function resets CardBus card. 1467 */ 1468 STATIC int 1469 cb_reset(struct pccbb_softc *sc) 1470 { 1471 /* 1472 * Reset Assert at least 20 ms 1473 * Some machines request longer duration. 1474 */ 1475 int reset_duration = 1476 (sc->sc_chipset == CB_RX5C47X ? 400 : 50); 1477 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1478 1479 /* Reset bit Assert (bit 6 at 0x3E) */ 1480 bcr |= CB_BCR_RESET_ENABLE; 1481 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr); 1482 delay_ms(reset_duration, sc); 1483 1484 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1485 /* Reset bit Deassert (bit 6 at 0x3E) */ 1486 bcr &= ~CB_BCR_RESET_ENABLE; 1487 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr); 1488 delay_ms(reset_duration, sc); 1489 } 1490 /* No card found on the slot. Keep Reset. */ 1491 return 1; 1492 } 1493 1494 /* 1495 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1496 * This function detect card Voltage. 1497 */ 1498 STATIC int 1499 cb_detect_voltage(struct pccbb_softc *sc) 1500 { 1501 u_int32_t psr; /* socket present-state reg */ 1502 bus_space_tag_t iot = sc->sc_base_memt; 1503 bus_space_handle_t ioh = sc->sc_base_memh; 1504 int vol = PCCARD_VCC_UKN; /* set 0 */ 1505 1506 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1507 1508 if (0x400u & psr) { 1509 vol |= PCCARD_VCC_5V; 1510 } 1511 if (0x800u & psr) { 1512 vol |= PCCARD_VCC_3V; 1513 } 1514 1515 return vol; 1516 } 1517 1518 STATIC int 1519 cbbprint(void *aux, const char *pcic) 1520 { 1521 #if 0 1522 struct cbslot_attach_args *cba = aux; 1523 1524 if (cba->cba_slot >= 0) { 1525 aprint_normal(" slot %d", cba->cba_slot); 1526 } 1527 #endif 1528 return UNCONF; 1529 } 1530 1531 /* 1532 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1533 * This function enables and disables the card 1534 */ 1535 STATIC int 1536 pccbb_cardenable(struct pccbb_softc *sc, int function) 1537 { 1538 u_int32_t command = 1539 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1540 1541 DPRINTF(("pccbb_cardenable:")); 1542 switch (function) { 1543 case CARDBUS_IO_ENABLE: 1544 command |= PCI_COMMAND_IO_ENABLE; 1545 break; 1546 case CARDBUS_IO_DISABLE: 1547 command &= ~PCI_COMMAND_IO_ENABLE; 1548 break; 1549 case CARDBUS_MEM_ENABLE: 1550 command |= PCI_COMMAND_MEM_ENABLE; 1551 break; 1552 case CARDBUS_MEM_DISABLE: 1553 command &= ~PCI_COMMAND_MEM_ENABLE; 1554 break; 1555 case CARDBUS_BM_ENABLE: 1556 command |= PCI_COMMAND_MASTER_ENABLE; 1557 break; 1558 case CARDBUS_BM_DISABLE: 1559 command &= ~PCI_COMMAND_MASTER_ENABLE; 1560 break; 1561 default: 1562 return 0; 1563 } 1564 1565 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1566 DPRINTF((" command reg 0x%x\n", command)); 1567 return 1; 1568 } 1569 1570 #if !rbus 1571 static int 1572 pccbb_io_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 1573 { 1574 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1575 int basereg; 1576 int limitreg; 1577 1578 if ((win < 0) || (win > 2)) { 1579 #if defined DIAGNOSTIC 1580 printf("cardbus_io_open: window out of range %d\n", win); 1581 #endif 1582 return 0; 1583 } 1584 1585 basereg = win * 8 + 0x2c; 1586 limitreg = win * 8 + 0x30; 1587 1588 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1589 start, basereg, end, limitreg)); 1590 1591 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1592 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1593 return 1; 1594 } 1595 1596 /* 1597 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1598 */ 1599 static int 1600 pccbb_io_close(cardbus_chipset_tag_t ct, int win) 1601 { 1602 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1603 int basereg; 1604 int limitreg; 1605 1606 if ((win < 0) || (win > 2)) { 1607 #if defined DIAGNOSTIC 1608 printf("cardbus_io_close: window out of range %d\n", win); 1609 #endif 1610 return 0; 1611 } 1612 1613 basereg = win * 8 + 0x2c; 1614 limitreg = win * 8 + 0x30; 1615 1616 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1617 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1618 return 1; 1619 } 1620 1621 static int 1622 pccbb_mem_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 1623 { 1624 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1625 int basereg; 1626 int limitreg; 1627 1628 if ((win < 0) || (win > 2)) { 1629 #if defined DIAGNOSTIC 1630 printf("cardbus_mem_open: window out of range %d\n", win); 1631 #endif 1632 return 0; 1633 } 1634 1635 basereg = win * 8 + 0x1c; 1636 limitreg = win * 8 + 0x20; 1637 1638 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1639 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1640 return 1; 1641 } 1642 1643 static int 1644 pccbb_mem_close(cardbus_chipset_tag_t ct, int win) 1645 { 1646 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1647 int basereg; 1648 int limitreg; 1649 1650 if ((win < 0) || (win > 2)) { 1651 #if defined DIAGNOSTIC 1652 printf("cardbus_mem_close: window out of range %d\n", win); 1653 #endif 1654 return 0; 1655 } 1656 1657 basereg = win * 8 + 0x1c; 1658 limitreg = win * 8 + 0x20; 1659 1660 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1661 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1662 return 1; 1663 } 1664 #endif 1665 1666 /* 1667 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1668 * int irq, 1669 * int level, 1670 * int (* func)(void *), 1671 * void *arg) 1672 * 1673 * This function registers an interrupt handler at the bridge, in 1674 * order not to call the interrupt handlers of child devices when 1675 * a card-deletion interrupt occurs. 1676 * 1677 * The arguments irq and level are not used. 1678 */ 1679 static void * 1680 pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, int irq, int level, 1681 int (*func)(void *), void *arg) 1682 { 1683 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1684 1685 return pccbb_intr_establish(sc, irq, level, func, arg); 1686 } 1687 1688 1689 /* 1690 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1691 * void *ih) 1692 * 1693 * This function removes an interrupt handler pointed by ih. 1694 */ 1695 static void 1696 pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih) 1697 { 1698 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1699 1700 pccbb_intr_disestablish(sc, ih); 1701 } 1702 1703 1704 void 1705 pccbb_intr_route(struct pccbb_softc *sc) 1706 { 1707 pcireg_t bcr, cbctrl; 1708 1709 /* initialize bridge intr routing */ 1710 bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1711 bcr &= ~CB_BCR_INTR_IREQ_ENABLE; 1712 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr); 1713 1714 switch (sc->sc_chipset) { 1715 case CB_TI113X: 1716 cbctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1717 /* functional intr enabled */ 1718 cbctrl |= PCI113X_CBCTRL_PCI_INTR; 1719 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, cbctrl); 1720 break; 1721 default: 1722 break; 1723 } 1724 } 1725 1726 /* 1727 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1728 * int irq, 1729 * int level, 1730 * int (* func)(void *), 1731 * void *arg) 1732 * 1733 * This function registers an interrupt handler at the bridge, in 1734 * order not to call the interrupt handlers of child devices when 1735 * a card-deletion interrupt occurs. 1736 * 1737 * The arguments irq is not used because pccbb selects intr vector. 1738 */ 1739 static void * 1740 pccbb_intr_establish(struct pccbb_softc *sc, int irq, int level, 1741 int (*func)(void *), void *arg) 1742 { 1743 struct pccbb_intrhand_list *pil, *newpil; 1744 1745 DPRINTF(("pccbb_intr_establish start. %p\n", LIST_FIRST(&sc->sc_pil))); 1746 1747 if (LIST_EMPTY(&sc->sc_pil)) { 1748 pccbb_intr_route(sc); 1749 } 1750 1751 /* 1752 * Allocate a room for interrupt handler structure. 1753 */ 1754 if (NULL == (newpil = 1755 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1756 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1757 return NULL; 1758 } 1759 1760 newpil->pil_func = func; 1761 newpil->pil_arg = arg; 1762 newpil->pil_icookie = makeiplcookie(level); 1763 1764 if (LIST_EMPTY(&sc->sc_pil)) { 1765 LIST_INSERT_HEAD(&sc->sc_pil, newpil, pil_next); 1766 } else { 1767 for (pil = LIST_FIRST(&sc->sc_pil); 1768 LIST_NEXT(pil, pil_next) != NULL; 1769 pil = LIST_NEXT(pil, pil_next)); 1770 LIST_INSERT_AFTER(pil, newpil, pil_next); 1771 } 1772 1773 DPRINTF(("pccbb_intr_establish add pil. %p\n", 1774 LIST_FIRST(&sc->sc_pil))); 1775 1776 return newpil; 1777 } 1778 1779 /* 1780 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1781 * void *ih) 1782 * 1783 * This function removes an interrupt handler pointed by ih. ih 1784 * should be the value returned by cardbus_intr_establish() or 1785 * NULL. 1786 * 1787 * When ih is NULL, this function will do nothing. 1788 */ 1789 static void 1790 pccbb_intr_disestablish(struct pccbb_softc *sc, void *ih) 1791 { 1792 struct pccbb_intrhand_list *pil; 1793 pcireg_t reg; 1794 1795 DPRINTF(("pccbb_intr_disestablish start. %p\n", 1796 LIST_FIRST(&sc->sc_pil))); 1797 1798 if (ih == NULL) { 1799 /* intr handler is not set */ 1800 DPRINTF(("pccbb_intr_disestablish: no ih\n")); 1801 return; 1802 } 1803 1804 #ifdef DIAGNOSTIC 1805 for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1806 pil = LIST_NEXT(pil, pil_next)) { 1807 DPRINTF(("pccbb_intr_disestablish: pil %p\n", pil)); 1808 if (pil == ih) { 1809 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1810 break; 1811 } 1812 } 1813 if (pil == NULL) { 1814 panic("pccbb_intr_disestablish: %s cannot find pil %p", 1815 sc->sc_dev.dv_xname, ih); 1816 } 1817 #endif 1818 1819 pil = (struct pccbb_intrhand_list *)ih; 1820 LIST_REMOVE(pil, pil_next); 1821 free(pil, M_DEVBUF); 1822 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1823 1824 if (LIST_EMPTY(&sc->sc_pil)) { 1825 /* No interrupt handlers */ 1826 1827 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1828 1829 /* stop routing PCI intr */ 1830 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1831 reg |= CB_BCR_INTR_IREQ_ENABLE; 1832 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, reg); 1833 1834 switch (sc->sc_chipset) { 1835 case CB_TI113X: 1836 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1837 /* functional intr disabled */ 1838 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1839 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1840 break; 1841 default: 1842 break; 1843 } 1844 } 1845 } 1846 1847 #if defined SHOW_REGS 1848 static void 1849 cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, bus_space_tag_t memt, 1850 bus_space_handle_t memh) 1851 { 1852 int i; 1853 printf("PCI config regs:"); 1854 for (i = 0; i < 0x50; i += 4) { 1855 if (i % 16 == 0) 1856 printf("\n 0x%02x:", i); 1857 printf(" %08x", pci_conf_read(pc, tag, i)); 1858 } 1859 for (i = 0x80; i < 0xb0; i += 4) { 1860 if (i % 16 == 0) 1861 printf("\n 0x%02x:", i); 1862 printf(" %08x", pci_conf_read(pc, tag, i)); 1863 } 1864 1865 if (memh == 0) { 1866 printf("\n"); 1867 return; 1868 } 1869 1870 printf("\nsocket regs:"); 1871 for (i = 0; i <= 0x10; i += 0x04) 1872 printf(" %08x", bus_space_read_4(memt, memh, i)); 1873 printf("\nExCA regs:"); 1874 for (i = 0; i < 0x08; ++i) 1875 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1876 printf("\n"); 1877 return; 1878 } 1879 #endif 1880 1881 /* 1882 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1883 * int busno, int function) 1884 * This is the function to make a tag to access config space of 1885 * a CardBus Card. It works same as pci_conf_read. 1886 */ 1887 static cardbustag_t 1888 pccbb_make_tag(cardbus_chipset_tag_t cc, int busno, int function) 1889 { 1890 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1891 1892 return pci_make_tag(sc->sc_pc, busno, 0, function); 1893 } 1894 1895 static void 1896 pccbb_free_tag(cardbus_chipset_tag_t cc, cardbustag_t tag) 1897 { 1898 } 1899 1900 /* 1901 * pccbb_conf_read 1902 * 1903 * This is the function to read the config space of a CardBus card. 1904 * It works the same as pci_conf_read(9). 1905 */ 1906 static cardbusreg_t 1907 pccbb_conf_read(cardbus_chipset_tag_t cc, cardbustag_t tag, int offset) 1908 { 1909 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1910 1911 return pci_conf_read(sc->sc_pc, tag, offset); 1912 } 1913 1914 /* 1915 * pccbb_conf_write 1916 * 1917 * This is the function to write the config space of a CardBus 1918 * card. It works the same as pci_conf_write(9). 1919 */ 1920 static void 1921 pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, int reg, 1922 cardbusreg_t val) 1923 { 1924 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1925 1926 pci_conf_write(sc->sc_pc, tag, reg, val); 1927 } 1928 1929 #if 0 1930 STATIC int 1931 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1932 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 1933 int speed, int flags, 1934 bus_space_handle_t * iohp) 1935 #endif 1936 /* 1937 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1938 * bus_addr_t start, bus_size_t size, 1939 * bus_size_t align, 1940 * struct pcmcia_io_handle *pcihp 1941 * 1942 * This function only allocates I/O region for pccard. This function 1943 * never maps the allocated region to pccard I/O area. 1944 * 1945 * XXX: The interface of this function is not very good, I believe. 1946 */ 1947 STATIC int 1948 pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, 1949 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 1950 { 1951 struct pcic_handle *ph = (struct pcic_handle *)pch; 1952 bus_addr_t ioaddr; 1953 int flags = 0; 1954 bus_space_tag_t iot; 1955 bus_space_handle_t ioh; 1956 bus_addr_t mask; 1957 #if rbus 1958 rbus_tag_t rb; 1959 #endif 1960 if (align == 0) { 1961 align = size; /* XXX: funny??? */ 1962 } 1963 1964 if (start != 0) { 1965 /* XXX: assume all card decode lower 10 bits by its hardware */ 1966 mask = 0x3ff; 1967 /* enforce to use only masked address */ 1968 start &= mask; 1969 } else { 1970 /* 1971 * calculate mask: 1972 * 1. get the most significant bit of size (call it msb). 1973 * 2. compare msb with the value of size. 1974 * 3. if size is larger, shift msb left once. 1975 * 4. obtain mask value to decrement msb. 1976 */ 1977 bus_size_t size_tmp = size; 1978 int shifts = 0; 1979 1980 mask = 1; 1981 while (size_tmp) { 1982 ++shifts; 1983 size_tmp >>= 1; 1984 } 1985 mask = (1 << shifts); 1986 if (mask < size) { 1987 mask <<= 1; 1988 } 1989 --mask; 1990 } 1991 1992 /* 1993 * Allocate some arbitrary I/O space. 1994 */ 1995 1996 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 1997 1998 #if rbus 1999 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 2000 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 2001 return 1; 2002 } 2003 DPRINTF(("pccbb_pcmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2004 (u_long) ioaddr, (u_long) size)); 2005 #else 2006 if (start) { 2007 ioaddr = start; 2008 if (bus_space_map(iot, start, size, 0, &ioh)) { 2009 return 1; 2010 } 2011 DPRINTF(("pccbb_pcmcia_io_alloc map port 0x%lx+0x%lx\n", 2012 (u_long) ioaddr, (u_long) size)); 2013 } else { 2014 flags |= PCMCIA_IO_ALLOCATED; 2015 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 2016 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 2017 size, align, 0, 0, &ioaddr, &ioh)) { 2018 /* No room be able to be get. */ 2019 return 1; 2020 } 2021 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2022 (u_long) ioaddr, (u_long) size)); 2023 } 2024 #endif 2025 2026 pcihp->iot = iot; 2027 pcihp->ioh = ioh; 2028 pcihp->addr = ioaddr; 2029 pcihp->size = size; 2030 pcihp->flags = flags; 2031 2032 return 0; 2033 } 2034 2035 /* 2036 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2037 * struct pcmcia_io_handle *pcihp) 2038 * 2039 * This function only frees I/O region for pccard. 2040 * 2041 * XXX: The interface of this function is not very good, I believe. 2042 */ 2043 void 2044 pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2045 struct pcmcia_io_handle *pcihp) 2046 { 2047 #if !rbus 2048 bus_space_tag_t iot = pcihp->iot; 2049 #endif 2050 bus_space_handle_t ioh = pcihp->ioh; 2051 bus_size_t size = pcihp->size; 2052 2053 #if rbus 2054 struct pccbb_softc *sc = 2055 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 2056 rbus_tag_t rb = sc->sc_rbus_iot; 2057 2058 rbus_space_free(rb, ioh, size, NULL); 2059 #else 2060 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 2061 bus_space_free(iot, ioh, size); 2062 else 2063 bus_space_unmap(iot, ioh, size); 2064 #endif 2065 } 2066 2067 /* 2068 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 2069 * bus_addr_t offset, bus_size_t size, 2070 * struct pcmcia_io_handle *pcihp, 2071 * int *windowp) 2072 * 2073 * This function maps the allocated I/O region to pccard. This function 2074 * never allocates any I/O region for pccard I/O area. I don't 2075 * understand why the original authors of pcmciabus separated alloc and 2076 * map. I believe the two must be unite. 2077 * 2078 * XXX: no wait timing control? 2079 */ 2080 int 2081 pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, bus_addr_t offset, 2082 bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp) 2083 { 2084 struct pcic_handle *ph = (struct pcic_handle *)pch; 2085 bus_addr_t ioaddr = pcihp->addr + offset; 2086 int i, win; 2087 #if defined CBB_DEBUG 2088 static const char *width_names[] = { "dynamic", "io8", "io16" }; 2089 #endif 2090 2091 /* Sanity check I/O handle. */ 2092 2093 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 2094 panic("pccbb_pcmcia_io_map iot is bogus"); 2095 } 2096 2097 /* XXX Sanity check offset/size. */ 2098 2099 win = -1; 2100 for (i = 0; i < PCIC_IO_WINS; i++) { 2101 if ((ph->ioalloc & (1 << i)) == 0) { 2102 win = i; 2103 ph->ioalloc |= (1 << i); 2104 break; 2105 } 2106 } 2107 2108 if (win == -1) { 2109 return 1; 2110 } 2111 2112 *windowp = win; 2113 2114 /* XXX this is pretty gross */ 2115 2116 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2117 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2118 2119 /* XXX wtf is this doing here? */ 2120 2121 #if 0 2122 printf(" port 0x%lx", (u_long) ioaddr); 2123 if (size > 1) { 2124 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2125 } 2126 #endif 2127 2128 ph->io[win].addr = ioaddr; 2129 ph->io[win].size = size; 2130 ph->io[win].width = width; 2131 2132 /* actual dirty register-value changing in the function below. */ 2133 pccbb_pcmcia_do_io_map(ph, win); 2134 2135 return 0; 2136 } 2137 2138 /* 2139 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2140 * 2141 * This function changes register-value to map I/O region for pccard. 2142 */ 2143 static void 2144 pccbb_pcmcia_do_io_map(struct pcic_handle *ph, int win) 2145 { 2146 static u_int8_t pcic_iowidth[3] = { 2147 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2148 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2149 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2150 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2151 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2152 }; 2153 2154 #define PCIC_SIA_START_LOW 0 2155 #define PCIC_SIA_START_HIGH 1 2156 #define PCIC_SIA_STOP_LOW 2 2157 #define PCIC_SIA_STOP_HIGH 3 2158 2159 int regbase_win = 0x8 + win * 0x04; 2160 u_int8_t ioctl, enable; 2161 2162 DPRINTF(("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx " 2163 "width %d\n", win, (unsigned long)ph->io[win].addr, 2164 (unsigned long)ph->io[win].size, ph->io[win].width * 8)); 2165 2166 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2167 ph->io[win].addr & 0xff); 2168 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2169 (ph->io[win].addr >> 8) & 0xff); 2170 2171 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2172 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2173 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2174 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2175 2176 ioctl = Pcic_read(ph, PCIC_IOCTL); 2177 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2178 switch (win) { 2179 case 0: 2180 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2181 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2182 PCIC_IOCTL_IO0_DATASIZE_MASK); 2183 ioctl |= pcic_iowidth[ph->io[win].width]; 2184 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2185 break; 2186 case 1: 2187 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2188 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2189 PCIC_IOCTL_IO1_DATASIZE_MASK); 2190 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2191 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2192 break; 2193 } 2194 Pcic_write(ph, PCIC_IOCTL, ioctl); 2195 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2196 #if defined(CBB_DEBUG) 2197 { 2198 u_int8_t start_low = 2199 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2200 u_int8_t start_high = 2201 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2202 u_int8_t stop_low = 2203 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2204 u_int8_t stop_high = 2205 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2206 printf("pccbb_pcmcia_do_io_map start %02x %02x, " 2207 "stop %02x %02x, ioctl %02x enable %02x\n", 2208 start_low, start_high, stop_low, stop_high, ioctl, enable); 2209 } 2210 #endif 2211 } 2212 2213 /* 2214 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2215 * 2216 * This function unmaps I/O region. No return value. 2217 */ 2218 STATIC void 2219 pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t pch, int win) 2220 { 2221 struct pcic_handle *ph = (struct pcic_handle *)pch; 2222 int reg; 2223 2224 if (win >= PCIC_IO_WINS || win < 0) { 2225 panic("pccbb_pcmcia_io_unmap: window out of range"); 2226 } 2227 2228 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2229 switch (win) { 2230 case 0: 2231 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2232 break; 2233 case 1: 2234 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2235 break; 2236 } 2237 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2238 2239 ph->ioalloc &= ~(1 << win); 2240 } 2241 2242 static int 2243 pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 2244 { 2245 u_int8_t stat; 2246 int i; 2247 2248 /* wait an initial 10ms for quick cards */ 2249 stat = Pcic_read(ph, PCIC_IF_STATUS); 2250 if (stat & PCIC_IF_STATUS_READY) 2251 return (0); 2252 pccbb_pcmcia_delay(ph, 10, "pccwr0"); 2253 for (i = 0; i < 50; i++) { 2254 stat = Pcic_read(ph, PCIC_IF_STATUS); 2255 if (stat & PCIC_IF_STATUS_READY) 2256 return (0); 2257 if ((stat & PCIC_IF_STATUS_CARDDETECT_MASK) != 2258 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2259 return (ENXIO); 2260 /* wait .1s (100ms) each iteration now */ 2261 pccbb_pcmcia_delay(ph, 100, "pccwr1"); 2262 } 2263 2264 printf("pccbb_pcmcia_wait_ready: ready never happened, status=%02x\n", stat); 2265 return (EWOULDBLOCK); 2266 } 2267 2268 /* 2269 * Perform long (msec order) delay. timo is in milliseconds. 2270 */ 2271 static void 2272 pccbb_pcmcia_delay(struct pcic_handle *ph, int timo, const char *wmesg) 2273 { 2274 #ifdef DIAGNOSTIC 2275 if (timo <= 0) 2276 panic("pccbb_pcmcia_delay: called with timeout %d", timo); 2277 if (!curlwp) 2278 panic("pccbb_pcmcia_delay: called in interrupt context"); 2279 #if 0 2280 if (!ph->event_thread) 2281 panic("pccbb_pcmcia_delay: no event thread"); 2282 #endif 2283 #endif 2284 DPRINTF(("pccbb_pcmcia_delay: \"%s\" %p, sleep %d ms\n", 2285 wmesg, ph->event_thread, timo)); 2286 tsleep(pccbb_pcmcia_delay, PWAIT, wmesg, roundup(timo * hz, 1000) / 1000); 2287 } 2288 2289 /* 2290 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2291 * 2292 * This function enables the card. All information is stored in 2293 * the first argument, pcmcia_chipset_handle_t. 2294 */ 2295 STATIC void 2296 pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2297 { 2298 struct pcic_handle *ph = (struct pcic_handle *)pch; 2299 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2300 pcireg_t spsr; 2301 int voltage; 2302 int win; 2303 u_int8_t power, intr; 2304 #ifdef DIAGNOSTIC 2305 int reg; 2306 #endif 2307 2308 /* this bit is mostly stolen from pcic_attach_card */ 2309 2310 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2311 2312 /* get card Vcc info */ 2313 spsr = 2314 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2315 CB_SOCKET_STAT); 2316 if (spsr & CB_SOCKET_STAT_5VCARD) { 2317 DPRINTF(("5V card\n")); 2318 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2319 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2320 DPRINTF(("3V card\n")); 2321 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2322 } else { 2323 DPRINTF(("?V card, 0x%x\n", spsr)); /* XXX */ 2324 return; 2325 } 2326 2327 /* disable interrupts; assert RESET */ 2328 intr = Pcic_read(ph, PCIC_INTR); 2329 intr &= PCIC_INTR_ENABLE; 2330 Pcic_write(ph, PCIC_INTR, intr); 2331 2332 /* zero out the address windows */ 2333 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2334 2335 /* power down the socket to reset it, clear the card reset pin */ 2336 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2337 2338 /* power off; assert output enable bit */ 2339 power = PCIC_PWRCTL_OE; 2340 Pcic_write(ph, PCIC_PWRCTL, power); 2341 2342 /* power up the socket */ 2343 if (pccbb_power(sc, voltage) == 0) 2344 return; 2345 2346 /* 2347 * Table 4-18 and figure 4-6 of the PC Card specifiction say: 2348 * Vcc Rising Time (Tpr) = 100ms (handled in pccbb_power() above) 2349 * RESET Width (Th (Hi-z RESET)) = 1ms 2350 * RESET Width (Tw (RESET)) = 10us 2351 * 2352 * some machines require some more time to be settled 2353 * for example old toshiba topic bridges! 2354 * (100ms is added here). 2355 */ 2356 pccbb_pcmcia_delay(ph, 200 + 1, "pccen1"); 2357 2358 /* negate RESET */ 2359 intr |= PCIC_INTR_RESET; 2360 Pcic_write(ph, PCIC_INTR, intr); 2361 2362 /* 2363 * RESET Setup Time (Tsu (RESET)) = 20ms 2364 */ 2365 pccbb_pcmcia_delay(ph, 20, "pccen2"); 2366 2367 #ifdef DIAGNOSTIC 2368 reg = Pcic_read(ph, PCIC_IF_STATUS); 2369 if ((reg & PCIC_IF_STATUS_POWERACTIVE) == 0) 2370 printf("pccbb_pcmcia_socket_enable: no power, status=%x\n", reg); 2371 #endif 2372 2373 /* wait for the chip to finish initializing */ 2374 if (pccbb_pcmcia_wait_ready(ph)) { 2375 #ifdef DIAGNOSTIC 2376 printf("pccbb_pcmcia_socket_enable: never became ready\n"); 2377 #endif 2378 /* XXX return a failure status?? */ 2379 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2380 Pcic_write(ph, PCIC_PWRCTL, 0); 2381 return; 2382 } 2383 2384 /* reinstall all the memory and io mappings */ 2385 for (win = 0; win < PCIC_MEM_WINS; ++win) 2386 if (ph->memalloc & (1 << win)) 2387 pccbb_pcmcia_do_mem_map(ph, win); 2388 for (win = 0; win < PCIC_IO_WINS; ++win) 2389 if (ph->ioalloc & (1 << win)) 2390 pccbb_pcmcia_do_io_map(ph, win); 2391 } 2392 2393 /* 2394 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2395 * 2396 * This function disables the card. All information is stored in 2397 * the first argument, pcmcia_chipset_handle_t. 2398 */ 2399 STATIC void 2400 pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t pch) 2401 { 2402 struct pcic_handle *ph = (struct pcic_handle *)pch; 2403 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2404 u_int8_t intr; 2405 2406 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2407 2408 /* disable interrupts; assert RESET */ 2409 intr = Pcic_read(ph, PCIC_INTR); 2410 intr &= PCIC_INTR_ENABLE; 2411 Pcic_write(ph, PCIC_INTR, intr); 2412 2413 /* zero out the address windows */ 2414 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2415 2416 /* power down the socket to reset it, clear the card reset pin */ 2417 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2418 2419 /* disable socket: negate output enable bit and power off */ 2420 Pcic_write(ph, PCIC_PWRCTL, 0); 2421 2422 /* 2423 * Vcc Falling Time (Tpf) = 300ms 2424 */ 2425 pccbb_pcmcia_delay(ph, 300, "pccwr1"); 2426 } 2427 2428 STATIC void 2429 pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t pch, int type) 2430 { 2431 struct pcic_handle *ph = (struct pcic_handle *)pch; 2432 u_int8_t intr; 2433 2434 /* set the card type */ 2435 2436 intr = Pcic_read(ph, PCIC_INTR); 2437 intr &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_CARDTYPE_MASK); 2438 if (type == PCMCIA_IFTYPE_IO) 2439 intr |= PCIC_INTR_CARDTYPE_IO; 2440 else 2441 intr |= PCIC_INTR_CARDTYPE_MEM; 2442 Pcic_write(ph, PCIC_INTR, intr); 2443 2444 DPRINTF(("%s: pccbb_pcmcia_socket_settype %02x type %s %02x\n", 2445 ph->ph_parent->dv_xname, ph->sock, 2446 ((type == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2447 } 2448 2449 /* 2450 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2451 * 2452 * This function detects whether a card is in the slot or not. 2453 * If a card is inserted, return 1. Otherwise, return 0. 2454 */ 2455 STATIC int 2456 pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch) 2457 { 2458 struct pcic_handle *ph = (struct pcic_handle *)pch; 2459 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2460 2461 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2462 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2463 } 2464 2465 #if 0 2466 STATIC int 2467 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2468 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2469 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2470 #endif 2471 /* 2472 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2473 * bus_size_t size, 2474 * struct pcmcia_mem_handle *pcmhp) 2475 * 2476 * This function only allocates memory region for pccard. This 2477 * function never maps the allocated region to pccard memory area. 2478 * 2479 * XXX: Why the argument of start address is not in? 2480 */ 2481 STATIC int 2482 pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 2483 struct pcmcia_mem_handle *pcmhp) 2484 { 2485 struct pcic_handle *ph = (struct pcic_handle *)pch; 2486 bus_space_handle_t memh; 2487 bus_addr_t addr; 2488 bus_size_t sizepg; 2489 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2490 #if rbus 2491 rbus_tag_t rb; 2492 #endif 2493 2494 /* Check that the card is still there. */ 2495 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2496 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2497 return 1; 2498 2499 /* out of sc->memh, allocate as many pages as necessary */ 2500 2501 /* convert size to PCIC pages */ 2502 /* 2503 * This is not enough; when the requested region is on the page 2504 * boundaries, this may calculate wrong result. 2505 */ 2506 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2507 #if 0 2508 if (sizepg > PCIC_MAX_MEM_PAGES) { 2509 return 1; 2510 } 2511 #endif 2512 2513 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2514 return 1; 2515 } 2516 2517 addr = 0; /* XXX gcc -Wuninitialized */ 2518 2519 #if rbus 2520 rb = sc->sc_rbus_memt; 2521 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2522 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2523 &addr, &memh)) { 2524 return 1; 2525 } 2526 #else 2527 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2528 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2529 0, /* boundary */ 2530 0, /* flags */ 2531 &addr, &memh)) { 2532 return 1; 2533 } 2534 #endif 2535 2536 DPRINTF(("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, " 2537 "realsize 0x%lx\n", (unsigned long)addr, (unsigned long)size, 2538 (unsigned long)sizepg * PCIC_MEM_PAGESIZE)); 2539 2540 pcmhp->memt = sc->sc_memt; 2541 pcmhp->memh = memh; 2542 pcmhp->addr = addr; 2543 pcmhp->size = size; 2544 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2545 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2546 pcmhp->mhandle = 0; 2547 /* No offset??? Funny. */ 2548 2549 return 0; 2550 } 2551 2552 /* 2553 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2554 * struct pcmcia_mem_handle *pcmhp) 2555 * 2556 * This function release the memory space allocated by the function 2557 * pccbb_pcmcia_mem_alloc(). 2558 */ 2559 STATIC void 2560 pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2561 struct pcmcia_mem_handle *pcmhp) 2562 { 2563 #if rbus 2564 struct pcic_handle *ph = (struct pcic_handle *)pch; 2565 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2566 2567 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2568 #else 2569 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2570 #endif 2571 } 2572 2573 /* 2574 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2575 * 2576 * This function release the memory space allocated by the function 2577 * pccbb_pcmcia_mem_alloc(). 2578 */ 2579 STATIC void 2580 pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2581 { 2582 int regbase_win; 2583 bus_addr_t phys_addr; 2584 bus_addr_t phys_end; 2585 2586 #define PCIC_SMM_START_LOW 0 2587 #define PCIC_SMM_START_HIGH 1 2588 #define PCIC_SMM_STOP_LOW 2 2589 #define PCIC_SMM_STOP_HIGH 3 2590 #define PCIC_CMA_LOW 4 2591 #define PCIC_CMA_HIGH 5 2592 2593 u_int8_t start_low, start_high = 0; 2594 u_int8_t stop_low, stop_high; 2595 u_int8_t off_low, off_high; 2596 u_int8_t mem_window; 2597 int reg; 2598 2599 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2600 int mem8 = 2601 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2602 || (kind == PCMCIA_MEM_ATTR); 2603 2604 regbase_win = 0x10 + win * 0x08; 2605 2606 phys_addr = ph->mem[win].addr; 2607 phys_end = phys_addr + ph->mem[win].size; 2608 2609 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2610 (unsigned long)phys_addr, (unsigned long)phys_end, 2611 (unsigned long)ph->mem[win].offset)); 2612 2613 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2614 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2615 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2616 2617 /* bit 19:12 */ 2618 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2619 /* bit 23:20 and bit 7 on */ 2620 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2621 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2622 /* bit 31:24, for 32-bit address */ 2623 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2624 2625 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2626 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2627 2628 if (((struct pccbb_softc *)ph-> 2629 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2630 Pcic_write(ph, 0x40 + win, mem_window); 2631 } 2632 2633 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2634 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2635 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2636 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2637 2638 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2639 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2640 2641 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2642 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2643 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2644 | ((kind == PCMCIA_MEM_ATTR) ? 2645 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2646 2647 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2648 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2649 2650 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2651 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2652 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2653 2654 #if defined(CBB_DEBUG) 2655 { 2656 int r1, r2, r3, r4, r5, r6, r7 = 0; 2657 2658 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2659 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2660 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2661 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2662 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2663 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2664 if (((struct pccbb_softc *)(ph-> 2665 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2666 r7 = Pcic_read(ph, 0x40 + win); 2667 } 2668 2669 printf("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2670 "%02x%02x", win, r1, r2, r3, r4, r5, r6); 2671 if (((struct pccbb_softc *)(ph-> 2672 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2673 printf(" %02x", r7); 2674 } 2675 printf("\n"); 2676 } 2677 #endif 2678 } 2679 2680 /* 2681 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2682 * bus_addr_t card_addr, bus_size_t size, 2683 * struct pcmcia_mem_handle *pcmhp, 2684 * bus_addr_t *offsetp, int *windowp) 2685 * 2686 * This function maps memory space allocated by the function 2687 * pccbb_pcmcia_mem_alloc(). 2688 */ 2689 STATIC int 2690 pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2691 bus_addr_t card_addr, bus_size_t size, struct pcmcia_mem_handle *pcmhp, 2692 bus_addr_t *offsetp, int *windowp) 2693 { 2694 struct pcic_handle *ph = (struct pcic_handle *)pch; 2695 bus_addr_t busaddr; 2696 long card_offset; 2697 int win; 2698 2699 /* Check that the card is still there. */ 2700 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2701 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2702 return 1; 2703 2704 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2705 if ((ph->memalloc & (1 << win)) == 0) { 2706 ph->memalloc |= (1 << win); 2707 break; 2708 } 2709 } 2710 2711 if (win == PCIC_MEM_WINS) { 2712 return 1; 2713 } 2714 2715 *windowp = win; 2716 2717 /* XXX this is pretty gross */ 2718 2719 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2720 panic("pccbb_pcmcia_mem_map memt is bogus"); 2721 } 2722 2723 busaddr = pcmhp->addr; 2724 2725 /* 2726 * compute the address offset to the pcmcia address space for the 2727 * pcic. this is intentionally signed. The masks and shifts below 2728 * will cause TRT to happen in the pcic registers. Deal with making 2729 * sure the address is aligned, and return the alignment offset. 2730 */ 2731 2732 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2733 card_addr -= *offsetp; 2734 2735 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2736 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2737 (u_long) card_addr)); 2738 2739 /* 2740 * include the offset in the size, and decrement size by one, since 2741 * the hw wants start/stop 2742 */ 2743 size += *offsetp - 1; 2744 2745 card_offset = (((long)card_addr) - ((long)busaddr)); 2746 2747 ph->mem[win].addr = busaddr; 2748 ph->mem[win].size = size; 2749 ph->mem[win].offset = card_offset; 2750 ph->mem[win].kind = kind; 2751 2752 pccbb_pcmcia_do_mem_map(ph, win); 2753 2754 return 0; 2755 } 2756 2757 /* 2758 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2759 * int window) 2760 * 2761 * This function unmaps memory space which mapped by the function 2762 * pccbb_pcmcia_mem_map(). 2763 */ 2764 STATIC void 2765 pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, int window) 2766 { 2767 struct pcic_handle *ph = (struct pcic_handle *)pch; 2768 int reg; 2769 2770 if (window >= PCIC_MEM_WINS) { 2771 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2772 } 2773 2774 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2775 reg &= ~(1 << window); 2776 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2777 2778 ph->memalloc &= ~(1 << window); 2779 } 2780 2781 #if defined PCCBB_PCMCIA_POLL 2782 struct pccbb_poll_str { 2783 void *arg; 2784 int (*func)(void *); 2785 int level; 2786 struct pcic_handle *ph; 2787 int count; 2788 int num; 2789 struct callout poll_ch; 2790 }; 2791 2792 static struct pccbb_poll_str pccbb_poll[10]; 2793 static int pccbb_poll_n = 0; 2794 2795 static void pccbb_pcmcia_poll(void *arg); 2796 2797 static void 2798 pccbb_pcmcia_poll(void *arg) 2799 { 2800 struct pccbb_poll_str *poll = arg; 2801 struct pcic_handle *ph = poll->ph; 2802 struct pccbb_softc *sc = ph->sc; 2803 int s; 2804 u_int32_t spsr; /* socket present-state reg */ 2805 2806 callout_reset(&poll->poll_ch, hz * 2, pccbb_pcmcia_poll, arg); 2807 switch (poll->level) { 2808 case IPL_NET: 2809 s = splnet(); 2810 break; 2811 case IPL_BIO: 2812 s = splbio(); 2813 break; 2814 case IPL_TTY: /* fallthrough */ 2815 default: 2816 s = spltty(); 2817 break; 2818 } 2819 2820 spsr = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2821 CB_SOCKET_STAT); 2822 2823 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2824 if (!(spsr & 0x40)) /* CINT low */ 2825 #else 2826 if (1) 2827 #endif 2828 { 2829 if ((*poll->func) (poll->arg) > 0) { 2830 ++poll->count; 2831 /* printf("intr: reported from poller, 0x%x\n", spsr); */ 2832 #if defined LEVEL2 2833 } else { 2834 printf("intr: miss! 0x%x\n", spsr); 2835 #endif 2836 } 2837 } 2838 splx(s); 2839 } 2840 #endif /* defined CB_PCMCIA_POLL */ 2841 2842 /* 2843 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2844 * struct pcmcia_function *pf, 2845 * int ipl, 2846 * int (*func)(void *), 2847 * void *arg); 2848 * 2849 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2850 */ 2851 STATIC void * 2852 pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2853 struct pcmcia_function *pf, int ipl, int (*func)(void *), void *arg) 2854 { 2855 struct pcic_handle *ph = (struct pcic_handle *)pch; 2856 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2857 2858 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2859 /* what should I do? */ 2860 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2861 DPRINTF(("%s does not provide edge nor pulse " 2862 "interrupt\n", sc->sc_dev.dv_xname)); 2863 return NULL; 2864 } 2865 /* 2866 * XXX Noooooo! The interrupt flag must set properly!! 2867 * dumb pcmcia driver!! 2868 */ 2869 } 2870 2871 return pccbb_intr_establish(sc, 0, ipl, func, arg); 2872 } 2873 2874 /* 2875 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2876 * void *ih) 2877 * 2878 * This function disables PC-Card interrupt. 2879 */ 2880 STATIC void 2881 pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 2882 { 2883 struct pcic_handle *ph = (struct pcic_handle *)pch; 2884 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2885 2886 pccbb_intr_disestablish(sc, ih); 2887 } 2888 2889 #if rbus 2890 /* 2891 * static int 2892 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2893 * bus_addr_t addr, bus_size_t size, 2894 * bus_addr_t mask, bus_size_t align, 2895 * int flags, bus_addr_t *addrp; 2896 * bus_space_handle_t *bshp) 2897 * 2898 * This function allocates a portion of memory or io space for 2899 * clients. This function is called from CardBus card drivers. 2900 */ 2901 static int 2902 pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2903 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 2904 int flags, bus_addr_t *addrp, bus_space_handle_t *bshp) 2905 { 2906 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2907 2908 DPRINTF(("pccbb_rbus_cb_space_alloc: addr 0x%lx, size 0x%lx, " 2909 "mask 0x%lx, align 0x%lx\n", (unsigned long)addr, 2910 (unsigned long)size, (unsigned long)mask, (unsigned long)align)); 2911 2912 if (align == 0) { 2913 align = size; 2914 } 2915 2916 if (rb->rb_bt == sc->sc_memt) { 2917 if (align < 16) { 2918 return 1; 2919 } 2920 /* 2921 * XXX: align more than 0x1000 to avoid overwrapping 2922 * memory windows for two or more devices. 0x1000 2923 * means memory window's granularity. 2924 * 2925 * Two or more devices should be able to share same 2926 * memory window region. However, overrapping memory 2927 * window is not good because some devices, such as 2928 * 3Com 3C575[BC], have a broken address decoder and 2929 * intrude other's memory region. 2930 */ 2931 if (align < 0x1000) { 2932 align = 0x1000; 2933 } 2934 } else if (rb->rb_bt == sc->sc_iot) { 2935 if (align < 4) { 2936 return 1; 2937 } 2938 /* XXX: hack for avoiding ISA image */ 2939 if (mask < 0x0100) { 2940 mask = 0x3ff; 2941 addr = 0x300; 2942 } 2943 2944 } else { 2945 DPRINTF(("pccbb_rbus_cb_space_alloc: Bus space tag 0x%lx is " 2946 "NOT used. io: 0x%lx, mem: 0x%lx\n", 2947 (unsigned long)rb->rb_bt, (unsigned long)sc->sc_iot, 2948 (unsigned long)sc->sc_memt)); 2949 return 1; 2950 /* XXX: panic here? */ 2951 } 2952 2953 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 2954 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 2955 return 1; 2956 } 2957 2958 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 2959 2960 return 0; 2961 } 2962 2963 /* 2964 * static int 2965 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 2966 * bus_space_handle_t *bshp, bus_size_t size); 2967 * 2968 * This function is called from CardBus card drivers. 2969 */ 2970 static int 2971 pccbb_rbus_cb_space_free(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2972 bus_space_handle_t bsh, bus_size_t size) 2973 { 2974 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2975 bus_space_tag_t bt = rb->rb_bt; 2976 2977 pccbb_close_win(sc, bt, bsh, size); 2978 2979 if (bt == sc->sc_memt) { 2980 } else if (bt == sc->sc_iot) { 2981 } else { 2982 return 1; 2983 /* XXX: panic here? */ 2984 } 2985 2986 return rbus_space_free(rb, bsh, size, NULL); 2987 } 2988 #endif /* rbus */ 2989 2990 #if rbus 2991 2992 static int 2993 pccbb_open_win(struct pccbb_softc *sc, bus_space_tag_t bst, bus_addr_t addr, 2994 bus_size_t size, bus_space_handle_t bsh, int flags) 2995 { 2996 struct pccbb_win_chain_head *head; 2997 bus_addr_t align; 2998 2999 head = &sc->sc_iowindow; 3000 align = 0x04; 3001 if (sc->sc_memt == bst) { 3002 head = &sc->sc_memwindow; 3003 align = 0x1000; 3004 DPRINTF(("using memory window, 0x%lx 0x%lx 0x%lx\n\n", 3005 (unsigned long)sc->sc_iot, (unsigned long)sc->sc_memt, 3006 (unsigned long)bst)); 3007 } 3008 3009 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 3010 printf("%s: pccbb_open_win: %s winlist insert failed\n", 3011 sc->sc_dev.dv_xname, 3012 (head == &sc->sc_memwindow) ? "mem" : "io"); 3013 } 3014 pccbb_winset(align, sc, bst); 3015 3016 return 0; 3017 } 3018 3019 static int 3020 pccbb_close_win(struct pccbb_softc *sc, bus_space_tag_t bst, 3021 bus_space_handle_t bsh, bus_size_t size) 3022 { 3023 struct pccbb_win_chain_head *head; 3024 bus_addr_t align; 3025 3026 head = &sc->sc_iowindow; 3027 align = 0x04; 3028 if (sc->sc_memt == bst) { 3029 head = &sc->sc_memwindow; 3030 align = 0x1000; 3031 } 3032 3033 if (pccbb_winlist_delete(head, bsh, size)) { 3034 printf("%s: pccbb_close_win: %s winlist delete failed\n", 3035 sc->sc_dev.dv_xname, 3036 (head == &sc->sc_memwindow) ? "mem" : "io"); 3037 } 3038 pccbb_winset(align, sc, bst); 3039 3040 return 0; 3041 } 3042 3043 static int 3044 pccbb_winlist_insert(struct pccbb_win_chain_head *head, bus_addr_t start, 3045 bus_size_t size, bus_space_handle_t bsh, int flags) 3046 { 3047 struct pccbb_win_chain *chainp, *elem; 3048 3049 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 3050 M_NOWAIT)) == NULL) 3051 return (1); /* fail */ 3052 3053 elem->wc_start = start; 3054 elem->wc_end = start + (size - 1); 3055 elem->wc_handle = bsh; 3056 elem->wc_flags = flags; 3057 3058 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3059 chainp = TAILQ_NEXT(chainp, wc_list)) { 3060 if (chainp->wc_end < start) 3061 continue; 3062 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 3063 return (0); 3064 } 3065 3066 TAILQ_INSERT_TAIL(head, elem, wc_list); 3067 return (0); 3068 } 3069 3070 static int 3071 pccbb_winlist_delete(struct pccbb_win_chain_head *head, bus_space_handle_t bsh, 3072 bus_size_t size) 3073 { 3074 struct pccbb_win_chain *chainp; 3075 3076 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3077 chainp = TAILQ_NEXT(chainp, wc_list)) { 3078 if (memcmp(&chainp->wc_handle, &bsh, sizeof(bsh))) 3079 continue; 3080 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 3081 printf("pccbb_winlist_delete: window 0x%lx size " 3082 "inconsistent: 0x%lx, 0x%lx\n", 3083 (unsigned long)chainp->wc_start, 3084 (unsigned long)(chainp->wc_end - chainp->wc_start), 3085 (unsigned long)(size - 1)); 3086 return 1; 3087 } 3088 3089 TAILQ_REMOVE(head, chainp, wc_list); 3090 free(chainp, M_DEVBUF); 3091 3092 return 0; 3093 } 3094 3095 return 1; /* fail: no candidate to remove */ 3096 } 3097 3098 static void 3099 pccbb_winset(bus_addr_t align, struct pccbb_softc *sc, bus_space_tag_t bst) 3100 { 3101 pci_chipset_tag_t pc; 3102 pcitag_t tag; 3103 bus_addr_t mask = ~(align - 1); 3104 struct { 3105 cardbusreg_t win_start; 3106 cardbusreg_t win_limit; 3107 int win_flags; 3108 } win[2]; 3109 struct pccbb_win_chain *chainp; 3110 int offs; 3111 3112 win[0].win_start = win[1].win_start = 0xffffffff; 3113 win[0].win_limit = win[1].win_limit = 0; 3114 win[0].win_flags = win[1].win_flags = 0; 3115 3116 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3117 offs = 0x2c; 3118 if (sc->sc_memt == bst) { 3119 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3120 offs = 0x1c; 3121 } 3122 3123 if (chainp != NULL) { 3124 win[0].win_start = chainp->wc_start & mask; 3125 win[0].win_limit = chainp->wc_end & mask; 3126 win[0].win_flags = chainp->wc_flags; 3127 chainp = TAILQ_NEXT(chainp, wc_list); 3128 } 3129 3130 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3131 if (win[1].win_start == 0xffffffff) { 3132 /* window 1 is not used */ 3133 if ((win[0].win_flags == chainp->wc_flags) && 3134 (win[0].win_limit + align >= 3135 (chainp->wc_start & mask))) { 3136 /* concatenate */ 3137 win[0].win_limit = chainp->wc_end & mask; 3138 } else { 3139 /* make new window */ 3140 win[1].win_start = chainp->wc_start & mask; 3141 win[1].win_limit = chainp->wc_end & mask; 3142 win[1].win_flags = chainp->wc_flags; 3143 } 3144 continue; 3145 } 3146 3147 /* Both windows are engaged. */ 3148 if (win[0].win_flags == win[1].win_flags) { 3149 /* same flags */ 3150 if (win[0].win_flags == chainp->wc_flags) { 3151 if (win[1].win_start - (win[0].win_limit + 3152 align) < 3153 (chainp->wc_start & mask) - 3154 ((chainp->wc_end & mask) + align)) { 3155 /* 3156 * merge window 0 and 1, and set win1 3157 * to chainp 3158 */ 3159 win[0].win_limit = win[1].win_limit; 3160 win[1].win_start = 3161 chainp->wc_start & mask; 3162 win[1].win_limit = 3163 chainp->wc_end & mask; 3164 } else { 3165 win[1].win_limit = 3166 chainp->wc_end & mask; 3167 } 3168 } else { 3169 /* different flags */ 3170 3171 /* concatenate win0 and win1 */ 3172 win[0].win_limit = win[1].win_limit; 3173 /* allocate win[1] to new space */ 3174 win[1].win_start = chainp->wc_start & mask; 3175 win[1].win_limit = chainp->wc_end & mask; 3176 win[1].win_flags = chainp->wc_flags; 3177 } 3178 } else { 3179 /* the flags of win[0] and win[1] is different */ 3180 if (win[0].win_flags == chainp->wc_flags) { 3181 win[0].win_limit = chainp->wc_end & mask; 3182 /* 3183 * XXX this creates overlapping windows, so 3184 * what should the poor bridge do if one is 3185 * cachable, and the other is not? 3186 */ 3187 printf("%s: overlapping windows\n", 3188 sc->sc_dev.dv_xname); 3189 } else { 3190 win[1].win_limit = chainp->wc_end & mask; 3191 } 3192 } 3193 } 3194 3195 pc = sc->sc_pc; 3196 tag = sc->sc_tag; 3197 pci_conf_write(pc, tag, offs, win[0].win_start); 3198 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3199 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3200 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3201 DPRINTF(("--pccbb_winset: win0 [0x%lx, 0x%lx), win1 [0x%lx, 0x%lx)\n", 3202 (unsigned long)pci_conf_read(pc, tag, offs), 3203 (unsigned long)pci_conf_read(pc, tag, offs + 4) + align, 3204 (unsigned long)pci_conf_read(pc, tag, offs + 8), 3205 (unsigned long)pci_conf_read(pc, tag, offs + 12) + align)); 3206 3207 if (bst == sc->sc_memt) { 3208 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BRIDGE_CONTROL_REG); 3209 3210 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 3211 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 3212 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3213 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 3214 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3215 pci_conf_write(pc, tag, PCI_BRIDGE_CONTROL_REG, bcr); 3216 } 3217 } 3218 3219 #endif /* rbus */ 3220 3221 static void 3222 pccbb_powerhook(int why, void *arg) 3223 { 3224 struct pccbb_softc *sc = arg; 3225 pcireg_t reg; 3226 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3227 bus_space_handle_t base_memh = sc->sc_base_memh; 3228 3229 DPRINTF(("%s: power: why %d\n", sc->sc_dev.dv_xname, why)); 3230 3231 if (why == PWR_SUSPEND || why == PWR_STANDBY) { 3232 DPRINTF(("%s: power: why %d stopping intr\n", 3233 sc->sc_dev.dv_xname, why)); 3234 if (sc->sc_pil_intr_enable) { 3235 (void)pccbbintr_function(sc); 3236 } 3237 sc->sc_pil_intr_enable = 0; 3238 3239 pci_conf_capture(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf); 3240 3241 if (sc->sc_chipset == CB_RX5C47X) 3242 sc->sc_ricoh_misc_ctrl = pci_conf_read(sc->sc_pc, 3243 sc->sc_tag, 3244 RICOH_PCI_MISC_CTRL); 3245 3246 /* ToDo: deactivate or suspend child devices */ 3247 } 3248 3249 if (why == PWR_RESUME) { 3250 if (sc->sc_pwrmgt_offs != 0) { 3251 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, 3252 sc->sc_pwrmgt_offs + PCI_PMCSR); 3253 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 3254 reg & PCI_PMCSR_PME_EN) { 3255 /* powrstate != D0 */ 3256 3257 printf("%s going back to D0 mode\n", 3258 sc->sc_dev.dv_xname); 3259 reg &= ~PCI_PMCSR_STATE_MASK; 3260 reg |= PCI_PMCSR_STATE_D0; 3261 reg &= ~PCI_PMCSR_PME_EN; 3262 pci_conf_write(sc->sc_pc, sc->sc_tag, 3263 sc->sc_pwrmgt_offs + PCI_PMCSR, reg); 3264 3265 pci_conf_write(sc->sc_pc, sc->sc_tag, 3266 PCI_SOCKBASE, sc->sc_sockbase); 3267 pci_conf_write(sc->sc_pc, sc->sc_tag, 3268 PCI_BUSNUM, sc->sc_busnum); 3269 pccbb_chipinit(sc); 3270 /* setup memory and io space window for CB */ 3271 pccbb_winset(0x1000, sc, sc->sc_memt); 3272 pccbb_winset(0x04, sc, sc->sc_iot); 3273 goto norestore; 3274 } 3275 } 3276 3277 norestore: 3278 pci_conf_restore(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf); 3279 if (sc->sc_chipset == CB_RX5C47X) { 3280 pci_conf_write(sc->sc_pc, sc->sc_tag, 3281 RICOH_PCI_MISC_CTRL, sc->sc_ricoh_misc_ctrl); 3282 } 3283 3284 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_SOCKBASE) == 0) 3285 /* BIOS did not recover this register */ 3286 pci_conf_write (sc->sc_pc, sc->sc_tag, 3287 PCI_SOCKBASE, sc->sc_sockbase); 3288 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_BUSNUM) == 0) 3289 /* BIOS did not recover this register */ 3290 pci_conf_write (sc->sc_pc, sc->sc_tag, 3291 PCI_BUSNUM, sc->sc_busnum); 3292 /* CSC Interrupt: Card detect interrupt on */ 3293 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3294 /* Card detect intr is turned on. */ 3295 reg |= CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; 3296 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3297 /* reset interrupt */ 3298 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3299 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3300 3301 /* 3302 * check for card insertion or removal during suspend period. 3303 * XXX: the code can't cope with card swap (remove then 3304 * insert). how can we detect such situation? 3305 */ 3306 (void)pccbbintr(sc); 3307 3308 sc->sc_pil_intr_enable = 1; 3309 DPRINTF(("%s: power: RESUME enabling intr\n", 3310 sc->sc_dev.dv_xname)); 3311 3312 /* ToDo: activate or wakeup child devices */ 3313 } 3314 } 3315
Indexes created Tue Oct 14 06:10:07 GMT 2025