pccbb.c revision 1.148
1 /* $NetBSD: pccbb.c,v 1.148 2007/10/19 12:00:53 ad Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: pccbb.c,v 1.148 2007/10/19 12:00:53 ad Exp $"); 35 36 /* 37 #define CBB_DEBUG 38 #define SHOW_REGS 39 */ 40 41 /* 42 * BROKEN! 43 #define PCCBB_PCMCIA_POLL 44 #define CB_PCMCIA_POLL 45 #define CB_PCMCIA_POLL_ONLY 46 #define LEVEL2 47 */ 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/kernel.h> 52 #include <sys/errno.h> 53 #include <sys/ioctl.h> 54 #include <sys/reboot.h> /* for bootverbose */ 55 #include <sys/syslog.h> 56 #include <sys/device.h> 57 #include <sys/malloc.h> 58 #include <sys/proc.h> 59 60 #include <sys/intr.h> 61 #include <sys/bus.h> 62 63 #include <dev/pci/pcivar.h> 64 #include <dev/pci/pcireg.h> 65 #include <dev/pci/pcidevs.h> 66 67 #include <dev/pci/pccbbreg.h> 68 69 #include <dev/cardbus/cardslotvar.h> 70 71 #include <dev/cardbus/cardbusvar.h> 72 73 #include <dev/pcmcia/pcmciareg.h> 74 #include <dev/pcmcia/pcmciavar.h> 75 76 #include <dev/ic/i82365reg.h> 77 #include <dev/ic/i82365var.h> 78 #include <dev/pci/pccbbvar.h> 79 80 #include "locators.h" 81 82 #if defined(__i386__) 83 #include "ioapic.h" 84 #include "acpi.h" 85 #endif 86 87 #ifndef __NetBSD_Version__ 88 struct cfdriver cbb_cd = { 89 NULL, "cbb", DV_DULL 90 }; 91 #endif 92 93 #ifdef CBB_DEBUG 94 #define DPRINTF(x) printf x 95 #define STATIC 96 #else 97 #define DPRINTF(x) 98 #define STATIC static 99 #endif 100 101 /* 102 * delay_ms() is wait in milliseconds. It should be used instead 103 * of delay() if you want to wait more than 1 ms. 104 */ 105 static inline void 106 delay_ms(int millis, void *param) 107 { 108 if (cold) 109 delay(millis * 1000); 110 else 111 tsleep(param, PWAIT, "pccbb", MAX(2, hz * millis / 1000)); 112 } 113 114 int pcicbbmatch(struct device *, struct cfdata *, void *); 115 void pccbbattach(struct device *, struct device *, void *); 116 int pccbbintr(void *); 117 static void pci113x_insert(void *); 118 static int pccbbintr_function(struct pccbb_softc *); 119 120 static int pccbb_detect_card(struct pccbb_softc *); 121 122 static void pccbb_pcmcia_write(struct pcic_handle *, int, u_int8_t); 123 static u_int8_t pccbb_pcmcia_read(struct pcic_handle *, int); 124 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 125 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 126 127 STATIC int cb_reset(struct pccbb_softc *); 128 STATIC int cb_detect_voltage(struct pccbb_softc *); 129 STATIC int cbbprint(void *, const char *); 130 131 static int cb_chipset(u_int32_t, int *); 132 STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *, 133 struct pcmciabus_attach_args *); 134 #if 0 135 STATIC void pccbb_pcmcia_attach_card(struct pcic_handle *); 136 STATIC void pccbb_pcmcia_detach_card(struct pcic_handle *, int); 137 STATIC void pccbb_pcmcia_deactivate_card(struct pcic_handle *); 138 #endif 139 140 STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int); 141 STATIC int pccbb_power(cardbus_chipset_tag_t, int); 142 STATIC int pccbb_cardenable(struct pccbb_softc * sc, int function); 143 #if !rbus 144 static int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 145 static int pccbb_io_close(cardbus_chipset_tag_t, int); 146 static int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 147 static int pccbb_mem_close(cardbus_chipset_tag_t, int); 148 #endif /* !rbus */ 149 static void *pccbb_intr_establish(struct pccbb_softc *, int irq, 150 int level, int (*ih) (void *), void *sc); 151 static void pccbb_intr_disestablish(struct pccbb_softc *, void *ih); 152 153 static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t, int irq, 154 int level, int (*ih) (void *), void *sc); 155 static void pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih); 156 157 static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t, int, int); 158 static void pccbb_free_tag(cardbus_chipset_tag_t, cardbustag_t); 159 static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t, cardbustag_t, int); 160 static void pccbb_conf_write(cardbus_chipset_tag_t, cardbustag_t, int, 161 cardbusreg_t); 162 static void pccbb_chipinit(struct pccbb_softc *); 163 164 STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 165 struct pcmcia_mem_handle *); 166 STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t, 167 struct pcmcia_mem_handle *); 168 STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 169 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *); 170 STATIC void pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t, int); 171 STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 172 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 173 STATIC void pccbb_pcmcia_io_free(pcmcia_chipset_handle_t, 174 struct pcmcia_io_handle *); 175 STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 176 bus_size_t, struct pcmcia_io_handle *, int *); 177 STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t, int); 178 STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t, 179 struct pcmcia_function *, int, int (*)(void *), void *); 180 STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t, void *); 181 STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t); 182 STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t); 183 STATIC void pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t, int); 184 STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch); 185 186 static int pccbb_pcmcia_wait_ready(struct pcic_handle *); 187 static void pccbb_pcmcia_delay(struct pcic_handle *, int, const char *); 188 189 static void pccbb_pcmcia_do_io_map(struct pcic_handle *, int); 190 static void pccbb_pcmcia_do_mem_map(struct pcic_handle *, int); 191 static void pccbb_powerhook(int, void *); 192 193 /* bus-space allocation and deallocation functions */ 194 #if rbus 195 196 static int pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t, rbus_tag_t, 197 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 198 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp); 199 static int pccbb_rbus_cb_space_free(cardbus_chipset_tag_t, rbus_tag_t, 200 bus_space_handle_t, bus_size_t); 201 202 #endif /* rbus */ 203 204 #if rbus 205 206 static int pccbb_open_win(struct pccbb_softc *, bus_space_tag_t, 207 bus_addr_t, bus_size_t, bus_space_handle_t, int flags); 208 static int pccbb_close_win(struct pccbb_softc *, bus_space_tag_t, 209 bus_space_handle_t, bus_size_t); 210 static int pccbb_winlist_insert(struct pccbb_win_chain_head *, bus_addr_t, 211 bus_size_t, bus_space_handle_t, int); 212 static int pccbb_winlist_delete(struct pccbb_win_chain_head *, 213 bus_space_handle_t, bus_size_t); 214 static void pccbb_winset(bus_addr_t align, struct pccbb_softc *, 215 bus_space_tag_t); 216 void pccbb_winlist_show(struct pccbb_win_chain *); 217 218 #endif /* rbus */ 219 220 /* for config_defer */ 221 static void pccbb_pci_callback(struct device *); 222 223 #if defined SHOW_REGS 224 static void cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, 225 bus_space_tag_t memt, bus_space_handle_t memh); 226 #endif 227 228 CFATTACH_DECL(cbb_pci, sizeof(struct pccbb_softc), 229 pcicbbmatch, pccbbattach, NULL, NULL); 230 231 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 232 pccbb_pcmcia_mem_alloc, 233 pccbb_pcmcia_mem_free, 234 pccbb_pcmcia_mem_map, 235 pccbb_pcmcia_mem_unmap, 236 pccbb_pcmcia_io_alloc, 237 pccbb_pcmcia_io_free, 238 pccbb_pcmcia_io_map, 239 pccbb_pcmcia_io_unmap, 240 pccbb_pcmcia_intr_establish, 241 pccbb_pcmcia_intr_disestablish, 242 pccbb_pcmcia_socket_enable, 243 pccbb_pcmcia_socket_disable, 244 pccbb_pcmcia_socket_settype, 245 pccbb_pcmcia_card_detect 246 }; 247 248 #if rbus 249 static struct cardbus_functions pccbb_funcs = { 250 pccbb_rbus_cb_space_alloc, 251 pccbb_rbus_cb_space_free, 252 pccbb_cb_intr_establish, 253 pccbb_cb_intr_disestablish, 254 pccbb_ctrl, 255 pccbb_power, 256 pccbb_make_tag, 257 pccbb_free_tag, 258 pccbb_conf_read, 259 pccbb_conf_write, 260 }; 261 #else 262 static struct cardbus_functions pccbb_funcs = { 263 pccbb_ctrl, 264 pccbb_power, 265 pccbb_mem_open, 266 pccbb_mem_close, 267 pccbb_io_open, 268 pccbb_io_close, 269 pccbb_cb_intr_establish, 270 pccbb_cb_intr_disestablish, 271 pccbb_make_tag, 272 pccbb_conf_read, 273 pccbb_conf_write, 274 }; 275 #endif 276 277 int 278 pcicbbmatch(struct device *parent, struct cfdata *match, void *aux) 279 { 280 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 281 282 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 283 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 284 PCI_INTERFACE(pa->pa_class) == 0) { 285 return 1; 286 } 287 288 return 0; 289 } 290 291 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 292 | ((prod) << PCI_PRODUCT_SHIFT)) 293 294 const struct yenta_chipinfo { 295 pcireg_t yc_id; /* vendor tag | product tag */ 296 int yc_chiptype; 297 int yc_flags; 298 } yc_chipsets[] = { 299 /* Texas Instruments chips */ 300 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 301 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 302 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 303 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 304 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI125X, 305 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 306 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 307 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 308 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 309 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 310 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 311 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 312 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI125X, 313 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 314 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI125X, 315 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 316 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 317 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 318 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 319 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 320 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 321 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 322 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI125X, 323 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 324 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 325 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 326 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1520), CB_TI12XX, 327 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 328 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4410YENTA), CB_TI12XX, 329 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 330 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4520YENTA), CB_TI12XX, 331 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 332 333 /* Ricoh chips */ 334 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 335 PCCBB_PCMCIA_MEM_32}, 336 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 337 PCCBB_PCMCIA_MEM_32}, 338 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 339 PCCBB_PCMCIA_MEM_32}, 340 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 341 PCCBB_PCMCIA_MEM_32}, 342 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 343 PCCBB_PCMCIA_MEM_32}, 344 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 345 PCCBB_PCMCIA_MEM_32}, 346 347 /* Toshiba products */ 348 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 349 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 350 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 351 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 352 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 353 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 354 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 355 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 356 357 /* Cirrus Logic products */ 358 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 359 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 360 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 361 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 362 363 /* sentinel, or Generic chip */ 364 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 365 }; 366 367 static int 368 cb_chipset(u_int32_t pci_id, int *flagp) 369 { 370 const struct yenta_chipinfo *yc; 371 372 /* Loop over except the last default entry. */ 373 for (yc = yc_chipsets; yc < yc_chipsets + 374 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 375 if (pci_id == yc->yc_id) 376 break; 377 378 if (flagp != NULL) 379 *flagp = yc->yc_flags; 380 381 return (yc->yc_chiptype); 382 } 383 384 static void 385 pccbb_shutdown(void *arg) 386 { 387 struct pccbb_softc *sc = arg; 388 pcireg_t command; 389 390 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 391 392 /* 393 * turn off power 394 * 395 * XXX - do not turn off power if chipset is TI 113X because 396 * only TI 1130 with PowerMac 2400 hangs in pccbb_power(). 397 */ 398 if (sc->sc_chipset != CB_TI113X) { 399 pccbb_power((cardbus_chipset_tag_t)sc, 400 CARDBUS_VCC_0V | CARDBUS_VPP_0V); 401 } 402 403 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 404 0); 405 406 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 407 408 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 409 PCI_COMMAND_MASTER_ENABLE); 410 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 411 412 } 413 414 void 415 pccbbattach(struct device *parent, struct device *self, void *aux) 416 { 417 struct pccbb_softc *sc = (void *)self; 418 struct pci_attach_args *pa = aux; 419 pci_chipset_tag_t pc = pa->pa_pc; 420 pcireg_t busreg, reg, sock_base; 421 bus_addr_t sockbase; 422 char devinfo[256]; 423 int flags; 424 int pwrmgt_offs; 425 426 #ifdef __HAVE_PCCBB_ATTACH_HOOK 427 pccbb_attach_hook(parent, self, pa); 428 #endif 429 430 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 431 432 pci_devinfo(pa->pa_id, 0, 0, devinfo, sizeof(devinfo)); 433 printf(": %s (rev. 0x%02x)", devinfo, PCI_REVISION(pa->pa_class)); 434 DPRINTF((" (chipflags %x)", flags)); 435 printf("\n"); 436 437 TAILQ_INIT(&sc->sc_memwindow); 438 TAILQ_INIT(&sc->sc_iowindow); 439 440 #if rbus 441 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 442 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 443 444 #if 0 445 printf("pa->pa_memt: %08x vs rbus_mem->rb_bt: %08x\n", 446 pa->pa_memt, sc->sc_rbus_memt->rb_bt); 447 #endif 448 #endif /* rbus */ 449 450 sc->sc_flags &= ~CBB_MEMHMAPPED; 451 452 /* power management: set D0 state */ 453 sc->sc_pwrmgt_offs = 0; 454 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, 455 &pwrmgt_offs, 0)) { 456 reg = pci_conf_read(pc, pa->pa_tag, pwrmgt_offs + PCI_PMCSR); 457 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 458 reg & 0x100 /* PCI_PMCSR_PME_EN */) { 459 reg &= ~PCI_PMCSR_STATE_MASK; 460 reg |= PCI_PMCSR_STATE_D0; 461 reg &= ~(0x100 /* PCI_PMCSR_PME_EN */); 462 pci_conf_write(pc, pa->pa_tag, 463 pwrmgt_offs + PCI_PMCSR, reg); 464 } 465 466 sc->sc_pwrmgt_offs = pwrmgt_offs; 467 } 468 469 /* 470 * MAP socket registers and ExCA registers on memory-space 471 * When no valid address is set on socket base registers (on pci 472 * config space), get it not polite way. 473 */ 474 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 475 476 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 477 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 478 /* The address must be valid. */ 479 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 480 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL)) { 481 printf("%s: can't map socket base address 0x%lx\n", 482 sc->sc_dev.dv_xname, (unsigned long)sock_base); 483 /* 484 * I think it's funny: socket base registers must be 485 * mapped on memory space, but ... 486 */ 487 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 488 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 489 NULL)) { 490 printf("%s: can't map socket base address" 491 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 492 (unsigned long)sockbase); 493 /* give up... allocate reg space via rbus. */ 494 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 495 } else 496 sc->sc_flags |= CBB_MEMHMAPPED; 497 } else { 498 DPRINTF(("%s: socket base address 0x%lx\n", 499 sc->sc_dev.dv_xname, (unsigned long)sockbase)); 500 sc->sc_flags |= CBB_MEMHMAPPED; 501 } 502 } 503 504 sc->sc_mem_start = 0; /* XXX */ 505 sc->sc_mem_end = 0xffffffff; /* XXX */ 506 507 /* 508 * When interrupt isn't routed correctly, give up probing cbb and do 509 * not kill pcic-compatible port. 510 * 511 * However, if we are using an ioapic, avoid this check -- pa_intrline 512 * may well be zero, with the interrupt routed through the apic. 513 */ 514 515 #if NIOAPIC == 0 && NACPI == 0 516 if ((0 == pa->pa_intrline) || (255 == pa->pa_intrline)) { 517 printf("%s: NOT USED because of unconfigured interrupt\n", 518 sc->sc_dev.dv_xname); 519 return; 520 } 521 #endif 522 523 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 524 525 /* pccbb_machdep.c end */ 526 527 #if defined CBB_DEBUG 528 { 529 static const char *intrname[] = { "NON", "A", "B", "C", "D" }; 530 printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname, 531 intrname[pa->pa_intrpin], pa->pa_intrline); 532 } 533 #endif 534 535 /* setup softc */ 536 sc->sc_pc = pc; 537 sc->sc_iot = pa->pa_iot; 538 sc->sc_memt = pa->pa_memt; 539 sc->sc_dmat = pa->pa_dmat; 540 sc->sc_tag = pa->pa_tag; 541 sc->sc_function = pa->pa_function; 542 sc->sc_sockbase = sock_base; 543 sc->sc_busnum = busreg; 544 545 memcpy(&sc->sc_pa, pa, sizeof(*pa)); 546 547 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 548 549 shutdownhook_establish(pccbb_shutdown, sc); 550 551 /* Disable legacy register mapping. */ 552 switch (sc->sc_chipset) { 553 case CB_RX5C46X: /* fallthrough */ 554 #if 0 555 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 556 case CB_RX5C47X: 557 #endif 558 /* 559 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 560 * cannot be disabled by substituting 0 into PCI_LEGACY 561 * register. Ricoh CardBus bridges have special bits on Bridge 562 * control reg (addr 0x3e on PCI config space). 563 */ 564 reg = pci_conf_read(pc, pa->pa_tag, PCI_BRIDGE_CONTROL_REG); 565 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 566 pci_conf_write(pc, pa->pa_tag, PCI_BRIDGE_CONTROL_REG, reg); 567 break; 568 569 default: 570 /* XXX I don't know proper way to kill legacy I/O. */ 571 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 572 break; 573 } 574 575 config_defer(self, pccbb_pci_callback); 576 } 577 578 579 580 581 /* 582 * static void pccbb_pci_callback(struct device *self) 583 * 584 * The actual attach routine: get memory space for YENTA register 585 * space, setup YENTA register and route interrupt. 586 * 587 * This function should be deferred because this device may obtain 588 * memory space dynamically. This function must avoid obtaining 589 * memory area which has already kept for another device. 590 */ 591 static void 592 pccbb_pci_callback(struct device *self) 593 { 594 struct pccbb_softc *sc = (void *)self; 595 pci_chipset_tag_t pc = sc->sc_pc; 596 pci_intr_handle_t ih; 597 const char *intrstr = NULL; 598 bus_addr_t sockbase; 599 struct cbslot_attach_args cba; 600 struct pcmciabus_attach_args paa; 601 struct cardslot_attach_args caa; 602 struct cardslot_softc *csc; 603 604 if (!(sc->sc_flags & CBB_MEMHMAPPED)) { 605 /* The socket registers aren't mapped correctly. */ 606 #if rbus 607 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 608 (sc->sc_chipset == CB_RX5C47X 609 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 610 0, &sockbase, &sc->sc_base_memh)) { 611 return; 612 } 613 sc->sc_base_memt = sc->sc_memt; 614 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 615 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 616 sc->sc_dev.dv_xname, (unsigned long)sockbase, 617 (unsigned long)pci_conf_read(pc, sc->sc_tag, 618 PCI_SOCKBASE))); 619 #else 620 sc->sc_base_memt = sc->sc_memt; 621 #if !defined CBB_PCI_BASE 622 #define CBB_PCI_BASE 0x20000000 623 #endif 624 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 625 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 626 /* cannot allocate memory space */ 627 return; 628 } 629 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 630 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 631 sc->sc_dev.dv_xname, (unsigned long)sock_base, 632 (unsigned long)pci_conf_read(pc, 633 sc->sc_tag, PCI_SOCKBASE))); 634 sc->sc_sockbase = sockbase; 635 #endif 636 sc->sc_flags |= CBB_MEMHMAPPED; 637 } 638 639 /* bus bridge initialization */ 640 pccbb_chipinit(sc); 641 642 /* clear data structure for child device interrupt handlers */ 643 LIST_INIT(&sc->sc_pil); 644 sc->sc_pil_intr_enable = 1; 645 646 /* Map and establish the interrupt. */ 647 if (pci_intr_map(&sc->sc_pa, &ih)) { 648 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 649 return; 650 } 651 intrstr = pci_intr_string(pc, ih); 652 653 /* 654 * XXX pccbbintr should be called under the priority lower 655 * than any other hard interupts. 656 */ 657 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 658 659 if (sc->sc_ih == NULL) { 660 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 661 if (intrstr != NULL) { 662 printf(" at %s", intrstr); 663 } 664 printf("\n"); 665 return; 666 } 667 668 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 669 powerhook_establish(sc->sc_dev.dv_xname, pccbb_powerhook, sc); 670 671 { 672 u_int32_t sockstat; 673 674 sockstat = bus_space_read_4(sc->sc_base_memt, 675 sc->sc_base_memh, CB_SOCKET_STAT); 676 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 677 sc->sc_flags |= CBB_CARDEXIST; 678 } 679 } 680 681 /* 682 * attach cardbus 683 */ 684 { 685 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 686 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 687 688 /* initialize cbslot_attach */ 689 cba.cba_busname = "cardbus"; 690 cba.cba_iot = sc->sc_iot; 691 cba.cba_memt = sc->sc_memt; 692 cba.cba_dmat = sc->sc_dmat; 693 cba.cba_bus = (busreg >> 8) & 0x0ff; 694 cba.cba_cc = (void *)sc; 695 cba.cba_cf = &pccbb_funcs; 696 cba.cba_intrline = sc->sc_pa.pa_intrline; 697 698 #if rbus 699 cba.cba_rbus_iot = sc->sc_rbus_iot; 700 cba.cba_rbus_memt = sc->sc_rbus_memt; 701 #endif 702 703 cba.cba_cacheline = PCI_CACHELINE(bhlc); 704 cba.cba_lattimer = PCI_LATTIMER(bhlc); 705 706 if (bootverbose) { 707 printf("%s: cacheline 0x%x lattimer 0x%x\n", 708 sc->sc_dev.dv_xname, cba.cba_cacheline, 709 cba.cba_lattimer); 710 printf("%s: bhlc 0x%x\n", 711 device_xname(&sc->sc_dev), bhlc); 712 } 713 #if defined SHOW_REGS 714 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 715 sc->sc_base_memh); 716 #endif 717 } 718 719 pccbb_pcmcia_attach_setup(sc, &paa); 720 caa.caa_cb_attach = NULL; 721 if (cba.cba_bus == 0) 722 printf("%s: secondary bus number uninitialized; try PCI_BUS_FIXUP\n", sc->sc_dev.dv_xname); 723 else 724 caa.caa_cb_attach = &cba; 725 caa.caa_16_attach = &paa; 726 caa.caa_ph = &sc->sc_pcmcia_h; 727 728 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 729 DPRINTF(("%s: found cardslot\n", __func__)); 730 sc->sc_csc = csc; 731 } 732 733 return; 734 } 735 736 737 738 739 740 /* 741 * static void pccbb_chipinit(struct pccbb_softc *sc) 742 * 743 * This function initialize YENTA chip registers listed below: 744 * 1) PCI command reg, 745 * 2) PCI and CardBus latency timer, 746 * 3) route PCI interrupt, 747 * 4) close all memory and io windows. 748 * 5) turn off bus power. 749 * 6) card detect and power cycle interrupts on. 750 * 7) clear interrupt 751 */ 752 static void 753 pccbb_chipinit(struct pccbb_softc *sc) 754 { 755 pci_chipset_tag_t pc = sc->sc_pc; 756 pcitag_t tag = sc->sc_tag; 757 bus_space_tag_t bmt = sc->sc_base_memt; 758 bus_space_handle_t bmh = sc->sc_base_memh; 759 pcireg_t bcr, bhlc, cbctl, csr, lscp, mfunc, slotctl, sockctl, sockmask, 760 sysctrl; 761 762 /* 763 * Set PCI command reg. 764 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 765 */ 766 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 767 /* I believe it is harmless. */ 768 csr |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 769 PCI_COMMAND_MASTER_ENABLE); 770 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 771 772 /* 773 * Set CardBus latency timer. 774 */ 775 lscp = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 776 if (PCI_CB_LATENCY(lscp) < 0x20) { 777 lscp &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 778 lscp |= (0x20 << PCI_CB_LATENCY_SHIFT); 779 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, lscp); 780 } 781 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 782 PCI_CB_LATENCY(lscp), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 783 784 /* 785 * Set PCI latency timer. 786 */ 787 bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG); 788 if (PCI_LATTIMER(bhlc) < 0x10) { 789 bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 790 bhlc |= (0x10 << PCI_LATTIMER_SHIFT); 791 pci_conf_write(pc, tag, PCI_BHLC_REG, bhlc); 792 } 793 DPRINTF(("PCI latency timer 0x%x (%x)\n", 794 PCI_LATTIMER(bhlc), pci_conf_read(pc, tag, PCI_BHLC_REG))); 795 796 797 /* Route functional interrupts to PCI. */ 798 bcr = pci_conf_read(pc, tag, PCI_BRIDGE_CONTROL_REG); 799 bcr |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 800 bcr |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 801 /* assert reset */ 802 bcr |= PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT; 803 pci_conf_write(pc, tag, PCI_BRIDGE_CONTROL_REG, bcr); 804 805 switch (sc->sc_chipset) { 806 case CB_TI113X: 807 cbctl = pci_conf_read(pc, tag, PCI_CBCTRL); 808 /* This bit is shared, but may read as 0 on some chips, so set 809 it explicitly on both functions. */ 810 cbctl |= PCI113X_CBCTRL_PCI_IRQ_ENA; 811 /* CSC intr enable */ 812 cbctl |= PCI113X_CBCTRL_PCI_CSC; 813 /* functional intr prohibit | prohibit ISA routing */ 814 cbctl &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 815 pci_conf_write(pc, tag, PCI_CBCTRL, cbctl); 816 break; 817 818 case CB_TI12XX: 819 /* 820 * Some TI 12xx (and [14][45]xx) based pci cards 821 * sometimes have issues with the MFUNC register not 822 * being initialized due to a bad EEPROM on board. 823 * Laptops that this matters on have this register 824 * properly initialized. 825 * 826 * The TI125X parts have a different register. 827 */ 828 mfunc = pci_conf_read(pc, tag, PCI12XX_MFUNC); 829 if (mfunc == 0) { 830 mfunc &= ~PCI12XX_MFUNC_PIN0; 831 mfunc |= PCI12XX_MFUNC_PIN0_INTA; 832 if ((pci_conf_read(pc, tag, PCI_SYSCTRL) & 833 PCI12XX_SYSCTRL_INTRTIE) == 0) { 834 mfunc &= ~PCI12XX_MFUNC_PIN1; 835 mfunc |= PCI12XX_MFUNC_PIN1_INTB; 836 } 837 pci_conf_write(pc, tag, PCI12XX_MFUNC, mfunc); 838 } 839 /* fallthrough */ 840 841 case CB_TI125X: 842 /* 843 * Disable zoom video. Some machines initialize this 844 * improperly and experience has shown that this helps 845 * prevent strange behavior. 846 */ 847 pci_conf_write(pc, tag, PCI12XX_MMCTRL, 0); 848 849 sysctrl = pci_conf_read(pc, tag, PCI_SYSCTRL); 850 sysctrl |= PCI12XX_SYSCTRL_VCCPROT; 851 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 852 cbctl = pci_conf_read(pc, tag, PCI_CBCTRL); 853 cbctl |= PCI12XX_CBCTRL_CSC; 854 pci_conf_write(pc, tag, PCI_CBCTRL, cbctl); 855 break; 856 857 case CB_TOPIC95B: 858 sockctl = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 859 sockctl |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 860 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, sockctl); 861 slotctl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 862 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 863 sc->sc_dev.dv_xname, slotctl)); 864 slotctl |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 865 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 866 slotctl &= ~TOPIC_SLOT_CTRL_SWDETECT; 867 DPRINTF(("0x%x\n", slotctl)); 868 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slotctl); 869 break; 870 871 case CB_TOPIC97: 872 slotctl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 873 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 874 sc->sc_dev.dv_xname, slotctl)); 875 slotctl |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 876 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 877 slotctl &= ~TOPIC_SLOT_CTRL_SWDETECT; 878 slotctl |= TOPIC97_SLOT_CTRL_PCIINT; 879 slotctl &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 880 DPRINTF(("0x%x\n", slotctl)); 881 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slotctl); 882 /* make sure to assert LV card support bits */ 883 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 884 0x800 + 0x3e, 885 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 886 0x800 + 0x3e) | 0x03); 887 break; 888 } 889 890 /* Close all memory and I/O windows. */ 891 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 892 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 893 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 894 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 895 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 896 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 897 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 898 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 899 900 /* reset 16-bit pcmcia bus */ 901 bus_space_write_1(bmt, bmh, 0x800 + PCIC_INTR, 902 bus_space_read_1(bmt, bmh, 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 903 904 /* turn off power */ 905 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 906 907 /* CSC Interrupt: Card detect and power cycle interrupts on */ 908 sockmask = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 909 sockmask |= CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; 910 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, sockmask); 911 /* reset interrupt */ 912 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 913 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 914 } 915 916 917 918 919 /* 920 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 921 * struct pcmciabus_attach_args *paa) 922 * 923 * This function attaches 16-bit PCcard bus. 924 */ 925 STATIC void 926 pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 927 struct pcmciabus_attach_args *paa) 928 { 929 struct pcic_handle *ph = &sc->sc_pcmcia_h; 930 #if rbus 931 rbus_tag_t rb; 932 #endif 933 934 /* initialize pcmcia part in pccbb_softc */ 935 ph->ph_parent = (struct device *)sc; 936 ph->sock = sc->sc_function; 937 ph->flags = 0; 938 ph->shutdown = 0; 939 ph->ih_irq = sc->sc_pa.pa_intrline; 940 ph->ph_bus_t = sc->sc_base_memt; 941 ph->ph_bus_h = sc->sc_base_memh; 942 ph->ph_read = pccbb_pcmcia_read; 943 ph->ph_write = pccbb_pcmcia_write; 944 sc->sc_pct = &pccbb_pcmcia_funcs; 945 946 /* 947 * We need to do a few things here: 948 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 949 * setting the IRQ numbers to 0. 950 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 951 * routing of CSC interrupts (e.g. card removal) to PCI while in 952 * PCMCIA mode. We just leave this set all the time. 953 * 3) Enable card insertion/removal interrupts in case the chip also 954 * needs that while in PCMCIA mode. 955 * 4) Clear any pending CSC interrupt. 956 */ 957 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE); 958 if (sc->sc_chipset == CB_TI113X) { 959 Pcic_write(ph, PCIC_CSC_INTR, 0); 960 } else { 961 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 962 Pcic_read(ph, PCIC_CSC); 963 } 964 965 /* initialize pcmcia bus attachment */ 966 paa->paa_busname = "pcmcia"; 967 paa->pct = sc->sc_pct; 968 paa->pch = ph; 969 paa->iobase = 0; /* I don't use them */ 970 paa->iosize = 0; 971 #if rbus 972 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 973 paa->iobase = rb->rb_start + rb->rb_offset; 974 paa->iosize = rb->rb_end - rb->rb_start; 975 #endif 976 977 return; 978 } 979 980 #if 0 981 STATIC void 982 pccbb_pcmcia_attach_card(struct pcic_handle *ph) 983 { 984 if (ph->flags & PCIC_FLAG_CARDP) { 985 panic("pccbb_pcmcia_attach_card: already attached"); 986 } 987 988 /* call the MI attach function */ 989 pcmcia_card_attach(ph->pcmcia); 990 991 ph->flags |= PCIC_FLAG_CARDP; 992 } 993 994 STATIC void 995 pccbb_pcmcia_detach_card(struct pcic_handle *ph, int flags) 996 { 997 if (!(ph->flags & PCIC_FLAG_CARDP)) { 998 panic("pccbb_pcmcia_detach_card: already detached"); 999 } 1000 1001 ph->flags &= ~PCIC_FLAG_CARDP; 1002 1003 /* call the MI detach function */ 1004 pcmcia_card_detach(ph->pcmcia, flags); 1005 } 1006 #endif 1007 1008 /* 1009 * int pccbbintr(arg) 1010 * void *arg; 1011 * This routine handles the interrupt from Yenta PCI-CardBus bridge 1012 * itself. 1013 */ 1014 int 1015 pccbbintr(void *arg) 1016 { 1017 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1018 u_int32_t sockevent, sockstate; 1019 bus_space_tag_t memt = sc->sc_base_memt; 1020 bus_space_handle_t memh = sc->sc_base_memh; 1021 struct pcic_handle *ph = &sc->sc_pcmcia_h; 1022 1023 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 1024 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 1025 Pcic_read(ph, PCIC_CSC); 1026 1027 if (sockevent == 0) { 1028 /* This intr is not for me: it may be for my child devices. */ 1029 if (sc->sc_pil_intr_enable) { 1030 return pccbbintr_function(sc); 1031 } else { 1032 return 0; 1033 } 1034 } 1035 1036 aprint_debug("%s: enter sockevent %" PRIx32 "\n", __func__, sockevent); 1037 1038 if (sockevent & CB_SOCKET_EVENT_CD) { 1039 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1040 if (0x00 != (sockstate & CB_SOCKET_STAT_CD)) { 1041 /* A card should be removed. */ 1042 if (sc->sc_flags & CBB_CARDEXIST) { 1043 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 1044 sockevent)); 1045 DPRINTF((" card removed, 0x%08x\n", sockstate)); 1046 sc->sc_flags &= ~CBB_CARDEXIST; 1047 if (sc->sc_csc->sc_status & 1048 CARDSLOT_STATUS_CARD_16) { 1049 #if 0 1050 struct pcic_handle *ph = 1051 &sc->sc_pcmcia_h; 1052 1053 pcmcia_card_deactivate(ph->pcmcia); 1054 pccbb_pcmcia_socket_disable(ph); 1055 pccbb_pcmcia_detach_card(ph, 1056 DETACH_FORCE); 1057 #endif 1058 cardslot_event_throw(sc->sc_csc, 1059 CARDSLOT_EVENT_REMOVAL_16); 1060 } else if (sc->sc_csc->sc_status & 1061 CARDSLOT_STATUS_CARD_CB) { 1062 /* Cardbus intr removed */ 1063 cardslot_event_throw(sc->sc_csc, 1064 CARDSLOT_EVENT_REMOVAL_CB); 1065 } 1066 } else if (sc->sc_flags & CBB_INSERTING) { 1067 sc->sc_flags &= ~CBB_INSERTING; 1068 callout_stop(&sc->sc_insert_ch); 1069 } 1070 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 1071 /* 1072 * The pccbbintr may called from powerdown hook when 1073 * the system resumed, to detect the card 1074 * insertion/removal during suspension. 1075 */ 1076 (sc->sc_flags & CBB_CARDEXIST) == 0) { 1077 if (sc->sc_flags & CBB_INSERTING) { 1078 callout_stop(&sc->sc_insert_ch); 1079 } 1080 callout_reset(&sc->sc_insert_ch, hz / 5, 1081 pci113x_insert, sc); 1082 sc->sc_flags |= CBB_INSERTING; 1083 } 1084 } 1085 1086 if (sockevent & CB_SOCKET_EVENT_POWER) { 1087 DPRINTF(("Powercycling because of socket event\n")); 1088 /* XXX: Does not happen when attaching a 16-bit card */ 1089 sc->sc_pwrcycle++; 1090 wakeup(&sc->sc_pwrcycle); 1091 } 1092 1093 return (1); 1094 } 1095 1096 /* 1097 * static int pccbbintr_function(struct pccbb_softc *sc) 1098 * 1099 * This function calls each interrupt handler registered at the 1100 * bridge. The interrupt handlers are called in registered order. 1101 */ 1102 static int 1103 pccbbintr_function(struct pccbb_softc *sc) 1104 { 1105 int retval = 0, val; 1106 struct pccbb_intrhand_list *pil; 1107 int s; 1108 1109 for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1110 pil = LIST_NEXT(pil, pil_next)) { 1111 s = splraiseipl(pil->pil_icookie); 1112 val = (*pil->pil_func)(pil->pil_arg); 1113 splx(s); 1114 1115 retval = retval == 1 ? 1 : 1116 retval == 0 ? val : val != 0 ? val : retval; 1117 } 1118 1119 return retval; 1120 } 1121 1122 static void 1123 pci113x_insert(void *arg) 1124 { 1125 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1126 u_int32_t sockevent, sockstate; 1127 1128 if (!(sc->sc_flags & CBB_INSERTING)) { 1129 /* We add a card only under inserting state. */ 1130 return; 1131 } 1132 sc->sc_flags &= ~CBB_INSERTING; 1133 1134 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1135 CB_SOCKET_EVENT); 1136 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1137 CB_SOCKET_STAT); 1138 1139 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1140 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1141 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1142 sc->sc_flags |= CBB_CARDEXIST; 1143 /* call pccard interrupt handler here */ 1144 if (sockstate & CB_SOCKET_STAT_16BIT) { 1145 /* 16-bit card found */ 1146 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1147 cardslot_event_throw(sc->sc_csc, 1148 CARDSLOT_EVENT_INSERTION_16); 1149 } else if (sockstate & CB_SOCKET_STAT_CB) { 1150 /* cardbus card found */ 1151 /* cardbus_attach_card(sc->sc_csc); */ 1152 cardslot_event_throw(sc->sc_csc, 1153 CARDSLOT_EVENT_INSERTION_CB); 1154 } else { 1155 /* who are you? */ 1156 } 1157 } else { 1158 callout_reset(&sc->sc_insert_ch, hz / 10, 1159 pci113x_insert, sc); 1160 } 1161 } 1162 1163 #define PCCBB_PCMCIA_OFFSET 0x800 1164 static u_int8_t 1165 pccbb_pcmcia_read(struct pcic_handle *ph, int reg) 1166 { 1167 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1168 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1169 1170 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1171 PCCBB_PCMCIA_OFFSET + reg); 1172 } 1173 1174 static void 1175 pccbb_pcmcia_write(struct pcic_handle *ph, int reg, u_int8_t val) 1176 { 1177 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1178 val); 1179 1180 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1181 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1182 } 1183 1184 /* 1185 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1186 */ 1187 STATIC int 1188 pccbb_ctrl(cardbus_chipset_tag_t ct, int command) 1189 { 1190 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1191 1192 switch (command) { 1193 case CARDBUS_CD: 1194 if (2 == pccbb_detect_card(sc)) { 1195 int retval = 0; 1196 int status = cb_detect_voltage(sc); 1197 if (PCCARD_VCC_5V & status) { 1198 retval |= CARDBUS_5V_CARD; 1199 } 1200 if (PCCARD_VCC_3V & status) { 1201 retval |= CARDBUS_3V_CARD; 1202 } 1203 if (PCCARD_VCC_XV & status) { 1204 retval |= CARDBUS_XV_CARD; 1205 } 1206 if (PCCARD_VCC_YV & status) { 1207 retval |= CARDBUS_YV_CARD; 1208 } 1209 return retval; 1210 } else { 1211 return 0; 1212 } 1213 case CARDBUS_RESET: 1214 return cb_reset(sc); 1215 case CARDBUS_IO_ENABLE: /* fallthrough */ 1216 case CARDBUS_IO_DISABLE: /* fallthrough */ 1217 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1218 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1219 case CARDBUS_BM_ENABLE: /* fallthrough */ 1220 case CARDBUS_BM_DISABLE: /* fallthrough */ 1221 /* XXX: I think we don't need to call this function below. */ 1222 return pccbb_cardenable(sc, command); 1223 } 1224 1225 return 0; 1226 } 1227 1228 /* 1229 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1230 * This function returns true when it succeeds and returns false when 1231 * it fails. 1232 */ 1233 STATIC int 1234 pccbb_power(cardbus_chipset_tag_t ct, int command) 1235 { 1236 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1237 u_int32_t status, osock_ctrl, sock_ctrl, reg_ctrl; 1238 bus_space_tag_t memt = sc->sc_base_memt; 1239 bus_space_handle_t memh = sc->sc_base_memh; 1240 int on = 0, pwrcycle, s, times; 1241 struct timeval before, after, diff; 1242 1243 DPRINTF(("pccbb_power: %s and %s [0x%x]\n", 1244 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1245 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1246 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1247 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1248 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1249 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1250 "UNKNOWN", 1251 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1252 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1253 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1254 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1255 "UNKNOWN", command)); 1256 1257 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1258 osock_ctrl = sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1259 1260 switch (command & CARDBUS_VCCMASK) { 1261 case CARDBUS_VCC_UC: 1262 break; 1263 case CARDBUS_VCC_5V: 1264 on++; 1265 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1266 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1267 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1268 } else { 1269 printf("%s: BAD voltage request: no 5 V card\n", 1270 sc->sc_dev.dv_xname); 1271 return 0; 1272 } 1273 break; 1274 case CARDBUS_VCC_3V: 1275 on++; 1276 if (CB_SOCKET_STAT_3VCARD & status) { 1277 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1278 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1279 } else { 1280 printf("%s: BAD voltage request: no 3.3 V card\n", 1281 sc->sc_dev.dv_xname); 1282 return 0; 1283 } 1284 break; 1285 case CARDBUS_VCC_0V: 1286 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1287 break; 1288 default: 1289 return 0; /* power NEVER changed */ 1290 } 1291 1292 switch (command & CARDBUS_VPPMASK) { 1293 case CARDBUS_VPP_UC: 1294 break; 1295 case CARDBUS_VPP_0V: 1296 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1297 break; 1298 case CARDBUS_VPP_VCC: 1299 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1300 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1301 break; 1302 case CARDBUS_VPP_12V: 1303 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1304 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1305 break; 1306 } 1307 1308 pwrcycle = sc->sc_pwrcycle; 1309 aprint_debug("%s: osock_ctrl %#" PRIx32 " sock_ctrl %#" PRIx32 "\n", 1310 device_xname(&sc->sc_dev), osock_ctrl, sock_ctrl); 1311 1312 microtime(&before); 1313 s = splbio(); 1314 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1315 1316 /* 1317 * Wait as long as 200ms for a power-cycle interrupt. If 1318 * interrupts are enabled, but the socket has already 1319 * changed to the desired status, keep waiting for the 1320 * interrupt. "Consuming" the interrupt in this way keeps 1321 * the interrupt from prematurely waking some subsequent 1322 * pccbb_power call. 1323 * 1324 * XXX Not every bridge interrupts on the ->OFF transition. 1325 * XXX That's ok, we will time-out after 200ms. 1326 * 1327 * XXX The power cycle event will never happen when attaching 1328 * XXX a 16-bit card. That's ok, we will time-out after 1329 * XXX 200ms. 1330 */ 1331 for (times = 5; --times >= 0; ) { 1332 if (cold) 1333 DELAY(40 * 1000); 1334 else { 1335 (void)tsleep(&sc->sc_pwrcycle, PWAIT, "pccpwr", 1336 hz / 25); 1337 if (pwrcycle == sc->sc_pwrcycle) 1338 continue; 1339 } 1340 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1341 if ((status & CB_SOCKET_STAT_PWRCYCLE) != 0 && on) 1342 break; 1343 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0 && !on) 1344 break; 1345 } 1346 splx(s); 1347 microtime(&after); 1348 timersub(&after, &before, &diff); 1349 aprint_debug("%s: wait took%s %ld.%06lds\n", sc->sc_dev.dv_xname, 1350 (on && times < 0) ? " too long" : "", diff.tv_sec, diff.tv_usec); 1351 1352 /* 1353 * Ok, wait a bit longer for things to settle. 1354 */ 1355 if (on && sc->sc_chipset == CB_TOPIC95B) 1356 delay_ms(100, sc); 1357 1358 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1359 1360 if (on && sc->sc_chipset != CB_TOPIC95B) { 1361 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0) 1362 printf("%s: power on failed?\n", sc->sc_dev.dv_xname); 1363 } 1364 1365 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1366 printf("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1367 sc->sc_dev.dv_xname, sock_ctrl, status); 1368 printf("%s: disabling socket\n", sc->sc_dev.dv_xname); 1369 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1370 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1371 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1372 status &= ~CB_SOCKET_STAT_BADVCC; 1373 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, status); 1374 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1375 CB_SOCKET_STAT)); 1376 return 0; 1377 } 1378 1379 if (sc->sc_chipset == CB_TOPIC97) { 1380 reg_ctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL); 1381 reg_ctrl &= ~TOPIC97_REG_CTRL_TESTMODE; 1382 if ((command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V) 1383 reg_ctrl &= ~TOPIC97_REG_CTRL_CLKRUN_ENA; 1384 else 1385 reg_ctrl |= TOPIC97_REG_CTRL_CLKRUN_ENA; 1386 pci_conf_write(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL, reg_ctrl); 1387 } 1388 1389 return 1; /* power changed correctly */ 1390 } 1391 1392 #if defined CB_PCMCIA_POLL 1393 struct cb_poll_str { 1394 void *arg; 1395 int (*func)(void *); 1396 int level; 1397 pccard_chipset_tag_t ct; 1398 int count; 1399 struct callout poll_ch; 1400 }; 1401 1402 static struct cb_poll_str cb_poll[10]; 1403 static int cb_poll_n = 0; 1404 1405 static void cb_pcmcia_poll(void *arg); 1406 1407 static void 1408 cb_pcmcia_poll(void *arg) 1409 { 1410 struct cb_poll_str *poll = arg; 1411 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1412 struct pccbb_softc *sc = psc->cpc_parent; 1413 int s; 1414 u_int32_t spsr; /* socket present-state reg */ 1415 1416 callout_reset(&poll->poll_ch, hz / 10, cb_pcmcia_poll, poll); 1417 switch (poll->level) { 1418 case IPL_NET: 1419 s = splnet(); 1420 break; 1421 case IPL_BIO: 1422 s = splbio(); 1423 break; 1424 case IPL_TTY: /* fallthrough */ 1425 default: 1426 s = spltty(); 1427 break; 1428 } 1429 1430 spsr = 1431 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1432 CB_SOCKET_STAT); 1433 1434 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1435 if (!(spsr & 0x40)) { /* CINT low */ 1436 #else 1437 if (1) { 1438 #endif 1439 if ((*poll->func) (poll->arg) == 1) { 1440 ++poll->count; 1441 printf("intr: reported from poller, 0x%x\n", spsr); 1442 #if defined LEVEL2 1443 } else { 1444 printf("intr: miss! 0x%x\n", spsr); 1445 #endif 1446 } 1447 } 1448 splx(s); 1449 } 1450 #endif /* defined CB_PCMCIA_POLL */ 1451 1452 /* 1453 * static int pccbb_detect_card(struct pccbb_softc *sc) 1454 * return value: 0 if no card exists. 1455 * 1 if 16-bit card exists. 1456 * 2 if cardbus card exists. 1457 */ 1458 static int 1459 pccbb_detect_card(struct pccbb_softc *sc) 1460 { 1461 bus_space_handle_t base_memh = sc->sc_base_memh; 1462 bus_space_tag_t base_memt = sc->sc_base_memt; 1463 u_int32_t sockstat = 1464 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1465 int retval = 0; 1466 1467 /* CD1 and CD2 asserted */ 1468 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1469 /* card must be present */ 1470 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1471 /* NOTACARD DEASSERTED */ 1472 if (CB_SOCKET_STAT_CB & sockstat) { 1473 /* CardBus mode */ 1474 retval = 2; 1475 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1476 /* 16-bit mode */ 1477 retval = 1; 1478 } 1479 } 1480 } 1481 return retval; 1482 } 1483 1484 /* 1485 * STATIC int cb_reset(struct pccbb_softc *sc) 1486 * This function resets CardBus card. 1487 */ 1488 STATIC int 1489 cb_reset(struct pccbb_softc *sc) 1490 { 1491 /* 1492 * Reset Assert at least 20 ms 1493 * Some machines request longer duration. 1494 */ 1495 int reset_duration = 1496 (sc->sc_chipset == CB_RX5C47X ? 400 : 50); 1497 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1498 1499 /* Reset bit Assert (bit 6 at 0x3E) */ 1500 bcr |= CB_BCR_RESET_ENABLE; 1501 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr); 1502 delay_ms(reset_duration, sc); 1503 1504 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1505 /* Reset bit Deassert (bit 6 at 0x3E) */ 1506 bcr &= ~CB_BCR_RESET_ENABLE; 1507 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr); 1508 delay_ms(reset_duration, sc); 1509 } 1510 /* No card found on the slot. Keep Reset. */ 1511 return 1; 1512 } 1513 1514 /* 1515 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1516 * This function detect card Voltage. 1517 */ 1518 STATIC int 1519 cb_detect_voltage(struct pccbb_softc *sc) 1520 { 1521 u_int32_t psr; /* socket present-state reg */ 1522 bus_space_tag_t iot = sc->sc_base_memt; 1523 bus_space_handle_t ioh = sc->sc_base_memh; 1524 int vol = PCCARD_VCC_UKN; /* set 0 */ 1525 1526 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1527 1528 if (0x400u & psr) { 1529 vol |= PCCARD_VCC_5V; 1530 } 1531 if (0x800u & psr) { 1532 vol |= PCCARD_VCC_3V; 1533 } 1534 1535 return vol; 1536 } 1537 1538 STATIC int 1539 cbbprint(void *aux, const char *pcic) 1540 { 1541 #if 0 1542 struct cbslot_attach_args *cba = aux; 1543 1544 if (cba->cba_slot >= 0) { 1545 aprint_normal(" slot %d", cba->cba_slot); 1546 } 1547 #endif 1548 return UNCONF; 1549 } 1550 1551 /* 1552 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1553 * This function enables and disables the card 1554 */ 1555 STATIC int 1556 pccbb_cardenable(struct pccbb_softc *sc, int function) 1557 { 1558 u_int32_t command = 1559 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1560 1561 DPRINTF(("pccbb_cardenable:")); 1562 switch (function) { 1563 case CARDBUS_IO_ENABLE: 1564 command |= PCI_COMMAND_IO_ENABLE; 1565 break; 1566 case CARDBUS_IO_DISABLE: 1567 command &= ~PCI_COMMAND_IO_ENABLE; 1568 break; 1569 case CARDBUS_MEM_ENABLE: 1570 command |= PCI_COMMAND_MEM_ENABLE; 1571 break; 1572 case CARDBUS_MEM_DISABLE: 1573 command &= ~PCI_COMMAND_MEM_ENABLE; 1574 break; 1575 case CARDBUS_BM_ENABLE: 1576 command |= PCI_COMMAND_MASTER_ENABLE; 1577 break; 1578 case CARDBUS_BM_DISABLE: 1579 command &= ~PCI_COMMAND_MASTER_ENABLE; 1580 break; 1581 default: 1582 return 0; 1583 } 1584 1585 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1586 DPRINTF((" command reg 0x%x\n", command)); 1587 return 1; 1588 } 1589 1590 #if !rbus 1591 static int 1592 pccbb_io_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 1593 { 1594 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1595 int basereg; 1596 int limitreg; 1597 1598 if ((win < 0) || (win > 2)) { 1599 #if defined DIAGNOSTIC 1600 printf("cardbus_io_open: window out of range %d\n", win); 1601 #endif 1602 return 0; 1603 } 1604 1605 basereg = win * 8 + 0x2c; 1606 limitreg = win * 8 + 0x30; 1607 1608 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1609 start, basereg, end, limitreg)); 1610 1611 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1612 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1613 return 1; 1614 } 1615 1616 /* 1617 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1618 */ 1619 static int 1620 pccbb_io_close(cardbus_chipset_tag_t ct, int win) 1621 { 1622 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1623 int basereg; 1624 int limitreg; 1625 1626 if ((win < 0) || (win > 2)) { 1627 #if defined DIAGNOSTIC 1628 printf("cardbus_io_close: window out of range %d\n", win); 1629 #endif 1630 return 0; 1631 } 1632 1633 basereg = win * 8 + 0x2c; 1634 limitreg = win * 8 + 0x30; 1635 1636 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1637 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1638 return 1; 1639 } 1640 1641 static int 1642 pccbb_mem_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 1643 { 1644 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1645 int basereg; 1646 int limitreg; 1647 1648 if ((win < 0) || (win > 2)) { 1649 #if defined DIAGNOSTIC 1650 printf("cardbus_mem_open: window out of range %d\n", win); 1651 #endif 1652 return 0; 1653 } 1654 1655 basereg = win * 8 + 0x1c; 1656 limitreg = win * 8 + 0x20; 1657 1658 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1659 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1660 return 1; 1661 } 1662 1663 static int 1664 pccbb_mem_close(cardbus_chipset_tag_t ct, int win) 1665 { 1666 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1667 int basereg; 1668 int limitreg; 1669 1670 if ((win < 0) || (win > 2)) { 1671 #if defined DIAGNOSTIC 1672 printf("cardbus_mem_close: window out of range %d\n", win); 1673 #endif 1674 return 0; 1675 } 1676 1677 basereg = win * 8 + 0x1c; 1678 limitreg = win * 8 + 0x20; 1679 1680 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1681 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1682 return 1; 1683 } 1684 #endif 1685 1686 /* 1687 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1688 * int irq, 1689 * int level, 1690 * int (* func)(void *), 1691 * void *arg) 1692 * 1693 * This function registers an interrupt handler at the bridge, in 1694 * order not to call the interrupt handlers of child devices when 1695 * a card-deletion interrupt occurs. 1696 * 1697 * The arguments irq and level are not used. 1698 */ 1699 static void * 1700 pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, int irq, int level, 1701 int (*func)(void *), void *arg) 1702 { 1703 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1704 1705 return pccbb_intr_establish(sc, irq, level, func, arg); 1706 } 1707 1708 1709 /* 1710 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1711 * void *ih) 1712 * 1713 * This function removes an interrupt handler pointed by ih. 1714 */ 1715 static void 1716 pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih) 1717 { 1718 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1719 1720 pccbb_intr_disestablish(sc, ih); 1721 } 1722 1723 1724 void 1725 pccbb_intr_route(struct pccbb_softc *sc) 1726 { 1727 pcireg_t bcr, cbctrl; 1728 1729 /* initialize bridge intr routing */ 1730 bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1731 bcr &= ~CB_BCR_INTR_IREQ_ENABLE; 1732 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr); 1733 1734 switch (sc->sc_chipset) { 1735 case CB_TI113X: 1736 cbctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1737 /* functional intr enabled */ 1738 cbctrl |= PCI113X_CBCTRL_PCI_INTR; 1739 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, cbctrl); 1740 break; 1741 default: 1742 break; 1743 } 1744 } 1745 1746 /* 1747 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1748 * int irq, 1749 * int level, 1750 * int (* func)(void *), 1751 * void *arg) 1752 * 1753 * This function registers an interrupt handler at the bridge, in 1754 * order not to call the interrupt handlers of child devices when 1755 * a card-deletion interrupt occurs. 1756 * 1757 * The arguments irq is not used because pccbb selects intr vector. 1758 */ 1759 static void * 1760 pccbb_intr_establish(struct pccbb_softc *sc, int irq, int level, 1761 int (*func)(void *), void *arg) 1762 { 1763 struct pccbb_intrhand_list *pil, *newpil; 1764 1765 DPRINTF(("pccbb_intr_establish start. %p\n", LIST_FIRST(&sc->sc_pil))); 1766 1767 if (LIST_EMPTY(&sc->sc_pil)) { 1768 pccbb_intr_route(sc); 1769 } 1770 1771 /* 1772 * Allocate a room for interrupt handler structure. 1773 */ 1774 if (NULL == (newpil = 1775 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1776 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1777 return NULL; 1778 } 1779 1780 newpil->pil_func = func; 1781 newpil->pil_arg = arg; 1782 newpil->pil_icookie = makeiplcookie(level); 1783 1784 if (LIST_EMPTY(&sc->sc_pil)) { 1785 LIST_INSERT_HEAD(&sc->sc_pil, newpil, pil_next); 1786 } else { 1787 for (pil = LIST_FIRST(&sc->sc_pil); 1788 LIST_NEXT(pil, pil_next) != NULL; 1789 pil = LIST_NEXT(pil, pil_next)); 1790 LIST_INSERT_AFTER(pil, newpil, pil_next); 1791 } 1792 1793 DPRINTF(("pccbb_intr_establish add pil. %p\n", 1794 LIST_FIRST(&sc->sc_pil))); 1795 1796 return newpil; 1797 } 1798 1799 /* 1800 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1801 * void *ih) 1802 * 1803 * This function removes an interrupt handler pointed by ih. ih 1804 * should be the value returned by cardbus_intr_establish() or 1805 * NULL. 1806 * 1807 * When ih is NULL, this function will do nothing. 1808 */ 1809 static void 1810 pccbb_intr_disestablish(struct pccbb_softc *sc, void *ih) 1811 { 1812 struct pccbb_intrhand_list *pil; 1813 pcireg_t reg; 1814 1815 DPRINTF(("pccbb_intr_disestablish start. %p\n", 1816 LIST_FIRST(&sc->sc_pil))); 1817 1818 if (ih == NULL) { 1819 /* intr handler is not set */ 1820 DPRINTF(("pccbb_intr_disestablish: no ih\n")); 1821 return; 1822 } 1823 1824 #ifdef DIAGNOSTIC 1825 for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1826 pil = LIST_NEXT(pil, pil_next)) { 1827 DPRINTF(("pccbb_intr_disestablish: pil %p\n", pil)); 1828 if (pil == ih) { 1829 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1830 break; 1831 } 1832 } 1833 if (pil == NULL) { 1834 panic("pccbb_intr_disestablish: %s cannot find pil %p", 1835 sc->sc_dev.dv_xname, ih); 1836 } 1837 #endif 1838 1839 pil = (struct pccbb_intrhand_list *)ih; 1840 LIST_REMOVE(pil, pil_next); 1841 free(pil, M_DEVBUF); 1842 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1843 1844 if (LIST_EMPTY(&sc->sc_pil)) { 1845 /* No interrupt handlers */ 1846 1847 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1848 1849 /* stop routing PCI intr */ 1850 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1851 reg |= CB_BCR_INTR_IREQ_ENABLE; 1852 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, reg); 1853 1854 switch (sc->sc_chipset) { 1855 case CB_TI113X: 1856 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1857 /* functional intr disabled */ 1858 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1859 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1860 break; 1861 default: 1862 break; 1863 } 1864 } 1865 } 1866 1867 #if defined SHOW_REGS 1868 static void 1869 cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, bus_space_tag_t memt, 1870 bus_space_handle_t memh) 1871 { 1872 int i; 1873 printf("PCI config regs:"); 1874 for (i = 0; i < 0x50; i += 4) { 1875 if (i % 16 == 0) 1876 printf("\n 0x%02x:", i); 1877 printf(" %08x", pci_conf_read(pc, tag, i)); 1878 } 1879 for (i = 0x80; i < 0xb0; i += 4) { 1880 if (i % 16 == 0) 1881 printf("\n 0x%02x:", i); 1882 printf(" %08x", pci_conf_read(pc, tag, i)); 1883 } 1884 1885 if (memh == 0) { 1886 printf("\n"); 1887 return; 1888 } 1889 1890 printf("\nsocket regs:"); 1891 for (i = 0; i <= 0x10; i += 0x04) 1892 printf(" %08x", bus_space_read_4(memt, memh, i)); 1893 printf("\nExCA regs:"); 1894 for (i = 0; i < 0x08; ++i) 1895 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1896 printf("\n"); 1897 return; 1898 } 1899 #endif 1900 1901 /* 1902 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1903 * int busno, int function) 1904 * This is the function to make a tag to access config space of 1905 * a CardBus Card. It works same as pci_conf_read. 1906 */ 1907 static cardbustag_t 1908 pccbb_make_tag(cardbus_chipset_tag_t cc, int busno, int function) 1909 { 1910 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1911 1912 return pci_make_tag(sc->sc_pc, busno, 0, function); 1913 } 1914 1915 static void 1916 pccbb_free_tag(cardbus_chipset_tag_t cc, cardbustag_t tag) 1917 { 1918 } 1919 1920 /* 1921 * pccbb_conf_read 1922 * 1923 * This is the function to read the config space of a CardBus card. 1924 * It works the same as pci_conf_read(9). 1925 */ 1926 static cardbusreg_t 1927 pccbb_conf_read(cardbus_chipset_tag_t cc, cardbustag_t tag, int offset) 1928 { 1929 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1930 1931 return pci_conf_read(sc->sc_pc, tag, offset); 1932 } 1933 1934 /* 1935 * pccbb_conf_write 1936 * 1937 * This is the function to write the config space of a CardBus 1938 * card. It works the same as pci_conf_write(9). 1939 */ 1940 static void 1941 pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, int reg, 1942 cardbusreg_t val) 1943 { 1944 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1945 1946 pci_conf_write(sc->sc_pc, tag, reg, val); 1947 } 1948 1949 #if 0 1950 STATIC int 1951 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1952 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 1953 int speed, int flags, 1954 bus_space_handle_t * iohp) 1955 #endif 1956 /* 1957 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1958 * bus_addr_t start, bus_size_t size, 1959 * bus_size_t align, 1960 * struct pcmcia_io_handle *pcihp 1961 * 1962 * This function only allocates I/O region for pccard. This function 1963 * never maps the allocated region to pccard I/O area. 1964 * 1965 * XXX: The interface of this function is not very good, I believe. 1966 */ 1967 STATIC int 1968 pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, 1969 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 1970 { 1971 struct pcic_handle *ph = (struct pcic_handle *)pch; 1972 bus_addr_t ioaddr; 1973 int flags = 0; 1974 bus_space_tag_t iot; 1975 bus_space_handle_t ioh; 1976 bus_addr_t mask; 1977 #if rbus 1978 rbus_tag_t rb; 1979 #endif 1980 if (align == 0) { 1981 align = size; /* XXX: funny??? */ 1982 } 1983 1984 if (start != 0) { 1985 /* XXX: assume all card decode lower 10 bits by its hardware */ 1986 mask = 0x3ff; 1987 /* enforce to use only masked address */ 1988 start &= mask; 1989 } else { 1990 /* 1991 * calculate mask: 1992 * 1. get the most significant bit of size (call it msb). 1993 * 2. compare msb with the value of size. 1994 * 3. if size is larger, shift msb left once. 1995 * 4. obtain mask value to decrement msb. 1996 */ 1997 bus_size_t size_tmp = size; 1998 int shifts = 0; 1999 2000 mask = 1; 2001 while (size_tmp) { 2002 ++shifts; 2003 size_tmp >>= 1; 2004 } 2005 mask = (1 << shifts); 2006 if (mask < size) { 2007 mask <<= 1; 2008 } 2009 --mask; 2010 } 2011 2012 /* 2013 * Allocate some arbitrary I/O space. 2014 */ 2015 2016 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 2017 2018 #if rbus 2019 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 2020 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 2021 return 1; 2022 } 2023 DPRINTF(("pccbb_pcmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2024 (u_long) ioaddr, (u_long) size)); 2025 #else 2026 if (start) { 2027 ioaddr = start; 2028 if (bus_space_map(iot, start, size, 0, &ioh)) { 2029 return 1; 2030 } 2031 DPRINTF(("pccbb_pcmcia_io_alloc map port 0x%lx+0x%lx\n", 2032 (u_long) ioaddr, (u_long) size)); 2033 } else { 2034 flags |= PCMCIA_IO_ALLOCATED; 2035 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 2036 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 2037 size, align, 0, 0, &ioaddr, &ioh)) { 2038 /* No room be able to be get. */ 2039 return 1; 2040 } 2041 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2042 (u_long) ioaddr, (u_long) size)); 2043 } 2044 #endif 2045 2046 pcihp->iot = iot; 2047 pcihp->ioh = ioh; 2048 pcihp->addr = ioaddr; 2049 pcihp->size = size; 2050 pcihp->flags = flags; 2051 2052 return 0; 2053 } 2054 2055 /* 2056 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2057 * struct pcmcia_io_handle *pcihp) 2058 * 2059 * This function only frees I/O region for pccard. 2060 * 2061 * XXX: The interface of this function is not very good, I believe. 2062 */ 2063 void 2064 pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2065 struct pcmcia_io_handle *pcihp) 2066 { 2067 #if !rbus 2068 bus_space_tag_t iot = pcihp->iot; 2069 #endif 2070 bus_space_handle_t ioh = pcihp->ioh; 2071 bus_size_t size = pcihp->size; 2072 2073 #if rbus 2074 struct pccbb_softc *sc = 2075 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 2076 rbus_tag_t rb = sc->sc_rbus_iot; 2077 2078 rbus_space_free(rb, ioh, size, NULL); 2079 #else 2080 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 2081 bus_space_free(iot, ioh, size); 2082 else 2083 bus_space_unmap(iot, ioh, size); 2084 #endif 2085 } 2086 2087 /* 2088 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 2089 * bus_addr_t offset, bus_size_t size, 2090 * struct pcmcia_io_handle *pcihp, 2091 * int *windowp) 2092 * 2093 * This function maps the allocated I/O region to pccard. This function 2094 * never allocates any I/O region for pccard I/O area. I don't 2095 * understand why the original authors of pcmciabus separated alloc and 2096 * map. I believe the two must be unite. 2097 * 2098 * XXX: no wait timing control? 2099 */ 2100 int 2101 pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, bus_addr_t offset, 2102 bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp) 2103 { 2104 struct pcic_handle *ph = (struct pcic_handle *)pch; 2105 bus_addr_t ioaddr = pcihp->addr + offset; 2106 int i, win; 2107 #if defined CBB_DEBUG 2108 static const char *width_names[] = { "dynamic", "io8", "io16" }; 2109 #endif 2110 2111 /* Sanity check I/O handle. */ 2112 2113 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 2114 panic("pccbb_pcmcia_io_map iot is bogus"); 2115 } 2116 2117 /* XXX Sanity check offset/size. */ 2118 2119 win = -1; 2120 for (i = 0; i < PCIC_IO_WINS; i++) { 2121 if ((ph->ioalloc & (1 << i)) == 0) { 2122 win = i; 2123 ph->ioalloc |= (1 << i); 2124 break; 2125 } 2126 } 2127 2128 if (win == -1) { 2129 return 1; 2130 } 2131 2132 *windowp = win; 2133 2134 /* XXX this is pretty gross */ 2135 2136 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2137 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2138 2139 /* XXX wtf is this doing here? */ 2140 2141 #if 0 2142 printf(" port 0x%lx", (u_long) ioaddr); 2143 if (size > 1) { 2144 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2145 } 2146 #endif 2147 2148 ph->io[win].addr = ioaddr; 2149 ph->io[win].size = size; 2150 ph->io[win].width = width; 2151 2152 /* actual dirty register-value changing in the function below. */ 2153 pccbb_pcmcia_do_io_map(ph, win); 2154 2155 return 0; 2156 } 2157 2158 /* 2159 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2160 * 2161 * This function changes register-value to map I/O region for pccard. 2162 */ 2163 static void 2164 pccbb_pcmcia_do_io_map(struct pcic_handle *ph, int win) 2165 { 2166 static u_int8_t pcic_iowidth[3] = { 2167 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2168 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2169 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2170 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2171 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2172 }; 2173 2174 #define PCIC_SIA_START_LOW 0 2175 #define PCIC_SIA_START_HIGH 1 2176 #define PCIC_SIA_STOP_LOW 2 2177 #define PCIC_SIA_STOP_HIGH 3 2178 2179 int regbase_win = 0x8 + win * 0x04; 2180 u_int8_t ioctl, enable; 2181 2182 DPRINTF(("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx " 2183 "width %d\n", win, (unsigned long)ph->io[win].addr, 2184 (unsigned long)ph->io[win].size, ph->io[win].width * 8)); 2185 2186 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2187 ph->io[win].addr & 0xff); 2188 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2189 (ph->io[win].addr >> 8) & 0xff); 2190 2191 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2192 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2193 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2194 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2195 2196 ioctl = Pcic_read(ph, PCIC_IOCTL); 2197 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2198 switch (win) { 2199 case 0: 2200 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2201 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2202 PCIC_IOCTL_IO0_DATASIZE_MASK); 2203 ioctl |= pcic_iowidth[ph->io[win].width]; 2204 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2205 break; 2206 case 1: 2207 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2208 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2209 PCIC_IOCTL_IO1_DATASIZE_MASK); 2210 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2211 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2212 break; 2213 } 2214 Pcic_write(ph, PCIC_IOCTL, ioctl); 2215 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2216 #if defined(CBB_DEBUG) 2217 { 2218 u_int8_t start_low = 2219 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2220 u_int8_t start_high = 2221 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2222 u_int8_t stop_low = 2223 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2224 u_int8_t stop_high = 2225 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2226 printf("pccbb_pcmcia_do_io_map start %02x %02x, " 2227 "stop %02x %02x, ioctl %02x enable %02x\n", 2228 start_low, start_high, stop_low, stop_high, ioctl, enable); 2229 } 2230 #endif 2231 } 2232 2233 /* 2234 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2235 * 2236 * This function unmaps I/O region. No return value. 2237 */ 2238 STATIC void 2239 pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t pch, int win) 2240 { 2241 struct pcic_handle *ph = (struct pcic_handle *)pch; 2242 int reg; 2243 2244 if (win >= PCIC_IO_WINS || win < 0) { 2245 panic("pccbb_pcmcia_io_unmap: window out of range"); 2246 } 2247 2248 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2249 switch (win) { 2250 case 0: 2251 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2252 break; 2253 case 1: 2254 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2255 break; 2256 } 2257 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2258 2259 ph->ioalloc &= ~(1 << win); 2260 } 2261 2262 static int 2263 pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 2264 { 2265 u_int8_t stat; 2266 int i; 2267 2268 /* wait an initial 10ms for quick cards */ 2269 stat = Pcic_read(ph, PCIC_IF_STATUS); 2270 if (stat & PCIC_IF_STATUS_READY) 2271 return (0); 2272 pccbb_pcmcia_delay(ph, 10, "pccwr0"); 2273 for (i = 0; i < 50; i++) { 2274 stat = Pcic_read(ph, PCIC_IF_STATUS); 2275 if (stat & PCIC_IF_STATUS_READY) 2276 return (0); 2277 if ((stat & PCIC_IF_STATUS_CARDDETECT_MASK) != 2278 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2279 return (ENXIO); 2280 /* wait .1s (100ms) each iteration now */ 2281 pccbb_pcmcia_delay(ph, 100, "pccwr1"); 2282 } 2283 2284 printf("pccbb_pcmcia_wait_ready: ready never happened, status=%02x\n", stat); 2285 return (EWOULDBLOCK); 2286 } 2287 2288 /* 2289 * Perform long (msec order) delay. timo is in milliseconds. 2290 */ 2291 static void 2292 pccbb_pcmcia_delay(struct pcic_handle *ph, int timo, const char *wmesg) 2293 { 2294 #ifdef DIAGNOSTIC 2295 if (timo <= 0) 2296 panic("pccbb_pcmcia_delay: called with timeout %d", timo); 2297 if (!curlwp) 2298 panic("pccbb_pcmcia_delay: called in interrupt context"); 2299 #if 0 2300 if (!ph->event_thread) 2301 panic("pccbb_pcmcia_delay: no event thread"); 2302 #endif 2303 #endif 2304 DPRINTF(("pccbb_pcmcia_delay: \"%s\" %p, sleep %d ms\n", 2305 wmesg, ph->event_thread, timo)); 2306 tsleep(pccbb_pcmcia_delay, PWAIT, wmesg, roundup(timo * hz, 1000) / 1000); 2307 } 2308 2309 /* 2310 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2311 * 2312 * This function enables the card. All information is stored in 2313 * the first argument, pcmcia_chipset_handle_t. 2314 */ 2315 STATIC void 2316 pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2317 { 2318 struct pcic_handle *ph = (struct pcic_handle *)pch; 2319 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2320 pcireg_t spsr; 2321 int voltage; 2322 int win; 2323 u_int8_t power, intr; 2324 #ifdef DIAGNOSTIC 2325 int reg; 2326 #endif 2327 2328 /* this bit is mostly stolen from pcic_attach_card */ 2329 2330 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2331 2332 /* get card Vcc info */ 2333 spsr = 2334 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2335 CB_SOCKET_STAT); 2336 if (spsr & CB_SOCKET_STAT_5VCARD) { 2337 DPRINTF(("5V card\n")); 2338 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2339 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2340 DPRINTF(("3V card\n")); 2341 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2342 } else { 2343 DPRINTF(("?V card, 0x%x\n", spsr)); /* XXX */ 2344 return; 2345 } 2346 2347 /* disable interrupts; assert RESET */ 2348 intr = Pcic_read(ph, PCIC_INTR); 2349 intr &= PCIC_INTR_ENABLE; 2350 Pcic_write(ph, PCIC_INTR, intr); 2351 2352 /* zero out the address windows */ 2353 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2354 2355 /* power down the socket to reset it, clear the card reset pin */ 2356 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2357 2358 /* power off; assert output enable bit */ 2359 power = PCIC_PWRCTL_OE; 2360 Pcic_write(ph, PCIC_PWRCTL, power); 2361 2362 /* power up the socket */ 2363 if (pccbb_power(sc, voltage) == 0) 2364 return; 2365 2366 /* 2367 * Table 4-18 and figure 4-6 of the PC Card specifiction say: 2368 * Vcc Rising Time (Tpr) = 100ms (handled in pccbb_power() above) 2369 * RESET Width (Th (Hi-z RESET)) = 1ms 2370 * RESET Width (Tw (RESET)) = 10us 2371 * 2372 * some machines require some more time to be settled 2373 * for example old toshiba topic bridges! 2374 * (100ms is added here). 2375 */ 2376 pccbb_pcmcia_delay(ph, 200 + 1, "pccen1"); 2377 2378 /* negate RESET */ 2379 intr |= PCIC_INTR_RESET; 2380 Pcic_write(ph, PCIC_INTR, intr); 2381 2382 /* 2383 * RESET Setup Time (Tsu (RESET)) = 20ms 2384 */ 2385 pccbb_pcmcia_delay(ph, 20, "pccen2"); 2386 2387 #ifdef DIAGNOSTIC 2388 reg = Pcic_read(ph, PCIC_IF_STATUS); 2389 if ((reg & PCIC_IF_STATUS_POWERACTIVE) == 0) 2390 printf("pccbb_pcmcia_socket_enable: no power, status=%x\n", reg); 2391 #endif 2392 2393 /* wait for the chip to finish initializing */ 2394 if (pccbb_pcmcia_wait_ready(ph)) { 2395 #ifdef DIAGNOSTIC 2396 printf("pccbb_pcmcia_socket_enable: never became ready\n"); 2397 #endif 2398 /* XXX return a failure status?? */ 2399 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2400 Pcic_write(ph, PCIC_PWRCTL, 0); 2401 return; 2402 } 2403 2404 /* reinstall all the memory and io mappings */ 2405 for (win = 0; win < PCIC_MEM_WINS; ++win) 2406 if (ph->memalloc & (1 << win)) 2407 pccbb_pcmcia_do_mem_map(ph, win); 2408 for (win = 0; win < PCIC_IO_WINS; ++win) 2409 if (ph->ioalloc & (1 << win)) 2410 pccbb_pcmcia_do_io_map(ph, win); 2411 } 2412 2413 /* 2414 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2415 * 2416 * This function disables the card. All information is stored in 2417 * the first argument, pcmcia_chipset_handle_t. 2418 */ 2419 STATIC void 2420 pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t pch) 2421 { 2422 struct pcic_handle *ph = (struct pcic_handle *)pch; 2423 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2424 u_int8_t intr; 2425 2426 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2427 2428 /* disable interrupts; assert RESET */ 2429 intr = Pcic_read(ph, PCIC_INTR); 2430 intr &= PCIC_INTR_ENABLE; 2431 Pcic_write(ph, PCIC_INTR, intr); 2432 2433 /* zero out the address windows */ 2434 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2435 2436 /* power down the socket to reset it, clear the card reset pin */ 2437 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2438 2439 /* disable socket: negate output enable bit and power off */ 2440 Pcic_write(ph, PCIC_PWRCTL, 0); 2441 2442 /* 2443 * Vcc Falling Time (Tpf) = 300ms 2444 */ 2445 pccbb_pcmcia_delay(ph, 300, "pccwr1"); 2446 } 2447 2448 STATIC void 2449 pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t pch, int type) 2450 { 2451 struct pcic_handle *ph = (struct pcic_handle *)pch; 2452 u_int8_t intr; 2453 2454 /* set the card type */ 2455 2456 intr = Pcic_read(ph, PCIC_INTR); 2457 intr &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_CARDTYPE_MASK); 2458 if (type == PCMCIA_IFTYPE_IO) 2459 intr |= PCIC_INTR_CARDTYPE_IO; 2460 else 2461 intr |= PCIC_INTR_CARDTYPE_MEM; 2462 Pcic_write(ph, PCIC_INTR, intr); 2463 2464 DPRINTF(("%s: pccbb_pcmcia_socket_settype %02x type %s %02x\n", 2465 ph->ph_parent->dv_xname, ph->sock, 2466 ((type == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2467 } 2468 2469 /* 2470 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2471 * 2472 * This function detects whether a card is in the slot or not. 2473 * If a card is inserted, return 1. Otherwise, return 0. 2474 */ 2475 STATIC int 2476 pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch) 2477 { 2478 struct pcic_handle *ph = (struct pcic_handle *)pch; 2479 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2480 2481 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2482 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2483 } 2484 2485 #if 0 2486 STATIC int 2487 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2488 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2489 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2490 #endif 2491 /* 2492 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2493 * bus_size_t size, 2494 * struct pcmcia_mem_handle *pcmhp) 2495 * 2496 * This function only allocates memory region for pccard. This 2497 * function never maps the allocated region to pccard memory area. 2498 * 2499 * XXX: Why the argument of start address is not in? 2500 */ 2501 STATIC int 2502 pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 2503 struct pcmcia_mem_handle *pcmhp) 2504 { 2505 struct pcic_handle *ph = (struct pcic_handle *)pch; 2506 bus_space_handle_t memh; 2507 bus_addr_t addr; 2508 bus_size_t sizepg; 2509 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2510 #if rbus 2511 rbus_tag_t rb; 2512 #endif 2513 2514 /* Check that the card is still there. */ 2515 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2516 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2517 return 1; 2518 2519 /* out of sc->memh, allocate as many pages as necessary */ 2520 2521 /* convert size to PCIC pages */ 2522 /* 2523 * This is not enough; when the requested region is on the page 2524 * boundaries, this may calculate wrong result. 2525 */ 2526 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2527 #if 0 2528 if (sizepg > PCIC_MAX_MEM_PAGES) { 2529 return 1; 2530 } 2531 #endif 2532 2533 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2534 return 1; 2535 } 2536 2537 addr = 0; /* XXX gcc -Wuninitialized */ 2538 2539 #if rbus 2540 rb = sc->sc_rbus_memt; 2541 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2542 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2543 &addr, &memh)) { 2544 return 1; 2545 } 2546 #else 2547 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2548 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2549 0, /* boundary */ 2550 0, /* flags */ 2551 &addr, &memh)) { 2552 return 1; 2553 } 2554 #endif 2555 2556 DPRINTF(("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, " 2557 "realsize 0x%lx\n", (unsigned long)addr, (unsigned long)size, 2558 (unsigned long)sizepg * PCIC_MEM_PAGESIZE)); 2559 2560 pcmhp->memt = sc->sc_memt; 2561 pcmhp->memh = memh; 2562 pcmhp->addr = addr; 2563 pcmhp->size = size; 2564 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2565 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2566 pcmhp->mhandle = 0; 2567 /* No offset??? Funny. */ 2568 2569 return 0; 2570 } 2571 2572 /* 2573 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2574 * struct pcmcia_mem_handle *pcmhp) 2575 * 2576 * This function release the memory space allocated by the function 2577 * pccbb_pcmcia_mem_alloc(). 2578 */ 2579 STATIC void 2580 pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2581 struct pcmcia_mem_handle *pcmhp) 2582 { 2583 #if rbus 2584 struct pcic_handle *ph = (struct pcic_handle *)pch; 2585 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2586 2587 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2588 #else 2589 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2590 #endif 2591 } 2592 2593 /* 2594 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2595 * 2596 * This function release the memory space allocated by the function 2597 * pccbb_pcmcia_mem_alloc(). 2598 */ 2599 STATIC void 2600 pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2601 { 2602 int regbase_win; 2603 bus_addr_t phys_addr; 2604 bus_addr_t phys_end; 2605 2606 #define PCIC_SMM_START_LOW 0 2607 #define PCIC_SMM_START_HIGH 1 2608 #define PCIC_SMM_STOP_LOW 2 2609 #define PCIC_SMM_STOP_HIGH 3 2610 #define PCIC_CMA_LOW 4 2611 #define PCIC_CMA_HIGH 5 2612 2613 u_int8_t start_low, start_high = 0; 2614 u_int8_t stop_low, stop_high; 2615 u_int8_t off_low, off_high; 2616 u_int8_t mem_window; 2617 int reg; 2618 2619 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2620 int mem8 = 2621 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2622 || (kind == PCMCIA_MEM_ATTR); 2623 2624 regbase_win = 0x10 + win * 0x08; 2625 2626 phys_addr = ph->mem[win].addr; 2627 phys_end = phys_addr + ph->mem[win].size; 2628 2629 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2630 (unsigned long)phys_addr, (unsigned long)phys_end, 2631 (unsigned long)ph->mem[win].offset)); 2632 2633 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2634 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2635 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2636 2637 /* bit 19:12 */ 2638 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2639 /* bit 23:20 and bit 7 on */ 2640 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2641 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2642 /* bit 31:24, for 32-bit address */ 2643 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2644 2645 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2646 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2647 2648 if (((struct pccbb_softc *)ph-> 2649 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2650 Pcic_write(ph, 0x40 + win, mem_window); 2651 } 2652 2653 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2654 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2655 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2656 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2657 2658 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2659 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2660 2661 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2662 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2663 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2664 | ((kind == PCMCIA_MEM_ATTR) ? 2665 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2666 2667 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2668 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2669 2670 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2671 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2672 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2673 2674 #if defined(CBB_DEBUG) 2675 { 2676 int r1, r2, r3, r4, r5, r6, r7 = 0; 2677 2678 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2679 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2680 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2681 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2682 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2683 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2684 if (((struct pccbb_softc *)(ph-> 2685 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2686 r7 = Pcic_read(ph, 0x40 + win); 2687 } 2688 2689 printf("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2690 "%02x%02x", win, r1, r2, r3, r4, r5, r6); 2691 if (((struct pccbb_softc *)(ph-> 2692 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2693 printf(" %02x", r7); 2694 } 2695 printf("\n"); 2696 } 2697 #endif 2698 } 2699 2700 /* 2701 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2702 * bus_addr_t card_addr, bus_size_t size, 2703 * struct pcmcia_mem_handle *pcmhp, 2704 * bus_addr_t *offsetp, int *windowp) 2705 * 2706 * This function maps memory space allocated by the function 2707 * pccbb_pcmcia_mem_alloc(). 2708 */ 2709 STATIC int 2710 pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2711 bus_addr_t card_addr, bus_size_t size, struct pcmcia_mem_handle *pcmhp, 2712 bus_addr_t *offsetp, int *windowp) 2713 { 2714 struct pcic_handle *ph = (struct pcic_handle *)pch; 2715 bus_addr_t busaddr; 2716 long card_offset; 2717 int win; 2718 2719 /* Check that the card is still there. */ 2720 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2721 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2722 return 1; 2723 2724 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2725 if ((ph->memalloc & (1 << win)) == 0) { 2726 ph->memalloc |= (1 << win); 2727 break; 2728 } 2729 } 2730 2731 if (win == PCIC_MEM_WINS) { 2732 return 1; 2733 } 2734 2735 *windowp = win; 2736 2737 /* XXX this is pretty gross */ 2738 2739 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2740 panic("pccbb_pcmcia_mem_map memt is bogus"); 2741 } 2742 2743 busaddr = pcmhp->addr; 2744 2745 /* 2746 * compute the address offset to the pcmcia address space for the 2747 * pcic. this is intentionally signed. The masks and shifts below 2748 * will cause TRT to happen in the pcic registers. Deal with making 2749 * sure the address is aligned, and return the alignment offset. 2750 */ 2751 2752 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2753 card_addr -= *offsetp; 2754 2755 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2756 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2757 (u_long) card_addr)); 2758 2759 /* 2760 * include the offset in the size, and decrement size by one, since 2761 * the hw wants start/stop 2762 */ 2763 size += *offsetp - 1; 2764 2765 card_offset = (((long)card_addr) - ((long)busaddr)); 2766 2767 ph->mem[win].addr = busaddr; 2768 ph->mem[win].size = size; 2769 ph->mem[win].offset = card_offset; 2770 ph->mem[win].kind = kind; 2771 2772 pccbb_pcmcia_do_mem_map(ph, win); 2773 2774 return 0; 2775 } 2776 2777 /* 2778 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2779 * int window) 2780 * 2781 * This function unmaps memory space which mapped by the function 2782 * pccbb_pcmcia_mem_map(). 2783 */ 2784 STATIC void 2785 pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, int window) 2786 { 2787 struct pcic_handle *ph = (struct pcic_handle *)pch; 2788 int reg; 2789 2790 if (window >= PCIC_MEM_WINS) { 2791 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2792 } 2793 2794 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2795 reg &= ~(1 << window); 2796 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2797 2798 ph->memalloc &= ~(1 << window); 2799 } 2800 2801 #if defined PCCBB_PCMCIA_POLL 2802 struct pccbb_poll_str { 2803 void *arg; 2804 int (*func)(void *); 2805 int level; 2806 struct pcic_handle *ph; 2807 int count; 2808 int num; 2809 struct callout poll_ch; 2810 }; 2811 2812 static struct pccbb_poll_str pccbb_poll[10]; 2813 static int pccbb_poll_n = 0; 2814 2815 static void pccbb_pcmcia_poll(void *arg); 2816 2817 static void 2818 pccbb_pcmcia_poll(void *arg) 2819 { 2820 struct pccbb_poll_str *poll = arg; 2821 struct pcic_handle *ph = poll->ph; 2822 struct pccbb_softc *sc = ph->sc; 2823 int s; 2824 u_int32_t spsr; /* socket present-state reg */ 2825 2826 callout_reset(&poll->poll_ch, hz * 2, pccbb_pcmcia_poll, arg); 2827 switch (poll->level) { 2828 case IPL_NET: 2829 s = splnet(); 2830 break; 2831 case IPL_BIO: 2832 s = splbio(); 2833 break; 2834 case IPL_TTY: /* fallthrough */ 2835 default: 2836 s = spltty(); 2837 break; 2838 } 2839 2840 spsr = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2841 CB_SOCKET_STAT); 2842 2843 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2844 if (!(spsr & 0x40)) /* CINT low */ 2845 #else 2846 if (1) 2847 #endif 2848 { 2849 if ((*poll->func) (poll->arg) > 0) { 2850 ++poll->count; 2851 /* printf("intr: reported from poller, 0x%x\n", spsr); */ 2852 #if defined LEVEL2 2853 } else { 2854 printf("intr: miss! 0x%x\n", spsr); 2855 #endif 2856 } 2857 } 2858 splx(s); 2859 } 2860 #endif /* defined CB_PCMCIA_POLL */ 2861 2862 /* 2863 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2864 * struct pcmcia_function *pf, 2865 * int ipl, 2866 * int (*func)(void *), 2867 * void *arg); 2868 * 2869 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2870 */ 2871 STATIC void * 2872 pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2873 struct pcmcia_function *pf, int ipl, int (*func)(void *), void *arg) 2874 { 2875 struct pcic_handle *ph = (struct pcic_handle *)pch; 2876 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2877 2878 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2879 /* what should I do? */ 2880 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2881 DPRINTF(("%s does not provide edge nor pulse " 2882 "interrupt\n", sc->sc_dev.dv_xname)); 2883 return NULL; 2884 } 2885 /* 2886 * XXX Noooooo! The interrupt flag must set properly!! 2887 * dumb pcmcia driver!! 2888 */ 2889 } 2890 2891 return pccbb_intr_establish(sc, 0, ipl, func, arg); 2892 } 2893 2894 /* 2895 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2896 * void *ih) 2897 * 2898 * This function disables PC-Card interrupt. 2899 */ 2900 STATIC void 2901 pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 2902 { 2903 struct pcic_handle *ph = (struct pcic_handle *)pch; 2904 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2905 2906 pccbb_intr_disestablish(sc, ih); 2907 } 2908 2909 #if rbus 2910 /* 2911 * static int 2912 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2913 * bus_addr_t addr, bus_size_t size, 2914 * bus_addr_t mask, bus_size_t align, 2915 * int flags, bus_addr_t *addrp; 2916 * bus_space_handle_t *bshp) 2917 * 2918 * This function allocates a portion of memory or io space for 2919 * clients. This function is called from CardBus card drivers. 2920 */ 2921 static int 2922 pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2923 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 2924 int flags, bus_addr_t *addrp, bus_space_handle_t *bshp) 2925 { 2926 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2927 2928 DPRINTF(("pccbb_rbus_cb_space_alloc: addr 0x%lx, size 0x%lx, " 2929 "mask 0x%lx, align 0x%lx\n", (unsigned long)addr, 2930 (unsigned long)size, (unsigned long)mask, (unsigned long)align)); 2931 2932 if (align == 0) { 2933 align = size; 2934 } 2935 2936 if (rb->rb_bt == sc->sc_memt) { 2937 if (align < 16) { 2938 return 1; 2939 } 2940 /* 2941 * XXX: align more than 0x1000 to avoid overwrapping 2942 * memory windows for two or more devices. 0x1000 2943 * means memory window's granularity. 2944 * 2945 * Two or more devices should be able to share same 2946 * memory window region. However, overrapping memory 2947 * window is not good because some devices, such as 2948 * 3Com 3C575[BC], have a broken address decoder and 2949 * intrude other's memory region. 2950 */ 2951 if (align < 0x1000) { 2952 align = 0x1000; 2953 } 2954 } else if (rb->rb_bt == sc->sc_iot) { 2955 if (align < 4) { 2956 return 1; 2957 } 2958 /* XXX: hack for avoiding ISA image */ 2959 if (mask < 0x0100) { 2960 mask = 0x3ff; 2961 addr = 0x300; 2962 } 2963 2964 } else { 2965 DPRINTF(("pccbb_rbus_cb_space_alloc: Bus space tag 0x%lx is " 2966 "NOT used. io: 0x%lx, mem: 0x%lx\n", 2967 (unsigned long)rb->rb_bt, (unsigned long)sc->sc_iot, 2968 (unsigned long)sc->sc_memt)); 2969 return 1; 2970 /* XXX: panic here? */ 2971 } 2972 2973 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 2974 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 2975 return 1; 2976 } 2977 2978 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 2979 2980 return 0; 2981 } 2982 2983 /* 2984 * static int 2985 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 2986 * bus_space_handle_t *bshp, bus_size_t size); 2987 * 2988 * This function is called from CardBus card drivers. 2989 */ 2990 static int 2991 pccbb_rbus_cb_space_free(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2992 bus_space_handle_t bsh, bus_size_t size) 2993 { 2994 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2995 bus_space_tag_t bt = rb->rb_bt; 2996 2997 pccbb_close_win(sc, bt, bsh, size); 2998 2999 if (bt == sc->sc_memt) { 3000 } else if (bt == sc->sc_iot) { 3001 } else { 3002 return 1; 3003 /* XXX: panic here? */ 3004 } 3005 3006 return rbus_space_free(rb, bsh, size, NULL); 3007 } 3008 #endif /* rbus */ 3009 3010 #if rbus 3011 3012 static int 3013 pccbb_open_win(struct pccbb_softc *sc, bus_space_tag_t bst, bus_addr_t addr, 3014 bus_size_t size, bus_space_handle_t bsh, int flags) 3015 { 3016 struct pccbb_win_chain_head *head; 3017 bus_addr_t align; 3018 3019 head = &sc->sc_iowindow; 3020 align = 0x04; 3021 if (sc->sc_memt == bst) { 3022 head = &sc->sc_memwindow; 3023 align = 0x1000; 3024 DPRINTF(("using memory window, 0x%lx 0x%lx 0x%lx\n\n", 3025 (unsigned long)sc->sc_iot, (unsigned long)sc->sc_memt, 3026 (unsigned long)bst)); 3027 } 3028 3029 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 3030 printf("%s: pccbb_open_win: %s winlist insert failed\n", 3031 sc->sc_dev.dv_xname, 3032 (head == &sc->sc_memwindow) ? "mem" : "io"); 3033 } 3034 pccbb_winset(align, sc, bst); 3035 3036 return 0; 3037 } 3038 3039 static int 3040 pccbb_close_win(struct pccbb_softc *sc, bus_space_tag_t bst, 3041 bus_space_handle_t bsh, bus_size_t size) 3042 { 3043 struct pccbb_win_chain_head *head; 3044 bus_addr_t align; 3045 3046 head = &sc->sc_iowindow; 3047 align = 0x04; 3048 if (sc->sc_memt == bst) { 3049 head = &sc->sc_memwindow; 3050 align = 0x1000; 3051 } 3052 3053 if (pccbb_winlist_delete(head, bsh, size)) { 3054 printf("%s: pccbb_close_win: %s winlist delete failed\n", 3055 sc->sc_dev.dv_xname, 3056 (head == &sc->sc_memwindow) ? "mem" : "io"); 3057 } 3058 pccbb_winset(align, sc, bst); 3059 3060 return 0; 3061 } 3062 3063 static int 3064 pccbb_winlist_insert(struct pccbb_win_chain_head *head, bus_addr_t start, 3065 bus_size_t size, bus_space_handle_t bsh, int flags) 3066 { 3067 struct pccbb_win_chain *chainp, *elem; 3068 3069 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 3070 M_NOWAIT)) == NULL) 3071 return (1); /* fail */ 3072 3073 elem->wc_start = start; 3074 elem->wc_end = start + (size - 1); 3075 elem->wc_handle = bsh; 3076 elem->wc_flags = flags; 3077 3078 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3079 chainp = TAILQ_NEXT(chainp, wc_list)) { 3080 if (chainp->wc_end < start) 3081 continue; 3082 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 3083 return (0); 3084 } 3085 3086 TAILQ_INSERT_TAIL(head, elem, wc_list); 3087 return (0); 3088 } 3089 3090 static int 3091 pccbb_winlist_delete(struct pccbb_win_chain_head *head, bus_space_handle_t bsh, 3092 bus_size_t size) 3093 { 3094 struct pccbb_win_chain *chainp; 3095 3096 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3097 chainp = TAILQ_NEXT(chainp, wc_list)) { 3098 if (memcmp(&chainp->wc_handle, &bsh, sizeof(bsh))) 3099 continue; 3100 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 3101 printf("pccbb_winlist_delete: window 0x%lx size " 3102 "inconsistent: 0x%lx, 0x%lx\n", 3103 (unsigned long)chainp->wc_start, 3104 (unsigned long)(chainp->wc_end - chainp->wc_start), 3105 (unsigned long)(size - 1)); 3106 return 1; 3107 } 3108 3109 TAILQ_REMOVE(head, chainp, wc_list); 3110 free(chainp, M_DEVBUF); 3111 3112 return 0; 3113 } 3114 3115 return 1; /* fail: no candidate to remove */ 3116 } 3117 3118 static void 3119 pccbb_winset(bus_addr_t align, struct pccbb_softc *sc, bus_space_tag_t bst) 3120 { 3121 pci_chipset_tag_t pc; 3122 pcitag_t tag; 3123 bus_addr_t mask = ~(align - 1); 3124 struct { 3125 cardbusreg_t win_start; 3126 cardbusreg_t win_limit; 3127 int win_flags; 3128 } win[2]; 3129 struct pccbb_win_chain *chainp; 3130 int offs; 3131 3132 win[0].win_start = win[1].win_start = 0xffffffff; 3133 win[0].win_limit = win[1].win_limit = 0; 3134 win[0].win_flags = win[1].win_flags = 0; 3135 3136 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3137 offs = 0x2c; 3138 if (sc->sc_memt == bst) { 3139 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3140 offs = 0x1c; 3141 } 3142 3143 if (chainp != NULL) { 3144 win[0].win_start = chainp->wc_start & mask; 3145 win[0].win_limit = chainp->wc_end & mask; 3146 win[0].win_flags = chainp->wc_flags; 3147 chainp = TAILQ_NEXT(chainp, wc_list); 3148 } 3149 3150 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3151 if (win[1].win_start == 0xffffffff) { 3152 /* window 1 is not used */ 3153 if ((win[0].win_flags == chainp->wc_flags) && 3154 (win[0].win_limit + align >= 3155 (chainp->wc_start & mask))) { 3156 /* concatenate */ 3157 win[0].win_limit = chainp->wc_end & mask; 3158 } else { 3159 /* make new window */ 3160 win[1].win_start = chainp->wc_start & mask; 3161 win[1].win_limit = chainp->wc_end & mask; 3162 win[1].win_flags = chainp->wc_flags; 3163 } 3164 continue; 3165 } 3166 3167 /* Both windows are engaged. */ 3168 if (win[0].win_flags == win[1].win_flags) { 3169 /* same flags */ 3170 if (win[0].win_flags == chainp->wc_flags) { 3171 if (win[1].win_start - (win[0].win_limit + 3172 align) < 3173 (chainp->wc_start & mask) - 3174 ((chainp->wc_end & mask) + align)) { 3175 /* 3176 * merge window 0 and 1, and set win1 3177 * to chainp 3178 */ 3179 win[0].win_limit = win[1].win_limit; 3180 win[1].win_start = 3181 chainp->wc_start & mask; 3182 win[1].win_limit = 3183 chainp->wc_end & mask; 3184 } else { 3185 win[1].win_limit = 3186 chainp->wc_end & mask; 3187 } 3188 } else { 3189 /* different flags */ 3190 3191 /* concatenate win0 and win1 */ 3192 win[0].win_limit = win[1].win_limit; 3193 /* allocate win[1] to new space */ 3194 win[1].win_start = chainp->wc_start & mask; 3195 win[1].win_limit = chainp->wc_end & mask; 3196 win[1].win_flags = chainp->wc_flags; 3197 } 3198 } else { 3199 /* the flags of win[0] and win[1] is different */ 3200 if (win[0].win_flags == chainp->wc_flags) { 3201 win[0].win_limit = chainp->wc_end & mask; 3202 /* 3203 * XXX this creates overlapping windows, so 3204 * what should the poor bridge do if one is 3205 * cachable, and the other is not? 3206 */ 3207 printf("%s: overlapping windows\n", 3208 sc->sc_dev.dv_xname); 3209 } else { 3210 win[1].win_limit = chainp->wc_end & mask; 3211 } 3212 } 3213 } 3214 3215 pc = sc->sc_pc; 3216 tag = sc->sc_tag; 3217 pci_conf_write(pc, tag, offs, win[0].win_start); 3218 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3219 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3220 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3221 DPRINTF(("--pccbb_winset: win0 [0x%lx, 0x%lx), win1 [0x%lx, 0x%lx)\n", 3222 (unsigned long)pci_conf_read(pc, tag, offs), 3223 (unsigned long)pci_conf_read(pc, tag, offs + 4) + align, 3224 (unsigned long)pci_conf_read(pc, tag, offs + 8), 3225 (unsigned long)pci_conf_read(pc, tag, offs + 12) + align)); 3226 3227 if (bst == sc->sc_memt) { 3228 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BRIDGE_CONTROL_REG); 3229 3230 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 3231 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 3232 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3233 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 3234 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3235 pci_conf_write(pc, tag, PCI_BRIDGE_CONTROL_REG, bcr); 3236 } 3237 } 3238 3239 #endif /* rbus */ 3240 3241 static void 3242 pccbb_powerhook(int why, void *arg) 3243 { 3244 struct pccbb_softc *sc = arg; 3245 pcireg_t reg; 3246 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3247 bus_space_handle_t base_memh = sc->sc_base_memh; 3248 3249 DPRINTF(("%s: power: why %d\n", sc->sc_dev.dv_xname, why)); 3250 3251 if (why == PWR_SUSPEND || why == PWR_STANDBY) { 3252 DPRINTF(("%s: power: why %d stopping intr\n", 3253 sc->sc_dev.dv_xname, why)); 3254 if (sc->sc_pil_intr_enable) { 3255 (void)pccbbintr_function(sc); 3256 } 3257 sc->sc_pil_intr_enable = 0; 3258 3259 pci_conf_capture(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf); 3260 3261 if (sc->sc_chipset == CB_RX5C47X) 3262 sc->sc_ricoh_misc_ctrl = pci_conf_read(sc->sc_pc, 3263 sc->sc_tag, 3264 RICOH_PCI_MISC_CTRL); 3265 3266 /* ToDo: deactivate or suspend child devices */ 3267 } 3268 3269 if (why == PWR_RESUME) { 3270 if (sc->sc_pwrmgt_offs != 0) { 3271 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, 3272 sc->sc_pwrmgt_offs + PCI_PMCSR); 3273 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 3274 reg & PCI_PMCSR_PME_EN) { 3275 /* powrstate != D0 */ 3276 3277 printf("%s going back to D0 mode\n", 3278 sc->sc_dev.dv_xname); 3279 reg &= ~PCI_PMCSR_STATE_MASK; 3280 reg |= PCI_PMCSR_STATE_D0; 3281 reg &= ~PCI_PMCSR_PME_EN; 3282 pci_conf_write(sc->sc_pc, sc->sc_tag, 3283 sc->sc_pwrmgt_offs + PCI_PMCSR, reg); 3284 3285 pci_conf_write(sc->sc_pc, sc->sc_tag, 3286 PCI_SOCKBASE, sc->sc_sockbase); 3287 pci_conf_write(sc->sc_pc, sc->sc_tag, 3288 PCI_BUSNUM, sc->sc_busnum); 3289 pccbb_chipinit(sc); 3290 /* setup memory and io space window for CB */ 3291 pccbb_winset(0x1000, sc, sc->sc_memt); 3292 pccbb_winset(0x04, sc, sc->sc_iot); 3293 goto norestore; 3294 } 3295 } 3296 3297 norestore: 3298 pci_conf_restore(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf); 3299 if (sc->sc_chipset == CB_RX5C47X) { 3300 pci_conf_write(sc->sc_pc, sc->sc_tag, 3301 RICOH_PCI_MISC_CTRL, sc->sc_ricoh_misc_ctrl); 3302 } 3303 3304 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_SOCKBASE) == 0) 3305 /* BIOS did not recover this register */ 3306 pci_conf_write (sc->sc_pc, sc->sc_tag, 3307 PCI_SOCKBASE, sc->sc_sockbase); 3308 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_BUSNUM) == 0) 3309 /* BIOS did not recover this register */ 3310 pci_conf_write (sc->sc_pc, sc->sc_tag, 3311 PCI_BUSNUM, sc->sc_busnum); 3312 /* CSC Interrupt: Card detect interrupt on */ 3313 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3314 /* Card detect intr is turned on. */ 3315 reg |= CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; 3316 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3317 /* reset interrupt */ 3318 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3319 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3320 3321 /* 3322 * check for card insertion or removal during suspend period. 3323 * XXX: the code can't cope with card swap (remove then 3324 * insert). how can we detect such situation? 3325 */ 3326 (void)pccbbintr(sc); 3327 3328 sc->sc_pil_intr_enable = 1; 3329 DPRINTF(("%s: power: RESUME enabling intr\n", 3330 sc->sc_dev.dv_xname)); 3331 3332 /* ToDo: activate or wakeup child devices */ 3333 } 3334 } 3335
Indexes created Fri Sep 26 08:10:20 GMT 2025