pccbb.c revision 1.149
1 /* $NetBSD: pccbb.c,v 1.149 2007/10/22 14:03:51 joerg Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: pccbb.c,v 1.149 2007/10/22 14:03:51 joerg Exp $"); 35 36 /* 37 #define CBB_DEBUG 38 #define SHOW_REGS 39 */ 40 41 /* 42 * BROKEN! 43 #define PCCBB_PCMCIA_POLL 44 #define CB_PCMCIA_POLL 45 #define CB_PCMCIA_POLL_ONLY 46 #define LEVEL2 47 */ 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/kernel.h> 52 #include <sys/errno.h> 53 #include <sys/ioctl.h> 54 #include <sys/reboot.h> /* for bootverbose */ 55 #include <sys/syslog.h> 56 #include <sys/device.h> 57 #include <sys/malloc.h> 58 #include <sys/proc.h> 59 60 #include <sys/intr.h> 61 #include <sys/bus.h> 62 63 #include <dev/pci/pcivar.h> 64 #include <dev/pci/pcireg.h> 65 #include <dev/pci/pcidevs.h> 66 67 #include <dev/pci/pccbbreg.h> 68 69 #include <dev/cardbus/cardslotvar.h> 70 71 #include <dev/cardbus/cardbusvar.h> 72 73 #include <dev/pcmcia/pcmciareg.h> 74 #include <dev/pcmcia/pcmciavar.h> 75 76 #include <dev/ic/i82365reg.h> 77 #include <dev/ic/i82365var.h> 78 #include <dev/pci/pccbbvar.h> 79 80 #include "locators.h" 81 82 #if defined(__i386__) 83 #include "ioapic.h" 84 #include "acpi.h" 85 #endif 86 87 #ifndef __NetBSD_Version__ 88 struct cfdriver cbb_cd = { 89 NULL, "cbb", DV_DULL 90 }; 91 #endif 92 93 #ifdef CBB_DEBUG 94 #define DPRINTF(x) printf x 95 #define STATIC 96 #else 97 #define DPRINTF(x) 98 #define STATIC static 99 #endif 100 101 /* 102 * delay_ms() is wait in milliseconds. It should be used instead 103 * of delay() if you want to wait more than 1 ms. 104 */ 105 static inline void 106 delay_ms(int millis, void *param) 107 { 108 if (cold) 109 delay(millis * 1000); 110 else 111 tsleep(param, PWAIT, "pccbb", MAX(2, hz * millis / 1000)); 112 } 113 114 int pcicbbmatch(struct device *, struct cfdata *, void *); 115 void pccbbattach(struct device *, struct device *, void *); 116 int pccbbintr(void *); 117 static void pci113x_insert(void *); 118 static int pccbbintr_function(struct pccbb_softc *); 119 120 static int pccbb_detect_card(struct pccbb_softc *); 121 122 static void pccbb_pcmcia_write(struct pcic_handle *, int, u_int8_t); 123 static u_int8_t pccbb_pcmcia_read(struct pcic_handle *, int); 124 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 125 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 126 127 STATIC int cb_reset(struct pccbb_softc *); 128 STATIC int cb_detect_voltage(struct pccbb_softc *); 129 STATIC int cbbprint(void *, const char *); 130 131 static int cb_chipset(u_int32_t, int *); 132 STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *, 133 struct pcmciabus_attach_args *); 134 #if 0 135 STATIC void pccbb_pcmcia_attach_card(struct pcic_handle *); 136 STATIC void pccbb_pcmcia_detach_card(struct pcic_handle *, int); 137 STATIC void pccbb_pcmcia_deactivate_card(struct pcic_handle *); 138 #endif 139 140 STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int); 141 STATIC int pccbb_power(cardbus_chipset_tag_t, int); 142 STATIC int pccbb_cardenable(struct pccbb_softc * sc, int function); 143 #if !rbus 144 static int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 145 static int pccbb_io_close(cardbus_chipset_tag_t, int); 146 static int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 147 static int pccbb_mem_close(cardbus_chipset_tag_t, int); 148 #endif /* !rbus */ 149 static void *pccbb_intr_establish(struct pccbb_softc *, int irq, 150 int level, int (*ih) (void *), void *sc); 151 static void pccbb_intr_disestablish(struct pccbb_softc *, void *ih); 152 153 static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t, int irq, 154 int level, int (*ih) (void *), void *sc); 155 static void pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih); 156 157 static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t, int, int); 158 static void pccbb_free_tag(cardbus_chipset_tag_t, cardbustag_t); 159 static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t, cardbustag_t, int); 160 static void pccbb_conf_write(cardbus_chipset_tag_t, cardbustag_t, int, 161 cardbusreg_t); 162 static void pccbb_chipinit(struct pccbb_softc *); 163 164 STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 165 struct pcmcia_mem_handle *); 166 STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t, 167 struct pcmcia_mem_handle *); 168 STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 169 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *); 170 STATIC void pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t, int); 171 STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 172 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 173 STATIC void pccbb_pcmcia_io_free(pcmcia_chipset_handle_t, 174 struct pcmcia_io_handle *); 175 STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 176 bus_size_t, struct pcmcia_io_handle *, int *); 177 STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t, int); 178 STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t, 179 struct pcmcia_function *, int, int (*)(void *), void *); 180 STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t, void *); 181 STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t); 182 STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t); 183 STATIC void pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t, int); 184 STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch); 185 186 static int pccbb_pcmcia_wait_ready(struct pcic_handle *); 187 static void pccbb_pcmcia_delay(struct pcic_handle *, int, const char *); 188 189 static void pccbb_pcmcia_do_io_map(struct pcic_handle *, int); 190 static void pccbb_pcmcia_do_mem_map(struct pcic_handle *, int); 191 static void pccbb_powerhook(int, void *); 192 193 /* bus-space allocation and deallocation functions */ 194 #if rbus 195 196 static int pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t, rbus_tag_t, 197 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 198 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp); 199 static int pccbb_rbus_cb_space_free(cardbus_chipset_tag_t, rbus_tag_t, 200 bus_space_handle_t, bus_size_t); 201 202 #endif /* rbus */ 203 204 #if rbus 205 206 static int pccbb_open_win(struct pccbb_softc *, bus_space_tag_t, 207 bus_addr_t, bus_size_t, bus_space_handle_t, int flags); 208 static int pccbb_close_win(struct pccbb_softc *, bus_space_tag_t, 209 bus_space_handle_t, bus_size_t); 210 static int pccbb_winlist_insert(struct pccbb_win_chain_head *, bus_addr_t, 211 bus_size_t, bus_space_handle_t, int); 212 static int pccbb_winlist_delete(struct pccbb_win_chain_head *, 213 bus_space_handle_t, bus_size_t); 214 static void pccbb_winset(bus_addr_t align, struct pccbb_softc *, 215 bus_space_tag_t); 216 void pccbb_winlist_show(struct pccbb_win_chain *); 217 218 #endif /* rbus */ 219 220 /* for config_defer */ 221 static void pccbb_pci_callback(struct device *); 222 223 #if defined SHOW_REGS 224 static void cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, 225 bus_space_tag_t memt, bus_space_handle_t memh); 226 #endif 227 228 CFATTACH_DECL(cbb_pci, sizeof(struct pccbb_softc), 229 pcicbbmatch, pccbbattach, NULL, NULL); 230 231 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 232 pccbb_pcmcia_mem_alloc, 233 pccbb_pcmcia_mem_free, 234 pccbb_pcmcia_mem_map, 235 pccbb_pcmcia_mem_unmap, 236 pccbb_pcmcia_io_alloc, 237 pccbb_pcmcia_io_free, 238 pccbb_pcmcia_io_map, 239 pccbb_pcmcia_io_unmap, 240 pccbb_pcmcia_intr_establish, 241 pccbb_pcmcia_intr_disestablish, 242 pccbb_pcmcia_socket_enable, 243 pccbb_pcmcia_socket_disable, 244 pccbb_pcmcia_socket_settype, 245 pccbb_pcmcia_card_detect 246 }; 247 248 #if rbus 249 static struct cardbus_functions pccbb_funcs = { 250 pccbb_rbus_cb_space_alloc, 251 pccbb_rbus_cb_space_free, 252 pccbb_cb_intr_establish, 253 pccbb_cb_intr_disestablish, 254 pccbb_ctrl, 255 pccbb_power, 256 pccbb_make_tag, 257 pccbb_free_tag, 258 pccbb_conf_read, 259 pccbb_conf_write, 260 }; 261 #else 262 static struct cardbus_functions pccbb_funcs = { 263 pccbb_ctrl, 264 pccbb_power, 265 pccbb_mem_open, 266 pccbb_mem_close, 267 pccbb_io_open, 268 pccbb_io_close, 269 pccbb_cb_intr_establish, 270 pccbb_cb_intr_disestablish, 271 pccbb_make_tag, 272 pccbb_conf_read, 273 pccbb_conf_write, 274 }; 275 #endif 276 277 int 278 pcicbbmatch(struct device *parent, struct cfdata *match, void *aux) 279 { 280 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 281 282 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 283 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 284 PCI_INTERFACE(pa->pa_class) == 0) { 285 return 1; 286 } 287 288 return 0; 289 } 290 291 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 292 | ((prod) << PCI_PRODUCT_SHIFT)) 293 294 const struct yenta_chipinfo { 295 pcireg_t yc_id; /* vendor tag | product tag */ 296 int yc_chiptype; 297 int yc_flags; 298 } yc_chipsets[] = { 299 /* Texas Instruments chips */ 300 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 301 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 302 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 303 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 304 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI125X, 305 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 306 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 307 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 308 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 309 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 310 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 311 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 312 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI125X, 313 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 314 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI125X, 315 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 316 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 317 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 318 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 319 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 320 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 321 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 322 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI125X, 323 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 324 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 325 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 326 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1520), CB_TI12XX, 327 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 328 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4410YENTA), CB_TI12XX, 329 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 330 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4520YENTA), CB_TI12XX, 331 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 332 333 /* Ricoh chips */ 334 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 335 PCCBB_PCMCIA_MEM_32}, 336 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 337 PCCBB_PCMCIA_MEM_32}, 338 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 339 PCCBB_PCMCIA_MEM_32}, 340 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 341 PCCBB_PCMCIA_MEM_32}, 342 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 343 PCCBB_PCMCIA_MEM_32}, 344 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 345 PCCBB_PCMCIA_MEM_32}, 346 347 /* Toshiba products */ 348 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 349 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 350 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 351 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 352 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 353 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 354 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 355 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 356 357 /* Cirrus Logic products */ 358 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 359 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 360 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 361 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 362 363 /* sentinel, or Generic chip */ 364 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 365 }; 366 367 static int 368 cb_chipset(u_int32_t pci_id, int *flagp) 369 { 370 const struct yenta_chipinfo *yc; 371 372 /* Loop over except the last default entry. */ 373 for (yc = yc_chipsets; yc < yc_chipsets + 374 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 375 if (pci_id == yc->yc_id) 376 break; 377 378 if (flagp != NULL) 379 *flagp = yc->yc_flags; 380 381 return (yc->yc_chiptype); 382 } 383 384 static void 385 pccbb_shutdown(void *arg) 386 { 387 struct pccbb_softc *sc = arg; 388 pcireg_t command; 389 390 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 391 392 /* 393 * turn off power 394 * 395 * XXX - do not turn off power if chipset is TI 113X because 396 * only TI 1130 with PowerMac 2400 hangs in pccbb_power(). 397 */ 398 if (sc->sc_chipset != CB_TI113X) { 399 pccbb_power((cardbus_chipset_tag_t)sc, 400 CARDBUS_VCC_0V | CARDBUS_VPP_0V); 401 } 402 403 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 404 0); 405 406 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 407 408 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 409 PCI_COMMAND_MASTER_ENABLE); 410 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 411 412 } 413 414 void 415 pccbbattach(struct device *parent, struct device *self, void *aux) 416 { 417 struct pccbb_softc *sc = (void *)self; 418 struct pci_attach_args *pa = aux; 419 pci_chipset_tag_t pc = pa->pa_pc; 420 pcireg_t busreg, reg, sock_base; 421 bus_addr_t sockbase; 422 char devinfo[256]; 423 int flags; 424 int pwrmgt_offs; 425 426 #ifdef __HAVE_PCCBB_ATTACH_HOOK 427 pccbb_attach_hook(parent, self, pa); 428 #endif 429 430 callout_init(&sc->sc_insert_ch, 0); 431 callout_setfunc(&sc->sc_insert_ch, pci113x_insert, sc); 432 433 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 434 435 pci_devinfo(pa->pa_id, 0, 0, devinfo, sizeof(devinfo)); 436 printf(": %s (rev. 0x%02x)", devinfo, PCI_REVISION(pa->pa_class)); 437 DPRINTF((" (chipflags %x)", flags)); 438 printf("\n"); 439 440 TAILQ_INIT(&sc->sc_memwindow); 441 TAILQ_INIT(&sc->sc_iowindow); 442 443 #if rbus 444 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 445 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 446 447 #if 0 448 printf("pa->pa_memt: %08x vs rbus_mem->rb_bt: %08x\n", 449 pa->pa_memt, sc->sc_rbus_memt->rb_bt); 450 #endif 451 #endif /* rbus */ 452 453 sc->sc_flags &= ~CBB_MEMHMAPPED; 454 455 /* power management: set D0 state */ 456 sc->sc_pwrmgt_offs = 0; 457 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, 458 &pwrmgt_offs, 0)) { 459 reg = pci_conf_read(pc, pa->pa_tag, pwrmgt_offs + PCI_PMCSR); 460 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 461 reg & 0x100 /* PCI_PMCSR_PME_EN */) { 462 reg &= ~PCI_PMCSR_STATE_MASK; 463 reg |= PCI_PMCSR_STATE_D0; 464 reg &= ~(0x100 /* PCI_PMCSR_PME_EN */); 465 pci_conf_write(pc, pa->pa_tag, 466 pwrmgt_offs + PCI_PMCSR, reg); 467 } 468 469 sc->sc_pwrmgt_offs = pwrmgt_offs; 470 } 471 472 /* 473 * MAP socket registers and ExCA registers on memory-space 474 * When no valid address is set on socket base registers (on pci 475 * config space), get it not polite way. 476 */ 477 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 478 479 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 480 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 481 /* The address must be valid. */ 482 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 483 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL)) { 484 printf("%s: can't map socket base address 0x%lx\n", 485 sc->sc_dev.dv_xname, (unsigned long)sock_base); 486 /* 487 * I think it's funny: socket base registers must be 488 * mapped on memory space, but ... 489 */ 490 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 491 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 492 NULL)) { 493 printf("%s: can't map socket base address" 494 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 495 (unsigned long)sockbase); 496 /* give up... allocate reg space via rbus. */ 497 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 498 } else 499 sc->sc_flags |= CBB_MEMHMAPPED; 500 } else { 501 DPRINTF(("%s: socket base address 0x%lx\n", 502 sc->sc_dev.dv_xname, (unsigned long)sockbase)); 503 sc->sc_flags |= CBB_MEMHMAPPED; 504 } 505 } 506 507 sc->sc_mem_start = 0; /* XXX */ 508 sc->sc_mem_end = 0xffffffff; /* XXX */ 509 510 /* 511 * When interrupt isn't routed correctly, give up probing cbb and do 512 * not kill pcic-compatible port. 513 * 514 * However, if we are using an ioapic, avoid this check -- pa_intrline 515 * may well be zero, with the interrupt routed through the apic. 516 */ 517 518 #if NIOAPIC == 0 && NACPI == 0 519 if ((0 == pa->pa_intrline) || (255 == pa->pa_intrline)) { 520 printf("%s: NOT USED because of unconfigured interrupt\n", 521 sc->sc_dev.dv_xname); 522 return; 523 } 524 #endif 525 526 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 527 528 /* pccbb_machdep.c end */ 529 530 #if defined CBB_DEBUG 531 { 532 static const char *intrname[] = { "NON", "A", "B", "C", "D" }; 533 printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname, 534 intrname[pa->pa_intrpin], pa->pa_intrline); 535 } 536 #endif 537 538 /* setup softc */ 539 sc->sc_pc = pc; 540 sc->sc_iot = pa->pa_iot; 541 sc->sc_memt = pa->pa_memt; 542 sc->sc_dmat = pa->pa_dmat; 543 sc->sc_tag = pa->pa_tag; 544 sc->sc_function = pa->pa_function; 545 sc->sc_sockbase = sock_base; 546 sc->sc_busnum = busreg; 547 548 memcpy(&sc->sc_pa, pa, sizeof(*pa)); 549 550 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 551 552 shutdownhook_establish(pccbb_shutdown, sc); 553 554 /* Disable legacy register mapping. */ 555 switch (sc->sc_chipset) { 556 case CB_RX5C46X: /* fallthrough */ 557 #if 0 558 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 559 case CB_RX5C47X: 560 #endif 561 /* 562 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 563 * cannot be disabled by substituting 0 into PCI_LEGACY 564 * register. Ricoh CardBus bridges have special bits on Bridge 565 * control reg (addr 0x3e on PCI config space). 566 */ 567 reg = pci_conf_read(pc, pa->pa_tag, PCI_BRIDGE_CONTROL_REG); 568 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 569 pci_conf_write(pc, pa->pa_tag, PCI_BRIDGE_CONTROL_REG, reg); 570 break; 571 572 default: 573 /* XXX I don't know proper way to kill legacy I/O. */ 574 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 575 break; 576 } 577 578 config_defer(self, pccbb_pci_callback); 579 } 580 581 582 583 584 /* 585 * static void pccbb_pci_callback(struct device *self) 586 * 587 * The actual attach routine: get memory space for YENTA register 588 * space, setup YENTA register and route interrupt. 589 * 590 * This function should be deferred because this device may obtain 591 * memory space dynamically. This function must avoid obtaining 592 * memory area which has already kept for another device. 593 */ 594 static void 595 pccbb_pci_callback(struct device *self) 596 { 597 struct pccbb_softc *sc = (void *)self; 598 pci_chipset_tag_t pc = sc->sc_pc; 599 pci_intr_handle_t ih; 600 const char *intrstr = NULL; 601 bus_addr_t sockbase; 602 struct cbslot_attach_args cba; 603 struct pcmciabus_attach_args paa; 604 struct cardslot_attach_args caa; 605 struct cardslot_softc *csc; 606 607 if (!(sc->sc_flags & CBB_MEMHMAPPED)) { 608 /* The socket registers aren't mapped correctly. */ 609 #if rbus 610 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 611 (sc->sc_chipset == CB_RX5C47X 612 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 613 0, &sockbase, &sc->sc_base_memh)) { 614 return; 615 } 616 sc->sc_base_memt = sc->sc_memt; 617 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 618 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 619 sc->sc_dev.dv_xname, (unsigned long)sockbase, 620 (unsigned long)pci_conf_read(pc, sc->sc_tag, 621 PCI_SOCKBASE))); 622 #else 623 sc->sc_base_memt = sc->sc_memt; 624 #if !defined CBB_PCI_BASE 625 #define CBB_PCI_BASE 0x20000000 626 #endif 627 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 628 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 629 /* cannot allocate memory space */ 630 return; 631 } 632 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 633 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 634 sc->sc_dev.dv_xname, (unsigned long)sock_base, 635 (unsigned long)pci_conf_read(pc, 636 sc->sc_tag, PCI_SOCKBASE))); 637 sc->sc_sockbase = sockbase; 638 #endif 639 sc->sc_flags |= CBB_MEMHMAPPED; 640 } 641 642 /* bus bridge initialization */ 643 pccbb_chipinit(sc); 644 645 /* clear data structure for child device interrupt handlers */ 646 LIST_INIT(&sc->sc_pil); 647 sc->sc_pil_intr_enable = 1; 648 649 /* Map and establish the interrupt. */ 650 if (pci_intr_map(&sc->sc_pa, &ih)) { 651 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 652 return; 653 } 654 intrstr = pci_intr_string(pc, ih); 655 656 /* 657 * XXX pccbbintr should be called under the priority lower 658 * than any other hard interupts. 659 */ 660 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 661 662 if (sc->sc_ih == NULL) { 663 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 664 if (intrstr != NULL) { 665 printf(" at %s", intrstr); 666 } 667 printf("\n"); 668 return; 669 } 670 671 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 672 powerhook_establish(sc->sc_dev.dv_xname, pccbb_powerhook, sc); 673 674 { 675 u_int32_t sockstat; 676 677 sockstat = bus_space_read_4(sc->sc_base_memt, 678 sc->sc_base_memh, CB_SOCKET_STAT); 679 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 680 sc->sc_flags |= CBB_CARDEXIST; 681 } 682 } 683 684 /* 685 * attach cardbus 686 */ 687 { 688 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 689 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 690 691 /* initialize cbslot_attach */ 692 cba.cba_busname = "cardbus"; 693 cba.cba_iot = sc->sc_iot; 694 cba.cba_memt = sc->sc_memt; 695 cba.cba_dmat = sc->sc_dmat; 696 cba.cba_bus = (busreg >> 8) & 0x0ff; 697 cba.cba_cc = (void *)sc; 698 cba.cba_cf = &pccbb_funcs; 699 cba.cba_intrline = sc->sc_pa.pa_intrline; 700 701 #if rbus 702 cba.cba_rbus_iot = sc->sc_rbus_iot; 703 cba.cba_rbus_memt = sc->sc_rbus_memt; 704 #endif 705 706 cba.cba_cacheline = PCI_CACHELINE(bhlc); 707 cba.cba_lattimer = PCI_LATTIMER(bhlc); 708 709 if (bootverbose) { 710 printf("%s: cacheline 0x%x lattimer 0x%x\n", 711 sc->sc_dev.dv_xname, cba.cba_cacheline, 712 cba.cba_lattimer); 713 printf("%s: bhlc 0x%x\n", 714 device_xname(&sc->sc_dev), bhlc); 715 } 716 #if defined SHOW_REGS 717 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 718 sc->sc_base_memh); 719 #endif 720 } 721 722 pccbb_pcmcia_attach_setup(sc, &paa); 723 caa.caa_cb_attach = NULL; 724 if (cba.cba_bus == 0) 725 printf("%s: secondary bus number uninitialized; try PCI_BUS_FIXUP\n", sc->sc_dev.dv_xname); 726 else 727 caa.caa_cb_attach = &cba; 728 caa.caa_16_attach = &paa; 729 caa.caa_ph = &sc->sc_pcmcia_h; 730 731 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 732 DPRINTF(("%s: found cardslot\n", __func__)); 733 sc->sc_csc = csc; 734 } 735 736 return; 737 } 738 739 740 741 742 743 /* 744 * static void pccbb_chipinit(struct pccbb_softc *sc) 745 * 746 * This function initialize YENTA chip registers listed below: 747 * 1) PCI command reg, 748 * 2) PCI and CardBus latency timer, 749 * 3) route PCI interrupt, 750 * 4) close all memory and io windows. 751 * 5) turn off bus power. 752 * 6) card detect and power cycle interrupts on. 753 * 7) clear interrupt 754 */ 755 static void 756 pccbb_chipinit(struct pccbb_softc *sc) 757 { 758 pci_chipset_tag_t pc = sc->sc_pc; 759 pcitag_t tag = sc->sc_tag; 760 bus_space_tag_t bmt = sc->sc_base_memt; 761 bus_space_handle_t bmh = sc->sc_base_memh; 762 pcireg_t bcr, bhlc, cbctl, csr, lscp, mfunc, slotctl, sockctl, sockmask, 763 sysctrl; 764 765 /* 766 * Set PCI command reg. 767 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 768 */ 769 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 770 /* I believe it is harmless. */ 771 csr |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 772 PCI_COMMAND_MASTER_ENABLE); 773 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 774 775 /* 776 * Set CardBus latency timer. 777 */ 778 lscp = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 779 if (PCI_CB_LATENCY(lscp) < 0x20) { 780 lscp &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 781 lscp |= (0x20 << PCI_CB_LATENCY_SHIFT); 782 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, lscp); 783 } 784 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 785 PCI_CB_LATENCY(lscp), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 786 787 /* 788 * Set PCI latency timer. 789 */ 790 bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG); 791 if (PCI_LATTIMER(bhlc) < 0x10) { 792 bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 793 bhlc |= (0x10 << PCI_LATTIMER_SHIFT); 794 pci_conf_write(pc, tag, PCI_BHLC_REG, bhlc); 795 } 796 DPRINTF(("PCI latency timer 0x%x (%x)\n", 797 PCI_LATTIMER(bhlc), pci_conf_read(pc, tag, PCI_BHLC_REG))); 798 799 800 /* Route functional interrupts to PCI. */ 801 bcr = pci_conf_read(pc, tag, PCI_BRIDGE_CONTROL_REG); 802 bcr |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 803 bcr |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 804 /* assert reset */ 805 bcr |= PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT; 806 pci_conf_write(pc, tag, PCI_BRIDGE_CONTROL_REG, bcr); 807 808 switch (sc->sc_chipset) { 809 case CB_TI113X: 810 cbctl = pci_conf_read(pc, tag, PCI_CBCTRL); 811 /* This bit is shared, but may read as 0 on some chips, so set 812 it explicitly on both functions. */ 813 cbctl |= PCI113X_CBCTRL_PCI_IRQ_ENA; 814 /* CSC intr enable */ 815 cbctl |= PCI113X_CBCTRL_PCI_CSC; 816 /* functional intr prohibit | prohibit ISA routing */ 817 cbctl &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 818 pci_conf_write(pc, tag, PCI_CBCTRL, cbctl); 819 break; 820 821 case CB_TI12XX: 822 /* 823 * Some TI 12xx (and [14][45]xx) based pci cards 824 * sometimes have issues with the MFUNC register not 825 * being initialized due to a bad EEPROM on board. 826 * Laptops that this matters on have this register 827 * properly initialized. 828 * 829 * The TI125X parts have a different register. 830 */ 831 mfunc = pci_conf_read(pc, tag, PCI12XX_MFUNC); 832 if (mfunc == 0) { 833 mfunc &= ~PCI12XX_MFUNC_PIN0; 834 mfunc |= PCI12XX_MFUNC_PIN0_INTA; 835 if ((pci_conf_read(pc, tag, PCI_SYSCTRL) & 836 PCI12XX_SYSCTRL_INTRTIE) == 0) { 837 mfunc &= ~PCI12XX_MFUNC_PIN1; 838 mfunc |= PCI12XX_MFUNC_PIN1_INTB; 839 } 840 pci_conf_write(pc, tag, PCI12XX_MFUNC, mfunc); 841 } 842 /* fallthrough */ 843 844 case CB_TI125X: 845 /* 846 * Disable zoom video. Some machines initialize this 847 * improperly and experience has shown that this helps 848 * prevent strange behavior. 849 */ 850 pci_conf_write(pc, tag, PCI12XX_MMCTRL, 0); 851 852 sysctrl = pci_conf_read(pc, tag, PCI_SYSCTRL); 853 sysctrl |= PCI12XX_SYSCTRL_VCCPROT; 854 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 855 cbctl = pci_conf_read(pc, tag, PCI_CBCTRL); 856 cbctl |= PCI12XX_CBCTRL_CSC; 857 pci_conf_write(pc, tag, PCI_CBCTRL, cbctl); 858 break; 859 860 case CB_TOPIC95B: 861 sockctl = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 862 sockctl |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 863 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, sockctl); 864 slotctl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 865 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 866 sc->sc_dev.dv_xname, slotctl)); 867 slotctl |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 868 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 869 slotctl &= ~TOPIC_SLOT_CTRL_SWDETECT; 870 DPRINTF(("0x%x\n", slotctl)); 871 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slotctl); 872 break; 873 874 case CB_TOPIC97: 875 slotctl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 876 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 877 sc->sc_dev.dv_xname, slotctl)); 878 slotctl |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 879 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 880 slotctl &= ~TOPIC_SLOT_CTRL_SWDETECT; 881 slotctl |= TOPIC97_SLOT_CTRL_PCIINT; 882 slotctl &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 883 DPRINTF(("0x%x\n", slotctl)); 884 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slotctl); 885 /* make sure to assert LV card support bits */ 886 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 887 0x800 + 0x3e, 888 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 889 0x800 + 0x3e) | 0x03); 890 break; 891 } 892 893 /* Close all memory and I/O windows. */ 894 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 895 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 896 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 897 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 898 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 899 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 900 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 901 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 902 903 /* reset 16-bit pcmcia bus */ 904 bus_space_write_1(bmt, bmh, 0x800 + PCIC_INTR, 905 bus_space_read_1(bmt, bmh, 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 906 907 /* turn off power */ 908 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 909 910 /* CSC Interrupt: Card detect and power cycle interrupts on */ 911 sockmask = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 912 sockmask |= CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; 913 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, sockmask); 914 /* reset interrupt */ 915 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 916 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 917 } 918 919 920 921 922 /* 923 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 924 * struct pcmciabus_attach_args *paa) 925 * 926 * This function attaches 16-bit PCcard bus. 927 */ 928 STATIC void 929 pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 930 struct pcmciabus_attach_args *paa) 931 { 932 struct pcic_handle *ph = &sc->sc_pcmcia_h; 933 #if rbus 934 rbus_tag_t rb; 935 #endif 936 937 /* initialize pcmcia part in pccbb_softc */ 938 ph->ph_parent = (struct device *)sc; 939 ph->sock = sc->sc_function; 940 ph->flags = 0; 941 ph->shutdown = 0; 942 ph->ih_irq = sc->sc_pa.pa_intrline; 943 ph->ph_bus_t = sc->sc_base_memt; 944 ph->ph_bus_h = sc->sc_base_memh; 945 ph->ph_read = pccbb_pcmcia_read; 946 ph->ph_write = pccbb_pcmcia_write; 947 sc->sc_pct = &pccbb_pcmcia_funcs; 948 949 /* 950 * We need to do a few things here: 951 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 952 * setting the IRQ numbers to 0. 953 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 954 * routing of CSC interrupts (e.g. card removal) to PCI while in 955 * PCMCIA mode. We just leave this set all the time. 956 * 3) Enable card insertion/removal interrupts in case the chip also 957 * needs that while in PCMCIA mode. 958 * 4) Clear any pending CSC interrupt. 959 */ 960 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE); 961 if (sc->sc_chipset == CB_TI113X) { 962 Pcic_write(ph, PCIC_CSC_INTR, 0); 963 } else { 964 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 965 Pcic_read(ph, PCIC_CSC); 966 } 967 968 /* initialize pcmcia bus attachment */ 969 paa->paa_busname = "pcmcia"; 970 paa->pct = sc->sc_pct; 971 paa->pch = ph; 972 paa->iobase = 0; /* I don't use them */ 973 paa->iosize = 0; 974 #if rbus 975 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 976 paa->iobase = rb->rb_start + rb->rb_offset; 977 paa->iosize = rb->rb_end - rb->rb_start; 978 #endif 979 980 return; 981 } 982 983 #if 0 984 STATIC void 985 pccbb_pcmcia_attach_card(struct pcic_handle *ph) 986 { 987 if (ph->flags & PCIC_FLAG_CARDP) { 988 panic("pccbb_pcmcia_attach_card: already attached"); 989 } 990 991 /* call the MI attach function */ 992 pcmcia_card_attach(ph->pcmcia); 993 994 ph->flags |= PCIC_FLAG_CARDP; 995 } 996 997 STATIC void 998 pccbb_pcmcia_detach_card(struct pcic_handle *ph, int flags) 999 { 1000 if (!(ph->flags & PCIC_FLAG_CARDP)) { 1001 panic("pccbb_pcmcia_detach_card: already detached"); 1002 } 1003 1004 ph->flags &= ~PCIC_FLAG_CARDP; 1005 1006 /* call the MI detach function */ 1007 pcmcia_card_detach(ph->pcmcia, flags); 1008 } 1009 #endif 1010 1011 /* 1012 * int pccbbintr(arg) 1013 * void *arg; 1014 * This routine handles the interrupt from Yenta PCI-CardBus bridge 1015 * itself. 1016 */ 1017 int 1018 pccbbintr(void *arg) 1019 { 1020 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1021 u_int32_t sockevent, sockstate; 1022 bus_space_tag_t memt = sc->sc_base_memt; 1023 bus_space_handle_t memh = sc->sc_base_memh; 1024 struct pcic_handle *ph = &sc->sc_pcmcia_h; 1025 1026 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 1027 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 1028 Pcic_read(ph, PCIC_CSC); 1029 1030 if (sockevent == 0) { 1031 /* This intr is not for me: it may be for my child devices. */ 1032 if (sc->sc_pil_intr_enable) { 1033 return pccbbintr_function(sc); 1034 } else { 1035 return 0; 1036 } 1037 } 1038 1039 aprint_debug("%s: enter sockevent %" PRIx32 "\n", __func__, sockevent); 1040 1041 if (sockevent & CB_SOCKET_EVENT_CD) { 1042 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1043 if (0x00 != (sockstate & CB_SOCKET_STAT_CD)) { 1044 /* A card should be removed. */ 1045 if (sc->sc_flags & CBB_CARDEXIST) { 1046 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 1047 sockevent)); 1048 DPRINTF((" card removed, 0x%08x\n", sockstate)); 1049 sc->sc_flags &= ~CBB_CARDEXIST; 1050 if (sc->sc_csc->sc_status & 1051 CARDSLOT_STATUS_CARD_16) { 1052 #if 0 1053 struct pcic_handle *ph = 1054 &sc->sc_pcmcia_h; 1055 1056 pcmcia_card_deactivate(ph->pcmcia); 1057 pccbb_pcmcia_socket_disable(ph); 1058 pccbb_pcmcia_detach_card(ph, 1059 DETACH_FORCE); 1060 #endif 1061 cardslot_event_throw(sc->sc_csc, 1062 CARDSLOT_EVENT_REMOVAL_16); 1063 } else if (sc->sc_csc->sc_status & 1064 CARDSLOT_STATUS_CARD_CB) { 1065 /* Cardbus intr removed */ 1066 cardslot_event_throw(sc->sc_csc, 1067 CARDSLOT_EVENT_REMOVAL_CB); 1068 } 1069 } else if (sc->sc_flags & CBB_INSERTING) { 1070 sc->sc_flags &= ~CBB_INSERTING; 1071 callout_stop(&sc->sc_insert_ch); 1072 } 1073 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 1074 /* 1075 * The pccbbintr may called from powerdown hook when 1076 * the system resumed, to detect the card 1077 * insertion/removal during suspension. 1078 */ 1079 (sc->sc_flags & CBB_CARDEXIST) == 0) { 1080 if (sc->sc_flags & CBB_INSERTING) { 1081 callout_stop(&sc->sc_insert_ch); 1082 } 1083 callout_schedule(&sc->sc_insert_ch, hz / 5); 1084 sc->sc_flags |= CBB_INSERTING; 1085 } 1086 } 1087 1088 if (sockevent & CB_SOCKET_EVENT_POWER) { 1089 DPRINTF(("Powercycling because of socket event\n")); 1090 /* XXX: Does not happen when attaching a 16-bit card */ 1091 sc->sc_pwrcycle++; 1092 wakeup(&sc->sc_pwrcycle); 1093 } 1094 1095 return (1); 1096 } 1097 1098 /* 1099 * static int pccbbintr_function(struct pccbb_softc *sc) 1100 * 1101 * This function calls each interrupt handler registered at the 1102 * bridge. The interrupt handlers are called in registered order. 1103 */ 1104 static int 1105 pccbbintr_function(struct pccbb_softc *sc) 1106 { 1107 int retval = 0, val; 1108 struct pccbb_intrhand_list *pil; 1109 int s; 1110 1111 for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1112 pil = LIST_NEXT(pil, pil_next)) { 1113 s = splraiseipl(pil->pil_icookie); 1114 val = (*pil->pil_func)(pil->pil_arg); 1115 splx(s); 1116 1117 retval = retval == 1 ? 1 : 1118 retval == 0 ? val : val != 0 ? val : retval; 1119 } 1120 1121 return retval; 1122 } 1123 1124 static void 1125 pci113x_insert(void *arg) 1126 { 1127 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1128 u_int32_t sockevent, sockstate; 1129 1130 if (!(sc->sc_flags & CBB_INSERTING)) { 1131 /* We add a card only under inserting state. */ 1132 return; 1133 } 1134 sc->sc_flags &= ~CBB_INSERTING; 1135 1136 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1137 CB_SOCKET_EVENT); 1138 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1139 CB_SOCKET_STAT); 1140 1141 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1142 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1143 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1144 sc->sc_flags |= CBB_CARDEXIST; 1145 /* call pccard interrupt handler here */ 1146 if (sockstate & CB_SOCKET_STAT_16BIT) { 1147 /* 16-bit card found */ 1148 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1149 cardslot_event_throw(sc->sc_csc, 1150 CARDSLOT_EVENT_INSERTION_16); 1151 } else if (sockstate & CB_SOCKET_STAT_CB) { 1152 /* cardbus card found */ 1153 /* cardbus_attach_card(sc->sc_csc); */ 1154 cardslot_event_throw(sc->sc_csc, 1155 CARDSLOT_EVENT_INSERTION_CB); 1156 } else { 1157 /* who are you? */ 1158 } 1159 } else { 1160 callout_schedule(&sc->sc_insert_ch, hz / 10); 1161 } 1162 } 1163 1164 #define PCCBB_PCMCIA_OFFSET 0x800 1165 static u_int8_t 1166 pccbb_pcmcia_read(struct pcic_handle *ph, int reg) 1167 { 1168 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1169 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1170 1171 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1172 PCCBB_PCMCIA_OFFSET + reg); 1173 } 1174 1175 static void 1176 pccbb_pcmcia_write(struct pcic_handle *ph, int reg, u_int8_t val) 1177 { 1178 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1179 val); 1180 1181 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1182 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1183 } 1184 1185 /* 1186 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1187 */ 1188 STATIC int 1189 pccbb_ctrl(cardbus_chipset_tag_t ct, int command) 1190 { 1191 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1192 1193 switch (command) { 1194 case CARDBUS_CD: 1195 if (2 == pccbb_detect_card(sc)) { 1196 int retval = 0; 1197 int status = cb_detect_voltage(sc); 1198 if (PCCARD_VCC_5V & status) { 1199 retval |= CARDBUS_5V_CARD; 1200 } 1201 if (PCCARD_VCC_3V & status) { 1202 retval |= CARDBUS_3V_CARD; 1203 } 1204 if (PCCARD_VCC_XV & status) { 1205 retval |= CARDBUS_XV_CARD; 1206 } 1207 if (PCCARD_VCC_YV & status) { 1208 retval |= CARDBUS_YV_CARD; 1209 } 1210 return retval; 1211 } else { 1212 return 0; 1213 } 1214 case CARDBUS_RESET: 1215 return cb_reset(sc); 1216 case CARDBUS_IO_ENABLE: /* fallthrough */ 1217 case CARDBUS_IO_DISABLE: /* fallthrough */ 1218 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1219 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1220 case CARDBUS_BM_ENABLE: /* fallthrough */ 1221 case CARDBUS_BM_DISABLE: /* fallthrough */ 1222 /* XXX: I think we don't need to call this function below. */ 1223 return pccbb_cardenable(sc, command); 1224 } 1225 1226 return 0; 1227 } 1228 1229 /* 1230 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1231 * This function returns true when it succeeds and returns false when 1232 * it fails. 1233 */ 1234 STATIC int 1235 pccbb_power(cardbus_chipset_tag_t ct, int command) 1236 { 1237 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1238 u_int32_t status, osock_ctrl, sock_ctrl, reg_ctrl; 1239 bus_space_tag_t memt = sc->sc_base_memt; 1240 bus_space_handle_t memh = sc->sc_base_memh; 1241 int on = 0, pwrcycle, s, times; 1242 struct timeval before, after, diff; 1243 1244 DPRINTF(("pccbb_power: %s and %s [0x%x]\n", 1245 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1246 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1247 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1248 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1249 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1250 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1251 "UNKNOWN", 1252 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1253 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1254 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1255 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1256 "UNKNOWN", command)); 1257 1258 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1259 osock_ctrl = sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1260 1261 switch (command & CARDBUS_VCCMASK) { 1262 case CARDBUS_VCC_UC: 1263 break; 1264 case CARDBUS_VCC_5V: 1265 on++; 1266 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1267 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1268 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1269 } else { 1270 printf("%s: BAD voltage request: no 5 V card\n", 1271 sc->sc_dev.dv_xname); 1272 return 0; 1273 } 1274 break; 1275 case CARDBUS_VCC_3V: 1276 on++; 1277 if (CB_SOCKET_STAT_3VCARD & status) { 1278 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1279 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1280 } else { 1281 printf("%s: BAD voltage request: no 3.3 V card\n", 1282 sc->sc_dev.dv_xname); 1283 return 0; 1284 } 1285 break; 1286 case CARDBUS_VCC_0V: 1287 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1288 break; 1289 default: 1290 return 0; /* power NEVER changed */ 1291 } 1292 1293 switch (command & CARDBUS_VPPMASK) { 1294 case CARDBUS_VPP_UC: 1295 break; 1296 case CARDBUS_VPP_0V: 1297 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1298 break; 1299 case CARDBUS_VPP_VCC: 1300 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1301 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1302 break; 1303 case CARDBUS_VPP_12V: 1304 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1305 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1306 break; 1307 } 1308 1309 pwrcycle = sc->sc_pwrcycle; 1310 aprint_debug("%s: osock_ctrl %#" PRIx32 " sock_ctrl %#" PRIx32 "\n", 1311 device_xname(&sc->sc_dev), osock_ctrl, sock_ctrl); 1312 1313 microtime(&before); 1314 s = splbio(); 1315 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1316 1317 /* 1318 * Wait as long as 200ms for a power-cycle interrupt. If 1319 * interrupts are enabled, but the socket has already 1320 * changed to the desired status, keep waiting for the 1321 * interrupt. "Consuming" the interrupt in this way keeps 1322 * the interrupt from prematurely waking some subsequent 1323 * pccbb_power call. 1324 * 1325 * XXX Not every bridge interrupts on the ->OFF transition. 1326 * XXX That's ok, we will time-out after 200ms. 1327 * 1328 * XXX The power cycle event will never happen when attaching 1329 * XXX a 16-bit card. That's ok, we will time-out after 1330 * XXX 200ms. 1331 */ 1332 for (times = 5; --times >= 0; ) { 1333 if (cold) 1334 DELAY(40 * 1000); 1335 else { 1336 (void)tsleep(&sc->sc_pwrcycle, PWAIT, "pccpwr", 1337 hz / 25); 1338 if (pwrcycle == sc->sc_pwrcycle) 1339 continue; 1340 } 1341 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1342 if ((status & CB_SOCKET_STAT_PWRCYCLE) != 0 && on) 1343 break; 1344 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0 && !on) 1345 break; 1346 } 1347 splx(s); 1348 microtime(&after); 1349 timersub(&after, &before, &diff); 1350 aprint_debug("%s: wait took%s %ld.%06lds\n", sc->sc_dev.dv_xname, 1351 (on && times < 0) ? " too long" : "", diff.tv_sec, diff.tv_usec); 1352 1353 /* 1354 * Ok, wait a bit longer for things to settle. 1355 */ 1356 if (on && sc->sc_chipset == CB_TOPIC95B) 1357 delay_ms(100, sc); 1358 1359 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1360 1361 if (on && sc->sc_chipset != CB_TOPIC95B) { 1362 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0) 1363 printf("%s: power on failed?\n", sc->sc_dev.dv_xname); 1364 } 1365 1366 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1367 printf("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1368 sc->sc_dev.dv_xname, sock_ctrl, status); 1369 printf("%s: disabling socket\n", sc->sc_dev.dv_xname); 1370 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1371 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1372 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1373 status &= ~CB_SOCKET_STAT_BADVCC; 1374 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, status); 1375 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1376 CB_SOCKET_STAT)); 1377 return 0; 1378 } 1379 1380 if (sc->sc_chipset == CB_TOPIC97) { 1381 reg_ctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL); 1382 reg_ctrl &= ~TOPIC97_REG_CTRL_TESTMODE; 1383 if ((command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V) 1384 reg_ctrl &= ~TOPIC97_REG_CTRL_CLKRUN_ENA; 1385 else 1386 reg_ctrl |= TOPIC97_REG_CTRL_CLKRUN_ENA; 1387 pci_conf_write(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL, reg_ctrl); 1388 } 1389 1390 return 1; /* power changed correctly */ 1391 } 1392 1393 #if defined CB_PCMCIA_POLL 1394 struct cb_poll_str { 1395 void *arg; 1396 int (*func)(void *); 1397 int level; 1398 pccard_chipset_tag_t ct; 1399 int count; 1400 struct callout poll_ch; 1401 }; 1402 1403 static struct cb_poll_str cb_poll[10]; 1404 static int cb_poll_n = 0; 1405 1406 static void cb_pcmcia_poll(void *arg); 1407 1408 static void 1409 cb_pcmcia_poll(void *arg) 1410 { 1411 struct cb_poll_str *poll = arg; 1412 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1413 struct pccbb_softc *sc = psc->cpc_parent; 1414 int s; 1415 u_int32_t spsr; /* socket present-state reg */ 1416 1417 callout_reset(&poll->poll_ch, hz / 10, cb_pcmcia_poll, poll); 1418 switch (poll->level) { 1419 case IPL_NET: 1420 s = splnet(); 1421 break; 1422 case IPL_BIO: 1423 s = splbio(); 1424 break; 1425 case IPL_TTY: /* fallthrough */ 1426 default: 1427 s = spltty(); 1428 break; 1429 } 1430 1431 spsr = 1432 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1433 CB_SOCKET_STAT); 1434 1435 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1436 if (!(spsr & 0x40)) { /* CINT low */ 1437 #else 1438 if (1) { 1439 #endif 1440 if ((*poll->func) (poll->arg) == 1) { 1441 ++poll->count; 1442 printf("intr: reported from poller, 0x%x\n", spsr); 1443 #if defined LEVEL2 1444 } else { 1445 printf("intr: miss! 0x%x\n", spsr); 1446 #endif 1447 } 1448 } 1449 splx(s); 1450 } 1451 #endif /* defined CB_PCMCIA_POLL */ 1452 1453 /* 1454 * static int pccbb_detect_card(struct pccbb_softc *sc) 1455 * return value: 0 if no card exists. 1456 * 1 if 16-bit card exists. 1457 * 2 if cardbus card exists. 1458 */ 1459 static int 1460 pccbb_detect_card(struct pccbb_softc *sc) 1461 { 1462 bus_space_handle_t base_memh = sc->sc_base_memh; 1463 bus_space_tag_t base_memt = sc->sc_base_memt; 1464 u_int32_t sockstat = 1465 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1466 int retval = 0; 1467 1468 /* CD1 and CD2 asserted */ 1469 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1470 /* card must be present */ 1471 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1472 /* NOTACARD DEASSERTED */ 1473 if (CB_SOCKET_STAT_CB & sockstat) { 1474 /* CardBus mode */ 1475 retval = 2; 1476 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1477 /* 16-bit mode */ 1478 retval = 1; 1479 } 1480 } 1481 } 1482 return retval; 1483 } 1484 1485 /* 1486 * STATIC int cb_reset(struct pccbb_softc *sc) 1487 * This function resets CardBus card. 1488 */ 1489 STATIC int 1490 cb_reset(struct pccbb_softc *sc) 1491 { 1492 /* 1493 * Reset Assert at least 20 ms 1494 * Some machines request longer duration. 1495 */ 1496 int reset_duration = 1497 (sc->sc_chipset == CB_RX5C47X ? 400 : 50); 1498 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1499 1500 /* Reset bit Assert (bit 6 at 0x3E) */ 1501 bcr |= CB_BCR_RESET_ENABLE; 1502 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr); 1503 delay_ms(reset_duration, sc); 1504 1505 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1506 /* Reset bit Deassert (bit 6 at 0x3E) */ 1507 bcr &= ~CB_BCR_RESET_ENABLE; 1508 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr); 1509 delay_ms(reset_duration, sc); 1510 } 1511 /* No card found on the slot. Keep Reset. */ 1512 return 1; 1513 } 1514 1515 /* 1516 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1517 * This function detect card Voltage. 1518 */ 1519 STATIC int 1520 cb_detect_voltage(struct pccbb_softc *sc) 1521 { 1522 u_int32_t psr; /* socket present-state reg */ 1523 bus_space_tag_t iot = sc->sc_base_memt; 1524 bus_space_handle_t ioh = sc->sc_base_memh; 1525 int vol = PCCARD_VCC_UKN; /* set 0 */ 1526 1527 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1528 1529 if (0x400u & psr) { 1530 vol |= PCCARD_VCC_5V; 1531 } 1532 if (0x800u & psr) { 1533 vol |= PCCARD_VCC_3V; 1534 } 1535 1536 return vol; 1537 } 1538 1539 STATIC int 1540 cbbprint(void *aux, const char *pcic) 1541 { 1542 #if 0 1543 struct cbslot_attach_args *cba = aux; 1544 1545 if (cba->cba_slot >= 0) { 1546 aprint_normal(" slot %d", cba->cba_slot); 1547 } 1548 #endif 1549 return UNCONF; 1550 } 1551 1552 /* 1553 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1554 * This function enables and disables the card 1555 */ 1556 STATIC int 1557 pccbb_cardenable(struct pccbb_softc *sc, int function) 1558 { 1559 u_int32_t command = 1560 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1561 1562 DPRINTF(("pccbb_cardenable:")); 1563 switch (function) { 1564 case CARDBUS_IO_ENABLE: 1565 command |= PCI_COMMAND_IO_ENABLE; 1566 break; 1567 case CARDBUS_IO_DISABLE: 1568 command &= ~PCI_COMMAND_IO_ENABLE; 1569 break; 1570 case CARDBUS_MEM_ENABLE: 1571 command |= PCI_COMMAND_MEM_ENABLE; 1572 break; 1573 case CARDBUS_MEM_DISABLE: 1574 command &= ~PCI_COMMAND_MEM_ENABLE; 1575 break; 1576 case CARDBUS_BM_ENABLE: 1577 command |= PCI_COMMAND_MASTER_ENABLE; 1578 break; 1579 case CARDBUS_BM_DISABLE: 1580 command &= ~PCI_COMMAND_MASTER_ENABLE; 1581 break; 1582 default: 1583 return 0; 1584 } 1585 1586 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1587 DPRINTF((" command reg 0x%x\n", command)); 1588 return 1; 1589 } 1590 1591 #if !rbus 1592 static int 1593 pccbb_io_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 1594 { 1595 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1596 int basereg; 1597 int limitreg; 1598 1599 if ((win < 0) || (win > 2)) { 1600 #if defined DIAGNOSTIC 1601 printf("cardbus_io_open: window out of range %d\n", win); 1602 #endif 1603 return 0; 1604 } 1605 1606 basereg = win * 8 + 0x2c; 1607 limitreg = win * 8 + 0x30; 1608 1609 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1610 start, basereg, end, limitreg)); 1611 1612 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1613 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1614 return 1; 1615 } 1616 1617 /* 1618 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1619 */ 1620 static int 1621 pccbb_io_close(cardbus_chipset_tag_t ct, int win) 1622 { 1623 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1624 int basereg; 1625 int limitreg; 1626 1627 if ((win < 0) || (win > 2)) { 1628 #if defined DIAGNOSTIC 1629 printf("cardbus_io_close: window out of range %d\n", win); 1630 #endif 1631 return 0; 1632 } 1633 1634 basereg = win * 8 + 0x2c; 1635 limitreg = win * 8 + 0x30; 1636 1637 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1638 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1639 return 1; 1640 } 1641 1642 static int 1643 pccbb_mem_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 1644 { 1645 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1646 int basereg; 1647 int limitreg; 1648 1649 if ((win < 0) || (win > 2)) { 1650 #if defined DIAGNOSTIC 1651 printf("cardbus_mem_open: window out of range %d\n", win); 1652 #endif 1653 return 0; 1654 } 1655 1656 basereg = win * 8 + 0x1c; 1657 limitreg = win * 8 + 0x20; 1658 1659 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1660 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1661 return 1; 1662 } 1663 1664 static int 1665 pccbb_mem_close(cardbus_chipset_tag_t ct, int win) 1666 { 1667 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1668 int basereg; 1669 int limitreg; 1670 1671 if ((win < 0) || (win > 2)) { 1672 #if defined DIAGNOSTIC 1673 printf("cardbus_mem_close: window out of range %d\n", win); 1674 #endif 1675 return 0; 1676 } 1677 1678 basereg = win * 8 + 0x1c; 1679 limitreg = win * 8 + 0x20; 1680 1681 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1682 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1683 return 1; 1684 } 1685 #endif 1686 1687 /* 1688 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1689 * int irq, 1690 * int level, 1691 * int (* func)(void *), 1692 * void *arg) 1693 * 1694 * This function registers an interrupt handler at the bridge, in 1695 * order not to call the interrupt handlers of child devices when 1696 * a card-deletion interrupt occurs. 1697 * 1698 * The arguments irq and level are not used. 1699 */ 1700 static void * 1701 pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, int irq, int level, 1702 int (*func)(void *), void *arg) 1703 { 1704 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1705 1706 return pccbb_intr_establish(sc, irq, level, func, arg); 1707 } 1708 1709 1710 /* 1711 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1712 * void *ih) 1713 * 1714 * This function removes an interrupt handler pointed by ih. 1715 */ 1716 static void 1717 pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih) 1718 { 1719 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1720 1721 pccbb_intr_disestablish(sc, ih); 1722 } 1723 1724 1725 void 1726 pccbb_intr_route(struct pccbb_softc *sc) 1727 { 1728 pcireg_t bcr, cbctrl; 1729 1730 /* initialize bridge intr routing */ 1731 bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1732 bcr &= ~CB_BCR_INTR_IREQ_ENABLE; 1733 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr); 1734 1735 switch (sc->sc_chipset) { 1736 case CB_TI113X: 1737 cbctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1738 /* functional intr enabled */ 1739 cbctrl |= PCI113X_CBCTRL_PCI_INTR; 1740 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, cbctrl); 1741 break; 1742 default: 1743 break; 1744 } 1745 } 1746 1747 /* 1748 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1749 * int irq, 1750 * int level, 1751 * int (* func)(void *), 1752 * void *arg) 1753 * 1754 * This function registers an interrupt handler at the bridge, in 1755 * order not to call the interrupt handlers of child devices when 1756 * a card-deletion interrupt occurs. 1757 * 1758 * The arguments irq is not used because pccbb selects intr vector. 1759 */ 1760 static void * 1761 pccbb_intr_establish(struct pccbb_softc *sc, int irq, int level, 1762 int (*func)(void *), void *arg) 1763 { 1764 struct pccbb_intrhand_list *pil, *newpil; 1765 1766 DPRINTF(("pccbb_intr_establish start. %p\n", LIST_FIRST(&sc->sc_pil))); 1767 1768 if (LIST_EMPTY(&sc->sc_pil)) { 1769 pccbb_intr_route(sc); 1770 } 1771 1772 /* 1773 * Allocate a room for interrupt handler structure. 1774 */ 1775 if (NULL == (newpil = 1776 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1777 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1778 return NULL; 1779 } 1780 1781 newpil->pil_func = func; 1782 newpil->pil_arg = arg; 1783 newpil->pil_icookie = makeiplcookie(level); 1784 1785 if (LIST_EMPTY(&sc->sc_pil)) { 1786 LIST_INSERT_HEAD(&sc->sc_pil, newpil, pil_next); 1787 } else { 1788 for (pil = LIST_FIRST(&sc->sc_pil); 1789 LIST_NEXT(pil, pil_next) != NULL; 1790 pil = LIST_NEXT(pil, pil_next)); 1791 LIST_INSERT_AFTER(pil, newpil, pil_next); 1792 } 1793 1794 DPRINTF(("pccbb_intr_establish add pil. %p\n", 1795 LIST_FIRST(&sc->sc_pil))); 1796 1797 return newpil; 1798 } 1799 1800 /* 1801 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1802 * void *ih) 1803 * 1804 * This function removes an interrupt handler pointed by ih. ih 1805 * should be the value returned by cardbus_intr_establish() or 1806 * NULL. 1807 * 1808 * When ih is NULL, this function will do nothing. 1809 */ 1810 static void 1811 pccbb_intr_disestablish(struct pccbb_softc *sc, void *ih) 1812 { 1813 struct pccbb_intrhand_list *pil; 1814 pcireg_t reg; 1815 1816 DPRINTF(("pccbb_intr_disestablish start. %p\n", 1817 LIST_FIRST(&sc->sc_pil))); 1818 1819 if (ih == NULL) { 1820 /* intr handler is not set */ 1821 DPRINTF(("pccbb_intr_disestablish: no ih\n")); 1822 return; 1823 } 1824 1825 #ifdef DIAGNOSTIC 1826 for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1827 pil = LIST_NEXT(pil, pil_next)) { 1828 DPRINTF(("pccbb_intr_disestablish: pil %p\n", pil)); 1829 if (pil == ih) { 1830 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1831 break; 1832 } 1833 } 1834 if (pil == NULL) { 1835 panic("pccbb_intr_disestablish: %s cannot find pil %p", 1836 sc->sc_dev.dv_xname, ih); 1837 } 1838 #endif 1839 1840 pil = (struct pccbb_intrhand_list *)ih; 1841 LIST_REMOVE(pil, pil_next); 1842 free(pil, M_DEVBUF); 1843 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1844 1845 if (LIST_EMPTY(&sc->sc_pil)) { 1846 /* No interrupt handlers */ 1847 1848 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1849 1850 /* stop routing PCI intr */ 1851 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1852 reg |= CB_BCR_INTR_IREQ_ENABLE; 1853 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, reg); 1854 1855 switch (sc->sc_chipset) { 1856 case CB_TI113X: 1857 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1858 /* functional intr disabled */ 1859 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1860 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1861 break; 1862 default: 1863 break; 1864 } 1865 } 1866 } 1867 1868 #if defined SHOW_REGS 1869 static void 1870 cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, bus_space_tag_t memt, 1871 bus_space_handle_t memh) 1872 { 1873 int i; 1874 printf("PCI config regs:"); 1875 for (i = 0; i < 0x50; i += 4) { 1876 if (i % 16 == 0) 1877 printf("\n 0x%02x:", i); 1878 printf(" %08x", pci_conf_read(pc, tag, i)); 1879 } 1880 for (i = 0x80; i < 0xb0; i += 4) { 1881 if (i % 16 == 0) 1882 printf("\n 0x%02x:", i); 1883 printf(" %08x", pci_conf_read(pc, tag, i)); 1884 } 1885 1886 if (memh == 0) { 1887 printf("\n"); 1888 return; 1889 } 1890 1891 printf("\nsocket regs:"); 1892 for (i = 0; i <= 0x10; i += 0x04) 1893 printf(" %08x", bus_space_read_4(memt, memh, i)); 1894 printf("\nExCA regs:"); 1895 for (i = 0; i < 0x08; ++i) 1896 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1897 printf("\n"); 1898 return; 1899 } 1900 #endif 1901 1902 /* 1903 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1904 * int busno, int function) 1905 * This is the function to make a tag to access config space of 1906 * a CardBus Card. It works same as pci_conf_read. 1907 */ 1908 static cardbustag_t 1909 pccbb_make_tag(cardbus_chipset_tag_t cc, int busno, int function) 1910 { 1911 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1912 1913 return pci_make_tag(sc->sc_pc, busno, 0, function); 1914 } 1915 1916 static void 1917 pccbb_free_tag(cardbus_chipset_tag_t cc, cardbustag_t tag) 1918 { 1919 } 1920 1921 /* 1922 * pccbb_conf_read 1923 * 1924 * This is the function to read the config space of a CardBus card. 1925 * It works the same as pci_conf_read(9). 1926 */ 1927 static cardbusreg_t 1928 pccbb_conf_read(cardbus_chipset_tag_t cc, cardbustag_t tag, int offset) 1929 { 1930 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1931 1932 return pci_conf_read(sc->sc_pc, tag, offset); 1933 } 1934 1935 /* 1936 * pccbb_conf_write 1937 * 1938 * This is the function to write the config space of a CardBus 1939 * card. It works the same as pci_conf_write(9). 1940 */ 1941 static void 1942 pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, int reg, 1943 cardbusreg_t val) 1944 { 1945 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1946 1947 pci_conf_write(sc->sc_pc, tag, reg, val); 1948 } 1949 1950 #if 0 1951 STATIC int 1952 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1953 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 1954 int speed, int flags, 1955 bus_space_handle_t * iohp) 1956 #endif 1957 /* 1958 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1959 * bus_addr_t start, bus_size_t size, 1960 * bus_size_t align, 1961 * struct pcmcia_io_handle *pcihp 1962 * 1963 * This function only allocates I/O region for pccard. This function 1964 * never maps the allocated region to pccard I/O area. 1965 * 1966 * XXX: The interface of this function is not very good, I believe. 1967 */ 1968 STATIC int 1969 pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, 1970 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 1971 { 1972 struct pcic_handle *ph = (struct pcic_handle *)pch; 1973 bus_addr_t ioaddr; 1974 int flags = 0; 1975 bus_space_tag_t iot; 1976 bus_space_handle_t ioh; 1977 bus_addr_t mask; 1978 #if rbus 1979 rbus_tag_t rb; 1980 #endif 1981 if (align == 0) { 1982 align = size; /* XXX: funny??? */ 1983 } 1984 1985 if (start != 0) { 1986 /* XXX: assume all card decode lower 10 bits by its hardware */ 1987 mask = 0x3ff; 1988 /* enforce to use only masked address */ 1989 start &= mask; 1990 } else { 1991 /* 1992 * calculate mask: 1993 * 1. get the most significant bit of size (call it msb). 1994 * 2. compare msb with the value of size. 1995 * 3. if size is larger, shift msb left once. 1996 * 4. obtain mask value to decrement msb. 1997 */ 1998 bus_size_t size_tmp = size; 1999 int shifts = 0; 2000 2001 mask = 1; 2002 while (size_tmp) { 2003 ++shifts; 2004 size_tmp >>= 1; 2005 } 2006 mask = (1 << shifts); 2007 if (mask < size) { 2008 mask <<= 1; 2009 } 2010 --mask; 2011 } 2012 2013 /* 2014 * Allocate some arbitrary I/O space. 2015 */ 2016 2017 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 2018 2019 #if rbus 2020 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 2021 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 2022 return 1; 2023 } 2024 DPRINTF(("pccbb_pcmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2025 (u_long) ioaddr, (u_long) size)); 2026 #else 2027 if (start) { 2028 ioaddr = start; 2029 if (bus_space_map(iot, start, size, 0, &ioh)) { 2030 return 1; 2031 } 2032 DPRINTF(("pccbb_pcmcia_io_alloc map port 0x%lx+0x%lx\n", 2033 (u_long) ioaddr, (u_long) size)); 2034 } else { 2035 flags |= PCMCIA_IO_ALLOCATED; 2036 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 2037 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 2038 size, align, 0, 0, &ioaddr, &ioh)) { 2039 /* No room be able to be get. */ 2040 return 1; 2041 } 2042 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2043 (u_long) ioaddr, (u_long) size)); 2044 } 2045 #endif 2046 2047 pcihp->iot = iot; 2048 pcihp->ioh = ioh; 2049 pcihp->addr = ioaddr; 2050 pcihp->size = size; 2051 pcihp->flags = flags; 2052 2053 return 0; 2054 } 2055 2056 /* 2057 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2058 * struct pcmcia_io_handle *pcihp) 2059 * 2060 * This function only frees I/O region for pccard. 2061 * 2062 * XXX: The interface of this function is not very good, I believe. 2063 */ 2064 void 2065 pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2066 struct pcmcia_io_handle *pcihp) 2067 { 2068 #if !rbus 2069 bus_space_tag_t iot = pcihp->iot; 2070 #endif 2071 bus_space_handle_t ioh = pcihp->ioh; 2072 bus_size_t size = pcihp->size; 2073 2074 #if rbus 2075 struct pccbb_softc *sc = 2076 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 2077 rbus_tag_t rb = sc->sc_rbus_iot; 2078 2079 rbus_space_free(rb, ioh, size, NULL); 2080 #else 2081 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 2082 bus_space_free(iot, ioh, size); 2083 else 2084 bus_space_unmap(iot, ioh, size); 2085 #endif 2086 } 2087 2088 /* 2089 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 2090 * bus_addr_t offset, bus_size_t size, 2091 * struct pcmcia_io_handle *pcihp, 2092 * int *windowp) 2093 * 2094 * This function maps the allocated I/O region to pccard. This function 2095 * never allocates any I/O region for pccard I/O area. I don't 2096 * understand why the original authors of pcmciabus separated alloc and 2097 * map. I believe the two must be unite. 2098 * 2099 * XXX: no wait timing control? 2100 */ 2101 int 2102 pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, bus_addr_t offset, 2103 bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp) 2104 { 2105 struct pcic_handle *ph = (struct pcic_handle *)pch; 2106 bus_addr_t ioaddr = pcihp->addr + offset; 2107 int i, win; 2108 #if defined CBB_DEBUG 2109 static const char *width_names[] = { "dynamic", "io8", "io16" }; 2110 #endif 2111 2112 /* Sanity check I/O handle. */ 2113 2114 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 2115 panic("pccbb_pcmcia_io_map iot is bogus"); 2116 } 2117 2118 /* XXX Sanity check offset/size. */ 2119 2120 win = -1; 2121 for (i = 0; i < PCIC_IO_WINS; i++) { 2122 if ((ph->ioalloc & (1 << i)) == 0) { 2123 win = i; 2124 ph->ioalloc |= (1 << i); 2125 break; 2126 } 2127 } 2128 2129 if (win == -1) { 2130 return 1; 2131 } 2132 2133 *windowp = win; 2134 2135 /* XXX this is pretty gross */ 2136 2137 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2138 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2139 2140 /* XXX wtf is this doing here? */ 2141 2142 #if 0 2143 printf(" port 0x%lx", (u_long) ioaddr); 2144 if (size > 1) { 2145 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2146 } 2147 #endif 2148 2149 ph->io[win].addr = ioaddr; 2150 ph->io[win].size = size; 2151 ph->io[win].width = width; 2152 2153 /* actual dirty register-value changing in the function below. */ 2154 pccbb_pcmcia_do_io_map(ph, win); 2155 2156 return 0; 2157 } 2158 2159 /* 2160 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2161 * 2162 * This function changes register-value to map I/O region for pccard. 2163 */ 2164 static void 2165 pccbb_pcmcia_do_io_map(struct pcic_handle *ph, int win) 2166 { 2167 static u_int8_t pcic_iowidth[3] = { 2168 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2169 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2170 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2171 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2172 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2173 }; 2174 2175 #define PCIC_SIA_START_LOW 0 2176 #define PCIC_SIA_START_HIGH 1 2177 #define PCIC_SIA_STOP_LOW 2 2178 #define PCIC_SIA_STOP_HIGH 3 2179 2180 int regbase_win = 0x8 + win * 0x04; 2181 u_int8_t ioctl, enable; 2182 2183 DPRINTF(("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx " 2184 "width %d\n", win, (unsigned long)ph->io[win].addr, 2185 (unsigned long)ph->io[win].size, ph->io[win].width * 8)); 2186 2187 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2188 ph->io[win].addr & 0xff); 2189 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2190 (ph->io[win].addr >> 8) & 0xff); 2191 2192 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2193 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2194 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2195 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2196 2197 ioctl = Pcic_read(ph, PCIC_IOCTL); 2198 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2199 switch (win) { 2200 case 0: 2201 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2202 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2203 PCIC_IOCTL_IO0_DATASIZE_MASK); 2204 ioctl |= pcic_iowidth[ph->io[win].width]; 2205 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2206 break; 2207 case 1: 2208 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2209 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2210 PCIC_IOCTL_IO1_DATASIZE_MASK); 2211 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2212 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2213 break; 2214 } 2215 Pcic_write(ph, PCIC_IOCTL, ioctl); 2216 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2217 #if defined(CBB_DEBUG) 2218 { 2219 u_int8_t start_low = 2220 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2221 u_int8_t start_high = 2222 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2223 u_int8_t stop_low = 2224 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2225 u_int8_t stop_high = 2226 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2227 printf("pccbb_pcmcia_do_io_map start %02x %02x, " 2228 "stop %02x %02x, ioctl %02x enable %02x\n", 2229 start_low, start_high, stop_low, stop_high, ioctl, enable); 2230 } 2231 #endif 2232 } 2233 2234 /* 2235 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2236 * 2237 * This function unmaps I/O region. No return value. 2238 */ 2239 STATIC void 2240 pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t pch, int win) 2241 { 2242 struct pcic_handle *ph = (struct pcic_handle *)pch; 2243 int reg; 2244 2245 if (win >= PCIC_IO_WINS || win < 0) { 2246 panic("pccbb_pcmcia_io_unmap: window out of range"); 2247 } 2248 2249 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2250 switch (win) { 2251 case 0: 2252 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2253 break; 2254 case 1: 2255 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2256 break; 2257 } 2258 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2259 2260 ph->ioalloc &= ~(1 << win); 2261 } 2262 2263 static int 2264 pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 2265 { 2266 u_int8_t stat; 2267 int i; 2268 2269 /* wait an initial 10ms for quick cards */ 2270 stat = Pcic_read(ph, PCIC_IF_STATUS); 2271 if (stat & PCIC_IF_STATUS_READY) 2272 return (0); 2273 pccbb_pcmcia_delay(ph, 10, "pccwr0"); 2274 for (i = 0; i < 50; i++) { 2275 stat = Pcic_read(ph, PCIC_IF_STATUS); 2276 if (stat & PCIC_IF_STATUS_READY) 2277 return (0); 2278 if ((stat & PCIC_IF_STATUS_CARDDETECT_MASK) != 2279 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2280 return (ENXIO); 2281 /* wait .1s (100ms) each iteration now */ 2282 pccbb_pcmcia_delay(ph, 100, "pccwr1"); 2283 } 2284 2285 printf("pccbb_pcmcia_wait_ready: ready never happened, status=%02x\n", stat); 2286 return (EWOULDBLOCK); 2287 } 2288 2289 /* 2290 * Perform long (msec order) delay. timo is in milliseconds. 2291 */ 2292 static void 2293 pccbb_pcmcia_delay(struct pcic_handle *ph, int timo, const char *wmesg) 2294 { 2295 #ifdef DIAGNOSTIC 2296 if (timo <= 0) 2297 panic("pccbb_pcmcia_delay: called with timeout %d", timo); 2298 if (!curlwp) 2299 panic("pccbb_pcmcia_delay: called in interrupt context"); 2300 #if 0 2301 if (!ph->event_thread) 2302 panic("pccbb_pcmcia_delay: no event thread"); 2303 #endif 2304 #endif 2305 DPRINTF(("pccbb_pcmcia_delay: \"%s\" %p, sleep %d ms\n", 2306 wmesg, ph->event_thread, timo)); 2307 tsleep(pccbb_pcmcia_delay, PWAIT, wmesg, roundup(timo * hz, 1000) / 1000); 2308 } 2309 2310 /* 2311 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2312 * 2313 * This function enables the card. All information is stored in 2314 * the first argument, pcmcia_chipset_handle_t. 2315 */ 2316 STATIC void 2317 pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2318 { 2319 struct pcic_handle *ph = (struct pcic_handle *)pch; 2320 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2321 pcireg_t spsr; 2322 int voltage; 2323 int win; 2324 u_int8_t power, intr; 2325 #ifdef DIAGNOSTIC 2326 int reg; 2327 #endif 2328 2329 /* this bit is mostly stolen from pcic_attach_card */ 2330 2331 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2332 2333 /* get card Vcc info */ 2334 spsr = 2335 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2336 CB_SOCKET_STAT); 2337 if (spsr & CB_SOCKET_STAT_5VCARD) { 2338 DPRINTF(("5V card\n")); 2339 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2340 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2341 DPRINTF(("3V card\n")); 2342 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2343 } else { 2344 DPRINTF(("?V card, 0x%x\n", spsr)); /* XXX */ 2345 return; 2346 } 2347 2348 /* disable interrupts; assert RESET */ 2349 intr = Pcic_read(ph, PCIC_INTR); 2350 intr &= PCIC_INTR_ENABLE; 2351 Pcic_write(ph, PCIC_INTR, intr); 2352 2353 /* zero out the address windows */ 2354 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2355 2356 /* power down the socket to reset it, clear the card reset pin */ 2357 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2358 2359 /* power off; assert output enable bit */ 2360 power = PCIC_PWRCTL_OE; 2361 Pcic_write(ph, PCIC_PWRCTL, power); 2362 2363 /* power up the socket */ 2364 if (pccbb_power(sc, voltage) == 0) 2365 return; 2366 2367 /* 2368 * Table 4-18 and figure 4-6 of the PC Card specifiction say: 2369 * Vcc Rising Time (Tpr) = 100ms (handled in pccbb_power() above) 2370 * RESET Width (Th (Hi-z RESET)) = 1ms 2371 * RESET Width (Tw (RESET)) = 10us 2372 * 2373 * some machines require some more time to be settled 2374 * for example old toshiba topic bridges! 2375 * (100ms is added here). 2376 */ 2377 pccbb_pcmcia_delay(ph, 200 + 1, "pccen1"); 2378 2379 /* negate RESET */ 2380 intr |= PCIC_INTR_RESET; 2381 Pcic_write(ph, PCIC_INTR, intr); 2382 2383 /* 2384 * RESET Setup Time (Tsu (RESET)) = 20ms 2385 */ 2386 pccbb_pcmcia_delay(ph, 20, "pccen2"); 2387 2388 #ifdef DIAGNOSTIC 2389 reg = Pcic_read(ph, PCIC_IF_STATUS); 2390 if ((reg & PCIC_IF_STATUS_POWERACTIVE) == 0) 2391 printf("pccbb_pcmcia_socket_enable: no power, status=%x\n", reg); 2392 #endif 2393 2394 /* wait for the chip to finish initializing */ 2395 if (pccbb_pcmcia_wait_ready(ph)) { 2396 #ifdef DIAGNOSTIC 2397 printf("pccbb_pcmcia_socket_enable: never became ready\n"); 2398 #endif 2399 /* XXX return a failure status?? */ 2400 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2401 Pcic_write(ph, PCIC_PWRCTL, 0); 2402 return; 2403 } 2404 2405 /* reinstall all the memory and io mappings */ 2406 for (win = 0; win < PCIC_MEM_WINS; ++win) 2407 if (ph->memalloc & (1 << win)) 2408 pccbb_pcmcia_do_mem_map(ph, win); 2409 for (win = 0; win < PCIC_IO_WINS; ++win) 2410 if (ph->ioalloc & (1 << win)) 2411 pccbb_pcmcia_do_io_map(ph, win); 2412 } 2413 2414 /* 2415 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2416 * 2417 * This function disables the card. All information is stored in 2418 * the first argument, pcmcia_chipset_handle_t. 2419 */ 2420 STATIC void 2421 pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t pch) 2422 { 2423 struct pcic_handle *ph = (struct pcic_handle *)pch; 2424 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2425 u_int8_t intr; 2426 2427 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2428 2429 /* disable interrupts; assert RESET */ 2430 intr = Pcic_read(ph, PCIC_INTR); 2431 intr &= PCIC_INTR_ENABLE; 2432 Pcic_write(ph, PCIC_INTR, intr); 2433 2434 /* zero out the address windows */ 2435 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2436 2437 /* power down the socket to reset it, clear the card reset pin */ 2438 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2439 2440 /* disable socket: negate output enable bit and power off */ 2441 Pcic_write(ph, PCIC_PWRCTL, 0); 2442 2443 /* 2444 * Vcc Falling Time (Tpf) = 300ms 2445 */ 2446 pccbb_pcmcia_delay(ph, 300, "pccwr1"); 2447 } 2448 2449 STATIC void 2450 pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t pch, int type) 2451 { 2452 struct pcic_handle *ph = (struct pcic_handle *)pch; 2453 u_int8_t intr; 2454 2455 /* set the card type */ 2456 2457 intr = Pcic_read(ph, PCIC_INTR); 2458 intr &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_CARDTYPE_MASK); 2459 if (type == PCMCIA_IFTYPE_IO) 2460 intr |= PCIC_INTR_CARDTYPE_IO; 2461 else 2462 intr |= PCIC_INTR_CARDTYPE_MEM; 2463 Pcic_write(ph, PCIC_INTR, intr); 2464 2465 DPRINTF(("%s: pccbb_pcmcia_socket_settype %02x type %s %02x\n", 2466 ph->ph_parent->dv_xname, ph->sock, 2467 ((type == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2468 } 2469 2470 /* 2471 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2472 * 2473 * This function detects whether a card is in the slot or not. 2474 * If a card is inserted, return 1. Otherwise, return 0. 2475 */ 2476 STATIC int 2477 pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch) 2478 { 2479 struct pcic_handle *ph = (struct pcic_handle *)pch; 2480 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2481 2482 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2483 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2484 } 2485 2486 #if 0 2487 STATIC int 2488 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2489 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2490 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2491 #endif 2492 /* 2493 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2494 * bus_size_t size, 2495 * struct pcmcia_mem_handle *pcmhp) 2496 * 2497 * This function only allocates memory region for pccard. This 2498 * function never maps the allocated region to pccard memory area. 2499 * 2500 * XXX: Why the argument of start address is not in? 2501 */ 2502 STATIC int 2503 pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 2504 struct pcmcia_mem_handle *pcmhp) 2505 { 2506 struct pcic_handle *ph = (struct pcic_handle *)pch; 2507 bus_space_handle_t memh; 2508 bus_addr_t addr; 2509 bus_size_t sizepg; 2510 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2511 #if rbus 2512 rbus_tag_t rb; 2513 #endif 2514 2515 /* Check that the card is still there. */ 2516 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2517 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2518 return 1; 2519 2520 /* out of sc->memh, allocate as many pages as necessary */ 2521 2522 /* convert size to PCIC pages */ 2523 /* 2524 * This is not enough; when the requested region is on the page 2525 * boundaries, this may calculate wrong result. 2526 */ 2527 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2528 #if 0 2529 if (sizepg > PCIC_MAX_MEM_PAGES) { 2530 return 1; 2531 } 2532 #endif 2533 2534 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2535 return 1; 2536 } 2537 2538 addr = 0; /* XXX gcc -Wuninitialized */ 2539 2540 #if rbus 2541 rb = sc->sc_rbus_memt; 2542 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2543 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2544 &addr, &memh)) { 2545 return 1; 2546 } 2547 #else 2548 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2549 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2550 0, /* boundary */ 2551 0, /* flags */ 2552 &addr, &memh)) { 2553 return 1; 2554 } 2555 #endif 2556 2557 DPRINTF(("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, " 2558 "realsize 0x%lx\n", (unsigned long)addr, (unsigned long)size, 2559 (unsigned long)sizepg * PCIC_MEM_PAGESIZE)); 2560 2561 pcmhp->memt = sc->sc_memt; 2562 pcmhp->memh = memh; 2563 pcmhp->addr = addr; 2564 pcmhp->size = size; 2565 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2566 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2567 pcmhp->mhandle = 0; 2568 /* No offset??? Funny. */ 2569 2570 return 0; 2571 } 2572 2573 /* 2574 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2575 * struct pcmcia_mem_handle *pcmhp) 2576 * 2577 * This function release the memory space allocated by the function 2578 * pccbb_pcmcia_mem_alloc(). 2579 */ 2580 STATIC void 2581 pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2582 struct pcmcia_mem_handle *pcmhp) 2583 { 2584 #if rbus 2585 struct pcic_handle *ph = (struct pcic_handle *)pch; 2586 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2587 2588 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2589 #else 2590 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2591 #endif 2592 } 2593 2594 /* 2595 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2596 * 2597 * This function release the memory space allocated by the function 2598 * pccbb_pcmcia_mem_alloc(). 2599 */ 2600 STATIC void 2601 pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2602 { 2603 int regbase_win; 2604 bus_addr_t phys_addr; 2605 bus_addr_t phys_end; 2606 2607 #define PCIC_SMM_START_LOW 0 2608 #define PCIC_SMM_START_HIGH 1 2609 #define PCIC_SMM_STOP_LOW 2 2610 #define PCIC_SMM_STOP_HIGH 3 2611 #define PCIC_CMA_LOW 4 2612 #define PCIC_CMA_HIGH 5 2613 2614 u_int8_t start_low, start_high = 0; 2615 u_int8_t stop_low, stop_high; 2616 u_int8_t off_low, off_high; 2617 u_int8_t mem_window; 2618 int reg; 2619 2620 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2621 int mem8 = 2622 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2623 || (kind == PCMCIA_MEM_ATTR); 2624 2625 regbase_win = 0x10 + win * 0x08; 2626 2627 phys_addr = ph->mem[win].addr; 2628 phys_end = phys_addr + ph->mem[win].size; 2629 2630 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2631 (unsigned long)phys_addr, (unsigned long)phys_end, 2632 (unsigned long)ph->mem[win].offset)); 2633 2634 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2635 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2636 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2637 2638 /* bit 19:12 */ 2639 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2640 /* bit 23:20 and bit 7 on */ 2641 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2642 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2643 /* bit 31:24, for 32-bit address */ 2644 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2645 2646 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2647 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2648 2649 if (((struct pccbb_softc *)ph-> 2650 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2651 Pcic_write(ph, 0x40 + win, mem_window); 2652 } 2653 2654 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2655 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2656 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2657 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2658 2659 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2660 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2661 2662 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2663 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2664 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2665 | ((kind == PCMCIA_MEM_ATTR) ? 2666 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2667 2668 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2669 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2670 2671 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2672 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2673 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2674 2675 #if defined(CBB_DEBUG) 2676 { 2677 int r1, r2, r3, r4, r5, r6, r7 = 0; 2678 2679 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2680 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2681 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2682 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2683 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2684 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2685 if (((struct pccbb_softc *)(ph-> 2686 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2687 r7 = Pcic_read(ph, 0x40 + win); 2688 } 2689 2690 printf("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2691 "%02x%02x", win, r1, r2, r3, r4, r5, r6); 2692 if (((struct pccbb_softc *)(ph-> 2693 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2694 printf(" %02x", r7); 2695 } 2696 printf("\n"); 2697 } 2698 #endif 2699 } 2700 2701 /* 2702 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2703 * bus_addr_t card_addr, bus_size_t size, 2704 * struct pcmcia_mem_handle *pcmhp, 2705 * bus_addr_t *offsetp, int *windowp) 2706 * 2707 * This function maps memory space allocated by the function 2708 * pccbb_pcmcia_mem_alloc(). 2709 */ 2710 STATIC int 2711 pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2712 bus_addr_t card_addr, bus_size_t size, struct pcmcia_mem_handle *pcmhp, 2713 bus_addr_t *offsetp, int *windowp) 2714 { 2715 struct pcic_handle *ph = (struct pcic_handle *)pch; 2716 bus_addr_t busaddr; 2717 long card_offset; 2718 int win; 2719 2720 /* Check that the card is still there. */ 2721 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2722 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2723 return 1; 2724 2725 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2726 if ((ph->memalloc & (1 << win)) == 0) { 2727 ph->memalloc |= (1 << win); 2728 break; 2729 } 2730 } 2731 2732 if (win == PCIC_MEM_WINS) { 2733 return 1; 2734 } 2735 2736 *windowp = win; 2737 2738 /* XXX this is pretty gross */ 2739 2740 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2741 panic("pccbb_pcmcia_mem_map memt is bogus"); 2742 } 2743 2744 busaddr = pcmhp->addr; 2745 2746 /* 2747 * compute the address offset to the pcmcia address space for the 2748 * pcic. this is intentionally signed. The masks and shifts below 2749 * will cause TRT to happen in the pcic registers. Deal with making 2750 * sure the address is aligned, and return the alignment offset. 2751 */ 2752 2753 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2754 card_addr -= *offsetp; 2755 2756 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2757 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2758 (u_long) card_addr)); 2759 2760 /* 2761 * include the offset in the size, and decrement size by one, since 2762 * the hw wants start/stop 2763 */ 2764 size += *offsetp - 1; 2765 2766 card_offset = (((long)card_addr) - ((long)busaddr)); 2767 2768 ph->mem[win].addr = busaddr; 2769 ph->mem[win].size = size; 2770 ph->mem[win].offset = card_offset; 2771 ph->mem[win].kind = kind; 2772 2773 pccbb_pcmcia_do_mem_map(ph, win); 2774 2775 return 0; 2776 } 2777 2778 /* 2779 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2780 * int window) 2781 * 2782 * This function unmaps memory space which mapped by the function 2783 * pccbb_pcmcia_mem_map(). 2784 */ 2785 STATIC void 2786 pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, int window) 2787 { 2788 struct pcic_handle *ph = (struct pcic_handle *)pch; 2789 int reg; 2790 2791 if (window >= PCIC_MEM_WINS) { 2792 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2793 } 2794 2795 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2796 reg &= ~(1 << window); 2797 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2798 2799 ph->memalloc &= ~(1 << window); 2800 } 2801 2802 #if defined PCCBB_PCMCIA_POLL 2803 struct pccbb_poll_str { 2804 void *arg; 2805 int (*func)(void *); 2806 int level; 2807 struct pcic_handle *ph; 2808 int count; 2809 int num; 2810 struct callout poll_ch; 2811 }; 2812 2813 static struct pccbb_poll_str pccbb_poll[10]; 2814 static int pccbb_poll_n = 0; 2815 2816 static void pccbb_pcmcia_poll(void *arg); 2817 2818 static void 2819 pccbb_pcmcia_poll(void *arg) 2820 { 2821 struct pccbb_poll_str *poll = arg; 2822 struct pcic_handle *ph = poll->ph; 2823 struct pccbb_softc *sc = ph->sc; 2824 int s; 2825 u_int32_t spsr; /* socket present-state reg */ 2826 2827 callout_reset(&poll->poll_ch, hz * 2, pccbb_pcmcia_poll, arg); 2828 switch (poll->level) { 2829 case IPL_NET: 2830 s = splnet(); 2831 break; 2832 case IPL_BIO: 2833 s = splbio(); 2834 break; 2835 case IPL_TTY: /* fallthrough */ 2836 default: 2837 s = spltty(); 2838 break; 2839 } 2840 2841 spsr = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2842 CB_SOCKET_STAT); 2843 2844 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2845 if (!(spsr & 0x40)) /* CINT low */ 2846 #else 2847 if (1) 2848 #endif 2849 { 2850 if ((*poll->func) (poll->arg) > 0) { 2851 ++poll->count; 2852 /* printf("intr: reported from poller, 0x%x\n", spsr); */ 2853 #if defined LEVEL2 2854 } else { 2855 printf("intr: miss! 0x%x\n", spsr); 2856 #endif 2857 } 2858 } 2859 splx(s); 2860 } 2861 #endif /* defined CB_PCMCIA_POLL */ 2862 2863 /* 2864 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2865 * struct pcmcia_function *pf, 2866 * int ipl, 2867 * int (*func)(void *), 2868 * void *arg); 2869 * 2870 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2871 */ 2872 STATIC void * 2873 pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2874 struct pcmcia_function *pf, int ipl, int (*func)(void *), void *arg) 2875 { 2876 struct pcic_handle *ph = (struct pcic_handle *)pch; 2877 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2878 2879 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2880 /* what should I do? */ 2881 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2882 DPRINTF(("%s does not provide edge nor pulse " 2883 "interrupt\n", sc->sc_dev.dv_xname)); 2884 return NULL; 2885 } 2886 /* 2887 * XXX Noooooo! The interrupt flag must set properly!! 2888 * dumb pcmcia driver!! 2889 */ 2890 } 2891 2892 return pccbb_intr_establish(sc, 0, ipl, func, arg); 2893 } 2894 2895 /* 2896 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2897 * void *ih) 2898 * 2899 * This function disables PC-Card interrupt. 2900 */ 2901 STATIC void 2902 pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 2903 { 2904 struct pcic_handle *ph = (struct pcic_handle *)pch; 2905 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2906 2907 pccbb_intr_disestablish(sc, ih); 2908 } 2909 2910 #if rbus 2911 /* 2912 * static int 2913 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2914 * bus_addr_t addr, bus_size_t size, 2915 * bus_addr_t mask, bus_size_t align, 2916 * int flags, bus_addr_t *addrp; 2917 * bus_space_handle_t *bshp) 2918 * 2919 * This function allocates a portion of memory or io space for 2920 * clients. This function is called from CardBus card drivers. 2921 */ 2922 static int 2923 pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2924 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 2925 int flags, bus_addr_t *addrp, bus_space_handle_t *bshp) 2926 { 2927 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2928 2929 DPRINTF(("pccbb_rbus_cb_space_alloc: addr 0x%lx, size 0x%lx, " 2930 "mask 0x%lx, align 0x%lx\n", (unsigned long)addr, 2931 (unsigned long)size, (unsigned long)mask, (unsigned long)align)); 2932 2933 if (align == 0) { 2934 align = size; 2935 } 2936 2937 if (rb->rb_bt == sc->sc_memt) { 2938 if (align < 16) { 2939 return 1; 2940 } 2941 /* 2942 * XXX: align more than 0x1000 to avoid overwrapping 2943 * memory windows for two or more devices. 0x1000 2944 * means memory window's granularity. 2945 * 2946 * Two or more devices should be able to share same 2947 * memory window region. However, overrapping memory 2948 * window is not good because some devices, such as 2949 * 3Com 3C575[BC], have a broken address decoder and 2950 * intrude other's memory region. 2951 */ 2952 if (align < 0x1000) { 2953 align = 0x1000; 2954 } 2955 } else if (rb->rb_bt == sc->sc_iot) { 2956 if (align < 4) { 2957 return 1; 2958 } 2959 /* XXX: hack for avoiding ISA image */ 2960 if (mask < 0x0100) { 2961 mask = 0x3ff; 2962 addr = 0x300; 2963 } 2964 2965 } else { 2966 DPRINTF(("pccbb_rbus_cb_space_alloc: Bus space tag 0x%lx is " 2967 "NOT used. io: 0x%lx, mem: 0x%lx\n", 2968 (unsigned long)rb->rb_bt, (unsigned long)sc->sc_iot, 2969 (unsigned long)sc->sc_memt)); 2970 return 1; 2971 /* XXX: panic here? */ 2972 } 2973 2974 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 2975 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 2976 return 1; 2977 } 2978 2979 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 2980 2981 return 0; 2982 } 2983 2984 /* 2985 * static int 2986 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 2987 * bus_space_handle_t *bshp, bus_size_t size); 2988 * 2989 * This function is called from CardBus card drivers. 2990 */ 2991 static int 2992 pccbb_rbus_cb_space_free(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2993 bus_space_handle_t bsh, bus_size_t size) 2994 { 2995 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2996 bus_space_tag_t bt = rb->rb_bt; 2997 2998 pccbb_close_win(sc, bt, bsh, size); 2999 3000 if (bt == sc->sc_memt) { 3001 } else if (bt == sc->sc_iot) { 3002 } else { 3003 return 1; 3004 /* XXX: panic here? */ 3005 } 3006 3007 return rbus_space_free(rb, bsh, size, NULL); 3008 } 3009 #endif /* rbus */ 3010 3011 #if rbus 3012 3013 static int 3014 pccbb_open_win(struct pccbb_softc *sc, bus_space_tag_t bst, bus_addr_t addr, 3015 bus_size_t size, bus_space_handle_t bsh, int flags) 3016 { 3017 struct pccbb_win_chain_head *head; 3018 bus_addr_t align; 3019 3020 head = &sc->sc_iowindow; 3021 align = 0x04; 3022 if (sc->sc_memt == bst) { 3023 head = &sc->sc_memwindow; 3024 align = 0x1000; 3025 DPRINTF(("using memory window, 0x%lx 0x%lx 0x%lx\n\n", 3026 (unsigned long)sc->sc_iot, (unsigned long)sc->sc_memt, 3027 (unsigned long)bst)); 3028 } 3029 3030 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 3031 printf("%s: pccbb_open_win: %s winlist insert failed\n", 3032 sc->sc_dev.dv_xname, 3033 (head == &sc->sc_memwindow) ? "mem" : "io"); 3034 } 3035 pccbb_winset(align, sc, bst); 3036 3037 return 0; 3038 } 3039 3040 static int 3041 pccbb_close_win(struct pccbb_softc *sc, bus_space_tag_t bst, 3042 bus_space_handle_t bsh, bus_size_t size) 3043 { 3044 struct pccbb_win_chain_head *head; 3045 bus_addr_t align; 3046 3047 head = &sc->sc_iowindow; 3048 align = 0x04; 3049 if (sc->sc_memt == bst) { 3050 head = &sc->sc_memwindow; 3051 align = 0x1000; 3052 } 3053 3054 if (pccbb_winlist_delete(head, bsh, size)) { 3055 printf("%s: pccbb_close_win: %s winlist delete failed\n", 3056 sc->sc_dev.dv_xname, 3057 (head == &sc->sc_memwindow) ? "mem" : "io"); 3058 } 3059 pccbb_winset(align, sc, bst); 3060 3061 return 0; 3062 } 3063 3064 static int 3065 pccbb_winlist_insert(struct pccbb_win_chain_head *head, bus_addr_t start, 3066 bus_size_t size, bus_space_handle_t bsh, int flags) 3067 { 3068 struct pccbb_win_chain *chainp, *elem; 3069 3070 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 3071 M_NOWAIT)) == NULL) 3072 return (1); /* fail */ 3073 3074 elem->wc_start = start; 3075 elem->wc_end = start + (size - 1); 3076 elem->wc_handle = bsh; 3077 elem->wc_flags = flags; 3078 3079 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3080 chainp = TAILQ_NEXT(chainp, wc_list)) { 3081 if (chainp->wc_end < start) 3082 continue; 3083 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 3084 return (0); 3085 } 3086 3087 TAILQ_INSERT_TAIL(head, elem, wc_list); 3088 return (0); 3089 } 3090 3091 static int 3092 pccbb_winlist_delete(struct pccbb_win_chain_head *head, bus_space_handle_t bsh, 3093 bus_size_t size) 3094 { 3095 struct pccbb_win_chain *chainp; 3096 3097 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3098 chainp = TAILQ_NEXT(chainp, wc_list)) { 3099 if (memcmp(&chainp->wc_handle, &bsh, sizeof(bsh))) 3100 continue; 3101 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 3102 printf("pccbb_winlist_delete: window 0x%lx size " 3103 "inconsistent: 0x%lx, 0x%lx\n", 3104 (unsigned long)chainp->wc_start, 3105 (unsigned long)(chainp->wc_end - chainp->wc_start), 3106 (unsigned long)(size - 1)); 3107 return 1; 3108 } 3109 3110 TAILQ_REMOVE(head, chainp, wc_list); 3111 free(chainp, M_DEVBUF); 3112 3113 return 0; 3114 } 3115 3116 return 1; /* fail: no candidate to remove */ 3117 } 3118 3119 static void 3120 pccbb_winset(bus_addr_t align, struct pccbb_softc *sc, bus_space_tag_t bst) 3121 { 3122 pci_chipset_tag_t pc; 3123 pcitag_t tag; 3124 bus_addr_t mask = ~(align - 1); 3125 struct { 3126 cardbusreg_t win_start; 3127 cardbusreg_t win_limit; 3128 int win_flags; 3129 } win[2]; 3130 struct pccbb_win_chain *chainp; 3131 int offs; 3132 3133 win[0].win_start = win[1].win_start = 0xffffffff; 3134 win[0].win_limit = win[1].win_limit = 0; 3135 win[0].win_flags = win[1].win_flags = 0; 3136 3137 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3138 offs = 0x2c; 3139 if (sc->sc_memt == bst) { 3140 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3141 offs = 0x1c; 3142 } 3143 3144 if (chainp != NULL) { 3145 win[0].win_start = chainp->wc_start & mask; 3146 win[0].win_limit = chainp->wc_end & mask; 3147 win[0].win_flags = chainp->wc_flags; 3148 chainp = TAILQ_NEXT(chainp, wc_list); 3149 } 3150 3151 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3152 if (win[1].win_start == 0xffffffff) { 3153 /* window 1 is not used */ 3154 if ((win[0].win_flags == chainp->wc_flags) && 3155 (win[0].win_limit + align >= 3156 (chainp->wc_start & mask))) { 3157 /* concatenate */ 3158 win[0].win_limit = chainp->wc_end & mask; 3159 } else { 3160 /* make new window */ 3161 win[1].win_start = chainp->wc_start & mask; 3162 win[1].win_limit = chainp->wc_end & mask; 3163 win[1].win_flags = chainp->wc_flags; 3164 } 3165 continue; 3166 } 3167 3168 /* Both windows are engaged. */ 3169 if (win[0].win_flags == win[1].win_flags) { 3170 /* same flags */ 3171 if (win[0].win_flags == chainp->wc_flags) { 3172 if (win[1].win_start - (win[0].win_limit + 3173 align) < 3174 (chainp->wc_start & mask) - 3175 ((chainp->wc_end & mask) + align)) { 3176 /* 3177 * merge window 0 and 1, and set win1 3178 * to chainp 3179 */ 3180 win[0].win_limit = win[1].win_limit; 3181 win[1].win_start = 3182 chainp->wc_start & mask; 3183 win[1].win_limit = 3184 chainp->wc_end & mask; 3185 } else { 3186 win[1].win_limit = 3187 chainp->wc_end & mask; 3188 } 3189 } else { 3190 /* different flags */ 3191 3192 /* concatenate win0 and win1 */ 3193 win[0].win_limit = win[1].win_limit; 3194 /* allocate win[1] to new space */ 3195 win[1].win_start = chainp->wc_start & mask; 3196 win[1].win_limit = chainp->wc_end & mask; 3197 win[1].win_flags = chainp->wc_flags; 3198 } 3199 } else { 3200 /* the flags of win[0] and win[1] is different */ 3201 if (win[0].win_flags == chainp->wc_flags) { 3202 win[0].win_limit = chainp->wc_end & mask; 3203 /* 3204 * XXX this creates overlapping windows, so 3205 * what should the poor bridge do if one is 3206 * cachable, and the other is not? 3207 */ 3208 printf("%s: overlapping windows\n", 3209 sc->sc_dev.dv_xname); 3210 } else { 3211 win[1].win_limit = chainp->wc_end & mask; 3212 } 3213 } 3214 } 3215 3216 pc = sc->sc_pc; 3217 tag = sc->sc_tag; 3218 pci_conf_write(pc, tag, offs, win[0].win_start); 3219 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3220 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3221 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3222 DPRINTF(("--pccbb_winset: win0 [0x%lx, 0x%lx), win1 [0x%lx, 0x%lx)\n", 3223 (unsigned long)pci_conf_read(pc, tag, offs), 3224 (unsigned long)pci_conf_read(pc, tag, offs + 4) + align, 3225 (unsigned long)pci_conf_read(pc, tag, offs + 8), 3226 (unsigned long)pci_conf_read(pc, tag, offs + 12) + align)); 3227 3228 if (bst == sc->sc_memt) { 3229 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BRIDGE_CONTROL_REG); 3230 3231 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 3232 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 3233 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3234 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 3235 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3236 pci_conf_write(pc, tag, PCI_BRIDGE_CONTROL_REG, bcr); 3237 } 3238 } 3239 3240 #endif /* rbus */ 3241 3242 static void 3243 pccbb_powerhook(int why, void *arg) 3244 { 3245 struct pccbb_softc *sc = arg; 3246 pcireg_t reg; 3247 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3248 bus_space_handle_t base_memh = sc->sc_base_memh; 3249 3250 DPRINTF(("%s: power: why %d\n", sc->sc_dev.dv_xname, why)); 3251 3252 if (why == PWR_SUSPEND || why == PWR_STANDBY) { 3253 DPRINTF(("%s: power: why %d stopping intr\n", 3254 sc->sc_dev.dv_xname, why)); 3255 if (sc->sc_pil_intr_enable) { 3256 (void)pccbbintr_function(sc); 3257 } 3258 sc->sc_pil_intr_enable = 0; 3259 3260 pci_conf_capture(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf); 3261 3262 if (sc->sc_chipset == CB_RX5C47X) 3263 sc->sc_ricoh_misc_ctrl = pci_conf_read(sc->sc_pc, 3264 sc->sc_tag, 3265 RICOH_PCI_MISC_CTRL); 3266 3267 /* ToDo: deactivate or suspend child devices */ 3268 } 3269 3270 if (why == PWR_RESUME) { 3271 if (sc->sc_pwrmgt_offs != 0) { 3272 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, 3273 sc->sc_pwrmgt_offs + PCI_PMCSR); 3274 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 3275 reg & PCI_PMCSR_PME_EN) { 3276 /* powrstate != D0 */ 3277 3278 printf("%s going back to D0 mode\n", 3279 sc->sc_dev.dv_xname); 3280 reg &= ~PCI_PMCSR_STATE_MASK; 3281 reg |= PCI_PMCSR_STATE_D0; 3282 reg &= ~PCI_PMCSR_PME_EN; 3283 pci_conf_write(sc->sc_pc, sc->sc_tag, 3284 sc->sc_pwrmgt_offs + PCI_PMCSR, reg); 3285 3286 pci_conf_write(sc->sc_pc, sc->sc_tag, 3287 PCI_SOCKBASE, sc->sc_sockbase); 3288 pci_conf_write(sc->sc_pc, sc->sc_tag, 3289 PCI_BUSNUM, sc->sc_busnum); 3290 pccbb_chipinit(sc); 3291 /* setup memory and io space window for CB */ 3292 pccbb_winset(0x1000, sc, sc->sc_memt); 3293 pccbb_winset(0x04, sc, sc->sc_iot); 3294 goto norestore; 3295 } 3296 } 3297 3298 norestore: 3299 pci_conf_restore(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf); 3300 if (sc->sc_chipset == CB_RX5C47X) { 3301 pci_conf_write(sc->sc_pc, sc->sc_tag, 3302 RICOH_PCI_MISC_CTRL, sc->sc_ricoh_misc_ctrl); 3303 } 3304 3305 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_SOCKBASE) == 0) 3306 /* BIOS did not recover this register */ 3307 pci_conf_write (sc->sc_pc, sc->sc_tag, 3308 PCI_SOCKBASE, sc->sc_sockbase); 3309 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_BUSNUM) == 0) 3310 /* BIOS did not recover this register */ 3311 pci_conf_write (sc->sc_pc, sc->sc_tag, 3312 PCI_BUSNUM, sc->sc_busnum); 3313 /* CSC Interrupt: Card detect interrupt on */ 3314 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3315 /* Card detect intr is turned on. */ 3316 reg |= CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; 3317 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3318 /* reset interrupt */ 3319 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3320 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3321 3322 /* 3323 * check for card insertion or removal during suspend period. 3324 * XXX: the code can't cope with card swap (remove then 3325 * insert). how can we detect such situation? 3326 */ 3327 (void)pccbbintr(sc); 3328 3329 sc->sc_pil_intr_enable = 1; 3330 DPRINTF(("%s: power: RESUME enabling intr\n", 3331 sc->sc_dev.dv_xname)); 3332 3333 /* ToDo: activate or wakeup child devices */ 3334 } 3335 } 3336
Indexes created Sun Sep 28 07:09:56 GMT 2025