pccbb.c revision 1.151
1 /* $NetBSD: pccbb.c,v 1.151 2007/11/16 18:36:51 dyoung Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: pccbb.c,v 1.151 2007/11/16 18:36:51 dyoung Exp $"); 35 36 /* 37 #define CBB_DEBUG 38 #define SHOW_REGS 39 */ 40 41 /* 42 * BROKEN! 43 #define PCCBB_PCMCIA_POLL 44 #define CB_PCMCIA_POLL 45 #define CB_PCMCIA_POLL_ONLY 46 #define LEVEL2 47 */ 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/kernel.h> 52 #include <sys/errno.h> 53 #include <sys/ioctl.h> 54 #include <sys/reboot.h> /* for bootverbose */ 55 #include <sys/syslog.h> 56 #include <sys/device.h> 57 #include <sys/malloc.h> 58 #include <sys/proc.h> 59 60 #include <sys/intr.h> 61 #include <sys/bus.h> 62 63 #include <dev/pci/pcivar.h> 64 #include <dev/pci/pcireg.h> 65 #include <dev/pci/pcidevs.h> 66 67 #include <dev/pci/pccbbreg.h> 68 69 #include <dev/cardbus/cardslotvar.h> 70 71 #include <dev/cardbus/cardbusvar.h> 72 73 #include <dev/pcmcia/pcmciareg.h> 74 #include <dev/pcmcia/pcmciavar.h> 75 76 #include <dev/ic/i82365reg.h> 77 #include <dev/ic/i82365var.h> 78 #include <dev/pci/pccbbvar.h> 79 80 #include "locators.h" 81 82 #ifndef __NetBSD_Version__ 83 struct cfdriver cbb_cd = { 84 NULL, "cbb", DV_DULL 85 }; 86 #endif 87 88 #ifdef CBB_DEBUG 89 #define DPRINTF(x) printf x 90 #define STATIC 91 #else 92 #define DPRINTF(x) 93 #define STATIC static 94 #endif 95 96 int pccbb_burstup = 1; 97 98 /* 99 * delay_ms() is wait in milliseconds. It should be used instead 100 * of delay() if you want to wait more than 1 ms. 101 */ 102 static inline void 103 delay_ms(int millis, void *param) 104 { 105 if (cold) 106 delay(millis * 1000); 107 else 108 tsleep(param, PWAIT, "pccbb", MAX(2, hz * millis / 1000)); 109 } 110 111 int pcicbbmatch(struct device *, struct cfdata *, void *); 112 void pccbbattach(struct device *, struct device *, void *); 113 int pccbbintr(void *); 114 static void pci113x_insert(void *); 115 static int pccbbintr_function(struct pccbb_softc *); 116 117 static int pccbb_detect_card(struct pccbb_softc *); 118 119 static void pccbb_pcmcia_write(struct pcic_handle *, int, u_int8_t); 120 static u_int8_t pccbb_pcmcia_read(struct pcic_handle *, int); 121 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 122 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 123 124 STATIC int cb_reset(struct pccbb_softc *); 125 STATIC int cb_detect_voltage(struct pccbb_softc *); 126 STATIC int cbbprint(void *, const char *); 127 128 static int cb_chipset(u_int32_t, int *); 129 STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *, 130 struct pcmciabus_attach_args *); 131 #if 0 132 STATIC void pccbb_pcmcia_attach_card(struct pcic_handle *); 133 STATIC void pccbb_pcmcia_detach_card(struct pcic_handle *, int); 134 STATIC void pccbb_pcmcia_deactivate_card(struct pcic_handle *); 135 #endif 136 137 STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int); 138 STATIC int pccbb_power(cardbus_chipset_tag_t, int); 139 STATIC int pccbb_cardenable(struct pccbb_softc * sc, int function); 140 #if !rbus 141 static int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 142 static int pccbb_io_close(cardbus_chipset_tag_t, int); 143 static int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 144 static int pccbb_mem_close(cardbus_chipset_tag_t, int); 145 #endif /* !rbus */ 146 static void *pccbb_intr_establish(struct pccbb_softc *, int irq, 147 int level, int (*ih) (void *), void *sc); 148 static void pccbb_intr_disestablish(struct pccbb_softc *, void *ih); 149 150 static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t, int irq, 151 int level, int (*ih) (void *), void *sc); 152 static void pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih); 153 154 static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t, int, int); 155 static void pccbb_free_tag(cardbus_chipset_tag_t, cardbustag_t); 156 static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t, cardbustag_t, int); 157 static void pccbb_conf_write(cardbus_chipset_tag_t, cardbustag_t, int, 158 cardbusreg_t); 159 static void pccbb_chipinit(struct pccbb_softc *); 160 161 STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 162 struct pcmcia_mem_handle *); 163 STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t, 164 struct pcmcia_mem_handle *); 165 STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 166 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *); 167 STATIC void pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t, int); 168 STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 169 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 170 STATIC void pccbb_pcmcia_io_free(pcmcia_chipset_handle_t, 171 struct pcmcia_io_handle *); 172 STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 173 bus_size_t, struct pcmcia_io_handle *, int *); 174 STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t, int); 175 STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t, 176 struct pcmcia_function *, int, int (*)(void *), void *); 177 STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t, void *); 178 STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t); 179 STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t); 180 STATIC void pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t, int); 181 STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch); 182 183 static int pccbb_pcmcia_wait_ready(struct pcic_handle *); 184 static void pccbb_pcmcia_delay(struct pcic_handle *, int, const char *); 185 186 static void pccbb_pcmcia_do_io_map(struct pcic_handle *, int); 187 static void pccbb_pcmcia_do_mem_map(struct pcic_handle *, int); 188 static void pccbb_powerhook(int, void *); 189 190 /* bus-space allocation and deallocation functions */ 191 #if rbus 192 193 static int pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t, rbus_tag_t, 194 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 195 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp); 196 static int pccbb_rbus_cb_space_free(cardbus_chipset_tag_t, rbus_tag_t, 197 bus_space_handle_t, bus_size_t); 198 199 #endif /* rbus */ 200 201 #if rbus 202 203 static int pccbb_open_win(struct pccbb_softc *, bus_space_tag_t, 204 bus_addr_t, bus_size_t, bus_space_handle_t, int flags); 205 static int pccbb_close_win(struct pccbb_softc *, bus_space_tag_t, 206 bus_space_handle_t, bus_size_t); 207 static int pccbb_winlist_insert(struct pccbb_win_chain_head *, bus_addr_t, 208 bus_size_t, bus_space_handle_t, int); 209 static int pccbb_winlist_delete(struct pccbb_win_chain_head *, 210 bus_space_handle_t, bus_size_t); 211 static void pccbb_winset(bus_addr_t align, struct pccbb_softc *, 212 bus_space_tag_t); 213 void pccbb_winlist_show(struct pccbb_win_chain *); 214 215 #endif /* rbus */ 216 217 /* for config_defer */ 218 static void pccbb_pci_callback(struct device *); 219 220 #if defined SHOW_REGS 221 static void cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, 222 bus_space_tag_t memt, bus_space_handle_t memh); 223 #endif 224 225 CFATTACH_DECL(cbb_pci, sizeof(struct pccbb_softc), 226 pcicbbmatch, pccbbattach, NULL, NULL); 227 228 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 229 pccbb_pcmcia_mem_alloc, 230 pccbb_pcmcia_mem_free, 231 pccbb_pcmcia_mem_map, 232 pccbb_pcmcia_mem_unmap, 233 pccbb_pcmcia_io_alloc, 234 pccbb_pcmcia_io_free, 235 pccbb_pcmcia_io_map, 236 pccbb_pcmcia_io_unmap, 237 pccbb_pcmcia_intr_establish, 238 pccbb_pcmcia_intr_disestablish, 239 pccbb_pcmcia_socket_enable, 240 pccbb_pcmcia_socket_disable, 241 pccbb_pcmcia_socket_settype, 242 pccbb_pcmcia_card_detect 243 }; 244 245 #if rbus 246 static struct cardbus_functions pccbb_funcs = { 247 pccbb_rbus_cb_space_alloc, 248 pccbb_rbus_cb_space_free, 249 pccbb_cb_intr_establish, 250 pccbb_cb_intr_disestablish, 251 pccbb_ctrl, 252 pccbb_power, 253 pccbb_make_tag, 254 pccbb_free_tag, 255 pccbb_conf_read, 256 pccbb_conf_write, 257 }; 258 #else 259 static struct cardbus_functions pccbb_funcs = { 260 pccbb_ctrl, 261 pccbb_power, 262 pccbb_mem_open, 263 pccbb_mem_close, 264 pccbb_io_open, 265 pccbb_io_close, 266 pccbb_cb_intr_establish, 267 pccbb_cb_intr_disestablish, 268 pccbb_make_tag, 269 pccbb_conf_read, 270 pccbb_conf_write, 271 }; 272 #endif 273 274 int 275 pcicbbmatch(struct device *parent, struct cfdata *match, void *aux) 276 { 277 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 278 279 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 280 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 281 PCI_INTERFACE(pa->pa_class) == 0) { 282 return 1; 283 } 284 285 return 0; 286 } 287 288 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 289 | ((prod) << PCI_PRODUCT_SHIFT)) 290 291 const struct yenta_chipinfo { 292 pcireg_t yc_id; /* vendor tag | product tag */ 293 int yc_chiptype; 294 int yc_flags; 295 } yc_chipsets[] = { 296 /* Texas Instruments chips */ 297 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 298 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 299 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 300 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 301 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI125X, 302 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 303 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 304 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 305 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 306 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 307 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 308 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 309 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI125X, 310 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 311 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI125X, 312 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 313 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 314 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 315 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 316 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 317 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI1420, 318 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 319 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI125X, 320 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 321 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 322 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 323 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1520), CB_TI12XX, 324 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 325 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4410YENTA), CB_TI12XX, 326 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 327 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4520YENTA), CB_TI12XX, 328 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 329 330 /* Ricoh chips */ 331 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 332 PCCBB_PCMCIA_MEM_32}, 333 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 334 PCCBB_PCMCIA_MEM_32}, 335 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 336 PCCBB_PCMCIA_MEM_32}, 337 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 338 PCCBB_PCMCIA_MEM_32}, 339 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 340 PCCBB_PCMCIA_MEM_32}, 341 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 342 PCCBB_PCMCIA_MEM_32}, 343 344 /* Toshiba products */ 345 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 346 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 347 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 348 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 349 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 350 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 351 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 352 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 353 354 /* Cirrus Logic products */ 355 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 356 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 357 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 358 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 359 360 /* sentinel, or Generic chip */ 361 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 362 }; 363 364 static int 365 cb_chipset(u_int32_t pci_id, int *flagp) 366 { 367 const struct yenta_chipinfo *yc; 368 369 /* Loop over except the last default entry. */ 370 for (yc = yc_chipsets; yc < yc_chipsets + 371 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 372 if (pci_id == yc->yc_id) 373 break; 374 375 if (flagp != NULL) 376 *flagp = yc->yc_flags; 377 378 return (yc->yc_chiptype); 379 } 380 381 static void 382 pccbb_shutdown(void *arg) 383 { 384 struct pccbb_softc *sc = arg; 385 pcireg_t command; 386 387 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 388 389 /* 390 * turn off power 391 * 392 * XXX - do not turn off power if chipset is TI 113X because 393 * only TI 1130 with PowerMac 2400 hangs in pccbb_power(). 394 */ 395 if (sc->sc_chipset != CB_TI113X) { 396 pccbb_power((cardbus_chipset_tag_t)sc, 397 CARDBUS_VCC_0V | CARDBUS_VPP_0V); 398 } 399 400 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 401 0); 402 403 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 404 405 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 406 PCI_COMMAND_MASTER_ENABLE); 407 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 408 409 } 410 411 void 412 pccbbattach(struct device *parent, struct device *self, void *aux) 413 { 414 struct pccbb_softc *sc = (void *)self; 415 struct pci_attach_args *pa = aux; 416 pci_chipset_tag_t pc = pa->pa_pc; 417 pcireg_t busreg, reg, sock_base; 418 bus_addr_t sockbase; 419 char devinfo[256]; 420 int flags; 421 int pwrmgt_offs; 422 423 #ifdef __HAVE_PCCBB_ATTACH_HOOK 424 pccbb_attach_hook(parent, self, pa); 425 #endif 426 427 callout_init(&sc->sc_insert_ch, 0); 428 callout_setfunc(&sc->sc_insert_ch, pci113x_insert, sc); 429 430 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 431 432 pci_devinfo(pa->pa_id, 0, 0, devinfo, sizeof(devinfo)); 433 printf(": %s (rev. 0x%02x)", devinfo, PCI_REVISION(pa->pa_class)); 434 DPRINTF((" (chipflags %x)", flags)); 435 printf("\n"); 436 437 TAILQ_INIT(&sc->sc_memwindow); 438 TAILQ_INIT(&sc->sc_iowindow); 439 440 #if rbus 441 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 442 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 443 444 #if 0 445 printf("pa->pa_memt: %08x vs rbus_mem->rb_bt: %08x\n", 446 pa->pa_memt, sc->sc_rbus_memt->rb_bt); 447 #endif 448 #endif /* rbus */ 449 450 sc->sc_flags &= ~CBB_MEMHMAPPED; 451 452 /* power management: set D0 state */ 453 sc->sc_pwrmgt_offs = 0; 454 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, 455 &pwrmgt_offs, 0)) { 456 reg = pci_conf_read(pc, pa->pa_tag, pwrmgt_offs + PCI_PMCSR); 457 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 458 reg & 0x100 /* PCI_PMCSR_PME_EN */) { 459 reg &= ~PCI_PMCSR_STATE_MASK; 460 reg |= PCI_PMCSR_STATE_D0; 461 reg &= ~(0x100 /* PCI_PMCSR_PME_EN */); 462 pci_conf_write(pc, pa->pa_tag, 463 pwrmgt_offs + PCI_PMCSR, reg); 464 } 465 466 sc->sc_pwrmgt_offs = pwrmgt_offs; 467 } 468 469 /* 470 * MAP socket registers and ExCA registers on memory-space 471 * When no valid address is set on socket base registers (on pci 472 * config space), get it not polite way. 473 */ 474 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 475 476 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 477 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 478 /* The address must be valid. */ 479 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 480 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL)) { 481 printf("%s: can't map socket base address 0x%lx\n", 482 sc->sc_dev.dv_xname, (unsigned long)sock_base); 483 /* 484 * I think it's funny: socket base registers must be 485 * mapped on memory space, but ... 486 */ 487 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 488 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 489 NULL)) { 490 printf("%s: can't map socket base address" 491 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 492 (unsigned long)sockbase); 493 /* give up... allocate reg space via rbus. */ 494 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 495 } else 496 sc->sc_flags |= CBB_MEMHMAPPED; 497 } else { 498 DPRINTF(("%s: socket base address 0x%lx\n", 499 sc->sc_dev.dv_xname, (unsigned long)sockbase)); 500 sc->sc_flags |= CBB_MEMHMAPPED; 501 } 502 } 503 504 sc->sc_mem_start = 0; /* XXX */ 505 sc->sc_mem_end = 0xffffffff; /* XXX */ 506 507 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 508 509 /* pccbb_machdep.c end */ 510 511 #if defined CBB_DEBUG 512 { 513 static const char *intrname[] = { "NON", "A", "B", "C", "D" }; 514 printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname, 515 intrname[pa->pa_intrpin], pa->pa_intrline); 516 } 517 #endif 518 519 /* setup softc */ 520 sc->sc_pc = pc; 521 sc->sc_iot = pa->pa_iot; 522 sc->sc_memt = pa->pa_memt; 523 sc->sc_dmat = pa->pa_dmat; 524 sc->sc_tag = pa->pa_tag; 525 sc->sc_function = pa->pa_function; 526 sc->sc_sockbase = sock_base; 527 sc->sc_busnum = busreg; 528 529 memcpy(&sc->sc_pa, pa, sizeof(*pa)); 530 531 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 532 533 shutdownhook_establish(pccbb_shutdown, sc); 534 535 /* Disable legacy register mapping. */ 536 switch (sc->sc_chipset) { 537 case CB_RX5C46X: /* fallthrough */ 538 #if 0 539 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 540 case CB_RX5C47X: 541 #endif 542 /* 543 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 544 * cannot be disabled by substituting 0 into PCI_LEGACY 545 * register. Ricoh CardBus bridges have special bits on Bridge 546 * control reg (addr 0x3e on PCI config space). 547 */ 548 reg = pci_conf_read(pc, pa->pa_tag, PCI_BRIDGE_CONTROL_REG); 549 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 550 pci_conf_write(pc, pa->pa_tag, PCI_BRIDGE_CONTROL_REG, reg); 551 break; 552 553 default: 554 /* XXX I don't know proper way to kill legacy I/O. */ 555 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 556 break; 557 } 558 559 config_defer(self, pccbb_pci_callback); 560 } 561 562 563 564 565 /* 566 * static void pccbb_pci_callback(struct device *self) 567 * 568 * The actual attach routine: get memory space for YENTA register 569 * space, setup YENTA register and route interrupt. 570 * 571 * This function should be deferred because this device may obtain 572 * memory space dynamically. This function must avoid obtaining 573 * memory area which has already kept for another device. 574 */ 575 static void 576 pccbb_pci_callback(struct device *self) 577 { 578 struct pccbb_softc *sc = (void *)self; 579 pci_chipset_tag_t pc = sc->sc_pc; 580 pci_intr_handle_t ih; 581 const char *intrstr = NULL; 582 bus_addr_t sockbase; 583 struct cbslot_attach_args cba; 584 struct pcmciabus_attach_args paa; 585 struct cardslot_attach_args caa; 586 struct cardslot_softc *csc; 587 588 if (!(sc->sc_flags & CBB_MEMHMAPPED)) { 589 /* The socket registers aren't mapped correctly. */ 590 #if rbus 591 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 592 (sc->sc_chipset == CB_RX5C47X 593 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 594 0, &sockbase, &sc->sc_base_memh)) { 595 return; 596 } 597 sc->sc_base_memt = sc->sc_memt; 598 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 599 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 600 sc->sc_dev.dv_xname, (unsigned long)sockbase, 601 (unsigned long)pci_conf_read(pc, sc->sc_tag, 602 PCI_SOCKBASE))); 603 #else 604 sc->sc_base_memt = sc->sc_memt; 605 #if !defined CBB_PCI_BASE 606 #define CBB_PCI_BASE 0x20000000 607 #endif 608 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 609 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 610 /* cannot allocate memory space */ 611 return; 612 } 613 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 614 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 615 sc->sc_dev.dv_xname, (unsigned long)sock_base, 616 (unsigned long)pci_conf_read(pc, 617 sc->sc_tag, PCI_SOCKBASE))); 618 sc->sc_sockbase = sockbase; 619 #endif 620 sc->sc_flags |= CBB_MEMHMAPPED; 621 } 622 623 /* bus bridge initialization */ 624 pccbb_chipinit(sc); 625 626 /* clear data structure for child device interrupt handlers */ 627 LIST_INIT(&sc->sc_pil); 628 sc->sc_pil_intr_enable = 1; 629 630 /* Map and establish the interrupt. */ 631 if (pci_intr_map(&sc->sc_pa, &ih)) { 632 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 633 return; 634 } 635 intrstr = pci_intr_string(pc, ih); 636 637 /* 638 * XXX pccbbintr should be called under the priority lower 639 * than any other hard interupts. 640 */ 641 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 642 643 if (sc->sc_ih == NULL) { 644 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 645 if (intrstr != NULL) { 646 printf(" at %s", intrstr); 647 } 648 printf("\n"); 649 return; 650 } 651 652 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 653 powerhook_establish(sc->sc_dev.dv_xname, pccbb_powerhook, sc); 654 655 { 656 u_int32_t sockstat; 657 658 sockstat = bus_space_read_4(sc->sc_base_memt, 659 sc->sc_base_memh, CB_SOCKET_STAT); 660 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 661 sc->sc_flags |= CBB_CARDEXIST; 662 } 663 } 664 665 /* 666 * attach cardbus 667 */ 668 { 669 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 670 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 671 672 /* initialize cbslot_attach */ 673 cba.cba_busname = "cardbus"; 674 cba.cba_iot = sc->sc_iot; 675 cba.cba_memt = sc->sc_memt; 676 cba.cba_dmat = sc->sc_dmat; 677 cba.cba_bus = (busreg >> 8) & 0x0ff; 678 cba.cba_cc = (void *)sc; 679 cba.cba_cf = &pccbb_funcs; 680 cba.cba_intrline = sc->sc_pa.pa_intrline; 681 682 #if rbus 683 cba.cba_rbus_iot = sc->sc_rbus_iot; 684 cba.cba_rbus_memt = sc->sc_rbus_memt; 685 #endif 686 687 cba.cba_cacheline = PCI_CACHELINE(bhlc); 688 cba.cba_max_lattimer = PCI_LATTIMER(bhlc); 689 690 if (bootverbose) { 691 printf("%s: cacheline 0x%x lattimer 0x%x\n", 692 sc->sc_dev.dv_xname, cba.cba_cacheline, 693 cba.cba_max_lattimer); 694 printf("%s: bhlc 0x%x\n", 695 device_xname(&sc->sc_dev), bhlc); 696 } 697 #if defined SHOW_REGS 698 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 699 sc->sc_base_memh); 700 #endif 701 } 702 703 pccbb_pcmcia_attach_setup(sc, &paa); 704 caa.caa_cb_attach = NULL; 705 if (cba.cba_bus == 0) 706 printf("%s: secondary bus number uninitialized; try PCI_BUS_FIXUP\n", sc->sc_dev.dv_xname); 707 else 708 caa.caa_cb_attach = &cba; 709 caa.caa_16_attach = &paa; 710 caa.caa_ph = &sc->sc_pcmcia_h; 711 712 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 713 DPRINTF(("%s: found cardslot\n", __func__)); 714 sc->sc_csc = csc; 715 } 716 717 return; 718 } 719 720 721 722 723 724 /* 725 * static void pccbb_chipinit(struct pccbb_softc *sc) 726 * 727 * This function initialize YENTA chip registers listed below: 728 * 1) PCI command reg, 729 * 2) PCI and CardBus latency timer, 730 * 3) route PCI interrupt, 731 * 4) close all memory and io windows. 732 * 5) turn off bus power. 733 * 6) card detect and power cycle interrupts on. 734 * 7) clear interrupt 735 */ 736 static void 737 pccbb_chipinit(struct pccbb_softc *sc) 738 { 739 pci_chipset_tag_t pc = sc->sc_pc; 740 pcitag_t tag = sc->sc_tag; 741 bus_space_tag_t bmt = sc->sc_base_memt; 742 bus_space_handle_t bmh = sc->sc_base_memh; 743 pcireg_t bcr, bhlc, cbctl, csr, lscp, mfunc, mrburst, slotctl, sockctl, 744 sockmask, sysctrl; 745 746 /* 747 * Set PCI command reg. 748 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 749 */ 750 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 751 /* I believe it is harmless. */ 752 csr |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 753 PCI_COMMAND_MASTER_ENABLE); 754 csr |= (PCI_COMMAND_PARITY_ENABLE|PCI_COMMAND_SERR_ENABLE); 755 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 756 757 /* 758 * Set CardBus latency timer. 759 */ 760 lscp = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 761 if (PCI_CB_LATENCY(lscp) < 0x20) { 762 lscp &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 763 lscp |= (0x20 << PCI_CB_LATENCY_SHIFT); 764 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, lscp); 765 } 766 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 767 PCI_CB_LATENCY(lscp), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 768 769 /* 770 * Set PCI latency timer. 771 */ 772 bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG); 773 if (PCI_LATTIMER(bhlc) < 0x10) { 774 bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 775 bhlc |= (0x10 << PCI_LATTIMER_SHIFT); 776 pci_conf_write(pc, tag, PCI_BHLC_REG, bhlc); 777 } 778 DPRINTF(("PCI latency timer 0x%x (%x)\n", 779 PCI_LATTIMER(bhlc), pci_conf_read(pc, tag, PCI_BHLC_REG))); 780 781 782 /* Route functional interrupts to PCI. */ 783 bcr = pci_conf_read(pc, tag, PCI_BRIDGE_CONTROL_REG); 784 bcr |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 785 bcr |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 786 /* assert reset */ 787 bcr |= PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT; 788 /* Set master abort mode to 1, forward SERR# from secondary 789 * to primary, and detect parity errors on secondary. 790 */ 791 bcr |= PCI_BRIDGE_CONTROL_MABRT << PCI_BRIDGE_CONTROL_SHIFT; 792 bcr |= PCI_BRIDGE_CONTROL_SERR << PCI_BRIDGE_CONTROL_SHIFT; 793 bcr |= PCI_BRIDGE_CONTROL_PERE << PCI_BRIDGE_CONTROL_SHIFT; 794 pci_conf_write(pc, tag, PCI_BRIDGE_CONTROL_REG, bcr); 795 796 switch (sc->sc_chipset) { 797 case CB_TI113X: 798 cbctl = pci_conf_read(pc, tag, PCI_CBCTRL); 799 /* This bit is shared, but may read as 0 on some chips, so set 800 it explicitly on both functions. */ 801 cbctl |= PCI113X_CBCTRL_PCI_IRQ_ENA; 802 /* CSC intr enable */ 803 cbctl |= PCI113X_CBCTRL_PCI_CSC; 804 /* functional intr prohibit | prohibit ISA routing */ 805 cbctl &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 806 pci_conf_write(pc, tag, PCI_CBCTRL, cbctl); 807 break; 808 809 case CB_TI1420: 810 sysctrl = pci_conf_read(pc, tag, PCI_SYSCTRL); 811 mrburst = pccbb_burstup 812 ? PCI1420_SYSCTRL_MRBURST : PCI1420_SYSCTRL_MRBURSTDN; 813 if ((sysctrl & PCI1420_SYSCTRL_MRBURST) == mrburst) { 814 printf("%s: %swrite bursts enabled\n", 815 device_xname(&sc->sc_dev), 816 pccbb_burstup ? "read/" : ""); 817 } else if (pccbb_burstup) { 818 printf("%s: enabling read/write bursts\n", 819 device_xname(&sc->sc_dev)); 820 sysctrl |= PCI1420_SYSCTRL_MRBURST; 821 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 822 } else { 823 printf("%s: disabling read bursts, " 824 "enabling write bursts\n", 825 device_xname(&sc->sc_dev)); 826 sysctrl |= PCI1420_SYSCTRL_MRBURSTDN; 827 sysctrl &= ~PCI1420_SYSCTRL_MRBURSTUP; 828 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 829 } 830 /*FALLTHROUGH*/ 831 case CB_TI12XX: 832 /* 833 * Some TI 12xx (and [14][45]xx) based pci cards 834 * sometimes have issues with the MFUNC register not 835 * being initialized due to a bad EEPROM on board. 836 * Laptops that this matters on have this register 837 * properly initialized. 838 * 839 * The TI125X parts have a different register. 840 */ 841 mfunc = pci_conf_read(pc, tag, PCI12XX_MFUNC); 842 if (mfunc == 0) { 843 mfunc &= ~PCI12XX_MFUNC_PIN0; 844 mfunc |= PCI12XX_MFUNC_PIN0_INTA; 845 if ((pci_conf_read(pc, tag, PCI_SYSCTRL) & 846 PCI12XX_SYSCTRL_INTRTIE) == 0) { 847 mfunc &= ~PCI12XX_MFUNC_PIN1; 848 mfunc |= PCI12XX_MFUNC_PIN1_INTB; 849 } 850 pci_conf_write(pc, tag, PCI12XX_MFUNC, mfunc); 851 } 852 /* fallthrough */ 853 854 case CB_TI125X: 855 /* 856 * Disable zoom video. Some machines initialize this 857 * improperly and experience has shown that this helps 858 * prevent strange behavior. 859 */ 860 pci_conf_write(pc, tag, PCI12XX_MMCTRL, 0); 861 862 sysctrl = pci_conf_read(pc, tag, PCI_SYSCTRL); 863 sysctrl |= PCI12XX_SYSCTRL_VCCPROT; 864 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 865 cbctl = pci_conf_read(pc, tag, PCI_CBCTRL); 866 cbctl |= PCI12XX_CBCTRL_CSC; 867 pci_conf_write(pc, tag, PCI_CBCTRL, cbctl); 868 break; 869 870 case CB_TOPIC95B: 871 sockctl = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 872 sockctl |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 873 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, sockctl); 874 slotctl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 875 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 876 sc->sc_dev.dv_xname, slotctl)); 877 slotctl |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 878 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 879 slotctl &= ~TOPIC_SLOT_CTRL_SWDETECT; 880 DPRINTF(("0x%x\n", slotctl)); 881 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slotctl); 882 break; 883 884 case CB_TOPIC97: 885 slotctl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 886 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 887 sc->sc_dev.dv_xname, slotctl)); 888 slotctl |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 889 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 890 slotctl &= ~TOPIC_SLOT_CTRL_SWDETECT; 891 slotctl |= TOPIC97_SLOT_CTRL_PCIINT; 892 slotctl &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 893 DPRINTF(("0x%x\n", slotctl)); 894 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slotctl); 895 /* make sure to assert LV card support bits */ 896 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 897 0x800 + 0x3e, 898 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 899 0x800 + 0x3e) | 0x03); 900 break; 901 } 902 903 /* Close all memory and I/O windows. */ 904 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 905 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 906 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 907 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 908 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 909 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 910 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 911 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 912 913 /* reset 16-bit pcmcia bus */ 914 bus_space_write_1(bmt, bmh, 0x800 + PCIC_INTR, 915 bus_space_read_1(bmt, bmh, 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 916 917 /* turn off power */ 918 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 919 920 /* CSC Interrupt: Card detect and power cycle interrupts on */ 921 sockmask = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 922 sockmask |= CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; 923 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, sockmask); 924 /* reset interrupt */ 925 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 926 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 927 } 928 929 930 931 932 /* 933 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 934 * struct pcmciabus_attach_args *paa) 935 * 936 * This function attaches 16-bit PCcard bus. 937 */ 938 STATIC void 939 pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 940 struct pcmciabus_attach_args *paa) 941 { 942 struct pcic_handle *ph = &sc->sc_pcmcia_h; 943 #if rbus 944 rbus_tag_t rb; 945 #endif 946 947 /* initialize pcmcia part in pccbb_softc */ 948 ph->ph_parent = (struct device *)sc; 949 ph->sock = sc->sc_function; 950 ph->flags = 0; 951 ph->shutdown = 0; 952 ph->ih_irq = sc->sc_pa.pa_intrline; 953 ph->ph_bus_t = sc->sc_base_memt; 954 ph->ph_bus_h = sc->sc_base_memh; 955 ph->ph_read = pccbb_pcmcia_read; 956 ph->ph_write = pccbb_pcmcia_write; 957 sc->sc_pct = &pccbb_pcmcia_funcs; 958 959 /* 960 * We need to do a few things here: 961 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 962 * setting the IRQ numbers to 0. 963 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 964 * routing of CSC interrupts (e.g. card removal) to PCI while in 965 * PCMCIA mode. We just leave this set all the time. 966 * 3) Enable card insertion/removal interrupts in case the chip also 967 * needs that while in PCMCIA mode. 968 * 4) Clear any pending CSC interrupt. 969 */ 970 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE); 971 if (sc->sc_chipset == CB_TI113X) { 972 Pcic_write(ph, PCIC_CSC_INTR, 0); 973 } else { 974 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 975 Pcic_read(ph, PCIC_CSC); 976 } 977 978 /* initialize pcmcia bus attachment */ 979 paa->paa_busname = "pcmcia"; 980 paa->pct = sc->sc_pct; 981 paa->pch = ph; 982 paa->iobase = 0; /* I don't use them */ 983 paa->iosize = 0; 984 #if rbus 985 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 986 paa->iobase = rb->rb_start + rb->rb_offset; 987 paa->iosize = rb->rb_end - rb->rb_start; 988 #endif 989 990 return; 991 } 992 993 #if 0 994 STATIC void 995 pccbb_pcmcia_attach_card(struct pcic_handle *ph) 996 { 997 if (ph->flags & PCIC_FLAG_CARDP) { 998 panic("pccbb_pcmcia_attach_card: already attached"); 999 } 1000 1001 /* call the MI attach function */ 1002 pcmcia_card_attach(ph->pcmcia); 1003 1004 ph->flags |= PCIC_FLAG_CARDP; 1005 } 1006 1007 STATIC void 1008 pccbb_pcmcia_detach_card(struct pcic_handle *ph, int flags) 1009 { 1010 if (!(ph->flags & PCIC_FLAG_CARDP)) { 1011 panic("pccbb_pcmcia_detach_card: already detached"); 1012 } 1013 1014 ph->flags &= ~PCIC_FLAG_CARDP; 1015 1016 /* call the MI detach function */ 1017 pcmcia_card_detach(ph->pcmcia, flags); 1018 } 1019 #endif 1020 1021 /* 1022 * int pccbbintr(arg) 1023 * void *arg; 1024 * This routine handles the interrupt from Yenta PCI-CardBus bridge 1025 * itself. 1026 */ 1027 int 1028 pccbbintr(void *arg) 1029 { 1030 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1031 u_int32_t sockevent, sockstate; 1032 bus_space_tag_t memt = sc->sc_base_memt; 1033 bus_space_handle_t memh = sc->sc_base_memh; 1034 struct pcic_handle *ph = &sc->sc_pcmcia_h; 1035 1036 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 1037 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 1038 Pcic_read(ph, PCIC_CSC); 1039 1040 if (sockevent == 0) { 1041 /* This intr is not for me: it may be for my child devices. */ 1042 if (sc->sc_pil_intr_enable) { 1043 return pccbbintr_function(sc); 1044 } else { 1045 return 0; 1046 } 1047 } 1048 1049 aprint_debug("%s: enter sockevent %" PRIx32 "\n", __func__, sockevent); 1050 1051 if (sockevent & CB_SOCKET_EVENT_CD) { 1052 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1053 if (0x00 != (sockstate & CB_SOCKET_STAT_CD)) { 1054 /* A card should be removed. */ 1055 if (sc->sc_flags & CBB_CARDEXIST) { 1056 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 1057 sockevent)); 1058 DPRINTF((" card removed, 0x%08x\n", sockstate)); 1059 sc->sc_flags &= ~CBB_CARDEXIST; 1060 if (sc->sc_csc->sc_status & 1061 CARDSLOT_STATUS_CARD_16) { 1062 #if 0 1063 struct pcic_handle *ph = 1064 &sc->sc_pcmcia_h; 1065 1066 pcmcia_card_deactivate(ph->pcmcia); 1067 pccbb_pcmcia_socket_disable(ph); 1068 pccbb_pcmcia_detach_card(ph, 1069 DETACH_FORCE); 1070 #endif 1071 cardslot_event_throw(sc->sc_csc, 1072 CARDSLOT_EVENT_REMOVAL_16); 1073 } else if (sc->sc_csc->sc_status & 1074 CARDSLOT_STATUS_CARD_CB) { 1075 /* Cardbus intr removed */ 1076 cardslot_event_throw(sc->sc_csc, 1077 CARDSLOT_EVENT_REMOVAL_CB); 1078 } 1079 } else if (sc->sc_flags & CBB_INSERTING) { 1080 sc->sc_flags &= ~CBB_INSERTING; 1081 callout_stop(&sc->sc_insert_ch); 1082 } 1083 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 1084 /* 1085 * The pccbbintr may called from powerdown hook when 1086 * the system resumed, to detect the card 1087 * insertion/removal during suspension. 1088 */ 1089 (sc->sc_flags & CBB_CARDEXIST) == 0) { 1090 if (sc->sc_flags & CBB_INSERTING) { 1091 callout_stop(&sc->sc_insert_ch); 1092 } 1093 callout_schedule(&sc->sc_insert_ch, hz / 5); 1094 sc->sc_flags |= CBB_INSERTING; 1095 } 1096 } 1097 1098 if (sockevent & CB_SOCKET_EVENT_POWER) { 1099 DPRINTF(("Powercycling because of socket event\n")); 1100 /* XXX: Does not happen when attaching a 16-bit card */ 1101 sc->sc_pwrcycle++; 1102 wakeup(&sc->sc_pwrcycle); 1103 } 1104 1105 return (1); 1106 } 1107 1108 /* 1109 * static int pccbbintr_function(struct pccbb_softc *sc) 1110 * 1111 * This function calls each interrupt handler registered at the 1112 * bridge. The interrupt handlers are called in registered order. 1113 */ 1114 static int 1115 pccbbintr_function(struct pccbb_softc *sc) 1116 { 1117 int retval = 0, val; 1118 struct pccbb_intrhand_list *pil; 1119 int s; 1120 1121 for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1122 pil = LIST_NEXT(pil, pil_next)) { 1123 s = splraiseipl(pil->pil_icookie); 1124 val = (*pil->pil_func)(pil->pil_arg); 1125 splx(s); 1126 1127 retval = retval == 1 ? 1 : 1128 retval == 0 ? val : val != 0 ? val : retval; 1129 } 1130 1131 return retval; 1132 } 1133 1134 static void 1135 pci113x_insert(void *arg) 1136 { 1137 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1138 u_int32_t sockevent, sockstate; 1139 1140 if (!(sc->sc_flags & CBB_INSERTING)) { 1141 /* We add a card only under inserting state. */ 1142 return; 1143 } 1144 sc->sc_flags &= ~CBB_INSERTING; 1145 1146 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1147 CB_SOCKET_EVENT); 1148 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1149 CB_SOCKET_STAT); 1150 1151 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1152 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1153 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1154 sc->sc_flags |= CBB_CARDEXIST; 1155 /* call pccard interrupt handler here */ 1156 if (sockstate & CB_SOCKET_STAT_16BIT) { 1157 /* 16-bit card found */ 1158 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1159 cardslot_event_throw(sc->sc_csc, 1160 CARDSLOT_EVENT_INSERTION_16); 1161 } else if (sockstate & CB_SOCKET_STAT_CB) { 1162 /* cardbus card found */ 1163 /* cardbus_attach_card(sc->sc_csc); */ 1164 cardslot_event_throw(sc->sc_csc, 1165 CARDSLOT_EVENT_INSERTION_CB); 1166 } else { 1167 /* who are you? */ 1168 } 1169 } else { 1170 callout_schedule(&sc->sc_insert_ch, hz / 10); 1171 } 1172 } 1173 1174 #define PCCBB_PCMCIA_OFFSET 0x800 1175 static u_int8_t 1176 pccbb_pcmcia_read(struct pcic_handle *ph, int reg) 1177 { 1178 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1179 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1180 1181 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1182 PCCBB_PCMCIA_OFFSET + reg); 1183 } 1184 1185 static void 1186 pccbb_pcmcia_write(struct pcic_handle *ph, int reg, u_int8_t val) 1187 { 1188 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1189 val); 1190 1191 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1192 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1193 } 1194 1195 /* 1196 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1197 */ 1198 STATIC int 1199 pccbb_ctrl(cardbus_chipset_tag_t ct, int command) 1200 { 1201 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1202 1203 switch (command) { 1204 case CARDBUS_CD: 1205 if (2 == pccbb_detect_card(sc)) { 1206 int retval = 0; 1207 int status = cb_detect_voltage(sc); 1208 if (PCCARD_VCC_5V & status) { 1209 retval |= CARDBUS_5V_CARD; 1210 } 1211 if (PCCARD_VCC_3V & status) { 1212 retval |= CARDBUS_3V_CARD; 1213 } 1214 if (PCCARD_VCC_XV & status) { 1215 retval |= CARDBUS_XV_CARD; 1216 } 1217 if (PCCARD_VCC_YV & status) { 1218 retval |= CARDBUS_YV_CARD; 1219 } 1220 return retval; 1221 } else { 1222 return 0; 1223 } 1224 case CARDBUS_RESET: 1225 return cb_reset(sc); 1226 case CARDBUS_IO_ENABLE: /* fallthrough */ 1227 case CARDBUS_IO_DISABLE: /* fallthrough */ 1228 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1229 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1230 case CARDBUS_BM_ENABLE: /* fallthrough */ 1231 case CARDBUS_BM_DISABLE: /* fallthrough */ 1232 /* XXX: I think we don't need to call this function below. */ 1233 return pccbb_cardenable(sc, command); 1234 } 1235 1236 return 0; 1237 } 1238 1239 /* 1240 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1241 * This function returns true when it succeeds and returns false when 1242 * it fails. 1243 */ 1244 STATIC int 1245 pccbb_power(cardbus_chipset_tag_t ct, int command) 1246 { 1247 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1248 u_int32_t status, osock_ctrl, sock_ctrl, reg_ctrl; 1249 bus_space_tag_t memt = sc->sc_base_memt; 1250 bus_space_handle_t memh = sc->sc_base_memh; 1251 int on = 0, pwrcycle, s, times; 1252 struct timeval before, after, diff; 1253 1254 DPRINTF(("pccbb_power: %s and %s [0x%x]\n", 1255 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1256 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1257 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1258 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1259 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1260 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1261 "UNKNOWN", 1262 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1263 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1264 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1265 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1266 "UNKNOWN", command)); 1267 1268 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1269 osock_ctrl = sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1270 1271 switch (command & CARDBUS_VCCMASK) { 1272 case CARDBUS_VCC_UC: 1273 break; 1274 case CARDBUS_VCC_5V: 1275 on++; 1276 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1277 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1278 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1279 } else { 1280 printf("%s: BAD voltage request: no 5 V card\n", 1281 sc->sc_dev.dv_xname); 1282 return 0; 1283 } 1284 break; 1285 case CARDBUS_VCC_3V: 1286 on++; 1287 if (CB_SOCKET_STAT_3VCARD & status) { 1288 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1289 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1290 } else { 1291 printf("%s: BAD voltage request: no 3.3 V card\n", 1292 sc->sc_dev.dv_xname); 1293 return 0; 1294 } 1295 break; 1296 case CARDBUS_VCC_0V: 1297 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1298 break; 1299 default: 1300 return 0; /* power NEVER changed */ 1301 } 1302 1303 switch (command & CARDBUS_VPPMASK) { 1304 case CARDBUS_VPP_UC: 1305 break; 1306 case CARDBUS_VPP_0V: 1307 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1308 break; 1309 case CARDBUS_VPP_VCC: 1310 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1311 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1312 break; 1313 case CARDBUS_VPP_12V: 1314 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1315 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1316 break; 1317 } 1318 1319 pwrcycle = sc->sc_pwrcycle; 1320 aprint_debug("%s: osock_ctrl %#" PRIx32 " sock_ctrl %#" PRIx32 "\n", 1321 device_xname(&sc->sc_dev), osock_ctrl, sock_ctrl); 1322 1323 microtime(&before); 1324 s = splbio(); 1325 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1326 1327 /* 1328 * Wait as long as 200ms for a power-cycle interrupt. If 1329 * interrupts are enabled, but the socket has already 1330 * changed to the desired status, keep waiting for the 1331 * interrupt. "Consuming" the interrupt in this way keeps 1332 * the interrupt from prematurely waking some subsequent 1333 * pccbb_power call. 1334 * 1335 * XXX Not every bridge interrupts on the ->OFF transition. 1336 * XXX That's ok, we will time-out after 200ms. 1337 * 1338 * XXX The power cycle event will never happen when attaching 1339 * XXX a 16-bit card. That's ok, we will time-out after 1340 * XXX 200ms. 1341 */ 1342 for (times = 5; --times >= 0; ) { 1343 if (cold) 1344 DELAY(40 * 1000); 1345 else { 1346 (void)tsleep(&sc->sc_pwrcycle, PWAIT, "pccpwr", 1347 hz / 25); 1348 if (pwrcycle == sc->sc_pwrcycle) 1349 continue; 1350 } 1351 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1352 if ((status & CB_SOCKET_STAT_PWRCYCLE) != 0 && on) 1353 break; 1354 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0 && !on) 1355 break; 1356 } 1357 splx(s); 1358 microtime(&after); 1359 timersub(&after, &before, &diff); 1360 aprint_debug("%s: wait took%s %ld.%06lds\n", sc->sc_dev.dv_xname, 1361 (on && times < 0) ? " too long" : "", diff.tv_sec, diff.tv_usec); 1362 1363 /* 1364 * Ok, wait a bit longer for things to settle. 1365 */ 1366 if (on && sc->sc_chipset == CB_TOPIC95B) 1367 delay_ms(100, sc); 1368 1369 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1370 1371 if (on && sc->sc_chipset != CB_TOPIC95B) { 1372 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0) 1373 printf("%s: power on failed?\n", sc->sc_dev.dv_xname); 1374 } 1375 1376 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1377 printf("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1378 sc->sc_dev.dv_xname, sock_ctrl, status); 1379 printf("%s: disabling socket\n", sc->sc_dev.dv_xname); 1380 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1381 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1382 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1383 status &= ~CB_SOCKET_STAT_BADVCC; 1384 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, status); 1385 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1386 CB_SOCKET_STAT)); 1387 return 0; 1388 } 1389 1390 if (sc->sc_chipset == CB_TOPIC97) { 1391 reg_ctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL); 1392 reg_ctrl &= ~TOPIC97_REG_CTRL_TESTMODE; 1393 if ((command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V) 1394 reg_ctrl &= ~TOPIC97_REG_CTRL_CLKRUN_ENA; 1395 else 1396 reg_ctrl |= TOPIC97_REG_CTRL_CLKRUN_ENA; 1397 pci_conf_write(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL, reg_ctrl); 1398 } 1399 1400 return 1; /* power changed correctly */ 1401 } 1402 1403 #if defined CB_PCMCIA_POLL 1404 struct cb_poll_str { 1405 void *arg; 1406 int (*func)(void *); 1407 int level; 1408 pccard_chipset_tag_t ct; 1409 int count; 1410 struct callout poll_ch; 1411 }; 1412 1413 static struct cb_poll_str cb_poll[10]; 1414 static int cb_poll_n = 0; 1415 1416 static void cb_pcmcia_poll(void *arg); 1417 1418 static void 1419 cb_pcmcia_poll(void *arg) 1420 { 1421 struct cb_poll_str *poll = arg; 1422 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1423 struct pccbb_softc *sc = psc->cpc_parent; 1424 int s; 1425 u_int32_t spsr; /* socket present-state reg */ 1426 1427 callout_reset(&poll->poll_ch, hz / 10, cb_pcmcia_poll, poll); 1428 switch (poll->level) { 1429 case IPL_NET: 1430 s = splnet(); 1431 break; 1432 case IPL_BIO: 1433 s = splbio(); 1434 break; 1435 case IPL_TTY: /* fallthrough */ 1436 default: 1437 s = spltty(); 1438 break; 1439 } 1440 1441 spsr = 1442 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1443 CB_SOCKET_STAT); 1444 1445 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1446 if (!(spsr & 0x40)) { /* CINT low */ 1447 #else 1448 if (1) { 1449 #endif 1450 if ((*poll->func) (poll->arg) == 1) { 1451 ++poll->count; 1452 printf("intr: reported from poller, 0x%x\n", spsr); 1453 #if defined LEVEL2 1454 } else { 1455 printf("intr: miss! 0x%x\n", spsr); 1456 #endif 1457 } 1458 } 1459 splx(s); 1460 } 1461 #endif /* defined CB_PCMCIA_POLL */ 1462 1463 /* 1464 * static int pccbb_detect_card(struct pccbb_softc *sc) 1465 * return value: 0 if no card exists. 1466 * 1 if 16-bit card exists. 1467 * 2 if cardbus card exists. 1468 */ 1469 static int 1470 pccbb_detect_card(struct pccbb_softc *sc) 1471 { 1472 bus_space_handle_t base_memh = sc->sc_base_memh; 1473 bus_space_tag_t base_memt = sc->sc_base_memt; 1474 u_int32_t sockstat = 1475 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1476 int retval = 0; 1477 1478 /* CD1 and CD2 asserted */ 1479 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1480 /* card must be present */ 1481 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1482 /* NOTACARD DEASSERTED */ 1483 if (CB_SOCKET_STAT_CB & sockstat) { 1484 /* CardBus mode */ 1485 retval = 2; 1486 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1487 /* 16-bit mode */ 1488 retval = 1; 1489 } 1490 } 1491 } 1492 return retval; 1493 } 1494 1495 /* 1496 * STATIC int cb_reset(struct pccbb_softc *sc) 1497 * This function resets CardBus card. 1498 */ 1499 STATIC int 1500 cb_reset(struct pccbb_softc *sc) 1501 { 1502 /* 1503 * Reset Assert at least 20 ms 1504 * Some machines request longer duration. 1505 */ 1506 int reset_duration = 1507 (sc->sc_chipset == CB_RX5C47X ? 400 : 50); 1508 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1509 1510 /* Reset bit Assert (bit 6 at 0x3E) */ 1511 bcr |= CB_BCR_RESET_ENABLE; 1512 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr); 1513 delay_ms(reset_duration, sc); 1514 1515 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1516 /* Reset bit Deassert (bit 6 at 0x3E) */ 1517 bcr &= ~CB_BCR_RESET_ENABLE; 1518 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr); 1519 delay_ms(reset_duration, sc); 1520 } 1521 /* No card found on the slot. Keep Reset. */ 1522 return 1; 1523 } 1524 1525 /* 1526 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1527 * This function detect card Voltage. 1528 */ 1529 STATIC int 1530 cb_detect_voltage(struct pccbb_softc *sc) 1531 { 1532 u_int32_t psr; /* socket present-state reg */ 1533 bus_space_tag_t iot = sc->sc_base_memt; 1534 bus_space_handle_t ioh = sc->sc_base_memh; 1535 int vol = PCCARD_VCC_UKN; /* set 0 */ 1536 1537 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1538 1539 if (0x400u & psr) { 1540 vol |= PCCARD_VCC_5V; 1541 } 1542 if (0x800u & psr) { 1543 vol |= PCCARD_VCC_3V; 1544 } 1545 1546 return vol; 1547 } 1548 1549 STATIC int 1550 cbbprint(void *aux, const char *pcic) 1551 { 1552 #if 0 1553 struct cbslot_attach_args *cba = aux; 1554 1555 if (cba->cba_slot >= 0) { 1556 aprint_normal(" slot %d", cba->cba_slot); 1557 } 1558 #endif 1559 return UNCONF; 1560 } 1561 1562 /* 1563 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1564 * This function enables and disables the card 1565 */ 1566 STATIC int 1567 pccbb_cardenable(struct pccbb_softc *sc, int function) 1568 { 1569 u_int32_t command = 1570 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1571 1572 DPRINTF(("pccbb_cardenable:")); 1573 switch (function) { 1574 case CARDBUS_IO_ENABLE: 1575 command |= PCI_COMMAND_IO_ENABLE; 1576 break; 1577 case CARDBUS_IO_DISABLE: 1578 command &= ~PCI_COMMAND_IO_ENABLE; 1579 break; 1580 case CARDBUS_MEM_ENABLE: 1581 command |= PCI_COMMAND_MEM_ENABLE; 1582 break; 1583 case CARDBUS_MEM_DISABLE: 1584 command &= ~PCI_COMMAND_MEM_ENABLE; 1585 break; 1586 case CARDBUS_BM_ENABLE: 1587 command |= PCI_COMMAND_MASTER_ENABLE; 1588 break; 1589 case CARDBUS_BM_DISABLE: 1590 command &= ~PCI_COMMAND_MASTER_ENABLE; 1591 break; 1592 default: 1593 return 0; 1594 } 1595 1596 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1597 DPRINTF((" command reg 0x%x\n", command)); 1598 return 1; 1599 } 1600 1601 #if !rbus 1602 static int 1603 pccbb_io_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 1604 { 1605 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1606 int basereg; 1607 int limitreg; 1608 1609 if ((win < 0) || (win > 2)) { 1610 #if defined DIAGNOSTIC 1611 printf("cardbus_io_open: window out of range %d\n", win); 1612 #endif 1613 return 0; 1614 } 1615 1616 basereg = win * 8 + 0x2c; 1617 limitreg = win * 8 + 0x30; 1618 1619 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1620 start, basereg, end, limitreg)); 1621 1622 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1623 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1624 return 1; 1625 } 1626 1627 /* 1628 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1629 */ 1630 static int 1631 pccbb_io_close(cardbus_chipset_tag_t ct, int win) 1632 { 1633 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1634 int basereg; 1635 int limitreg; 1636 1637 if ((win < 0) || (win > 2)) { 1638 #if defined DIAGNOSTIC 1639 printf("cardbus_io_close: window out of range %d\n", win); 1640 #endif 1641 return 0; 1642 } 1643 1644 basereg = win * 8 + 0x2c; 1645 limitreg = win * 8 + 0x30; 1646 1647 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1648 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1649 return 1; 1650 } 1651 1652 static int 1653 pccbb_mem_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 1654 { 1655 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1656 int basereg; 1657 int limitreg; 1658 1659 if ((win < 0) || (win > 2)) { 1660 #if defined DIAGNOSTIC 1661 printf("cardbus_mem_open: window out of range %d\n", win); 1662 #endif 1663 return 0; 1664 } 1665 1666 basereg = win * 8 + 0x1c; 1667 limitreg = win * 8 + 0x20; 1668 1669 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1670 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1671 return 1; 1672 } 1673 1674 static int 1675 pccbb_mem_close(cardbus_chipset_tag_t ct, int win) 1676 { 1677 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1678 int basereg; 1679 int limitreg; 1680 1681 if ((win < 0) || (win > 2)) { 1682 #if defined DIAGNOSTIC 1683 printf("cardbus_mem_close: window out of range %d\n", win); 1684 #endif 1685 return 0; 1686 } 1687 1688 basereg = win * 8 + 0x1c; 1689 limitreg = win * 8 + 0x20; 1690 1691 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1692 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1693 return 1; 1694 } 1695 #endif 1696 1697 /* 1698 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1699 * int irq, 1700 * int level, 1701 * int (* func)(void *), 1702 * void *arg) 1703 * 1704 * This function registers an interrupt handler at the bridge, in 1705 * order not to call the interrupt handlers of child devices when 1706 * a card-deletion interrupt occurs. 1707 * 1708 * The arguments irq and level are not used. 1709 */ 1710 static void * 1711 pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, int irq, int level, 1712 int (*func)(void *), void *arg) 1713 { 1714 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1715 1716 return pccbb_intr_establish(sc, irq, level, func, arg); 1717 } 1718 1719 1720 /* 1721 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1722 * void *ih) 1723 * 1724 * This function removes an interrupt handler pointed by ih. 1725 */ 1726 static void 1727 pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih) 1728 { 1729 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1730 1731 pccbb_intr_disestablish(sc, ih); 1732 } 1733 1734 1735 void 1736 pccbb_intr_route(struct pccbb_softc *sc) 1737 { 1738 pcireg_t bcr, cbctrl; 1739 1740 /* initialize bridge intr routing */ 1741 bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1742 bcr &= ~CB_BCR_INTR_IREQ_ENABLE; 1743 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr); 1744 1745 switch (sc->sc_chipset) { 1746 case CB_TI113X: 1747 cbctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1748 /* functional intr enabled */ 1749 cbctrl |= PCI113X_CBCTRL_PCI_INTR; 1750 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, cbctrl); 1751 break; 1752 default: 1753 break; 1754 } 1755 } 1756 1757 /* 1758 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1759 * int irq, 1760 * int level, 1761 * int (* func)(void *), 1762 * void *arg) 1763 * 1764 * This function registers an interrupt handler at the bridge, in 1765 * order not to call the interrupt handlers of child devices when 1766 * a card-deletion interrupt occurs. 1767 * 1768 * The arguments irq is not used because pccbb selects intr vector. 1769 */ 1770 static void * 1771 pccbb_intr_establish(struct pccbb_softc *sc, int irq, int level, 1772 int (*func)(void *), void *arg) 1773 { 1774 struct pccbb_intrhand_list *pil, *newpil; 1775 1776 DPRINTF(("pccbb_intr_establish start. %p\n", LIST_FIRST(&sc->sc_pil))); 1777 1778 if (LIST_EMPTY(&sc->sc_pil)) { 1779 pccbb_intr_route(sc); 1780 } 1781 1782 /* 1783 * Allocate a room for interrupt handler structure. 1784 */ 1785 if (NULL == (newpil = 1786 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1787 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1788 return NULL; 1789 } 1790 1791 newpil->pil_func = func; 1792 newpil->pil_arg = arg; 1793 newpil->pil_icookie = makeiplcookie(level); 1794 1795 if (LIST_EMPTY(&sc->sc_pil)) { 1796 LIST_INSERT_HEAD(&sc->sc_pil, newpil, pil_next); 1797 } else { 1798 for (pil = LIST_FIRST(&sc->sc_pil); 1799 LIST_NEXT(pil, pil_next) != NULL; 1800 pil = LIST_NEXT(pil, pil_next)); 1801 LIST_INSERT_AFTER(pil, newpil, pil_next); 1802 } 1803 1804 DPRINTF(("pccbb_intr_establish add pil. %p\n", 1805 LIST_FIRST(&sc->sc_pil))); 1806 1807 return newpil; 1808 } 1809 1810 /* 1811 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1812 * void *ih) 1813 * 1814 * This function removes an interrupt handler pointed by ih. ih 1815 * should be the value returned by cardbus_intr_establish() or 1816 * NULL. 1817 * 1818 * When ih is NULL, this function will do nothing. 1819 */ 1820 static void 1821 pccbb_intr_disestablish(struct pccbb_softc *sc, void *ih) 1822 { 1823 struct pccbb_intrhand_list *pil; 1824 pcireg_t reg; 1825 1826 DPRINTF(("pccbb_intr_disestablish start. %p\n", 1827 LIST_FIRST(&sc->sc_pil))); 1828 1829 if (ih == NULL) { 1830 /* intr handler is not set */ 1831 DPRINTF(("pccbb_intr_disestablish: no ih\n")); 1832 return; 1833 } 1834 1835 #ifdef DIAGNOSTIC 1836 for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1837 pil = LIST_NEXT(pil, pil_next)) { 1838 DPRINTF(("pccbb_intr_disestablish: pil %p\n", pil)); 1839 if (pil == ih) { 1840 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1841 break; 1842 } 1843 } 1844 if (pil == NULL) { 1845 panic("pccbb_intr_disestablish: %s cannot find pil %p", 1846 sc->sc_dev.dv_xname, ih); 1847 } 1848 #endif 1849 1850 pil = (struct pccbb_intrhand_list *)ih; 1851 LIST_REMOVE(pil, pil_next); 1852 free(pil, M_DEVBUF); 1853 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1854 1855 if (LIST_EMPTY(&sc->sc_pil)) { 1856 /* No interrupt handlers */ 1857 1858 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1859 1860 /* stop routing PCI intr */ 1861 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1862 reg |= CB_BCR_INTR_IREQ_ENABLE; 1863 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, reg); 1864 1865 switch (sc->sc_chipset) { 1866 case CB_TI113X: 1867 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1868 /* functional intr disabled */ 1869 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1870 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1871 break; 1872 default: 1873 break; 1874 } 1875 } 1876 } 1877 1878 #if defined SHOW_REGS 1879 static void 1880 cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, bus_space_tag_t memt, 1881 bus_space_handle_t memh) 1882 { 1883 int i; 1884 printf("PCI config regs:"); 1885 for (i = 0; i < 0x50; i += 4) { 1886 if (i % 16 == 0) 1887 printf("\n 0x%02x:", i); 1888 printf(" %08x", pci_conf_read(pc, tag, i)); 1889 } 1890 for (i = 0x80; i < 0xb0; i += 4) { 1891 if (i % 16 == 0) 1892 printf("\n 0x%02x:", i); 1893 printf(" %08x", pci_conf_read(pc, tag, i)); 1894 } 1895 1896 if (memh == 0) { 1897 printf("\n"); 1898 return; 1899 } 1900 1901 printf("\nsocket regs:"); 1902 for (i = 0; i <= 0x10; i += 0x04) 1903 printf(" %08x", bus_space_read_4(memt, memh, i)); 1904 printf("\nExCA regs:"); 1905 for (i = 0; i < 0x08; ++i) 1906 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1907 printf("\n"); 1908 return; 1909 } 1910 #endif 1911 1912 /* 1913 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1914 * int busno, int function) 1915 * This is the function to make a tag to access config space of 1916 * a CardBus Card. It works same as pci_conf_read. 1917 */ 1918 static cardbustag_t 1919 pccbb_make_tag(cardbus_chipset_tag_t cc, int busno, int function) 1920 { 1921 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1922 1923 return pci_make_tag(sc->sc_pc, busno, 0, function); 1924 } 1925 1926 static void 1927 pccbb_free_tag(cardbus_chipset_tag_t cc, cardbustag_t tag) 1928 { 1929 } 1930 1931 /* 1932 * pccbb_conf_read 1933 * 1934 * This is the function to read the config space of a CardBus card. 1935 * It works the same as pci_conf_read(9). 1936 */ 1937 static cardbusreg_t 1938 pccbb_conf_read(cardbus_chipset_tag_t cc, cardbustag_t tag, int offset) 1939 { 1940 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1941 1942 return pci_conf_read(sc->sc_pc, tag, offset); 1943 } 1944 1945 /* 1946 * pccbb_conf_write 1947 * 1948 * This is the function to write the config space of a CardBus 1949 * card. It works the same as pci_conf_write(9). 1950 */ 1951 static void 1952 pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, int reg, 1953 cardbusreg_t val) 1954 { 1955 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1956 1957 pci_conf_write(sc->sc_pc, tag, reg, val); 1958 } 1959 1960 #if 0 1961 STATIC int 1962 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1963 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 1964 int speed, int flags, 1965 bus_space_handle_t * iohp) 1966 #endif 1967 /* 1968 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1969 * bus_addr_t start, bus_size_t size, 1970 * bus_size_t align, 1971 * struct pcmcia_io_handle *pcihp 1972 * 1973 * This function only allocates I/O region for pccard. This function 1974 * never maps the allocated region to pccard I/O area. 1975 * 1976 * XXX: The interface of this function is not very good, I believe. 1977 */ 1978 STATIC int 1979 pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, 1980 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 1981 { 1982 struct pcic_handle *ph = (struct pcic_handle *)pch; 1983 bus_addr_t ioaddr; 1984 int flags = 0; 1985 bus_space_tag_t iot; 1986 bus_space_handle_t ioh; 1987 bus_addr_t mask; 1988 #if rbus 1989 rbus_tag_t rb; 1990 #endif 1991 if (align == 0) { 1992 align = size; /* XXX: funny??? */ 1993 } 1994 1995 if (start != 0) { 1996 /* XXX: assume all card decode lower 10 bits by its hardware */ 1997 mask = 0x3ff; 1998 /* enforce to use only masked address */ 1999 start &= mask; 2000 } else { 2001 /* 2002 * calculate mask: 2003 * 1. get the most significant bit of size (call it msb). 2004 * 2. compare msb with the value of size. 2005 * 3. if size is larger, shift msb left once. 2006 * 4. obtain mask value to decrement msb. 2007 */ 2008 bus_size_t size_tmp = size; 2009 int shifts = 0; 2010 2011 mask = 1; 2012 while (size_tmp) { 2013 ++shifts; 2014 size_tmp >>= 1; 2015 } 2016 mask = (1 << shifts); 2017 if (mask < size) { 2018 mask <<= 1; 2019 } 2020 --mask; 2021 } 2022 2023 /* 2024 * Allocate some arbitrary I/O space. 2025 */ 2026 2027 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 2028 2029 #if rbus 2030 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 2031 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 2032 return 1; 2033 } 2034 DPRINTF(("pccbb_pcmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2035 (u_long) ioaddr, (u_long) size)); 2036 #else 2037 if (start) { 2038 ioaddr = start; 2039 if (bus_space_map(iot, start, size, 0, &ioh)) { 2040 return 1; 2041 } 2042 DPRINTF(("pccbb_pcmcia_io_alloc map port 0x%lx+0x%lx\n", 2043 (u_long) ioaddr, (u_long) size)); 2044 } else { 2045 flags |= PCMCIA_IO_ALLOCATED; 2046 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 2047 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 2048 size, align, 0, 0, &ioaddr, &ioh)) { 2049 /* No room be able to be get. */ 2050 return 1; 2051 } 2052 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2053 (u_long) ioaddr, (u_long) size)); 2054 } 2055 #endif 2056 2057 pcihp->iot = iot; 2058 pcihp->ioh = ioh; 2059 pcihp->addr = ioaddr; 2060 pcihp->size = size; 2061 pcihp->flags = flags; 2062 2063 return 0; 2064 } 2065 2066 /* 2067 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2068 * struct pcmcia_io_handle *pcihp) 2069 * 2070 * This function only frees I/O region for pccard. 2071 * 2072 * XXX: The interface of this function is not very good, I believe. 2073 */ 2074 void 2075 pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2076 struct pcmcia_io_handle *pcihp) 2077 { 2078 #if !rbus 2079 bus_space_tag_t iot = pcihp->iot; 2080 #endif 2081 bus_space_handle_t ioh = pcihp->ioh; 2082 bus_size_t size = pcihp->size; 2083 2084 #if rbus 2085 struct pccbb_softc *sc = 2086 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 2087 rbus_tag_t rb = sc->sc_rbus_iot; 2088 2089 rbus_space_free(rb, ioh, size, NULL); 2090 #else 2091 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 2092 bus_space_free(iot, ioh, size); 2093 else 2094 bus_space_unmap(iot, ioh, size); 2095 #endif 2096 } 2097 2098 /* 2099 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 2100 * bus_addr_t offset, bus_size_t size, 2101 * struct pcmcia_io_handle *pcihp, 2102 * int *windowp) 2103 * 2104 * This function maps the allocated I/O region to pccard. This function 2105 * never allocates any I/O region for pccard I/O area. I don't 2106 * understand why the original authors of pcmciabus separated alloc and 2107 * map. I believe the two must be unite. 2108 * 2109 * XXX: no wait timing control? 2110 */ 2111 int 2112 pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, bus_addr_t offset, 2113 bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp) 2114 { 2115 struct pcic_handle *ph = (struct pcic_handle *)pch; 2116 bus_addr_t ioaddr = pcihp->addr + offset; 2117 int i, win; 2118 #if defined CBB_DEBUG 2119 static const char *width_names[] = { "dynamic", "io8", "io16" }; 2120 #endif 2121 2122 /* Sanity check I/O handle. */ 2123 2124 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 2125 panic("pccbb_pcmcia_io_map iot is bogus"); 2126 } 2127 2128 /* XXX Sanity check offset/size. */ 2129 2130 win = -1; 2131 for (i = 0; i < PCIC_IO_WINS; i++) { 2132 if ((ph->ioalloc & (1 << i)) == 0) { 2133 win = i; 2134 ph->ioalloc |= (1 << i); 2135 break; 2136 } 2137 } 2138 2139 if (win == -1) { 2140 return 1; 2141 } 2142 2143 *windowp = win; 2144 2145 /* XXX this is pretty gross */ 2146 2147 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2148 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2149 2150 /* XXX wtf is this doing here? */ 2151 2152 #if 0 2153 printf(" port 0x%lx", (u_long) ioaddr); 2154 if (size > 1) { 2155 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2156 } 2157 #endif 2158 2159 ph->io[win].addr = ioaddr; 2160 ph->io[win].size = size; 2161 ph->io[win].width = width; 2162 2163 /* actual dirty register-value changing in the function below. */ 2164 pccbb_pcmcia_do_io_map(ph, win); 2165 2166 return 0; 2167 } 2168 2169 /* 2170 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2171 * 2172 * This function changes register-value to map I/O region for pccard. 2173 */ 2174 static void 2175 pccbb_pcmcia_do_io_map(struct pcic_handle *ph, int win) 2176 { 2177 static u_int8_t pcic_iowidth[3] = { 2178 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2179 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2180 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2181 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2182 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2183 }; 2184 2185 #define PCIC_SIA_START_LOW 0 2186 #define PCIC_SIA_START_HIGH 1 2187 #define PCIC_SIA_STOP_LOW 2 2188 #define PCIC_SIA_STOP_HIGH 3 2189 2190 int regbase_win = 0x8 + win * 0x04; 2191 u_int8_t ioctl, enable; 2192 2193 DPRINTF(("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx " 2194 "width %d\n", win, (unsigned long)ph->io[win].addr, 2195 (unsigned long)ph->io[win].size, ph->io[win].width * 8)); 2196 2197 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2198 ph->io[win].addr & 0xff); 2199 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2200 (ph->io[win].addr >> 8) & 0xff); 2201 2202 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2203 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2204 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2205 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2206 2207 ioctl = Pcic_read(ph, PCIC_IOCTL); 2208 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2209 switch (win) { 2210 case 0: 2211 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2212 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2213 PCIC_IOCTL_IO0_DATASIZE_MASK); 2214 ioctl |= pcic_iowidth[ph->io[win].width]; 2215 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2216 break; 2217 case 1: 2218 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2219 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2220 PCIC_IOCTL_IO1_DATASIZE_MASK); 2221 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2222 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2223 break; 2224 } 2225 Pcic_write(ph, PCIC_IOCTL, ioctl); 2226 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2227 #if defined(CBB_DEBUG) 2228 { 2229 u_int8_t start_low = 2230 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2231 u_int8_t start_high = 2232 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2233 u_int8_t stop_low = 2234 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2235 u_int8_t stop_high = 2236 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2237 printf("pccbb_pcmcia_do_io_map start %02x %02x, " 2238 "stop %02x %02x, ioctl %02x enable %02x\n", 2239 start_low, start_high, stop_low, stop_high, ioctl, enable); 2240 } 2241 #endif 2242 } 2243 2244 /* 2245 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2246 * 2247 * This function unmaps I/O region. No return value. 2248 */ 2249 STATIC void 2250 pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t pch, int win) 2251 { 2252 struct pcic_handle *ph = (struct pcic_handle *)pch; 2253 int reg; 2254 2255 if (win >= PCIC_IO_WINS || win < 0) { 2256 panic("pccbb_pcmcia_io_unmap: window out of range"); 2257 } 2258 2259 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2260 switch (win) { 2261 case 0: 2262 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2263 break; 2264 case 1: 2265 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2266 break; 2267 } 2268 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2269 2270 ph->ioalloc &= ~(1 << win); 2271 } 2272 2273 static int 2274 pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 2275 { 2276 u_int8_t stat; 2277 int i; 2278 2279 /* wait an initial 10ms for quick cards */ 2280 stat = Pcic_read(ph, PCIC_IF_STATUS); 2281 if (stat & PCIC_IF_STATUS_READY) 2282 return (0); 2283 pccbb_pcmcia_delay(ph, 10, "pccwr0"); 2284 for (i = 0; i < 50; i++) { 2285 stat = Pcic_read(ph, PCIC_IF_STATUS); 2286 if (stat & PCIC_IF_STATUS_READY) 2287 return (0); 2288 if ((stat & PCIC_IF_STATUS_CARDDETECT_MASK) != 2289 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2290 return (ENXIO); 2291 /* wait .1s (100ms) each iteration now */ 2292 pccbb_pcmcia_delay(ph, 100, "pccwr1"); 2293 } 2294 2295 printf("pccbb_pcmcia_wait_ready: ready never happened, status=%02x\n", stat); 2296 return (EWOULDBLOCK); 2297 } 2298 2299 /* 2300 * Perform long (msec order) delay. timo is in milliseconds. 2301 */ 2302 static void 2303 pccbb_pcmcia_delay(struct pcic_handle *ph, int timo, const char *wmesg) 2304 { 2305 #ifdef DIAGNOSTIC 2306 if (timo <= 0) 2307 panic("pccbb_pcmcia_delay: called with timeout %d", timo); 2308 if (!curlwp) 2309 panic("pccbb_pcmcia_delay: called in interrupt context"); 2310 #if 0 2311 if (!ph->event_thread) 2312 panic("pccbb_pcmcia_delay: no event thread"); 2313 #endif 2314 #endif 2315 DPRINTF(("pccbb_pcmcia_delay: \"%s\" %p, sleep %d ms\n", 2316 wmesg, ph->event_thread, timo)); 2317 tsleep(pccbb_pcmcia_delay, PWAIT, wmesg, roundup(timo * hz, 1000) / 1000); 2318 } 2319 2320 /* 2321 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2322 * 2323 * This function enables the card. All information is stored in 2324 * the first argument, pcmcia_chipset_handle_t. 2325 */ 2326 STATIC void 2327 pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2328 { 2329 struct pcic_handle *ph = (struct pcic_handle *)pch; 2330 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2331 pcireg_t spsr; 2332 int voltage; 2333 int win; 2334 u_int8_t power, intr; 2335 #ifdef DIAGNOSTIC 2336 int reg; 2337 #endif 2338 2339 /* this bit is mostly stolen from pcic_attach_card */ 2340 2341 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2342 2343 /* get card Vcc info */ 2344 spsr = 2345 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2346 CB_SOCKET_STAT); 2347 if (spsr & CB_SOCKET_STAT_5VCARD) { 2348 DPRINTF(("5V card\n")); 2349 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2350 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2351 DPRINTF(("3V card\n")); 2352 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2353 } else { 2354 DPRINTF(("?V card, 0x%x\n", spsr)); /* XXX */ 2355 return; 2356 } 2357 2358 /* disable interrupts; assert RESET */ 2359 intr = Pcic_read(ph, PCIC_INTR); 2360 intr &= PCIC_INTR_ENABLE; 2361 Pcic_write(ph, PCIC_INTR, intr); 2362 2363 /* zero out the address windows */ 2364 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2365 2366 /* power down the socket to reset it, clear the card reset pin */ 2367 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2368 2369 /* power off; assert output enable bit */ 2370 power = PCIC_PWRCTL_OE; 2371 Pcic_write(ph, PCIC_PWRCTL, power); 2372 2373 /* power up the socket */ 2374 if (pccbb_power(sc, voltage) == 0) 2375 return; 2376 2377 /* 2378 * Table 4-18 and figure 4-6 of the PC Card specifiction say: 2379 * Vcc Rising Time (Tpr) = 100ms (handled in pccbb_power() above) 2380 * RESET Width (Th (Hi-z RESET)) = 1ms 2381 * RESET Width (Tw (RESET)) = 10us 2382 * 2383 * some machines require some more time to be settled 2384 * for example old toshiba topic bridges! 2385 * (100ms is added here). 2386 */ 2387 pccbb_pcmcia_delay(ph, 200 + 1, "pccen1"); 2388 2389 /* negate RESET */ 2390 intr |= PCIC_INTR_RESET; 2391 Pcic_write(ph, PCIC_INTR, intr); 2392 2393 /* 2394 * RESET Setup Time (Tsu (RESET)) = 20ms 2395 */ 2396 pccbb_pcmcia_delay(ph, 20, "pccen2"); 2397 2398 #ifdef DIAGNOSTIC 2399 reg = Pcic_read(ph, PCIC_IF_STATUS); 2400 if ((reg & PCIC_IF_STATUS_POWERACTIVE) == 0) 2401 printf("pccbb_pcmcia_socket_enable: no power, status=%x\n", reg); 2402 #endif 2403 2404 /* wait for the chip to finish initializing */ 2405 if (pccbb_pcmcia_wait_ready(ph)) { 2406 #ifdef DIAGNOSTIC 2407 printf("pccbb_pcmcia_socket_enable: never became ready\n"); 2408 #endif 2409 /* XXX return a failure status?? */ 2410 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2411 Pcic_write(ph, PCIC_PWRCTL, 0); 2412 return; 2413 } 2414 2415 /* reinstall all the memory and io mappings */ 2416 for (win = 0; win < PCIC_MEM_WINS; ++win) 2417 if (ph->memalloc & (1 << win)) 2418 pccbb_pcmcia_do_mem_map(ph, win); 2419 for (win = 0; win < PCIC_IO_WINS; ++win) 2420 if (ph->ioalloc & (1 << win)) 2421 pccbb_pcmcia_do_io_map(ph, win); 2422 } 2423 2424 /* 2425 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2426 * 2427 * This function disables the card. All information is stored in 2428 * the first argument, pcmcia_chipset_handle_t. 2429 */ 2430 STATIC void 2431 pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t pch) 2432 { 2433 struct pcic_handle *ph = (struct pcic_handle *)pch; 2434 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2435 u_int8_t intr; 2436 2437 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2438 2439 /* disable interrupts; assert RESET */ 2440 intr = Pcic_read(ph, PCIC_INTR); 2441 intr &= PCIC_INTR_ENABLE; 2442 Pcic_write(ph, PCIC_INTR, intr); 2443 2444 /* zero out the address windows */ 2445 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2446 2447 /* power down the socket to reset it, clear the card reset pin */ 2448 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2449 2450 /* disable socket: negate output enable bit and power off */ 2451 Pcic_write(ph, PCIC_PWRCTL, 0); 2452 2453 /* 2454 * Vcc Falling Time (Tpf) = 300ms 2455 */ 2456 pccbb_pcmcia_delay(ph, 300, "pccwr1"); 2457 } 2458 2459 STATIC void 2460 pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t pch, int type) 2461 { 2462 struct pcic_handle *ph = (struct pcic_handle *)pch; 2463 u_int8_t intr; 2464 2465 /* set the card type */ 2466 2467 intr = Pcic_read(ph, PCIC_INTR); 2468 intr &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_CARDTYPE_MASK); 2469 if (type == PCMCIA_IFTYPE_IO) 2470 intr |= PCIC_INTR_CARDTYPE_IO; 2471 else 2472 intr |= PCIC_INTR_CARDTYPE_MEM; 2473 Pcic_write(ph, PCIC_INTR, intr); 2474 2475 DPRINTF(("%s: pccbb_pcmcia_socket_settype %02x type %s %02x\n", 2476 ph->ph_parent->dv_xname, ph->sock, 2477 ((type == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2478 } 2479 2480 /* 2481 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2482 * 2483 * This function detects whether a card is in the slot or not. 2484 * If a card is inserted, return 1. Otherwise, return 0. 2485 */ 2486 STATIC int 2487 pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch) 2488 { 2489 struct pcic_handle *ph = (struct pcic_handle *)pch; 2490 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2491 2492 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2493 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2494 } 2495 2496 #if 0 2497 STATIC int 2498 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2499 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2500 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2501 #endif 2502 /* 2503 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2504 * bus_size_t size, 2505 * struct pcmcia_mem_handle *pcmhp) 2506 * 2507 * This function only allocates memory region for pccard. This 2508 * function never maps the allocated region to pccard memory area. 2509 * 2510 * XXX: Why the argument of start address is not in? 2511 */ 2512 STATIC int 2513 pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 2514 struct pcmcia_mem_handle *pcmhp) 2515 { 2516 struct pcic_handle *ph = (struct pcic_handle *)pch; 2517 bus_space_handle_t memh; 2518 bus_addr_t addr; 2519 bus_size_t sizepg; 2520 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2521 #if rbus 2522 rbus_tag_t rb; 2523 #endif 2524 2525 /* Check that the card is still there. */ 2526 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2527 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2528 return 1; 2529 2530 /* out of sc->memh, allocate as many pages as necessary */ 2531 2532 /* convert size to PCIC pages */ 2533 /* 2534 * This is not enough; when the requested region is on the page 2535 * boundaries, this may calculate wrong result. 2536 */ 2537 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2538 #if 0 2539 if (sizepg > PCIC_MAX_MEM_PAGES) { 2540 return 1; 2541 } 2542 #endif 2543 2544 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2545 return 1; 2546 } 2547 2548 addr = 0; /* XXX gcc -Wuninitialized */ 2549 2550 #if rbus 2551 rb = sc->sc_rbus_memt; 2552 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2553 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2554 &addr, &memh)) { 2555 return 1; 2556 } 2557 #else 2558 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2559 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2560 0, /* boundary */ 2561 0, /* flags */ 2562 &addr, &memh)) { 2563 return 1; 2564 } 2565 #endif 2566 2567 DPRINTF(("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, " 2568 "realsize 0x%lx\n", (unsigned long)addr, (unsigned long)size, 2569 (unsigned long)sizepg * PCIC_MEM_PAGESIZE)); 2570 2571 pcmhp->memt = sc->sc_memt; 2572 pcmhp->memh = memh; 2573 pcmhp->addr = addr; 2574 pcmhp->size = size; 2575 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2576 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2577 pcmhp->mhandle = 0; 2578 /* No offset??? Funny. */ 2579 2580 return 0; 2581 } 2582 2583 /* 2584 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2585 * struct pcmcia_mem_handle *pcmhp) 2586 * 2587 * This function release the memory space allocated by the function 2588 * pccbb_pcmcia_mem_alloc(). 2589 */ 2590 STATIC void 2591 pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2592 struct pcmcia_mem_handle *pcmhp) 2593 { 2594 #if rbus 2595 struct pcic_handle *ph = (struct pcic_handle *)pch; 2596 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2597 2598 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2599 #else 2600 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2601 #endif 2602 } 2603 2604 /* 2605 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2606 * 2607 * This function release the memory space allocated by the function 2608 * pccbb_pcmcia_mem_alloc(). 2609 */ 2610 STATIC void 2611 pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2612 { 2613 int regbase_win; 2614 bus_addr_t phys_addr; 2615 bus_addr_t phys_end; 2616 2617 #define PCIC_SMM_START_LOW 0 2618 #define PCIC_SMM_START_HIGH 1 2619 #define PCIC_SMM_STOP_LOW 2 2620 #define PCIC_SMM_STOP_HIGH 3 2621 #define PCIC_CMA_LOW 4 2622 #define PCIC_CMA_HIGH 5 2623 2624 u_int8_t start_low, start_high = 0; 2625 u_int8_t stop_low, stop_high; 2626 u_int8_t off_low, off_high; 2627 u_int8_t mem_window; 2628 int reg; 2629 2630 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2631 int mem8 = 2632 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2633 || (kind == PCMCIA_MEM_ATTR); 2634 2635 regbase_win = 0x10 + win * 0x08; 2636 2637 phys_addr = ph->mem[win].addr; 2638 phys_end = phys_addr + ph->mem[win].size; 2639 2640 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2641 (unsigned long)phys_addr, (unsigned long)phys_end, 2642 (unsigned long)ph->mem[win].offset)); 2643 2644 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2645 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2646 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2647 2648 /* bit 19:12 */ 2649 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2650 /* bit 23:20 and bit 7 on */ 2651 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2652 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2653 /* bit 31:24, for 32-bit address */ 2654 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2655 2656 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2657 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2658 2659 if (((struct pccbb_softc *)ph-> 2660 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2661 Pcic_write(ph, 0x40 + win, mem_window); 2662 } 2663 2664 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2665 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2666 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2667 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2668 2669 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2670 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2671 2672 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2673 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2674 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2675 | ((kind == PCMCIA_MEM_ATTR) ? 2676 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2677 2678 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2679 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2680 2681 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2682 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2683 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2684 2685 #if defined(CBB_DEBUG) 2686 { 2687 int r1, r2, r3, r4, r5, r6, r7 = 0; 2688 2689 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2690 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2691 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2692 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2693 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2694 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2695 if (((struct pccbb_softc *)(ph-> 2696 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2697 r7 = Pcic_read(ph, 0x40 + win); 2698 } 2699 2700 printf("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2701 "%02x%02x", win, r1, r2, r3, r4, r5, r6); 2702 if (((struct pccbb_softc *)(ph-> 2703 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2704 printf(" %02x", r7); 2705 } 2706 printf("\n"); 2707 } 2708 #endif 2709 } 2710 2711 /* 2712 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2713 * bus_addr_t card_addr, bus_size_t size, 2714 * struct pcmcia_mem_handle *pcmhp, 2715 * bus_addr_t *offsetp, int *windowp) 2716 * 2717 * This function maps memory space allocated by the function 2718 * pccbb_pcmcia_mem_alloc(). 2719 */ 2720 STATIC int 2721 pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2722 bus_addr_t card_addr, bus_size_t size, struct pcmcia_mem_handle *pcmhp, 2723 bus_addr_t *offsetp, int *windowp) 2724 { 2725 struct pcic_handle *ph = (struct pcic_handle *)pch; 2726 bus_addr_t busaddr; 2727 long card_offset; 2728 int win; 2729 2730 /* Check that the card is still there. */ 2731 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2732 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2733 return 1; 2734 2735 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2736 if ((ph->memalloc & (1 << win)) == 0) { 2737 ph->memalloc |= (1 << win); 2738 break; 2739 } 2740 } 2741 2742 if (win == PCIC_MEM_WINS) { 2743 return 1; 2744 } 2745 2746 *windowp = win; 2747 2748 /* XXX this is pretty gross */ 2749 2750 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2751 panic("pccbb_pcmcia_mem_map memt is bogus"); 2752 } 2753 2754 busaddr = pcmhp->addr; 2755 2756 /* 2757 * compute the address offset to the pcmcia address space for the 2758 * pcic. this is intentionally signed. The masks and shifts below 2759 * will cause TRT to happen in the pcic registers. Deal with making 2760 * sure the address is aligned, and return the alignment offset. 2761 */ 2762 2763 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2764 card_addr -= *offsetp; 2765 2766 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2767 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2768 (u_long) card_addr)); 2769 2770 /* 2771 * include the offset in the size, and decrement size by one, since 2772 * the hw wants start/stop 2773 */ 2774 size += *offsetp - 1; 2775 2776 card_offset = (((long)card_addr) - ((long)busaddr)); 2777 2778 ph->mem[win].addr = busaddr; 2779 ph->mem[win].size = size; 2780 ph->mem[win].offset = card_offset; 2781 ph->mem[win].kind = kind; 2782 2783 pccbb_pcmcia_do_mem_map(ph, win); 2784 2785 return 0; 2786 } 2787 2788 /* 2789 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2790 * int window) 2791 * 2792 * This function unmaps memory space which mapped by the function 2793 * pccbb_pcmcia_mem_map(). 2794 */ 2795 STATIC void 2796 pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, int window) 2797 { 2798 struct pcic_handle *ph = (struct pcic_handle *)pch; 2799 int reg; 2800 2801 if (window >= PCIC_MEM_WINS) { 2802 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2803 } 2804 2805 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2806 reg &= ~(1 << window); 2807 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2808 2809 ph->memalloc &= ~(1 << window); 2810 } 2811 2812 #if defined PCCBB_PCMCIA_POLL 2813 struct pccbb_poll_str { 2814 void *arg; 2815 int (*func)(void *); 2816 int level; 2817 struct pcic_handle *ph; 2818 int count; 2819 int num; 2820 struct callout poll_ch; 2821 }; 2822 2823 static struct pccbb_poll_str pccbb_poll[10]; 2824 static int pccbb_poll_n = 0; 2825 2826 static void pccbb_pcmcia_poll(void *arg); 2827 2828 static void 2829 pccbb_pcmcia_poll(void *arg) 2830 { 2831 struct pccbb_poll_str *poll = arg; 2832 struct pcic_handle *ph = poll->ph; 2833 struct pccbb_softc *sc = ph->sc; 2834 int s; 2835 u_int32_t spsr; /* socket present-state reg */ 2836 2837 callout_reset(&poll->poll_ch, hz * 2, pccbb_pcmcia_poll, arg); 2838 switch (poll->level) { 2839 case IPL_NET: 2840 s = splnet(); 2841 break; 2842 case IPL_BIO: 2843 s = splbio(); 2844 break; 2845 case IPL_TTY: /* fallthrough */ 2846 default: 2847 s = spltty(); 2848 break; 2849 } 2850 2851 spsr = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2852 CB_SOCKET_STAT); 2853 2854 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2855 if (!(spsr & 0x40)) /* CINT low */ 2856 #else 2857 if (1) 2858 #endif 2859 { 2860 if ((*poll->func) (poll->arg) > 0) { 2861 ++poll->count; 2862 /* printf("intr: reported from poller, 0x%x\n", spsr); */ 2863 #if defined LEVEL2 2864 } else { 2865 printf("intr: miss! 0x%x\n", spsr); 2866 #endif 2867 } 2868 } 2869 splx(s); 2870 } 2871 #endif /* defined CB_PCMCIA_POLL */ 2872 2873 /* 2874 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2875 * struct pcmcia_function *pf, 2876 * int ipl, 2877 * int (*func)(void *), 2878 * void *arg); 2879 * 2880 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2881 */ 2882 STATIC void * 2883 pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2884 struct pcmcia_function *pf, int ipl, int (*func)(void *), void *arg) 2885 { 2886 struct pcic_handle *ph = (struct pcic_handle *)pch; 2887 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2888 2889 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2890 /* what should I do? */ 2891 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2892 DPRINTF(("%s does not provide edge nor pulse " 2893 "interrupt\n", sc->sc_dev.dv_xname)); 2894 return NULL; 2895 } 2896 /* 2897 * XXX Noooooo! The interrupt flag must set properly!! 2898 * dumb pcmcia driver!! 2899 */ 2900 } 2901 2902 return pccbb_intr_establish(sc, 0, ipl, func, arg); 2903 } 2904 2905 /* 2906 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2907 * void *ih) 2908 * 2909 * This function disables PC-Card interrupt. 2910 */ 2911 STATIC void 2912 pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 2913 { 2914 struct pcic_handle *ph = (struct pcic_handle *)pch; 2915 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2916 2917 pccbb_intr_disestablish(sc, ih); 2918 } 2919 2920 #if rbus 2921 /* 2922 * static int 2923 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2924 * bus_addr_t addr, bus_size_t size, 2925 * bus_addr_t mask, bus_size_t align, 2926 * int flags, bus_addr_t *addrp; 2927 * bus_space_handle_t *bshp) 2928 * 2929 * This function allocates a portion of memory or io space for 2930 * clients. This function is called from CardBus card drivers. 2931 */ 2932 static int 2933 pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2934 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 2935 int flags, bus_addr_t *addrp, bus_space_handle_t *bshp) 2936 { 2937 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2938 2939 DPRINTF(("pccbb_rbus_cb_space_alloc: addr 0x%lx, size 0x%lx, " 2940 "mask 0x%lx, align 0x%lx\n", (unsigned long)addr, 2941 (unsigned long)size, (unsigned long)mask, (unsigned long)align)); 2942 2943 if (align == 0) { 2944 align = size; 2945 } 2946 2947 if (rb->rb_bt == sc->sc_memt) { 2948 if (align < 16) { 2949 return 1; 2950 } 2951 /* 2952 * XXX: align more than 0x1000 to avoid overwrapping 2953 * memory windows for two or more devices. 0x1000 2954 * means memory window's granularity. 2955 * 2956 * Two or more devices should be able to share same 2957 * memory window region. However, overrapping memory 2958 * window is not good because some devices, such as 2959 * 3Com 3C575[BC], have a broken address decoder and 2960 * intrude other's memory region. 2961 */ 2962 if (align < 0x1000) { 2963 align = 0x1000; 2964 } 2965 } else if (rb->rb_bt == sc->sc_iot) { 2966 if (align < 4) { 2967 return 1; 2968 } 2969 /* XXX: hack for avoiding ISA image */ 2970 if (mask < 0x0100) { 2971 mask = 0x3ff; 2972 addr = 0x300; 2973 } 2974 2975 } else { 2976 DPRINTF(("pccbb_rbus_cb_space_alloc: Bus space tag 0x%lx is " 2977 "NOT used. io: 0x%lx, mem: 0x%lx\n", 2978 (unsigned long)rb->rb_bt, (unsigned long)sc->sc_iot, 2979 (unsigned long)sc->sc_memt)); 2980 return 1; 2981 /* XXX: panic here? */ 2982 } 2983 2984 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 2985 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 2986 return 1; 2987 } 2988 2989 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 2990 2991 return 0; 2992 } 2993 2994 /* 2995 * static int 2996 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 2997 * bus_space_handle_t *bshp, bus_size_t size); 2998 * 2999 * This function is called from CardBus card drivers. 3000 */ 3001 static int 3002 pccbb_rbus_cb_space_free(cardbus_chipset_tag_t ct, rbus_tag_t rb, 3003 bus_space_handle_t bsh, bus_size_t size) 3004 { 3005 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 3006 bus_space_tag_t bt = rb->rb_bt; 3007 3008 pccbb_close_win(sc, bt, bsh, size); 3009 3010 if (bt == sc->sc_memt) { 3011 } else if (bt == sc->sc_iot) { 3012 } else { 3013 return 1; 3014 /* XXX: panic here? */ 3015 } 3016 3017 return rbus_space_free(rb, bsh, size, NULL); 3018 } 3019 #endif /* rbus */ 3020 3021 #if rbus 3022 3023 static int 3024 pccbb_open_win(struct pccbb_softc *sc, bus_space_tag_t bst, bus_addr_t addr, 3025 bus_size_t size, bus_space_handle_t bsh, int flags) 3026 { 3027 struct pccbb_win_chain_head *head; 3028 bus_addr_t align; 3029 3030 head = &sc->sc_iowindow; 3031 align = 0x04; 3032 if (sc->sc_memt == bst) { 3033 head = &sc->sc_memwindow; 3034 align = 0x1000; 3035 DPRINTF(("using memory window, 0x%lx 0x%lx 0x%lx\n\n", 3036 (unsigned long)sc->sc_iot, (unsigned long)sc->sc_memt, 3037 (unsigned long)bst)); 3038 } 3039 3040 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 3041 printf("%s: pccbb_open_win: %s winlist insert failed\n", 3042 sc->sc_dev.dv_xname, 3043 (head == &sc->sc_memwindow) ? "mem" : "io"); 3044 } 3045 pccbb_winset(align, sc, bst); 3046 3047 return 0; 3048 } 3049 3050 static int 3051 pccbb_close_win(struct pccbb_softc *sc, bus_space_tag_t bst, 3052 bus_space_handle_t bsh, bus_size_t size) 3053 { 3054 struct pccbb_win_chain_head *head; 3055 bus_addr_t align; 3056 3057 head = &sc->sc_iowindow; 3058 align = 0x04; 3059 if (sc->sc_memt == bst) { 3060 head = &sc->sc_memwindow; 3061 align = 0x1000; 3062 } 3063 3064 if (pccbb_winlist_delete(head, bsh, size)) { 3065 printf("%s: pccbb_close_win: %s winlist delete failed\n", 3066 sc->sc_dev.dv_xname, 3067 (head == &sc->sc_memwindow) ? "mem" : "io"); 3068 } 3069 pccbb_winset(align, sc, bst); 3070 3071 return 0; 3072 } 3073 3074 static int 3075 pccbb_winlist_insert(struct pccbb_win_chain_head *head, bus_addr_t start, 3076 bus_size_t size, bus_space_handle_t bsh, int flags) 3077 { 3078 struct pccbb_win_chain *chainp, *elem; 3079 3080 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 3081 M_NOWAIT)) == NULL) 3082 return (1); /* fail */ 3083 3084 elem->wc_start = start; 3085 elem->wc_end = start + (size - 1); 3086 elem->wc_handle = bsh; 3087 elem->wc_flags = flags; 3088 3089 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3090 chainp = TAILQ_NEXT(chainp, wc_list)) { 3091 if (chainp->wc_end < start) 3092 continue; 3093 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 3094 return (0); 3095 } 3096 3097 TAILQ_INSERT_TAIL(head, elem, wc_list); 3098 return (0); 3099 } 3100 3101 static int 3102 pccbb_winlist_delete(struct pccbb_win_chain_head *head, bus_space_handle_t bsh, 3103 bus_size_t size) 3104 { 3105 struct pccbb_win_chain *chainp; 3106 3107 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3108 chainp = TAILQ_NEXT(chainp, wc_list)) { 3109 if (memcmp(&chainp->wc_handle, &bsh, sizeof(bsh))) 3110 continue; 3111 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 3112 printf("pccbb_winlist_delete: window 0x%lx size " 3113 "inconsistent: 0x%lx, 0x%lx\n", 3114 (unsigned long)chainp->wc_start, 3115 (unsigned long)(chainp->wc_end - chainp->wc_start), 3116 (unsigned long)(size - 1)); 3117 return 1; 3118 } 3119 3120 TAILQ_REMOVE(head, chainp, wc_list); 3121 free(chainp, M_DEVBUF); 3122 3123 return 0; 3124 } 3125 3126 return 1; /* fail: no candidate to remove */ 3127 } 3128 3129 static void 3130 pccbb_winset(bus_addr_t align, struct pccbb_softc *sc, bus_space_tag_t bst) 3131 { 3132 pci_chipset_tag_t pc; 3133 pcitag_t tag; 3134 bus_addr_t mask = ~(align - 1); 3135 struct { 3136 cardbusreg_t win_start; 3137 cardbusreg_t win_limit; 3138 int win_flags; 3139 } win[2]; 3140 struct pccbb_win_chain *chainp; 3141 int offs; 3142 3143 win[0].win_start = win[1].win_start = 0xffffffff; 3144 win[0].win_limit = win[1].win_limit = 0; 3145 win[0].win_flags = win[1].win_flags = 0; 3146 3147 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3148 offs = 0x2c; 3149 if (sc->sc_memt == bst) { 3150 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3151 offs = 0x1c; 3152 } 3153 3154 if (chainp != NULL) { 3155 win[0].win_start = chainp->wc_start & mask; 3156 win[0].win_limit = chainp->wc_end & mask; 3157 win[0].win_flags = chainp->wc_flags; 3158 chainp = TAILQ_NEXT(chainp, wc_list); 3159 } 3160 3161 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3162 if (win[1].win_start == 0xffffffff) { 3163 /* window 1 is not used */ 3164 if ((win[0].win_flags == chainp->wc_flags) && 3165 (win[0].win_limit + align >= 3166 (chainp->wc_start & mask))) { 3167 /* concatenate */ 3168 win[0].win_limit = chainp->wc_end & mask; 3169 } else { 3170 /* make new window */ 3171 win[1].win_start = chainp->wc_start & mask; 3172 win[1].win_limit = chainp->wc_end & mask; 3173 win[1].win_flags = chainp->wc_flags; 3174 } 3175 continue; 3176 } 3177 3178 /* Both windows are engaged. */ 3179 if (win[0].win_flags == win[1].win_flags) { 3180 /* same flags */ 3181 if (win[0].win_flags == chainp->wc_flags) { 3182 if (win[1].win_start - (win[0].win_limit + 3183 align) < 3184 (chainp->wc_start & mask) - 3185 ((chainp->wc_end & mask) + align)) { 3186 /* 3187 * merge window 0 and 1, and set win1 3188 * to chainp 3189 */ 3190 win[0].win_limit = win[1].win_limit; 3191 win[1].win_start = 3192 chainp->wc_start & mask; 3193 win[1].win_limit = 3194 chainp->wc_end & mask; 3195 } else { 3196 win[1].win_limit = 3197 chainp->wc_end & mask; 3198 } 3199 } else { 3200 /* different flags */ 3201 3202 /* concatenate win0 and win1 */ 3203 win[0].win_limit = win[1].win_limit; 3204 /* allocate win[1] to new space */ 3205 win[1].win_start = chainp->wc_start & mask; 3206 win[1].win_limit = chainp->wc_end & mask; 3207 win[1].win_flags = chainp->wc_flags; 3208 } 3209 } else { 3210 /* the flags of win[0] and win[1] is different */ 3211 if (win[0].win_flags == chainp->wc_flags) { 3212 win[0].win_limit = chainp->wc_end & mask; 3213 /* 3214 * XXX this creates overlapping windows, so 3215 * what should the poor bridge do if one is 3216 * cachable, and the other is not? 3217 */ 3218 printf("%s: overlapping windows\n", 3219 sc->sc_dev.dv_xname); 3220 } else { 3221 win[1].win_limit = chainp->wc_end & mask; 3222 } 3223 } 3224 } 3225 3226 pc = sc->sc_pc; 3227 tag = sc->sc_tag; 3228 pci_conf_write(pc, tag, offs, win[0].win_start); 3229 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3230 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3231 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3232 DPRINTF(("--pccbb_winset: win0 [0x%lx, 0x%lx), win1 [0x%lx, 0x%lx)\n", 3233 (unsigned long)pci_conf_read(pc, tag, offs), 3234 (unsigned long)pci_conf_read(pc, tag, offs + 4) + align, 3235 (unsigned long)pci_conf_read(pc, tag, offs + 8), 3236 (unsigned long)pci_conf_read(pc, tag, offs + 12) + align)); 3237 3238 if (bst == sc->sc_memt) { 3239 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BRIDGE_CONTROL_REG); 3240 3241 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 3242 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 3243 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3244 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 3245 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3246 pci_conf_write(pc, tag, PCI_BRIDGE_CONTROL_REG, bcr); 3247 } 3248 } 3249 3250 #endif /* rbus */ 3251 3252 static void 3253 pccbb_powerhook(int why, void *arg) 3254 { 3255 struct pccbb_softc *sc = arg; 3256 pcireg_t reg; 3257 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3258 bus_space_handle_t base_memh = sc->sc_base_memh; 3259 3260 DPRINTF(("%s: power: why %d\n", sc->sc_dev.dv_xname, why)); 3261 3262 if (why == PWR_SUSPEND || why == PWR_STANDBY) { 3263 DPRINTF(("%s: power: why %d stopping intr\n", 3264 sc->sc_dev.dv_xname, why)); 3265 if (sc->sc_pil_intr_enable) { 3266 (void)pccbbintr_function(sc); 3267 } 3268 sc->sc_pil_intr_enable = 0; 3269 3270 pci_conf_capture(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf); 3271 3272 if (sc->sc_chipset == CB_RX5C47X) 3273 sc->sc_ricoh_misc_ctrl = pci_conf_read(sc->sc_pc, 3274 sc->sc_tag, 3275 RICOH_PCI_MISC_CTRL); 3276 3277 /* ToDo: deactivate or suspend child devices */ 3278 } 3279 3280 if (why == PWR_RESUME) { 3281 if (sc->sc_pwrmgt_offs != 0) { 3282 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, 3283 sc->sc_pwrmgt_offs + PCI_PMCSR); 3284 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 3285 reg & PCI_PMCSR_PME_EN) { 3286 /* powrstate != D0 */ 3287 3288 printf("%s going back to D0 mode\n", 3289 sc->sc_dev.dv_xname); 3290 reg &= ~PCI_PMCSR_STATE_MASK; 3291 reg |= PCI_PMCSR_STATE_D0; 3292 reg &= ~PCI_PMCSR_PME_EN; 3293 pci_conf_write(sc->sc_pc, sc->sc_tag, 3294 sc->sc_pwrmgt_offs + PCI_PMCSR, reg); 3295 3296 pci_conf_write(sc->sc_pc, sc->sc_tag, 3297 PCI_SOCKBASE, sc->sc_sockbase); 3298 pci_conf_write(sc->sc_pc, sc->sc_tag, 3299 PCI_BUSNUM, sc->sc_busnum); 3300 pccbb_chipinit(sc); 3301 /* setup memory and io space window for CB */ 3302 pccbb_winset(0x1000, sc, sc->sc_memt); 3303 pccbb_winset(0x04, sc, sc->sc_iot); 3304 goto norestore; 3305 } 3306 } 3307 3308 norestore: 3309 pci_conf_restore(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf); 3310 if (sc->sc_chipset == CB_RX5C47X) { 3311 pci_conf_write(sc->sc_pc, sc->sc_tag, 3312 RICOH_PCI_MISC_CTRL, sc->sc_ricoh_misc_ctrl); 3313 } 3314 3315 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_SOCKBASE) == 0) 3316 /* BIOS did not recover this register */ 3317 pci_conf_write (sc->sc_pc, sc->sc_tag, 3318 PCI_SOCKBASE, sc->sc_sockbase); 3319 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_BUSNUM) == 0) 3320 /* BIOS did not recover this register */ 3321 pci_conf_write (sc->sc_pc, sc->sc_tag, 3322 PCI_BUSNUM, sc->sc_busnum); 3323 /* CSC Interrupt: Card detect interrupt on */ 3324 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3325 /* Card detect intr is turned on. */ 3326 reg |= CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; 3327 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3328 /* reset interrupt */ 3329 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3330 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3331 3332 /* 3333 * check for card insertion or removal during suspend period. 3334 * XXX: the code can't cope with card swap (remove then 3335 * insert). how can we detect such situation? 3336 */ 3337 (void)pccbbintr(sc); 3338 3339 sc->sc_pil_intr_enable = 1; 3340 DPRINTF(("%s: power: RESUME enabling intr\n", 3341 sc->sc_dev.dv_xname)); 3342 3343 /* ToDo: activate or wakeup child devices */ 3344 } 3345 } 3346
Indexes created Fri Sep 26 20:09:58 GMT 2025