pccbb.c revision 1.152
1 /* $NetBSD: pccbb.c,v 1.152 2007/11/21 02:07:09 dyoung Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: pccbb.c,v 1.152 2007/11/21 02:07:09 dyoung Exp $"); 35 36 /* 37 #define CBB_DEBUG 38 #define SHOW_REGS 39 */ 40 41 /* 42 * BROKEN! 43 #define PCCBB_PCMCIA_POLL 44 #define CB_PCMCIA_POLL 45 #define CB_PCMCIA_POLL_ONLY 46 #define LEVEL2 47 */ 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/kernel.h> 52 #include <sys/errno.h> 53 #include <sys/ioctl.h> 54 #include <sys/reboot.h> /* for bootverbose */ 55 #include <sys/syslog.h> 56 #include <sys/device.h> 57 #include <sys/malloc.h> 58 #include <sys/proc.h> 59 60 #include <sys/intr.h> 61 #include <sys/bus.h> 62 63 #include <dev/pci/pcivar.h> 64 #include <dev/pci/pcireg.h> 65 #include <dev/pci/pcidevs.h> 66 67 #include <dev/pci/pccbbreg.h> 68 69 #include <dev/cardbus/cardslotvar.h> 70 71 #include <dev/cardbus/cardbusvar.h> 72 73 #include <dev/pcmcia/pcmciareg.h> 74 #include <dev/pcmcia/pcmciavar.h> 75 76 #include <dev/ic/i82365reg.h> 77 #include <dev/ic/i82365var.h> 78 #include <dev/pci/pccbbvar.h> 79 80 #include "locators.h" 81 82 #ifndef __NetBSD_Version__ 83 struct cfdriver cbb_cd = { 84 NULL, "cbb", DV_DULL 85 }; 86 #endif 87 88 #ifdef CBB_DEBUG 89 #define DPRINTF(x) printf x 90 #define STATIC 91 #else 92 #define DPRINTF(x) 93 #define STATIC static 94 #endif 95 96 int pccbb_burstup = 1; 97 98 /* 99 * delay_ms() is wait in milliseconds. It should be used instead 100 * of delay() if you want to wait more than 1 ms. 101 */ 102 static inline void 103 delay_ms(int millis, void *param) 104 { 105 if (cold) 106 delay(millis * 1000); 107 else 108 tsleep(param, PWAIT, "pccbb", MAX(2, hz * millis / 1000)); 109 } 110 111 int pcicbbmatch(struct device *, struct cfdata *, void *); 112 void pccbbattach(struct device *, struct device *, void *); 113 int pccbbintr(void *); 114 static void pci113x_insert(void *); 115 static int pccbbintr_function(struct pccbb_softc *); 116 117 static int pccbb_detect_card(struct pccbb_softc *); 118 119 static void pccbb_pcmcia_write(struct pcic_handle *, int, u_int8_t); 120 static u_int8_t pccbb_pcmcia_read(struct pcic_handle *, int); 121 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 122 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 123 124 STATIC int cb_reset(struct pccbb_softc *); 125 STATIC int cb_detect_voltage(struct pccbb_softc *); 126 STATIC int cbbprint(void *, const char *); 127 128 static int cb_chipset(u_int32_t, int *); 129 STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *, 130 struct pcmciabus_attach_args *); 131 #if 0 132 STATIC void pccbb_pcmcia_attach_card(struct pcic_handle *); 133 STATIC void pccbb_pcmcia_detach_card(struct pcic_handle *, int); 134 STATIC void pccbb_pcmcia_deactivate_card(struct pcic_handle *); 135 #endif 136 137 STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int); 138 STATIC int pccbb_power(cardbus_chipset_tag_t, int); 139 STATIC int pccbb_cardenable(struct pccbb_softc * sc, int function); 140 #if !rbus 141 static int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 142 static int pccbb_io_close(cardbus_chipset_tag_t, int); 143 static int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 144 static int pccbb_mem_close(cardbus_chipset_tag_t, int); 145 #endif /* !rbus */ 146 static void *pccbb_intr_establish(struct pccbb_softc *, int irq, 147 int level, int (*ih) (void *), void *sc); 148 static void pccbb_intr_disestablish(struct pccbb_softc *, void *ih); 149 150 static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t, int irq, 151 int level, int (*ih) (void *), void *sc); 152 static void pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih); 153 154 static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t, int, int); 155 static void pccbb_free_tag(cardbus_chipset_tag_t, cardbustag_t); 156 static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t, cardbustag_t, int); 157 static void pccbb_conf_write(cardbus_chipset_tag_t, cardbustag_t, int, 158 cardbusreg_t); 159 static void pccbb_chipinit(struct pccbb_softc *); 160 161 STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 162 struct pcmcia_mem_handle *); 163 STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t, 164 struct pcmcia_mem_handle *); 165 STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 166 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *); 167 STATIC void pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t, int); 168 STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 169 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 170 STATIC void pccbb_pcmcia_io_free(pcmcia_chipset_handle_t, 171 struct pcmcia_io_handle *); 172 STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 173 bus_size_t, struct pcmcia_io_handle *, int *); 174 STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t, int); 175 STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t, 176 struct pcmcia_function *, int, int (*)(void *), void *); 177 STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t, void *); 178 STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t); 179 STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t); 180 STATIC void pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t, int); 181 STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch); 182 183 static int pccbb_pcmcia_wait_ready(struct pcic_handle *); 184 static void pccbb_pcmcia_delay(struct pcic_handle *, int, const char *); 185 186 static void pccbb_pcmcia_do_io_map(struct pcic_handle *, int); 187 static void pccbb_pcmcia_do_mem_map(struct pcic_handle *, int); 188 static void pccbb_powerhook(int, void *); 189 190 /* bus-space allocation and deallocation functions */ 191 #if rbus 192 193 static int pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t, rbus_tag_t, 194 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 195 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp); 196 static int pccbb_rbus_cb_space_free(cardbus_chipset_tag_t, rbus_tag_t, 197 bus_space_handle_t, bus_size_t); 198 199 #endif /* rbus */ 200 201 #if rbus 202 203 static int pccbb_open_win(struct pccbb_softc *, bus_space_tag_t, 204 bus_addr_t, bus_size_t, bus_space_handle_t, int flags); 205 static int pccbb_close_win(struct pccbb_softc *, bus_space_tag_t, 206 bus_space_handle_t, bus_size_t); 207 static int pccbb_winlist_insert(struct pccbb_win_chain_head *, bus_addr_t, 208 bus_size_t, bus_space_handle_t, int); 209 static int pccbb_winlist_delete(struct pccbb_win_chain_head *, 210 bus_space_handle_t, bus_size_t); 211 static void pccbb_winset(bus_addr_t align, struct pccbb_softc *, 212 bus_space_tag_t); 213 void pccbb_winlist_show(struct pccbb_win_chain *); 214 215 #endif /* rbus */ 216 217 /* for config_defer */ 218 static void pccbb_pci_callback(struct device *); 219 220 #if defined SHOW_REGS 221 static void cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, 222 bus_space_tag_t memt, bus_space_handle_t memh); 223 #endif 224 225 CFATTACH_DECL(cbb_pci, sizeof(struct pccbb_softc), 226 pcicbbmatch, pccbbattach, NULL, NULL); 227 228 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 229 pccbb_pcmcia_mem_alloc, 230 pccbb_pcmcia_mem_free, 231 pccbb_pcmcia_mem_map, 232 pccbb_pcmcia_mem_unmap, 233 pccbb_pcmcia_io_alloc, 234 pccbb_pcmcia_io_free, 235 pccbb_pcmcia_io_map, 236 pccbb_pcmcia_io_unmap, 237 pccbb_pcmcia_intr_establish, 238 pccbb_pcmcia_intr_disestablish, 239 pccbb_pcmcia_socket_enable, 240 pccbb_pcmcia_socket_disable, 241 pccbb_pcmcia_socket_settype, 242 pccbb_pcmcia_card_detect 243 }; 244 245 #if rbus 246 static struct cardbus_functions pccbb_funcs = { 247 pccbb_rbus_cb_space_alloc, 248 pccbb_rbus_cb_space_free, 249 pccbb_cb_intr_establish, 250 pccbb_cb_intr_disestablish, 251 pccbb_ctrl, 252 pccbb_power, 253 pccbb_make_tag, 254 pccbb_free_tag, 255 pccbb_conf_read, 256 pccbb_conf_write, 257 }; 258 #else 259 static struct cardbus_functions pccbb_funcs = { 260 pccbb_ctrl, 261 pccbb_power, 262 pccbb_mem_open, 263 pccbb_mem_close, 264 pccbb_io_open, 265 pccbb_io_close, 266 pccbb_cb_intr_establish, 267 pccbb_cb_intr_disestablish, 268 pccbb_make_tag, 269 pccbb_conf_read, 270 pccbb_conf_write, 271 }; 272 #endif 273 274 int 275 pcicbbmatch(struct device *parent, struct cfdata *match, void *aux) 276 { 277 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 278 279 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 280 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 281 PCI_INTERFACE(pa->pa_class) == 0) { 282 return 1; 283 } 284 285 return 0; 286 } 287 288 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 289 | ((prod) << PCI_PRODUCT_SHIFT)) 290 291 const struct yenta_chipinfo { 292 pcireg_t yc_id; /* vendor tag | product tag */ 293 int yc_chiptype; 294 int yc_flags; 295 } yc_chipsets[] = { 296 /* Texas Instruments chips */ 297 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 298 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 299 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 300 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 301 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI125X, 302 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 303 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 304 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 305 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 306 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 307 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 308 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 309 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI125X, 310 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 311 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI125X, 312 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 313 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 314 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 315 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 316 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 317 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI1420, 318 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 319 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI125X, 320 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 321 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 322 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 323 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1520), CB_TI12XX, 324 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 325 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4410YENTA), CB_TI12XX, 326 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 327 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4520YENTA), CB_TI12XX, 328 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 329 330 /* Ricoh chips */ 331 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 332 PCCBB_PCMCIA_MEM_32}, 333 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 334 PCCBB_PCMCIA_MEM_32}, 335 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 336 PCCBB_PCMCIA_MEM_32}, 337 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 338 PCCBB_PCMCIA_MEM_32}, 339 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 340 PCCBB_PCMCIA_MEM_32}, 341 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 342 PCCBB_PCMCIA_MEM_32}, 343 344 /* Toshiba products */ 345 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 346 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 347 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 348 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 349 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 350 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 351 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 352 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 353 354 /* Cirrus Logic products */ 355 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 356 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 357 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 358 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 359 360 /* sentinel, or Generic chip */ 361 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 362 }; 363 364 static int 365 cb_chipset(u_int32_t pci_id, int *flagp) 366 { 367 const struct yenta_chipinfo *yc; 368 369 /* Loop over except the last default entry. */ 370 for (yc = yc_chipsets; yc < yc_chipsets + 371 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 372 if (pci_id == yc->yc_id) 373 break; 374 375 if (flagp != NULL) 376 *flagp = yc->yc_flags; 377 378 return (yc->yc_chiptype); 379 } 380 381 static void 382 pccbb_shutdown(void *arg) 383 { 384 struct pccbb_softc *sc = arg; 385 pcireg_t command; 386 387 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 388 389 /* 390 * turn off power 391 * 392 * XXX - do not turn off power if chipset is TI 113X because 393 * only TI 1130 with PowerMac 2400 hangs in pccbb_power(). 394 */ 395 if (sc->sc_chipset != CB_TI113X) { 396 pccbb_power((cardbus_chipset_tag_t)sc, 397 CARDBUS_VCC_0V | CARDBUS_VPP_0V); 398 } 399 400 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 401 0); 402 403 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 404 405 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 406 PCI_COMMAND_MASTER_ENABLE); 407 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 408 409 } 410 411 void 412 pccbbattach(struct device *parent, struct device *self, void *aux) 413 { 414 struct pccbb_softc *sc = (void *)self; 415 struct pci_attach_args *pa = aux; 416 pci_chipset_tag_t pc = pa->pa_pc; 417 pcireg_t busreg, reg, sock_base; 418 bus_addr_t sockbase; 419 char devinfo[256]; 420 int flags; 421 int pwrmgt_offs; 422 423 #ifdef __HAVE_PCCBB_ATTACH_HOOK 424 pccbb_attach_hook(parent, self, pa); 425 #endif 426 427 callout_init(&sc->sc_insert_ch, 0); 428 callout_setfunc(&sc->sc_insert_ch, pci113x_insert, sc); 429 430 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 431 432 pci_devinfo(pa->pa_id, 0, 0, devinfo, sizeof(devinfo)); 433 printf(": %s (rev. 0x%02x)", devinfo, PCI_REVISION(pa->pa_class)); 434 DPRINTF((" (chipflags %x)", flags)); 435 printf("\n"); 436 437 TAILQ_INIT(&sc->sc_memwindow); 438 TAILQ_INIT(&sc->sc_iowindow); 439 440 #if rbus 441 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 442 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 443 444 #if 0 445 printf("pa->pa_memt: %08x vs rbus_mem->rb_bt: %08x\n", 446 pa->pa_memt, sc->sc_rbus_memt->rb_bt); 447 #endif 448 #endif /* rbus */ 449 450 sc->sc_flags &= ~CBB_MEMHMAPPED; 451 452 /* power management: set D0 state */ 453 sc->sc_pwrmgt_offs = 0; 454 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, 455 &pwrmgt_offs, 0)) { 456 reg = pci_conf_read(pc, pa->pa_tag, pwrmgt_offs + PCI_PMCSR); 457 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 458 reg & 0x100 /* PCI_PMCSR_PME_EN */) { 459 reg &= ~PCI_PMCSR_STATE_MASK; 460 reg |= PCI_PMCSR_STATE_D0; 461 reg &= ~(0x100 /* PCI_PMCSR_PME_EN */); 462 pci_conf_write(pc, pa->pa_tag, 463 pwrmgt_offs + PCI_PMCSR, reg); 464 } 465 466 sc->sc_pwrmgt_offs = pwrmgt_offs; 467 } 468 469 /* 470 * MAP socket registers and ExCA registers on memory-space 471 * When no valid address is set on socket base registers (on pci 472 * config space), get it not polite way. 473 */ 474 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 475 476 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 477 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 478 /* The address must be valid. */ 479 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 480 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL)) { 481 printf("%s: can't map socket base address 0x%lx\n", 482 sc->sc_dev.dv_xname, (unsigned long)sock_base); 483 /* 484 * I think it's funny: socket base registers must be 485 * mapped on memory space, but ... 486 */ 487 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 488 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 489 NULL)) { 490 printf("%s: can't map socket base address" 491 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 492 (unsigned long)sockbase); 493 /* give up... allocate reg space via rbus. */ 494 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 495 } else 496 sc->sc_flags |= CBB_MEMHMAPPED; 497 } else { 498 DPRINTF(("%s: socket base address 0x%lx\n", 499 sc->sc_dev.dv_xname, (unsigned long)sockbase)); 500 sc->sc_flags |= CBB_MEMHMAPPED; 501 } 502 } 503 504 sc->sc_mem_start = 0; /* XXX */ 505 sc->sc_mem_end = 0xffffffff; /* XXX */ 506 507 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 508 509 /* pccbb_machdep.c end */ 510 511 #if defined CBB_DEBUG 512 { 513 static const char *intrname[] = { "NON", "A", "B", "C", "D" }; 514 printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname, 515 intrname[pa->pa_intrpin], pa->pa_intrline); 516 } 517 #endif 518 519 /* setup softc */ 520 sc->sc_pc = pc; 521 sc->sc_iot = pa->pa_iot; 522 sc->sc_memt = pa->pa_memt; 523 sc->sc_dmat = pa->pa_dmat; 524 sc->sc_tag = pa->pa_tag; 525 sc->sc_function = pa->pa_function; 526 sc->sc_sockbase = sock_base; 527 sc->sc_busnum = busreg; 528 529 memcpy(&sc->sc_pa, pa, sizeof(*pa)); 530 531 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 532 533 shutdownhook_establish(pccbb_shutdown, sc); 534 535 /* Disable legacy register mapping. */ 536 switch (sc->sc_chipset) { 537 case CB_RX5C46X: /* fallthrough */ 538 #if 0 539 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 540 case CB_RX5C47X: 541 #endif 542 /* 543 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 544 * cannot be disabled by substituting 0 into PCI_LEGACY 545 * register. Ricoh CardBus bridges have special bits on Bridge 546 * control reg (addr 0x3e on PCI config space). 547 */ 548 reg = pci_conf_read(pc, pa->pa_tag, PCI_BRIDGE_CONTROL_REG); 549 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 550 pci_conf_write(pc, pa->pa_tag, PCI_BRIDGE_CONTROL_REG, reg); 551 break; 552 553 default: 554 /* XXX I don't know proper way to kill legacy I/O. */ 555 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 556 break; 557 } 558 559 config_defer(self, pccbb_pci_callback); 560 } 561 562 563 564 565 /* 566 * static void pccbb_pci_callback(struct device *self) 567 * 568 * The actual attach routine: get memory space for YENTA register 569 * space, setup YENTA register and route interrupt. 570 * 571 * This function should be deferred because this device may obtain 572 * memory space dynamically. This function must avoid obtaining 573 * memory area which has already kept for another device. 574 */ 575 static void 576 pccbb_pci_callback(struct device *self) 577 { 578 struct pccbb_softc *sc = (void *)self; 579 pci_chipset_tag_t pc = sc->sc_pc; 580 pci_intr_handle_t ih; 581 const char *intrstr = NULL; 582 bus_addr_t sockbase; 583 struct cbslot_attach_args cba; 584 struct pcmciabus_attach_args paa; 585 struct cardslot_attach_args caa; 586 struct cardslot_softc *csc; 587 588 if (!(sc->sc_flags & CBB_MEMHMAPPED)) { 589 /* The socket registers aren't mapped correctly. */ 590 #if rbus 591 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 592 (sc->sc_chipset == CB_RX5C47X 593 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 594 0, &sockbase, &sc->sc_base_memh)) { 595 return; 596 } 597 sc->sc_base_memt = sc->sc_memt; 598 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 599 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 600 sc->sc_dev.dv_xname, (unsigned long)sockbase, 601 (unsigned long)pci_conf_read(pc, sc->sc_tag, 602 PCI_SOCKBASE))); 603 #else 604 sc->sc_base_memt = sc->sc_memt; 605 #if !defined CBB_PCI_BASE 606 #define CBB_PCI_BASE 0x20000000 607 #endif 608 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 609 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 610 /* cannot allocate memory space */ 611 return; 612 } 613 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 614 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 615 sc->sc_dev.dv_xname, (unsigned long)sock_base, 616 (unsigned long)pci_conf_read(pc, 617 sc->sc_tag, PCI_SOCKBASE))); 618 sc->sc_sockbase = sockbase; 619 #endif 620 sc->sc_flags |= CBB_MEMHMAPPED; 621 } 622 623 /* bus bridge initialization */ 624 pccbb_chipinit(sc); 625 626 /* clear data structure for child device interrupt handlers */ 627 LIST_INIT(&sc->sc_pil); 628 sc->sc_pil_intr_enable = 1; 629 630 /* Map and establish the interrupt. */ 631 if (pci_intr_map(&sc->sc_pa, &ih)) { 632 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 633 return; 634 } 635 intrstr = pci_intr_string(pc, ih); 636 637 /* 638 * XXX pccbbintr should be called under the priority lower 639 * than any other hard interupts. 640 */ 641 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 642 643 if (sc->sc_ih == NULL) { 644 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 645 if (intrstr != NULL) { 646 printf(" at %s", intrstr); 647 } 648 printf("\n"); 649 return; 650 } 651 652 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 653 powerhook_establish(sc->sc_dev.dv_xname, pccbb_powerhook, sc); 654 655 { 656 u_int32_t sockstat; 657 658 sockstat = bus_space_read_4(sc->sc_base_memt, 659 sc->sc_base_memh, CB_SOCKET_STAT); 660 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 661 sc->sc_flags |= CBB_CARDEXIST; 662 } 663 } 664 665 /* 666 * attach cardbus 667 */ 668 { 669 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 670 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 671 672 /* initialize cbslot_attach */ 673 cba.cba_busname = "cardbus"; 674 cba.cba_iot = sc->sc_iot; 675 cba.cba_memt = sc->sc_memt; 676 cba.cba_dmat = sc->sc_dmat; 677 cba.cba_bus = (busreg >> 8) & 0x0ff; 678 cba.cba_cc = (void *)sc; 679 cba.cba_cf = &pccbb_funcs; 680 cba.cba_intrline = sc->sc_pa.pa_intrline; 681 682 #if rbus 683 cba.cba_rbus_iot = sc->sc_rbus_iot; 684 cba.cba_rbus_memt = sc->sc_rbus_memt; 685 #endif 686 687 cba.cba_cacheline = PCI_CACHELINE(bhlc); 688 cba.cba_max_lattimer = PCI_LATTIMER(bhlc); 689 690 if (bootverbose) { 691 printf("%s: cacheline 0x%x lattimer 0x%x\n", 692 sc->sc_dev.dv_xname, cba.cba_cacheline, 693 cba.cba_max_lattimer); 694 printf("%s: bhlc 0x%x\n", 695 device_xname(&sc->sc_dev), bhlc); 696 } 697 #if defined SHOW_REGS 698 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 699 sc->sc_base_memh); 700 #endif 701 } 702 703 pccbb_pcmcia_attach_setup(sc, &paa); 704 caa.caa_cb_attach = NULL; 705 if (cba.cba_bus == 0) 706 printf("%s: secondary bus number uninitialized; try PCI_BUS_FIXUP\n", sc->sc_dev.dv_xname); 707 else 708 caa.caa_cb_attach = &cba; 709 caa.caa_16_attach = &paa; 710 caa.caa_ph = &sc->sc_pcmcia_h; 711 712 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 713 DPRINTF(("%s: found cardslot\n", __func__)); 714 sc->sc_csc = csc; 715 } 716 717 return; 718 } 719 720 721 722 723 724 /* 725 * static void pccbb_chipinit(struct pccbb_softc *sc) 726 * 727 * This function initialize YENTA chip registers listed below: 728 * 1) PCI command reg, 729 * 2) PCI and CardBus latency timer, 730 * 3) route PCI interrupt, 731 * 4) close all memory and io windows. 732 * 5) turn off bus power. 733 * 6) card detect and power cycle interrupts on. 734 * 7) clear interrupt 735 */ 736 static void 737 pccbb_chipinit(struct pccbb_softc *sc) 738 { 739 pci_chipset_tag_t pc = sc->sc_pc; 740 pcitag_t tag = sc->sc_tag; 741 bus_space_tag_t bmt = sc->sc_base_memt; 742 bus_space_handle_t bmh = sc->sc_base_memh; 743 pcireg_t bcr, bhlc, cbctl, csr, lscp, mfunc, mrburst, slotctl, sockctl, 744 sockmask, sysctrl; 745 746 /* 747 * Set PCI command reg. 748 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 749 */ 750 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 751 /* I believe it is harmless. */ 752 csr |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 753 PCI_COMMAND_MASTER_ENABLE); 754 csr |= (PCI_COMMAND_PARITY_ENABLE|PCI_COMMAND_SERR_ENABLE); 755 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 756 757 /* 758 * Set CardBus latency timer. 759 */ 760 lscp = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 761 if (PCI_CB_LATENCY(lscp) < 0x20) { 762 lscp &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 763 lscp |= (0x20 << PCI_CB_LATENCY_SHIFT); 764 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, lscp); 765 } 766 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 767 PCI_CB_LATENCY(lscp), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 768 769 /* 770 * Set PCI latency timer. 771 */ 772 bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG); 773 if (PCI_LATTIMER(bhlc) < 0x10) { 774 bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 775 bhlc |= (0x10 << PCI_LATTIMER_SHIFT); 776 pci_conf_write(pc, tag, PCI_BHLC_REG, bhlc); 777 } 778 DPRINTF(("PCI latency timer 0x%x (%x)\n", 779 PCI_LATTIMER(bhlc), pci_conf_read(pc, tag, PCI_BHLC_REG))); 780 781 782 /* Route functional interrupts to PCI. */ 783 bcr = pci_conf_read(pc, tag, PCI_BRIDGE_CONTROL_REG); 784 bcr |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 785 bcr |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 786 /* assert reset */ 787 bcr |= PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT; 788 /* Set master abort mode to 1, forward SERR# from secondary 789 * to primary, and detect parity errors on secondary. 790 */ 791 bcr |= PCI_BRIDGE_CONTROL_MABRT << PCI_BRIDGE_CONTROL_SHIFT; 792 bcr |= PCI_BRIDGE_CONTROL_SERR << PCI_BRIDGE_CONTROL_SHIFT; 793 bcr |= PCI_BRIDGE_CONTROL_PERE << PCI_BRIDGE_CONTROL_SHIFT; 794 pci_conf_write(pc, tag, PCI_BRIDGE_CONTROL_REG, bcr); 795 796 switch (sc->sc_chipset) { 797 case CB_TI113X: 798 cbctl = pci_conf_read(pc, tag, PCI_CBCTRL); 799 /* This bit is shared, but may read as 0 on some chips, so set 800 it explicitly on both functions. */ 801 cbctl |= PCI113X_CBCTRL_PCI_IRQ_ENA; 802 /* CSC intr enable */ 803 cbctl |= PCI113X_CBCTRL_PCI_CSC; 804 /* functional intr prohibit | prohibit ISA routing */ 805 cbctl &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 806 pci_conf_write(pc, tag, PCI_CBCTRL, cbctl); 807 break; 808 809 case CB_TI1420: 810 sysctrl = pci_conf_read(pc, tag, PCI_SYSCTRL); 811 mrburst = pccbb_burstup 812 ? PCI1420_SYSCTRL_MRBURST : PCI1420_SYSCTRL_MRBURSTDN; 813 if ((sysctrl & PCI1420_SYSCTRL_MRBURST) == mrburst) { 814 printf("%s: %swrite bursts enabled\n", 815 device_xname(&sc->sc_dev), 816 pccbb_burstup ? "read/" : ""); 817 } else if (pccbb_burstup) { 818 printf("%s: enabling read/write bursts\n", 819 device_xname(&sc->sc_dev)); 820 sysctrl |= PCI1420_SYSCTRL_MRBURST; 821 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 822 } else { 823 printf("%s: disabling read bursts, " 824 "enabling write bursts\n", 825 device_xname(&sc->sc_dev)); 826 sysctrl |= PCI1420_SYSCTRL_MRBURSTDN; 827 sysctrl &= ~PCI1420_SYSCTRL_MRBURSTUP; 828 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 829 } 830 /*FALLTHROUGH*/ 831 case CB_TI12XX: 832 /* 833 * Some TI 12xx (and [14][45]xx) based pci cards 834 * sometimes have issues with the MFUNC register not 835 * being initialized due to a bad EEPROM on board. 836 * Laptops that this matters on have this register 837 * properly initialized. 838 * 839 * The TI125X parts have a different register. 840 */ 841 mfunc = pci_conf_read(pc, tag, PCI12XX_MFUNC); 842 if (mfunc == 0) { 843 mfunc &= ~PCI12XX_MFUNC_PIN0; 844 mfunc |= PCI12XX_MFUNC_PIN0_INTA; 845 if ((pci_conf_read(pc, tag, PCI_SYSCTRL) & 846 PCI12XX_SYSCTRL_INTRTIE) == 0) { 847 mfunc &= ~PCI12XX_MFUNC_PIN1; 848 mfunc |= PCI12XX_MFUNC_PIN1_INTB; 849 } 850 pci_conf_write(pc, tag, PCI12XX_MFUNC, mfunc); 851 } 852 /* fallthrough */ 853 854 case CB_TI125X: 855 /* 856 * Disable zoom video. Some machines initialize this 857 * improperly and experience has shown that this helps 858 * prevent strange behavior. 859 */ 860 pci_conf_write(pc, tag, PCI12XX_MMCTRL, 0); 861 862 sysctrl = pci_conf_read(pc, tag, PCI_SYSCTRL); 863 sysctrl |= PCI12XX_SYSCTRL_VCCPROT; 864 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 865 cbctl = pci_conf_read(pc, tag, PCI_CBCTRL); 866 cbctl |= PCI12XX_CBCTRL_CSC; 867 pci_conf_write(pc, tag, PCI_CBCTRL, cbctl); 868 break; 869 870 case CB_TOPIC95B: 871 sockctl = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 872 sockctl |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 873 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, sockctl); 874 slotctl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 875 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 876 sc->sc_dev.dv_xname, slotctl)); 877 slotctl |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 878 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 879 slotctl &= ~TOPIC_SLOT_CTRL_SWDETECT; 880 DPRINTF(("0x%x\n", slotctl)); 881 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slotctl); 882 break; 883 884 case CB_TOPIC97: 885 slotctl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 886 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 887 sc->sc_dev.dv_xname, slotctl)); 888 slotctl |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 889 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 890 slotctl &= ~TOPIC_SLOT_CTRL_SWDETECT; 891 slotctl |= TOPIC97_SLOT_CTRL_PCIINT; 892 slotctl &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 893 DPRINTF(("0x%x\n", slotctl)); 894 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slotctl); 895 /* make sure to assert LV card support bits */ 896 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 897 0x800 + 0x3e, 898 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 899 0x800 + 0x3e) | 0x03); 900 break; 901 } 902 903 /* Close all memory and I/O windows. */ 904 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 905 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 906 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 907 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 908 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 909 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 910 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 911 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 912 913 /* reset 16-bit pcmcia bus */ 914 bus_space_write_1(bmt, bmh, 0x800 + PCIC_INTR, 915 bus_space_read_1(bmt, bmh, 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 916 917 /* turn off power */ 918 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 919 920 /* CSC Interrupt: Card detect and power cycle interrupts on */ 921 sockmask = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 922 sockmask |= CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; 923 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, sockmask); 924 /* reset interrupt */ 925 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 926 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 927 } 928 929 930 931 932 /* 933 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 934 * struct pcmciabus_attach_args *paa) 935 * 936 * This function attaches 16-bit PCcard bus. 937 */ 938 STATIC void 939 pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 940 struct pcmciabus_attach_args *paa) 941 { 942 struct pcic_handle *ph = &sc->sc_pcmcia_h; 943 #if rbus 944 rbus_tag_t rb; 945 #endif 946 947 /* initialize pcmcia part in pccbb_softc */ 948 ph->ph_parent = (struct device *)sc; 949 ph->sock = sc->sc_function; 950 ph->flags = 0; 951 ph->shutdown = 0; 952 ph->ih_irq = sc->sc_pa.pa_intrline; 953 ph->ph_bus_t = sc->sc_base_memt; 954 ph->ph_bus_h = sc->sc_base_memh; 955 ph->ph_read = pccbb_pcmcia_read; 956 ph->ph_write = pccbb_pcmcia_write; 957 sc->sc_pct = &pccbb_pcmcia_funcs; 958 959 /* 960 * We need to do a few things here: 961 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 962 * setting the IRQ numbers to 0. 963 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 964 * routing of CSC interrupts (e.g. card removal) to PCI while in 965 * PCMCIA mode. We just leave this set all the time. 966 * 3) Enable card insertion/removal interrupts in case the chip also 967 * needs that while in PCMCIA mode. 968 * 4) Clear any pending CSC interrupt. 969 */ 970 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE); 971 if (sc->sc_chipset == CB_TI113X) { 972 Pcic_write(ph, PCIC_CSC_INTR, 0); 973 } else { 974 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 975 Pcic_read(ph, PCIC_CSC); 976 } 977 978 /* initialize pcmcia bus attachment */ 979 paa->paa_busname = "pcmcia"; 980 paa->pct = sc->sc_pct; 981 paa->pch = ph; 982 paa->iobase = 0; /* I don't use them */ 983 paa->iosize = 0; 984 #if rbus 985 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 986 paa->iobase = rb->rb_start + rb->rb_offset; 987 paa->iosize = rb->rb_end - rb->rb_start; 988 #endif 989 990 return; 991 } 992 993 #if 0 994 STATIC void 995 pccbb_pcmcia_attach_card(struct pcic_handle *ph) 996 { 997 if (ph->flags & PCIC_FLAG_CARDP) { 998 panic("pccbb_pcmcia_attach_card: already attached"); 999 } 1000 1001 /* call the MI attach function */ 1002 pcmcia_card_attach(ph->pcmcia); 1003 1004 ph->flags |= PCIC_FLAG_CARDP; 1005 } 1006 1007 STATIC void 1008 pccbb_pcmcia_detach_card(struct pcic_handle *ph, int flags) 1009 { 1010 if (!(ph->flags & PCIC_FLAG_CARDP)) { 1011 panic("pccbb_pcmcia_detach_card: already detached"); 1012 } 1013 1014 ph->flags &= ~PCIC_FLAG_CARDP; 1015 1016 /* call the MI detach function */ 1017 pcmcia_card_detach(ph->pcmcia, flags); 1018 } 1019 #endif 1020 1021 /* 1022 * int pccbbintr(arg) 1023 * void *arg; 1024 * This routine handles the interrupt from Yenta PCI-CardBus bridge 1025 * itself. 1026 */ 1027 int 1028 pccbbintr(void *arg) 1029 { 1030 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1031 u_int32_t sockevent, sockstate; 1032 bus_space_tag_t memt = sc->sc_base_memt; 1033 bus_space_handle_t memh = sc->sc_base_memh; 1034 struct pcic_handle *ph = &sc->sc_pcmcia_h; 1035 1036 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 1037 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 1038 Pcic_read(ph, PCIC_CSC); 1039 1040 if (sockevent != 0) { 1041 aprint_debug("%s: enter sockevent %" PRIx32 "\n", __func__, 1042 sockevent); 1043 } 1044 1045 /* Sometimes a change of CSTSCHG# accompanies the first 1046 * interrupt from an Atheros WLAN. That generates a 1047 * CB_SOCKET_EVENT_CSTS event on the bridge. The event 1048 * isn't interesting to pccbb(4), so we used to ignore the 1049 * interrupt. Now, let the child devices try to handle 1050 * the interrupt, instead. The Atheros NIC produces 1051 * interrupts more reliably, now: used to be that it would 1052 * only interrupt if the driver avoided powering down the 1053 * NIC's cardslot, and then the NIC would only work after 1054 * it was reset a second time. 1055 */ 1056 if (sockevent == 0 || 1057 (sockevent & ~(CB_SOCKET_EVENT_POWER|CB_SOCKET_EVENT_CD)) != 0) { 1058 /* This intr is not for me: it may be for my child devices. */ 1059 if (sc->sc_pil_intr_enable) { 1060 return pccbbintr_function(sc); 1061 } else { 1062 return 0; 1063 } 1064 } 1065 1066 if (sockevent & CB_SOCKET_EVENT_CD) { 1067 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1068 if (0x00 != (sockstate & CB_SOCKET_STAT_CD)) { 1069 /* A card should be removed. */ 1070 if (sc->sc_flags & CBB_CARDEXIST) { 1071 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 1072 sockevent)); 1073 DPRINTF((" card removed, 0x%08x\n", sockstate)); 1074 sc->sc_flags &= ~CBB_CARDEXIST; 1075 if (sc->sc_csc->sc_status & 1076 CARDSLOT_STATUS_CARD_16) { 1077 #if 0 1078 struct pcic_handle *ph = 1079 &sc->sc_pcmcia_h; 1080 1081 pcmcia_card_deactivate(ph->pcmcia); 1082 pccbb_pcmcia_socket_disable(ph); 1083 pccbb_pcmcia_detach_card(ph, 1084 DETACH_FORCE); 1085 #endif 1086 cardslot_event_throw(sc->sc_csc, 1087 CARDSLOT_EVENT_REMOVAL_16); 1088 } else if (sc->sc_csc->sc_status & 1089 CARDSLOT_STATUS_CARD_CB) { 1090 /* Cardbus intr removed */ 1091 cardslot_event_throw(sc->sc_csc, 1092 CARDSLOT_EVENT_REMOVAL_CB); 1093 } 1094 } else if (sc->sc_flags & CBB_INSERTING) { 1095 sc->sc_flags &= ~CBB_INSERTING; 1096 callout_stop(&sc->sc_insert_ch); 1097 } 1098 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 1099 /* 1100 * The pccbbintr may called from powerdown hook when 1101 * the system resumed, to detect the card 1102 * insertion/removal during suspension. 1103 */ 1104 (sc->sc_flags & CBB_CARDEXIST) == 0) { 1105 if (sc->sc_flags & CBB_INSERTING) { 1106 callout_stop(&sc->sc_insert_ch); 1107 } 1108 callout_schedule(&sc->sc_insert_ch, hz / 5); 1109 sc->sc_flags |= CBB_INSERTING; 1110 } 1111 } 1112 1113 if (sockevent & CB_SOCKET_EVENT_POWER) { 1114 DPRINTF(("Powercycling because of socket event\n")); 1115 /* XXX: Does not happen when attaching a 16-bit card */ 1116 sc->sc_pwrcycle++; 1117 wakeup(&sc->sc_pwrcycle); 1118 } 1119 1120 return (1); 1121 } 1122 1123 /* 1124 * static int pccbbintr_function(struct pccbb_softc *sc) 1125 * 1126 * This function calls each interrupt handler registered at the 1127 * bridge. The interrupt handlers are called in registered order. 1128 */ 1129 static int 1130 pccbbintr_function(struct pccbb_softc *sc) 1131 { 1132 int retval = 0, val; 1133 struct pccbb_intrhand_list *pil; 1134 int s; 1135 1136 for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1137 pil = LIST_NEXT(pil, pil_next)) { 1138 s = splraiseipl(pil->pil_icookie); 1139 val = (*pil->pil_func)(pil->pil_arg); 1140 splx(s); 1141 1142 retval = retval == 1 ? 1 : 1143 retval == 0 ? val : val != 0 ? val : retval; 1144 } 1145 1146 return retval; 1147 } 1148 1149 static void 1150 pci113x_insert(void *arg) 1151 { 1152 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1153 u_int32_t sockevent, sockstate; 1154 1155 if (!(sc->sc_flags & CBB_INSERTING)) { 1156 /* We add a card only under inserting state. */ 1157 return; 1158 } 1159 sc->sc_flags &= ~CBB_INSERTING; 1160 1161 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1162 CB_SOCKET_EVENT); 1163 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1164 CB_SOCKET_STAT); 1165 1166 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1167 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1168 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1169 sc->sc_flags |= CBB_CARDEXIST; 1170 /* call pccard interrupt handler here */ 1171 if (sockstate & CB_SOCKET_STAT_16BIT) { 1172 /* 16-bit card found */ 1173 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1174 cardslot_event_throw(sc->sc_csc, 1175 CARDSLOT_EVENT_INSERTION_16); 1176 } else if (sockstate & CB_SOCKET_STAT_CB) { 1177 /* cardbus card found */ 1178 /* cardbus_attach_card(sc->sc_csc); */ 1179 cardslot_event_throw(sc->sc_csc, 1180 CARDSLOT_EVENT_INSERTION_CB); 1181 } else { 1182 /* who are you? */ 1183 } 1184 } else { 1185 callout_schedule(&sc->sc_insert_ch, hz / 10); 1186 } 1187 } 1188 1189 #define PCCBB_PCMCIA_OFFSET 0x800 1190 static u_int8_t 1191 pccbb_pcmcia_read(struct pcic_handle *ph, int reg) 1192 { 1193 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1194 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1195 1196 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1197 PCCBB_PCMCIA_OFFSET + reg); 1198 } 1199 1200 static void 1201 pccbb_pcmcia_write(struct pcic_handle *ph, int reg, u_int8_t val) 1202 { 1203 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1204 val); 1205 1206 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1207 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1208 } 1209 1210 /* 1211 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1212 */ 1213 STATIC int 1214 pccbb_ctrl(cardbus_chipset_tag_t ct, int command) 1215 { 1216 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1217 1218 switch (command) { 1219 case CARDBUS_CD: 1220 if (2 == pccbb_detect_card(sc)) { 1221 int retval = 0; 1222 int status = cb_detect_voltage(sc); 1223 if (PCCARD_VCC_5V & status) { 1224 retval |= CARDBUS_5V_CARD; 1225 } 1226 if (PCCARD_VCC_3V & status) { 1227 retval |= CARDBUS_3V_CARD; 1228 } 1229 if (PCCARD_VCC_XV & status) { 1230 retval |= CARDBUS_XV_CARD; 1231 } 1232 if (PCCARD_VCC_YV & status) { 1233 retval |= CARDBUS_YV_CARD; 1234 } 1235 return retval; 1236 } else { 1237 return 0; 1238 } 1239 case CARDBUS_RESET: 1240 return cb_reset(sc); 1241 case CARDBUS_IO_ENABLE: /* fallthrough */ 1242 case CARDBUS_IO_DISABLE: /* fallthrough */ 1243 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1244 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1245 case CARDBUS_BM_ENABLE: /* fallthrough */ 1246 case CARDBUS_BM_DISABLE: /* fallthrough */ 1247 /* XXX: I think we don't need to call this function below. */ 1248 return pccbb_cardenable(sc, command); 1249 } 1250 1251 return 0; 1252 } 1253 1254 /* 1255 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1256 * This function returns true when it succeeds and returns false when 1257 * it fails. 1258 */ 1259 STATIC int 1260 pccbb_power(cardbus_chipset_tag_t ct, int command) 1261 { 1262 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1263 u_int32_t status, osock_ctrl, sock_ctrl, reg_ctrl; 1264 bus_space_tag_t memt = sc->sc_base_memt; 1265 bus_space_handle_t memh = sc->sc_base_memh; 1266 int on = 0, pwrcycle, s, times; 1267 struct timeval before, after, diff; 1268 1269 DPRINTF(("pccbb_power: %s and %s [0x%x]\n", 1270 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1271 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1272 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1273 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1274 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1275 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1276 "UNKNOWN", 1277 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1278 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1279 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1280 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1281 "UNKNOWN", command)); 1282 1283 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1284 osock_ctrl = sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1285 1286 switch (command & CARDBUS_VCCMASK) { 1287 case CARDBUS_VCC_UC: 1288 break; 1289 case CARDBUS_VCC_5V: 1290 on++; 1291 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1292 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1293 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1294 } else { 1295 printf("%s: BAD voltage request: no 5 V card\n", 1296 sc->sc_dev.dv_xname); 1297 return 0; 1298 } 1299 break; 1300 case CARDBUS_VCC_3V: 1301 on++; 1302 if (CB_SOCKET_STAT_3VCARD & status) { 1303 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1304 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1305 } else { 1306 printf("%s: BAD voltage request: no 3.3 V card\n", 1307 sc->sc_dev.dv_xname); 1308 return 0; 1309 } 1310 break; 1311 case CARDBUS_VCC_0V: 1312 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1313 break; 1314 default: 1315 return 0; /* power NEVER changed */ 1316 } 1317 1318 switch (command & CARDBUS_VPPMASK) { 1319 case CARDBUS_VPP_UC: 1320 break; 1321 case CARDBUS_VPP_0V: 1322 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1323 break; 1324 case CARDBUS_VPP_VCC: 1325 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1326 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1327 break; 1328 case CARDBUS_VPP_12V: 1329 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1330 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1331 break; 1332 } 1333 1334 pwrcycle = sc->sc_pwrcycle; 1335 aprint_debug("%s: osock_ctrl %#" PRIx32 " sock_ctrl %#" PRIx32 "\n", 1336 device_xname(&sc->sc_dev), osock_ctrl, sock_ctrl); 1337 1338 microtime(&before); 1339 s = splbio(); 1340 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1341 1342 /* 1343 * Wait as long as 200ms for a power-cycle interrupt. If 1344 * interrupts are enabled, but the socket has already 1345 * changed to the desired status, keep waiting for the 1346 * interrupt. "Consuming" the interrupt in this way keeps 1347 * the interrupt from prematurely waking some subsequent 1348 * pccbb_power call. 1349 * 1350 * XXX Not every bridge interrupts on the ->OFF transition. 1351 * XXX That's ok, we will time-out after 200ms. 1352 * 1353 * XXX The power cycle event will never happen when attaching 1354 * XXX a 16-bit card. That's ok, we will time-out after 1355 * XXX 200ms. 1356 */ 1357 for (times = 5; --times >= 0; ) { 1358 if (cold) 1359 DELAY(40 * 1000); 1360 else { 1361 (void)tsleep(&sc->sc_pwrcycle, PWAIT, "pccpwr", 1362 hz / 25); 1363 if (pwrcycle == sc->sc_pwrcycle) 1364 continue; 1365 } 1366 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1367 if ((status & CB_SOCKET_STAT_PWRCYCLE) != 0 && on) 1368 break; 1369 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0 && !on) 1370 break; 1371 } 1372 splx(s); 1373 microtime(&after); 1374 timersub(&after, &before, &diff); 1375 aprint_debug("%s: wait took%s %ld.%06lds\n", sc->sc_dev.dv_xname, 1376 (on && times < 0) ? " too long" : "", diff.tv_sec, diff.tv_usec); 1377 1378 /* 1379 * Ok, wait a bit longer for things to settle. 1380 */ 1381 if (on && sc->sc_chipset == CB_TOPIC95B) 1382 delay_ms(100, sc); 1383 1384 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1385 1386 if (on && sc->sc_chipset != CB_TOPIC95B) { 1387 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0) 1388 printf("%s: power on failed?\n", sc->sc_dev.dv_xname); 1389 } 1390 1391 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1392 printf("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1393 sc->sc_dev.dv_xname, sock_ctrl, status); 1394 printf("%s: disabling socket\n", sc->sc_dev.dv_xname); 1395 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1396 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1397 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1398 status &= ~CB_SOCKET_STAT_BADVCC; 1399 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, status); 1400 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1401 CB_SOCKET_STAT)); 1402 return 0; 1403 } 1404 1405 if (sc->sc_chipset == CB_TOPIC97) { 1406 reg_ctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL); 1407 reg_ctrl &= ~TOPIC97_REG_CTRL_TESTMODE; 1408 if ((command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V) 1409 reg_ctrl &= ~TOPIC97_REG_CTRL_CLKRUN_ENA; 1410 else 1411 reg_ctrl |= TOPIC97_REG_CTRL_CLKRUN_ENA; 1412 pci_conf_write(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL, reg_ctrl); 1413 } 1414 1415 return 1; /* power changed correctly */ 1416 } 1417 1418 #if defined CB_PCMCIA_POLL 1419 struct cb_poll_str { 1420 void *arg; 1421 int (*func)(void *); 1422 int level; 1423 pccard_chipset_tag_t ct; 1424 int count; 1425 struct callout poll_ch; 1426 }; 1427 1428 static struct cb_poll_str cb_poll[10]; 1429 static int cb_poll_n = 0; 1430 1431 static void cb_pcmcia_poll(void *arg); 1432 1433 static void 1434 cb_pcmcia_poll(void *arg) 1435 { 1436 struct cb_poll_str *poll = arg; 1437 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1438 struct pccbb_softc *sc = psc->cpc_parent; 1439 int s; 1440 u_int32_t spsr; /* socket present-state reg */ 1441 1442 callout_reset(&poll->poll_ch, hz / 10, cb_pcmcia_poll, poll); 1443 switch (poll->level) { 1444 case IPL_NET: 1445 s = splnet(); 1446 break; 1447 case IPL_BIO: 1448 s = splbio(); 1449 break; 1450 case IPL_TTY: /* fallthrough */ 1451 default: 1452 s = spltty(); 1453 break; 1454 } 1455 1456 spsr = 1457 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1458 CB_SOCKET_STAT); 1459 1460 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1461 if (!(spsr & 0x40)) { /* CINT low */ 1462 #else 1463 if (1) { 1464 #endif 1465 if ((*poll->func) (poll->arg) == 1) { 1466 ++poll->count; 1467 printf("intr: reported from poller, 0x%x\n", spsr); 1468 #if defined LEVEL2 1469 } else { 1470 printf("intr: miss! 0x%x\n", spsr); 1471 #endif 1472 } 1473 } 1474 splx(s); 1475 } 1476 #endif /* defined CB_PCMCIA_POLL */ 1477 1478 /* 1479 * static int pccbb_detect_card(struct pccbb_softc *sc) 1480 * return value: 0 if no card exists. 1481 * 1 if 16-bit card exists. 1482 * 2 if cardbus card exists. 1483 */ 1484 static int 1485 pccbb_detect_card(struct pccbb_softc *sc) 1486 { 1487 bus_space_handle_t base_memh = sc->sc_base_memh; 1488 bus_space_tag_t base_memt = sc->sc_base_memt; 1489 u_int32_t sockstat = 1490 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1491 int retval = 0; 1492 1493 /* CD1 and CD2 asserted */ 1494 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1495 /* card must be present */ 1496 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1497 /* NOTACARD DEASSERTED */ 1498 if (CB_SOCKET_STAT_CB & sockstat) { 1499 /* CardBus mode */ 1500 retval = 2; 1501 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1502 /* 16-bit mode */ 1503 retval = 1; 1504 } 1505 } 1506 } 1507 return retval; 1508 } 1509 1510 /* 1511 * STATIC int cb_reset(struct pccbb_softc *sc) 1512 * This function resets CardBus card. 1513 */ 1514 STATIC int 1515 cb_reset(struct pccbb_softc *sc) 1516 { 1517 /* 1518 * Reset Assert at least 20 ms 1519 * Some machines request longer duration. 1520 */ 1521 int reset_duration = 1522 (sc->sc_chipset == CB_RX5C47X ? 400 : 50); 1523 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1524 1525 /* Reset bit Assert (bit 6 at 0x3E) */ 1526 bcr |= CB_BCR_RESET_ENABLE; 1527 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr); 1528 delay_ms(reset_duration, sc); 1529 1530 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1531 /* Reset bit Deassert (bit 6 at 0x3E) */ 1532 bcr &= ~CB_BCR_RESET_ENABLE; 1533 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr); 1534 delay_ms(reset_duration, sc); 1535 } 1536 /* No card found on the slot. Keep Reset. */ 1537 return 1; 1538 } 1539 1540 /* 1541 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1542 * This function detect card Voltage. 1543 */ 1544 STATIC int 1545 cb_detect_voltage(struct pccbb_softc *sc) 1546 { 1547 u_int32_t psr; /* socket present-state reg */ 1548 bus_space_tag_t iot = sc->sc_base_memt; 1549 bus_space_handle_t ioh = sc->sc_base_memh; 1550 int vol = PCCARD_VCC_UKN; /* set 0 */ 1551 1552 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1553 1554 if (0x400u & psr) { 1555 vol |= PCCARD_VCC_5V; 1556 } 1557 if (0x800u & psr) { 1558 vol |= PCCARD_VCC_3V; 1559 } 1560 1561 return vol; 1562 } 1563 1564 STATIC int 1565 cbbprint(void *aux, const char *pcic) 1566 { 1567 #if 0 1568 struct cbslot_attach_args *cba = aux; 1569 1570 if (cba->cba_slot >= 0) { 1571 aprint_normal(" slot %d", cba->cba_slot); 1572 } 1573 #endif 1574 return UNCONF; 1575 } 1576 1577 /* 1578 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1579 * This function enables and disables the card 1580 */ 1581 STATIC int 1582 pccbb_cardenable(struct pccbb_softc *sc, int function) 1583 { 1584 u_int32_t command = 1585 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1586 1587 DPRINTF(("pccbb_cardenable:")); 1588 switch (function) { 1589 case CARDBUS_IO_ENABLE: 1590 command |= PCI_COMMAND_IO_ENABLE; 1591 break; 1592 case CARDBUS_IO_DISABLE: 1593 command &= ~PCI_COMMAND_IO_ENABLE; 1594 break; 1595 case CARDBUS_MEM_ENABLE: 1596 command |= PCI_COMMAND_MEM_ENABLE; 1597 break; 1598 case CARDBUS_MEM_DISABLE: 1599 command &= ~PCI_COMMAND_MEM_ENABLE; 1600 break; 1601 case CARDBUS_BM_ENABLE: 1602 command |= PCI_COMMAND_MASTER_ENABLE; 1603 break; 1604 case CARDBUS_BM_DISABLE: 1605 command &= ~PCI_COMMAND_MASTER_ENABLE; 1606 break; 1607 default: 1608 return 0; 1609 } 1610 1611 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1612 DPRINTF((" command reg 0x%x\n", command)); 1613 return 1; 1614 } 1615 1616 #if !rbus 1617 static int 1618 pccbb_io_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 1619 { 1620 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1621 int basereg; 1622 int limitreg; 1623 1624 if ((win < 0) || (win > 2)) { 1625 #if defined DIAGNOSTIC 1626 printf("cardbus_io_open: window out of range %d\n", win); 1627 #endif 1628 return 0; 1629 } 1630 1631 basereg = win * 8 + 0x2c; 1632 limitreg = win * 8 + 0x30; 1633 1634 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1635 start, basereg, end, limitreg)); 1636 1637 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1638 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1639 return 1; 1640 } 1641 1642 /* 1643 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1644 */ 1645 static int 1646 pccbb_io_close(cardbus_chipset_tag_t ct, int win) 1647 { 1648 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1649 int basereg; 1650 int limitreg; 1651 1652 if ((win < 0) || (win > 2)) { 1653 #if defined DIAGNOSTIC 1654 printf("cardbus_io_close: window out of range %d\n", win); 1655 #endif 1656 return 0; 1657 } 1658 1659 basereg = win * 8 + 0x2c; 1660 limitreg = win * 8 + 0x30; 1661 1662 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1663 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1664 return 1; 1665 } 1666 1667 static int 1668 pccbb_mem_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 1669 { 1670 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1671 int basereg; 1672 int limitreg; 1673 1674 if ((win < 0) || (win > 2)) { 1675 #if defined DIAGNOSTIC 1676 printf("cardbus_mem_open: window out of range %d\n", win); 1677 #endif 1678 return 0; 1679 } 1680 1681 basereg = win * 8 + 0x1c; 1682 limitreg = win * 8 + 0x20; 1683 1684 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1685 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1686 return 1; 1687 } 1688 1689 static int 1690 pccbb_mem_close(cardbus_chipset_tag_t ct, int win) 1691 { 1692 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1693 int basereg; 1694 int limitreg; 1695 1696 if ((win < 0) || (win > 2)) { 1697 #if defined DIAGNOSTIC 1698 printf("cardbus_mem_close: window out of range %d\n", win); 1699 #endif 1700 return 0; 1701 } 1702 1703 basereg = win * 8 + 0x1c; 1704 limitreg = win * 8 + 0x20; 1705 1706 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1707 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1708 return 1; 1709 } 1710 #endif 1711 1712 /* 1713 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1714 * int irq, 1715 * int level, 1716 * int (* func)(void *), 1717 * void *arg) 1718 * 1719 * This function registers an interrupt handler at the bridge, in 1720 * order not to call the interrupt handlers of child devices when 1721 * a card-deletion interrupt occurs. 1722 * 1723 * The arguments irq and level are not used. 1724 */ 1725 static void * 1726 pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, int irq, int level, 1727 int (*func)(void *), void *arg) 1728 { 1729 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1730 1731 return pccbb_intr_establish(sc, irq, level, func, arg); 1732 } 1733 1734 1735 /* 1736 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1737 * void *ih) 1738 * 1739 * This function removes an interrupt handler pointed by ih. 1740 */ 1741 static void 1742 pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih) 1743 { 1744 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1745 1746 pccbb_intr_disestablish(sc, ih); 1747 } 1748 1749 1750 void 1751 pccbb_intr_route(struct pccbb_softc *sc) 1752 { 1753 pcireg_t bcr, cbctrl; 1754 1755 /* initialize bridge intr routing */ 1756 bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1757 bcr &= ~CB_BCR_INTR_IREQ_ENABLE; 1758 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr); 1759 1760 switch (sc->sc_chipset) { 1761 case CB_TI113X: 1762 cbctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1763 /* functional intr enabled */ 1764 cbctrl |= PCI113X_CBCTRL_PCI_INTR; 1765 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, cbctrl); 1766 break; 1767 default: 1768 break; 1769 } 1770 } 1771 1772 /* 1773 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1774 * int irq, 1775 * int level, 1776 * int (* func)(void *), 1777 * void *arg) 1778 * 1779 * This function registers an interrupt handler at the bridge, in 1780 * order not to call the interrupt handlers of child devices when 1781 * a card-deletion interrupt occurs. 1782 * 1783 * The arguments irq is not used because pccbb selects intr vector. 1784 */ 1785 static void * 1786 pccbb_intr_establish(struct pccbb_softc *sc, int irq, int level, 1787 int (*func)(void *), void *arg) 1788 { 1789 struct pccbb_intrhand_list *pil, *newpil; 1790 1791 DPRINTF(("pccbb_intr_establish start. %p\n", LIST_FIRST(&sc->sc_pil))); 1792 1793 if (LIST_EMPTY(&sc->sc_pil)) { 1794 pccbb_intr_route(sc); 1795 } 1796 1797 /* 1798 * Allocate a room for interrupt handler structure. 1799 */ 1800 if (NULL == (newpil = 1801 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1802 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1803 return NULL; 1804 } 1805 1806 newpil->pil_func = func; 1807 newpil->pil_arg = arg; 1808 newpil->pil_icookie = makeiplcookie(level); 1809 1810 if (LIST_EMPTY(&sc->sc_pil)) { 1811 LIST_INSERT_HEAD(&sc->sc_pil, newpil, pil_next); 1812 } else { 1813 for (pil = LIST_FIRST(&sc->sc_pil); 1814 LIST_NEXT(pil, pil_next) != NULL; 1815 pil = LIST_NEXT(pil, pil_next)); 1816 LIST_INSERT_AFTER(pil, newpil, pil_next); 1817 } 1818 1819 DPRINTF(("pccbb_intr_establish add pil. %p\n", 1820 LIST_FIRST(&sc->sc_pil))); 1821 1822 return newpil; 1823 } 1824 1825 /* 1826 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1827 * void *ih) 1828 * 1829 * This function removes an interrupt handler pointed by ih. ih 1830 * should be the value returned by cardbus_intr_establish() or 1831 * NULL. 1832 * 1833 * When ih is NULL, this function will do nothing. 1834 */ 1835 static void 1836 pccbb_intr_disestablish(struct pccbb_softc *sc, void *ih) 1837 { 1838 struct pccbb_intrhand_list *pil; 1839 pcireg_t reg; 1840 1841 DPRINTF(("pccbb_intr_disestablish start. %p\n", 1842 LIST_FIRST(&sc->sc_pil))); 1843 1844 if (ih == NULL) { 1845 /* intr handler is not set */ 1846 DPRINTF(("pccbb_intr_disestablish: no ih\n")); 1847 return; 1848 } 1849 1850 #ifdef DIAGNOSTIC 1851 for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1852 pil = LIST_NEXT(pil, pil_next)) { 1853 DPRINTF(("pccbb_intr_disestablish: pil %p\n", pil)); 1854 if (pil == ih) { 1855 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1856 break; 1857 } 1858 } 1859 if (pil == NULL) { 1860 panic("pccbb_intr_disestablish: %s cannot find pil %p", 1861 sc->sc_dev.dv_xname, ih); 1862 } 1863 #endif 1864 1865 pil = (struct pccbb_intrhand_list *)ih; 1866 LIST_REMOVE(pil, pil_next); 1867 free(pil, M_DEVBUF); 1868 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1869 1870 if (LIST_EMPTY(&sc->sc_pil)) { 1871 /* No interrupt handlers */ 1872 1873 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1874 1875 /* stop routing PCI intr */ 1876 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1877 reg |= CB_BCR_INTR_IREQ_ENABLE; 1878 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, reg); 1879 1880 switch (sc->sc_chipset) { 1881 case CB_TI113X: 1882 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1883 /* functional intr disabled */ 1884 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1885 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1886 break; 1887 default: 1888 break; 1889 } 1890 } 1891 } 1892 1893 #if defined SHOW_REGS 1894 static void 1895 cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, bus_space_tag_t memt, 1896 bus_space_handle_t memh) 1897 { 1898 int i; 1899 printf("PCI config regs:"); 1900 for (i = 0; i < 0x50; i += 4) { 1901 if (i % 16 == 0) 1902 printf("\n 0x%02x:", i); 1903 printf(" %08x", pci_conf_read(pc, tag, i)); 1904 } 1905 for (i = 0x80; i < 0xb0; i += 4) { 1906 if (i % 16 == 0) 1907 printf("\n 0x%02x:", i); 1908 printf(" %08x", pci_conf_read(pc, tag, i)); 1909 } 1910 1911 if (memh == 0) { 1912 printf("\n"); 1913 return; 1914 } 1915 1916 printf("\nsocket regs:"); 1917 for (i = 0; i <= 0x10; i += 0x04) 1918 printf(" %08x", bus_space_read_4(memt, memh, i)); 1919 printf("\nExCA regs:"); 1920 for (i = 0; i < 0x08; ++i) 1921 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1922 printf("\n"); 1923 return; 1924 } 1925 #endif 1926 1927 /* 1928 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1929 * int busno, int function) 1930 * This is the function to make a tag to access config space of 1931 * a CardBus Card. It works same as pci_conf_read. 1932 */ 1933 static cardbustag_t 1934 pccbb_make_tag(cardbus_chipset_tag_t cc, int busno, int function) 1935 { 1936 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1937 1938 return pci_make_tag(sc->sc_pc, busno, 0, function); 1939 } 1940 1941 static void 1942 pccbb_free_tag(cardbus_chipset_tag_t cc, cardbustag_t tag) 1943 { 1944 } 1945 1946 /* 1947 * pccbb_conf_read 1948 * 1949 * This is the function to read the config space of a CardBus card. 1950 * It works the same as pci_conf_read(9). 1951 */ 1952 static cardbusreg_t 1953 pccbb_conf_read(cardbus_chipset_tag_t cc, cardbustag_t tag, int offset) 1954 { 1955 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1956 1957 return pci_conf_read(sc->sc_pc, tag, offset); 1958 } 1959 1960 /* 1961 * pccbb_conf_write 1962 * 1963 * This is the function to write the config space of a CardBus 1964 * card. It works the same as pci_conf_write(9). 1965 */ 1966 static void 1967 pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, int reg, 1968 cardbusreg_t val) 1969 { 1970 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1971 1972 pci_conf_write(sc->sc_pc, tag, reg, val); 1973 } 1974 1975 #if 0 1976 STATIC int 1977 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1978 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 1979 int speed, int flags, 1980 bus_space_handle_t * iohp) 1981 #endif 1982 /* 1983 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1984 * bus_addr_t start, bus_size_t size, 1985 * bus_size_t align, 1986 * struct pcmcia_io_handle *pcihp 1987 * 1988 * This function only allocates I/O region for pccard. This function 1989 * never maps the allocated region to pccard I/O area. 1990 * 1991 * XXX: The interface of this function is not very good, I believe. 1992 */ 1993 STATIC int 1994 pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, 1995 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 1996 { 1997 struct pcic_handle *ph = (struct pcic_handle *)pch; 1998 bus_addr_t ioaddr; 1999 int flags = 0; 2000 bus_space_tag_t iot; 2001 bus_space_handle_t ioh; 2002 bus_addr_t mask; 2003 #if rbus 2004 rbus_tag_t rb; 2005 #endif 2006 if (align == 0) { 2007 align = size; /* XXX: funny??? */ 2008 } 2009 2010 if (start != 0) { 2011 /* XXX: assume all card decode lower 10 bits by its hardware */ 2012 mask = 0x3ff; 2013 /* enforce to use only masked address */ 2014 start &= mask; 2015 } else { 2016 /* 2017 * calculate mask: 2018 * 1. get the most significant bit of size (call it msb). 2019 * 2. compare msb with the value of size. 2020 * 3. if size is larger, shift msb left once. 2021 * 4. obtain mask value to decrement msb. 2022 */ 2023 bus_size_t size_tmp = size; 2024 int shifts = 0; 2025 2026 mask = 1; 2027 while (size_tmp) { 2028 ++shifts; 2029 size_tmp >>= 1; 2030 } 2031 mask = (1 << shifts); 2032 if (mask < size) { 2033 mask <<= 1; 2034 } 2035 --mask; 2036 } 2037 2038 /* 2039 * Allocate some arbitrary I/O space. 2040 */ 2041 2042 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 2043 2044 #if rbus 2045 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 2046 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 2047 return 1; 2048 } 2049 DPRINTF(("pccbb_pcmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2050 (u_long) ioaddr, (u_long) size)); 2051 #else 2052 if (start) { 2053 ioaddr = start; 2054 if (bus_space_map(iot, start, size, 0, &ioh)) { 2055 return 1; 2056 } 2057 DPRINTF(("pccbb_pcmcia_io_alloc map port 0x%lx+0x%lx\n", 2058 (u_long) ioaddr, (u_long) size)); 2059 } else { 2060 flags |= PCMCIA_IO_ALLOCATED; 2061 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 2062 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 2063 size, align, 0, 0, &ioaddr, &ioh)) { 2064 /* No room be able to be get. */ 2065 return 1; 2066 } 2067 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2068 (u_long) ioaddr, (u_long) size)); 2069 } 2070 #endif 2071 2072 pcihp->iot = iot; 2073 pcihp->ioh = ioh; 2074 pcihp->addr = ioaddr; 2075 pcihp->size = size; 2076 pcihp->flags = flags; 2077 2078 return 0; 2079 } 2080 2081 /* 2082 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2083 * struct pcmcia_io_handle *pcihp) 2084 * 2085 * This function only frees I/O region for pccard. 2086 * 2087 * XXX: The interface of this function is not very good, I believe. 2088 */ 2089 void 2090 pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2091 struct pcmcia_io_handle *pcihp) 2092 { 2093 #if !rbus 2094 bus_space_tag_t iot = pcihp->iot; 2095 #endif 2096 bus_space_handle_t ioh = pcihp->ioh; 2097 bus_size_t size = pcihp->size; 2098 2099 #if rbus 2100 struct pccbb_softc *sc = 2101 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 2102 rbus_tag_t rb = sc->sc_rbus_iot; 2103 2104 rbus_space_free(rb, ioh, size, NULL); 2105 #else 2106 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 2107 bus_space_free(iot, ioh, size); 2108 else 2109 bus_space_unmap(iot, ioh, size); 2110 #endif 2111 } 2112 2113 /* 2114 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 2115 * bus_addr_t offset, bus_size_t size, 2116 * struct pcmcia_io_handle *pcihp, 2117 * int *windowp) 2118 * 2119 * This function maps the allocated I/O region to pccard. This function 2120 * never allocates any I/O region for pccard I/O area. I don't 2121 * understand why the original authors of pcmciabus separated alloc and 2122 * map. I believe the two must be unite. 2123 * 2124 * XXX: no wait timing control? 2125 */ 2126 int 2127 pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, bus_addr_t offset, 2128 bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp) 2129 { 2130 struct pcic_handle *ph = (struct pcic_handle *)pch; 2131 bus_addr_t ioaddr = pcihp->addr + offset; 2132 int i, win; 2133 #if defined CBB_DEBUG 2134 static const char *width_names[] = { "dynamic", "io8", "io16" }; 2135 #endif 2136 2137 /* Sanity check I/O handle. */ 2138 2139 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 2140 panic("pccbb_pcmcia_io_map iot is bogus"); 2141 } 2142 2143 /* XXX Sanity check offset/size. */ 2144 2145 win = -1; 2146 for (i = 0; i < PCIC_IO_WINS; i++) { 2147 if ((ph->ioalloc & (1 << i)) == 0) { 2148 win = i; 2149 ph->ioalloc |= (1 << i); 2150 break; 2151 } 2152 } 2153 2154 if (win == -1) { 2155 return 1; 2156 } 2157 2158 *windowp = win; 2159 2160 /* XXX this is pretty gross */ 2161 2162 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2163 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2164 2165 /* XXX wtf is this doing here? */ 2166 2167 #if 0 2168 printf(" port 0x%lx", (u_long) ioaddr); 2169 if (size > 1) { 2170 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2171 } 2172 #endif 2173 2174 ph->io[win].addr = ioaddr; 2175 ph->io[win].size = size; 2176 ph->io[win].width = width; 2177 2178 /* actual dirty register-value changing in the function below. */ 2179 pccbb_pcmcia_do_io_map(ph, win); 2180 2181 return 0; 2182 } 2183 2184 /* 2185 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2186 * 2187 * This function changes register-value to map I/O region for pccard. 2188 */ 2189 static void 2190 pccbb_pcmcia_do_io_map(struct pcic_handle *ph, int win) 2191 { 2192 static u_int8_t pcic_iowidth[3] = { 2193 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2194 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2195 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2196 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2197 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2198 }; 2199 2200 #define PCIC_SIA_START_LOW 0 2201 #define PCIC_SIA_START_HIGH 1 2202 #define PCIC_SIA_STOP_LOW 2 2203 #define PCIC_SIA_STOP_HIGH 3 2204 2205 int regbase_win = 0x8 + win * 0x04; 2206 u_int8_t ioctl, enable; 2207 2208 DPRINTF(("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx " 2209 "width %d\n", win, (unsigned long)ph->io[win].addr, 2210 (unsigned long)ph->io[win].size, ph->io[win].width * 8)); 2211 2212 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2213 ph->io[win].addr & 0xff); 2214 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2215 (ph->io[win].addr >> 8) & 0xff); 2216 2217 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2218 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2219 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2220 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2221 2222 ioctl = Pcic_read(ph, PCIC_IOCTL); 2223 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2224 switch (win) { 2225 case 0: 2226 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2227 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2228 PCIC_IOCTL_IO0_DATASIZE_MASK); 2229 ioctl |= pcic_iowidth[ph->io[win].width]; 2230 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2231 break; 2232 case 1: 2233 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2234 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2235 PCIC_IOCTL_IO1_DATASIZE_MASK); 2236 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2237 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2238 break; 2239 } 2240 Pcic_write(ph, PCIC_IOCTL, ioctl); 2241 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2242 #if defined(CBB_DEBUG) 2243 { 2244 u_int8_t start_low = 2245 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2246 u_int8_t start_high = 2247 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2248 u_int8_t stop_low = 2249 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2250 u_int8_t stop_high = 2251 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2252 printf("pccbb_pcmcia_do_io_map start %02x %02x, " 2253 "stop %02x %02x, ioctl %02x enable %02x\n", 2254 start_low, start_high, stop_low, stop_high, ioctl, enable); 2255 } 2256 #endif 2257 } 2258 2259 /* 2260 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2261 * 2262 * This function unmaps I/O region. No return value. 2263 */ 2264 STATIC void 2265 pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t pch, int win) 2266 { 2267 struct pcic_handle *ph = (struct pcic_handle *)pch; 2268 int reg; 2269 2270 if (win >= PCIC_IO_WINS || win < 0) { 2271 panic("pccbb_pcmcia_io_unmap: window out of range"); 2272 } 2273 2274 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2275 switch (win) { 2276 case 0: 2277 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2278 break; 2279 case 1: 2280 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2281 break; 2282 } 2283 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2284 2285 ph->ioalloc &= ~(1 << win); 2286 } 2287 2288 static int 2289 pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 2290 { 2291 u_int8_t stat; 2292 int i; 2293 2294 /* wait an initial 10ms for quick cards */ 2295 stat = Pcic_read(ph, PCIC_IF_STATUS); 2296 if (stat & PCIC_IF_STATUS_READY) 2297 return (0); 2298 pccbb_pcmcia_delay(ph, 10, "pccwr0"); 2299 for (i = 0; i < 50; i++) { 2300 stat = Pcic_read(ph, PCIC_IF_STATUS); 2301 if (stat & PCIC_IF_STATUS_READY) 2302 return (0); 2303 if ((stat & PCIC_IF_STATUS_CARDDETECT_MASK) != 2304 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2305 return (ENXIO); 2306 /* wait .1s (100ms) each iteration now */ 2307 pccbb_pcmcia_delay(ph, 100, "pccwr1"); 2308 } 2309 2310 printf("pccbb_pcmcia_wait_ready: ready never happened, status=%02x\n", stat); 2311 return (EWOULDBLOCK); 2312 } 2313 2314 /* 2315 * Perform long (msec order) delay. timo is in milliseconds. 2316 */ 2317 static void 2318 pccbb_pcmcia_delay(struct pcic_handle *ph, int timo, const char *wmesg) 2319 { 2320 #ifdef DIAGNOSTIC 2321 if (timo <= 0) 2322 panic("pccbb_pcmcia_delay: called with timeout %d", timo); 2323 if (!curlwp) 2324 panic("pccbb_pcmcia_delay: called in interrupt context"); 2325 #if 0 2326 if (!ph->event_thread) 2327 panic("pccbb_pcmcia_delay: no event thread"); 2328 #endif 2329 #endif 2330 DPRINTF(("pccbb_pcmcia_delay: \"%s\" %p, sleep %d ms\n", 2331 wmesg, ph->event_thread, timo)); 2332 tsleep(pccbb_pcmcia_delay, PWAIT, wmesg, roundup(timo * hz, 1000) / 1000); 2333 } 2334 2335 /* 2336 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2337 * 2338 * This function enables the card. All information is stored in 2339 * the first argument, pcmcia_chipset_handle_t. 2340 */ 2341 STATIC void 2342 pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2343 { 2344 struct pcic_handle *ph = (struct pcic_handle *)pch; 2345 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2346 pcireg_t spsr; 2347 int voltage; 2348 int win; 2349 u_int8_t power, intr; 2350 #ifdef DIAGNOSTIC 2351 int reg; 2352 #endif 2353 2354 /* this bit is mostly stolen from pcic_attach_card */ 2355 2356 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2357 2358 /* get card Vcc info */ 2359 spsr = 2360 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2361 CB_SOCKET_STAT); 2362 if (spsr & CB_SOCKET_STAT_5VCARD) { 2363 DPRINTF(("5V card\n")); 2364 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2365 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2366 DPRINTF(("3V card\n")); 2367 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2368 } else { 2369 DPRINTF(("?V card, 0x%x\n", spsr)); /* XXX */ 2370 return; 2371 } 2372 2373 /* disable interrupts; assert RESET */ 2374 intr = Pcic_read(ph, PCIC_INTR); 2375 intr &= PCIC_INTR_ENABLE; 2376 Pcic_write(ph, PCIC_INTR, intr); 2377 2378 /* zero out the address windows */ 2379 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2380 2381 /* power down the socket to reset it, clear the card reset pin */ 2382 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2383 2384 /* power off; assert output enable bit */ 2385 power = PCIC_PWRCTL_OE; 2386 Pcic_write(ph, PCIC_PWRCTL, power); 2387 2388 /* power up the socket */ 2389 if (pccbb_power(sc, voltage) == 0) 2390 return; 2391 2392 /* 2393 * Table 4-18 and figure 4-6 of the PC Card specifiction say: 2394 * Vcc Rising Time (Tpr) = 100ms (handled in pccbb_power() above) 2395 * RESET Width (Th (Hi-z RESET)) = 1ms 2396 * RESET Width (Tw (RESET)) = 10us 2397 * 2398 * some machines require some more time to be settled 2399 * for example old toshiba topic bridges! 2400 * (100ms is added here). 2401 */ 2402 pccbb_pcmcia_delay(ph, 200 + 1, "pccen1"); 2403 2404 /* negate RESET */ 2405 intr |= PCIC_INTR_RESET; 2406 Pcic_write(ph, PCIC_INTR, intr); 2407 2408 /* 2409 * RESET Setup Time (Tsu (RESET)) = 20ms 2410 */ 2411 pccbb_pcmcia_delay(ph, 20, "pccen2"); 2412 2413 #ifdef DIAGNOSTIC 2414 reg = Pcic_read(ph, PCIC_IF_STATUS); 2415 if ((reg & PCIC_IF_STATUS_POWERACTIVE) == 0) 2416 printf("pccbb_pcmcia_socket_enable: no power, status=%x\n", reg); 2417 #endif 2418 2419 /* wait for the chip to finish initializing */ 2420 if (pccbb_pcmcia_wait_ready(ph)) { 2421 #ifdef DIAGNOSTIC 2422 printf("pccbb_pcmcia_socket_enable: never became ready\n"); 2423 #endif 2424 /* XXX return a failure status?? */ 2425 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2426 Pcic_write(ph, PCIC_PWRCTL, 0); 2427 return; 2428 } 2429 2430 /* reinstall all the memory and io mappings */ 2431 for (win = 0; win < PCIC_MEM_WINS; ++win) 2432 if (ph->memalloc & (1 << win)) 2433 pccbb_pcmcia_do_mem_map(ph, win); 2434 for (win = 0; win < PCIC_IO_WINS; ++win) 2435 if (ph->ioalloc & (1 << win)) 2436 pccbb_pcmcia_do_io_map(ph, win); 2437 } 2438 2439 /* 2440 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2441 * 2442 * This function disables the card. All information is stored in 2443 * the first argument, pcmcia_chipset_handle_t. 2444 */ 2445 STATIC void 2446 pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t pch) 2447 { 2448 struct pcic_handle *ph = (struct pcic_handle *)pch; 2449 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2450 u_int8_t intr; 2451 2452 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2453 2454 /* disable interrupts; assert RESET */ 2455 intr = Pcic_read(ph, PCIC_INTR); 2456 intr &= PCIC_INTR_ENABLE; 2457 Pcic_write(ph, PCIC_INTR, intr); 2458 2459 /* zero out the address windows */ 2460 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2461 2462 /* power down the socket to reset it, clear the card reset pin */ 2463 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2464 2465 /* disable socket: negate output enable bit and power off */ 2466 Pcic_write(ph, PCIC_PWRCTL, 0); 2467 2468 /* 2469 * Vcc Falling Time (Tpf) = 300ms 2470 */ 2471 pccbb_pcmcia_delay(ph, 300, "pccwr1"); 2472 } 2473 2474 STATIC void 2475 pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t pch, int type) 2476 { 2477 struct pcic_handle *ph = (struct pcic_handle *)pch; 2478 u_int8_t intr; 2479 2480 /* set the card type */ 2481 2482 intr = Pcic_read(ph, PCIC_INTR); 2483 intr &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_CARDTYPE_MASK); 2484 if (type == PCMCIA_IFTYPE_IO) 2485 intr |= PCIC_INTR_CARDTYPE_IO; 2486 else 2487 intr |= PCIC_INTR_CARDTYPE_MEM; 2488 Pcic_write(ph, PCIC_INTR, intr); 2489 2490 DPRINTF(("%s: pccbb_pcmcia_socket_settype %02x type %s %02x\n", 2491 ph->ph_parent->dv_xname, ph->sock, 2492 ((type == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2493 } 2494 2495 /* 2496 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2497 * 2498 * This function detects whether a card is in the slot or not. 2499 * If a card is inserted, return 1. Otherwise, return 0. 2500 */ 2501 STATIC int 2502 pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch) 2503 { 2504 struct pcic_handle *ph = (struct pcic_handle *)pch; 2505 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2506 2507 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2508 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2509 } 2510 2511 #if 0 2512 STATIC int 2513 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2514 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2515 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2516 #endif 2517 /* 2518 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2519 * bus_size_t size, 2520 * struct pcmcia_mem_handle *pcmhp) 2521 * 2522 * This function only allocates memory region for pccard. This 2523 * function never maps the allocated region to pccard memory area. 2524 * 2525 * XXX: Why the argument of start address is not in? 2526 */ 2527 STATIC int 2528 pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 2529 struct pcmcia_mem_handle *pcmhp) 2530 { 2531 struct pcic_handle *ph = (struct pcic_handle *)pch; 2532 bus_space_handle_t memh; 2533 bus_addr_t addr; 2534 bus_size_t sizepg; 2535 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2536 #if rbus 2537 rbus_tag_t rb; 2538 #endif 2539 2540 /* Check that the card is still there. */ 2541 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2542 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2543 return 1; 2544 2545 /* out of sc->memh, allocate as many pages as necessary */ 2546 2547 /* convert size to PCIC pages */ 2548 /* 2549 * This is not enough; when the requested region is on the page 2550 * boundaries, this may calculate wrong result. 2551 */ 2552 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2553 #if 0 2554 if (sizepg > PCIC_MAX_MEM_PAGES) { 2555 return 1; 2556 } 2557 #endif 2558 2559 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2560 return 1; 2561 } 2562 2563 addr = 0; /* XXX gcc -Wuninitialized */ 2564 2565 #if rbus 2566 rb = sc->sc_rbus_memt; 2567 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2568 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2569 &addr, &memh)) { 2570 return 1; 2571 } 2572 #else 2573 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2574 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2575 0, /* boundary */ 2576 0, /* flags */ 2577 &addr, &memh)) { 2578 return 1; 2579 } 2580 #endif 2581 2582 DPRINTF(("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, " 2583 "realsize 0x%lx\n", (unsigned long)addr, (unsigned long)size, 2584 (unsigned long)sizepg * PCIC_MEM_PAGESIZE)); 2585 2586 pcmhp->memt = sc->sc_memt; 2587 pcmhp->memh = memh; 2588 pcmhp->addr = addr; 2589 pcmhp->size = size; 2590 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2591 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2592 pcmhp->mhandle = 0; 2593 /* No offset??? Funny. */ 2594 2595 return 0; 2596 } 2597 2598 /* 2599 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2600 * struct pcmcia_mem_handle *pcmhp) 2601 * 2602 * This function release the memory space allocated by the function 2603 * pccbb_pcmcia_mem_alloc(). 2604 */ 2605 STATIC void 2606 pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2607 struct pcmcia_mem_handle *pcmhp) 2608 { 2609 #if rbus 2610 struct pcic_handle *ph = (struct pcic_handle *)pch; 2611 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2612 2613 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2614 #else 2615 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2616 #endif 2617 } 2618 2619 /* 2620 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2621 * 2622 * This function release the memory space allocated by the function 2623 * pccbb_pcmcia_mem_alloc(). 2624 */ 2625 STATIC void 2626 pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2627 { 2628 int regbase_win; 2629 bus_addr_t phys_addr; 2630 bus_addr_t phys_end; 2631 2632 #define PCIC_SMM_START_LOW 0 2633 #define PCIC_SMM_START_HIGH 1 2634 #define PCIC_SMM_STOP_LOW 2 2635 #define PCIC_SMM_STOP_HIGH 3 2636 #define PCIC_CMA_LOW 4 2637 #define PCIC_CMA_HIGH 5 2638 2639 u_int8_t start_low, start_high = 0; 2640 u_int8_t stop_low, stop_high; 2641 u_int8_t off_low, off_high; 2642 u_int8_t mem_window; 2643 int reg; 2644 2645 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2646 int mem8 = 2647 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2648 || (kind == PCMCIA_MEM_ATTR); 2649 2650 regbase_win = 0x10 + win * 0x08; 2651 2652 phys_addr = ph->mem[win].addr; 2653 phys_end = phys_addr + ph->mem[win].size; 2654 2655 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2656 (unsigned long)phys_addr, (unsigned long)phys_end, 2657 (unsigned long)ph->mem[win].offset)); 2658 2659 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2660 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2661 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2662 2663 /* bit 19:12 */ 2664 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2665 /* bit 23:20 and bit 7 on */ 2666 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2667 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2668 /* bit 31:24, for 32-bit address */ 2669 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2670 2671 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2672 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2673 2674 if (((struct pccbb_softc *)ph-> 2675 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2676 Pcic_write(ph, 0x40 + win, mem_window); 2677 } 2678 2679 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2680 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2681 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2682 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2683 2684 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2685 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2686 2687 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2688 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2689 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2690 | ((kind == PCMCIA_MEM_ATTR) ? 2691 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2692 2693 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2694 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2695 2696 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2697 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2698 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2699 2700 #if defined(CBB_DEBUG) 2701 { 2702 int r1, r2, r3, r4, r5, r6, r7 = 0; 2703 2704 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2705 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2706 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2707 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2708 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2709 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2710 if (((struct pccbb_softc *)(ph-> 2711 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2712 r7 = Pcic_read(ph, 0x40 + win); 2713 } 2714 2715 printf("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2716 "%02x%02x", win, r1, r2, r3, r4, r5, r6); 2717 if (((struct pccbb_softc *)(ph-> 2718 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2719 printf(" %02x", r7); 2720 } 2721 printf("\n"); 2722 } 2723 #endif 2724 } 2725 2726 /* 2727 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2728 * bus_addr_t card_addr, bus_size_t size, 2729 * struct pcmcia_mem_handle *pcmhp, 2730 * bus_addr_t *offsetp, int *windowp) 2731 * 2732 * This function maps memory space allocated by the function 2733 * pccbb_pcmcia_mem_alloc(). 2734 */ 2735 STATIC int 2736 pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2737 bus_addr_t card_addr, bus_size_t size, struct pcmcia_mem_handle *pcmhp, 2738 bus_addr_t *offsetp, int *windowp) 2739 { 2740 struct pcic_handle *ph = (struct pcic_handle *)pch; 2741 bus_addr_t busaddr; 2742 long card_offset; 2743 int win; 2744 2745 /* Check that the card is still there. */ 2746 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2747 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2748 return 1; 2749 2750 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2751 if ((ph->memalloc & (1 << win)) == 0) { 2752 ph->memalloc |= (1 << win); 2753 break; 2754 } 2755 } 2756 2757 if (win == PCIC_MEM_WINS) { 2758 return 1; 2759 } 2760 2761 *windowp = win; 2762 2763 /* XXX this is pretty gross */ 2764 2765 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2766 panic("pccbb_pcmcia_mem_map memt is bogus"); 2767 } 2768 2769 busaddr = pcmhp->addr; 2770 2771 /* 2772 * compute the address offset to the pcmcia address space for the 2773 * pcic. this is intentionally signed. The masks and shifts below 2774 * will cause TRT to happen in the pcic registers. Deal with making 2775 * sure the address is aligned, and return the alignment offset. 2776 */ 2777 2778 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2779 card_addr -= *offsetp; 2780 2781 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2782 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2783 (u_long) card_addr)); 2784 2785 /* 2786 * include the offset in the size, and decrement size by one, since 2787 * the hw wants start/stop 2788 */ 2789 size += *offsetp - 1; 2790 2791 card_offset = (((long)card_addr) - ((long)busaddr)); 2792 2793 ph->mem[win].addr = busaddr; 2794 ph->mem[win].size = size; 2795 ph->mem[win].offset = card_offset; 2796 ph->mem[win].kind = kind; 2797 2798 pccbb_pcmcia_do_mem_map(ph, win); 2799 2800 return 0; 2801 } 2802 2803 /* 2804 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2805 * int window) 2806 * 2807 * This function unmaps memory space which mapped by the function 2808 * pccbb_pcmcia_mem_map(). 2809 */ 2810 STATIC void 2811 pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, int window) 2812 { 2813 struct pcic_handle *ph = (struct pcic_handle *)pch; 2814 int reg; 2815 2816 if (window >= PCIC_MEM_WINS) { 2817 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2818 } 2819 2820 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2821 reg &= ~(1 << window); 2822 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2823 2824 ph->memalloc &= ~(1 << window); 2825 } 2826 2827 #if defined PCCBB_PCMCIA_POLL 2828 struct pccbb_poll_str { 2829 void *arg; 2830 int (*func)(void *); 2831 int level; 2832 struct pcic_handle *ph; 2833 int count; 2834 int num; 2835 struct callout poll_ch; 2836 }; 2837 2838 static struct pccbb_poll_str pccbb_poll[10]; 2839 static int pccbb_poll_n = 0; 2840 2841 static void pccbb_pcmcia_poll(void *arg); 2842 2843 static void 2844 pccbb_pcmcia_poll(void *arg) 2845 { 2846 struct pccbb_poll_str *poll = arg; 2847 struct pcic_handle *ph = poll->ph; 2848 struct pccbb_softc *sc = ph->sc; 2849 int s; 2850 u_int32_t spsr; /* socket present-state reg */ 2851 2852 callout_reset(&poll->poll_ch, hz * 2, pccbb_pcmcia_poll, arg); 2853 switch (poll->level) { 2854 case IPL_NET: 2855 s = splnet(); 2856 break; 2857 case IPL_BIO: 2858 s = splbio(); 2859 break; 2860 case IPL_TTY: /* fallthrough */ 2861 default: 2862 s = spltty(); 2863 break; 2864 } 2865 2866 spsr = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2867 CB_SOCKET_STAT); 2868 2869 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2870 if (!(spsr & 0x40)) /* CINT low */ 2871 #else 2872 if (1) 2873 #endif 2874 { 2875 if ((*poll->func) (poll->arg) > 0) { 2876 ++poll->count; 2877 /* printf("intr: reported from poller, 0x%x\n", spsr); */ 2878 #if defined LEVEL2 2879 } else { 2880 printf("intr: miss! 0x%x\n", spsr); 2881 #endif 2882 } 2883 } 2884 splx(s); 2885 } 2886 #endif /* defined CB_PCMCIA_POLL */ 2887 2888 /* 2889 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2890 * struct pcmcia_function *pf, 2891 * int ipl, 2892 * int (*func)(void *), 2893 * void *arg); 2894 * 2895 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2896 */ 2897 STATIC void * 2898 pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2899 struct pcmcia_function *pf, int ipl, int (*func)(void *), void *arg) 2900 { 2901 struct pcic_handle *ph = (struct pcic_handle *)pch; 2902 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2903 2904 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2905 /* what should I do? */ 2906 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2907 DPRINTF(("%s does not provide edge nor pulse " 2908 "interrupt\n", sc->sc_dev.dv_xname)); 2909 return NULL; 2910 } 2911 /* 2912 * XXX Noooooo! The interrupt flag must set properly!! 2913 * dumb pcmcia driver!! 2914 */ 2915 } 2916 2917 return pccbb_intr_establish(sc, 0, ipl, func, arg); 2918 } 2919 2920 /* 2921 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2922 * void *ih) 2923 * 2924 * This function disables PC-Card interrupt. 2925 */ 2926 STATIC void 2927 pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 2928 { 2929 struct pcic_handle *ph = (struct pcic_handle *)pch; 2930 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2931 2932 pccbb_intr_disestablish(sc, ih); 2933 } 2934 2935 #if rbus 2936 /* 2937 * static int 2938 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2939 * bus_addr_t addr, bus_size_t size, 2940 * bus_addr_t mask, bus_size_t align, 2941 * int flags, bus_addr_t *addrp; 2942 * bus_space_handle_t *bshp) 2943 * 2944 * This function allocates a portion of memory or io space for 2945 * clients. This function is called from CardBus card drivers. 2946 */ 2947 static int 2948 pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2949 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 2950 int flags, bus_addr_t *addrp, bus_space_handle_t *bshp) 2951 { 2952 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2953 2954 DPRINTF(("pccbb_rbus_cb_space_alloc: addr 0x%lx, size 0x%lx, " 2955 "mask 0x%lx, align 0x%lx\n", (unsigned long)addr, 2956 (unsigned long)size, (unsigned long)mask, (unsigned long)align)); 2957 2958 if (align == 0) { 2959 align = size; 2960 } 2961 2962 if (rb->rb_bt == sc->sc_memt) { 2963 if (align < 16) { 2964 return 1; 2965 } 2966 /* 2967 * XXX: align more than 0x1000 to avoid overwrapping 2968 * memory windows for two or more devices. 0x1000 2969 * means memory window's granularity. 2970 * 2971 * Two or more devices should be able to share same 2972 * memory window region. However, overrapping memory 2973 * window is not good because some devices, such as 2974 * 3Com 3C575[BC], have a broken address decoder and 2975 * intrude other's memory region. 2976 */ 2977 if (align < 0x1000) { 2978 align = 0x1000; 2979 } 2980 } else if (rb->rb_bt == sc->sc_iot) { 2981 if (align < 4) { 2982 return 1; 2983 } 2984 /* XXX: hack for avoiding ISA image */ 2985 if (mask < 0x0100) { 2986 mask = 0x3ff; 2987 addr = 0x300; 2988 } 2989 2990 } else { 2991 DPRINTF(("pccbb_rbus_cb_space_alloc: Bus space tag 0x%lx is " 2992 "NOT used. io: 0x%lx, mem: 0x%lx\n", 2993 (unsigned long)rb->rb_bt, (unsigned long)sc->sc_iot, 2994 (unsigned long)sc->sc_memt)); 2995 return 1; 2996 /* XXX: panic here? */ 2997 } 2998 2999 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 3000 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 3001 return 1; 3002 } 3003 3004 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 3005 3006 return 0; 3007 } 3008 3009 /* 3010 * static int 3011 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 3012 * bus_space_handle_t *bshp, bus_size_t size); 3013 * 3014 * This function is called from CardBus card drivers. 3015 */ 3016 static int 3017 pccbb_rbus_cb_space_free(cardbus_chipset_tag_t ct, rbus_tag_t rb, 3018 bus_space_handle_t bsh, bus_size_t size) 3019 { 3020 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 3021 bus_space_tag_t bt = rb->rb_bt; 3022 3023 pccbb_close_win(sc, bt, bsh, size); 3024 3025 if (bt == sc->sc_memt) { 3026 } else if (bt == sc->sc_iot) { 3027 } else { 3028 return 1; 3029 /* XXX: panic here? */ 3030 } 3031 3032 return rbus_space_free(rb, bsh, size, NULL); 3033 } 3034 #endif /* rbus */ 3035 3036 #if rbus 3037 3038 static int 3039 pccbb_open_win(struct pccbb_softc *sc, bus_space_tag_t bst, bus_addr_t addr, 3040 bus_size_t size, bus_space_handle_t bsh, int flags) 3041 { 3042 struct pccbb_win_chain_head *head; 3043 bus_addr_t align; 3044 3045 head = &sc->sc_iowindow; 3046 align = 0x04; 3047 if (sc->sc_memt == bst) { 3048 head = &sc->sc_memwindow; 3049 align = 0x1000; 3050 DPRINTF(("using memory window, 0x%lx 0x%lx 0x%lx\n\n", 3051 (unsigned long)sc->sc_iot, (unsigned long)sc->sc_memt, 3052 (unsigned long)bst)); 3053 } 3054 3055 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 3056 printf("%s: pccbb_open_win: %s winlist insert failed\n", 3057 sc->sc_dev.dv_xname, 3058 (head == &sc->sc_memwindow) ? "mem" : "io"); 3059 } 3060 pccbb_winset(align, sc, bst); 3061 3062 return 0; 3063 } 3064 3065 static int 3066 pccbb_close_win(struct pccbb_softc *sc, bus_space_tag_t bst, 3067 bus_space_handle_t bsh, bus_size_t size) 3068 { 3069 struct pccbb_win_chain_head *head; 3070 bus_addr_t align; 3071 3072 head = &sc->sc_iowindow; 3073 align = 0x04; 3074 if (sc->sc_memt == bst) { 3075 head = &sc->sc_memwindow; 3076 align = 0x1000; 3077 } 3078 3079 if (pccbb_winlist_delete(head, bsh, size)) { 3080 printf("%s: pccbb_close_win: %s winlist delete failed\n", 3081 sc->sc_dev.dv_xname, 3082 (head == &sc->sc_memwindow) ? "mem" : "io"); 3083 } 3084 pccbb_winset(align, sc, bst); 3085 3086 return 0; 3087 } 3088 3089 static int 3090 pccbb_winlist_insert(struct pccbb_win_chain_head *head, bus_addr_t start, 3091 bus_size_t size, bus_space_handle_t bsh, int flags) 3092 { 3093 struct pccbb_win_chain *chainp, *elem; 3094 3095 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 3096 M_NOWAIT)) == NULL) 3097 return (1); /* fail */ 3098 3099 elem->wc_start = start; 3100 elem->wc_end = start + (size - 1); 3101 elem->wc_handle = bsh; 3102 elem->wc_flags = flags; 3103 3104 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3105 chainp = TAILQ_NEXT(chainp, wc_list)) { 3106 if (chainp->wc_end < start) 3107 continue; 3108 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 3109 return (0); 3110 } 3111 3112 TAILQ_INSERT_TAIL(head, elem, wc_list); 3113 return (0); 3114 } 3115 3116 static int 3117 pccbb_winlist_delete(struct pccbb_win_chain_head *head, bus_space_handle_t bsh, 3118 bus_size_t size) 3119 { 3120 struct pccbb_win_chain *chainp; 3121 3122 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3123 chainp = TAILQ_NEXT(chainp, wc_list)) { 3124 if (memcmp(&chainp->wc_handle, &bsh, sizeof(bsh))) 3125 continue; 3126 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 3127 printf("pccbb_winlist_delete: window 0x%lx size " 3128 "inconsistent: 0x%lx, 0x%lx\n", 3129 (unsigned long)chainp->wc_start, 3130 (unsigned long)(chainp->wc_end - chainp->wc_start), 3131 (unsigned long)(size - 1)); 3132 return 1; 3133 } 3134 3135 TAILQ_REMOVE(head, chainp, wc_list); 3136 free(chainp, M_DEVBUF); 3137 3138 return 0; 3139 } 3140 3141 return 1; /* fail: no candidate to remove */ 3142 } 3143 3144 static void 3145 pccbb_winset(bus_addr_t align, struct pccbb_softc *sc, bus_space_tag_t bst) 3146 { 3147 pci_chipset_tag_t pc; 3148 pcitag_t tag; 3149 bus_addr_t mask = ~(align - 1); 3150 struct { 3151 cardbusreg_t win_start; 3152 cardbusreg_t win_limit; 3153 int win_flags; 3154 } win[2]; 3155 struct pccbb_win_chain *chainp; 3156 int offs; 3157 3158 win[0].win_start = win[1].win_start = 0xffffffff; 3159 win[0].win_limit = win[1].win_limit = 0; 3160 win[0].win_flags = win[1].win_flags = 0; 3161 3162 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3163 offs = 0x2c; 3164 if (sc->sc_memt == bst) { 3165 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3166 offs = 0x1c; 3167 } 3168 3169 if (chainp != NULL) { 3170 win[0].win_start = chainp->wc_start & mask; 3171 win[0].win_limit = chainp->wc_end & mask; 3172 win[0].win_flags = chainp->wc_flags; 3173 chainp = TAILQ_NEXT(chainp, wc_list); 3174 } 3175 3176 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3177 if (win[1].win_start == 0xffffffff) { 3178 /* window 1 is not used */ 3179 if ((win[0].win_flags == chainp->wc_flags) && 3180 (win[0].win_limit + align >= 3181 (chainp->wc_start & mask))) { 3182 /* concatenate */ 3183 win[0].win_limit = chainp->wc_end & mask; 3184 } else { 3185 /* make new window */ 3186 win[1].win_start = chainp->wc_start & mask; 3187 win[1].win_limit = chainp->wc_end & mask; 3188 win[1].win_flags = chainp->wc_flags; 3189 } 3190 continue; 3191 } 3192 3193 /* Both windows are engaged. */ 3194 if (win[0].win_flags == win[1].win_flags) { 3195 /* same flags */ 3196 if (win[0].win_flags == chainp->wc_flags) { 3197 if (win[1].win_start - (win[0].win_limit + 3198 align) < 3199 (chainp->wc_start & mask) - 3200 ((chainp->wc_end & mask) + align)) { 3201 /* 3202 * merge window 0 and 1, and set win1 3203 * to chainp 3204 */ 3205 win[0].win_limit = win[1].win_limit; 3206 win[1].win_start = 3207 chainp->wc_start & mask; 3208 win[1].win_limit = 3209 chainp->wc_end & mask; 3210 } else { 3211 win[1].win_limit = 3212 chainp->wc_end & mask; 3213 } 3214 } else { 3215 /* different flags */ 3216 3217 /* concatenate win0 and win1 */ 3218 win[0].win_limit = win[1].win_limit; 3219 /* allocate win[1] to new space */ 3220 win[1].win_start = chainp->wc_start & mask; 3221 win[1].win_limit = chainp->wc_end & mask; 3222 win[1].win_flags = chainp->wc_flags; 3223 } 3224 } else { 3225 /* the flags of win[0] and win[1] is different */ 3226 if (win[0].win_flags == chainp->wc_flags) { 3227 win[0].win_limit = chainp->wc_end & mask; 3228 /* 3229 * XXX this creates overlapping windows, so 3230 * what should the poor bridge do if one is 3231 * cachable, and the other is not? 3232 */ 3233 printf("%s: overlapping windows\n", 3234 sc->sc_dev.dv_xname); 3235 } else { 3236 win[1].win_limit = chainp->wc_end & mask; 3237 } 3238 } 3239 } 3240 3241 pc = sc->sc_pc; 3242 tag = sc->sc_tag; 3243 pci_conf_write(pc, tag, offs, win[0].win_start); 3244 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3245 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3246 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3247 DPRINTF(("--pccbb_winset: win0 [0x%lx, 0x%lx), win1 [0x%lx, 0x%lx)\n", 3248 (unsigned long)pci_conf_read(pc, tag, offs), 3249 (unsigned long)pci_conf_read(pc, tag, offs + 4) + align, 3250 (unsigned long)pci_conf_read(pc, tag, offs + 8), 3251 (unsigned long)pci_conf_read(pc, tag, offs + 12) + align)); 3252 3253 if (bst == sc->sc_memt) { 3254 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BRIDGE_CONTROL_REG); 3255 3256 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 3257 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 3258 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3259 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 3260 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3261 pci_conf_write(pc, tag, PCI_BRIDGE_CONTROL_REG, bcr); 3262 } 3263 } 3264 3265 #endif /* rbus */ 3266 3267 static void 3268 pccbb_powerhook(int why, void *arg) 3269 { 3270 struct pccbb_softc *sc = arg; 3271 pcireg_t reg; 3272 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3273 bus_space_handle_t base_memh = sc->sc_base_memh; 3274 3275 DPRINTF(("%s: power: why %d\n", sc->sc_dev.dv_xname, why)); 3276 3277 if (why == PWR_SUSPEND || why == PWR_STANDBY) { 3278 DPRINTF(("%s: power: why %d stopping intr\n", 3279 sc->sc_dev.dv_xname, why)); 3280 if (sc->sc_pil_intr_enable) { 3281 (void)pccbbintr_function(sc); 3282 } 3283 sc->sc_pil_intr_enable = 0; 3284 3285 pci_conf_capture(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf); 3286 3287 if (sc->sc_chipset == CB_RX5C47X) 3288 sc->sc_ricoh_misc_ctrl = pci_conf_read(sc->sc_pc, 3289 sc->sc_tag, 3290 RICOH_PCI_MISC_CTRL); 3291 3292 /* ToDo: deactivate or suspend child devices */ 3293 } 3294 3295 if (why == PWR_RESUME) { 3296 if (sc->sc_pwrmgt_offs != 0) { 3297 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, 3298 sc->sc_pwrmgt_offs + PCI_PMCSR); 3299 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 3300 reg & PCI_PMCSR_PME_EN) { 3301 /* powrstate != D0 */ 3302 3303 printf("%s going back to D0 mode\n", 3304 sc->sc_dev.dv_xname); 3305 reg &= ~PCI_PMCSR_STATE_MASK; 3306 reg |= PCI_PMCSR_STATE_D0; 3307 reg &= ~PCI_PMCSR_PME_EN; 3308 pci_conf_write(sc->sc_pc, sc->sc_tag, 3309 sc->sc_pwrmgt_offs + PCI_PMCSR, reg); 3310 3311 pci_conf_write(sc->sc_pc, sc->sc_tag, 3312 PCI_SOCKBASE, sc->sc_sockbase); 3313 pci_conf_write(sc->sc_pc, sc->sc_tag, 3314 PCI_BUSNUM, sc->sc_busnum); 3315 pccbb_chipinit(sc); 3316 /* setup memory and io space window for CB */ 3317 pccbb_winset(0x1000, sc, sc->sc_memt); 3318 pccbb_winset(0x04, sc, sc->sc_iot); 3319 goto norestore; 3320 } 3321 } 3322 3323 norestore: 3324 pci_conf_restore(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf); 3325 if (sc->sc_chipset == CB_RX5C47X) { 3326 pci_conf_write(sc->sc_pc, sc->sc_tag, 3327 RICOH_PCI_MISC_CTRL, sc->sc_ricoh_misc_ctrl); 3328 } 3329 3330 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_SOCKBASE) == 0) 3331 /* BIOS did not recover this register */ 3332 pci_conf_write (sc->sc_pc, sc->sc_tag, 3333 PCI_SOCKBASE, sc->sc_sockbase); 3334 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_BUSNUM) == 0) 3335 /* BIOS did not recover this register */ 3336 pci_conf_write (sc->sc_pc, sc->sc_tag, 3337 PCI_BUSNUM, sc->sc_busnum); 3338 /* CSC Interrupt: Card detect interrupt on */ 3339 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3340 /* Card detect intr is turned on. */ 3341 reg |= CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; 3342 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3343 /* reset interrupt */ 3344 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3345 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3346 3347 /* 3348 * check for card insertion or removal during suspend period. 3349 * XXX: the code can't cope with card swap (remove then 3350 * insert). how can we detect such situation? 3351 */ 3352 (void)pccbbintr(sc); 3353 3354 sc->sc_pil_intr_enable = 1; 3355 DPRINTF(("%s: power: RESUME enabling intr\n", 3356 sc->sc_dev.dv_xname)); 3357 3358 /* ToDo: activate or wakeup child devices */ 3359 } 3360 } 3361
Indexes created Fri Sep 26 20:09:58 GMT 2025