pccbb.c revision 1.154
1 /* $NetBSD: pccbb.c,v 1.154 2007/11/24 07:59:21 dyoung Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: pccbb.c,v 1.154 2007/11/24 07:59:21 dyoung Exp $"); 35 36 /* 37 #define CBB_DEBUG 38 #define SHOW_REGS 39 */ 40 41 /* 42 * BROKEN! 43 #define PCCBB_PCMCIA_POLL 44 #define CB_PCMCIA_POLL 45 #define CB_PCMCIA_POLL_ONLY 46 #define LEVEL2 47 */ 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/kernel.h> 52 #include <sys/errno.h> 53 #include <sys/ioctl.h> 54 #include <sys/reboot.h> /* for bootverbose */ 55 #include <sys/syslog.h> 56 #include <sys/device.h> 57 #include <sys/malloc.h> 58 #include <sys/proc.h> 59 60 #include <sys/intr.h> 61 #include <sys/bus.h> 62 63 #include <dev/pci/pcivar.h> 64 #include <dev/pci/pcireg.h> 65 #include <dev/pci/pcidevs.h> 66 67 #include <dev/pci/pccbbreg.h> 68 69 #include <dev/cardbus/cardslotvar.h> 70 71 #include <dev/cardbus/cardbusvar.h> 72 73 #include <dev/pcmcia/pcmciareg.h> 74 #include <dev/pcmcia/pcmciavar.h> 75 76 #include <dev/ic/i82365reg.h> 77 #include <dev/ic/i82365var.h> 78 #include <dev/pci/pccbbvar.h> 79 80 #include "locators.h" 81 82 #ifndef __NetBSD_Version__ 83 struct cfdriver cbb_cd = { 84 NULL, "cbb", DV_DULL 85 }; 86 #endif 87 88 #ifdef CBB_DEBUG 89 #define DPRINTF(x) printf x 90 #define STATIC 91 #else 92 #define DPRINTF(x) 93 #define STATIC static 94 #endif 95 96 int pccbb_burstup = 1; 97 98 /* 99 * delay_ms() is wait in milliseconds. It should be used instead 100 * of delay() if you want to wait more than 1 ms. 101 */ 102 static inline void 103 delay_ms(int millis, void *param) 104 { 105 if (cold) 106 delay(millis * 1000); 107 else 108 tsleep(param, PWAIT, "pccbb", MAX(2, hz * millis / 1000)); 109 } 110 111 int pcicbbmatch(struct device *, struct cfdata *, void *); 112 void pccbbattach(struct device *, struct device *, void *); 113 int pccbbintr(void *); 114 static void pci113x_insert(void *); 115 static int pccbbintr_function(struct pccbb_softc *); 116 117 static int pccbb_detect_card(struct pccbb_softc *); 118 119 static void pccbb_pcmcia_write(struct pcic_handle *, int, u_int8_t); 120 static u_int8_t pccbb_pcmcia_read(struct pcic_handle *, int); 121 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 122 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 123 124 STATIC int cb_reset(struct pccbb_softc *); 125 STATIC int cb_detect_voltage(struct pccbb_softc *); 126 STATIC int cbbprint(void *, const char *); 127 128 static int cb_chipset(u_int32_t, int *); 129 STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *, 130 struct pcmciabus_attach_args *); 131 #if 0 132 STATIC void pccbb_pcmcia_attach_card(struct pcic_handle *); 133 STATIC void pccbb_pcmcia_detach_card(struct pcic_handle *, int); 134 STATIC void pccbb_pcmcia_deactivate_card(struct pcic_handle *); 135 #endif 136 137 STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int); 138 STATIC int pccbb_power(cardbus_chipset_tag_t, int); 139 STATIC int pccbb_cardenable(struct pccbb_softc * sc, int function); 140 #if !rbus 141 static int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 142 static int pccbb_io_close(cardbus_chipset_tag_t, int); 143 static int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 144 static int pccbb_mem_close(cardbus_chipset_tag_t, int); 145 #endif /* !rbus */ 146 static void *pccbb_intr_establish(struct pccbb_softc *, int irq, 147 int level, int (*ih) (void *), void *sc); 148 static void pccbb_intr_disestablish(struct pccbb_softc *, void *ih); 149 150 static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t, int irq, 151 int level, int (*ih) (void *), void *sc); 152 static void pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih); 153 154 static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t, int, int); 155 static void pccbb_free_tag(cardbus_chipset_tag_t, cardbustag_t); 156 static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t, cardbustag_t, int); 157 static void pccbb_conf_write(cardbus_chipset_tag_t, cardbustag_t, int, 158 cardbusreg_t); 159 static void pccbb_chipinit(struct pccbb_softc *); 160 161 STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 162 struct pcmcia_mem_handle *); 163 STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t, 164 struct pcmcia_mem_handle *); 165 STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 166 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *); 167 STATIC void pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t, int); 168 STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 169 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 170 STATIC void pccbb_pcmcia_io_free(pcmcia_chipset_handle_t, 171 struct pcmcia_io_handle *); 172 STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 173 bus_size_t, struct pcmcia_io_handle *, int *); 174 STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t, int); 175 STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t, 176 struct pcmcia_function *, int, int (*)(void *), void *); 177 STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t, void *); 178 STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t); 179 STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t); 180 STATIC void pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t, int); 181 STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch); 182 183 static int pccbb_pcmcia_wait_ready(struct pcic_handle *); 184 static void pccbb_pcmcia_delay(struct pcic_handle *, int, const char *); 185 186 static void pccbb_pcmcia_do_io_map(struct pcic_handle *, int); 187 static void pccbb_pcmcia_do_mem_map(struct pcic_handle *, int); 188 static void pccbb_powerhook(int, void *); 189 190 /* bus-space allocation and deallocation functions */ 191 #if rbus 192 193 static int pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t, rbus_tag_t, 194 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 195 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp); 196 static int pccbb_rbus_cb_space_free(cardbus_chipset_tag_t, rbus_tag_t, 197 bus_space_handle_t, bus_size_t); 198 199 #endif /* rbus */ 200 201 #if rbus 202 203 static int pccbb_open_win(struct pccbb_softc *, bus_space_tag_t, 204 bus_addr_t, bus_size_t, bus_space_handle_t, int flags); 205 static int pccbb_close_win(struct pccbb_softc *, bus_space_tag_t, 206 bus_space_handle_t, bus_size_t); 207 static int pccbb_winlist_insert(struct pccbb_win_chain_head *, bus_addr_t, 208 bus_size_t, bus_space_handle_t, int); 209 static int pccbb_winlist_delete(struct pccbb_win_chain_head *, 210 bus_space_handle_t, bus_size_t); 211 static void pccbb_winset(bus_addr_t align, struct pccbb_softc *, 212 bus_space_tag_t); 213 void pccbb_winlist_show(struct pccbb_win_chain *); 214 215 #endif /* rbus */ 216 217 /* for config_defer */ 218 static void pccbb_pci_callback(struct device *); 219 220 #if defined SHOW_REGS 221 static void cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, 222 bus_space_tag_t memt, bus_space_handle_t memh); 223 #endif 224 225 CFATTACH_DECL(cbb_pci, sizeof(struct pccbb_softc), 226 pcicbbmatch, pccbbattach, NULL, NULL); 227 228 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 229 pccbb_pcmcia_mem_alloc, 230 pccbb_pcmcia_mem_free, 231 pccbb_pcmcia_mem_map, 232 pccbb_pcmcia_mem_unmap, 233 pccbb_pcmcia_io_alloc, 234 pccbb_pcmcia_io_free, 235 pccbb_pcmcia_io_map, 236 pccbb_pcmcia_io_unmap, 237 pccbb_pcmcia_intr_establish, 238 pccbb_pcmcia_intr_disestablish, 239 pccbb_pcmcia_socket_enable, 240 pccbb_pcmcia_socket_disable, 241 pccbb_pcmcia_socket_settype, 242 pccbb_pcmcia_card_detect 243 }; 244 245 #if rbus 246 static struct cardbus_functions pccbb_funcs = { 247 pccbb_rbus_cb_space_alloc, 248 pccbb_rbus_cb_space_free, 249 pccbb_cb_intr_establish, 250 pccbb_cb_intr_disestablish, 251 pccbb_ctrl, 252 pccbb_power, 253 pccbb_make_tag, 254 pccbb_free_tag, 255 pccbb_conf_read, 256 pccbb_conf_write, 257 }; 258 #else 259 static struct cardbus_functions pccbb_funcs = { 260 pccbb_ctrl, 261 pccbb_power, 262 pccbb_mem_open, 263 pccbb_mem_close, 264 pccbb_io_open, 265 pccbb_io_close, 266 pccbb_cb_intr_establish, 267 pccbb_cb_intr_disestablish, 268 pccbb_make_tag, 269 pccbb_conf_read, 270 pccbb_conf_write, 271 }; 272 #endif 273 274 int 275 pcicbbmatch(struct device *parent, struct cfdata *match, void *aux) 276 { 277 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 278 279 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 280 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 281 PCI_INTERFACE(pa->pa_class) == 0) { 282 return 1; 283 } 284 285 return 0; 286 } 287 288 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 289 | ((prod) << PCI_PRODUCT_SHIFT)) 290 291 const struct yenta_chipinfo { 292 pcireg_t yc_id; /* vendor tag | product tag */ 293 int yc_chiptype; 294 int yc_flags; 295 } yc_chipsets[] = { 296 /* Texas Instruments chips */ 297 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 298 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 299 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 300 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 301 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI125X, 302 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 303 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 304 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 305 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 306 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 307 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 308 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 309 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI125X, 310 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 311 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI125X, 312 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 313 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 314 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 315 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 316 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 317 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI1420, 318 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 319 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI125X, 320 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 321 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 322 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 323 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1520), CB_TI12XX, 324 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 325 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4410YENTA), CB_TI12XX, 326 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 327 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4520YENTA), CB_TI12XX, 328 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 329 330 /* Ricoh chips */ 331 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 332 PCCBB_PCMCIA_MEM_32}, 333 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 334 PCCBB_PCMCIA_MEM_32}, 335 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 336 PCCBB_PCMCIA_MEM_32}, 337 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 338 PCCBB_PCMCIA_MEM_32}, 339 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 340 PCCBB_PCMCIA_MEM_32}, 341 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 342 PCCBB_PCMCIA_MEM_32}, 343 344 /* Toshiba products */ 345 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 346 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 347 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 348 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 349 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 350 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 351 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 352 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 353 354 /* Cirrus Logic products */ 355 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 356 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 357 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 358 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 359 360 /* sentinel, or Generic chip */ 361 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 362 }; 363 364 static int 365 cb_chipset(u_int32_t pci_id, int *flagp) 366 { 367 const struct yenta_chipinfo *yc; 368 369 /* Loop over except the last default entry. */ 370 for (yc = yc_chipsets; yc < yc_chipsets + 371 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 372 if (pci_id == yc->yc_id) 373 break; 374 375 if (flagp != NULL) 376 *flagp = yc->yc_flags; 377 378 return (yc->yc_chiptype); 379 } 380 381 static void 382 pccbb_shutdown(void *arg) 383 { 384 struct pccbb_softc *sc = arg; 385 pcireg_t command; 386 387 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 388 389 /* 390 * turn off power 391 * 392 * XXX - do not turn off power if chipset is TI 113X because 393 * only TI 1130 with PowerMac 2400 hangs in pccbb_power(). 394 */ 395 if (sc->sc_chipset != CB_TI113X) { 396 pccbb_power((cardbus_chipset_tag_t)sc, 397 CARDBUS_VCC_0V | CARDBUS_VPP_0V); 398 } 399 400 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 401 0); 402 403 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 404 405 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 406 PCI_COMMAND_MASTER_ENABLE); 407 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 408 409 } 410 411 void 412 pccbbattach(struct device *parent, struct device *self, void *aux) 413 { 414 struct pccbb_softc *sc = (void *)self; 415 struct pci_attach_args *pa = aux; 416 pci_chipset_tag_t pc = pa->pa_pc; 417 pcireg_t busreg, reg, sock_base; 418 bus_addr_t sockbase; 419 char devinfo[256]; 420 int flags; 421 int pwrmgt_offs; 422 423 #ifdef __HAVE_PCCBB_ATTACH_HOOK 424 pccbb_attach_hook(parent, self, pa); 425 #endif 426 427 callout_init(&sc->sc_insert_ch, 0); 428 callout_setfunc(&sc->sc_insert_ch, pci113x_insert, sc); 429 430 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 431 432 pci_devinfo(pa->pa_id, 0, 0, devinfo, sizeof(devinfo)); 433 printf(": %s (rev. 0x%02x)", devinfo, PCI_REVISION(pa->pa_class)); 434 DPRINTF((" (chipflags %x)", flags)); 435 printf("\n"); 436 437 TAILQ_INIT(&sc->sc_memwindow); 438 TAILQ_INIT(&sc->sc_iowindow); 439 440 #if rbus 441 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 442 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 443 444 #if 0 445 printf("pa->pa_memt: %08x vs rbus_mem->rb_bt: %08x\n", 446 pa->pa_memt, sc->sc_rbus_memt->rb_bt); 447 #endif 448 #endif /* rbus */ 449 450 sc->sc_flags &= ~CBB_MEMHMAPPED; 451 452 /* power management: set D0 state */ 453 sc->sc_pwrmgt_offs = 0; 454 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, 455 &pwrmgt_offs, 0)) { 456 reg = pci_conf_read(pc, pa->pa_tag, pwrmgt_offs + PCI_PMCSR); 457 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 458 reg & 0x100 /* PCI_PMCSR_PME_EN */) { 459 reg &= ~PCI_PMCSR_STATE_MASK; 460 reg |= PCI_PMCSR_STATE_D0; 461 reg &= ~(0x100 /* PCI_PMCSR_PME_EN */); 462 pci_conf_write(pc, pa->pa_tag, 463 pwrmgt_offs + PCI_PMCSR, reg); 464 } 465 466 sc->sc_pwrmgt_offs = pwrmgt_offs; 467 } 468 469 /* 470 * MAP socket registers and ExCA registers on memory-space 471 * When no valid address is set on socket base registers (on pci 472 * config space), get it not polite way. 473 */ 474 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 475 476 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 477 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 478 /* The address must be valid. */ 479 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 480 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL)) { 481 printf("%s: can't map socket base address 0x%lx\n", 482 sc->sc_dev.dv_xname, (unsigned long)sock_base); 483 /* 484 * I think it's funny: socket base registers must be 485 * mapped on memory space, but ... 486 */ 487 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 488 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 489 NULL)) { 490 printf("%s: can't map socket base address" 491 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 492 (unsigned long)sockbase); 493 /* give up... allocate reg space via rbus. */ 494 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 495 } else 496 sc->sc_flags |= CBB_MEMHMAPPED; 497 } else { 498 DPRINTF(("%s: socket base address 0x%lx\n", 499 sc->sc_dev.dv_xname, (unsigned long)sockbase)); 500 sc->sc_flags |= CBB_MEMHMAPPED; 501 } 502 } 503 504 sc->sc_mem_start = 0; /* XXX */ 505 sc->sc_mem_end = 0xffffffff; /* XXX */ 506 507 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 508 509 /* pccbb_machdep.c end */ 510 511 #if defined CBB_DEBUG 512 { 513 static const char *intrname[] = { "NON", "A", "B", "C", "D" }; 514 printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname, 515 intrname[pa->pa_intrpin], pa->pa_intrline); 516 } 517 #endif 518 519 /* setup softc */ 520 sc->sc_pc = pc; 521 sc->sc_iot = pa->pa_iot; 522 sc->sc_memt = pa->pa_memt; 523 sc->sc_dmat = pa->pa_dmat; 524 sc->sc_tag = pa->pa_tag; 525 sc->sc_function = pa->pa_function; 526 sc->sc_sockbase = sock_base; 527 sc->sc_busnum = busreg; 528 529 memcpy(&sc->sc_pa, pa, sizeof(*pa)); 530 531 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 532 533 shutdownhook_establish(pccbb_shutdown, sc); 534 535 /* Disable legacy register mapping. */ 536 switch (sc->sc_chipset) { 537 case CB_RX5C46X: /* fallthrough */ 538 #if 0 539 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 540 case CB_RX5C47X: 541 #endif 542 /* 543 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 544 * cannot be disabled by substituting 0 into PCI_LEGACY 545 * register. Ricoh CardBus bridges have special bits on Bridge 546 * control reg (addr 0x3e on PCI config space). 547 */ 548 reg = pci_conf_read(pc, pa->pa_tag, PCI_BRIDGE_CONTROL_REG); 549 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 550 pci_conf_write(pc, pa->pa_tag, PCI_BRIDGE_CONTROL_REG, reg); 551 break; 552 553 default: 554 /* XXX I don't know proper way to kill legacy I/O. */ 555 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 556 break; 557 } 558 559 config_defer(self, pccbb_pci_callback); 560 } 561 562 563 564 565 /* 566 * static void pccbb_pci_callback(struct device *self) 567 * 568 * The actual attach routine: get memory space for YENTA register 569 * space, setup YENTA register and route interrupt. 570 * 571 * This function should be deferred because this device may obtain 572 * memory space dynamically. This function must avoid obtaining 573 * memory area which has already kept for another device. 574 */ 575 static void 576 pccbb_pci_callback(struct device *self) 577 { 578 struct pccbb_softc *sc = (void *)self; 579 pci_chipset_tag_t pc = sc->sc_pc; 580 pci_intr_handle_t ih; 581 const char *intrstr = NULL; 582 bus_addr_t sockbase; 583 struct cbslot_attach_args cba; 584 struct pcmciabus_attach_args paa; 585 struct cardslot_attach_args caa; 586 struct cardslot_softc *csc; 587 588 if (!(sc->sc_flags & CBB_MEMHMAPPED)) { 589 /* The socket registers aren't mapped correctly. */ 590 #if rbus 591 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 592 (sc->sc_chipset == CB_RX5C47X 593 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 594 0, &sockbase, &sc->sc_base_memh)) { 595 return; 596 } 597 sc->sc_base_memt = sc->sc_memt; 598 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 599 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 600 sc->sc_dev.dv_xname, (unsigned long)sockbase, 601 (unsigned long)pci_conf_read(pc, sc->sc_tag, 602 PCI_SOCKBASE))); 603 #else 604 sc->sc_base_memt = sc->sc_memt; 605 #if !defined CBB_PCI_BASE 606 #define CBB_PCI_BASE 0x20000000 607 #endif 608 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 609 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 610 /* cannot allocate memory space */ 611 return; 612 } 613 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 614 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 615 sc->sc_dev.dv_xname, (unsigned long)sock_base, 616 (unsigned long)pci_conf_read(pc, 617 sc->sc_tag, PCI_SOCKBASE))); 618 sc->sc_sockbase = sockbase; 619 #endif 620 sc->sc_flags |= CBB_MEMHMAPPED; 621 } 622 623 /* bus bridge initialization */ 624 pccbb_chipinit(sc); 625 626 /* clear data structure for child device interrupt handlers */ 627 LIST_INIT(&sc->sc_pil); 628 sc->sc_pil_intr_enable = 1; 629 630 /* Map and establish the interrupt. */ 631 if (pci_intr_map(&sc->sc_pa, &ih)) { 632 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 633 return; 634 } 635 intrstr = pci_intr_string(pc, ih); 636 637 /* 638 * XXX pccbbintr should be called under the priority lower 639 * than any other hard interupts. 640 */ 641 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 642 643 if (sc->sc_ih == NULL) { 644 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 645 if (intrstr != NULL) { 646 printf(" at %s", intrstr); 647 } 648 printf("\n"); 649 return; 650 } 651 652 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 653 powerhook_establish(sc->sc_dev.dv_xname, pccbb_powerhook, sc); 654 655 { 656 u_int32_t sockstat; 657 658 sockstat = bus_space_read_4(sc->sc_base_memt, 659 sc->sc_base_memh, CB_SOCKET_STAT); 660 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 661 sc->sc_flags |= CBB_CARDEXIST; 662 } 663 } 664 665 /* 666 * attach cardbus 667 */ 668 { 669 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 670 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 671 672 /* initialize cbslot_attach */ 673 cba.cba_busname = "cardbus"; 674 cba.cba_iot = sc->sc_iot; 675 cba.cba_memt = sc->sc_memt; 676 cba.cba_dmat = sc->sc_dmat; 677 cba.cba_bus = (busreg >> 8) & 0x0ff; 678 cba.cba_cc = (void *)sc; 679 cba.cba_cf = &pccbb_funcs; 680 cba.cba_intrline = sc->sc_pa.pa_intrline; 681 682 #if rbus 683 cba.cba_rbus_iot = sc->sc_rbus_iot; 684 cba.cba_rbus_memt = sc->sc_rbus_memt; 685 #endif 686 687 cba.cba_cacheline = PCI_CACHELINE(bhlc); 688 cba.cba_max_lattimer = PCI_LATTIMER(bhlc); 689 690 if (bootverbose) { 691 printf("%s: cacheline 0x%x lattimer 0x%x\n", 692 sc->sc_dev.dv_xname, cba.cba_cacheline, 693 cba.cba_max_lattimer); 694 printf("%s: bhlc 0x%x\n", 695 device_xname(&sc->sc_dev), bhlc); 696 } 697 #if defined SHOW_REGS 698 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 699 sc->sc_base_memh); 700 #endif 701 } 702 703 pccbb_pcmcia_attach_setup(sc, &paa); 704 caa.caa_cb_attach = NULL; 705 if (cba.cba_bus == 0) 706 printf("%s: secondary bus number uninitialized; try PCI_BUS_FIXUP\n", sc->sc_dev.dv_xname); 707 else 708 caa.caa_cb_attach = &cba; 709 caa.caa_16_attach = &paa; 710 caa.caa_ph = &sc->sc_pcmcia_h; 711 712 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 713 DPRINTF(("%s: found cardslot\n", __func__)); 714 sc->sc_csc = csc; 715 } 716 717 return; 718 } 719 720 721 722 723 724 /* 725 * static void pccbb_chipinit(struct pccbb_softc *sc) 726 * 727 * This function initialize YENTA chip registers listed below: 728 * 1) PCI command reg, 729 * 2) PCI and CardBus latency timer, 730 * 3) route PCI interrupt, 731 * 4) close all memory and io windows. 732 * 5) turn off bus power. 733 * 6) card detect and power cycle interrupts on. 734 * 7) clear interrupt 735 */ 736 static void 737 pccbb_chipinit(struct pccbb_softc *sc) 738 { 739 pci_chipset_tag_t pc = sc->sc_pc; 740 pcitag_t tag = sc->sc_tag; 741 bus_space_tag_t bmt = sc->sc_base_memt; 742 bus_space_handle_t bmh = sc->sc_base_memh; 743 pcireg_t bcr, bhlc, cbctl, csr, lscp, mfunc, mrburst, slotctl, sockctl, 744 sockmask, sysctrl; 745 746 /* 747 * Set PCI command reg. 748 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 749 */ 750 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 751 /* I believe it is harmless. */ 752 csr |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 753 PCI_COMMAND_MASTER_ENABLE); 754 csr |= (PCI_COMMAND_PARITY_ENABLE|PCI_COMMAND_SERR_ENABLE); 755 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 756 757 /* 758 * Set CardBus latency timer. 759 */ 760 lscp = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 761 if (PCI_CB_LATENCY(lscp) < 0x20) { 762 lscp &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 763 lscp |= (0x20 << PCI_CB_LATENCY_SHIFT); 764 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, lscp); 765 } 766 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 767 PCI_CB_LATENCY(lscp), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 768 769 /* 770 * Set PCI latency timer. 771 */ 772 bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG); 773 if (PCI_LATTIMER(bhlc) < 0x10) { 774 bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 775 bhlc |= (0x10 << PCI_LATTIMER_SHIFT); 776 pci_conf_write(pc, tag, PCI_BHLC_REG, bhlc); 777 } 778 DPRINTF(("PCI latency timer 0x%x (%x)\n", 779 PCI_LATTIMER(bhlc), pci_conf_read(pc, tag, PCI_BHLC_REG))); 780 781 782 /* Route functional interrupts to PCI. */ 783 bcr = pci_conf_read(pc, tag, PCI_BRIDGE_CONTROL_REG); 784 bcr |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 785 bcr |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 786 /* assert reset */ 787 bcr |= PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT; 788 /* Set master abort mode to 1, forward SERR# from secondary 789 * to primary, and detect parity errors on secondary. 790 */ 791 bcr |= PCI_BRIDGE_CONTROL_MABRT << PCI_BRIDGE_CONTROL_SHIFT; 792 bcr |= PCI_BRIDGE_CONTROL_SERR << PCI_BRIDGE_CONTROL_SHIFT; 793 bcr |= PCI_BRIDGE_CONTROL_PERE << PCI_BRIDGE_CONTROL_SHIFT; 794 pci_conf_write(pc, tag, PCI_BRIDGE_CONTROL_REG, bcr); 795 796 switch (sc->sc_chipset) { 797 case CB_TI113X: 798 cbctl = pci_conf_read(pc, tag, PCI_CBCTRL); 799 /* This bit is shared, but may read as 0 on some chips, so set 800 it explicitly on both functions. */ 801 cbctl |= PCI113X_CBCTRL_PCI_IRQ_ENA; 802 /* CSC intr enable */ 803 cbctl |= PCI113X_CBCTRL_PCI_CSC; 804 /* functional intr prohibit | prohibit ISA routing */ 805 cbctl &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 806 pci_conf_write(pc, tag, PCI_CBCTRL, cbctl); 807 break; 808 809 case CB_TI1420: 810 sysctrl = pci_conf_read(pc, tag, PCI_SYSCTRL); 811 mrburst = pccbb_burstup 812 ? PCI1420_SYSCTRL_MRBURST : PCI1420_SYSCTRL_MRBURSTDN; 813 if ((sysctrl & PCI1420_SYSCTRL_MRBURST) == mrburst) { 814 printf("%s: %swrite bursts enabled\n", 815 device_xname(&sc->sc_dev), 816 pccbb_burstup ? "read/" : ""); 817 } else if (pccbb_burstup) { 818 printf("%s: enabling read/write bursts\n", 819 device_xname(&sc->sc_dev)); 820 sysctrl |= PCI1420_SYSCTRL_MRBURST; 821 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 822 } else { 823 printf("%s: disabling read bursts, " 824 "enabling write bursts\n", 825 device_xname(&sc->sc_dev)); 826 sysctrl |= PCI1420_SYSCTRL_MRBURSTDN; 827 sysctrl &= ~PCI1420_SYSCTRL_MRBURSTUP; 828 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 829 } 830 /*FALLTHROUGH*/ 831 case CB_TI12XX: 832 /* 833 * Some TI 12xx (and [14][45]xx) based pci cards 834 * sometimes have issues with the MFUNC register not 835 * being initialized due to a bad EEPROM on board. 836 * Laptops that this matters on have this register 837 * properly initialized. 838 * 839 * The TI125X parts have a different register. 840 */ 841 mfunc = pci_conf_read(pc, tag, PCI12XX_MFUNC); 842 if (mfunc == 0) { 843 mfunc &= ~PCI12XX_MFUNC_PIN0; 844 mfunc |= PCI12XX_MFUNC_PIN0_INTA; 845 if ((pci_conf_read(pc, tag, PCI_SYSCTRL) & 846 PCI12XX_SYSCTRL_INTRTIE) == 0) { 847 mfunc &= ~PCI12XX_MFUNC_PIN1; 848 mfunc |= PCI12XX_MFUNC_PIN1_INTB; 849 } 850 pci_conf_write(pc, tag, PCI12XX_MFUNC, mfunc); 851 } 852 /* fallthrough */ 853 854 case CB_TI125X: 855 /* 856 * Disable zoom video. Some machines initialize this 857 * improperly and experience has shown that this helps 858 * prevent strange behavior. 859 */ 860 pci_conf_write(pc, tag, PCI12XX_MMCTRL, 0); 861 862 sysctrl = pci_conf_read(pc, tag, PCI_SYSCTRL); 863 sysctrl |= PCI12XX_SYSCTRL_VCCPROT; 864 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 865 cbctl = pci_conf_read(pc, tag, PCI_CBCTRL); 866 cbctl |= PCI12XX_CBCTRL_CSC; 867 pci_conf_write(pc, tag, PCI_CBCTRL, cbctl); 868 break; 869 870 case CB_TOPIC95B: 871 sockctl = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 872 sockctl |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 873 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, sockctl); 874 slotctl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 875 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 876 sc->sc_dev.dv_xname, slotctl)); 877 slotctl |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 878 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 879 slotctl &= ~TOPIC_SLOT_CTRL_SWDETECT; 880 DPRINTF(("0x%x\n", slotctl)); 881 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slotctl); 882 break; 883 884 case CB_TOPIC97: 885 slotctl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 886 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 887 sc->sc_dev.dv_xname, slotctl)); 888 slotctl |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 889 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 890 slotctl &= ~TOPIC_SLOT_CTRL_SWDETECT; 891 slotctl |= TOPIC97_SLOT_CTRL_PCIINT; 892 slotctl &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 893 DPRINTF(("0x%x\n", slotctl)); 894 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slotctl); 895 /* make sure to assert LV card support bits */ 896 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 897 0x800 + 0x3e, 898 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 899 0x800 + 0x3e) | 0x03); 900 break; 901 } 902 903 /* Close all memory and I/O windows. */ 904 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 905 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 906 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 907 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 908 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 909 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 910 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 911 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 912 913 /* reset 16-bit pcmcia bus */ 914 bus_space_write_1(bmt, bmh, 0x800 + PCIC_INTR, 915 bus_space_read_1(bmt, bmh, 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 916 917 /* turn off power */ 918 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 919 920 /* CSC Interrupt: Card detect and power cycle interrupts on */ 921 sockmask = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 922 sockmask |= CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; 923 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, sockmask); 924 /* reset interrupt */ 925 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 926 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 927 } 928 929 930 931 932 /* 933 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 934 * struct pcmciabus_attach_args *paa) 935 * 936 * This function attaches 16-bit PCcard bus. 937 */ 938 STATIC void 939 pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 940 struct pcmciabus_attach_args *paa) 941 { 942 struct pcic_handle *ph = &sc->sc_pcmcia_h; 943 #if rbus 944 rbus_tag_t rb; 945 #endif 946 947 /* initialize pcmcia part in pccbb_softc */ 948 ph->ph_parent = (struct device *)sc; 949 ph->sock = sc->sc_function; 950 ph->flags = 0; 951 ph->shutdown = 0; 952 ph->ih_irq = sc->sc_pa.pa_intrline; 953 ph->ph_bus_t = sc->sc_base_memt; 954 ph->ph_bus_h = sc->sc_base_memh; 955 ph->ph_read = pccbb_pcmcia_read; 956 ph->ph_write = pccbb_pcmcia_write; 957 sc->sc_pct = &pccbb_pcmcia_funcs; 958 959 /* 960 * We need to do a few things here: 961 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 962 * setting the IRQ numbers to 0. 963 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 964 * routing of CSC interrupts (e.g. card removal) to PCI while in 965 * PCMCIA mode. We just leave this set all the time. 966 * 3) Enable card insertion/removal interrupts in case the chip also 967 * needs that while in PCMCIA mode. 968 * 4) Clear any pending CSC interrupt. 969 */ 970 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE); 971 if (sc->sc_chipset == CB_TI113X) { 972 Pcic_write(ph, PCIC_CSC_INTR, 0); 973 } else { 974 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 975 Pcic_read(ph, PCIC_CSC); 976 } 977 978 /* initialize pcmcia bus attachment */ 979 paa->paa_busname = "pcmcia"; 980 paa->pct = sc->sc_pct; 981 paa->pch = ph; 982 paa->iobase = 0; /* I don't use them */ 983 paa->iosize = 0; 984 #if rbus 985 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 986 paa->iobase = rb->rb_start + rb->rb_offset; 987 paa->iosize = rb->rb_end - rb->rb_start; 988 #endif 989 990 return; 991 } 992 993 #if 0 994 STATIC void 995 pccbb_pcmcia_attach_card(struct pcic_handle *ph) 996 { 997 if (ph->flags & PCIC_FLAG_CARDP) { 998 panic("pccbb_pcmcia_attach_card: already attached"); 999 } 1000 1001 /* call the MI attach function */ 1002 pcmcia_card_attach(ph->pcmcia); 1003 1004 ph->flags |= PCIC_FLAG_CARDP; 1005 } 1006 1007 STATIC void 1008 pccbb_pcmcia_detach_card(struct pcic_handle *ph, int flags) 1009 { 1010 if (!(ph->flags & PCIC_FLAG_CARDP)) { 1011 panic("pccbb_pcmcia_detach_card: already detached"); 1012 } 1013 1014 ph->flags &= ~PCIC_FLAG_CARDP; 1015 1016 /* call the MI detach function */ 1017 pcmcia_card_detach(ph->pcmcia, flags); 1018 } 1019 #endif 1020 1021 /* 1022 * int pccbbintr(arg) 1023 * void *arg; 1024 * This routine handles the interrupt from Yenta PCI-CardBus bridge 1025 * itself. 1026 */ 1027 int 1028 pccbbintr(void *arg) 1029 { 1030 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1031 u_int32_t sockevent, sockstate; 1032 bus_space_tag_t memt = sc->sc_base_memt; 1033 bus_space_handle_t memh = sc->sc_base_memh; 1034 struct pcic_handle *ph = &sc->sc_pcmcia_h; 1035 1036 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 1037 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 1038 Pcic_read(ph, PCIC_CSC); 1039 1040 if (sockevent != 0) { 1041 aprint_debug("%s: enter sockevent %" PRIx32 "\n", __func__, 1042 sockevent); 1043 } 1044 1045 /* Sometimes a change of CSTSCHG# accompanies the first 1046 * interrupt from an Atheros WLAN. That generates a 1047 * CB_SOCKET_EVENT_CSTS event on the bridge. The event 1048 * isn't interesting to pccbb(4), so we used to ignore the 1049 * interrupt. Now, let the child devices try to handle 1050 * the interrupt, instead. The Atheros NIC produces 1051 * interrupts more reliably, now: used to be that it would 1052 * only interrupt if the driver avoided powering down the 1053 * NIC's cardslot, and then the NIC would only work after 1054 * it was reset a second time. 1055 */ 1056 if (sockevent == 0 || 1057 (sockevent & ~(CB_SOCKET_EVENT_POWER|CB_SOCKET_EVENT_CD)) != 0) { 1058 /* This intr is not for me: it may be for my child devices. */ 1059 if (sc->sc_pil_intr_enable) { 1060 return pccbbintr_function(sc); 1061 } else { 1062 return 0; 1063 } 1064 } 1065 1066 if (sockevent & CB_SOCKET_EVENT_CD) { 1067 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1068 if (0x00 != (sockstate & CB_SOCKET_STAT_CD)) { 1069 /* A card should be removed. */ 1070 if (sc->sc_flags & CBB_CARDEXIST) { 1071 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 1072 sockevent)); 1073 DPRINTF((" card removed, 0x%08x\n", sockstate)); 1074 sc->sc_flags &= ~CBB_CARDEXIST; 1075 if (sc->sc_csc->sc_status & 1076 CARDSLOT_STATUS_CARD_16) { 1077 #if 0 1078 struct pcic_handle *ph = 1079 &sc->sc_pcmcia_h; 1080 1081 pcmcia_card_deactivate(ph->pcmcia); 1082 pccbb_pcmcia_socket_disable(ph); 1083 pccbb_pcmcia_detach_card(ph, 1084 DETACH_FORCE); 1085 #endif 1086 cardslot_event_throw(sc->sc_csc, 1087 CARDSLOT_EVENT_REMOVAL_16); 1088 } else if (sc->sc_csc->sc_status & 1089 CARDSLOT_STATUS_CARD_CB) { 1090 /* Cardbus intr removed */ 1091 cardslot_event_throw(sc->sc_csc, 1092 CARDSLOT_EVENT_REMOVAL_CB); 1093 } 1094 } else if (sc->sc_flags & CBB_INSERTING) { 1095 sc->sc_flags &= ~CBB_INSERTING; 1096 callout_stop(&sc->sc_insert_ch); 1097 } 1098 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 1099 /* 1100 * The pccbbintr may called from powerdown hook when 1101 * the system resumed, to detect the card 1102 * insertion/removal during suspension. 1103 */ 1104 (sc->sc_flags & CBB_CARDEXIST) == 0) { 1105 if (sc->sc_flags & CBB_INSERTING) { 1106 callout_stop(&sc->sc_insert_ch); 1107 } 1108 callout_schedule(&sc->sc_insert_ch, hz / 5); 1109 sc->sc_flags |= CBB_INSERTING; 1110 } 1111 } 1112 1113 /* XXX sockevent == 9 does occur in the wild. handle it. */ 1114 if (sockevent & CB_SOCKET_EVENT_POWER) { 1115 DPRINTF(("Powercycling because of socket event\n")); 1116 /* XXX: Does not happen when attaching a 16-bit card */ 1117 sc->sc_pwrcycle++; 1118 wakeup(&sc->sc_pwrcycle); 1119 } 1120 1121 return (1); 1122 } 1123 1124 /* 1125 * static int pccbbintr_function(struct pccbb_softc *sc) 1126 * 1127 * This function calls each interrupt handler registered at the 1128 * bridge. The interrupt handlers are called in registered order. 1129 */ 1130 static int 1131 pccbbintr_function(struct pccbb_softc *sc) 1132 { 1133 int retval = 0, val; 1134 struct pccbb_intrhand_list *pil; 1135 int s; 1136 1137 for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1138 pil = LIST_NEXT(pil, pil_next)) { 1139 s = splraiseipl(pil->pil_icookie); 1140 val = (*pil->pil_func)(pil->pil_arg); 1141 splx(s); 1142 1143 retval = retval == 1 ? 1 : 1144 retval == 0 ? val : val != 0 ? val : retval; 1145 } 1146 1147 return retval; 1148 } 1149 1150 static void 1151 pci113x_insert(void *arg) 1152 { 1153 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1154 u_int32_t sockevent, sockstate; 1155 1156 if (!(sc->sc_flags & CBB_INSERTING)) { 1157 /* We add a card only under inserting state. */ 1158 return; 1159 } 1160 sc->sc_flags &= ~CBB_INSERTING; 1161 1162 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1163 CB_SOCKET_EVENT); 1164 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1165 CB_SOCKET_STAT); 1166 1167 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1168 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1169 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1170 sc->sc_flags |= CBB_CARDEXIST; 1171 /* call pccard interrupt handler here */ 1172 if (sockstate & CB_SOCKET_STAT_16BIT) { 1173 /* 16-bit card found */ 1174 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1175 cardslot_event_throw(sc->sc_csc, 1176 CARDSLOT_EVENT_INSERTION_16); 1177 } else if (sockstate & CB_SOCKET_STAT_CB) { 1178 /* cardbus card found */ 1179 /* cardbus_attach_card(sc->sc_csc); */ 1180 cardslot_event_throw(sc->sc_csc, 1181 CARDSLOT_EVENT_INSERTION_CB); 1182 } else { 1183 /* who are you? */ 1184 } 1185 } else { 1186 callout_schedule(&sc->sc_insert_ch, hz / 10); 1187 } 1188 } 1189 1190 #define PCCBB_PCMCIA_OFFSET 0x800 1191 static u_int8_t 1192 pccbb_pcmcia_read(struct pcic_handle *ph, int reg) 1193 { 1194 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1195 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1196 1197 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1198 PCCBB_PCMCIA_OFFSET + reg); 1199 } 1200 1201 static void 1202 pccbb_pcmcia_write(struct pcic_handle *ph, int reg, u_int8_t val) 1203 { 1204 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1205 val); 1206 1207 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1208 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1209 } 1210 1211 /* 1212 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1213 */ 1214 STATIC int 1215 pccbb_ctrl(cardbus_chipset_tag_t ct, int command) 1216 { 1217 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1218 1219 switch (command) { 1220 case CARDBUS_CD: 1221 if (2 == pccbb_detect_card(sc)) { 1222 int retval = 0; 1223 int status = cb_detect_voltage(sc); 1224 if (PCCARD_VCC_5V & status) { 1225 retval |= CARDBUS_5V_CARD; 1226 } 1227 if (PCCARD_VCC_3V & status) { 1228 retval |= CARDBUS_3V_CARD; 1229 } 1230 if (PCCARD_VCC_XV & status) { 1231 retval |= CARDBUS_XV_CARD; 1232 } 1233 if (PCCARD_VCC_YV & status) { 1234 retval |= CARDBUS_YV_CARD; 1235 } 1236 return retval; 1237 } else { 1238 return 0; 1239 } 1240 case CARDBUS_RESET: 1241 return cb_reset(sc); 1242 case CARDBUS_IO_ENABLE: /* fallthrough */ 1243 case CARDBUS_IO_DISABLE: /* fallthrough */ 1244 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1245 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1246 case CARDBUS_BM_ENABLE: /* fallthrough */ 1247 case CARDBUS_BM_DISABLE: /* fallthrough */ 1248 /* XXX: I think we don't need to call this function below. */ 1249 return pccbb_cardenable(sc, command); 1250 } 1251 1252 return 0; 1253 } 1254 1255 /* 1256 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1257 * This function returns true when it succeeds and returns false when 1258 * it fails. 1259 */ 1260 STATIC int 1261 pccbb_power(cardbus_chipset_tag_t ct, int command) 1262 { 1263 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1264 u_int32_t status, osock_ctrl, sock_ctrl, reg_ctrl; 1265 bus_space_tag_t memt = sc->sc_base_memt; 1266 bus_space_handle_t memh = sc->sc_base_memh; 1267 int on = 0, pwrcycle, s, times; 1268 struct timeval before, after, diff; 1269 1270 DPRINTF(("pccbb_power: %s and %s [0x%x]\n", 1271 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1272 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1273 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1274 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1275 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1276 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1277 "UNKNOWN", 1278 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1279 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1280 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1281 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1282 "UNKNOWN", command)); 1283 1284 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1285 osock_ctrl = sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1286 1287 switch (command & CARDBUS_VCCMASK) { 1288 case CARDBUS_VCC_UC: 1289 break; 1290 case CARDBUS_VCC_5V: 1291 on++; 1292 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1293 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1294 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1295 } else { 1296 printf("%s: BAD voltage request: no 5 V card\n", 1297 sc->sc_dev.dv_xname); 1298 return 0; 1299 } 1300 break; 1301 case CARDBUS_VCC_3V: 1302 on++; 1303 if (CB_SOCKET_STAT_3VCARD & status) { 1304 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1305 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1306 } else { 1307 printf("%s: BAD voltage request: no 3.3 V card\n", 1308 sc->sc_dev.dv_xname); 1309 return 0; 1310 } 1311 break; 1312 case CARDBUS_VCC_0V: 1313 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1314 break; 1315 default: 1316 return 0; /* power NEVER changed */ 1317 } 1318 1319 switch (command & CARDBUS_VPPMASK) { 1320 case CARDBUS_VPP_UC: 1321 break; 1322 case CARDBUS_VPP_0V: 1323 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1324 break; 1325 case CARDBUS_VPP_VCC: 1326 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1327 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1328 break; 1329 case CARDBUS_VPP_12V: 1330 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1331 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1332 break; 1333 } 1334 1335 pwrcycle = sc->sc_pwrcycle; 1336 aprint_debug("%s: osock_ctrl %#" PRIx32 " sock_ctrl %#" PRIx32 "\n", 1337 device_xname(&sc->sc_dev), osock_ctrl, sock_ctrl); 1338 1339 microtime(&before); 1340 s = splbio(); 1341 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1342 1343 /* 1344 * Wait as long as 200ms for a power-cycle interrupt. If 1345 * interrupts are enabled, but the socket has already 1346 * changed to the desired status, keep waiting for the 1347 * interrupt. "Consuming" the interrupt in this way keeps 1348 * the interrupt from prematurely waking some subsequent 1349 * pccbb_power call. 1350 * 1351 * XXX Not every bridge interrupts on the ->OFF transition. 1352 * XXX That's ok, we will time-out after 200ms. 1353 * 1354 * XXX The power cycle event will never happen when attaching 1355 * XXX a 16-bit card. That's ok, we will time-out after 1356 * XXX 200ms. 1357 */ 1358 for (times = 5; --times >= 0; ) { 1359 if (cold) 1360 DELAY(40 * 1000); 1361 else { 1362 (void)tsleep(&sc->sc_pwrcycle, PWAIT, "pccpwr", 1363 hz / 25); 1364 if (pwrcycle == sc->sc_pwrcycle) 1365 continue; 1366 } 1367 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1368 if ((status & CB_SOCKET_STAT_PWRCYCLE) != 0 && on) 1369 break; 1370 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0 && !on) 1371 break; 1372 } 1373 splx(s); 1374 microtime(&after); 1375 timersub(&after, &before, &diff); 1376 aprint_debug("%s: wait took%s %ld.%06lds\n", sc->sc_dev.dv_xname, 1377 (on && times < 0) ? " too long" : "", diff.tv_sec, diff.tv_usec); 1378 1379 /* 1380 * Ok, wait a bit longer for things to settle. 1381 */ 1382 if (on && sc->sc_chipset == CB_TOPIC95B) 1383 delay_ms(100, sc); 1384 1385 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1386 1387 if (on && sc->sc_chipset != CB_TOPIC95B) { 1388 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0) 1389 printf("%s: power on failed?\n", sc->sc_dev.dv_xname); 1390 } 1391 1392 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1393 printf("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1394 sc->sc_dev.dv_xname, sock_ctrl, status); 1395 printf("%s: disabling socket\n", sc->sc_dev.dv_xname); 1396 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1397 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1398 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1399 status &= ~CB_SOCKET_STAT_BADVCC; 1400 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, status); 1401 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1402 CB_SOCKET_STAT)); 1403 return 0; 1404 } 1405 1406 if (sc->sc_chipset == CB_TOPIC97) { 1407 reg_ctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL); 1408 reg_ctrl &= ~TOPIC97_REG_CTRL_TESTMODE; 1409 if ((command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V) 1410 reg_ctrl &= ~TOPIC97_REG_CTRL_CLKRUN_ENA; 1411 else 1412 reg_ctrl |= TOPIC97_REG_CTRL_CLKRUN_ENA; 1413 pci_conf_write(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL, reg_ctrl); 1414 } 1415 1416 return 1; /* power changed correctly */ 1417 } 1418 1419 #if defined CB_PCMCIA_POLL 1420 struct cb_poll_str { 1421 void *arg; 1422 int (*func)(void *); 1423 int level; 1424 pccard_chipset_tag_t ct; 1425 int count; 1426 struct callout poll_ch; 1427 }; 1428 1429 static struct cb_poll_str cb_poll[10]; 1430 static int cb_poll_n = 0; 1431 1432 static void cb_pcmcia_poll(void *arg); 1433 1434 static void 1435 cb_pcmcia_poll(void *arg) 1436 { 1437 struct cb_poll_str *poll = arg; 1438 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1439 struct pccbb_softc *sc = psc->cpc_parent; 1440 int s; 1441 u_int32_t spsr; /* socket present-state reg */ 1442 1443 callout_reset(&poll->poll_ch, hz / 10, cb_pcmcia_poll, poll); 1444 switch (poll->level) { 1445 case IPL_NET: 1446 s = splnet(); 1447 break; 1448 case IPL_BIO: 1449 s = splbio(); 1450 break; 1451 case IPL_TTY: /* fallthrough */ 1452 default: 1453 s = spltty(); 1454 break; 1455 } 1456 1457 spsr = 1458 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1459 CB_SOCKET_STAT); 1460 1461 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1462 if (!(spsr & 0x40)) { /* CINT low */ 1463 #else 1464 if (1) { 1465 #endif 1466 if ((*poll->func) (poll->arg) == 1) { 1467 ++poll->count; 1468 printf("intr: reported from poller, 0x%x\n", spsr); 1469 #if defined LEVEL2 1470 } else { 1471 printf("intr: miss! 0x%x\n", spsr); 1472 #endif 1473 } 1474 } 1475 splx(s); 1476 } 1477 #endif /* defined CB_PCMCIA_POLL */ 1478 1479 /* 1480 * static int pccbb_detect_card(struct pccbb_softc *sc) 1481 * return value: 0 if no card exists. 1482 * 1 if 16-bit card exists. 1483 * 2 if cardbus card exists. 1484 */ 1485 static int 1486 pccbb_detect_card(struct pccbb_softc *sc) 1487 { 1488 bus_space_handle_t base_memh = sc->sc_base_memh; 1489 bus_space_tag_t base_memt = sc->sc_base_memt; 1490 u_int32_t sockstat = 1491 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1492 int retval = 0; 1493 1494 /* CD1 and CD2 asserted */ 1495 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1496 /* card must be present */ 1497 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1498 /* NOTACARD DEASSERTED */ 1499 if (CB_SOCKET_STAT_CB & sockstat) { 1500 /* CardBus mode */ 1501 retval = 2; 1502 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1503 /* 16-bit mode */ 1504 retval = 1; 1505 } 1506 } 1507 } 1508 return retval; 1509 } 1510 1511 /* 1512 * STATIC int cb_reset(struct pccbb_softc *sc) 1513 * This function resets CardBus card. 1514 */ 1515 STATIC int 1516 cb_reset(struct pccbb_softc *sc) 1517 { 1518 /* 1519 * Reset Assert at least 20 ms 1520 * Some machines request longer duration. 1521 */ 1522 int reset_duration = 1523 (sc->sc_chipset == CB_RX5C47X ? 400 : 50); 1524 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1525 aprint_debug("%s: enter bcr %" PRIx32 "\n", __func__, bcr); 1526 1527 /* Reset bit Assert (bit 6 at 0x3E) */ 1528 bcr |= PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT; 1529 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr); 1530 aprint_debug("%s: wrote bcr %" PRIx32 "\n", __func__, bcr); 1531 delay_ms(reset_duration, sc); 1532 1533 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1534 /* Reset bit Deassert (bit 6 at 0x3E) */ 1535 bcr &= ~(PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT); 1536 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, 1537 bcr); 1538 aprint_debug("%s: wrote bcr %" PRIx32 "\n", __func__, bcr); 1539 delay_ms(reset_duration, sc); 1540 aprint_debug("%s: end of delay\n", __func__); 1541 } 1542 /* No card found on the slot. Keep Reset. */ 1543 return 1; 1544 } 1545 1546 /* 1547 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1548 * This function detect card Voltage. 1549 */ 1550 STATIC int 1551 cb_detect_voltage(struct pccbb_softc *sc) 1552 { 1553 u_int32_t psr; /* socket present-state reg */ 1554 bus_space_tag_t iot = sc->sc_base_memt; 1555 bus_space_handle_t ioh = sc->sc_base_memh; 1556 int vol = PCCARD_VCC_UKN; /* set 0 */ 1557 1558 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1559 1560 if (0x400u & psr) { 1561 vol |= PCCARD_VCC_5V; 1562 } 1563 if (0x800u & psr) { 1564 vol |= PCCARD_VCC_3V; 1565 } 1566 1567 return vol; 1568 } 1569 1570 STATIC int 1571 cbbprint(void *aux, const char *pcic) 1572 { 1573 #if 0 1574 struct cbslot_attach_args *cba = aux; 1575 1576 if (cba->cba_slot >= 0) { 1577 aprint_normal(" slot %d", cba->cba_slot); 1578 } 1579 #endif 1580 return UNCONF; 1581 } 1582 1583 /* 1584 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1585 * This function enables and disables the card 1586 */ 1587 STATIC int 1588 pccbb_cardenable(struct pccbb_softc *sc, int function) 1589 { 1590 u_int32_t command = 1591 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1592 1593 DPRINTF(("pccbb_cardenable:")); 1594 switch (function) { 1595 case CARDBUS_IO_ENABLE: 1596 command |= PCI_COMMAND_IO_ENABLE; 1597 break; 1598 case CARDBUS_IO_DISABLE: 1599 command &= ~PCI_COMMAND_IO_ENABLE; 1600 break; 1601 case CARDBUS_MEM_ENABLE: 1602 command |= PCI_COMMAND_MEM_ENABLE; 1603 break; 1604 case CARDBUS_MEM_DISABLE: 1605 command &= ~PCI_COMMAND_MEM_ENABLE; 1606 break; 1607 case CARDBUS_BM_ENABLE: 1608 command |= PCI_COMMAND_MASTER_ENABLE; 1609 break; 1610 case CARDBUS_BM_DISABLE: 1611 command &= ~PCI_COMMAND_MASTER_ENABLE; 1612 break; 1613 default: 1614 return 0; 1615 } 1616 1617 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1618 DPRINTF((" command reg 0x%x\n", command)); 1619 return 1; 1620 } 1621 1622 #if !rbus 1623 static int 1624 pccbb_io_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 1625 { 1626 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1627 int basereg; 1628 int limitreg; 1629 1630 if ((win < 0) || (win > 2)) { 1631 #if defined DIAGNOSTIC 1632 printf("cardbus_io_open: window out of range %d\n", win); 1633 #endif 1634 return 0; 1635 } 1636 1637 basereg = win * 8 + 0x2c; 1638 limitreg = win * 8 + 0x30; 1639 1640 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1641 start, basereg, end, limitreg)); 1642 1643 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1644 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1645 return 1; 1646 } 1647 1648 /* 1649 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1650 */ 1651 static int 1652 pccbb_io_close(cardbus_chipset_tag_t ct, int win) 1653 { 1654 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1655 int basereg; 1656 int limitreg; 1657 1658 if ((win < 0) || (win > 2)) { 1659 #if defined DIAGNOSTIC 1660 printf("cardbus_io_close: window out of range %d\n", win); 1661 #endif 1662 return 0; 1663 } 1664 1665 basereg = win * 8 + 0x2c; 1666 limitreg = win * 8 + 0x30; 1667 1668 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1669 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1670 return 1; 1671 } 1672 1673 static int 1674 pccbb_mem_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 1675 { 1676 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1677 int basereg; 1678 int limitreg; 1679 1680 if ((win < 0) || (win > 2)) { 1681 #if defined DIAGNOSTIC 1682 printf("cardbus_mem_open: window out of range %d\n", win); 1683 #endif 1684 return 0; 1685 } 1686 1687 basereg = win * 8 + 0x1c; 1688 limitreg = win * 8 + 0x20; 1689 1690 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1691 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1692 return 1; 1693 } 1694 1695 static int 1696 pccbb_mem_close(cardbus_chipset_tag_t ct, int win) 1697 { 1698 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1699 int basereg; 1700 int limitreg; 1701 1702 if ((win < 0) || (win > 2)) { 1703 #if defined DIAGNOSTIC 1704 printf("cardbus_mem_close: window out of range %d\n", win); 1705 #endif 1706 return 0; 1707 } 1708 1709 basereg = win * 8 + 0x1c; 1710 limitreg = win * 8 + 0x20; 1711 1712 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1713 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1714 return 1; 1715 } 1716 #endif 1717 1718 /* 1719 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1720 * int irq, 1721 * int level, 1722 * int (* func)(void *), 1723 * void *arg) 1724 * 1725 * This function registers an interrupt handler at the bridge, in 1726 * order not to call the interrupt handlers of child devices when 1727 * a card-deletion interrupt occurs. 1728 * 1729 * The arguments irq and level are not used. 1730 */ 1731 static void * 1732 pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, int irq, int level, 1733 int (*func)(void *), void *arg) 1734 { 1735 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1736 1737 return pccbb_intr_establish(sc, irq, level, func, arg); 1738 } 1739 1740 1741 /* 1742 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1743 * void *ih) 1744 * 1745 * This function removes an interrupt handler pointed by ih. 1746 */ 1747 static void 1748 pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih) 1749 { 1750 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1751 1752 pccbb_intr_disestablish(sc, ih); 1753 } 1754 1755 1756 void 1757 pccbb_intr_route(struct pccbb_softc *sc) 1758 { 1759 pcireg_t bcr, cbctrl; 1760 1761 /* initialize bridge intr routing */ 1762 bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1763 bcr &= ~CB_BCR_INTR_IREQ_ENABLE; 1764 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr); 1765 1766 switch (sc->sc_chipset) { 1767 case CB_TI113X: 1768 cbctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1769 /* functional intr enabled */ 1770 cbctrl |= PCI113X_CBCTRL_PCI_INTR; 1771 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, cbctrl); 1772 break; 1773 default: 1774 break; 1775 } 1776 } 1777 1778 /* 1779 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1780 * int irq, 1781 * int level, 1782 * int (* func)(void *), 1783 * void *arg) 1784 * 1785 * This function registers an interrupt handler at the bridge, in 1786 * order not to call the interrupt handlers of child devices when 1787 * a card-deletion interrupt occurs. 1788 * 1789 * The arguments irq is not used because pccbb selects intr vector. 1790 */ 1791 static void * 1792 pccbb_intr_establish(struct pccbb_softc *sc, int irq, int level, 1793 int (*func)(void *), void *arg) 1794 { 1795 struct pccbb_intrhand_list *pil, *newpil; 1796 1797 DPRINTF(("pccbb_intr_establish start. %p\n", LIST_FIRST(&sc->sc_pil))); 1798 1799 if (LIST_EMPTY(&sc->sc_pil)) { 1800 pccbb_intr_route(sc); 1801 } 1802 1803 /* 1804 * Allocate a room for interrupt handler structure. 1805 */ 1806 if (NULL == (newpil = 1807 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1808 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1809 return NULL; 1810 } 1811 1812 newpil->pil_func = func; 1813 newpil->pil_arg = arg; 1814 newpil->pil_icookie = makeiplcookie(level); 1815 1816 if (LIST_EMPTY(&sc->sc_pil)) { 1817 LIST_INSERT_HEAD(&sc->sc_pil, newpil, pil_next); 1818 } else { 1819 for (pil = LIST_FIRST(&sc->sc_pil); 1820 LIST_NEXT(pil, pil_next) != NULL; 1821 pil = LIST_NEXT(pil, pil_next)); 1822 LIST_INSERT_AFTER(pil, newpil, pil_next); 1823 } 1824 1825 DPRINTF(("pccbb_intr_establish add pil. %p\n", 1826 LIST_FIRST(&sc->sc_pil))); 1827 1828 return newpil; 1829 } 1830 1831 /* 1832 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1833 * void *ih) 1834 * 1835 * This function removes an interrupt handler pointed by ih. ih 1836 * should be the value returned by cardbus_intr_establish() or 1837 * NULL. 1838 * 1839 * When ih is NULL, this function will do nothing. 1840 */ 1841 static void 1842 pccbb_intr_disestablish(struct pccbb_softc *sc, void *ih) 1843 { 1844 struct pccbb_intrhand_list *pil; 1845 pcireg_t reg; 1846 1847 DPRINTF(("pccbb_intr_disestablish start. %p\n", 1848 LIST_FIRST(&sc->sc_pil))); 1849 1850 if (ih == NULL) { 1851 /* intr handler is not set */ 1852 DPRINTF(("pccbb_intr_disestablish: no ih\n")); 1853 return; 1854 } 1855 1856 #ifdef DIAGNOSTIC 1857 for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1858 pil = LIST_NEXT(pil, pil_next)) { 1859 DPRINTF(("pccbb_intr_disestablish: pil %p\n", pil)); 1860 if (pil == ih) { 1861 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1862 break; 1863 } 1864 } 1865 if (pil == NULL) { 1866 panic("pccbb_intr_disestablish: %s cannot find pil %p", 1867 sc->sc_dev.dv_xname, ih); 1868 } 1869 #endif 1870 1871 pil = (struct pccbb_intrhand_list *)ih; 1872 LIST_REMOVE(pil, pil_next); 1873 free(pil, M_DEVBUF); 1874 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1875 1876 if (LIST_EMPTY(&sc->sc_pil)) { 1877 /* No interrupt handlers */ 1878 1879 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1880 1881 /* stop routing PCI intr */ 1882 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1883 reg |= CB_BCR_INTR_IREQ_ENABLE; 1884 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, reg); 1885 1886 switch (sc->sc_chipset) { 1887 case CB_TI113X: 1888 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1889 /* functional intr disabled */ 1890 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1891 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1892 break; 1893 default: 1894 break; 1895 } 1896 } 1897 } 1898 1899 #if defined SHOW_REGS 1900 static void 1901 cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, bus_space_tag_t memt, 1902 bus_space_handle_t memh) 1903 { 1904 int i; 1905 printf("PCI config regs:"); 1906 for (i = 0; i < 0x50; i += 4) { 1907 if (i % 16 == 0) 1908 printf("\n 0x%02x:", i); 1909 printf(" %08x", pci_conf_read(pc, tag, i)); 1910 } 1911 for (i = 0x80; i < 0xb0; i += 4) { 1912 if (i % 16 == 0) 1913 printf("\n 0x%02x:", i); 1914 printf(" %08x", pci_conf_read(pc, tag, i)); 1915 } 1916 1917 if (memh == 0) { 1918 printf("\n"); 1919 return; 1920 } 1921 1922 printf("\nsocket regs:"); 1923 for (i = 0; i <= 0x10; i += 0x04) 1924 printf(" %08x", bus_space_read_4(memt, memh, i)); 1925 printf("\nExCA regs:"); 1926 for (i = 0; i < 0x08; ++i) 1927 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1928 printf("\n"); 1929 return; 1930 } 1931 #endif 1932 1933 /* 1934 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1935 * int busno, int function) 1936 * This is the function to make a tag to access config space of 1937 * a CardBus Card. It works same as pci_conf_read. 1938 */ 1939 static cardbustag_t 1940 pccbb_make_tag(cardbus_chipset_tag_t cc, int busno, int function) 1941 { 1942 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1943 1944 return pci_make_tag(sc->sc_pc, busno, 0, function); 1945 } 1946 1947 static void 1948 pccbb_free_tag(cardbus_chipset_tag_t cc, cardbustag_t tag) 1949 { 1950 } 1951 1952 /* 1953 * pccbb_conf_read 1954 * 1955 * This is the function to read the config space of a CardBus card. 1956 * It works the same as pci_conf_read(9). 1957 */ 1958 static cardbusreg_t 1959 pccbb_conf_read(cardbus_chipset_tag_t cc, cardbustag_t tag, int offset) 1960 { 1961 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1962 1963 return pci_conf_read(sc->sc_pc, tag, offset); 1964 } 1965 1966 /* 1967 * pccbb_conf_write 1968 * 1969 * This is the function to write the config space of a CardBus 1970 * card. It works the same as pci_conf_write(9). 1971 */ 1972 static void 1973 pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, int reg, 1974 cardbusreg_t val) 1975 { 1976 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1977 1978 pci_conf_write(sc->sc_pc, tag, reg, val); 1979 } 1980 1981 #if 0 1982 STATIC int 1983 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1984 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 1985 int speed, int flags, 1986 bus_space_handle_t * iohp) 1987 #endif 1988 /* 1989 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1990 * bus_addr_t start, bus_size_t size, 1991 * bus_size_t align, 1992 * struct pcmcia_io_handle *pcihp 1993 * 1994 * This function only allocates I/O region for pccard. This function 1995 * never maps the allocated region to pccard I/O area. 1996 * 1997 * XXX: The interface of this function is not very good, I believe. 1998 */ 1999 STATIC int 2000 pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, 2001 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 2002 { 2003 struct pcic_handle *ph = (struct pcic_handle *)pch; 2004 bus_addr_t ioaddr; 2005 int flags = 0; 2006 bus_space_tag_t iot; 2007 bus_space_handle_t ioh; 2008 bus_addr_t mask; 2009 #if rbus 2010 rbus_tag_t rb; 2011 #endif 2012 if (align == 0) { 2013 align = size; /* XXX: funny??? */ 2014 } 2015 2016 if (start != 0) { 2017 /* XXX: assume all card decode lower 10 bits by its hardware */ 2018 mask = 0x3ff; 2019 /* enforce to use only masked address */ 2020 start &= mask; 2021 } else { 2022 /* 2023 * calculate mask: 2024 * 1. get the most significant bit of size (call it msb). 2025 * 2. compare msb with the value of size. 2026 * 3. if size is larger, shift msb left once. 2027 * 4. obtain mask value to decrement msb. 2028 */ 2029 bus_size_t size_tmp = size; 2030 int shifts = 0; 2031 2032 mask = 1; 2033 while (size_tmp) { 2034 ++shifts; 2035 size_tmp >>= 1; 2036 } 2037 mask = (1 << shifts); 2038 if (mask < size) { 2039 mask <<= 1; 2040 } 2041 --mask; 2042 } 2043 2044 /* 2045 * Allocate some arbitrary I/O space. 2046 */ 2047 2048 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 2049 2050 #if rbus 2051 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 2052 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 2053 return 1; 2054 } 2055 DPRINTF(("pccbb_pcmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2056 (u_long) ioaddr, (u_long) size)); 2057 #else 2058 if (start) { 2059 ioaddr = start; 2060 if (bus_space_map(iot, start, size, 0, &ioh)) { 2061 return 1; 2062 } 2063 DPRINTF(("pccbb_pcmcia_io_alloc map port 0x%lx+0x%lx\n", 2064 (u_long) ioaddr, (u_long) size)); 2065 } else { 2066 flags |= PCMCIA_IO_ALLOCATED; 2067 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 2068 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 2069 size, align, 0, 0, &ioaddr, &ioh)) { 2070 /* No room be able to be get. */ 2071 return 1; 2072 } 2073 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2074 (u_long) ioaddr, (u_long) size)); 2075 } 2076 #endif 2077 2078 pcihp->iot = iot; 2079 pcihp->ioh = ioh; 2080 pcihp->addr = ioaddr; 2081 pcihp->size = size; 2082 pcihp->flags = flags; 2083 2084 return 0; 2085 } 2086 2087 /* 2088 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2089 * struct pcmcia_io_handle *pcihp) 2090 * 2091 * This function only frees I/O region for pccard. 2092 * 2093 * XXX: The interface of this function is not very good, I believe. 2094 */ 2095 void 2096 pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2097 struct pcmcia_io_handle *pcihp) 2098 { 2099 #if !rbus 2100 bus_space_tag_t iot = pcihp->iot; 2101 #endif 2102 bus_space_handle_t ioh = pcihp->ioh; 2103 bus_size_t size = pcihp->size; 2104 2105 #if rbus 2106 struct pccbb_softc *sc = 2107 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 2108 rbus_tag_t rb = sc->sc_rbus_iot; 2109 2110 rbus_space_free(rb, ioh, size, NULL); 2111 #else 2112 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 2113 bus_space_free(iot, ioh, size); 2114 else 2115 bus_space_unmap(iot, ioh, size); 2116 #endif 2117 } 2118 2119 /* 2120 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 2121 * bus_addr_t offset, bus_size_t size, 2122 * struct pcmcia_io_handle *pcihp, 2123 * int *windowp) 2124 * 2125 * This function maps the allocated I/O region to pccard. This function 2126 * never allocates any I/O region for pccard I/O area. I don't 2127 * understand why the original authors of pcmciabus separated alloc and 2128 * map. I believe the two must be unite. 2129 * 2130 * XXX: no wait timing control? 2131 */ 2132 int 2133 pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, bus_addr_t offset, 2134 bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp) 2135 { 2136 struct pcic_handle *ph = (struct pcic_handle *)pch; 2137 bus_addr_t ioaddr = pcihp->addr + offset; 2138 int i, win; 2139 #if defined CBB_DEBUG 2140 static const char *width_names[] = { "dynamic", "io8", "io16" }; 2141 #endif 2142 2143 /* Sanity check I/O handle. */ 2144 2145 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 2146 panic("pccbb_pcmcia_io_map iot is bogus"); 2147 } 2148 2149 /* XXX Sanity check offset/size. */ 2150 2151 win = -1; 2152 for (i = 0; i < PCIC_IO_WINS; i++) { 2153 if ((ph->ioalloc & (1 << i)) == 0) { 2154 win = i; 2155 ph->ioalloc |= (1 << i); 2156 break; 2157 } 2158 } 2159 2160 if (win == -1) { 2161 return 1; 2162 } 2163 2164 *windowp = win; 2165 2166 /* XXX this is pretty gross */ 2167 2168 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2169 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2170 2171 /* XXX wtf is this doing here? */ 2172 2173 #if 0 2174 printf(" port 0x%lx", (u_long) ioaddr); 2175 if (size > 1) { 2176 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2177 } 2178 #endif 2179 2180 ph->io[win].addr = ioaddr; 2181 ph->io[win].size = size; 2182 ph->io[win].width = width; 2183 2184 /* actual dirty register-value changing in the function below. */ 2185 pccbb_pcmcia_do_io_map(ph, win); 2186 2187 return 0; 2188 } 2189 2190 /* 2191 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2192 * 2193 * This function changes register-value to map I/O region for pccard. 2194 */ 2195 static void 2196 pccbb_pcmcia_do_io_map(struct pcic_handle *ph, int win) 2197 { 2198 static u_int8_t pcic_iowidth[3] = { 2199 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2200 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2201 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2202 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2203 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2204 }; 2205 2206 #define PCIC_SIA_START_LOW 0 2207 #define PCIC_SIA_START_HIGH 1 2208 #define PCIC_SIA_STOP_LOW 2 2209 #define PCIC_SIA_STOP_HIGH 3 2210 2211 int regbase_win = 0x8 + win * 0x04; 2212 u_int8_t ioctl, enable; 2213 2214 DPRINTF(("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx " 2215 "width %d\n", win, (unsigned long)ph->io[win].addr, 2216 (unsigned long)ph->io[win].size, ph->io[win].width * 8)); 2217 2218 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2219 ph->io[win].addr & 0xff); 2220 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2221 (ph->io[win].addr >> 8) & 0xff); 2222 2223 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2224 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2225 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2226 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2227 2228 ioctl = Pcic_read(ph, PCIC_IOCTL); 2229 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2230 switch (win) { 2231 case 0: 2232 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2233 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2234 PCIC_IOCTL_IO0_DATASIZE_MASK); 2235 ioctl |= pcic_iowidth[ph->io[win].width]; 2236 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2237 break; 2238 case 1: 2239 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2240 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2241 PCIC_IOCTL_IO1_DATASIZE_MASK); 2242 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2243 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2244 break; 2245 } 2246 Pcic_write(ph, PCIC_IOCTL, ioctl); 2247 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2248 #if defined(CBB_DEBUG) 2249 { 2250 u_int8_t start_low = 2251 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2252 u_int8_t start_high = 2253 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2254 u_int8_t stop_low = 2255 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2256 u_int8_t stop_high = 2257 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2258 printf("pccbb_pcmcia_do_io_map start %02x %02x, " 2259 "stop %02x %02x, ioctl %02x enable %02x\n", 2260 start_low, start_high, stop_low, stop_high, ioctl, enable); 2261 } 2262 #endif 2263 } 2264 2265 /* 2266 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2267 * 2268 * This function unmaps I/O region. No return value. 2269 */ 2270 STATIC void 2271 pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t pch, int win) 2272 { 2273 struct pcic_handle *ph = (struct pcic_handle *)pch; 2274 int reg; 2275 2276 if (win >= PCIC_IO_WINS || win < 0) { 2277 panic("pccbb_pcmcia_io_unmap: window out of range"); 2278 } 2279 2280 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2281 switch (win) { 2282 case 0: 2283 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2284 break; 2285 case 1: 2286 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2287 break; 2288 } 2289 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2290 2291 ph->ioalloc &= ~(1 << win); 2292 } 2293 2294 static int 2295 pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 2296 { 2297 u_int8_t stat; 2298 int i; 2299 2300 /* wait an initial 10ms for quick cards */ 2301 stat = Pcic_read(ph, PCIC_IF_STATUS); 2302 if (stat & PCIC_IF_STATUS_READY) 2303 return (0); 2304 pccbb_pcmcia_delay(ph, 10, "pccwr0"); 2305 for (i = 0; i < 50; i++) { 2306 stat = Pcic_read(ph, PCIC_IF_STATUS); 2307 if (stat & PCIC_IF_STATUS_READY) 2308 return (0); 2309 if ((stat & PCIC_IF_STATUS_CARDDETECT_MASK) != 2310 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2311 return (ENXIO); 2312 /* wait .1s (100ms) each iteration now */ 2313 pccbb_pcmcia_delay(ph, 100, "pccwr1"); 2314 } 2315 2316 printf("pccbb_pcmcia_wait_ready: ready never happened, status=%02x\n", stat); 2317 return (EWOULDBLOCK); 2318 } 2319 2320 /* 2321 * Perform long (msec order) delay. timo is in milliseconds. 2322 */ 2323 static void 2324 pccbb_pcmcia_delay(struct pcic_handle *ph, int timo, const char *wmesg) 2325 { 2326 #ifdef DIAGNOSTIC 2327 if (timo <= 0) 2328 panic("pccbb_pcmcia_delay: called with timeout %d", timo); 2329 if (!curlwp) 2330 panic("pccbb_pcmcia_delay: called in interrupt context"); 2331 #if 0 2332 if (!ph->event_thread) 2333 panic("pccbb_pcmcia_delay: no event thread"); 2334 #endif 2335 #endif 2336 DPRINTF(("pccbb_pcmcia_delay: \"%s\" %p, sleep %d ms\n", 2337 wmesg, ph->event_thread, timo)); 2338 tsleep(pccbb_pcmcia_delay, PWAIT, wmesg, roundup(timo * hz, 1000) / 1000); 2339 } 2340 2341 /* 2342 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2343 * 2344 * This function enables the card. All information is stored in 2345 * the first argument, pcmcia_chipset_handle_t. 2346 */ 2347 STATIC void 2348 pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2349 { 2350 struct pcic_handle *ph = (struct pcic_handle *)pch; 2351 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2352 pcireg_t spsr; 2353 int voltage; 2354 int win; 2355 u_int8_t power, intr; 2356 #ifdef DIAGNOSTIC 2357 int reg; 2358 #endif 2359 2360 /* this bit is mostly stolen from pcic_attach_card */ 2361 2362 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2363 2364 /* get card Vcc info */ 2365 spsr = 2366 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2367 CB_SOCKET_STAT); 2368 if (spsr & CB_SOCKET_STAT_5VCARD) { 2369 DPRINTF(("5V card\n")); 2370 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2371 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2372 DPRINTF(("3V card\n")); 2373 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2374 } else { 2375 DPRINTF(("?V card, 0x%x\n", spsr)); /* XXX */ 2376 return; 2377 } 2378 2379 /* disable interrupts; assert RESET */ 2380 intr = Pcic_read(ph, PCIC_INTR); 2381 intr &= PCIC_INTR_ENABLE; 2382 Pcic_write(ph, PCIC_INTR, intr); 2383 2384 /* zero out the address windows */ 2385 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2386 2387 /* power down the socket to reset it, clear the card reset pin */ 2388 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2389 2390 /* power off; assert output enable bit */ 2391 power = PCIC_PWRCTL_OE; 2392 Pcic_write(ph, PCIC_PWRCTL, power); 2393 2394 /* power up the socket */ 2395 if (pccbb_power(sc, voltage) == 0) 2396 return; 2397 2398 /* 2399 * Table 4-18 and figure 4-6 of the PC Card specifiction say: 2400 * Vcc Rising Time (Tpr) = 100ms (handled in pccbb_power() above) 2401 * RESET Width (Th (Hi-z RESET)) = 1ms 2402 * RESET Width (Tw (RESET)) = 10us 2403 * 2404 * some machines require some more time to be settled 2405 * for example old toshiba topic bridges! 2406 * (100ms is added here). 2407 */ 2408 pccbb_pcmcia_delay(ph, 200 + 1, "pccen1"); 2409 2410 /* negate RESET */ 2411 intr |= PCIC_INTR_RESET; 2412 Pcic_write(ph, PCIC_INTR, intr); 2413 2414 /* 2415 * RESET Setup Time (Tsu (RESET)) = 20ms 2416 */ 2417 pccbb_pcmcia_delay(ph, 20, "pccen2"); 2418 2419 #ifdef DIAGNOSTIC 2420 reg = Pcic_read(ph, PCIC_IF_STATUS); 2421 if ((reg & PCIC_IF_STATUS_POWERACTIVE) == 0) 2422 printf("pccbb_pcmcia_socket_enable: no power, status=%x\n", reg); 2423 #endif 2424 2425 /* wait for the chip to finish initializing */ 2426 if (pccbb_pcmcia_wait_ready(ph)) { 2427 #ifdef DIAGNOSTIC 2428 printf("pccbb_pcmcia_socket_enable: never became ready\n"); 2429 #endif 2430 /* XXX return a failure status?? */ 2431 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2432 Pcic_write(ph, PCIC_PWRCTL, 0); 2433 return; 2434 } 2435 2436 /* reinstall all the memory and io mappings */ 2437 for (win = 0; win < PCIC_MEM_WINS; ++win) 2438 if (ph->memalloc & (1 << win)) 2439 pccbb_pcmcia_do_mem_map(ph, win); 2440 for (win = 0; win < PCIC_IO_WINS; ++win) 2441 if (ph->ioalloc & (1 << win)) 2442 pccbb_pcmcia_do_io_map(ph, win); 2443 } 2444 2445 /* 2446 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2447 * 2448 * This function disables the card. All information is stored in 2449 * the first argument, pcmcia_chipset_handle_t. 2450 */ 2451 STATIC void 2452 pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t pch) 2453 { 2454 struct pcic_handle *ph = (struct pcic_handle *)pch; 2455 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2456 u_int8_t intr; 2457 2458 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2459 2460 /* disable interrupts; assert RESET */ 2461 intr = Pcic_read(ph, PCIC_INTR); 2462 intr &= PCIC_INTR_ENABLE; 2463 Pcic_write(ph, PCIC_INTR, intr); 2464 2465 /* zero out the address windows */ 2466 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2467 2468 /* power down the socket to reset it, clear the card reset pin */ 2469 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2470 2471 /* disable socket: negate output enable bit and power off */ 2472 Pcic_write(ph, PCIC_PWRCTL, 0); 2473 2474 /* 2475 * Vcc Falling Time (Tpf) = 300ms 2476 */ 2477 pccbb_pcmcia_delay(ph, 300, "pccwr1"); 2478 } 2479 2480 STATIC void 2481 pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t pch, int type) 2482 { 2483 struct pcic_handle *ph = (struct pcic_handle *)pch; 2484 u_int8_t intr; 2485 2486 /* set the card type */ 2487 2488 intr = Pcic_read(ph, PCIC_INTR); 2489 intr &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_CARDTYPE_MASK); 2490 if (type == PCMCIA_IFTYPE_IO) 2491 intr |= PCIC_INTR_CARDTYPE_IO; 2492 else 2493 intr |= PCIC_INTR_CARDTYPE_MEM; 2494 Pcic_write(ph, PCIC_INTR, intr); 2495 2496 DPRINTF(("%s: pccbb_pcmcia_socket_settype %02x type %s %02x\n", 2497 ph->ph_parent->dv_xname, ph->sock, 2498 ((type == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2499 } 2500 2501 /* 2502 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2503 * 2504 * This function detects whether a card is in the slot or not. 2505 * If a card is inserted, return 1. Otherwise, return 0. 2506 */ 2507 STATIC int 2508 pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch) 2509 { 2510 struct pcic_handle *ph = (struct pcic_handle *)pch; 2511 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2512 2513 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2514 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2515 } 2516 2517 #if 0 2518 STATIC int 2519 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2520 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2521 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2522 #endif 2523 /* 2524 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2525 * bus_size_t size, 2526 * struct pcmcia_mem_handle *pcmhp) 2527 * 2528 * This function only allocates memory region for pccard. This 2529 * function never maps the allocated region to pccard memory area. 2530 * 2531 * XXX: Why the argument of start address is not in? 2532 */ 2533 STATIC int 2534 pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 2535 struct pcmcia_mem_handle *pcmhp) 2536 { 2537 struct pcic_handle *ph = (struct pcic_handle *)pch; 2538 bus_space_handle_t memh; 2539 bus_addr_t addr; 2540 bus_size_t sizepg; 2541 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2542 #if rbus 2543 rbus_tag_t rb; 2544 #endif 2545 2546 /* Check that the card is still there. */ 2547 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2548 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2549 return 1; 2550 2551 /* out of sc->memh, allocate as many pages as necessary */ 2552 2553 /* convert size to PCIC pages */ 2554 /* 2555 * This is not enough; when the requested region is on the page 2556 * boundaries, this may calculate wrong result. 2557 */ 2558 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2559 #if 0 2560 if (sizepg > PCIC_MAX_MEM_PAGES) { 2561 return 1; 2562 } 2563 #endif 2564 2565 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2566 return 1; 2567 } 2568 2569 addr = 0; /* XXX gcc -Wuninitialized */ 2570 2571 #if rbus 2572 rb = sc->sc_rbus_memt; 2573 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2574 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2575 &addr, &memh)) { 2576 return 1; 2577 } 2578 #else 2579 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2580 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2581 0, /* boundary */ 2582 0, /* flags */ 2583 &addr, &memh)) { 2584 return 1; 2585 } 2586 #endif 2587 2588 DPRINTF(("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, " 2589 "realsize 0x%lx\n", (unsigned long)addr, (unsigned long)size, 2590 (unsigned long)sizepg * PCIC_MEM_PAGESIZE)); 2591 2592 pcmhp->memt = sc->sc_memt; 2593 pcmhp->memh = memh; 2594 pcmhp->addr = addr; 2595 pcmhp->size = size; 2596 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2597 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2598 pcmhp->mhandle = 0; 2599 /* No offset??? Funny. */ 2600 2601 return 0; 2602 } 2603 2604 /* 2605 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2606 * struct pcmcia_mem_handle *pcmhp) 2607 * 2608 * This function release the memory space allocated by the function 2609 * pccbb_pcmcia_mem_alloc(). 2610 */ 2611 STATIC void 2612 pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2613 struct pcmcia_mem_handle *pcmhp) 2614 { 2615 #if rbus 2616 struct pcic_handle *ph = (struct pcic_handle *)pch; 2617 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2618 2619 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2620 #else 2621 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2622 #endif 2623 } 2624 2625 /* 2626 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2627 * 2628 * This function release the memory space allocated by the function 2629 * pccbb_pcmcia_mem_alloc(). 2630 */ 2631 STATIC void 2632 pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2633 { 2634 int regbase_win; 2635 bus_addr_t phys_addr; 2636 bus_addr_t phys_end; 2637 2638 #define PCIC_SMM_START_LOW 0 2639 #define PCIC_SMM_START_HIGH 1 2640 #define PCIC_SMM_STOP_LOW 2 2641 #define PCIC_SMM_STOP_HIGH 3 2642 #define PCIC_CMA_LOW 4 2643 #define PCIC_CMA_HIGH 5 2644 2645 u_int8_t start_low, start_high = 0; 2646 u_int8_t stop_low, stop_high; 2647 u_int8_t off_low, off_high; 2648 u_int8_t mem_window; 2649 int reg; 2650 2651 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2652 int mem8 = 2653 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2654 || (kind == PCMCIA_MEM_ATTR); 2655 2656 regbase_win = 0x10 + win * 0x08; 2657 2658 phys_addr = ph->mem[win].addr; 2659 phys_end = phys_addr + ph->mem[win].size; 2660 2661 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2662 (unsigned long)phys_addr, (unsigned long)phys_end, 2663 (unsigned long)ph->mem[win].offset)); 2664 2665 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2666 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2667 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2668 2669 /* bit 19:12 */ 2670 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2671 /* bit 23:20 and bit 7 on */ 2672 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2673 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2674 /* bit 31:24, for 32-bit address */ 2675 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2676 2677 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2678 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2679 2680 if (((struct pccbb_softc *)ph-> 2681 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2682 Pcic_write(ph, 0x40 + win, mem_window); 2683 } 2684 2685 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2686 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2687 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2688 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2689 2690 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2691 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2692 2693 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2694 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2695 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2696 | ((kind == PCMCIA_MEM_ATTR) ? 2697 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2698 2699 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2700 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2701 2702 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2703 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2704 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2705 2706 #if defined(CBB_DEBUG) 2707 { 2708 int r1, r2, r3, r4, r5, r6, r7 = 0; 2709 2710 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2711 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2712 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2713 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2714 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2715 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2716 if (((struct pccbb_softc *)(ph-> 2717 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2718 r7 = Pcic_read(ph, 0x40 + win); 2719 } 2720 2721 printf("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2722 "%02x%02x", win, r1, r2, r3, r4, r5, r6); 2723 if (((struct pccbb_softc *)(ph-> 2724 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2725 printf(" %02x", r7); 2726 } 2727 printf("\n"); 2728 } 2729 #endif 2730 } 2731 2732 /* 2733 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2734 * bus_addr_t card_addr, bus_size_t size, 2735 * struct pcmcia_mem_handle *pcmhp, 2736 * bus_addr_t *offsetp, int *windowp) 2737 * 2738 * This function maps memory space allocated by the function 2739 * pccbb_pcmcia_mem_alloc(). 2740 */ 2741 STATIC int 2742 pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2743 bus_addr_t card_addr, bus_size_t size, struct pcmcia_mem_handle *pcmhp, 2744 bus_addr_t *offsetp, int *windowp) 2745 { 2746 struct pcic_handle *ph = (struct pcic_handle *)pch; 2747 bus_addr_t busaddr; 2748 long card_offset; 2749 int win; 2750 2751 /* Check that the card is still there. */ 2752 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2753 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2754 return 1; 2755 2756 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2757 if ((ph->memalloc & (1 << win)) == 0) { 2758 ph->memalloc |= (1 << win); 2759 break; 2760 } 2761 } 2762 2763 if (win == PCIC_MEM_WINS) { 2764 return 1; 2765 } 2766 2767 *windowp = win; 2768 2769 /* XXX this is pretty gross */ 2770 2771 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2772 panic("pccbb_pcmcia_mem_map memt is bogus"); 2773 } 2774 2775 busaddr = pcmhp->addr; 2776 2777 /* 2778 * compute the address offset to the pcmcia address space for the 2779 * pcic. this is intentionally signed. The masks and shifts below 2780 * will cause TRT to happen in the pcic registers. Deal with making 2781 * sure the address is aligned, and return the alignment offset. 2782 */ 2783 2784 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2785 card_addr -= *offsetp; 2786 2787 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2788 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2789 (u_long) card_addr)); 2790 2791 /* 2792 * include the offset in the size, and decrement size by one, since 2793 * the hw wants start/stop 2794 */ 2795 size += *offsetp - 1; 2796 2797 card_offset = (((long)card_addr) - ((long)busaddr)); 2798 2799 ph->mem[win].addr = busaddr; 2800 ph->mem[win].size = size; 2801 ph->mem[win].offset = card_offset; 2802 ph->mem[win].kind = kind; 2803 2804 pccbb_pcmcia_do_mem_map(ph, win); 2805 2806 return 0; 2807 } 2808 2809 /* 2810 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2811 * int window) 2812 * 2813 * This function unmaps memory space which mapped by the function 2814 * pccbb_pcmcia_mem_map(). 2815 */ 2816 STATIC void 2817 pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, int window) 2818 { 2819 struct pcic_handle *ph = (struct pcic_handle *)pch; 2820 int reg; 2821 2822 if (window >= PCIC_MEM_WINS) { 2823 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2824 } 2825 2826 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2827 reg &= ~(1 << window); 2828 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2829 2830 ph->memalloc &= ~(1 << window); 2831 } 2832 2833 #if defined PCCBB_PCMCIA_POLL 2834 struct pccbb_poll_str { 2835 void *arg; 2836 int (*func)(void *); 2837 int level; 2838 struct pcic_handle *ph; 2839 int count; 2840 int num; 2841 struct callout poll_ch; 2842 }; 2843 2844 static struct pccbb_poll_str pccbb_poll[10]; 2845 static int pccbb_poll_n = 0; 2846 2847 static void pccbb_pcmcia_poll(void *arg); 2848 2849 static void 2850 pccbb_pcmcia_poll(void *arg) 2851 { 2852 struct pccbb_poll_str *poll = arg; 2853 struct pcic_handle *ph = poll->ph; 2854 struct pccbb_softc *sc = ph->sc; 2855 int s; 2856 u_int32_t spsr; /* socket present-state reg */ 2857 2858 callout_reset(&poll->poll_ch, hz * 2, pccbb_pcmcia_poll, arg); 2859 switch (poll->level) { 2860 case IPL_NET: 2861 s = splnet(); 2862 break; 2863 case IPL_BIO: 2864 s = splbio(); 2865 break; 2866 case IPL_TTY: /* fallthrough */ 2867 default: 2868 s = spltty(); 2869 break; 2870 } 2871 2872 spsr = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2873 CB_SOCKET_STAT); 2874 2875 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2876 if (!(spsr & 0x40)) /* CINT low */ 2877 #else 2878 if (1) 2879 #endif 2880 { 2881 if ((*poll->func) (poll->arg) > 0) { 2882 ++poll->count; 2883 /* printf("intr: reported from poller, 0x%x\n", spsr); */ 2884 #if defined LEVEL2 2885 } else { 2886 printf("intr: miss! 0x%x\n", spsr); 2887 #endif 2888 } 2889 } 2890 splx(s); 2891 } 2892 #endif /* defined CB_PCMCIA_POLL */ 2893 2894 /* 2895 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2896 * struct pcmcia_function *pf, 2897 * int ipl, 2898 * int (*func)(void *), 2899 * void *arg); 2900 * 2901 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2902 */ 2903 STATIC void * 2904 pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2905 struct pcmcia_function *pf, int ipl, int (*func)(void *), void *arg) 2906 { 2907 struct pcic_handle *ph = (struct pcic_handle *)pch; 2908 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2909 2910 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2911 /* what should I do? */ 2912 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2913 DPRINTF(("%s does not provide edge nor pulse " 2914 "interrupt\n", sc->sc_dev.dv_xname)); 2915 return NULL; 2916 } 2917 /* 2918 * XXX Noooooo! The interrupt flag must set properly!! 2919 * dumb pcmcia driver!! 2920 */ 2921 } 2922 2923 return pccbb_intr_establish(sc, 0, ipl, func, arg); 2924 } 2925 2926 /* 2927 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2928 * void *ih) 2929 * 2930 * This function disables PC-Card interrupt. 2931 */ 2932 STATIC void 2933 pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 2934 { 2935 struct pcic_handle *ph = (struct pcic_handle *)pch; 2936 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2937 2938 pccbb_intr_disestablish(sc, ih); 2939 } 2940 2941 #if rbus 2942 /* 2943 * static int 2944 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2945 * bus_addr_t addr, bus_size_t size, 2946 * bus_addr_t mask, bus_size_t align, 2947 * int flags, bus_addr_t *addrp; 2948 * bus_space_handle_t *bshp) 2949 * 2950 * This function allocates a portion of memory or io space for 2951 * clients. This function is called from CardBus card drivers. 2952 */ 2953 static int 2954 pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2955 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 2956 int flags, bus_addr_t *addrp, bus_space_handle_t *bshp) 2957 { 2958 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2959 2960 DPRINTF(("pccbb_rbus_cb_space_alloc: addr 0x%lx, size 0x%lx, " 2961 "mask 0x%lx, align 0x%lx\n", (unsigned long)addr, 2962 (unsigned long)size, (unsigned long)mask, (unsigned long)align)); 2963 2964 if (align == 0) { 2965 align = size; 2966 } 2967 2968 if (rb->rb_bt == sc->sc_memt) { 2969 if (align < 16) { 2970 return 1; 2971 } 2972 /* 2973 * XXX: align more than 0x1000 to avoid overwrapping 2974 * memory windows for two or more devices. 0x1000 2975 * means memory window's granularity. 2976 * 2977 * Two or more devices should be able to share same 2978 * memory window region. However, overrapping memory 2979 * window is not good because some devices, such as 2980 * 3Com 3C575[BC], have a broken address decoder and 2981 * intrude other's memory region. 2982 */ 2983 if (align < 0x1000) { 2984 align = 0x1000; 2985 } 2986 } else if (rb->rb_bt == sc->sc_iot) { 2987 if (align < 4) { 2988 return 1; 2989 } 2990 /* XXX: hack for avoiding ISA image */ 2991 if (mask < 0x0100) { 2992 mask = 0x3ff; 2993 addr = 0x300; 2994 } 2995 2996 } else { 2997 DPRINTF(("pccbb_rbus_cb_space_alloc: Bus space tag 0x%lx is " 2998 "NOT used. io: 0x%lx, mem: 0x%lx\n", 2999 (unsigned long)rb->rb_bt, (unsigned long)sc->sc_iot, 3000 (unsigned long)sc->sc_memt)); 3001 return 1; 3002 /* XXX: panic here? */ 3003 } 3004 3005 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 3006 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 3007 return 1; 3008 } 3009 3010 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 3011 3012 return 0; 3013 } 3014 3015 /* 3016 * static int 3017 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 3018 * bus_space_handle_t *bshp, bus_size_t size); 3019 * 3020 * This function is called from CardBus card drivers. 3021 */ 3022 static int 3023 pccbb_rbus_cb_space_free(cardbus_chipset_tag_t ct, rbus_tag_t rb, 3024 bus_space_handle_t bsh, bus_size_t size) 3025 { 3026 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 3027 bus_space_tag_t bt = rb->rb_bt; 3028 3029 pccbb_close_win(sc, bt, bsh, size); 3030 3031 if (bt == sc->sc_memt) { 3032 } else if (bt == sc->sc_iot) { 3033 } else { 3034 return 1; 3035 /* XXX: panic here? */ 3036 } 3037 3038 return rbus_space_free(rb, bsh, size, NULL); 3039 } 3040 #endif /* rbus */ 3041 3042 #if rbus 3043 3044 static int 3045 pccbb_open_win(struct pccbb_softc *sc, bus_space_tag_t bst, bus_addr_t addr, 3046 bus_size_t size, bus_space_handle_t bsh, int flags) 3047 { 3048 struct pccbb_win_chain_head *head; 3049 bus_addr_t align; 3050 3051 head = &sc->sc_iowindow; 3052 align = 0x04; 3053 if (sc->sc_memt == bst) { 3054 head = &sc->sc_memwindow; 3055 align = 0x1000; 3056 DPRINTF(("using memory window, 0x%lx 0x%lx 0x%lx\n\n", 3057 (unsigned long)sc->sc_iot, (unsigned long)sc->sc_memt, 3058 (unsigned long)bst)); 3059 } 3060 3061 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 3062 printf("%s: pccbb_open_win: %s winlist insert failed\n", 3063 sc->sc_dev.dv_xname, 3064 (head == &sc->sc_memwindow) ? "mem" : "io"); 3065 } 3066 pccbb_winset(align, sc, bst); 3067 3068 return 0; 3069 } 3070 3071 static int 3072 pccbb_close_win(struct pccbb_softc *sc, bus_space_tag_t bst, 3073 bus_space_handle_t bsh, bus_size_t size) 3074 { 3075 struct pccbb_win_chain_head *head; 3076 bus_addr_t align; 3077 3078 head = &sc->sc_iowindow; 3079 align = 0x04; 3080 if (sc->sc_memt == bst) { 3081 head = &sc->sc_memwindow; 3082 align = 0x1000; 3083 } 3084 3085 if (pccbb_winlist_delete(head, bsh, size)) { 3086 printf("%s: pccbb_close_win: %s winlist delete failed\n", 3087 sc->sc_dev.dv_xname, 3088 (head == &sc->sc_memwindow) ? "mem" : "io"); 3089 } 3090 pccbb_winset(align, sc, bst); 3091 3092 return 0; 3093 } 3094 3095 static int 3096 pccbb_winlist_insert(struct pccbb_win_chain_head *head, bus_addr_t start, 3097 bus_size_t size, bus_space_handle_t bsh, int flags) 3098 { 3099 struct pccbb_win_chain *chainp, *elem; 3100 3101 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 3102 M_NOWAIT)) == NULL) 3103 return (1); /* fail */ 3104 3105 elem->wc_start = start; 3106 elem->wc_end = start + (size - 1); 3107 elem->wc_handle = bsh; 3108 elem->wc_flags = flags; 3109 3110 TAILQ_FOREACH(chainp, head, wc_list) { 3111 if (chainp->wc_end >= start) 3112 break; 3113 } 3114 if (chainp != NULL) 3115 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 3116 else 3117 TAILQ_INSERT_TAIL(head, elem, wc_list); 3118 return (0); 3119 } 3120 3121 static int 3122 pccbb_winlist_delete(struct pccbb_win_chain_head *head, bus_space_handle_t bsh, 3123 bus_size_t size) 3124 { 3125 struct pccbb_win_chain *chainp; 3126 3127 TAILQ_FOREACH(chainp, head, wc_list) { 3128 if (memcmp(&chainp->wc_handle, &bsh, sizeof(bsh)) == 0) 3129 break; 3130 } 3131 if (chainp == NULL) 3132 return 1; /* fail: no candidate to remove */ 3133 3134 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 3135 printf("pccbb_winlist_delete: window 0x%lx size " 3136 "inconsistent: 0x%lx, 0x%lx\n", 3137 (unsigned long)chainp->wc_start, 3138 (unsigned long)(chainp->wc_end - chainp->wc_start), 3139 (unsigned long)(size - 1)); 3140 return 1; 3141 } 3142 3143 TAILQ_REMOVE(head, chainp, wc_list); 3144 free(chainp, M_DEVBUF); 3145 3146 return 0; 3147 } 3148 3149 static void 3150 pccbb_winset(bus_addr_t align, struct pccbb_softc *sc, bus_space_tag_t bst) 3151 { 3152 pci_chipset_tag_t pc; 3153 pcitag_t tag; 3154 bus_addr_t mask = ~(align - 1); 3155 struct { 3156 cardbusreg_t win_start; 3157 cardbusreg_t win_limit; 3158 int win_flags; 3159 } win[2]; 3160 struct pccbb_win_chain *chainp; 3161 int offs; 3162 3163 win[0].win_start = win[1].win_start = 0xffffffff; 3164 win[0].win_limit = win[1].win_limit = 0; 3165 win[0].win_flags = win[1].win_flags = 0; 3166 3167 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3168 offs = 0x2c; 3169 if (sc->sc_memt == bst) { 3170 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3171 offs = 0x1c; 3172 } 3173 3174 if (chainp != NULL) { 3175 win[0].win_start = chainp->wc_start & mask; 3176 win[0].win_limit = chainp->wc_end & mask; 3177 win[0].win_flags = chainp->wc_flags; 3178 chainp = TAILQ_NEXT(chainp, wc_list); 3179 } 3180 3181 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3182 if (win[1].win_start == 0xffffffff) { 3183 /* window 1 is not used */ 3184 if ((win[0].win_flags == chainp->wc_flags) && 3185 (win[0].win_limit + align >= 3186 (chainp->wc_start & mask))) { 3187 /* concatenate */ 3188 win[0].win_limit = chainp->wc_end & mask; 3189 } else { 3190 /* make new window */ 3191 win[1].win_start = chainp->wc_start & mask; 3192 win[1].win_limit = chainp->wc_end & mask; 3193 win[1].win_flags = chainp->wc_flags; 3194 } 3195 continue; 3196 } 3197 3198 /* Both windows are engaged. */ 3199 if (win[0].win_flags == win[1].win_flags) { 3200 /* same flags */ 3201 if (win[0].win_flags == chainp->wc_flags) { 3202 if (win[1].win_start - (win[0].win_limit + 3203 align) < 3204 (chainp->wc_start & mask) - 3205 ((chainp->wc_end & mask) + align)) { 3206 /* 3207 * merge window 0 and 1, and set win1 3208 * to chainp 3209 */ 3210 win[0].win_limit = win[1].win_limit; 3211 win[1].win_start = 3212 chainp->wc_start & mask; 3213 win[1].win_limit = 3214 chainp->wc_end & mask; 3215 } else { 3216 win[1].win_limit = 3217 chainp->wc_end & mask; 3218 } 3219 } else { 3220 /* different flags */ 3221 3222 /* concatenate win0 and win1 */ 3223 win[0].win_limit = win[1].win_limit; 3224 /* allocate win[1] to new space */ 3225 win[1].win_start = chainp->wc_start & mask; 3226 win[1].win_limit = chainp->wc_end & mask; 3227 win[1].win_flags = chainp->wc_flags; 3228 } 3229 } else { 3230 /* the flags of win[0] and win[1] is different */ 3231 if (win[0].win_flags == chainp->wc_flags) { 3232 win[0].win_limit = chainp->wc_end & mask; 3233 /* 3234 * XXX this creates overlapping windows, so 3235 * what should the poor bridge do if one is 3236 * cachable, and the other is not? 3237 */ 3238 printf("%s: overlapping windows\n", 3239 sc->sc_dev.dv_xname); 3240 } else { 3241 win[1].win_limit = chainp->wc_end & mask; 3242 } 3243 } 3244 } 3245 3246 pc = sc->sc_pc; 3247 tag = sc->sc_tag; 3248 pci_conf_write(pc, tag, offs, win[0].win_start); 3249 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3250 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3251 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3252 DPRINTF(("--pccbb_winset: win0 [0x%lx, 0x%lx), win1 [0x%lx, 0x%lx)\n", 3253 (unsigned long)pci_conf_read(pc, tag, offs), 3254 (unsigned long)pci_conf_read(pc, tag, offs + 4) + align, 3255 (unsigned long)pci_conf_read(pc, tag, offs + 8), 3256 (unsigned long)pci_conf_read(pc, tag, offs + 12) + align)); 3257 3258 if (bst == sc->sc_memt) { 3259 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BRIDGE_CONTROL_REG); 3260 3261 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 3262 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 3263 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3264 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 3265 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3266 pci_conf_write(pc, tag, PCI_BRIDGE_CONTROL_REG, bcr); 3267 } 3268 } 3269 3270 #endif /* rbus */ 3271 3272 static void 3273 pccbb_powerhook(int why, void *arg) 3274 { 3275 struct pccbb_softc *sc = arg; 3276 pcireg_t reg; 3277 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3278 bus_space_handle_t base_memh = sc->sc_base_memh; 3279 3280 DPRINTF(("%s: power: why %d\n", sc->sc_dev.dv_xname, why)); 3281 3282 if (why == PWR_SUSPEND || why == PWR_STANDBY) { 3283 DPRINTF(("%s: power: why %d stopping intr\n", 3284 sc->sc_dev.dv_xname, why)); 3285 if (sc->sc_pil_intr_enable) { 3286 (void)pccbbintr_function(sc); 3287 } 3288 sc->sc_pil_intr_enable = 0; 3289 3290 pci_conf_capture(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf); 3291 3292 if (sc->sc_chipset == CB_RX5C47X) 3293 sc->sc_ricoh_misc_ctrl = pci_conf_read(sc->sc_pc, 3294 sc->sc_tag, 3295 RICOH_PCI_MISC_CTRL); 3296 3297 /* ToDo: deactivate or suspend child devices */ 3298 } 3299 3300 if (why == PWR_RESUME) { 3301 if (sc->sc_pwrmgt_offs != 0) { 3302 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, 3303 sc->sc_pwrmgt_offs + PCI_PMCSR); 3304 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 3305 reg & PCI_PMCSR_PME_EN) { 3306 /* powrstate != D0 */ 3307 3308 printf("%s going back to D0 mode\n", 3309 sc->sc_dev.dv_xname); 3310 reg &= ~PCI_PMCSR_STATE_MASK; 3311 reg |= PCI_PMCSR_STATE_D0; 3312 reg &= ~PCI_PMCSR_PME_EN; 3313 pci_conf_write(sc->sc_pc, sc->sc_tag, 3314 sc->sc_pwrmgt_offs + PCI_PMCSR, reg); 3315 3316 pci_conf_write(sc->sc_pc, sc->sc_tag, 3317 PCI_SOCKBASE, sc->sc_sockbase); 3318 pci_conf_write(sc->sc_pc, sc->sc_tag, 3319 PCI_BUSNUM, sc->sc_busnum); 3320 pccbb_chipinit(sc); 3321 /* setup memory and io space window for CB */ 3322 pccbb_winset(0x1000, sc, sc->sc_memt); 3323 pccbb_winset(0x04, sc, sc->sc_iot); 3324 goto norestore; 3325 } 3326 } 3327 3328 norestore: 3329 pci_conf_restore(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf); 3330 if (sc->sc_chipset == CB_RX5C47X) { 3331 pci_conf_write(sc->sc_pc, sc->sc_tag, 3332 RICOH_PCI_MISC_CTRL, sc->sc_ricoh_misc_ctrl); 3333 } 3334 3335 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_SOCKBASE) == 0) 3336 /* BIOS did not recover this register */ 3337 pci_conf_write (sc->sc_pc, sc->sc_tag, 3338 PCI_SOCKBASE, sc->sc_sockbase); 3339 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_BUSNUM) == 0) 3340 /* BIOS did not recover this register */ 3341 pci_conf_write (sc->sc_pc, sc->sc_tag, 3342 PCI_BUSNUM, sc->sc_busnum); 3343 /* CSC Interrupt: Card detect interrupt on */ 3344 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3345 /* Card detect intr is turned on. */ 3346 reg |= CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; 3347 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3348 /* reset interrupt */ 3349 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3350 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3351 3352 /* 3353 * check for card insertion or removal during suspend period. 3354 * XXX: the code can't cope with card swap (remove then 3355 * insert). how can we detect such situation? 3356 */ 3357 (void)pccbbintr(sc); 3358 3359 sc->sc_pil_intr_enable = 1; 3360 DPRINTF(("%s: power: RESUME enabling intr\n", 3361 sc->sc_dev.dv_xname)); 3362 3363 /* ToDo: activate or wakeup child devices */ 3364 } 3365 } 3366
Indexes created Fri Sep 26 08:10:20 GMT 2025