pccbb.c revision 1.156
1 /* $NetBSD: pccbb.c,v 1.156 2007/12/09 20:28:11 jmcneill Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: pccbb.c,v 1.156 2007/12/09 20:28:11 jmcneill Exp $"); 35 36 /* 37 #define CBB_DEBUG 38 #define SHOW_REGS 39 */ 40 41 /* 42 * BROKEN! 43 #define PCCBB_PCMCIA_POLL 44 #define CB_PCMCIA_POLL 45 #define CB_PCMCIA_POLL_ONLY 46 #define LEVEL2 47 */ 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/kernel.h> 52 #include <sys/errno.h> 53 #include <sys/ioctl.h> 54 #include <sys/reboot.h> /* for bootverbose */ 55 #include <sys/syslog.h> 56 #include <sys/device.h> 57 #include <sys/malloc.h> 58 #include <sys/proc.h> 59 60 #include <sys/intr.h> 61 #include <sys/bus.h> 62 63 #include <dev/pci/pcivar.h> 64 #include <dev/pci/pcireg.h> 65 #include <dev/pci/pcidevs.h> 66 67 #include <dev/pci/pccbbreg.h> 68 69 #include <dev/cardbus/cardslotvar.h> 70 71 #include <dev/cardbus/cardbusvar.h> 72 73 #include <dev/pcmcia/pcmciareg.h> 74 #include <dev/pcmcia/pcmciavar.h> 75 76 #include <dev/ic/i82365reg.h> 77 #include <dev/ic/i82365var.h> 78 #include <dev/pci/pccbbvar.h> 79 80 #include "locators.h" 81 82 #ifndef __NetBSD_Version__ 83 struct cfdriver cbb_cd = { 84 NULL, "cbb", DV_DULL 85 }; 86 #endif 87 88 #ifdef CBB_DEBUG 89 #define DPRINTF(x) printf x 90 #define STATIC 91 #else 92 #define DPRINTF(x) 93 #define STATIC static 94 #endif 95 96 int pccbb_burstup = 1; 97 98 /* 99 * delay_ms() is wait in milliseconds. It should be used instead 100 * of delay() if you want to wait more than 1 ms. 101 */ 102 static inline void 103 delay_ms(int millis, void *param) 104 { 105 if (cold) 106 delay(millis * 1000); 107 else 108 tsleep(param, PWAIT, "pccbb", MAX(2, hz * millis / 1000)); 109 } 110 111 int pcicbbmatch(struct device *, struct cfdata *, void *); 112 void pccbbattach(struct device *, struct device *, void *); 113 int pccbbintr(void *); 114 static void pci113x_insert(void *); 115 static int pccbbintr_function(struct pccbb_softc *); 116 117 static int pccbb_detect_card(struct pccbb_softc *); 118 119 static void pccbb_pcmcia_write(struct pcic_handle *, int, u_int8_t); 120 static u_int8_t pccbb_pcmcia_read(struct pcic_handle *, int); 121 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 122 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 123 124 STATIC int cb_reset(struct pccbb_softc *); 125 STATIC int cb_detect_voltage(struct pccbb_softc *); 126 STATIC int cbbprint(void *, const char *); 127 128 static int cb_chipset(u_int32_t, int *); 129 STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *, 130 struct pcmciabus_attach_args *); 131 #if 0 132 STATIC void pccbb_pcmcia_attach_card(struct pcic_handle *); 133 STATIC void pccbb_pcmcia_detach_card(struct pcic_handle *, int); 134 STATIC void pccbb_pcmcia_deactivate_card(struct pcic_handle *); 135 #endif 136 137 STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int); 138 STATIC int pccbb_power(cardbus_chipset_tag_t, int); 139 STATIC int pccbb_cardenable(struct pccbb_softc * sc, int function); 140 #if !rbus 141 static int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 142 static int pccbb_io_close(cardbus_chipset_tag_t, int); 143 static int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 144 static int pccbb_mem_close(cardbus_chipset_tag_t, int); 145 #endif /* !rbus */ 146 static void *pccbb_intr_establish(struct pccbb_softc *, int irq, 147 int level, int (*ih) (void *), void *sc); 148 static void pccbb_intr_disestablish(struct pccbb_softc *, void *ih); 149 150 static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t, int irq, 151 int level, int (*ih) (void *), void *sc); 152 static void pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih); 153 154 static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t, int, int); 155 static void pccbb_free_tag(cardbus_chipset_tag_t, cardbustag_t); 156 static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t, cardbustag_t, int); 157 static void pccbb_conf_write(cardbus_chipset_tag_t, cardbustag_t, int, 158 cardbusreg_t); 159 static void pccbb_chipinit(struct pccbb_softc *); 160 161 STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 162 struct pcmcia_mem_handle *); 163 STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t, 164 struct pcmcia_mem_handle *); 165 STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 166 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *); 167 STATIC void pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t, int); 168 STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 169 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 170 STATIC void pccbb_pcmcia_io_free(pcmcia_chipset_handle_t, 171 struct pcmcia_io_handle *); 172 STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 173 bus_size_t, struct pcmcia_io_handle *, int *); 174 STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t, int); 175 STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t, 176 struct pcmcia_function *, int, int (*)(void *), void *); 177 STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t, void *); 178 STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t); 179 STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t); 180 STATIC void pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t, int); 181 STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch); 182 183 static int pccbb_pcmcia_wait_ready(struct pcic_handle *); 184 static void pccbb_pcmcia_delay(struct pcic_handle *, int, const char *); 185 186 static void pccbb_pcmcia_do_io_map(struct pcic_handle *, int); 187 static void pccbb_pcmcia_do_mem_map(struct pcic_handle *, int); 188 189 /* bus-space allocation and deallocation functions */ 190 #if rbus 191 192 static int pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t, rbus_tag_t, 193 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 194 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp); 195 static int pccbb_rbus_cb_space_free(cardbus_chipset_tag_t, rbus_tag_t, 196 bus_space_handle_t, bus_size_t); 197 198 #endif /* rbus */ 199 200 #if rbus 201 202 static int pccbb_open_win(struct pccbb_softc *, bus_space_tag_t, 203 bus_addr_t, bus_size_t, bus_space_handle_t, int flags); 204 static int pccbb_close_win(struct pccbb_softc *, bus_space_tag_t, 205 bus_space_handle_t, bus_size_t); 206 static int pccbb_winlist_insert(struct pccbb_win_chain_head *, bus_addr_t, 207 bus_size_t, bus_space_handle_t, int); 208 static int pccbb_winlist_delete(struct pccbb_win_chain_head *, 209 bus_space_handle_t, bus_size_t); 210 static void pccbb_winset(bus_addr_t align, struct pccbb_softc *, 211 bus_space_tag_t); 212 void pccbb_winlist_show(struct pccbb_win_chain *); 213 214 #endif /* rbus */ 215 216 /* for config_defer */ 217 static void pccbb_pci_callback(struct device *); 218 219 static bool pccbb_suspend(device_t); 220 static bool pccbb_resume(device_t); 221 222 #if defined SHOW_REGS 223 static void cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, 224 bus_space_tag_t memt, bus_space_handle_t memh); 225 #endif 226 227 CFATTACH_DECL(cbb_pci, sizeof(struct pccbb_softc), 228 pcicbbmatch, pccbbattach, NULL, NULL); 229 230 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 231 pccbb_pcmcia_mem_alloc, 232 pccbb_pcmcia_mem_free, 233 pccbb_pcmcia_mem_map, 234 pccbb_pcmcia_mem_unmap, 235 pccbb_pcmcia_io_alloc, 236 pccbb_pcmcia_io_free, 237 pccbb_pcmcia_io_map, 238 pccbb_pcmcia_io_unmap, 239 pccbb_pcmcia_intr_establish, 240 pccbb_pcmcia_intr_disestablish, 241 pccbb_pcmcia_socket_enable, 242 pccbb_pcmcia_socket_disable, 243 pccbb_pcmcia_socket_settype, 244 pccbb_pcmcia_card_detect 245 }; 246 247 #if rbus 248 static struct cardbus_functions pccbb_funcs = { 249 pccbb_rbus_cb_space_alloc, 250 pccbb_rbus_cb_space_free, 251 pccbb_cb_intr_establish, 252 pccbb_cb_intr_disestablish, 253 pccbb_ctrl, 254 pccbb_power, 255 pccbb_make_tag, 256 pccbb_free_tag, 257 pccbb_conf_read, 258 pccbb_conf_write, 259 }; 260 #else 261 static struct cardbus_functions pccbb_funcs = { 262 pccbb_ctrl, 263 pccbb_power, 264 pccbb_mem_open, 265 pccbb_mem_close, 266 pccbb_io_open, 267 pccbb_io_close, 268 pccbb_cb_intr_establish, 269 pccbb_cb_intr_disestablish, 270 pccbb_make_tag, 271 pccbb_conf_read, 272 pccbb_conf_write, 273 }; 274 #endif 275 276 int 277 pcicbbmatch(struct device *parent, struct cfdata *match, void *aux) 278 { 279 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 280 281 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 282 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 283 PCI_INTERFACE(pa->pa_class) == 0) { 284 return 1; 285 } 286 287 return 0; 288 } 289 290 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 291 | ((prod) << PCI_PRODUCT_SHIFT)) 292 293 const struct yenta_chipinfo { 294 pcireg_t yc_id; /* vendor tag | product tag */ 295 int yc_chiptype; 296 int yc_flags; 297 } yc_chipsets[] = { 298 /* Texas Instruments chips */ 299 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 300 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 301 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 302 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 303 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI125X, 304 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 305 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 306 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 307 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 308 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 309 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 310 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 311 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI125X, 312 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 313 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI125X, 314 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 315 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 316 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 317 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 318 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 319 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI1420, 320 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 321 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI125X, 322 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 323 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 324 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 325 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1520), CB_TI12XX, 326 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 327 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4410YENTA), CB_TI12XX, 328 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 329 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4520YENTA), CB_TI12XX, 330 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 331 332 /* Ricoh chips */ 333 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 334 PCCBB_PCMCIA_MEM_32}, 335 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 336 PCCBB_PCMCIA_MEM_32}, 337 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 338 PCCBB_PCMCIA_MEM_32}, 339 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 340 PCCBB_PCMCIA_MEM_32}, 341 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 342 PCCBB_PCMCIA_MEM_32}, 343 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 344 PCCBB_PCMCIA_MEM_32}, 345 346 /* Toshiba products */ 347 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 348 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 349 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 350 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 351 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 352 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 353 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 354 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 355 356 /* Cirrus Logic products */ 357 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 358 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 359 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 360 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 361 362 /* sentinel, or Generic chip */ 363 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 364 }; 365 366 static int 367 cb_chipset(u_int32_t pci_id, int *flagp) 368 { 369 const struct yenta_chipinfo *yc; 370 371 /* Loop over except the last default entry. */ 372 for (yc = yc_chipsets; yc < yc_chipsets + 373 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 374 if (pci_id == yc->yc_id) 375 break; 376 377 if (flagp != NULL) 378 *flagp = yc->yc_flags; 379 380 return (yc->yc_chiptype); 381 } 382 383 void 384 pccbbattach(struct device *parent, struct device *self, void *aux) 385 { 386 struct pccbb_softc *sc = (void *)self; 387 struct pci_attach_args *pa = aux; 388 pci_chipset_tag_t pc = pa->pa_pc; 389 pcireg_t busreg, reg, sock_base; 390 bus_addr_t sockbase; 391 char devinfo[256]; 392 int flags; 393 394 #ifdef __HAVE_PCCBB_ATTACH_HOOK 395 pccbb_attach_hook(parent, self, pa); 396 #endif 397 398 callout_init(&sc->sc_insert_ch, 0); 399 callout_setfunc(&sc->sc_insert_ch, pci113x_insert, sc); 400 401 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 402 403 aprint_naive("\n"); 404 405 pci_devinfo(pa->pa_id, 0, 0, devinfo, sizeof(devinfo)); 406 aprint_normal(": %s (rev. 0x%02x)", devinfo, 407 PCI_REVISION(pa->pa_class)); 408 DPRINTF((" (chipflags %x)", flags)); 409 aprint_normal("\n"); 410 411 TAILQ_INIT(&sc->sc_memwindow); 412 TAILQ_INIT(&sc->sc_iowindow); 413 414 #if rbus 415 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 416 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 417 418 #if 0 419 printf("pa->pa_memt: %08x vs rbus_mem->rb_bt: %08x\n", 420 pa->pa_memt, sc->sc_rbus_memt->rb_bt); 421 #endif 422 #endif /* rbus */ 423 424 sc->sc_flags &= ~CBB_MEMHMAPPED; 425 426 /* 427 * MAP socket registers and ExCA registers on memory-space 428 * When no valid address is set on socket base registers (on pci 429 * config space), get it not polite way. 430 */ 431 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 432 433 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 434 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 435 /* The address must be valid. */ 436 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 437 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL)) { 438 aprint_error("%s: can't map socket base address 0x%lx\n", 439 sc->sc_dev.dv_xname, (unsigned long)sock_base); 440 /* 441 * I think it's funny: socket base registers must be 442 * mapped on memory space, but ... 443 */ 444 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 445 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 446 NULL)) { 447 aprint_error("%s: can't map socket base address" 448 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 449 (unsigned long)sockbase); 450 /* give up... allocate reg space via rbus. */ 451 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 452 } else 453 sc->sc_flags |= CBB_MEMHMAPPED; 454 } else { 455 DPRINTF(("%s: socket base address 0x%lx\n", 456 sc->sc_dev.dv_xname, (unsigned long)sockbase)); 457 sc->sc_flags |= CBB_MEMHMAPPED; 458 } 459 } 460 461 sc->sc_mem_start = 0; /* XXX */ 462 sc->sc_mem_end = 0xffffffff; /* XXX */ 463 464 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 465 466 /* pccbb_machdep.c end */ 467 468 #if defined CBB_DEBUG 469 { 470 static const char *intrname[] = { "NON", "A", "B", "C", "D" }; 471 printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname, 472 intrname[pa->pa_intrpin], pa->pa_intrline); 473 } 474 #endif 475 476 /* setup softc */ 477 sc->sc_pc = pc; 478 sc->sc_iot = pa->pa_iot; 479 sc->sc_memt = pa->pa_memt; 480 sc->sc_dmat = pa->pa_dmat; 481 sc->sc_tag = pa->pa_tag; 482 sc->sc_function = pa->pa_function; 483 484 memcpy(&sc->sc_pa, pa, sizeof(*pa)); 485 486 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 487 488 /* Disable legacy register mapping. */ 489 switch (sc->sc_chipset) { 490 case CB_RX5C46X: /* fallthrough */ 491 #if 0 492 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 493 case CB_RX5C47X: 494 #endif 495 /* 496 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 497 * cannot be disabled by substituting 0 into PCI_LEGACY 498 * register. Ricoh CardBus bridges have special bits on Bridge 499 * control reg (addr 0x3e on PCI config space). 500 */ 501 reg = pci_conf_read(pc, pa->pa_tag, PCI_BRIDGE_CONTROL_REG); 502 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 503 pci_conf_write(pc, pa->pa_tag, PCI_BRIDGE_CONTROL_REG, reg); 504 break; 505 506 default: 507 /* XXX I don't know proper way to kill legacy I/O. */ 508 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 509 break; 510 } 511 512 if (!pmf_device_register(self, pccbb_suspend, pccbb_resume)) 513 aprint_error_dev(self, "couldn't establish power handler\n"); 514 515 config_defer(self, pccbb_pci_callback); 516 } 517 518 519 520 521 /* 522 * static void pccbb_pci_callback(struct device *self) 523 * 524 * The actual attach routine: get memory space for YENTA register 525 * space, setup YENTA register and route interrupt. 526 * 527 * This function should be deferred because this device may obtain 528 * memory space dynamically. This function must avoid obtaining 529 * memory area which has already kept for another device. 530 */ 531 static void 532 pccbb_pci_callback(struct device *self) 533 { 534 struct pccbb_softc *sc = (void *)self; 535 pci_chipset_tag_t pc = sc->sc_pc; 536 pci_intr_handle_t ih; 537 const char *intrstr = NULL; 538 bus_addr_t sockbase; 539 struct cbslot_attach_args cba; 540 struct pcmciabus_attach_args paa; 541 struct cardslot_attach_args caa; 542 struct cardslot_softc *csc; 543 544 if (!(sc->sc_flags & CBB_MEMHMAPPED)) { 545 /* The socket registers aren't mapped correctly. */ 546 #if rbus 547 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 548 (sc->sc_chipset == CB_RX5C47X 549 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 550 0, &sockbase, &sc->sc_base_memh)) { 551 return; 552 } 553 sc->sc_base_memt = sc->sc_memt; 554 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 555 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 556 sc->sc_dev.dv_xname, (unsigned long)sockbase, 557 (unsigned long)pci_conf_read(pc, sc->sc_tag, 558 PCI_SOCKBASE))); 559 #else 560 sc->sc_base_memt = sc->sc_memt; 561 #if !defined CBB_PCI_BASE 562 #define CBB_PCI_BASE 0x20000000 563 #endif 564 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 565 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 566 /* cannot allocate memory space */ 567 return; 568 } 569 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 570 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 571 sc->sc_dev.dv_xname, (unsigned long)sock_base, 572 (unsigned long)pci_conf_read(pc, 573 sc->sc_tag, PCI_SOCKBASE))); 574 #endif 575 sc->sc_flags |= CBB_MEMHMAPPED; 576 } 577 578 /* bus bridge initialization */ 579 pccbb_chipinit(sc); 580 581 /* clear data structure for child device interrupt handlers */ 582 LIST_INIT(&sc->sc_pil); 583 sc->sc_pil_intr_enable = 1; 584 585 /* Map and establish the interrupt. */ 586 if (pci_intr_map(&sc->sc_pa, &ih)) { 587 aprint_error("%s: couldn't map interrupt\n", 588 sc->sc_dev.dv_xname); 589 return; 590 } 591 intrstr = pci_intr_string(pc, ih); 592 593 /* 594 * XXX pccbbintr should be called under the priority lower 595 * than any other hard interupts. 596 */ 597 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 598 599 if (sc->sc_ih == NULL) { 600 aprint_error("%s: couldn't establish interrupt", 601 sc->sc_dev.dv_xname); 602 if (intrstr != NULL) { 603 aprint_normal(" at %s", intrstr); 604 } 605 aprint_normal("\n"); 606 return; 607 } 608 609 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 610 611 { 612 u_int32_t sockstat; 613 614 sockstat = bus_space_read_4(sc->sc_base_memt, 615 sc->sc_base_memh, CB_SOCKET_STAT); 616 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 617 sc->sc_flags |= CBB_CARDEXIST; 618 } 619 } 620 621 /* 622 * attach cardbus 623 */ 624 { 625 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 626 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 627 628 /* initialize cbslot_attach */ 629 cba.cba_busname = "cardbus"; 630 cba.cba_iot = sc->sc_iot; 631 cba.cba_memt = sc->sc_memt; 632 cba.cba_dmat = sc->sc_dmat; 633 cba.cba_bus = (busreg >> 8) & 0x0ff; 634 cba.cba_cc = (void *)sc; 635 cba.cba_cf = &pccbb_funcs; 636 cba.cba_intrline = sc->sc_pa.pa_intrline; 637 638 #if rbus 639 cba.cba_rbus_iot = sc->sc_rbus_iot; 640 cba.cba_rbus_memt = sc->sc_rbus_memt; 641 #endif 642 643 cba.cba_cacheline = PCI_CACHELINE(bhlc); 644 cba.cba_max_lattimer = PCI_LATTIMER(bhlc); 645 646 if (bootverbose) { 647 printf("%s: cacheline 0x%x lattimer 0x%x\n", 648 sc->sc_dev.dv_xname, cba.cba_cacheline, 649 cba.cba_max_lattimer); 650 printf("%s: bhlc 0x%x\n", 651 device_xname(&sc->sc_dev), bhlc); 652 } 653 #if defined SHOW_REGS 654 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 655 sc->sc_base_memh); 656 #endif 657 } 658 659 pccbb_pcmcia_attach_setup(sc, &paa); 660 caa.caa_cb_attach = NULL; 661 if (cba.cba_bus == 0) 662 printf("%s: secondary bus number uninitialized; try PCI_BUS_FIXUP\n", sc->sc_dev.dv_xname); 663 else 664 caa.caa_cb_attach = &cba; 665 caa.caa_16_attach = &paa; 666 caa.caa_ph = &sc->sc_pcmcia_h; 667 668 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 669 DPRINTF(("%s: found cardslot\n", __func__)); 670 sc->sc_csc = csc; 671 } 672 673 return; 674 } 675 676 677 678 679 680 /* 681 * static void pccbb_chipinit(struct pccbb_softc *sc) 682 * 683 * This function initialize YENTA chip registers listed below: 684 * 1) PCI command reg, 685 * 2) PCI and CardBus latency timer, 686 * 3) route PCI interrupt, 687 * 4) close all memory and io windows. 688 * 5) turn off bus power. 689 * 6) card detect and power cycle interrupts on. 690 * 7) clear interrupt 691 */ 692 static void 693 pccbb_chipinit(struct pccbb_softc *sc) 694 { 695 pci_chipset_tag_t pc = sc->sc_pc; 696 pcitag_t tag = sc->sc_tag; 697 bus_space_tag_t bmt = sc->sc_base_memt; 698 bus_space_handle_t bmh = sc->sc_base_memh; 699 pcireg_t bcr, bhlc, cbctl, csr, lscp, mfunc, mrburst, slotctl, sockctl, 700 sockmask, sysctrl; 701 702 /* 703 * Set PCI command reg. 704 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 705 */ 706 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 707 /* I believe it is harmless. */ 708 csr |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 709 PCI_COMMAND_MASTER_ENABLE); 710 csr |= (PCI_COMMAND_PARITY_ENABLE|PCI_COMMAND_SERR_ENABLE); 711 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 712 713 /* 714 * Set CardBus latency timer. 715 */ 716 lscp = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 717 if (PCI_CB_LATENCY(lscp) < 0x20) { 718 lscp &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 719 lscp |= (0x20 << PCI_CB_LATENCY_SHIFT); 720 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, lscp); 721 } 722 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 723 PCI_CB_LATENCY(lscp), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 724 725 /* 726 * Set PCI latency timer. 727 */ 728 bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG); 729 if (PCI_LATTIMER(bhlc) < 0x10) { 730 bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 731 bhlc |= (0x10 << PCI_LATTIMER_SHIFT); 732 pci_conf_write(pc, tag, PCI_BHLC_REG, bhlc); 733 } 734 DPRINTF(("PCI latency timer 0x%x (%x)\n", 735 PCI_LATTIMER(bhlc), pci_conf_read(pc, tag, PCI_BHLC_REG))); 736 737 738 /* Route functional interrupts to PCI. */ 739 bcr = pci_conf_read(pc, tag, PCI_BRIDGE_CONTROL_REG); 740 bcr |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 741 bcr |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 742 /* assert reset */ 743 bcr |= PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT; 744 /* Set master abort mode to 1, forward SERR# from secondary 745 * to primary, and detect parity errors on secondary. 746 */ 747 bcr |= PCI_BRIDGE_CONTROL_MABRT << PCI_BRIDGE_CONTROL_SHIFT; 748 bcr |= PCI_BRIDGE_CONTROL_SERR << PCI_BRIDGE_CONTROL_SHIFT; 749 bcr |= PCI_BRIDGE_CONTROL_PERE << PCI_BRIDGE_CONTROL_SHIFT; 750 pci_conf_write(pc, tag, PCI_BRIDGE_CONTROL_REG, bcr); 751 752 switch (sc->sc_chipset) { 753 case CB_TI113X: 754 cbctl = pci_conf_read(pc, tag, PCI_CBCTRL); 755 /* This bit is shared, but may read as 0 on some chips, so set 756 it explicitly on both functions. */ 757 cbctl |= PCI113X_CBCTRL_PCI_IRQ_ENA; 758 /* CSC intr enable */ 759 cbctl |= PCI113X_CBCTRL_PCI_CSC; 760 /* functional intr prohibit | prohibit ISA routing */ 761 cbctl &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 762 pci_conf_write(pc, tag, PCI_CBCTRL, cbctl); 763 break; 764 765 case CB_TI1420: 766 sysctrl = pci_conf_read(pc, tag, PCI_SYSCTRL); 767 mrburst = pccbb_burstup 768 ? PCI1420_SYSCTRL_MRBURST : PCI1420_SYSCTRL_MRBURSTDN; 769 if ((sysctrl & PCI1420_SYSCTRL_MRBURST) == mrburst) { 770 printf("%s: %swrite bursts enabled\n", 771 device_xname(&sc->sc_dev), 772 pccbb_burstup ? "read/" : ""); 773 } else if (pccbb_burstup) { 774 printf("%s: enabling read/write bursts\n", 775 device_xname(&sc->sc_dev)); 776 sysctrl |= PCI1420_SYSCTRL_MRBURST; 777 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 778 } else { 779 printf("%s: disabling read bursts, " 780 "enabling write bursts\n", 781 device_xname(&sc->sc_dev)); 782 sysctrl |= PCI1420_SYSCTRL_MRBURSTDN; 783 sysctrl &= ~PCI1420_SYSCTRL_MRBURSTUP; 784 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 785 } 786 /*FALLTHROUGH*/ 787 case CB_TI12XX: 788 /* 789 * Some TI 12xx (and [14][45]xx) based pci cards 790 * sometimes have issues with the MFUNC register not 791 * being initialized due to a bad EEPROM on board. 792 * Laptops that this matters on have this register 793 * properly initialized. 794 * 795 * The TI125X parts have a different register. 796 */ 797 mfunc = pci_conf_read(pc, tag, PCI12XX_MFUNC); 798 if (mfunc == 0) { 799 mfunc &= ~PCI12XX_MFUNC_PIN0; 800 mfunc |= PCI12XX_MFUNC_PIN0_INTA; 801 if ((pci_conf_read(pc, tag, PCI_SYSCTRL) & 802 PCI12XX_SYSCTRL_INTRTIE) == 0) { 803 mfunc &= ~PCI12XX_MFUNC_PIN1; 804 mfunc |= PCI12XX_MFUNC_PIN1_INTB; 805 } 806 pci_conf_write(pc, tag, PCI12XX_MFUNC, mfunc); 807 } 808 /* fallthrough */ 809 810 case CB_TI125X: 811 /* 812 * Disable zoom video. Some machines initialize this 813 * improperly and experience has shown that this helps 814 * prevent strange behavior. 815 */ 816 pci_conf_write(pc, tag, PCI12XX_MMCTRL, 0); 817 818 sysctrl = pci_conf_read(pc, tag, PCI_SYSCTRL); 819 sysctrl |= PCI12XX_SYSCTRL_VCCPROT; 820 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 821 cbctl = pci_conf_read(pc, tag, PCI_CBCTRL); 822 cbctl |= PCI12XX_CBCTRL_CSC; 823 pci_conf_write(pc, tag, PCI_CBCTRL, cbctl); 824 break; 825 826 case CB_TOPIC95B: 827 sockctl = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 828 sockctl |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 829 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, sockctl); 830 slotctl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 831 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 832 sc->sc_dev.dv_xname, slotctl)); 833 slotctl |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 834 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 835 slotctl &= ~TOPIC_SLOT_CTRL_SWDETECT; 836 DPRINTF(("0x%x\n", slotctl)); 837 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slotctl); 838 break; 839 840 case CB_TOPIC97: 841 slotctl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 842 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 843 sc->sc_dev.dv_xname, slotctl)); 844 slotctl |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 845 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 846 slotctl &= ~TOPIC_SLOT_CTRL_SWDETECT; 847 slotctl |= TOPIC97_SLOT_CTRL_PCIINT; 848 slotctl &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 849 DPRINTF(("0x%x\n", slotctl)); 850 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slotctl); 851 /* make sure to assert LV card support bits */ 852 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 853 0x800 + 0x3e, 854 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 855 0x800 + 0x3e) | 0x03); 856 break; 857 } 858 859 /* Close all memory and I/O windows. */ 860 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 861 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 862 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 863 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 864 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 865 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 866 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 867 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 868 869 /* reset 16-bit pcmcia bus */ 870 bus_space_write_1(bmt, bmh, 0x800 + PCIC_INTR, 871 bus_space_read_1(bmt, bmh, 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 872 873 /* turn off power */ 874 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 875 876 /* CSC Interrupt: Card detect and power cycle interrupts on */ 877 sockmask = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 878 sockmask |= CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; 879 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, sockmask); 880 /* reset interrupt */ 881 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 882 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 883 } 884 885 886 887 888 /* 889 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 890 * struct pcmciabus_attach_args *paa) 891 * 892 * This function attaches 16-bit PCcard bus. 893 */ 894 STATIC void 895 pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 896 struct pcmciabus_attach_args *paa) 897 { 898 struct pcic_handle *ph = &sc->sc_pcmcia_h; 899 #if rbus 900 rbus_tag_t rb; 901 #endif 902 903 /* initialize pcmcia part in pccbb_softc */ 904 ph->ph_parent = (struct device *)sc; 905 ph->sock = sc->sc_function; 906 ph->flags = 0; 907 ph->shutdown = 0; 908 ph->ih_irq = sc->sc_pa.pa_intrline; 909 ph->ph_bus_t = sc->sc_base_memt; 910 ph->ph_bus_h = sc->sc_base_memh; 911 ph->ph_read = pccbb_pcmcia_read; 912 ph->ph_write = pccbb_pcmcia_write; 913 sc->sc_pct = &pccbb_pcmcia_funcs; 914 915 /* 916 * We need to do a few things here: 917 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 918 * setting the IRQ numbers to 0. 919 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 920 * routing of CSC interrupts (e.g. card removal) to PCI while in 921 * PCMCIA mode. We just leave this set all the time. 922 * 3) Enable card insertion/removal interrupts in case the chip also 923 * needs that while in PCMCIA mode. 924 * 4) Clear any pending CSC interrupt. 925 */ 926 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE); 927 if (sc->sc_chipset == CB_TI113X) { 928 Pcic_write(ph, PCIC_CSC_INTR, 0); 929 } else { 930 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 931 Pcic_read(ph, PCIC_CSC); 932 } 933 934 /* initialize pcmcia bus attachment */ 935 paa->paa_busname = "pcmcia"; 936 paa->pct = sc->sc_pct; 937 paa->pch = ph; 938 paa->iobase = 0; /* I don't use them */ 939 paa->iosize = 0; 940 #if rbus 941 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 942 paa->iobase = rb->rb_start + rb->rb_offset; 943 paa->iosize = rb->rb_end - rb->rb_start; 944 #endif 945 946 return; 947 } 948 949 #if 0 950 STATIC void 951 pccbb_pcmcia_attach_card(struct pcic_handle *ph) 952 { 953 if (ph->flags & PCIC_FLAG_CARDP) { 954 panic("pccbb_pcmcia_attach_card: already attached"); 955 } 956 957 /* call the MI attach function */ 958 pcmcia_card_attach(ph->pcmcia); 959 960 ph->flags |= PCIC_FLAG_CARDP; 961 } 962 963 STATIC void 964 pccbb_pcmcia_detach_card(struct pcic_handle *ph, int flags) 965 { 966 if (!(ph->flags & PCIC_FLAG_CARDP)) { 967 panic("pccbb_pcmcia_detach_card: already detached"); 968 } 969 970 ph->flags &= ~PCIC_FLAG_CARDP; 971 972 /* call the MI detach function */ 973 pcmcia_card_detach(ph->pcmcia, flags); 974 } 975 #endif 976 977 /* 978 * int pccbbintr(arg) 979 * void *arg; 980 * This routine handles the interrupt from Yenta PCI-CardBus bridge 981 * itself. 982 */ 983 int 984 pccbbintr(void *arg) 985 { 986 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 987 u_int32_t sockevent, sockstate; 988 bus_space_tag_t memt = sc->sc_base_memt; 989 bus_space_handle_t memh = sc->sc_base_memh; 990 struct pcic_handle *ph = &sc->sc_pcmcia_h; 991 992 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 993 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 994 Pcic_read(ph, PCIC_CSC); 995 996 if (sockevent != 0) { 997 aprint_debug("%s: enter sockevent %" PRIx32 "\n", __func__, 998 sockevent); 999 } 1000 1001 /* Sometimes a change of CSTSCHG# accompanies the first 1002 * interrupt from an Atheros WLAN. That generates a 1003 * CB_SOCKET_EVENT_CSTS event on the bridge. The event 1004 * isn't interesting to pccbb(4), so we used to ignore the 1005 * interrupt. Now, let the child devices try to handle 1006 * the interrupt, instead. The Atheros NIC produces 1007 * interrupts more reliably, now: used to be that it would 1008 * only interrupt if the driver avoided powering down the 1009 * NIC's cardslot, and then the NIC would only work after 1010 * it was reset a second time. 1011 */ 1012 if (sockevent == 0 || 1013 (sockevent & ~(CB_SOCKET_EVENT_POWER|CB_SOCKET_EVENT_CD)) != 0) { 1014 /* This intr is not for me: it may be for my child devices. */ 1015 if (sc->sc_pil_intr_enable) { 1016 return pccbbintr_function(sc); 1017 } else { 1018 return 0; 1019 } 1020 } 1021 1022 if (sockevent & CB_SOCKET_EVENT_CD) { 1023 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1024 if (0x00 != (sockstate & CB_SOCKET_STAT_CD)) { 1025 /* A card should be removed. */ 1026 if (sc->sc_flags & CBB_CARDEXIST) { 1027 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 1028 sockevent)); 1029 DPRINTF((" card removed, 0x%08x\n", sockstate)); 1030 sc->sc_flags &= ~CBB_CARDEXIST; 1031 if (sc->sc_csc->sc_status & 1032 CARDSLOT_STATUS_CARD_16) { 1033 #if 0 1034 struct pcic_handle *ph = 1035 &sc->sc_pcmcia_h; 1036 1037 pcmcia_card_deactivate(ph->pcmcia); 1038 pccbb_pcmcia_socket_disable(ph); 1039 pccbb_pcmcia_detach_card(ph, 1040 DETACH_FORCE); 1041 #endif 1042 cardslot_event_throw(sc->sc_csc, 1043 CARDSLOT_EVENT_REMOVAL_16); 1044 } else if (sc->sc_csc->sc_status & 1045 CARDSLOT_STATUS_CARD_CB) { 1046 /* Cardbus intr removed */ 1047 cardslot_event_throw(sc->sc_csc, 1048 CARDSLOT_EVENT_REMOVAL_CB); 1049 } 1050 } else if (sc->sc_flags & CBB_INSERTING) { 1051 sc->sc_flags &= ~CBB_INSERTING; 1052 callout_stop(&sc->sc_insert_ch); 1053 } 1054 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 1055 /* 1056 * The pccbbintr may called from powerdown hook when 1057 * the system resumed, to detect the card 1058 * insertion/removal during suspension. 1059 */ 1060 (sc->sc_flags & CBB_CARDEXIST) == 0) { 1061 if (sc->sc_flags & CBB_INSERTING) { 1062 callout_stop(&sc->sc_insert_ch); 1063 } 1064 callout_schedule(&sc->sc_insert_ch, hz / 5); 1065 sc->sc_flags |= CBB_INSERTING; 1066 } 1067 } 1068 1069 /* XXX sockevent == 9 does occur in the wild. handle it. */ 1070 if (sockevent & CB_SOCKET_EVENT_POWER) { 1071 DPRINTF(("Powercycling because of socket event\n")); 1072 /* XXX: Does not happen when attaching a 16-bit card */ 1073 sc->sc_pwrcycle++; 1074 wakeup(&sc->sc_pwrcycle); 1075 } 1076 1077 return (1); 1078 } 1079 1080 /* 1081 * static int pccbbintr_function(struct pccbb_softc *sc) 1082 * 1083 * This function calls each interrupt handler registered at the 1084 * bridge. The interrupt handlers are called in registered order. 1085 */ 1086 static int 1087 pccbbintr_function(struct pccbb_softc *sc) 1088 { 1089 int retval = 0, val; 1090 struct pccbb_intrhand_list *pil; 1091 int s; 1092 1093 for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1094 pil = LIST_NEXT(pil, pil_next)) { 1095 s = splraiseipl(pil->pil_icookie); 1096 val = (*pil->pil_func)(pil->pil_arg); 1097 splx(s); 1098 1099 retval = retval == 1 ? 1 : 1100 retval == 0 ? val : val != 0 ? val : retval; 1101 } 1102 1103 return retval; 1104 } 1105 1106 static void 1107 pci113x_insert(void *arg) 1108 { 1109 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1110 u_int32_t sockevent, sockstate; 1111 1112 if (!(sc->sc_flags & CBB_INSERTING)) { 1113 /* We add a card only under inserting state. */ 1114 return; 1115 } 1116 sc->sc_flags &= ~CBB_INSERTING; 1117 1118 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1119 CB_SOCKET_EVENT); 1120 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1121 CB_SOCKET_STAT); 1122 1123 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1124 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1125 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1126 sc->sc_flags |= CBB_CARDEXIST; 1127 /* call pccard interrupt handler here */ 1128 if (sockstate & CB_SOCKET_STAT_16BIT) { 1129 /* 16-bit card found */ 1130 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1131 cardslot_event_throw(sc->sc_csc, 1132 CARDSLOT_EVENT_INSERTION_16); 1133 } else if (sockstate & CB_SOCKET_STAT_CB) { 1134 /* cardbus card found */ 1135 /* cardbus_attach_card(sc->sc_csc); */ 1136 cardslot_event_throw(sc->sc_csc, 1137 CARDSLOT_EVENT_INSERTION_CB); 1138 } else { 1139 /* who are you? */ 1140 } 1141 } else { 1142 callout_schedule(&sc->sc_insert_ch, hz / 10); 1143 } 1144 } 1145 1146 #define PCCBB_PCMCIA_OFFSET 0x800 1147 static u_int8_t 1148 pccbb_pcmcia_read(struct pcic_handle *ph, int reg) 1149 { 1150 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1151 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1152 1153 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1154 PCCBB_PCMCIA_OFFSET + reg); 1155 } 1156 1157 static void 1158 pccbb_pcmcia_write(struct pcic_handle *ph, int reg, u_int8_t val) 1159 { 1160 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1161 val); 1162 1163 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1164 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1165 } 1166 1167 /* 1168 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1169 */ 1170 STATIC int 1171 pccbb_ctrl(cardbus_chipset_tag_t ct, int command) 1172 { 1173 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1174 1175 switch (command) { 1176 case CARDBUS_CD: 1177 if (2 == pccbb_detect_card(sc)) { 1178 int retval = 0; 1179 int status = cb_detect_voltage(sc); 1180 if (PCCARD_VCC_5V & status) { 1181 retval |= CARDBUS_5V_CARD; 1182 } 1183 if (PCCARD_VCC_3V & status) { 1184 retval |= CARDBUS_3V_CARD; 1185 } 1186 if (PCCARD_VCC_XV & status) { 1187 retval |= CARDBUS_XV_CARD; 1188 } 1189 if (PCCARD_VCC_YV & status) { 1190 retval |= CARDBUS_YV_CARD; 1191 } 1192 return retval; 1193 } else { 1194 return 0; 1195 } 1196 case CARDBUS_RESET: 1197 return cb_reset(sc); 1198 case CARDBUS_IO_ENABLE: /* fallthrough */ 1199 case CARDBUS_IO_DISABLE: /* fallthrough */ 1200 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1201 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1202 case CARDBUS_BM_ENABLE: /* fallthrough */ 1203 case CARDBUS_BM_DISABLE: /* fallthrough */ 1204 /* XXX: I think we don't need to call this function below. */ 1205 return pccbb_cardenable(sc, command); 1206 } 1207 1208 return 0; 1209 } 1210 1211 /* 1212 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1213 * This function returns true when it succeeds and returns false when 1214 * it fails. 1215 */ 1216 STATIC int 1217 pccbb_power(cardbus_chipset_tag_t ct, int command) 1218 { 1219 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1220 u_int32_t status, osock_ctrl, sock_ctrl, reg_ctrl; 1221 bus_space_tag_t memt = sc->sc_base_memt; 1222 bus_space_handle_t memh = sc->sc_base_memh; 1223 int on = 0, pwrcycle, s, times; 1224 struct timeval before, after, diff; 1225 1226 DPRINTF(("pccbb_power: %s and %s [0x%x]\n", 1227 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1228 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1229 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1230 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1231 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1232 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1233 "UNKNOWN", 1234 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1235 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1236 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1237 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1238 "UNKNOWN", command)); 1239 1240 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1241 osock_ctrl = sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1242 1243 switch (command & CARDBUS_VCCMASK) { 1244 case CARDBUS_VCC_UC: 1245 break; 1246 case CARDBUS_VCC_5V: 1247 on++; 1248 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1249 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1250 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1251 } else { 1252 printf("%s: BAD voltage request: no 5 V card\n", 1253 sc->sc_dev.dv_xname); 1254 return 0; 1255 } 1256 break; 1257 case CARDBUS_VCC_3V: 1258 on++; 1259 if (CB_SOCKET_STAT_3VCARD & status) { 1260 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1261 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1262 } else { 1263 printf("%s: BAD voltage request: no 3.3 V card\n", 1264 sc->sc_dev.dv_xname); 1265 return 0; 1266 } 1267 break; 1268 case CARDBUS_VCC_0V: 1269 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1270 break; 1271 default: 1272 return 0; /* power NEVER changed */ 1273 } 1274 1275 switch (command & CARDBUS_VPPMASK) { 1276 case CARDBUS_VPP_UC: 1277 break; 1278 case CARDBUS_VPP_0V: 1279 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1280 break; 1281 case CARDBUS_VPP_VCC: 1282 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1283 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1284 break; 1285 case CARDBUS_VPP_12V: 1286 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1287 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1288 break; 1289 } 1290 1291 pwrcycle = sc->sc_pwrcycle; 1292 aprint_debug("%s: osock_ctrl %#" PRIx32 " sock_ctrl %#" PRIx32 "\n", 1293 device_xname(&sc->sc_dev), osock_ctrl, sock_ctrl); 1294 1295 microtime(&before); 1296 s = splbio(); 1297 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1298 1299 /* 1300 * Wait as long as 200ms for a power-cycle interrupt. If 1301 * interrupts are enabled, but the socket has already 1302 * changed to the desired status, keep waiting for the 1303 * interrupt. "Consuming" the interrupt in this way keeps 1304 * the interrupt from prematurely waking some subsequent 1305 * pccbb_power call. 1306 * 1307 * XXX Not every bridge interrupts on the ->OFF transition. 1308 * XXX That's ok, we will time-out after 200ms. 1309 * 1310 * XXX The power cycle event will never happen when attaching 1311 * XXX a 16-bit card. That's ok, we will time-out after 1312 * XXX 200ms. 1313 */ 1314 for (times = 5; --times >= 0; ) { 1315 if (cold) 1316 DELAY(40 * 1000); 1317 else { 1318 (void)tsleep(&sc->sc_pwrcycle, PWAIT, "pccpwr", 1319 hz / 25); 1320 if (pwrcycle == sc->sc_pwrcycle) 1321 continue; 1322 } 1323 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1324 if ((status & CB_SOCKET_STAT_PWRCYCLE) != 0 && on) 1325 break; 1326 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0 && !on) 1327 break; 1328 } 1329 splx(s); 1330 microtime(&after); 1331 timersub(&after, &before, &diff); 1332 aprint_debug("%s: wait took%s %ld.%06lds\n", sc->sc_dev.dv_xname, 1333 (on && times < 0) ? " too long" : "", diff.tv_sec, diff.tv_usec); 1334 1335 /* 1336 * Ok, wait a bit longer for things to settle. 1337 */ 1338 if (on && sc->sc_chipset == CB_TOPIC95B) 1339 delay_ms(100, sc); 1340 1341 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1342 1343 if (on && sc->sc_chipset != CB_TOPIC95B) { 1344 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0) 1345 printf("%s: power on failed?\n", sc->sc_dev.dv_xname); 1346 } 1347 1348 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1349 printf("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1350 sc->sc_dev.dv_xname, sock_ctrl, status); 1351 printf("%s: disabling socket\n", sc->sc_dev.dv_xname); 1352 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1353 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1354 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1355 status &= ~CB_SOCKET_STAT_BADVCC; 1356 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, status); 1357 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1358 CB_SOCKET_STAT)); 1359 return 0; 1360 } 1361 1362 if (sc->sc_chipset == CB_TOPIC97) { 1363 reg_ctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL); 1364 reg_ctrl &= ~TOPIC97_REG_CTRL_TESTMODE; 1365 if ((command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V) 1366 reg_ctrl &= ~TOPIC97_REG_CTRL_CLKRUN_ENA; 1367 else 1368 reg_ctrl |= TOPIC97_REG_CTRL_CLKRUN_ENA; 1369 pci_conf_write(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL, reg_ctrl); 1370 } 1371 1372 return 1; /* power changed correctly */ 1373 } 1374 1375 #if defined CB_PCMCIA_POLL 1376 struct cb_poll_str { 1377 void *arg; 1378 int (*func)(void *); 1379 int level; 1380 pccard_chipset_tag_t ct; 1381 int count; 1382 struct callout poll_ch; 1383 }; 1384 1385 static struct cb_poll_str cb_poll[10]; 1386 static int cb_poll_n = 0; 1387 1388 static void cb_pcmcia_poll(void *arg); 1389 1390 static void 1391 cb_pcmcia_poll(void *arg) 1392 { 1393 struct cb_poll_str *poll = arg; 1394 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1395 struct pccbb_softc *sc = psc->cpc_parent; 1396 int s; 1397 u_int32_t spsr; /* socket present-state reg */ 1398 1399 callout_reset(&poll->poll_ch, hz / 10, cb_pcmcia_poll, poll); 1400 switch (poll->level) { 1401 case IPL_NET: 1402 s = splnet(); 1403 break; 1404 case IPL_BIO: 1405 s = splbio(); 1406 break; 1407 case IPL_TTY: /* fallthrough */ 1408 default: 1409 s = spltty(); 1410 break; 1411 } 1412 1413 spsr = 1414 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1415 CB_SOCKET_STAT); 1416 1417 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1418 if (!(spsr & 0x40)) { /* CINT low */ 1419 #else 1420 if (1) { 1421 #endif 1422 if ((*poll->func) (poll->arg) == 1) { 1423 ++poll->count; 1424 printf("intr: reported from poller, 0x%x\n", spsr); 1425 #if defined LEVEL2 1426 } else { 1427 printf("intr: miss! 0x%x\n", spsr); 1428 #endif 1429 } 1430 } 1431 splx(s); 1432 } 1433 #endif /* defined CB_PCMCIA_POLL */ 1434 1435 /* 1436 * static int pccbb_detect_card(struct pccbb_softc *sc) 1437 * return value: 0 if no card exists. 1438 * 1 if 16-bit card exists. 1439 * 2 if cardbus card exists. 1440 */ 1441 static int 1442 pccbb_detect_card(struct pccbb_softc *sc) 1443 { 1444 bus_space_handle_t base_memh = sc->sc_base_memh; 1445 bus_space_tag_t base_memt = sc->sc_base_memt; 1446 u_int32_t sockstat = 1447 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1448 int retval = 0; 1449 1450 /* CD1 and CD2 asserted */ 1451 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1452 /* card must be present */ 1453 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1454 /* NOTACARD DEASSERTED */ 1455 if (CB_SOCKET_STAT_CB & sockstat) { 1456 /* CardBus mode */ 1457 retval = 2; 1458 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1459 /* 16-bit mode */ 1460 retval = 1; 1461 } 1462 } 1463 } 1464 return retval; 1465 } 1466 1467 /* 1468 * STATIC int cb_reset(struct pccbb_softc *sc) 1469 * This function resets CardBus card. 1470 */ 1471 STATIC int 1472 cb_reset(struct pccbb_softc *sc) 1473 { 1474 /* 1475 * Reset Assert at least 20 ms 1476 * Some machines request longer duration. 1477 */ 1478 int reset_duration = 1479 (sc->sc_chipset == CB_RX5C47X ? 400 : 50); 1480 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1481 aprint_debug("%s: enter bcr %" PRIx32 "\n", __func__, bcr); 1482 1483 /* Reset bit Assert (bit 6 at 0x3E) */ 1484 bcr |= PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT; 1485 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr); 1486 aprint_debug("%s: wrote bcr %" PRIx32 "\n", __func__, bcr); 1487 delay_ms(reset_duration, sc); 1488 1489 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1490 /* Reset bit Deassert (bit 6 at 0x3E) */ 1491 bcr &= ~(PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT); 1492 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, 1493 bcr); 1494 aprint_debug("%s: wrote bcr %" PRIx32 "\n", __func__, bcr); 1495 delay_ms(reset_duration, sc); 1496 aprint_debug("%s: end of delay\n", __func__); 1497 } 1498 /* No card found on the slot. Keep Reset. */ 1499 return 1; 1500 } 1501 1502 /* 1503 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1504 * This function detect card Voltage. 1505 */ 1506 STATIC int 1507 cb_detect_voltage(struct pccbb_softc *sc) 1508 { 1509 u_int32_t psr; /* socket present-state reg */ 1510 bus_space_tag_t iot = sc->sc_base_memt; 1511 bus_space_handle_t ioh = sc->sc_base_memh; 1512 int vol = PCCARD_VCC_UKN; /* set 0 */ 1513 1514 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1515 1516 if (0x400u & psr) { 1517 vol |= PCCARD_VCC_5V; 1518 } 1519 if (0x800u & psr) { 1520 vol |= PCCARD_VCC_3V; 1521 } 1522 1523 return vol; 1524 } 1525 1526 STATIC int 1527 cbbprint(void *aux, const char *pcic) 1528 { 1529 #if 0 1530 struct cbslot_attach_args *cba = aux; 1531 1532 if (cba->cba_slot >= 0) { 1533 aprint_normal(" slot %d", cba->cba_slot); 1534 } 1535 #endif 1536 return UNCONF; 1537 } 1538 1539 /* 1540 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1541 * This function enables and disables the card 1542 */ 1543 STATIC int 1544 pccbb_cardenable(struct pccbb_softc *sc, int function) 1545 { 1546 u_int32_t command = 1547 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1548 1549 DPRINTF(("pccbb_cardenable:")); 1550 switch (function) { 1551 case CARDBUS_IO_ENABLE: 1552 command |= PCI_COMMAND_IO_ENABLE; 1553 break; 1554 case CARDBUS_IO_DISABLE: 1555 command &= ~PCI_COMMAND_IO_ENABLE; 1556 break; 1557 case CARDBUS_MEM_ENABLE: 1558 command |= PCI_COMMAND_MEM_ENABLE; 1559 break; 1560 case CARDBUS_MEM_DISABLE: 1561 command &= ~PCI_COMMAND_MEM_ENABLE; 1562 break; 1563 case CARDBUS_BM_ENABLE: 1564 command |= PCI_COMMAND_MASTER_ENABLE; 1565 break; 1566 case CARDBUS_BM_DISABLE: 1567 command &= ~PCI_COMMAND_MASTER_ENABLE; 1568 break; 1569 default: 1570 return 0; 1571 } 1572 1573 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1574 DPRINTF((" command reg 0x%x\n", command)); 1575 return 1; 1576 } 1577 1578 #if !rbus 1579 static int 1580 pccbb_io_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 1581 { 1582 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1583 int basereg; 1584 int limitreg; 1585 1586 if ((win < 0) || (win > 2)) { 1587 #if defined DIAGNOSTIC 1588 printf("cardbus_io_open: window out of range %d\n", win); 1589 #endif 1590 return 0; 1591 } 1592 1593 basereg = win * 8 + 0x2c; 1594 limitreg = win * 8 + 0x30; 1595 1596 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1597 start, basereg, end, limitreg)); 1598 1599 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1600 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1601 return 1; 1602 } 1603 1604 /* 1605 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1606 */ 1607 static int 1608 pccbb_io_close(cardbus_chipset_tag_t ct, int win) 1609 { 1610 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1611 int basereg; 1612 int limitreg; 1613 1614 if ((win < 0) || (win > 2)) { 1615 #if defined DIAGNOSTIC 1616 printf("cardbus_io_close: window out of range %d\n", win); 1617 #endif 1618 return 0; 1619 } 1620 1621 basereg = win * 8 + 0x2c; 1622 limitreg = win * 8 + 0x30; 1623 1624 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1625 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1626 return 1; 1627 } 1628 1629 static int 1630 pccbb_mem_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 1631 { 1632 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1633 int basereg; 1634 int limitreg; 1635 1636 if ((win < 0) || (win > 2)) { 1637 #if defined DIAGNOSTIC 1638 printf("cardbus_mem_open: window out of range %d\n", win); 1639 #endif 1640 return 0; 1641 } 1642 1643 basereg = win * 8 + 0x1c; 1644 limitreg = win * 8 + 0x20; 1645 1646 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1647 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1648 return 1; 1649 } 1650 1651 static int 1652 pccbb_mem_close(cardbus_chipset_tag_t ct, int win) 1653 { 1654 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1655 int basereg; 1656 int limitreg; 1657 1658 if ((win < 0) || (win > 2)) { 1659 #if defined DIAGNOSTIC 1660 printf("cardbus_mem_close: window out of range %d\n", win); 1661 #endif 1662 return 0; 1663 } 1664 1665 basereg = win * 8 + 0x1c; 1666 limitreg = win * 8 + 0x20; 1667 1668 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1669 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1670 return 1; 1671 } 1672 #endif 1673 1674 /* 1675 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1676 * int irq, 1677 * int level, 1678 * int (* func)(void *), 1679 * void *arg) 1680 * 1681 * This function registers an interrupt handler at the bridge, in 1682 * order not to call the interrupt handlers of child devices when 1683 * a card-deletion interrupt occurs. 1684 * 1685 * The arguments irq and level are not used. 1686 */ 1687 static void * 1688 pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, int irq, int level, 1689 int (*func)(void *), void *arg) 1690 { 1691 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1692 1693 return pccbb_intr_establish(sc, irq, level, func, arg); 1694 } 1695 1696 1697 /* 1698 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1699 * void *ih) 1700 * 1701 * This function removes an interrupt handler pointed by ih. 1702 */ 1703 static void 1704 pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih) 1705 { 1706 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1707 1708 pccbb_intr_disestablish(sc, ih); 1709 } 1710 1711 1712 void 1713 pccbb_intr_route(struct pccbb_softc *sc) 1714 { 1715 pcireg_t bcr, cbctrl; 1716 1717 /* initialize bridge intr routing */ 1718 bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1719 bcr &= ~CB_BCR_INTR_IREQ_ENABLE; 1720 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr); 1721 1722 switch (sc->sc_chipset) { 1723 case CB_TI113X: 1724 cbctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1725 /* functional intr enabled */ 1726 cbctrl |= PCI113X_CBCTRL_PCI_INTR; 1727 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, cbctrl); 1728 break; 1729 default: 1730 break; 1731 } 1732 } 1733 1734 /* 1735 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1736 * int irq, 1737 * int level, 1738 * int (* func)(void *), 1739 * void *arg) 1740 * 1741 * This function registers an interrupt handler at the bridge, in 1742 * order not to call the interrupt handlers of child devices when 1743 * a card-deletion interrupt occurs. 1744 * 1745 * The arguments irq is not used because pccbb selects intr vector. 1746 */ 1747 static void * 1748 pccbb_intr_establish(struct pccbb_softc *sc, int irq, int level, 1749 int (*func)(void *), void *arg) 1750 { 1751 struct pccbb_intrhand_list *pil, *newpil; 1752 1753 DPRINTF(("pccbb_intr_establish start. %p\n", LIST_FIRST(&sc->sc_pil))); 1754 1755 if (LIST_EMPTY(&sc->sc_pil)) { 1756 pccbb_intr_route(sc); 1757 } 1758 1759 /* 1760 * Allocate a room for interrupt handler structure. 1761 */ 1762 if (NULL == (newpil = 1763 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1764 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1765 return NULL; 1766 } 1767 1768 newpil->pil_func = func; 1769 newpil->pil_arg = arg; 1770 newpil->pil_icookie = makeiplcookie(level); 1771 1772 if (LIST_EMPTY(&sc->sc_pil)) { 1773 LIST_INSERT_HEAD(&sc->sc_pil, newpil, pil_next); 1774 } else { 1775 for (pil = LIST_FIRST(&sc->sc_pil); 1776 LIST_NEXT(pil, pil_next) != NULL; 1777 pil = LIST_NEXT(pil, pil_next)); 1778 LIST_INSERT_AFTER(pil, newpil, pil_next); 1779 } 1780 1781 DPRINTF(("pccbb_intr_establish add pil. %p\n", 1782 LIST_FIRST(&sc->sc_pil))); 1783 1784 return newpil; 1785 } 1786 1787 /* 1788 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1789 * void *ih) 1790 * 1791 * This function removes an interrupt handler pointed by ih. ih 1792 * should be the value returned by cardbus_intr_establish() or 1793 * NULL. 1794 * 1795 * When ih is NULL, this function will do nothing. 1796 */ 1797 static void 1798 pccbb_intr_disestablish(struct pccbb_softc *sc, void *ih) 1799 { 1800 struct pccbb_intrhand_list *pil; 1801 pcireg_t reg; 1802 1803 DPRINTF(("pccbb_intr_disestablish start. %p\n", 1804 LIST_FIRST(&sc->sc_pil))); 1805 1806 if (ih == NULL) { 1807 /* intr handler is not set */ 1808 DPRINTF(("pccbb_intr_disestablish: no ih\n")); 1809 return; 1810 } 1811 1812 #ifdef DIAGNOSTIC 1813 for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1814 pil = LIST_NEXT(pil, pil_next)) { 1815 DPRINTF(("pccbb_intr_disestablish: pil %p\n", pil)); 1816 if (pil == ih) { 1817 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1818 break; 1819 } 1820 } 1821 if (pil == NULL) { 1822 panic("pccbb_intr_disestablish: %s cannot find pil %p", 1823 sc->sc_dev.dv_xname, ih); 1824 } 1825 #endif 1826 1827 pil = (struct pccbb_intrhand_list *)ih; 1828 LIST_REMOVE(pil, pil_next); 1829 free(pil, M_DEVBUF); 1830 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1831 1832 if (LIST_EMPTY(&sc->sc_pil)) { 1833 /* No interrupt handlers */ 1834 1835 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1836 1837 /* stop routing PCI intr */ 1838 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1839 reg |= CB_BCR_INTR_IREQ_ENABLE; 1840 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, reg); 1841 1842 switch (sc->sc_chipset) { 1843 case CB_TI113X: 1844 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1845 /* functional intr disabled */ 1846 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1847 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1848 break; 1849 default: 1850 break; 1851 } 1852 } 1853 } 1854 1855 #if defined SHOW_REGS 1856 static void 1857 cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, bus_space_tag_t memt, 1858 bus_space_handle_t memh) 1859 { 1860 int i; 1861 printf("PCI config regs:"); 1862 for (i = 0; i < 0x50; i += 4) { 1863 if (i % 16 == 0) 1864 printf("\n 0x%02x:", i); 1865 printf(" %08x", pci_conf_read(pc, tag, i)); 1866 } 1867 for (i = 0x80; i < 0xb0; i += 4) { 1868 if (i % 16 == 0) 1869 printf("\n 0x%02x:", i); 1870 printf(" %08x", pci_conf_read(pc, tag, i)); 1871 } 1872 1873 if (memh == 0) { 1874 printf("\n"); 1875 return; 1876 } 1877 1878 printf("\nsocket regs:"); 1879 for (i = 0; i <= 0x10; i += 0x04) 1880 printf(" %08x", bus_space_read_4(memt, memh, i)); 1881 printf("\nExCA regs:"); 1882 for (i = 0; i < 0x08; ++i) 1883 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1884 printf("\n"); 1885 return; 1886 } 1887 #endif 1888 1889 /* 1890 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1891 * int busno, int function) 1892 * This is the function to make a tag to access config space of 1893 * a CardBus Card. It works same as pci_conf_read. 1894 */ 1895 static cardbustag_t 1896 pccbb_make_tag(cardbus_chipset_tag_t cc, int busno, int function) 1897 { 1898 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1899 1900 return pci_make_tag(sc->sc_pc, busno, 0, function); 1901 } 1902 1903 static void 1904 pccbb_free_tag(cardbus_chipset_tag_t cc, cardbustag_t tag) 1905 { 1906 } 1907 1908 /* 1909 * pccbb_conf_read 1910 * 1911 * This is the function to read the config space of a CardBus card. 1912 * It works the same as pci_conf_read(9). 1913 */ 1914 static cardbusreg_t 1915 pccbb_conf_read(cardbus_chipset_tag_t cc, cardbustag_t tag, int offset) 1916 { 1917 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1918 1919 return pci_conf_read(sc->sc_pc, tag, offset); 1920 } 1921 1922 /* 1923 * pccbb_conf_write 1924 * 1925 * This is the function to write the config space of a CardBus 1926 * card. It works the same as pci_conf_write(9). 1927 */ 1928 static void 1929 pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, int reg, 1930 cardbusreg_t val) 1931 { 1932 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1933 1934 pci_conf_write(sc->sc_pc, tag, reg, val); 1935 } 1936 1937 #if 0 1938 STATIC int 1939 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1940 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 1941 int speed, int flags, 1942 bus_space_handle_t * iohp) 1943 #endif 1944 /* 1945 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1946 * bus_addr_t start, bus_size_t size, 1947 * bus_size_t align, 1948 * struct pcmcia_io_handle *pcihp 1949 * 1950 * This function only allocates I/O region for pccard. This function 1951 * never maps the allocated region to pccard I/O area. 1952 * 1953 * XXX: The interface of this function is not very good, I believe. 1954 */ 1955 STATIC int 1956 pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, 1957 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 1958 { 1959 struct pcic_handle *ph = (struct pcic_handle *)pch; 1960 bus_addr_t ioaddr; 1961 int flags = 0; 1962 bus_space_tag_t iot; 1963 bus_space_handle_t ioh; 1964 bus_addr_t mask; 1965 #if rbus 1966 rbus_tag_t rb; 1967 #endif 1968 if (align == 0) { 1969 align = size; /* XXX: funny??? */ 1970 } 1971 1972 if (start != 0) { 1973 /* XXX: assume all card decode lower 10 bits by its hardware */ 1974 mask = 0x3ff; 1975 /* enforce to use only masked address */ 1976 start &= mask; 1977 } else { 1978 /* 1979 * calculate mask: 1980 * 1. get the most significant bit of size (call it msb). 1981 * 2. compare msb with the value of size. 1982 * 3. if size is larger, shift msb left once. 1983 * 4. obtain mask value to decrement msb. 1984 */ 1985 bus_size_t size_tmp = size; 1986 int shifts = 0; 1987 1988 mask = 1; 1989 while (size_tmp) { 1990 ++shifts; 1991 size_tmp >>= 1; 1992 } 1993 mask = (1 << shifts); 1994 if (mask < size) { 1995 mask <<= 1; 1996 } 1997 --mask; 1998 } 1999 2000 /* 2001 * Allocate some arbitrary I/O space. 2002 */ 2003 2004 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 2005 2006 #if rbus 2007 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 2008 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 2009 return 1; 2010 } 2011 DPRINTF(("pccbb_pcmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2012 (u_long) ioaddr, (u_long) size)); 2013 #else 2014 if (start) { 2015 ioaddr = start; 2016 if (bus_space_map(iot, start, size, 0, &ioh)) { 2017 return 1; 2018 } 2019 DPRINTF(("pccbb_pcmcia_io_alloc map port 0x%lx+0x%lx\n", 2020 (u_long) ioaddr, (u_long) size)); 2021 } else { 2022 flags |= PCMCIA_IO_ALLOCATED; 2023 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 2024 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 2025 size, align, 0, 0, &ioaddr, &ioh)) { 2026 /* No room be able to be get. */ 2027 return 1; 2028 } 2029 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2030 (u_long) ioaddr, (u_long) size)); 2031 } 2032 #endif 2033 2034 pcihp->iot = iot; 2035 pcihp->ioh = ioh; 2036 pcihp->addr = ioaddr; 2037 pcihp->size = size; 2038 pcihp->flags = flags; 2039 2040 return 0; 2041 } 2042 2043 /* 2044 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2045 * struct pcmcia_io_handle *pcihp) 2046 * 2047 * This function only frees I/O region for pccard. 2048 * 2049 * XXX: The interface of this function is not very good, I believe. 2050 */ 2051 void 2052 pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2053 struct pcmcia_io_handle *pcihp) 2054 { 2055 #if !rbus 2056 bus_space_tag_t iot = pcihp->iot; 2057 #endif 2058 bus_space_handle_t ioh = pcihp->ioh; 2059 bus_size_t size = pcihp->size; 2060 2061 #if rbus 2062 struct pccbb_softc *sc = 2063 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 2064 rbus_tag_t rb = sc->sc_rbus_iot; 2065 2066 rbus_space_free(rb, ioh, size, NULL); 2067 #else 2068 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 2069 bus_space_free(iot, ioh, size); 2070 else 2071 bus_space_unmap(iot, ioh, size); 2072 #endif 2073 } 2074 2075 /* 2076 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 2077 * bus_addr_t offset, bus_size_t size, 2078 * struct pcmcia_io_handle *pcihp, 2079 * int *windowp) 2080 * 2081 * This function maps the allocated I/O region to pccard. This function 2082 * never allocates any I/O region for pccard I/O area. I don't 2083 * understand why the original authors of pcmciabus separated alloc and 2084 * map. I believe the two must be unite. 2085 * 2086 * XXX: no wait timing control? 2087 */ 2088 int 2089 pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, bus_addr_t offset, 2090 bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp) 2091 { 2092 struct pcic_handle *ph = (struct pcic_handle *)pch; 2093 bus_addr_t ioaddr = pcihp->addr + offset; 2094 int i, win; 2095 #if defined CBB_DEBUG 2096 static const char *width_names[] = { "dynamic", "io8", "io16" }; 2097 #endif 2098 2099 /* Sanity check I/O handle. */ 2100 2101 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 2102 panic("pccbb_pcmcia_io_map iot is bogus"); 2103 } 2104 2105 /* XXX Sanity check offset/size. */ 2106 2107 win = -1; 2108 for (i = 0; i < PCIC_IO_WINS; i++) { 2109 if ((ph->ioalloc & (1 << i)) == 0) { 2110 win = i; 2111 ph->ioalloc |= (1 << i); 2112 break; 2113 } 2114 } 2115 2116 if (win == -1) { 2117 return 1; 2118 } 2119 2120 *windowp = win; 2121 2122 /* XXX this is pretty gross */ 2123 2124 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2125 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2126 2127 /* XXX wtf is this doing here? */ 2128 2129 #if 0 2130 printf(" port 0x%lx", (u_long) ioaddr); 2131 if (size > 1) { 2132 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2133 } 2134 #endif 2135 2136 ph->io[win].addr = ioaddr; 2137 ph->io[win].size = size; 2138 ph->io[win].width = width; 2139 2140 /* actual dirty register-value changing in the function below. */ 2141 pccbb_pcmcia_do_io_map(ph, win); 2142 2143 return 0; 2144 } 2145 2146 /* 2147 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2148 * 2149 * This function changes register-value to map I/O region for pccard. 2150 */ 2151 static void 2152 pccbb_pcmcia_do_io_map(struct pcic_handle *ph, int win) 2153 { 2154 static u_int8_t pcic_iowidth[3] = { 2155 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2156 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2157 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2158 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2159 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2160 }; 2161 2162 #define PCIC_SIA_START_LOW 0 2163 #define PCIC_SIA_START_HIGH 1 2164 #define PCIC_SIA_STOP_LOW 2 2165 #define PCIC_SIA_STOP_HIGH 3 2166 2167 int regbase_win = 0x8 + win * 0x04; 2168 u_int8_t ioctl, enable; 2169 2170 DPRINTF(("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx " 2171 "width %d\n", win, (unsigned long)ph->io[win].addr, 2172 (unsigned long)ph->io[win].size, ph->io[win].width * 8)); 2173 2174 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2175 ph->io[win].addr & 0xff); 2176 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2177 (ph->io[win].addr >> 8) & 0xff); 2178 2179 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2180 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2181 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2182 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2183 2184 ioctl = Pcic_read(ph, PCIC_IOCTL); 2185 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2186 switch (win) { 2187 case 0: 2188 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2189 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2190 PCIC_IOCTL_IO0_DATASIZE_MASK); 2191 ioctl |= pcic_iowidth[ph->io[win].width]; 2192 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2193 break; 2194 case 1: 2195 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2196 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2197 PCIC_IOCTL_IO1_DATASIZE_MASK); 2198 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2199 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2200 break; 2201 } 2202 Pcic_write(ph, PCIC_IOCTL, ioctl); 2203 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2204 #if defined(CBB_DEBUG) 2205 { 2206 u_int8_t start_low = 2207 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2208 u_int8_t start_high = 2209 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2210 u_int8_t stop_low = 2211 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2212 u_int8_t stop_high = 2213 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2214 printf("pccbb_pcmcia_do_io_map start %02x %02x, " 2215 "stop %02x %02x, ioctl %02x enable %02x\n", 2216 start_low, start_high, stop_low, stop_high, ioctl, enable); 2217 } 2218 #endif 2219 } 2220 2221 /* 2222 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2223 * 2224 * This function unmaps I/O region. No return value. 2225 */ 2226 STATIC void 2227 pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t pch, int win) 2228 { 2229 struct pcic_handle *ph = (struct pcic_handle *)pch; 2230 int reg; 2231 2232 if (win >= PCIC_IO_WINS || win < 0) { 2233 panic("pccbb_pcmcia_io_unmap: window out of range"); 2234 } 2235 2236 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2237 switch (win) { 2238 case 0: 2239 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2240 break; 2241 case 1: 2242 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2243 break; 2244 } 2245 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2246 2247 ph->ioalloc &= ~(1 << win); 2248 } 2249 2250 static int 2251 pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 2252 { 2253 u_int8_t stat; 2254 int i; 2255 2256 /* wait an initial 10ms for quick cards */ 2257 stat = Pcic_read(ph, PCIC_IF_STATUS); 2258 if (stat & PCIC_IF_STATUS_READY) 2259 return (0); 2260 pccbb_pcmcia_delay(ph, 10, "pccwr0"); 2261 for (i = 0; i < 50; i++) { 2262 stat = Pcic_read(ph, PCIC_IF_STATUS); 2263 if (stat & PCIC_IF_STATUS_READY) 2264 return (0); 2265 if ((stat & PCIC_IF_STATUS_CARDDETECT_MASK) != 2266 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2267 return (ENXIO); 2268 /* wait .1s (100ms) each iteration now */ 2269 pccbb_pcmcia_delay(ph, 100, "pccwr1"); 2270 } 2271 2272 printf("pccbb_pcmcia_wait_ready: ready never happened, status=%02x\n", stat); 2273 return (EWOULDBLOCK); 2274 } 2275 2276 /* 2277 * Perform long (msec order) delay. timo is in milliseconds. 2278 */ 2279 static void 2280 pccbb_pcmcia_delay(struct pcic_handle *ph, int timo, const char *wmesg) 2281 { 2282 #ifdef DIAGNOSTIC 2283 if (timo <= 0) 2284 panic("pccbb_pcmcia_delay: called with timeout %d", timo); 2285 if (!curlwp) 2286 panic("pccbb_pcmcia_delay: called in interrupt context"); 2287 #if 0 2288 if (!ph->event_thread) 2289 panic("pccbb_pcmcia_delay: no event thread"); 2290 #endif 2291 #endif 2292 DPRINTF(("pccbb_pcmcia_delay: \"%s\" %p, sleep %d ms\n", 2293 wmesg, ph->event_thread, timo)); 2294 tsleep(pccbb_pcmcia_delay, PWAIT, wmesg, roundup(timo * hz, 1000) / 1000); 2295 } 2296 2297 /* 2298 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2299 * 2300 * This function enables the card. All information is stored in 2301 * the first argument, pcmcia_chipset_handle_t. 2302 */ 2303 STATIC void 2304 pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2305 { 2306 struct pcic_handle *ph = (struct pcic_handle *)pch; 2307 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2308 pcireg_t spsr; 2309 int voltage; 2310 int win; 2311 u_int8_t power, intr; 2312 #ifdef DIAGNOSTIC 2313 int reg; 2314 #endif 2315 2316 /* this bit is mostly stolen from pcic_attach_card */ 2317 2318 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2319 2320 /* get card Vcc info */ 2321 spsr = 2322 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2323 CB_SOCKET_STAT); 2324 if (spsr & CB_SOCKET_STAT_5VCARD) { 2325 DPRINTF(("5V card\n")); 2326 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2327 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2328 DPRINTF(("3V card\n")); 2329 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2330 } else { 2331 DPRINTF(("?V card, 0x%x\n", spsr)); /* XXX */ 2332 return; 2333 } 2334 2335 /* disable interrupts; assert RESET */ 2336 intr = Pcic_read(ph, PCIC_INTR); 2337 intr &= PCIC_INTR_ENABLE; 2338 Pcic_write(ph, PCIC_INTR, intr); 2339 2340 /* zero out the address windows */ 2341 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2342 2343 /* power down the socket to reset it, clear the card reset pin */ 2344 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2345 2346 /* power off; assert output enable bit */ 2347 power = PCIC_PWRCTL_OE; 2348 Pcic_write(ph, PCIC_PWRCTL, power); 2349 2350 /* power up the socket */ 2351 if (pccbb_power(sc, voltage) == 0) 2352 return; 2353 2354 /* 2355 * Table 4-18 and figure 4-6 of the PC Card specifiction say: 2356 * Vcc Rising Time (Tpr) = 100ms (handled in pccbb_power() above) 2357 * RESET Width (Th (Hi-z RESET)) = 1ms 2358 * RESET Width (Tw (RESET)) = 10us 2359 * 2360 * some machines require some more time to be settled 2361 * for example old toshiba topic bridges! 2362 * (100ms is added here). 2363 */ 2364 pccbb_pcmcia_delay(ph, 200 + 1, "pccen1"); 2365 2366 /* negate RESET */ 2367 intr |= PCIC_INTR_RESET; 2368 Pcic_write(ph, PCIC_INTR, intr); 2369 2370 /* 2371 * RESET Setup Time (Tsu (RESET)) = 20ms 2372 */ 2373 pccbb_pcmcia_delay(ph, 20, "pccen2"); 2374 2375 #ifdef DIAGNOSTIC 2376 reg = Pcic_read(ph, PCIC_IF_STATUS); 2377 if ((reg & PCIC_IF_STATUS_POWERACTIVE) == 0) 2378 printf("pccbb_pcmcia_socket_enable: no power, status=%x\n", reg); 2379 #endif 2380 2381 /* wait for the chip to finish initializing */ 2382 if (pccbb_pcmcia_wait_ready(ph)) { 2383 #ifdef DIAGNOSTIC 2384 printf("pccbb_pcmcia_socket_enable: never became ready\n"); 2385 #endif 2386 /* XXX return a failure status?? */ 2387 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2388 Pcic_write(ph, PCIC_PWRCTL, 0); 2389 return; 2390 } 2391 2392 /* reinstall all the memory and io mappings */ 2393 for (win = 0; win < PCIC_MEM_WINS; ++win) 2394 if (ph->memalloc & (1 << win)) 2395 pccbb_pcmcia_do_mem_map(ph, win); 2396 for (win = 0; win < PCIC_IO_WINS; ++win) 2397 if (ph->ioalloc & (1 << win)) 2398 pccbb_pcmcia_do_io_map(ph, win); 2399 } 2400 2401 /* 2402 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2403 * 2404 * This function disables the card. All information is stored in 2405 * the first argument, pcmcia_chipset_handle_t. 2406 */ 2407 STATIC void 2408 pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t pch) 2409 { 2410 struct pcic_handle *ph = (struct pcic_handle *)pch; 2411 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2412 u_int8_t intr; 2413 2414 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2415 2416 /* disable interrupts; assert RESET */ 2417 intr = Pcic_read(ph, PCIC_INTR); 2418 intr &= PCIC_INTR_ENABLE; 2419 Pcic_write(ph, PCIC_INTR, intr); 2420 2421 /* zero out the address windows */ 2422 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2423 2424 /* power down the socket to reset it, clear the card reset pin */ 2425 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2426 2427 /* disable socket: negate output enable bit and power off */ 2428 Pcic_write(ph, PCIC_PWRCTL, 0); 2429 2430 /* 2431 * Vcc Falling Time (Tpf) = 300ms 2432 */ 2433 pccbb_pcmcia_delay(ph, 300, "pccwr1"); 2434 } 2435 2436 STATIC void 2437 pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t pch, int type) 2438 { 2439 struct pcic_handle *ph = (struct pcic_handle *)pch; 2440 u_int8_t intr; 2441 2442 /* set the card type */ 2443 2444 intr = Pcic_read(ph, PCIC_INTR); 2445 intr &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_CARDTYPE_MASK); 2446 if (type == PCMCIA_IFTYPE_IO) 2447 intr |= PCIC_INTR_CARDTYPE_IO; 2448 else 2449 intr |= PCIC_INTR_CARDTYPE_MEM; 2450 Pcic_write(ph, PCIC_INTR, intr); 2451 2452 DPRINTF(("%s: pccbb_pcmcia_socket_settype %02x type %s %02x\n", 2453 ph->ph_parent->dv_xname, ph->sock, 2454 ((type == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2455 } 2456 2457 /* 2458 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2459 * 2460 * This function detects whether a card is in the slot or not. 2461 * If a card is inserted, return 1. Otherwise, return 0. 2462 */ 2463 STATIC int 2464 pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch) 2465 { 2466 struct pcic_handle *ph = (struct pcic_handle *)pch; 2467 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2468 2469 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2470 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2471 } 2472 2473 #if 0 2474 STATIC int 2475 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2476 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2477 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2478 #endif 2479 /* 2480 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2481 * bus_size_t size, 2482 * struct pcmcia_mem_handle *pcmhp) 2483 * 2484 * This function only allocates memory region for pccard. This 2485 * function never maps the allocated region to pccard memory area. 2486 * 2487 * XXX: Why the argument of start address is not in? 2488 */ 2489 STATIC int 2490 pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 2491 struct pcmcia_mem_handle *pcmhp) 2492 { 2493 struct pcic_handle *ph = (struct pcic_handle *)pch; 2494 bus_space_handle_t memh; 2495 bus_addr_t addr; 2496 bus_size_t sizepg; 2497 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2498 #if rbus 2499 rbus_tag_t rb; 2500 #endif 2501 2502 /* Check that the card is still there. */ 2503 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2504 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2505 return 1; 2506 2507 /* out of sc->memh, allocate as many pages as necessary */ 2508 2509 /* convert size to PCIC pages */ 2510 /* 2511 * This is not enough; when the requested region is on the page 2512 * boundaries, this may calculate wrong result. 2513 */ 2514 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2515 #if 0 2516 if (sizepg > PCIC_MAX_MEM_PAGES) { 2517 return 1; 2518 } 2519 #endif 2520 2521 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2522 return 1; 2523 } 2524 2525 addr = 0; /* XXX gcc -Wuninitialized */ 2526 2527 #if rbus 2528 rb = sc->sc_rbus_memt; 2529 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2530 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2531 &addr, &memh)) { 2532 return 1; 2533 } 2534 #else 2535 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2536 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2537 0, /* boundary */ 2538 0, /* flags */ 2539 &addr, &memh)) { 2540 return 1; 2541 } 2542 #endif 2543 2544 DPRINTF(("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, " 2545 "realsize 0x%lx\n", (unsigned long)addr, (unsigned long)size, 2546 (unsigned long)sizepg * PCIC_MEM_PAGESIZE)); 2547 2548 pcmhp->memt = sc->sc_memt; 2549 pcmhp->memh = memh; 2550 pcmhp->addr = addr; 2551 pcmhp->size = size; 2552 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2553 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2554 pcmhp->mhandle = 0; 2555 /* No offset??? Funny. */ 2556 2557 return 0; 2558 } 2559 2560 /* 2561 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2562 * struct pcmcia_mem_handle *pcmhp) 2563 * 2564 * This function release the memory space allocated by the function 2565 * pccbb_pcmcia_mem_alloc(). 2566 */ 2567 STATIC void 2568 pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2569 struct pcmcia_mem_handle *pcmhp) 2570 { 2571 #if rbus 2572 struct pcic_handle *ph = (struct pcic_handle *)pch; 2573 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2574 2575 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2576 #else 2577 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2578 #endif 2579 } 2580 2581 /* 2582 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2583 * 2584 * This function release the memory space allocated by the function 2585 * pccbb_pcmcia_mem_alloc(). 2586 */ 2587 STATIC void 2588 pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2589 { 2590 int regbase_win; 2591 bus_addr_t phys_addr; 2592 bus_addr_t phys_end; 2593 2594 #define PCIC_SMM_START_LOW 0 2595 #define PCIC_SMM_START_HIGH 1 2596 #define PCIC_SMM_STOP_LOW 2 2597 #define PCIC_SMM_STOP_HIGH 3 2598 #define PCIC_CMA_LOW 4 2599 #define PCIC_CMA_HIGH 5 2600 2601 u_int8_t start_low, start_high = 0; 2602 u_int8_t stop_low, stop_high; 2603 u_int8_t off_low, off_high; 2604 u_int8_t mem_window; 2605 int reg; 2606 2607 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2608 int mem8 = 2609 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2610 || (kind == PCMCIA_MEM_ATTR); 2611 2612 regbase_win = 0x10 + win * 0x08; 2613 2614 phys_addr = ph->mem[win].addr; 2615 phys_end = phys_addr + ph->mem[win].size; 2616 2617 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2618 (unsigned long)phys_addr, (unsigned long)phys_end, 2619 (unsigned long)ph->mem[win].offset)); 2620 2621 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2622 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2623 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2624 2625 /* bit 19:12 */ 2626 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2627 /* bit 23:20 and bit 7 on */ 2628 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2629 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2630 /* bit 31:24, for 32-bit address */ 2631 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2632 2633 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2634 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2635 2636 if (((struct pccbb_softc *)ph-> 2637 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2638 Pcic_write(ph, 0x40 + win, mem_window); 2639 } 2640 2641 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2642 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2643 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2644 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2645 2646 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2647 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2648 2649 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2650 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2651 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2652 | ((kind == PCMCIA_MEM_ATTR) ? 2653 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2654 2655 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2656 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2657 2658 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2659 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2660 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2661 2662 #if defined(CBB_DEBUG) 2663 { 2664 int r1, r2, r3, r4, r5, r6, r7 = 0; 2665 2666 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2667 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2668 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2669 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2670 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2671 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2672 if (((struct pccbb_softc *)(ph-> 2673 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2674 r7 = Pcic_read(ph, 0x40 + win); 2675 } 2676 2677 printf("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2678 "%02x%02x", win, r1, r2, r3, r4, r5, r6); 2679 if (((struct pccbb_softc *)(ph-> 2680 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2681 printf(" %02x", r7); 2682 } 2683 printf("\n"); 2684 } 2685 #endif 2686 } 2687 2688 /* 2689 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2690 * bus_addr_t card_addr, bus_size_t size, 2691 * struct pcmcia_mem_handle *pcmhp, 2692 * bus_addr_t *offsetp, int *windowp) 2693 * 2694 * This function maps memory space allocated by the function 2695 * pccbb_pcmcia_mem_alloc(). 2696 */ 2697 STATIC int 2698 pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2699 bus_addr_t card_addr, bus_size_t size, struct pcmcia_mem_handle *pcmhp, 2700 bus_addr_t *offsetp, int *windowp) 2701 { 2702 struct pcic_handle *ph = (struct pcic_handle *)pch; 2703 bus_addr_t busaddr; 2704 long card_offset; 2705 int win; 2706 2707 /* Check that the card is still there. */ 2708 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2709 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2710 return 1; 2711 2712 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2713 if ((ph->memalloc & (1 << win)) == 0) { 2714 ph->memalloc |= (1 << win); 2715 break; 2716 } 2717 } 2718 2719 if (win == PCIC_MEM_WINS) { 2720 return 1; 2721 } 2722 2723 *windowp = win; 2724 2725 /* XXX this is pretty gross */ 2726 2727 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2728 panic("pccbb_pcmcia_mem_map memt is bogus"); 2729 } 2730 2731 busaddr = pcmhp->addr; 2732 2733 /* 2734 * compute the address offset to the pcmcia address space for the 2735 * pcic. this is intentionally signed. The masks and shifts below 2736 * will cause TRT to happen in the pcic registers. Deal with making 2737 * sure the address is aligned, and return the alignment offset. 2738 */ 2739 2740 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2741 card_addr -= *offsetp; 2742 2743 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2744 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2745 (u_long) card_addr)); 2746 2747 /* 2748 * include the offset in the size, and decrement size by one, since 2749 * the hw wants start/stop 2750 */ 2751 size += *offsetp - 1; 2752 2753 card_offset = (((long)card_addr) - ((long)busaddr)); 2754 2755 ph->mem[win].addr = busaddr; 2756 ph->mem[win].size = size; 2757 ph->mem[win].offset = card_offset; 2758 ph->mem[win].kind = kind; 2759 2760 pccbb_pcmcia_do_mem_map(ph, win); 2761 2762 return 0; 2763 } 2764 2765 /* 2766 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2767 * int window) 2768 * 2769 * This function unmaps memory space which mapped by the function 2770 * pccbb_pcmcia_mem_map(). 2771 */ 2772 STATIC void 2773 pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, int window) 2774 { 2775 struct pcic_handle *ph = (struct pcic_handle *)pch; 2776 int reg; 2777 2778 if (window >= PCIC_MEM_WINS) { 2779 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2780 } 2781 2782 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2783 reg &= ~(1 << window); 2784 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2785 2786 ph->memalloc &= ~(1 << window); 2787 } 2788 2789 #if defined PCCBB_PCMCIA_POLL 2790 struct pccbb_poll_str { 2791 void *arg; 2792 int (*func)(void *); 2793 int level; 2794 struct pcic_handle *ph; 2795 int count; 2796 int num; 2797 struct callout poll_ch; 2798 }; 2799 2800 static struct pccbb_poll_str pccbb_poll[10]; 2801 static int pccbb_poll_n = 0; 2802 2803 static void pccbb_pcmcia_poll(void *arg); 2804 2805 static void 2806 pccbb_pcmcia_poll(void *arg) 2807 { 2808 struct pccbb_poll_str *poll = arg; 2809 struct pcic_handle *ph = poll->ph; 2810 struct pccbb_softc *sc = ph->sc; 2811 int s; 2812 u_int32_t spsr; /* socket present-state reg */ 2813 2814 callout_reset(&poll->poll_ch, hz * 2, pccbb_pcmcia_poll, arg); 2815 switch (poll->level) { 2816 case IPL_NET: 2817 s = splnet(); 2818 break; 2819 case IPL_BIO: 2820 s = splbio(); 2821 break; 2822 case IPL_TTY: /* fallthrough */ 2823 default: 2824 s = spltty(); 2825 break; 2826 } 2827 2828 spsr = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2829 CB_SOCKET_STAT); 2830 2831 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2832 if (!(spsr & 0x40)) /* CINT low */ 2833 #else 2834 if (1) 2835 #endif 2836 { 2837 if ((*poll->func) (poll->arg) > 0) { 2838 ++poll->count; 2839 /* printf("intr: reported from poller, 0x%x\n", spsr); */ 2840 #if defined LEVEL2 2841 } else { 2842 printf("intr: miss! 0x%x\n", spsr); 2843 #endif 2844 } 2845 } 2846 splx(s); 2847 } 2848 #endif /* defined CB_PCMCIA_POLL */ 2849 2850 /* 2851 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2852 * struct pcmcia_function *pf, 2853 * int ipl, 2854 * int (*func)(void *), 2855 * void *arg); 2856 * 2857 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2858 */ 2859 STATIC void * 2860 pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2861 struct pcmcia_function *pf, int ipl, int (*func)(void *), void *arg) 2862 { 2863 struct pcic_handle *ph = (struct pcic_handle *)pch; 2864 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2865 2866 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2867 /* what should I do? */ 2868 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2869 DPRINTF(("%s does not provide edge nor pulse " 2870 "interrupt\n", sc->sc_dev.dv_xname)); 2871 return NULL; 2872 } 2873 /* 2874 * XXX Noooooo! The interrupt flag must set properly!! 2875 * dumb pcmcia driver!! 2876 */ 2877 } 2878 2879 return pccbb_intr_establish(sc, 0, ipl, func, arg); 2880 } 2881 2882 /* 2883 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2884 * void *ih) 2885 * 2886 * This function disables PC-Card interrupt. 2887 */ 2888 STATIC void 2889 pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 2890 { 2891 struct pcic_handle *ph = (struct pcic_handle *)pch; 2892 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2893 2894 pccbb_intr_disestablish(sc, ih); 2895 } 2896 2897 #if rbus 2898 /* 2899 * static int 2900 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2901 * bus_addr_t addr, bus_size_t size, 2902 * bus_addr_t mask, bus_size_t align, 2903 * int flags, bus_addr_t *addrp; 2904 * bus_space_handle_t *bshp) 2905 * 2906 * This function allocates a portion of memory or io space for 2907 * clients. This function is called from CardBus card drivers. 2908 */ 2909 static int 2910 pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2911 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 2912 int flags, bus_addr_t *addrp, bus_space_handle_t *bshp) 2913 { 2914 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2915 2916 DPRINTF(("pccbb_rbus_cb_space_alloc: addr 0x%lx, size 0x%lx, " 2917 "mask 0x%lx, align 0x%lx\n", (unsigned long)addr, 2918 (unsigned long)size, (unsigned long)mask, (unsigned long)align)); 2919 2920 if (align == 0) { 2921 align = size; 2922 } 2923 2924 if (rb->rb_bt == sc->sc_memt) { 2925 if (align < 16) { 2926 return 1; 2927 } 2928 /* 2929 * XXX: align more than 0x1000 to avoid overwrapping 2930 * memory windows for two or more devices. 0x1000 2931 * means memory window's granularity. 2932 * 2933 * Two or more devices should be able to share same 2934 * memory window region. However, overrapping memory 2935 * window is not good because some devices, such as 2936 * 3Com 3C575[BC], have a broken address decoder and 2937 * intrude other's memory region. 2938 */ 2939 if (align < 0x1000) { 2940 align = 0x1000; 2941 } 2942 } else if (rb->rb_bt == sc->sc_iot) { 2943 if (align < 4) { 2944 return 1; 2945 } 2946 /* XXX: hack for avoiding ISA image */ 2947 if (mask < 0x0100) { 2948 mask = 0x3ff; 2949 addr = 0x300; 2950 } 2951 2952 } else { 2953 DPRINTF(("pccbb_rbus_cb_space_alloc: Bus space tag 0x%lx is " 2954 "NOT used. io: 0x%lx, mem: 0x%lx\n", 2955 (unsigned long)rb->rb_bt, (unsigned long)sc->sc_iot, 2956 (unsigned long)sc->sc_memt)); 2957 return 1; 2958 /* XXX: panic here? */ 2959 } 2960 2961 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 2962 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 2963 return 1; 2964 } 2965 2966 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 2967 2968 return 0; 2969 } 2970 2971 /* 2972 * static int 2973 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 2974 * bus_space_handle_t *bshp, bus_size_t size); 2975 * 2976 * This function is called from CardBus card drivers. 2977 */ 2978 static int 2979 pccbb_rbus_cb_space_free(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2980 bus_space_handle_t bsh, bus_size_t size) 2981 { 2982 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2983 bus_space_tag_t bt = rb->rb_bt; 2984 2985 pccbb_close_win(sc, bt, bsh, size); 2986 2987 if (bt == sc->sc_memt) { 2988 } else if (bt == sc->sc_iot) { 2989 } else { 2990 return 1; 2991 /* XXX: panic here? */ 2992 } 2993 2994 return rbus_space_free(rb, bsh, size, NULL); 2995 } 2996 #endif /* rbus */ 2997 2998 #if rbus 2999 3000 static int 3001 pccbb_open_win(struct pccbb_softc *sc, bus_space_tag_t bst, bus_addr_t addr, 3002 bus_size_t size, bus_space_handle_t bsh, int flags) 3003 { 3004 struct pccbb_win_chain_head *head; 3005 bus_addr_t align; 3006 3007 head = &sc->sc_iowindow; 3008 align = 0x04; 3009 if (sc->sc_memt == bst) { 3010 head = &sc->sc_memwindow; 3011 align = 0x1000; 3012 DPRINTF(("using memory window, 0x%lx 0x%lx 0x%lx\n\n", 3013 (unsigned long)sc->sc_iot, (unsigned long)sc->sc_memt, 3014 (unsigned long)bst)); 3015 } 3016 3017 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 3018 printf("%s: pccbb_open_win: %s winlist insert failed\n", 3019 sc->sc_dev.dv_xname, 3020 (head == &sc->sc_memwindow) ? "mem" : "io"); 3021 } 3022 pccbb_winset(align, sc, bst); 3023 3024 return 0; 3025 } 3026 3027 static int 3028 pccbb_close_win(struct pccbb_softc *sc, bus_space_tag_t bst, 3029 bus_space_handle_t bsh, bus_size_t size) 3030 { 3031 struct pccbb_win_chain_head *head; 3032 bus_addr_t align; 3033 3034 head = &sc->sc_iowindow; 3035 align = 0x04; 3036 if (sc->sc_memt == bst) { 3037 head = &sc->sc_memwindow; 3038 align = 0x1000; 3039 } 3040 3041 if (pccbb_winlist_delete(head, bsh, size)) { 3042 printf("%s: pccbb_close_win: %s winlist delete failed\n", 3043 sc->sc_dev.dv_xname, 3044 (head == &sc->sc_memwindow) ? "mem" : "io"); 3045 } 3046 pccbb_winset(align, sc, bst); 3047 3048 return 0; 3049 } 3050 3051 static int 3052 pccbb_winlist_insert(struct pccbb_win_chain_head *head, bus_addr_t start, 3053 bus_size_t size, bus_space_handle_t bsh, int flags) 3054 { 3055 struct pccbb_win_chain *chainp, *elem; 3056 3057 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 3058 M_NOWAIT)) == NULL) 3059 return (1); /* fail */ 3060 3061 elem->wc_start = start; 3062 elem->wc_end = start + (size - 1); 3063 elem->wc_handle = bsh; 3064 elem->wc_flags = flags; 3065 3066 TAILQ_FOREACH(chainp, head, wc_list) { 3067 if (chainp->wc_end >= start) 3068 break; 3069 } 3070 if (chainp != NULL) 3071 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 3072 else 3073 TAILQ_INSERT_TAIL(head, elem, wc_list); 3074 return (0); 3075 } 3076 3077 static int 3078 pccbb_winlist_delete(struct pccbb_win_chain_head *head, bus_space_handle_t bsh, 3079 bus_size_t size) 3080 { 3081 struct pccbb_win_chain *chainp; 3082 3083 TAILQ_FOREACH(chainp, head, wc_list) { 3084 if (memcmp(&chainp->wc_handle, &bsh, sizeof(bsh)) == 0) 3085 break; 3086 } 3087 if (chainp == NULL) 3088 return 1; /* fail: no candidate to remove */ 3089 3090 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 3091 printf("pccbb_winlist_delete: window 0x%lx size " 3092 "inconsistent: 0x%lx, 0x%lx\n", 3093 (unsigned long)chainp->wc_start, 3094 (unsigned long)(chainp->wc_end - chainp->wc_start), 3095 (unsigned long)(size - 1)); 3096 return 1; 3097 } 3098 3099 TAILQ_REMOVE(head, chainp, wc_list); 3100 free(chainp, M_DEVBUF); 3101 3102 return 0; 3103 } 3104 3105 static void 3106 pccbb_winset(bus_addr_t align, struct pccbb_softc *sc, bus_space_tag_t bst) 3107 { 3108 pci_chipset_tag_t pc; 3109 pcitag_t tag; 3110 bus_addr_t mask = ~(align - 1); 3111 struct { 3112 cardbusreg_t win_start; 3113 cardbusreg_t win_limit; 3114 int win_flags; 3115 } win[2]; 3116 struct pccbb_win_chain *chainp; 3117 int offs; 3118 3119 win[0].win_start = win[1].win_start = 0xffffffff; 3120 win[0].win_limit = win[1].win_limit = 0; 3121 win[0].win_flags = win[1].win_flags = 0; 3122 3123 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3124 offs = 0x2c; 3125 if (sc->sc_memt == bst) { 3126 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3127 offs = 0x1c; 3128 } 3129 3130 if (chainp != NULL) { 3131 win[0].win_start = chainp->wc_start & mask; 3132 win[0].win_limit = chainp->wc_end & mask; 3133 win[0].win_flags = chainp->wc_flags; 3134 chainp = TAILQ_NEXT(chainp, wc_list); 3135 } 3136 3137 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3138 if (win[1].win_start == 0xffffffff) { 3139 /* window 1 is not used */ 3140 if ((win[0].win_flags == chainp->wc_flags) && 3141 (win[0].win_limit + align >= 3142 (chainp->wc_start & mask))) { 3143 /* concatenate */ 3144 win[0].win_limit = chainp->wc_end & mask; 3145 } else { 3146 /* make new window */ 3147 win[1].win_start = chainp->wc_start & mask; 3148 win[1].win_limit = chainp->wc_end & mask; 3149 win[1].win_flags = chainp->wc_flags; 3150 } 3151 continue; 3152 } 3153 3154 /* Both windows are engaged. */ 3155 if (win[0].win_flags == win[1].win_flags) { 3156 /* same flags */ 3157 if (win[0].win_flags == chainp->wc_flags) { 3158 if (win[1].win_start - (win[0].win_limit + 3159 align) < 3160 (chainp->wc_start & mask) - 3161 ((chainp->wc_end & mask) + align)) { 3162 /* 3163 * merge window 0 and 1, and set win1 3164 * to chainp 3165 */ 3166 win[0].win_limit = win[1].win_limit; 3167 win[1].win_start = 3168 chainp->wc_start & mask; 3169 win[1].win_limit = 3170 chainp->wc_end & mask; 3171 } else { 3172 win[1].win_limit = 3173 chainp->wc_end & mask; 3174 } 3175 } else { 3176 /* different flags */ 3177 3178 /* concatenate win0 and win1 */ 3179 win[0].win_limit = win[1].win_limit; 3180 /* allocate win[1] to new space */ 3181 win[1].win_start = chainp->wc_start & mask; 3182 win[1].win_limit = chainp->wc_end & mask; 3183 win[1].win_flags = chainp->wc_flags; 3184 } 3185 } else { 3186 /* the flags of win[0] and win[1] is different */ 3187 if (win[0].win_flags == chainp->wc_flags) { 3188 win[0].win_limit = chainp->wc_end & mask; 3189 /* 3190 * XXX this creates overlapping windows, so 3191 * what should the poor bridge do if one is 3192 * cachable, and the other is not? 3193 */ 3194 printf("%s: overlapping windows\n", 3195 sc->sc_dev.dv_xname); 3196 } else { 3197 win[1].win_limit = chainp->wc_end & mask; 3198 } 3199 } 3200 } 3201 3202 pc = sc->sc_pc; 3203 tag = sc->sc_tag; 3204 pci_conf_write(pc, tag, offs, win[0].win_start); 3205 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3206 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3207 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3208 DPRINTF(("--pccbb_winset: win0 [0x%lx, 0x%lx), win1 [0x%lx, 0x%lx)\n", 3209 (unsigned long)pci_conf_read(pc, tag, offs), 3210 (unsigned long)pci_conf_read(pc, tag, offs + 4) + align, 3211 (unsigned long)pci_conf_read(pc, tag, offs + 8), 3212 (unsigned long)pci_conf_read(pc, tag, offs + 12) + align)); 3213 3214 if (bst == sc->sc_memt) { 3215 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BRIDGE_CONTROL_REG); 3216 3217 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 3218 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 3219 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3220 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 3221 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3222 pci_conf_write(pc, tag, PCI_BRIDGE_CONTROL_REG, bcr); 3223 } 3224 } 3225 3226 #endif /* rbus */ 3227 3228 static bool 3229 pccbb_suspend(device_t dv) 3230 { 3231 struct pccbb_softc *sc = device_private(dv); 3232 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3233 bus_space_handle_t base_memh = sc->sc_base_memh; 3234 pcireg_t reg; 3235 3236 if (sc->sc_pil_intr_enable) 3237 (void)pccbbintr_function(sc); 3238 sc->sc_pil_intr_enable = 0; 3239 3240 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3241 /* Disable interrupts. */ 3242 reg &= ~(CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER); 3243 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3244 /* XXX joerg Disable power to the socket? */ 3245 3246 if (sc->sc_chipset == CB_RX5C47X) 3247 sc->sc_ricoh_misc_ctrl = pci_conf_read(sc->sc_pc, 3248 sc->sc_tag, RICOH_PCI_MISC_CTRL); 3249 3250 return true; 3251 } 3252 3253 static bool 3254 pccbb_resume(device_t dv) 3255 { 3256 struct pccbb_softc *sc = device_private(dv); 3257 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3258 bus_space_handle_t base_memh = sc->sc_base_memh; 3259 pcireg_t reg; 3260 3261 pccbb_chipinit(sc); 3262 /* setup memory and io space window for CB */ 3263 pccbb_winset(0x1000, sc, sc->sc_memt); 3264 pccbb_winset(0x04, sc, sc->sc_iot); 3265 if (sc->sc_chipset == CB_RX5C47X) 3266 pci_conf_write(sc->sc_pc, sc->sc_tag, 3267 RICOH_PCI_MISC_CTRL, sc->sc_ricoh_misc_ctrl); 3268 3269 /* CSC Interrupt: Card detect interrupt on */ 3270 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3271 /* Card detect intr is turned on. */ 3272 reg |= CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; 3273 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3274 /* reset interrupt */ 3275 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3276 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3277 3278 /* 3279 * check for card insertion or removal during suspend period. 3280 * XXX: the code can't cope with card swap (remove then 3281 * insert). how can we detect such situation? 3282 */ 3283 (void)pccbbintr(sc); 3284 3285 sc->sc_pil_intr_enable = 1; 3286 3287 return true; 3288 } 3289
Indexes created Thu Sep 25 16:09:42 GMT 2025