pccbb.c revision 1.158
1 /* $NetBSD: pccbb.c,v 1.158 2007/12/16 21:28:31 dyoung Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: pccbb.c,v 1.158 2007/12/16 21:28:31 dyoung Exp $"); 35 36 /* 37 #define CBB_DEBUG 38 #define SHOW_REGS 39 */ 40 41 /* 42 * BROKEN! 43 #define PCCBB_PCMCIA_POLL 44 #define CB_PCMCIA_POLL 45 #define CB_PCMCIA_POLL_ONLY 46 #define LEVEL2 47 */ 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/kernel.h> 52 #include <sys/errno.h> 53 #include <sys/ioctl.h> 54 #include <sys/reboot.h> /* for bootverbose */ 55 #include <sys/syslog.h> 56 #include <sys/device.h> 57 #include <sys/malloc.h> 58 #include <sys/proc.h> 59 60 #include <sys/intr.h> 61 #include <sys/bus.h> 62 63 #include <dev/pci/pcivar.h> 64 #include <dev/pci/pcireg.h> 65 #include <dev/pci/pcidevs.h> 66 67 #include <dev/pci/pccbbreg.h> 68 69 #include <dev/cardbus/cardslotvar.h> 70 71 #include <dev/cardbus/cardbusvar.h> 72 73 #include <dev/pcmcia/pcmciareg.h> 74 #include <dev/pcmcia/pcmciavar.h> 75 76 #include <dev/ic/i82365reg.h> 77 #include <dev/ic/i82365var.h> 78 #include <dev/pci/pccbbvar.h> 79 80 #include "locators.h" 81 82 #ifndef __NetBSD_Version__ 83 struct cfdriver cbb_cd = { 84 NULL, "cbb", DV_DULL 85 }; 86 #endif 87 88 #ifdef CBB_DEBUG 89 #define DPRINTF(x) printf x 90 #define STATIC 91 #else 92 #define DPRINTF(x) 93 #define STATIC static 94 #endif 95 96 int pccbb_burstup = 1; 97 98 /* 99 * delay_ms() is wait in milliseconds. It should be used instead 100 * of delay() if you want to wait more than 1 ms. 101 */ 102 static inline void 103 delay_ms(int millis, void *param) 104 { 105 if (cold) 106 delay(millis * 1000); 107 else 108 tsleep(param, PWAIT, "pccbb", MAX(2, hz * millis / 1000)); 109 } 110 111 int pcicbbmatch(struct device *, struct cfdata *, void *); 112 void pccbbattach(struct device *, struct device *, void *); 113 int pccbbdetach(device_t, int); 114 int pccbbintr(void *); 115 static void pci113x_insert(void *); 116 static int pccbbintr_function(struct pccbb_softc *); 117 118 static int pccbb_detect_card(struct pccbb_softc *); 119 120 static void pccbb_pcmcia_write(struct pcic_handle *, int, u_int8_t); 121 static u_int8_t pccbb_pcmcia_read(struct pcic_handle *, int); 122 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 123 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 124 125 STATIC int cb_reset(struct pccbb_softc *); 126 STATIC int cb_detect_voltage(struct pccbb_softc *); 127 STATIC int cbbprint(void *, const char *); 128 129 static int cb_chipset(u_int32_t, int *); 130 STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *, 131 struct pcmciabus_attach_args *); 132 #if 0 133 STATIC void pccbb_pcmcia_attach_card(struct pcic_handle *); 134 STATIC void pccbb_pcmcia_detach_card(struct pcic_handle *, int); 135 STATIC void pccbb_pcmcia_deactivate_card(struct pcic_handle *); 136 #endif 137 138 STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int); 139 STATIC int pccbb_power(cardbus_chipset_tag_t, int); 140 STATIC int pccbb_cardenable(struct pccbb_softc * sc, int function); 141 #if !rbus 142 static int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 143 static int pccbb_io_close(cardbus_chipset_tag_t, int); 144 static int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 145 static int pccbb_mem_close(cardbus_chipset_tag_t, int); 146 #endif /* !rbus */ 147 static void *pccbb_intr_establish(struct pccbb_softc *, int irq, 148 int level, int (*ih) (void *), void *sc); 149 static void pccbb_intr_disestablish(struct pccbb_softc *, void *ih); 150 151 static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t, int irq, 152 int level, int (*ih) (void *), void *sc); 153 static void pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih); 154 155 static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t, int, int); 156 static void pccbb_free_tag(cardbus_chipset_tag_t, cardbustag_t); 157 static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t, cardbustag_t, int); 158 static void pccbb_conf_write(cardbus_chipset_tag_t, cardbustag_t, int, 159 cardbusreg_t); 160 static void pccbb_chipinit(struct pccbb_softc *); 161 162 STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 163 struct pcmcia_mem_handle *); 164 STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t, 165 struct pcmcia_mem_handle *); 166 STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 167 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *); 168 STATIC void pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t, int); 169 STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 170 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 171 STATIC void pccbb_pcmcia_io_free(pcmcia_chipset_handle_t, 172 struct pcmcia_io_handle *); 173 STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 174 bus_size_t, struct pcmcia_io_handle *, int *); 175 STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t, int); 176 STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t, 177 struct pcmcia_function *, int, int (*)(void *), void *); 178 STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t, void *); 179 STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t); 180 STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t); 181 STATIC void pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t, int); 182 STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch); 183 184 static int pccbb_pcmcia_wait_ready(struct pcic_handle *); 185 static void pccbb_pcmcia_delay(struct pcic_handle *, int, const char *); 186 187 static void pccbb_pcmcia_do_io_map(struct pcic_handle *, int); 188 static void pccbb_pcmcia_do_mem_map(struct pcic_handle *, int); 189 190 /* bus-space allocation and deallocation functions */ 191 #if rbus 192 193 static int pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t, rbus_tag_t, 194 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 195 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp); 196 static int pccbb_rbus_cb_space_free(cardbus_chipset_tag_t, rbus_tag_t, 197 bus_space_handle_t, bus_size_t); 198 199 #endif /* rbus */ 200 201 #if rbus 202 203 static int pccbb_open_win(struct pccbb_softc *, bus_space_tag_t, 204 bus_addr_t, bus_size_t, bus_space_handle_t, int flags); 205 static int pccbb_close_win(struct pccbb_softc *, bus_space_tag_t, 206 bus_space_handle_t, bus_size_t); 207 static int pccbb_winlist_insert(struct pccbb_win_chain_head *, bus_addr_t, 208 bus_size_t, bus_space_handle_t, int); 209 static int pccbb_winlist_delete(struct pccbb_win_chain_head *, 210 bus_space_handle_t, bus_size_t); 211 static void pccbb_winset(bus_addr_t align, struct pccbb_softc *, 212 bus_space_tag_t); 213 void pccbb_winlist_show(struct pccbb_win_chain *); 214 215 #endif /* rbus */ 216 217 /* for config_defer */ 218 static void pccbb_pci_callback(struct device *); 219 220 static bool pccbb_suspend(device_t); 221 static bool pccbb_resume(device_t); 222 223 #if defined SHOW_REGS 224 static void cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, 225 bus_space_tag_t memt, bus_space_handle_t memh); 226 #endif 227 228 CFATTACH_DECL(cbb_pci, sizeof(struct pccbb_softc), 229 pcicbbmatch, pccbbattach, pccbbdetach, NULL); 230 231 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 232 pccbb_pcmcia_mem_alloc, 233 pccbb_pcmcia_mem_free, 234 pccbb_pcmcia_mem_map, 235 pccbb_pcmcia_mem_unmap, 236 pccbb_pcmcia_io_alloc, 237 pccbb_pcmcia_io_free, 238 pccbb_pcmcia_io_map, 239 pccbb_pcmcia_io_unmap, 240 pccbb_pcmcia_intr_establish, 241 pccbb_pcmcia_intr_disestablish, 242 pccbb_pcmcia_socket_enable, 243 pccbb_pcmcia_socket_disable, 244 pccbb_pcmcia_socket_settype, 245 pccbb_pcmcia_card_detect 246 }; 247 248 #if rbus 249 static struct cardbus_functions pccbb_funcs = { 250 pccbb_rbus_cb_space_alloc, 251 pccbb_rbus_cb_space_free, 252 pccbb_cb_intr_establish, 253 pccbb_cb_intr_disestablish, 254 pccbb_ctrl, 255 pccbb_power, 256 pccbb_make_tag, 257 pccbb_free_tag, 258 pccbb_conf_read, 259 pccbb_conf_write, 260 }; 261 #else 262 static struct cardbus_functions pccbb_funcs = { 263 pccbb_ctrl, 264 pccbb_power, 265 pccbb_mem_open, 266 pccbb_mem_close, 267 pccbb_io_open, 268 pccbb_io_close, 269 pccbb_cb_intr_establish, 270 pccbb_cb_intr_disestablish, 271 pccbb_make_tag, 272 pccbb_conf_read, 273 pccbb_conf_write, 274 }; 275 #endif 276 277 int 278 pcicbbmatch(struct device *parent, struct cfdata *match, void *aux) 279 { 280 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 281 282 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 283 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 284 PCI_INTERFACE(pa->pa_class) == 0) { 285 return 1; 286 } 287 288 return 0; 289 } 290 291 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 292 | ((prod) << PCI_PRODUCT_SHIFT)) 293 294 const struct yenta_chipinfo { 295 pcireg_t yc_id; /* vendor tag | product tag */ 296 int yc_chiptype; 297 int yc_flags; 298 } yc_chipsets[] = { 299 /* Texas Instruments chips */ 300 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 301 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 302 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 303 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 304 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI125X, 305 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 306 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 307 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 308 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 309 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 310 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 311 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 312 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI125X, 313 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 314 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI125X, 315 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 316 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 317 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 318 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 319 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 320 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI1420, 321 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 322 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI125X, 323 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 324 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 325 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 326 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1520), CB_TI12XX, 327 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 328 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4410YENTA), CB_TI12XX, 329 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 330 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4520YENTA), CB_TI12XX, 331 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 332 333 /* Ricoh chips */ 334 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 335 PCCBB_PCMCIA_MEM_32}, 336 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 337 PCCBB_PCMCIA_MEM_32}, 338 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 339 PCCBB_PCMCIA_MEM_32}, 340 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 341 PCCBB_PCMCIA_MEM_32}, 342 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 343 PCCBB_PCMCIA_MEM_32}, 344 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 345 PCCBB_PCMCIA_MEM_32}, 346 347 /* Toshiba products */ 348 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 349 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 350 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 351 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 352 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 353 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 354 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 355 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 356 357 /* Cirrus Logic products */ 358 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 359 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 360 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 361 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 362 363 /* sentinel, or Generic chip */ 364 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 365 }; 366 367 static int 368 cb_chipset(u_int32_t pci_id, int *flagp) 369 { 370 const struct yenta_chipinfo *yc; 371 372 /* Loop over except the last default entry. */ 373 for (yc = yc_chipsets; yc < yc_chipsets + 374 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 375 if (pci_id == yc->yc_id) 376 break; 377 378 if (flagp != NULL) 379 *flagp = yc->yc_flags; 380 381 return (yc->yc_chiptype); 382 } 383 384 void 385 pccbbattach(struct device *parent, struct device *self, void *aux) 386 { 387 struct pccbb_softc *sc = (void *)self; 388 struct pci_attach_args *pa = aux; 389 pci_chipset_tag_t pc = pa->pa_pc; 390 pcireg_t busreg, reg, sock_base; 391 bus_addr_t sockbase; 392 char devinfo[256]; 393 int flags; 394 395 #ifdef __HAVE_PCCBB_ATTACH_HOOK 396 pccbb_attach_hook(parent, self, pa); 397 #endif 398 399 callout_init(&sc->sc_insert_ch, 0); 400 callout_setfunc(&sc->sc_insert_ch, pci113x_insert, sc); 401 402 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 403 404 aprint_naive("\n"); 405 406 pci_devinfo(pa->pa_id, 0, 0, devinfo, sizeof(devinfo)); 407 aprint_normal(": %s (rev. 0x%02x)", devinfo, 408 PCI_REVISION(pa->pa_class)); 409 DPRINTF((" (chipflags %x)", flags)); 410 aprint_normal("\n"); 411 412 TAILQ_INIT(&sc->sc_memwindow); 413 TAILQ_INIT(&sc->sc_iowindow); 414 415 #if rbus 416 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 417 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 418 419 #if 0 420 printf("pa->pa_memt: %08x vs rbus_mem->rb_bt: %08x\n", 421 pa->pa_memt, sc->sc_rbus_memt->rb_bt); 422 #endif 423 #endif /* rbus */ 424 425 sc->sc_flags &= ~CBB_MEMHMAPPED; 426 427 /* 428 * MAP socket registers and ExCA registers on memory-space 429 * When no valid address is set on socket base registers (on pci 430 * config space), get it not polite way. 431 */ 432 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 433 434 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 435 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 436 /* The address must be valid. */ 437 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 438 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, &sc->sc_base_size)) { 439 aprint_error("%s: can't map socket base address 0x%lx\n", 440 sc->sc_dev.dv_xname, (unsigned long)sock_base); 441 /* 442 * I think it's funny: socket base registers must be 443 * mapped on memory space, but ... 444 */ 445 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 446 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 447 &sc->sc_base_size)) { 448 aprint_error("%s: can't map socket base address" 449 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 450 (unsigned long)sockbase); 451 /* give up... allocate reg space via rbus. */ 452 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 453 } else 454 sc->sc_flags |= CBB_MEMHMAPPED; 455 } else { 456 DPRINTF(("%s: socket base address 0x%lx\n", 457 sc->sc_dev.dv_xname, (unsigned long)sockbase)); 458 sc->sc_flags |= CBB_MEMHMAPPED; 459 } 460 } 461 462 sc->sc_mem_start = 0; /* XXX */ 463 sc->sc_mem_end = 0xffffffff; /* XXX */ 464 465 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 466 467 /* pccbb_machdep.c end */ 468 469 #if defined CBB_DEBUG 470 { 471 static const char *intrname[] = { "NON", "A", "B", "C", "D" }; 472 printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname, 473 intrname[pa->pa_intrpin], pa->pa_intrline); 474 } 475 #endif 476 477 /* setup softc */ 478 sc->sc_pc = pc; 479 sc->sc_iot = pa->pa_iot; 480 sc->sc_memt = pa->pa_memt; 481 sc->sc_dmat = pa->pa_dmat; 482 sc->sc_tag = pa->pa_tag; 483 sc->sc_function = pa->pa_function; 484 485 memcpy(&sc->sc_pa, pa, sizeof(*pa)); 486 487 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 488 489 /* Disable legacy register mapping. */ 490 switch (sc->sc_chipset) { 491 case CB_RX5C46X: /* fallthrough */ 492 #if 0 493 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 494 case CB_RX5C47X: 495 #endif 496 /* 497 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 498 * cannot be disabled by substituting 0 into PCI_LEGACY 499 * register. Ricoh CardBus bridges have special bits on Bridge 500 * control reg (addr 0x3e on PCI config space). 501 */ 502 reg = pci_conf_read(pc, pa->pa_tag, PCI_BRIDGE_CONTROL_REG); 503 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 504 pci_conf_write(pc, pa->pa_tag, PCI_BRIDGE_CONTROL_REG, reg); 505 break; 506 507 default: 508 /* XXX I don't know proper way to kill legacy I/O. */ 509 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 510 break; 511 } 512 513 if (!pmf_device_register(self, pccbb_suspend, pccbb_resume)) 514 aprint_error_dev(self, "couldn't establish power handler\n"); 515 516 config_defer(self, pccbb_pci_callback); 517 } 518 519 int 520 pccbbdetach(device_t self, int flags) 521 { 522 struct pccbb_softc *sc = device_private(self); 523 pci_chipset_tag_t pc = sc->sc_pa.pa_pc; 524 bus_space_tag_t bmt = sc->sc_base_memt; 525 bus_space_handle_t bmh = sc->sc_base_memh; 526 uint32_t sockmask; 527 int rc; 528 529 if ((rc = config_detach_children(self, flags)) != 0) 530 return rc; 531 532 if (sc->sc_ih != NULL) { 533 pci_intr_disestablish(pc, sc->sc_ih); 534 sc->sc_ih = NULL; 535 } 536 537 /* CSC Interrupt: turn off card detect and power cycle interrupts */ 538 sockmask = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 539 sockmask &= ~(CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER); 540 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, sockmask); 541 /* reset interrupt */ 542 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 543 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 544 545 switch (sc->sc_flags & (CBB_MEMHMAPPED|CBB_SPECMAPPED)) { 546 case CBB_MEMHMAPPED: 547 bus_space_unmap(bmt, bmh, sc->sc_base_size); 548 break; 549 case CBB_MEMHMAPPED|CBB_SPECMAPPED: 550 #if rbus 551 { 552 pcireg_t sockbase; 553 554 sockbase = pci_conf_read(pc, sc->sc_tag, PCI_SOCKBASE); 555 rbus_space_free(sc->sc_rbus_memt, bmh, 0x1000, 556 NULL); 557 } 558 #else 559 bus_space_free(bmt, bmh, 0x1000); 560 #endif 561 } 562 sc->sc_flags &= ~(CBB_MEMHMAPPED|CBB_SPECMAPPED); 563 564 if (!TAILQ_EMPTY(&sc->sc_iowindow)) 565 aprint_error_dev(self, "i/o windows not empty"); 566 if (!TAILQ_EMPTY(&sc->sc_memwindow)) 567 aprint_error_dev(self, "memory windows not empty"); 568 569 callout_stop(&sc->sc_insert_ch); 570 callout_destroy(&sc->sc_insert_ch); 571 return 0; 572 } 573 574 /* 575 * static void pccbb_pci_callback(struct device *self) 576 * 577 * The actual attach routine: get memory space for YENTA register 578 * space, setup YENTA register and route interrupt. 579 * 580 * This function should be deferred because this device may obtain 581 * memory space dynamically. This function must avoid obtaining 582 * memory area which has already kept for another device. 583 */ 584 static void 585 pccbb_pci_callback(struct device *self) 586 { 587 struct pccbb_softc *sc = (void *)self; 588 pci_chipset_tag_t pc = sc->sc_pc; 589 pci_intr_handle_t ih; 590 const char *intrstr = NULL; 591 bus_addr_t sockbase; 592 struct cbslot_attach_args cba; 593 struct pcmciabus_attach_args paa; 594 struct cardslot_attach_args caa; 595 struct cardslot_softc *csc; 596 597 if (!(sc->sc_flags & CBB_MEMHMAPPED)) { 598 /* The socket registers aren't mapped correctly. */ 599 #if rbus 600 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 601 (sc->sc_chipset == CB_RX5C47X 602 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 603 0, &sockbase, &sc->sc_base_memh)) { 604 return; 605 } 606 sc->sc_base_memt = sc->sc_memt; 607 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 608 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 609 sc->sc_dev.dv_xname, (unsigned long)sockbase, 610 (unsigned long)pci_conf_read(pc, sc->sc_tag, 611 PCI_SOCKBASE))); 612 #else 613 sc->sc_base_memt = sc->sc_memt; 614 #if !defined CBB_PCI_BASE 615 #define CBB_PCI_BASE 0x20000000 616 #endif 617 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 618 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 619 /* cannot allocate memory space */ 620 return; 621 } 622 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 623 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 624 sc->sc_dev.dv_xname, (unsigned long)sock_base, 625 (unsigned long)pci_conf_read(pc, 626 sc->sc_tag, PCI_SOCKBASE))); 627 #endif 628 sc->sc_flags |= CBB_MEMHMAPPED; 629 } 630 631 /* bus bridge initialization */ 632 pccbb_chipinit(sc); 633 634 /* clear data structure for child device interrupt handlers */ 635 LIST_INIT(&sc->sc_pil); 636 sc->sc_pil_intr_enable = 1; 637 638 /* Map and establish the interrupt. */ 639 if (pci_intr_map(&sc->sc_pa, &ih)) { 640 aprint_error("%s: couldn't map interrupt\n", 641 sc->sc_dev.dv_xname); 642 return; 643 } 644 intrstr = pci_intr_string(pc, ih); 645 646 /* 647 * XXX pccbbintr should be called under the priority lower 648 * than any other hard interupts. 649 */ 650 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 651 652 if (sc->sc_ih == NULL) { 653 aprint_error("%s: couldn't establish interrupt", 654 sc->sc_dev.dv_xname); 655 if (intrstr != NULL) { 656 aprint_normal(" at %s", intrstr); 657 } 658 aprint_normal("\n"); 659 return; 660 } 661 662 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 663 664 { 665 u_int32_t sockstat; 666 667 sockstat = bus_space_read_4(sc->sc_base_memt, 668 sc->sc_base_memh, CB_SOCKET_STAT); 669 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 670 sc->sc_flags |= CBB_CARDEXIST; 671 } 672 } 673 674 /* 675 * attach cardbus 676 */ 677 { 678 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 679 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 680 681 /* initialize cbslot_attach */ 682 cba.cba_busname = "cardbus"; 683 cba.cba_iot = sc->sc_iot; 684 cba.cba_memt = sc->sc_memt; 685 cba.cba_dmat = sc->sc_dmat; 686 cba.cba_bus = (busreg >> 8) & 0x0ff; 687 cba.cba_cc = (void *)sc; 688 cba.cba_cf = &pccbb_funcs; 689 cba.cba_intrline = sc->sc_pa.pa_intrline; 690 691 #if rbus 692 cba.cba_rbus_iot = sc->sc_rbus_iot; 693 cba.cba_rbus_memt = sc->sc_rbus_memt; 694 #endif 695 696 cba.cba_cacheline = PCI_CACHELINE(bhlc); 697 cba.cba_max_lattimer = PCI_LATTIMER(bhlc); 698 699 if (bootverbose) { 700 printf("%s: cacheline 0x%x lattimer 0x%x\n", 701 sc->sc_dev.dv_xname, cba.cba_cacheline, 702 cba.cba_max_lattimer); 703 printf("%s: bhlc 0x%x\n", 704 device_xname(&sc->sc_dev), bhlc); 705 } 706 #if defined SHOW_REGS 707 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 708 sc->sc_base_memh); 709 #endif 710 } 711 712 pccbb_pcmcia_attach_setup(sc, &paa); 713 caa.caa_cb_attach = NULL; 714 if (cba.cba_bus == 0) 715 printf("%s: secondary bus number uninitialized; try PCI_BUS_FIXUP\n", sc->sc_dev.dv_xname); 716 else 717 caa.caa_cb_attach = &cba; 718 caa.caa_16_attach = &paa; 719 caa.caa_ph = &sc->sc_pcmcia_h; 720 721 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 722 DPRINTF(("%s: found cardslot\n", __func__)); 723 sc->sc_csc = csc; 724 } 725 726 return; 727 } 728 729 730 731 732 733 /* 734 * static void pccbb_chipinit(struct pccbb_softc *sc) 735 * 736 * This function initialize YENTA chip registers listed below: 737 * 1) PCI command reg, 738 * 2) PCI and CardBus latency timer, 739 * 3) route PCI interrupt, 740 * 4) close all memory and io windows. 741 * 5) turn off bus power. 742 * 6) card detect and power cycle interrupts on. 743 * 7) clear interrupt 744 */ 745 static void 746 pccbb_chipinit(struct pccbb_softc *sc) 747 { 748 pci_chipset_tag_t pc = sc->sc_pc; 749 pcitag_t tag = sc->sc_tag; 750 bus_space_tag_t bmt = sc->sc_base_memt; 751 bus_space_handle_t bmh = sc->sc_base_memh; 752 pcireg_t bcr, bhlc, cbctl, csr, lscp, mfunc, mrburst, slotctl, sockctl, 753 sockmask, sysctrl; 754 755 /* 756 * Set PCI command reg. 757 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 758 */ 759 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 760 /* I believe it is harmless. */ 761 csr |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 762 PCI_COMMAND_MASTER_ENABLE); 763 csr |= (PCI_COMMAND_PARITY_ENABLE|PCI_COMMAND_SERR_ENABLE); 764 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 765 766 /* 767 * Set CardBus latency timer. 768 */ 769 lscp = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 770 if (PCI_CB_LATENCY(lscp) < 0x20) { 771 lscp &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 772 lscp |= (0x20 << PCI_CB_LATENCY_SHIFT); 773 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, lscp); 774 } 775 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 776 PCI_CB_LATENCY(lscp), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 777 778 /* 779 * Set PCI latency timer. 780 */ 781 bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG); 782 if (PCI_LATTIMER(bhlc) < 0x10) { 783 bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 784 bhlc |= (0x10 << PCI_LATTIMER_SHIFT); 785 pci_conf_write(pc, tag, PCI_BHLC_REG, bhlc); 786 } 787 DPRINTF(("PCI latency timer 0x%x (%x)\n", 788 PCI_LATTIMER(bhlc), pci_conf_read(pc, tag, PCI_BHLC_REG))); 789 790 791 /* Route functional interrupts to PCI. */ 792 bcr = pci_conf_read(pc, tag, PCI_BRIDGE_CONTROL_REG); 793 bcr |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 794 bcr |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 795 /* assert reset */ 796 bcr |= PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT; 797 /* Set master abort mode to 1, forward SERR# from secondary 798 * to primary, and detect parity errors on secondary. 799 */ 800 bcr |= PCI_BRIDGE_CONTROL_MABRT << PCI_BRIDGE_CONTROL_SHIFT; 801 bcr |= PCI_BRIDGE_CONTROL_SERR << PCI_BRIDGE_CONTROL_SHIFT; 802 bcr |= PCI_BRIDGE_CONTROL_PERE << PCI_BRIDGE_CONTROL_SHIFT; 803 pci_conf_write(pc, tag, PCI_BRIDGE_CONTROL_REG, bcr); 804 805 switch (sc->sc_chipset) { 806 case CB_TI113X: 807 cbctl = pci_conf_read(pc, tag, PCI_CBCTRL); 808 /* This bit is shared, but may read as 0 on some chips, so set 809 it explicitly on both functions. */ 810 cbctl |= PCI113X_CBCTRL_PCI_IRQ_ENA; 811 /* CSC intr enable */ 812 cbctl |= PCI113X_CBCTRL_PCI_CSC; 813 /* functional intr prohibit | prohibit ISA routing */ 814 cbctl &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 815 pci_conf_write(pc, tag, PCI_CBCTRL, cbctl); 816 break; 817 818 case CB_TI1420: 819 sysctrl = pci_conf_read(pc, tag, PCI_SYSCTRL); 820 mrburst = pccbb_burstup 821 ? PCI1420_SYSCTRL_MRBURST : PCI1420_SYSCTRL_MRBURSTDN; 822 if ((sysctrl & PCI1420_SYSCTRL_MRBURST) == mrburst) { 823 printf("%s: %swrite bursts enabled\n", 824 device_xname(&sc->sc_dev), 825 pccbb_burstup ? "read/" : ""); 826 } else if (pccbb_burstup) { 827 printf("%s: enabling read/write bursts\n", 828 device_xname(&sc->sc_dev)); 829 sysctrl |= PCI1420_SYSCTRL_MRBURST; 830 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 831 } else { 832 printf("%s: disabling read bursts, " 833 "enabling write bursts\n", 834 device_xname(&sc->sc_dev)); 835 sysctrl |= PCI1420_SYSCTRL_MRBURSTDN; 836 sysctrl &= ~PCI1420_SYSCTRL_MRBURSTUP; 837 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 838 } 839 /*FALLTHROUGH*/ 840 case CB_TI12XX: 841 /* 842 * Some TI 12xx (and [14][45]xx) based pci cards 843 * sometimes have issues with the MFUNC register not 844 * being initialized due to a bad EEPROM on board. 845 * Laptops that this matters on have this register 846 * properly initialized. 847 * 848 * The TI125X parts have a different register. 849 */ 850 mfunc = pci_conf_read(pc, tag, PCI12XX_MFUNC); 851 if (mfunc == 0) { 852 mfunc &= ~PCI12XX_MFUNC_PIN0; 853 mfunc |= PCI12XX_MFUNC_PIN0_INTA; 854 if ((pci_conf_read(pc, tag, PCI_SYSCTRL) & 855 PCI12XX_SYSCTRL_INTRTIE) == 0) { 856 mfunc &= ~PCI12XX_MFUNC_PIN1; 857 mfunc |= PCI12XX_MFUNC_PIN1_INTB; 858 } 859 pci_conf_write(pc, tag, PCI12XX_MFUNC, mfunc); 860 } 861 /* fallthrough */ 862 863 case CB_TI125X: 864 /* 865 * Disable zoom video. Some machines initialize this 866 * improperly and experience has shown that this helps 867 * prevent strange behavior. 868 */ 869 pci_conf_write(pc, tag, PCI12XX_MMCTRL, 0); 870 871 sysctrl = pci_conf_read(pc, tag, PCI_SYSCTRL); 872 sysctrl |= PCI12XX_SYSCTRL_VCCPROT; 873 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 874 cbctl = pci_conf_read(pc, tag, PCI_CBCTRL); 875 cbctl |= PCI12XX_CBCTRL_CSC; 876 pci_conf_write(pc, tag, PCI_CBCTRL, cbctl); 877 break; 878 879 case CB_TOPIC95B: 880 sockctl = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 881 sockctl |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 882 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, sockctl); 883 slotctl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 884 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 885 sc->sc_dev.dv_xname, slotctl)); 886 slotctl |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 887 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 888 slotctl &= ~TOPIC_SLOT_CTRL_SWDETECT; 889 DPRINTF(("0x%x\n", slotctl)); 890 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slotctl); 891 break; 892 893 case CB_TOPIC97: 894 slotctl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 895 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 896 sc->sc_dev.dv_xname, slotctl)); 897 slotctl |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 898 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 899 slotctl &= ~TOPIC_SLOT_CTRL_SWDETECT; 900 slotctl |= TOPIC97_SLOT_CTRL_PCIINT; 901 slotctl &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 902 DPRINTF(("0x%x\n", slotctl)); 903 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slotctl); 904 /* make sure to assert LV card support bits */ 905 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 906 0x800 + 0x3e, 907 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 908 0x800 + 0x3e) | 0x03); 909 break; 910 } 911 912 /* Close all memory and I/O windows. */ 913 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 914 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 915 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 916 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 917 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 918 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 919 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 920 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 921 922 /* reset 16-bit pcmcia bus */ 923 bus_space_write_1(bmt, bmh, 0x800 + PCIC_INTR, 924 bus_space_read_1(bmt, bmh, 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 925 926 /* turn off power */ 927 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 928 929 /* CSC Interrupt: Card detect and power cycle interrupts on */ 930 sockmask = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 931 sockmask |= CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; 932 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, sockmask); 933 /* reset interrupt */ 934 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 935 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 936 } 937 938 939 940 941 /* 942 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 943 * struct pcmciabus_attach_args *paa) 944 * 945 * This function attaches 16-bit PCcard bus. 946 */ 947 STATIC void 948 pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 949 struct pcmciabus_attach_args *paa) 950 { 951 struct pcic_handle *ph = &sc->sc_pcmcia_h; 952 #if rbus 953 rbus_tag_t rb; 954 #endif 955 956 /* initialize pcmcia part in pccbb_softc */ 957 ph->ph_parent = (struct device *)sc; 958 ph->sock = sc->sc_function; 959 ph->flags = 0; 960 ph->shutdown = 0; 961 ph->ih_irq = sc->sc_pa.pa_intrline; 962 ph->ph_bus_t = sc->sc_base_memt; 963 ph->ph_bus_h = sc->sc_base_memh; 964 ph->ph_read = pccbb_pcmcia_read; 965 ph->ph_write = pccbb_pcmcia_write; 966 sc->sc_pct = &pccbb_pcmcia_funcs; 967 968 /* 969 * We need to do a few things here: 970 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 971 * setting the IRQ numbers to 0. 972 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 973 * routing of CSC interrupts (e.g. card removal) to PCI while in 974 * PCMCIA mode. We just leave this set all the time. 975 * 3) Enable card insertion/removal interrupts in case the chip also 976 * needs that while in PCMCIA mode. 977 * 4) Clear any pending CSC interrupt. 978 */ 979 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE); 980 if (sc->sc_chipset == CB_TI113X) { 981 Pcic_write(ph, PCIC_CSC_INTR, 0); 982 } else { 983 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 984 Pcic_read(ph, PCIC_CSC); 985 } 986 987 /* initialize pcmcia bus attachment */ 988 paa->paa_busname = "pcmcia"; 989 paa->pct = sc->sc_pct; 990 paa->pch = ph; 991 paa->iobase = 0; /* I don't use them */ 992 paa->iosize = 0; 993 #if rbus 994 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 995 paa->iobase = rb->rb_start + rb->rb_offset; 996 paa->iosize = rb->rb_end - rb->rb_start; 997 #endif 998 999 return; 1000 } 1001 1002 #if 0 1003 STATIC void 1004 pccbb_pcmcia_attach_card(struct pcic_handle *ph) 1005 { 1006 if (ph->flags & PCIC_FLAG_CARDP) { 1007 panic("pccbb_pcmcia_attach_card: already attached"); 1008 } 1009 1010 /* call the MI attach function */ 1011 pcmcia_card_attach(ph->pcmcia); 1012 1013 ph->flags |= PCIC_FLAG_CARDP; 1014 } 1015 1016 STATIC void 1017 pccbb_pcmcia_detach_card(struct pcic_handle *ph, int flags) 1018 { 1019 if (!(ph->flags & PCIC_FLAG_CARDP)) { 1020 panic("pccbb_pcmcia_detach_card: already detached"); 1021 } 1022 1023 ph->flags &= ~PCIC_FLAG_CARDP; 1024 1025 /* call the MI detach function */ 1026 pcmcia_card_detach(ph->pcmcia, flags); 1027 } 1028 #endif 1029 1030 /* 1031 * int pccbbintr(arg) 1032 * void *arg; 1033 * This routine handles the interrupt from Yenta PCI-CardBus bridge 1034 * itself. 1035 */ 1036 int 1037 pccbbintr(void *arg) 1038 { 1039 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1040 u_int32_t sockevent, sockstate; 1041 bus_space_tag_t memt = sc->sc_base_memt; 1042 bus_space_handle_t memh = sc->sc_base_memh; 1043 struct pcic_handle *ph = &sc->sc_pcmcia_h; 1044 1045 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 1046 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 1047 Pcic_read(ph, PCIC_CSC); 1048 1049 if (sockevent != 0) { 1050 aprint_debug("%s: enter sockevent %" PRIx32 "\n", __func__, 1051 sockevent); 1052 } 1053 1054 /* Sometimes a change of CSTSCHG# accompanies the first 1055 * interrupt from an Atheros WLAN. That generates a 1056 * CB_SOCKET_EVENT_CSTS event on the bridge. The event 1057 * isn't interesting to pccbb(4), so we used to ignore the 1058 * interrupt. Now, let the child devices try to handle 1059 * the interrupt, instead. The Atheros NIC produces 1060 * interrupts more reliably, now: used to be that it would 1061 * only interrupt if the driver avoided powering down the 1062 * NIC's cardslot, and then the NIC would only work after 1063 * it was reset a second time. 1064 */ 1065 if (sockevent == 0 || 1066 (sockevent & ~(CB_SOCKET_EVENT_POWER|CB_SOCKET_EVENT_CD)) != 0) { 1067 /* This intr is not for me: it may be for my child devices. */ 1068 if (sc->sc_pil_intr_enable) { 1069 return pccbbintr_function(sc); 1070 } else { 1071 return 0; 1072 } 1073 } 1074 1075 if (sockevent & CB_SOCKET_EVENT_CD) { 1076 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1077 if (0x00 != (sockstate & CB_SOCKET_STAT_CD)) { 1078 /* A card should be removed. */ 1079 if (sc->sc_flags & CBB_CARDEXIST) { 1080 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 1081 sockevent)); 1082 DPRINTF((" card removed, 0x%08x\n", sockstate)); 1083 sc->sc_flags &= ~CBB_CARDEXIST; 1084 if (sc->sc_csc->sc_status & 1085 CARDSLOT_STATUS_CARD_16) { 1086 #if 0 1087 struct pcic_handle *ph = 1088 &sc->sc_pcmcia_h; 1089 1090 pcmcia_card_deactivate(ph->pcmcia); 1091 pccbb_pcmcia_socket_disable(ph); 1092 pccbb_pcmcia_detach_card(ph, 1093 DETACH_FORCE); 1094 #endif 1095 cardslot_event_throw(sc->sc_csc, 1096 CARDSLOT_EVENT_REMOVAL_16); 1097 } else if (sc->sc_csc->sc_status & 1098 CARDSLOT_STATUS_CARD_CB) { 1099 /* Cardbus intr removed */ 1100 cardslot_event_throw(sc->sc_csc, 1101 CARDSLOT_EVENT_REMOVAL_CB); 1102 } 1103 } else if (sc->sc_flags & CBB_INSERTING) { 1104 sc->sc_flags &= ~CBB_INSERTING; 1105 callout_stop(&sc->sc_insert_ch); 1106 } 1107 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 1108 /* 1109 * The pccbbintr may called from powerdown hook when 1110 * the system resumed, to detect the card 1111 * insertion/removal during suspension. 1112 */ 1113 (sc->sc_flags & CBB_CARDEXIST) == 0) { 1114 if (sc->sc_flags & CBB_INSERTING) { 1115 callout_stop(&sc->sc_insert_ch); 1116 } 1117 callout_schedule(&sc->sc_insert_ch, hz / 5); 1118 sc->sc_flags |= CBB_INSERTING; 1119 } 1120 } 1121 1122 /* XXX sockevent == 9 does occur in the wild. handle it. */ 1123 if (sockevent & CB_SOCKET_EVENT_POWER) { 1124 DPRINTF(("Powercycling because of socket event\n")); 1125 /* XXX: Does not happen when attaching a 16-bit card */ 1126 sc->sc_pwrcycle++; 1127 wakeup(&sc->sc_pwrcycle); 1128 } 1129 1130 return (1); 1131 } 1132 1133 /* 1134 * static int pccbbintr_function(struct pccbb_softc *sc) 1135 * 1136 * This function calls each interrupt handler registered at the 1137 * bridge. The interrupt handlers are called in registered order. 1138 */ 1139 static int 1140 pccbbintr_function(struct pccbb_softc *sc) 1141 { 1142 int retval = 0, val; 1143 struct pccbb_intrhand_list *pil; 1144 int s; 1145 1146 for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1147 pil = LIST_NEXT(pil, pil_next)) { 1148 s = splraiseipl(pil->pil_icookie); 1149 val = (*pil->pil_func)(pil->pil_arg); 1150 splx(s); 1151 1152 retval = retval == 1 ? 1 : 1153 retval == 0 ? val : val != 0 ? val : retval; 1154 } 1155 1156 return retval; 1157 } 1158 1159 static void 1160 pci113x_insert(void *arg) 1161 { 1162 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1163 u_int32_t sockevent, sockstate; 1164 1165 if (!(sc->sc_flags & CBB_INSERTING)) { 1166 /* We add a card only under inserting state. */ 1167 return; 1168 } 1169 sc->sc_flags &= ~CBB_INSERTING; 1170 1171 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1172 CB_SOCKET_EVENT); 1173 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1174 CB_SOCKET_STAT); 1175 1176 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1177 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1178 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1179 sc->sc_flags |= CBB_CARDEXIST; 1180 /* call pccard interrupt handler here */ 1181 if (sockstate & CB_SOCKET_STAT_16BIT) { 1182 /* 16-bit card found */ 1183 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1184 cardslot_event_throw(sc->sc_csc, 1185 CARDSLOT_EVENT_INSERTION_16); 1186 } else if (sockstate & CB_SOCKET_STAT_CB) { 1187 /* cardbus card found */ 1188 /* cardbus_attach_card(sc->sc_csc); */ 1189 cardslot_event_throw(sc->sc_csc, 1190 CARDSLOT_EVENT_INSERTION_CB); 1191 } else { 1192 /* who are you? */ 1193 } 1194 } else { 1195 callout_schedule(&sc->sc_insert_ch, hz / 10); 1196 } 1197 } 1198 1199 #define PCCBB_PCMCIA_OFFSET 0x800 1200 static u_int8_t 1201 pccbb_pcmcia_read(struct pcic_handle *ph, int reg) 1202 { 1203 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1204 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1205 1206 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1207 PCCBB_PCMCIA_OFFSET + reg); 1208 } 1209 1210 static void 1211 pccbb_pcmcia_write(struct pcic_handle *ph, int reg, u_int8_t val) 1212 { 1213 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1214 val); 1215 1216 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1217 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1218 } 1219 1220 /* 1221 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1222 */ 1223 STATIC int 1224 pccbb_ctrl(cardbus_chipset_tag_t ct, int command) 1225 { 1226 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1227 1228 switch (command) { 1229 case CARDBUS_CD: 1230 if (2 == pccbb_detect_card(sc)) { 1231 int retval = 0; 1232 int status = cb_detect_voltage(sc); 1233 if (PCCARD_VCC_5V & status) { 1234 retval |= CARDBUS_5V_CARD; 1235 } 1236 if (PCCARD_VCC_3V & status) { 1237 retval |= CARDBUS_3V_CARD; 1238 } 1239 if (PCCARD_VCC_XV & status) { 1240 retval |= CARDBUS_XV_CARD; 1241 } 1242 if (PCCARD_VCC_YV & status) { 1243 retval |= CARDBUS_YV_CARD; 1244 } 1245 return retval; 1246 } else { 1247 return 0; 1248 } 1249 case CARDBUS_RESET: 1250 return cb_reset(sc); 1251 case CARDBUS_IO_ENABLE: /* fallthrough */ 1252 case CARDBUS_IO_DISABLE: /* fallthrough */ 1253 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1254 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1255 case CARDBUS_BM_ENABLE: /* fallthrough */ 1256 case CARDBUS_BM_DISABLE: /* fallthrough */ 1257 /* XXX: I think we don't need to call this function below. */ 1258 return pccbb_cardenable(sc, command); 1259 } 1260 1261 return 0; 1262 } 1263 1264 /* 1265 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1266 * This function returns true when it succeeds and returns false when 1267 * it fails. 1268 */ 1269 STATIC int 1270 pccbb_power(cardbus_chipset_tag_t ct, int command) 1271 { 1272 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1273 u_int32_t status, osock_ctrl, sock_ctrl, reg_ctrl; 1274 bus_space_tag_t memt = sc->sc_base_memt; 1275 bus_space_handle_t memh = sc->sc_base_memh; 1276 int on = 0, pwrcycle, s, times; 1277 struct timeval before, after, diff; 1278 1279 DPRINTF(("pccbb_power: %s and %s [0x%x]\n", 1280 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1281 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1282 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1283 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1284 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1285 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1286 "UNKNOWN", 1287 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1288 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1289 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1290 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1291 "UNKNOWN", command)); 1292 1293 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1294 osock_ctrl = sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1295 1296 switch (command & CARDBUS_VCCMASK) { 1297 case CARDBUS_VCC_UC: 1298 break; 1299 case CARDBUS_VCC_5V: 1300 on++; 1301 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1302 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1303 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1304 } else { 1305 printf("%s: BAD voltage request: no 5 V card\n", 1306 sc->sc_dev.dv_xname); 1307 return 0; 1308 } 1309 break; 1310 case CARDBUS_VCC_3V: 1311 on++; 1312 if (CB_SOCKET_STAT_3VCARD & status) { 1313 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1314 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1315 } else { 1316 printf("%s: BAD voltage request: no 3.3 V card\n", 1317 sc->sc_dev.dv_xname); 1318 return 0; 1319 } 1320 break; 1321 case CARDBUS_VCC_0V: 1322 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1323 break; 1324 default: 1325 return 0; /* power NEVER changed */ 1326 } 1327 1328 switch (command & CARDBUS_VPPMASK) { 1329 case CARDBUS_VPP_UC: 1330 break; 1331 case CARDBUS_VPP_0V: 1332 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1333 break; 1334 case CARDBUS_VPP_VCC: 1335 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1336 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1337 break; 1338 case CARDBUS_VPP_12V: 1339 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1340 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1341 break; 1342 } 1343 1344 pwrcycle = sc->sc_pwrcycle; 1345 aprint_debug("%s: osock_ctrl %#" PRIx32 " sock_ctrl %#" PRIx32 "\n", 1346 device_xname(&sc->sc_dev), osock_ctrl, sock_ctrl); 1347 1348 microtime(&before); 1349 s = splbio(); 1350 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1351 1352 /* 1353 * Wait as long as 200ms for a power-cycle interrupt. If 1354 * interrupts are enabled, but the socket has already 1355 * changed to the desired status, keep waiting for the 1356 * interrupt. "Consuming" the interrupt in this way keeps 1357 * the interrupt from prematurely waking some subsequent 1358 * pccbb_power call. 1359 * 1360 * XXX Not every bridge interrupts on the ->OFF transition. 1361 * XXX That's ok, we will time-out after 200ms. 1362 * 1363 * XXX The power cycle event will never happen when attaching 1364 * XXX a 16-bit card. That's ok, we will time-out after 1365 * XXX 200ms. 1366 */ 1367 for (times = 5; --times >= 0; ) { 1368 if (cold) 1369 DELAY(40 * 1000); 1370 else { 1371 (void)tsleep(&sc->sc_pwrcycle, PWAIT, "pccpwr", 1372 hz / 25); 1373 if (pwrcycle == sc->sc_pwrcycle) 1374 continue; 1375 } 1376 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1377 if ((status & CB_SOCKET_STAT_PWRCYCLE) != 0 && on) 1378 break; 1379 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0 && !on) 1380 break; 1381 } 1382 splx(s); 1383 microtime(&after); 1384 timersub(&after, &before, &diff); 1385 aprint_debug("%s: wait took%s %ld.%06lds\n", sc->sc_dev.dv_xname, 1386 (on && times < 0) ? " too long" : "", diff.tv_sec, diff.tv_usec); 1387 1388 /* 1389 * Ok, wait a bit longer for things to settle. 1390 */ 1391 if (on && sc->sc_chipset == CB_TOPIC95B) 1392 delay_ms(100, sc); 1393 1394 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1395 1396 if (on && sc->sc_chipset != CB_TOPIC95B) { 1397 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0) 1398 printf("%s: power on failed?\n", sc->sc_dev.dv_xname); 1399 } 1400 1401 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1402 printf("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1403 sc->sc_dev.dv_xname, sock_ctrl, status); 1404 printf("%s: disabling socket\n", sc->sc_dev.dv_xname); 1405 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1406 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1407 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1408 status &= ~CB_SOCKET_STAT_BADVCC; 1409 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, status); 1410 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1411 CB_SOCKET_STAT)); 1412 return 0; 1413 } 1414 1415 if (sc->sc_chipset == CB_TOPIC97) { 1416 reg_ctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL); 1417 reg_ctrl &= ~TOPIC97_REG_CTRL_TESTMODE; 1418 if ((command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V) 1419 reg_ctrl &= ~TOPIC97_REG_CTRL_CLKRUN_ENA; 1420 else 1421 reg_ctrl |= TOPIC97_REG_CTRL_CLKRUN_ENA; 1422 pci_conf_write(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL, reg_ctrl); 1423 } 1424 1425 return 1; /* power changed correctly */ 1426 } 1427 1428 #if defined CB_PCMCIA_POLL 1429 struct cb_poll_str { 1430 void *arg; 1431 int (*func)(void *); 1432 int level; 1433 pccard_chipset_tag_t ct; 1434 int count; 1435 struct callout poll_ch; 1436 }; 1437 1438 static struct cb_poll_str cb_poll[10]; 1439 static int cb_poll_n = 0; 1440 1441 static void cb_pcmcia_poll(void *arg); 1442 1443 static void 1444 cb_pcmcia_poll(void *arg) 1445 { 1446 struct cb_poll_str *poll = arg; 1447 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1448 struct pccbb_softc *sc = psc->cpc_parent; 1449 int s; 1450 u_int32_t spsr; /* socket present-state reg */ 1451 1452 callout_reset(&poll->poll_ch, hz / 10, cb_pcmcia_poll, poll); 1453 switch (poll->level) { 1454 case IPL_NET: 1455 s = splnet(); 1456 break; 1457 case IPL_BIO: 1458 s = splbio(); 1459 break; 1460 case IPL_TTY: /* fallthrough */ 1461 default: 1462 s = spltty(); 1463 break; 1464 } 1465 1466 spsr = 1467 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1468 CB_SOCKET_STAT); 1469 1470 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1471 if (!(spsr & 0x40)) { /* CINT low */ 1472 #else 1473 if (1) { 1474 #endif 1475 if ((*poll->func) (poll->arg) == 1) { 1476 ++poll->count; 1477 printf("intr: reported from poller, 0x%x\n", spsr); 1478 #if defined LEVEL2 1479 } else { 1480 printf("intr: miss! 0x%x\n", spsr); 1481 #endif 1482 } 1483 } 1484 splx(s); 1485 } 1486 #endif /* defined CB_PCMCIA_POLL */ 1487 1488 /* 1489 * static int pccbb_detect_card(struct pccbb_softc *sc) 1490 * return value: 0 if no card exists. 1491 * 1 if 16-bit card exists. 1492 * 2 if cardbus card exists. 1493 */ 1494 static int 1495 pccbb_detect_card(struct pccbb_softc *sc) 1496 { 1497 bus_space_handle_t base_memh = sc->sc_base_memh; 1498 bus_space_tag_t base_memt = sc->sc_base_memt; 1499 u_int32_t sockstat = 1500 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1501 int retval = 0; 1502 1503 /* CD1 and CD2 asserted */ 1504 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1505 /* card must be present */ 1506 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1507 /* NOTACARD DEASSERTED */ 1508 if (CB_SOCKET_STAT_CB & sockstat) { 1509 /* CardBus mode */ 1510 retval = 2; 1511 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1512 /* 16-bit mode */ 1513 retval = 1; 1514 } 1515 } 1516 } 1517 return retval; 1518 } 1519 1520 /* 1521 * STATIC int cb_reset(struct pccbb_softc *sc) 1522 * This function resets CardBus card. 1523 */ 1524 STATIC int 1525 cb_reset(struct pccbb_softc *sc) 1526 { 1527 /* 1528 * Reset Assert at least 20 ms 1529 * Some machines request longer duration. 1530 */ 1531 int reset_duration = 1532 (sc->sc_chipset == CB_RX5C47X ? 400 : 50); 1533 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1534 aprint_debug("%s: enter bcr %" PRIx32 "\n", __func__, bcr); 1535 1536 /* Reset bit Assert (bit 6 at 0x3E) */ 1537 bcr |= PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT; 1538 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr); 1539 aprint_debug("%s: wrote bcr %" PRIx32 "\n", __func__, bcr); 1540 delay_ms(reset_duration, sc); 1541 1542 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1543 /* Reset bit Deassert (bit 6 at 0x3E) */ 1544 bcr &= ~(PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT); 1545 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, 1546 bcr); 1547 aprint_debug("%s: wrote bcr %" PRIx32 "\n", __func__, bcr); 1548 delay_ms(reset_duration, sc); 1549 aprint_debug("%s: end of delay\n", __func__); 1550 } 1551 /* No card found on the slot. Keep Reset. */ 1552 return 1; 1553 } 1554 1555 /* 1556 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1557 * This function detect card Voltage. 1558 */ 1559 STATIC int 1560 cb_detect_voltage(struct pccbb_softc *sc) 1561 { 1562 u_int32_t psr; /* socket present-state reg */ 1563 bus_space_tag_t iot = sc->sc_base_memt; 1564 bus_space_handle_t ioh = sc->sc_base_memh; 1565 int vol = PCCARD_VCC_UKN; /* set 0 */ 1566 1567 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1568 1569 if (0x400u & psr) { 1570 vol |= PCCARD_VCC_5V; 1571 } 1572 if (0x800u & psr) { 1573 vol |= PCCARD_VCC_3V; 1574 } 1575 1576 return vol; 1577 } 1578 1579 STATIC int 1580 cbbprint(void *aux, const char *pcic) 1581 { 1582 #if 0 1583 struct cbslot_attach_args *cba = aux; 1584 1585 if (cba->cba_slot >= 0) { 1586 aprint_normal(" slot %d", cba->cba_slot); 1587 } 1588 #endif 1589 return UNCONF; 1590 } 1591 1592 /* 1593 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1594 * This function enables and disables the card 1595 */ 1596 STATIC int 1597 pccbb_cardenable(struct pccbb_softc *sc, int function) 1598 { 1599 u_int32_t command = 1600 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1601 1602 DPRINTF(("pccbb_cardenable:")); 1603 switch (function) { 1604 case CARDBUS_IO_ENABLE: 1605 command |= PCI_COMMAND_IO_ENABLE; 1606 break; 1607 case CARDBUS_IO_DISABLE: 1608 command &= ~PCI_COMMAND_IO_ENABLE; 1609 break; 1610 case CARDBUS_MEM_ENABLE: 1611 command |= PCI_COMMAND_MEM_ENABLE; 1612 break; 1613 case CARDBUS_MEM_DISABLE: 1614 command &= ~PCI_COMMAND_MEM_ENABLE; 1615 break; 1616 case CARDBUS_BM_ENABLE: 1617 command |= PCI_COMMAND_MASTER_ENABLE; 1618 break; 1619 case CARDBUS_BM_DISABLE: 1620 command &= ~PCI_COMMAND_MASTER_ENABLE; 1621 break; 1622 default: 1623 return 0; 1624 } 1625 1626 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1627 DPRINTF((" command reg 0x%x\n", command)); 1628 return 1; 1629 } 1630 1631 #if !rbus 1632 static int 1633 pccbb_io_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 1634 { 1635 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1636 int basereg; 1637 int limitreg; 1638 1639 if ((win < 0) || (win > 2)) { 1640 #if defined DIAGNOSTIC 1641 printf("cardbus_io_open: window out of range %d\n", win); 1642 #endif 1643 return 0; 1644 } 1645 1646 basereg = win * 8 + 0x2c; 1647 limitreg = win * 8 + 0x30; 1648 1649 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1650 start, basereg, end, limitreg)); 1651 1652 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1653 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1654 return 1; 1655 } 1656 1657 /* 1658 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1659 */ 1660 static int 1661 pccbb_io_close(cardbus_chipset_tag_t ct, int win) 1662 { 1663 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1664 int basereg; 1665 int limitreg; 1666 1667 if ((win < 0) || (win > 2)) { 1668 #if defined DIAGNOSTIC 1669 printf("cardbus_io_close: window out of range %d\n", win); 1670 #endif 1671 return 0; 1672 } 1673 1674 basereg = win * 8 + 0x2c; 1675 limitreg = win * 8 + 0x30; 1676 1677 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1678 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1679 return 1; 1680 } 1681 1682 static int 1683 pccbb_mem_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 1684 { 1685 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1686 int basereg; 1687 int limitreg; 1688 1689 if ((win < 0) || (win > 2)) { 1690 #if defined DIAGNOSTIC 1691 printf("cardbus_mem_open: window out of range %d\n", win); 1692 #endif 1693 return 0; 1694 } 1695 1696 basereg = win * 8 + 0x1c; 1697 limitreg = win * 8 + 0x20; 1698 1699 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1700 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1701 return 1; 1702 } 1703 1704 static int 1705 pccbb_mem_close(cardbus_chipset_tag_t ct, int win) 1706 { 1707 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1708 int basereg; 1709 int limitreg; 1710 1711 if ((win < 0) || (win > 2)) { 1712 #if defined DIAGNOSTIC 1713 printf("cardbus_mem_close: window out of range %d\n", win); 1714 #endif 1715 return 0; 1716 } 1717 1718 basereg = win * 8 + 0x1c; 1719 limitreg = win * 8 + 0x20; 1720 1721 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1722 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1723 return 1; 1724 } 1725 #endif 1726 1727 /* 1728 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1729 * int irq, 1730 * int level, 1731 * int (* func)(void *), 1732 * void *arg) 1733 * 1734 * This function registers an interrupt handler at the bridge, in 1735 * order not to call the interrupt handlers of child devices when 1736 * a card-deletion interrupt occurs. 1737 * 1738 * The arguments irq and level are not used. 1739 */ 1740 static void * 1741 pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, int irq, int level, 1742 int (*func)(void *), void *arg) 1743 { 1744 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1745 1746 return pccbb_intr_establish(sc, irq, level, func, arg); 1747 } 1748 1749 1750 /* 1751 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1752 * void *ih) 1753 * 1754 * This function removes an interrupt handler pointed by ih. 1755 */ 1756 static void 1757 pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih) 1758 { 1759 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1760 1761 pccbb_intr_disestablish(sc, ih); 1762 } 1763 1764 1765 void 1766 pccbb_intr_route(struct pccbb_softc *sc) 1767 { 1768 pcireg_t bcr, cbctrl; 1769 1770 /* initialize bridge intr routing */ 1771 bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1772 bcr &= ~CB_BCR_INTR_IREQ_ENABLE; 1773 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr); 1774 1775 switch (sc->sc_chipset) { 1776 case CB_TI113X: 1777 cbctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1778 /* functional intr enabled */ 1779 cbctrl |= PCI113X_CBCTRL_PCI_INTR; 1780 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, cbctrl); 1781 break; 1782 default: 1783 break; 1784 } 1785 } 1786 1787 /* 1788 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1789 * int irq, 1790 * int level, 1791 * int (* func)(void *), 1792 * void *arg) 1793 * 1794 * This function registers an interrupt handler at the bridge, in 1795 * order not to call the interrupt handlers of child devices when 1796 * a card-deletion interrupt occurs. 1797 * 1798 * The arguments irq is not used because pccbb selects intr vector. 1799 */ 1800 static void * 1801 pccbb_intr_establish(struct pccbb_softc *sc, int irq, int level, 1802 int (*func)(void *), void *arg) 1803 { 1804 struct pccbb_intrhand_list *pil, *newpil; 1805 1806 DPRINTF(("pccbb_intr_establish start. %p\n", LIST_FIRST(&sc->sc_pil))); 1807 1808 if (LIST_EMPTY(&sc->sc_pil)) { 1809 pccbb_intr_route(sc); 1810 } 1811 1812 /* 1813 * Allocate a room for interrupt handler structure. 1814 */ 1815 if (NULL == (newpil = 1816 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1817 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1818 return NULL; 1819 } 1820 1821 newpil->pil_func = func; 1822 newpil->pil_arg = arg; 1823 newpil->pil_icookie = makeiplcookie(level); 1824 1825 if (LIST_EMPTY(&sc->sc_pil)) { 1826 LIST_INSERT_HEAD(&sc->sc_pil, newpil, pil_next); 1827 } else { 1828 for (pil = LIST_FIRST(&sc->sc_pil); 1829 LIST_NEXT(pil, pil_next) != NULL; 1830 pil = LIST_NEXT(pil, pil_next)); 1831 LIST_INSERT_AFTER(pil, newpil, pil_next); 1832 } 1833 1834 DPRINTF(("pccbb_intr_establish add pil. %p\n", 1835 LIST_FIRST(&sc->sc_pil))); 1836 1837 return newpil; 1838 } 1839 1840 /* 1841 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1842 * void *ih) 1843 * 1844 * This function removes an interrupt handler pointed by ih. ih 1845 * should be the value returned by cardbus_intr_establish() or 1846 * NULL. 1847 * 1848 * When ih is NULL, this function will do nothing. 1849 */ 1850 static void 1851 pccbb_intr_disestablish(struct pccbb_softc *sc, void *ih) 1852 { 1853 struct pccbb_intrhand_list *pil; 1854 pcireg_t reg; 1855 1856 DPRINTF(("pccbb_intr_disestablish start. %p\n", 1857 LIST_FIRST(&sc->sc_pil))); 1858 1859 if (ih == NULL) { 1860 /* intr handler is not set */ 1861 DPRINTF(("pccbb_intr_disestablish: no ih\n")); 1862 return; 1863 } 1864 1865 #ifdef DIAGNOSTIC 1866 for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1867 pil = LIST_NEXT(pil, pil_next)) { 1868 DPRINTF(("pccbb_intr_disestablish: pil %p\n", pil)); 1869 if (pil == ih) { 1870 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1871 break; 1872 } 1873 } 1874 if (pil == NULL) { 1875 panic("pccbb_intr_disestablish: %s cannot find pil %p", 1876 sc->sc_dev.dv_xname, ih); 1877 } 1878 #endif 1879 1880 pil = (struct pccbb_intrhand_list *)ih; 1881 LIST_REMOVE(pil, pil_next); 1882 free(pil, M_DEVBUF); 1883 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1884 1885 if (LIST_EMPTY(&sc->sc_pil)) { 1886 /* No interrupt handlers */ 1887 1888 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1889 1890 /* stop routing PCI intr */ 1891 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1892 reg |= CB_BCR_INTR_IREQ_ENABLE; 1893 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, reg); 1894 1895 switch (sc->sc_chipset) { 1896 case CB_TI113X: 1897 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1898 /* functional intr disabled */ 1899 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1900 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1901 break; 1902 default: 1903 break; 1904 } 1905 } 1906 } 1907 1908 #if defined SHOW_REGS 1909 static void 1910 cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, bus_space_tag_t memt, 1911 bus_space_handle_t memh) 1912 { 1913 int i; 1914 printf("PCI config regs:"); 1915 for (i = 0; i < 0x50; i += 4) { 1916 if (i % 16 == 0) 1917 printf("\n 0x%02x:", i); 1918 printf(" %08x", pci_conf_read(pc, tag, i)); 1919 } 1920 for (i = 0x80; i < 0xb0; i += 4) { 1921 if (i % 16 == 0) 1922 printf("\n 0x%02x:", i); 1923 printf(" %08x", pci_conf_read(pc, tag, i)); 1924 } 1925 1926 if (memh == 0) { 1927 printf("\n"); 1928 return; 1929 } 1930 1931 printf("\nsocket regs:"); 1932 for (i = 0; i <= 0x10; i += 0x04) 1933 printf(" %08x", bus_space_read_4(memt, memh, i)); 1934 printf("\nExCA regs:"); 1935 for (i = 0; i < 0x08; ++i) 1936 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1937 printf("\n"); 1938 return; 1939 } 1940 #endif 1941 1942 /* 1943 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1944 * int busno, int function) 1945 * This is the function to make a tag to access config space of 1946 * a CardBus Card. It works same as pci_conf_read. 1947 */ 1948 static cardbustag_t 1949 pccbb_make_tag(cardbus_chipset_tag_t cc, int busno, int function) 1950 { 1951 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1952 1953 return pci_make_tag(sc->sc_pc, busno, 0, function); 1954 } 1955 1956 static void 1957 pccbb_free_tag(cardbus_chipset_tag_t cc, cardbustag_t tag) 1958 { 1959 } 1960 1961 /* 1962 * pccbb_conf_read 1963 * 1964 * This is the function to read the config space of a CardBus card. 1965 * It works the same as pci_conf_read(9). 1966 */ 1967 static cardbusreg_t 1968 pccbb_conf_read(cardbus_chipset_tag_t cc, cardbustag_t tag, int offset) 1969 { 1970 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1971 1972 return pci_conf_read(sc->sc_pc, tag, offset); 1973 } 1974 1975 /* 1976 * pccbb_conf_write 1977 * 1978 * This is the function to write the config space of a CardBus 1979 * card. It works the same as pci_conf_write(9). 1980 */ 1981 static void 1982 pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, int reg, 1983 cardbusreg_t val) 1984 { 1985 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1986 1987 pci_conf_write(sc->sc_pc, tag, reg, val); 1988 } 1989 1990 #if 0 1991 STATIC int 1992 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1993 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 1994 int speed, int flags, 1995 bus_space_handle_t * iohp) 1996 #endif 1997 /* 1998 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1999 * bus_addr_t start, bus_size_t size, 2000 * bus_size_t align, 2001 * struct pcmcia_io_handle *pcihp 2002 * 2003 * This function only allocates I/O region for pccard. This function 2004 * never maps the allocated region to pccard I/O area. 2005 * 2006 * XXX: The interface of this function is not very good, I believe. 2007 */ 2008 STATIC int 2009 pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, 2010 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 2011 { 2012 struct pcic_handle *ph = (struct pcic_handle *)pch; 2013 bus_addr_t ioaddr; 2014 int flags = 0; 2015 bus_space_tag_t iot; 2016 bus_space_handle_t ioh; 2017 bus_addr_t mask; 2018 #if rbus 2019 rbus_tag_t rb; 2020 #endif 2021 if (align == 0) { 2022 align = size; /* XXX: funny??? */ 2023 } 2024 2025 if (start != 0) { 2026 /* XXX: assume all card decode lower 10 bits by its hardware */ 2027 mask = 0x3ff; 2028 /* enforce to use only masked address */ 2029 start &= mask; 2030 } else { 2031 /* 2032 * calculate mask: 2033 * 1. get the most significant bit of size (call it msb). 2034 * 2. compare msb with the value of size. 2035 * 3. if size is larger, shift msb left once. 2036 * 4. obtain mask value to decrement msb. 2037 */ 2038 bus_size_t size_tmp = size; 2039 int shifts = 0; 2040 2041 mask = 1; 2042 while (size_tmp) { 2043 ++shifts; 2044 size_tmp >>= 1; 2045 } 2046 mask = (1 << shifts); 2047 if (mask < size) { 2048 mask <<= 1; 2049 } 2050 --mask; 2051 } 2052 2053 /* 2054 * Allocate some arbitrary I/O space. 2055 */ 2056 2057 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 2058 2059 #if rbus 2060 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 2061 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 2062 return 1; 2063 } 2064 DPRINTF(("pccbb_pcmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2065 (u_long) ioaddr, (u_long) size)); 2066 #else 2067 if (start) { 2068 ioaddr = start; 2069 if (bus_space_map(iot, start, size, 0, &ioh)) { 2070 return 1; 2071 } 2072 DPRINTF(("pccbb_pcmcia_io_alloc map port 0x%lx+0x%lx\n", 2073 (u_long) ioaddr, (u_long) size)); 2074 } else { 2075 flags |= PCMCIA_IO_ALLOCATED; 2076 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 2077 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 2078 size, align, 0, 0, &ioaddr, &ioh)) { 2079 /* No room be able to be get. */ 2080 return 1; 2081 } 2082 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2083 (u_long) ioaddr, (u_long) size)); 2084 } 2085 #endif 2086 2087 pcihp->iot = iot; 2088 pcihp->ioh = ioh; 2089 pcihp->addr = ioaddr; 2090 pcihp->size = size; 2091 pcihp->flags = flags; 2092 2093 return 0; 2094 } 2095 2096 /* 2097 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2098 * struct pcmcia_io_handle *pcihp) 2099 * 2100 * This function only frees I/O region for pccard. 2101 * 2102 * XXX: The interface of this function is not very good, I believe. 2103 */ 2104 void 2105 pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2106 struct pcmcia_io_handle *pcihp) 2107 { 2108 #if !rbus 2109 bus_space_tag_t iot = pcihp->iot; 2110 #endif 2111 bus_space_handle_t ioh = pcihp->ioh; 2112 bus_size_t size = pcihp->size; 2113 2114 #if rbus 2115 struct pccbb_softc *sc = 2116 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 2117 rbus_tag_t rb = sc->sc_rbus_iot; 2118 2119 rbus_space_free(rb, ioh, size, NULL); 2120 #else 2121 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 2122 bus_space_free(iot, ioh, size); 2123 else 2124 bus_space_unmap(iot, ioh, size); 2125 #endif 2126 } 2127 2128 /* 2129 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 2130 * bus_addr_t offset, bus_size_t size, 2131 * struct pcmcia_io_handle *pcihp, 2132 * int *windowp) 2133 * 2134 * This function maps the allocated I/O region to pccard. This function 2135 * never allocates any I/O region for pccard I/O area. I don't 2136 * understand why the original authors of pcmciabus separated alloc and 2137 * map. I believe the two must be unite. 2138 * 2139 * XXX: no wait timing control? 2140 */ 2141 int 2142 pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, bus_addr_t offset, 2143 bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp) 2144 { 2145 struct pcic_handle *ph = (struct pcic_handle *)pch; 2146 bus_addr_t ioaddr = pcihp->addr + offset; 2147 int i, win; 2148 #if defined CBB_DEBUG 2149 static const char *width_names[] = { "dynamic", "io8", "io16" }; 2150 #endif 2151 2152 /* Sanity check I/O handle. */ 2153 2154 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 2155 panic("pccbb_pcmcia_io_map iot is bogus"); 2156 } 2157 2158 /* XXX Sanity check offset/size. */ 2159 2160 win = -1; 2161 for (i = 0; i < PCIC_IO_WINS; i++) { 2162 if ((ph->ioalloc & (1 << i)) == 0) { 2163 win = i; 2164 ph->ioalloc |= (1 << i); 2165 break; 2166 } 2167 } 2168 2169 if (win == -1) { 2170 return 1; 2171 } 2172 2173 *windowp = win; 2174 2175 /* XXX this is pretty gross */ 2176 2177 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2178 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2179 2180 /* XXX wtf is this doing here? */ 2181 2182 #if 0 2183 printf(" port 0x%lx", (u_long) ioaddr); 2184 if (size > 1) { 2185 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2186 } 2187 #endif 2188 2189 ph->io[win].addr = ioaddr; 2190 ph->io[win].size = size; 2191 ph->io[win].width = width; 2192 2193 /* actual dirty register-value changing in the function below. */ 2194 pccbb_pcmcia_do_io_map(ph, win); 2195 2196 return 0; 2197 } 2198 2199 /* 2200 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2201 * 2202 * This function changes register-value to map I/O region for pccard. 2203 */ 2204 static void 2205 pccbb_pcmcia_do_io_map(struct pcic_handle *ph, int win) 2206 { 2207 static u_int8_t pcic_iowidth[3] = { 2208 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2209 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2210 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2211 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2212 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2213 }; 2214 2215 #define PCIC_SIA_START_LOW 0 2216 #define PCIC_SIA_START_HIGH 1 2217 #define PCIC_SIA_STOP_LOW 2 2218 #define PCIC_SIA_STOP_HIGH 3 2219 2220 int regbase_win = 0x8 + win * 0x04; 2221 u_int8_t ioctl, enable; 2222 2223 DPRINTF(("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx " 2224 "width %d\n", win, (unsigned long)ph->io[win].addr, 2225 (unsigned long)ph->io[win].size, ph->io[win].width * 8)); 2226 2227 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2228 ph->io[win].addr & 0xff); 2229 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2230 (ph->io[win].addr >> 8) & 0xff); 2231 2232 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2233 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2234 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2235 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2236 2237 ioctl = Pcic_read(ph, PCIC_IOCTL); 2238 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2239 switch (win) { 2240 case 0: 2241 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2242 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2243 PCIC_IOCTL_IO0_DATASIZE_MASK); 2244 ioctl |= pcic_iowidth[ph->io[win].width]; 2245 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2246 break; 2247 case 1: 2248 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2249 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2250 PCIC_IOCTL_IO1_DATASIZE_MASK); 2251 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2252 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2253 break; 2254 } 2255 Pcic_write(ph, PCIC_IOCTL, ioctl); 2256 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2257 #if defined(CBB_DEBUG) 2258 { 2259 u_int8_t start_low = 2260 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2261 u_int8_t start_high = 2262 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2263 u_int8_t stop_low = 2264 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2265 u_int8_t stop_high = 2266 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2267 printf("pccbb_pcmcia_do_io_map start %02x %02x, " 2268 "stop %02x %02x, ioctl %02x enable %02x\n", 2269 start_low, start_high, stop_low, stop_high, ioctl, enable); 2270 } 2271 #endif 2272 } 2273 2274 /* 2275 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2276 * 2277 * This function unmaps I/O region. No return value. 2278 */ 2279 STATIC void 2280 pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t pch, int win) 2281 { 2282 struct pcic_handle *ph = (struct pcic_handle *)pch; 2283 int reg; 2284 2285 if (win >= PCIC_IO_WINS || win < 0) { 2286 panic("pccbb_pcmcia_io_unmap: window out of range"); 2287 } 2288 2289 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2290 switch (win) { 2291 case 0: 2292 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2293 break; 2294 case 1: 2295 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2296 break; 2297 } 2298 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2299 2300 ph->ioalloc &= ~(1 << win); 2301 } 2302 2303 static int 2304 pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 2305 { 2306 u_int8_t stat; 2307 int i; 2308 2309 /* wait an initial 10ms for quick cards */ 2310 stat = Pcic_read(ph, PCIC_IF_STATUS); 2311 if (stat & PCIC_IF_STATUS_READY) 2312 return (0); 2313 pccbb_pcmcia_delay(ph, 10, "pccwr0"); 2314 for (i = 0; i < 50; i++) { 2315 stat = Pcic_read(ph, PCIC_IF_STATUS); 2316 if (stat & PCIC_IF_STATUS_READY) 2317 return (0); 2318 if ((stat & PCIC_IF_STATUS_CARDDETECT_MASK) != 2319 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2320 return (ENXIO); 2321 /* wait .1s (100ms) each iteration now */ 2322 pccbb_pcmcia_delay(ph, 100, "pccwr1"); 2323 } 2324 2325 printf("pccbb_pcmcia_wait_ready: ready never happened, status=%02x\n", stat); 2326 return (EWOULDBLOCK); 2327 } 2328 2329 /* 2330 * Perform long (msec order) delay. timo is in milliseconds. 2331 */ 2332 static void 2333 pccbb_pcmcia_delay(struct pcic_handle *ph, int timo, const char *wmesg) 2334 { 2335 #ifdef DIAGNOSTIC 2336 if (timo <= 0) 2337 panic("pccbb_pcmcia_delay: called with timeout %d", timo); 2338 if (!curlwp) 2339 panic("pccbb_pcmcia_delay: called in interrupt context"); 2340 #if 0 2341 if (!ph->event_thread) 2342 panic("pccbb_pcmcia_delay: no event thread"); 2343 #endif 2344 #endif 2345 DPRINTF(("pccbb_pcmcia_delay: \"%s\" %p, sleep %d ms\n", 2346 wmesg, ph->event_thread, timo)); 2347 tsleep(pccbb_pcmcia_delay, PWAIT, wmesg, roundup(timo * hz, 1000) / 1000); 2348 } 2349 2350 /* 2351 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2352 * 2353 * This function enables the card. All information is stored in 2354 * the first argument, pcmcia_chipset_handle_t. 2355 */ 2356 STATIC void 2357 pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2358 { 2359 struct pcic_handle *ph = (struct pcic_handle *)pch; 2360 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2361 pcireg_t spsr; 2362 int voltage; 2363 int win; 2364 u_int8_t power, intr; 2365 #ifdef DIAGNOSTIC 2366 int reg; 2367 #endif 2368 2369 /* this bit is mostly stolen from pcic_attach_card */ 2370 2371 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2372 2373 /* get card Vcc info */ 2374 spsr = 2375 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2376 CB_SOCKET_STAT); 2377 if (spsr & CB_SOCKET_STAT_5VCARD) { 2378 DPRINTF(("5V card\n")); 2379 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2380 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2381 DPRINTF(("3V card\n")); 2382 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2383 } else { 2384 DPRINTF(("?V card, 0x%x\n", spsr)); /* XXX */ 2385 return; 2386 } 2387 2388 /* disable interrupts; assert RESET */ 2389 intr = Pcic_read(ph, PCIC_INTR); 2390 intr &= PCIC_INTR_ENABLE; 2391 Pcic_write(ph, PCIC_INTR, intr); 2392 2393 /* zero out the address windows */ 2394 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2395 2396 /* power down the socket to reset it, clear the card reset pin */ 2397 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2398 2399 /* power off; assert output enable bit */ 2400 power = PCIC_PWRCTL_OE; 2401 Pcic_write(ph, PCIC_PWRCTL, power); 2402 2403 /* power up the socket */ 2404 if (pccbb_power(sc, voltage) == 0) 2405 return; 2406 2407 /* 2408 * Table 4-18 and figure 4-6 of the PC Card specifiction say: 2409 * Vcc Rising Time (Tpr) = 100ms (handled in pccbb_power() above) 2410 * RESET Width (Th (Hi-z RESET)) = 1ms 2411 * RESET Width (Tw (RESET)) = 10us 2412 * 2413 * some machines require some more time to be settled 2414 * for example old toshiba topic bridges! 2415 * (100ms is added here). 2416 */ 2417 pccbb_pcmcia_delay(ph, 200 + 1, "pccen1"); 2418 2419 /* negate RESET */ 2420 intr |= PCIC_INTR_RESET; 2421 Pcic_write(ph, PCIC_INTR, intr); 2422 2423 /* 2424 * RESET Setup Time (Tsu (RESET)) = 20ms 2425 */ 2426 pccbb_pcmcia_delay(ph, 20, "pccen2"); 2427 2428 #ifdef DIAGNOSTIC 2429 reg = Pcic_read(ph, PCIC_IF_STATUS); 2430 if ((reg & PCIC_IF_STATUS_POWERACTIVE) == 0) 2431 printf("pccbb_pcmcia_socket_enable: no power, status=%x\n", reg); 2432 #endif 2433 2434 /* wait for the chip to finish initializing */ 2435 if (pccbb_pcmcia_wait_ready(ph)) { 2436 #ifdef DIAGNOSTIC 2437 printf("pccbb_pcmcia_socket_enable: never became ready\n"); 2438 #endif 2439 /* XXX return a failure status?? */ 2440 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2441 Pcic_write(ph, PCIC_PWRCTL, 0); 2442 return; 2443 } 2444 2445 /* reinstall all the memory and io mappings */ 2446 for (win = 0; win < PCIC_MEM_WINS; ++win) 2447 if (ph->memalloc & (1 << win)) 2448 pccbb_pcmcia_do_mem_map(ph, win); 2449 for (win = 0; win < PCIC_IO_WINS; ++win) 2450 if (ph->ioalloc & (1 << win)) 2451 pccbb_pcmcia_do_io_map(ph, win); 2452 } 2453 2454 /* 2455 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2456 * 2457 * This function disables the card. All information is stored in 2458 * the first argument, pcmcia_chipset_handle_t. 2459 */ 2460 STATIC void 2461 pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t pch) 2462 { 2463 struct pcic_handle *ph = (struct pcic_handle *)pch; 2464 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2465 u_int8_t intr; 2466 2467 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2468 2469 /* disable interrupts; assert RESET */ 2470 intr = Pcic_read(ph, PCIC_INTR); 2471 intr &= PCIC_INTR_ENABLE; 2472 Pcic_write(ph, PCIC_INTR, intr); 2473 2474 /* zero out the address windows */ 2475 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2476 2477 /* power down the socket to reset it, clear the card reset pin */ 2478 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2479 2480 /* disable socket: negate output enable bit and power off */ 2481 Pcic_write(ph, PCIC_PWRCTL, 0); 2482 2483 /* 2484 * Vcc Falling Time (Tpf) = 300ms 2485 */ 2486 pccbb_pcmcia_delay(ph, 300, "pccwr1"); 2487 } 2488 2489 STATIC void 2490 pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t pch, int type) 2491 { 2492 struct pcic_handle *ph = (struct pcic_handle *)pch; 2493 u_int8_t intr; 2494 2495 /* set the card type */ 2496 2497 intr = Pcic_read(ph, PCIC_INTR); 2498 intr &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_CARDTYPE_MASK); 2499 if (type == PCMCIA_IFTYPE_IO) 2500 intr |= PCIC_INTR_CARDTYPE_IO; 2501 else 2502 intr |= PCIC_INTR_CARDTYPE_MEM; 2503 Pcic_write(ph, PCIC_INTR, intr); 2504 2505 DPRINTF(("%s: pccbb_pcmcia_socket_settype %02x type %s %02x\n", 2506 ph->ph_parent->dv_xname, ph->sock, 2507 ((type == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2508 } 2509 2510 /* 2511 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2512 * 2513 * This function detects whether a card is in the slot or not. 2514 * If a card is inserted, return 1. Otherwise, return 0. 2515 */ 2516 STATIC int 2517 pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch) 2518 { 2519 struct pcic_handle *ph = (struct pcic_handle *)pch; 2520 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2521 2522 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2523 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2524 } 2525 2526 #if 0 2527 STATIC int 2528 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2529 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2530 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2531 #endif 2532 /* 2533 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2534 * bus_size_t size, 2535 * struct pcmcia_mem_handle *pcmhp) 2536 * 2537 * This function only allocates memory region for pccard. This 2538 * function never maps the allocated region to pccard memory area. 2539 * 2540 * XXX: Why the argument of start address is not in? 2541 */ 2542 STATIC int 2543 pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 2544 struct pcmcia_mem_handle *pcmhp) 2545 { 2546 struct pcic_handle *ph = (struct pcic_handle *)pch; 2547 bus_space_handle_t memh; 2548 bus_addr_t addr; 2549 bus_size_t sizepg; 2550 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2551 #if rbus 2552 rbus_tag_t rb; 2553 #endif 2554 2555 /* Check that the card is still there. */ 2556 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2557 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2558 return 1; 2559 2560 /* out of sc->memh, allocate as many pages as necessary */ 2561 2562 /* convert size to PCIC pages */ 2563 /* 2564 * This is not enough; when the requested region is on the page 2565 * boundaries, this may calculate wrong result. 2566 */ 2567 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2568 #if 0 2569 if (sizepg > PCIC_MAX_MEM_PAGES) { 2570 return 1; 2571 } 2572 #endif 2573 2574 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2575 return 1; 2576 } 2577 2578 addr = 0; /* XXX gcc -Wuninitialized */ 2579 2580 #if rbus 2581 rb = sc->sc_rbus_memt; 2582 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2583 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2584 &addr, &memh)) { 2585 return 1; 2586 } 2587 #else 2588 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2589 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2590 0, /* boundary */ 2591 0, /* flags */ 2592 &addr, &memh)) { 2593 return 1; 2594 } 2595 #endif 2596 2597 DPRINTF(("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, " 2598 "realsize 0x%lx\n", (unsigned long)addr, (unsigned long)size, 2599 (unsigned long)sizepg * PCIC_MEM_PAGESIZE)); 2600 2601 pcmhp->memt = sc->sc_memt; 2602 pcmhp->memh = memh; 2603 pcmhp->addr = addr; 2604 pcmhp->size = size; 2605 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2606 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2607 pcmhp->mhandle = 0; 2608 /* No offset??? Funny. */ 2609 2610 return 0; 2611 } 2612 2613 /* 2614 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2615 * struct pcmcia_mem_handle *pcmhp) 2616 * 2617 * This function release the memory space allocated by the function 2618 * pccbb_pcmcia_mem_alloc(). 2619 */ 2620 STATIC void 2621 pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2622 struct pcmcia_mem_handle *pcmhp) 2623 { 2624 #if rbus 2625 struct pcic_handle *ph = (struct pcic_handle *)pch; 2626 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2627 2628 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2629 #else 2630 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2631 #endif 2632 } 2633 2634 /* 2635 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2636 * 2637 * This function release the memory space allocated by the function 2638 * pccbb_pcmcia_mem_alloc(). 2639 */ 2640 STATIC void 2641 pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2642 { 2643 int regbase_win; 2644 bus_addr_t phys_addr; 2645 bus_addr_t phys_end; 2646 2647 #define PCIC_SMM_START_LOW 0 2648 #define PCIC_SMM_START_HIGH 1 2649 #define PCIC_SMM_STOP_LOW 2 2650 #define PCIC_SMM_STOP_HIGH 3 2651 #define PCIC_CMA_LOW 4 2652 #define PCIC_CMA_HIGH 5 2653 2654 u_int8_t start_low, start_high = 0; 2655 u_int8_t stop_low, stop_high; 2656 u_int8_t off_low, off_high; 2657 u_int8_t mem_window; 2658 int reg; 2659 2660 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2661 int mem8 = 2662 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2663 || (kind == PCMCIA_MEM_ATTR); 2664 2665 regbase_win = 0x10 + win * 0x08; 2666 2667 phys_addr = ph->mem[win].addr; 2668 phys_end = phys_addr + ph->mem[win].size; 2669 2670 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2671 (unsigned long)phys_addr, (unsigned long)phys_end, 2672 (unsigned long)ph->mem[win].offset)); 2673 2674 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2675 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2676 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2677 2678 /* bit 19:12 */ 2679 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2680 /* bit 23:20 and bit 7 on */ 2681 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2682 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2683 /* bit 31:24, for 32-bit address */ 2684 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2685 2686 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2687 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2688 2689 if (((struct pccbb_softc *)ph-> 2690 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2691 Pcic_write(ph, 0x40 + win, mem_window); 2692 } 2693 2694 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2695 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2696 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2697 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2698 2699 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2700 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2701 2702 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2703 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2704 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2705 | ((kind == PCMCIA_MEM_ATTR) ? 2706 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2707 2708 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2709 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2710 2711 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2712 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2713 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2714 2715 #if defined(CBB_DEBUG) 2716 { 2717 int r1, r2, r3, r4, r5, r6, r7 = 0; 2718 2719 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2720 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2721 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2722 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2723 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2724 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2725 if (((struct pccbb_softc *)(ph-> 2726 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2727 r7 = Pcic_read(ph, 0x40 + win); 2728 } 2729 2730 printf("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2731 "%02x%02x", win, r1, r2, r3, r4, r5, r6); 2732 if (((struct pccbb_softc *)(ph-> 2733 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2734 printf(" %02x", r7); 2735 } 2736 printf("\n"); 2737 } 2738 #endif 2739 } 2740 2741 /* 2742 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2743 * bus_addr_t card_addr, bus_size_t size, 2744 * struct pcmcia_mem_handle *pcmhp, 2745 * bus_addr_t *offsetp, int *windowp) 2746 * 2747 * This function maps memory space allocated by the function 2748 * pccbb_pcmcia_mem_alloc(). 2749 */ 2750 STATIC int 2751 pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2752 bus_addr_t card_addr, bus_size_t size, struct pcmcia_mem_handle *pcmhp, 2753 bus_addr_t *offsetp, int *windowp) 2754 { 2755 struct pcic_handle *ph = (struct pcic_handle *)pch; 2756 bus_addr_t busaddr; 2757 long card_offset; 2758 int win; 2759 2760 /* Check that the card is still there. */ 2761 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2762 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2763 return 1; 2764 2765 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2766 if ((ph->memalloc & (1 << win)) == 0) { 2767 ph->memalloc |= (1 << win); 2768 break; 2769 } 2770 } 2771 2772 if (win == PCIC_MEM_WINS) { 2773 return 1; 2774 } 2775 2776 *windowp = win; 2777 2778 /* XXX this is pretty gross */ 2779 2780 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2781 panic("pccbb_pcmcia_mem_map memt is bogus"); 2782 } 2783 2784 busaddr = pcmhp->addr; 2785 2786 /* 2787 * compute the address offset to the pcmcia address space for the 2788 * pcic. this is intentionally signed. The masks and shifts below 2789 * will cause TRT to happen in the pcic registers. Deal with making 2790 * sure the address is aligned, and return the alignment offset. 2791 */ 2792 2793 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2794 card_addr -= *offsetp; 2795 2796 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2797 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2798 (u_long) card_addr)); 2799 2800 /* 2801 * include the offset in the size, and decrement size by one, since 2802 * the hw wants start/stop 2803 */ 2804 size += *offsetp - 1; 2805 2806 card_offset = (((long)card_addr) - ((long)busaddr)); 2807 2808 ph->mem[win].addr = busaddr; 2809 ph->mem[win].size = size; 2810 ph->mem[win].offset = card_offset; 2811 ph->mem[win].kind = kind; 2812 2813 pccbb_pcmcia_do_mem_map(ph, win); 2814 2815 return 0; 2816 } 2817 2818 /* 2819 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2820 * int window) 2821 * 2822 * This function unmaps memory space which mapped by the function 2823 * pccbb_pcmcia_mem_map(). 2824 */ 2825 STATIC void 2826 pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, int window) 2827 { 2828 struct pcic_handle *ph = (struct pcic_handle *)pch; 2829 int reg; 2830 2831 if (window >= PCIC_MEM_WINS) { 2832 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2833 } 2834 2835 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2836 reg &= ~(1 << window); 2837 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2838 2839 ph->memalloc &= ~(1 << window); 2840 } 2841 2842 #if defined PCCBB_PCMCIA_POLL 2843 struct pccbb_poll_str { 2844 void *arg; 2845 int (*func)(void *); 2846 int level; 2847 struct pcic_handle *ph; 2848 int count; 2849 int num; 2850 struct callout poll_ch; 2851 }; 2852 2853 static struct pccbb_poll_str pccbb_poll[10]; 2854 static int pccbb_poll_n = 0; 2855 2856 static void pccbb_pcmcia_poll(void *arg); 2857 2858 static void 2859 pccbb_pcmcia_poll(void *arg) 2860 { 2861 struct pccbb_poll_str *poll = arg; 2862 struct pcic_handle *ph = poll->ph; 2863 struct pccbb_softc *sc = ph->sc; 2864 int s; 2865 u_int32_t spsr; /* socket present-state reg */ 2866 2867 callout_reset(&poll->poll_ch, hz * 2, pccbb_pcmcia_poll, arg); 2868 switch (poll->level) { 2869 case IPL_NET: 2870 s = splnet(); 2871 break; 2872 case IPL_BIO: 2873 s = splbio(); 2874 break; 2875 case IPL_TTY: /* fallthrough */ 2876 default: 2877 s = spltty(); 2878 break; 2879 } 2880 2881 spsr = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2882 CB_SOCKET_STAT); 2883 2884 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2885 if (!(spsr & 0x40)) /* CINT low */ 2886 #else 2887 if (1) 2888 #endif 2889 { 2890 if ((*poll->func) (poll->arg) > 0) { 2891 ++poll->count; 2892 /* printf("intr: reported from poller, 0x%x\n", spsr); */ 2893 #if defined LEVEL2 2894 } else { 2895 printf("intr: miss! 0x%x\n", spsr); 2896 #endif 2897 } 2898 } 2899 splx(s); 2900 } 2901 #endif /* defined CB_PCMCIA_POLL */ 2902 2903 /* 2904 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2905 * struct pcmcia_function *pf, 2906 * int ipl, 2907 * int (*func)(void *), 2908 * void *arg); 2909 * 2910 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2911 */ 2912 STATIC void * 2913 pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2914 struct pcmcia_function *pf, int ipl, int (*func)(void *), void *arg) 2915 { 2916 struct pcic_handle *ph = (struct pcic_handle *)pch; 2917 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2918 2919 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2920 /* what should I do? */ 2921 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2922 DPRINTF(("%s does not provide edge nor pulse " 2923 "interrupt\n", sc->sc_dev.dv_xname)); 2924 return NULL; 2925 } 2926 /* 2927 * XXX Noooooo! The interrupt flag must set properly!! 2928 * dumb pcmcia driver!! 2929 */ 2930 } 2931 2932 return pccbb_intr_establish(sc, 0, ipl, func, arg); 2933 } 2934 2935 /* 2936 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2937 * void *ih) 2938 * 2939 * This function disables PC-Card interrupt. 2940 */ 2941 STATIC void 2942 pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 2943 { 2944 struct pcic_handle *ph = (struct pcic_handle *)pch; 2945 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2946 2947 pccbb_intr_disestablish(sc, ih); 2948 } 2949 2950 #if rbus 2951 /* 2952 * static int 2953 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2954 * bus_addr_t addr, bus_size_t size, 2955 * bus_addr_t mask, bus_size_t align, 2956 * int flags, bus_addr_t *addrp; 2957 * bus_space_handle_t *bshp) 2958 * 2959 * This function allocates a portion of memory or io space for 2960 * clients. This function is called from CardBus card drivers. 2961 */ 2962 static int 2963 pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2964 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 2965 int flags, bus_addr_t *addrp, bus_space_handle_t *bshp) 2966 { 2967 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2968 2969 DPRINTF(("pccbb_rbus_cb_space_alloc: addr 0x%lx, size 0x%lx, " 2970 "mask 0x%lx, align 0x%lx\n", (unsigned long)addr, 2971 (unsigned long)size, (unsigned long)mask, (unsigned long)align)); 2972 2973 if (align == 0) { 2974 align = size; 2975 } 2976 2977 if (rb->rb_bt == sc->sc_memt) { 2978 if (align < 16) { 2979 return 1; 2980 } 2981 /* 2982 * XXX: align more than 0x1000 to avoid overwrapping 2983 * memory windows for two or more devices. 0x1000 2984 * means memory window's granularity. 2985 * 2986 * Two or more devices should be able to share same 2987 * memory window region. However, overrapping memory 2988 * window is not good because some devices, such as 2989 * 3Com 3C575[BC], have a broken address decoder and 2990 * intrude other's memory region. 2991 */ 2992 if (align < 0x1000) { 2993 align = 0x1000; 2994 } 2995 } else if (rb->rb_bt == sc->sc_iot) { 2996 if (align < 4) { 2997 return 1; 2998 } 2999 /* XXX: hack for avoiding ISA image */ 3000 if (mask < 0x0100) { 3001 mask = 0x3ff; 3002 addr = 0x300; 3003 } 3004 3005 } else { 3006 DPRINTF(("pccbb_rbus_cb_space_alloc: Bus space tag 0x%lx is " 3007 "NOT used. io: 0x%lx, mem: 0x%lx\n", 3008 (unsigned long)rb->rb_bt, (unsigned long)sc->sc_iot, 3009 (unsigned long)sc->sc_memt)); 3010 return 1; 3011 /* XXX: panic here? */ 3012 } 3013 3014 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 3015 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 3016 return 1; 3017 } 3018 3019 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 3020 3021 return 0; 3022 } 3023 3024 /* 3025 * static int 3026 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 3027 * bus_space_handle_t *bshp, bus_size_t size); 3028 * 3029 * This function is called from CardBus card drivers. 3030 */ 3031 static int 3032 pccbb_rbus_cb_space_free(cardbus_chipset_tag_t ct, rbus_tag_t rb, 3033 bus_space_handle_t bsh, bus_size_t size) 3034 { 3035 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 3036 bus_space_tag_t bt = rb->rb_bt; 3037 3038 pccbb_close_win(sc, bt, bsh, size); 3039 3040 if (bt == sc->sc_memt) { 3041 } else if (bt == sc->sc_iot) { 3042 } else { 3043 return 1; 3044 /* XXX: panic here? */ 3045 } 3046 3047 return rbus_space_free(rb, bsh, size, NULL); 3048 } 3049 #endif /* rbus */ 3050 3051 #if rbus 3052 3053 static int 3054 pccbb_open_win(struct pccbb_softc *sc, bus_space_tag_t bst, bus_addr_t addr, 3055 bus_size_t size, bus_space_handle_t bsh, int flags) 3056 { 3057 struct pccbb_win_chain_head *head; 3058 bus_addr_t align; 3059 3060 head = &sc->sc_iowindow; 3061 align = 0x04; 3062 if (sc->sc_memt == bst) { 3063 head = &sc->sc_memwindow; 3064 align = 0x1000; 3065 DPRINTF(("using memory window, 0x%lx 0x%lx 0x%lx\n\n", 3066 (unsigned long)sc->sc_iot, (unsigned long)sc->sc_memt, 3067 (unsigned long)bst)); 3068 } 3069 3070 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 3071 printf("%s: pccbb_open_win: %s winlist insert failed\n", 3072 sc->sc_dev.dv_xname, 3073 (head == &sc->sc_memwindow) ? "mem" : "io"); 3074 } 3075 pccbb_winset(align, sc, bst); 3076 3077 return 0; 3078 } 3079 3080 static int 3081 pccbb_close_win(struct pccbb_softc *sc, bus_space_tag_t bst, 3082 bus_space_handle_t bsh, bus_size_t size) 3083 { 3084 struct pccbb_win_chain_head *head; 3085 bus_addr_t align; 3086 3087 head = &sc->sc_iowindow; 3088 align = 0x04; 3089 if (sc->sc_memt == bst) { 3090 head = &sc->sc_memwindow; 3091 align = 0x1000; 3092 } 3093 3094 if (pccbb_winlist_delete(head, bsh, size)) { 3095 printf("%s: pccbb_close_win: %s winlist delete failed\n", 3096 sc->sc_dev.dv_xname, 3097 (head == &sc->sc_memwindow) ? "mem" : "io"); 3098 } 3099 pccbb_winset(align, sc, bst); 3100 3101 return 0; 3102 } 3103 3104 static int 3105 pccbb_winlist_insert(struct pccbb_win_chain_head *head, bus_addr_t start, 3106 bus_size_t size, bus_space_handle_t bsh, int flags) 3107 { 3108 struct pccbb_win_chain *chainp, *elem; 3109 3110 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 3111 M_NOWAIT)) == NULL) 3112 return (1); /* fail */ 3113 3114 elem->wc_start = start; 3115 elem->wc_end = start + (size - 1); 3116 elem->wc_handle = bsh; 3117 elem->wc_flags = flags; 3118 3119 TAILQ_FOREACH(chainp, head, wc_list) { 3120 if (chainp->wc_end >= start) 3121 break; 3122 } 3123 if (chainp != NULL) 3124 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 3125 else 3126 TAILQ_INSERT_TAIL(head, elem, wc_list); 3127 return (0); 3128 } 3129 3130 static int 3131 pccbb_winlist_delete(struct pccbb_win_chain_head *head, bus_space_handle_t bsh, 3132 bus_size_t size) 3133 { 3134 struct pccbb_win_chain *chainp; 3135 3136 TAILQ_FOREACH(chainp, head, wc_list) { 3137 if (memcmp(&chainp->wc_handle, &bsh, sizeof(bsh)) == 0) 3138 break; 3139 } 3140 if (chainp == NULL) 3141 return 1; /* fail: no candidate to remove */ 3142 3143 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 3144 printf("pccbb_winlist_delete: window 0x%lx size " 3145 "inconsistent: 0x%lx, 0x%lx\n", 3146 (unsigned long)chainp->wc_start, 3147 (unsigned long)(chainp->wc_end - chainp->wc_start), 3148 (unsigned long)(size - 1)); 3149 return 1; 3150 } 3151 3152 TAILQ_REMOVE(head, chainp, wc_list); 3153 free(chainp, M_DEVBUF); 3154 3155 return 0; 3156 } 3157 3158 static void 3159 pccbb_winset(bus_addr_t align, struct pccbb_softc *sc, bus_space_tag_t bst) 3160 { 3161 pci_chipset_tag_t pc; 3162 pcitag_t tag; 3163 bus_addr_t mask = ~(align - 1); 3164 struct { 3165 cardbusreg_t win_start; 3166 cardbusreg_t win_limit; 3167 int win_flags; 3168 } win[2]; 3169 struct pccbb_win_chain *chainp; 3170 int offs; 3171 3172 win[0].win_start = win[1].win_start = 0xffffffff; 3173 win[0].win_limit = win[1].win_limit = 0; 3174 win[0].win_flags = win[1].win_flags = 0; 3175 3176 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3177 offs = 0x2c; 3178 if (sc->sc_memt == bst) { 3179 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3180 offs = 0x1c; 3181 } 3182 3183 if (chainp != NULL) { 3184 win[0].win_start = chainp->wc_start & mask; 3185 win[0].win_limit = chainp->wc_end & mask; 3186 win[0].win_flags = chainp->wc_flags; 3187 chainp = TAILQ_NEXT(chainp, wc_list); 3188 } 3189 3190 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3191 if (win[1].win_start == 0xffffffff) { 3192 /* window 1 is not used */ 3193 if ((win[0].win_flags == chainp->wc_flags) && 3194 (win[0].win_limit + align >= 3195 (chainp->wc_start & mask))) { 3196 /* concatenate */ 3197 win[0].win_limit = chainp->wc_end & mask; 3198 } else { 3199 /* make new window */ 3200 win[1].win_start = chainp->wc_start & mask; 3201 win[1].win_limit = chainp->wc_end & mask; 3202 win[1].win_flags = chainp->wc_flags; 3203 } 3204 continue; 3205 } 3206 3207 /* Both windows are engaged. */ 3208 if (win[0].win_flags == win[1].win_flags) { 3209 /* same flags */ 3210 if (win[0].win_flags == chainp->wc_flags) { 3211 if (win[1].win_start - (win[0].win_limit + 3212 align) < 3213 (chainp->wc_start & mask) - 3214 ((chainp->wc_end & mask) + align)) { 3215 /* 3216 * merge window 0 and 1, and set win1 3217 * to chainp 3218 */ 3219 win[0].win_limit = win[1].win_limit; 3220 win[1].win_start = 3221 chainp->wc_start & mask; 3222 win[1].win_limit = 3223 chainp->wc_end & mask; 3224 } else { 3225 win[1].win_limit = 3226 chainp->wc_end & mask; 3227 } 3228 } else { 3229 /* different flags */ 3230 3231 /* concatenate win0 and win1 */ 3232 win[0].win_limit = win[1].win_limit; 3233 /* allocate win[1] to new space */ 3234 win[1].win_start = chainp->wc_start & mask; 3235 win[1].win_limit = chainp->wc_end & mask; 3236 win[1].win_flags = chainp->wc_flags; 3237 } 3238 } else { 3239 /* the flags of win[0] and win[1] is different */ 3240 if (win[0].win_flags == chainp->wc_flags) { 3241 win[0].win_limit = chainp->wc_end & mask; 3242 /* 3243 * XXX this creates overlapping windows, so 3244 * what should the poor bridge do if one is 3245 * cachable, and the other is not? 3246 */ 3247 printf("%s: overlapping windows\n", 3248 sc->sc_dev.dv_xname); 3249 } else { 3250 win[1].win_limit = chainp->wc_end & mask; 3251 } 3252 } 3253 } 3254 3255 pc = sc->sc_pc; 3256 tag = sc->sc_tag; 3257 pci_conf_write(pc, tag, offs, win[0].win_start); 3258 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3259 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3260 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3261 DPRINTF(("--pccbb_winset: win0 [0x%lx, 0x%lx), win1 [0x%lx, 0x%lx)\n", 3262 (unsigned long)pci_conf_read(pc, tag, offs), 3263 (unsigned long)pci_conf_read(pc, tag, offs + 4) + align, 3264 (unsigned long)pci_conf_read(pc, tag, offs + 8), 3265 (unsigned long)pci_conf_read(pc, tag, offs + 12) + align)); 3266 3267 if (bst == sc->sc_memt) { 3268 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BRIDGE_CONTROL_REG); 3269 3270 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 3271 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 3272 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3273 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 3274 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3275 pci_conf_write(pc, tag, PCI_BRIDGE_CONTROL_REG, bcr); 3276 } 3277 } 3278 3279 #endif /* rbus */ 3280 3281 static bool 3282 pccbb_suspend(device_t dv) 3283 { 3284 struct pccbb_softc *sc = device_private(dv); 3285 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3286 bus_space_handle_t base_memh = sc->sc_base_memh; 3287 pcireg_t reg; 3288 3289 if (sc->sc_pil_intr_enable) 3290 (void)pccbbintr_function(sc); 3291 sc->sc_pil_intr_enable = 0; 3292 3293 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3294 /* Disable interrupts. */ 3295 reg &= ~(CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER); 3296 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3297 /* XXX joerg Disable power to the socket? */ 3298 3299 #ifdef __NO_STRICT_ALIGNMENT 3300 /* XXX - the register is at 0x82, so this access is not valid */ 3301 if (sc->sc_chipset == CB_RX5C47X) 3302 sc->sc_ricoh_misc_ctrl = pci_conf_read(sc->sc_pc, 3303 sc->sc_tag, RICOH_PCI_MISC_CTRL); 3304 #endif 3305 3306 return true; 3307 } 3308 3309 static bool 3310 pccbb_resume(device_t dv) 3311 { 3312 struct pccbb_softc *sc = device_private(dv); 3313 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3314 bus_space_handle_t base_memh = sc->sc_base_memh; 3315 pcireg_t reg; 3316 3317 pccbb_chipinit(sc); 3318 /* setup memory and io space window for CB */ 3319 pccbb_winset(0x1000, sc, sc->sc_memt); 3320 pccbb_winset(0x04, sc, sc->sc_iot); 3321 #ifdef __NO_STRICT_ALIGNMENT 3322 /* XXX - the register is at 0x82, so this access is not valid */ 3323 if (sc->sc_chipset == CB_RX5C47X) 3324 pci_conf_write(sc->sc_pc, sc->sc_tag, 3325 RICOH_PCI_MISC_CTRL, sc->sc_ricoh_misc_ctrl); 3326 #endif 3327 3328 /* CSC Interrupt: Card detect interrupt on */ 3329 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3330 /* Card detect intr is turned on. */ 3331 reg |= CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; 3332 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3333 /* reset interrupt */ 3334 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3335 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3336 3337 /* 3338 * check for card insertion or removal during suspend period. 3339 * XXX: the code can't cope with card swap (remove then 3340 * insert). how can we detect such situation? 3341 */ 3342 (void)pccbbintr(sc); 3343 3344 sc->sc_pil_intr_enable = 1; 3345 3346 return true; 3347 } 3348
Indexes created Mon Sep 29 21:09:56 GMT 2025