pccbb.c revision 1.159
1 /* $NetBSD: pccbb.c,v 1.159 2007/12/20 20:48:24 dyoung Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: pccbb.c,v 1.159 2007/12/20 20:48:24 dyoung Exp $"); 35 36 /* 37 #define CBB_DEBUG 38 #define SHOW_REGS 39 */ 40 41 /* 42 * BROKEN! 43 #define PCCBB_PCMCIA_POLL 44 #define CB_PCMCIA_POLL 45 #define CB_PCMCIA_POLL_ONLY 46 #define LEVEL2 47 */ 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/kernel.h> 52 #include <sys/errno.h> 53 #include <sys/ioctl.h> 54 #include <sys/reboot.h> /* for bootverbose */ 55 #include <sys/syslog.h> 56 #include <sys/device.h> 57 #include <sys/malloc.h> 58 #include <sys/proc.h> 59 60 #include <sys/intr.h> 61 #include <sys/bus.h> 62 63 #include <dev/pci/pcivar.h> 64 #include <dev/pci/pcireg.h> 65 #include <dev/pci/pcidevs.h> 66 67 #include <dev/pci/pccbbreg.h> 68 69 #include <dev/cardbus/cardslotvar.h> 70 71 #include <dev/cardbus/cardbusvar.h> 72 73 #include <dev/pcmcia/pcmciareg.h> 74 #include <dev/pcmcia/pcmciavar.h> 75 76 #include <dev/ic/i82365reg.h> 77 #include <dev/ic/i82365var.h> 78 #include <dev/pci/pccbbvar.h> 79 80 #include "locators.h" 81 82 #ifndef __NetBSD_Version__ 83 struct cfdriver cbb_cd = { 84 NULL, "cbb", DV_DULL 85 }; 86 #endif 87 88 #ifdef CBB_DEBUG 89 #define DPRINTF(x) printf x 90 #define STATIC 91 #else 92 #define DPRINTF(x) 93 #define STATIC static 94 #endif 95 96 int pccbb_burstup = 1; 97 98 /* 99 * delay_ms() is wait in milliseconds. It should be used instead 100 * of delay() if you want to wait more than 1 ms. 101 */ 102 static inline void 103 delay_ms(int millis, void *param) 104 { 105 if (cold) 106 delay(millis * 1000); 107 else 108 tsleep(param, PWAIT, "pccbb", MAX(2, hz * millis / 1000)); 109 } 110 111 int pcicbbmatch(struct device *, struct cfdata *, void *); 112 void pccbbattach(struct device *, struct device *, void *); 113 int pccbbdetach(device_t, int); 114 int pccbbintr(void *); 115 static void pci113x_insert(void *); 116 static int pccbbintr_function(struct pccbb_softc *); 117 118 static int pccbb_detect_card(struct pccbb_softc *); 119 120 static void pccbb_pcmcia_write(struct pcic_handle *, int, u_int8_t); 121 static u_int8_t pccbb_pcmcia_read(struct pcic_handle *, int); 122 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 123 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 124 125 STATIC int cb_reset(struct pccbb_softc *); 126 STATIC int cb_detect_voltage(struct pccbb_softc *); 127 STATIC int cbbprint(void *, const char *); 128 129 static int cb_chipset(u_int32_t, int *); 130 STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *, 131 struct pcmciabus_attach_args *); 132 #if 0 133 STATIC void pccbb_pcmcia_attach_card(struct pcic_handle *); 134 STATIC void pccbb_pcmcia_detach_card(struct pcic_handle *, int); 135 STATIC void pccbb_pcmcia_deactivate_card(struct pcic_handle *); 136 #endif 137 138 STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int); 139 STATIC int pccbb_power(cardbus_chipset_tag_t, int); 140 STATIC int pccbb_cardenable(struct pccbb_softc * sc, int function); 141 #if !rbus 142 static int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 143 static int pccbb_io_close(cardbus_chipset_tag_t, int); 144 static int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 145 static int pccbb_mem_close(cardbus_chipset_tag_t, int); 146 #endif /* !rbus */ 147 static void *pccbb_intr_establish(struct pccbb_softc *, int irq, 148 int level, int (*ih) (void *), void *sc); 149 static void pccbb_intr_disestablish(struct pccbb_softc *, void *ih); 150 151 static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t, int irq, 152 int level, int (*ih) (void *), void *sc); 153 static void pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih); 154 155 static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t, int, int); 156 static void pccbb_free_tag(cardbus_chipset_tag_t, cardbustag_t); 157 static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t, cardbustag_t, int); 158 static void pccbb_conf_write(cardbus_chipset_tag_t, cardbustag_t, int, 159 cardbusreg_t); 160 static void pccbb_chipinit(struct pccbb_softc *); 161 162 STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 163 struct pcmcia_mem_handle *); 164 STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t, 165 struct pcmcia_mem_handle *); 166 STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 167 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *); 168 STATIC void pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t, int); 169 STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 170 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 171 STATIC void pccbb_pcmcia_io_free(pcmcia_chipset_handle_t, 172 struct pcmcia_io_handle *); 173 STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 174 bus_size_t, struct pcmcia_io_handle *, int *); 175 STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t, int); 176 STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t, 177 struct pcmcia_function *, int, int (*)(void *), void *); 178 STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t, void *); 179 STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t); 180 STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t); 181 STATIC void pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t, int); 182 STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch); 183 184 static int pccbb_pcmcia_wait_ready(struct pcic_handle *); 185 static void pccbb_pcmcia_delay(struct pcic_handle *, int, const char *); 186 187 static void pccbb_pcmcia_do_io_map(struct pcic_handle *, int); 188 static void pccbb_pcmcia_do_mem_map(struct pcic_handle *, int); 189 190 /* bus-space allocation and deallocation functions */ 191 #if rbus 192 193 static int pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t, rbus_tag_t, 194 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 195 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp); 196 static int pccbb_rbus_cb_space_free(cardbus_chipset_tag_t, rbus_tag_t, 197 bus_space_handle_t, bus_size_t); 198 199 #endif /* rbus */ 200 201 #if rbus 202 203 static int pccbb_open_win(struct pccbb_softc *, bus_space_tag_t, 204 bus_addr_t, bus_size_t, bus_space_handle_t, int flags); 205 static int pccbb_close_win(struct pccbb_softc *, bus_space_tag_t, 206 bus_space_handle_t, bus_size_t); 207 static int pccbb_winlist_insert(struct pccbb_win_chain_head *, bus_addr_t, 208 bus_size_t, bus_space_handle_t, int); 209 static int pccbb_winlist_delete(struct pccbb_win_chain_head *, 210 bus_space_handle_t, bus_size_t); 211 static void pccbb_winset(bus_addr_t align, struct pccbb_softc *, 212 bus_space_tag_t); 213 void pccbb_winlist_show(struct pccbb_win_chain *); 214 215 #endif /* rbus */ 216 217 /* for config_defer */ 218 static void pccbb_pci_callback(struct device *); 219 220 static bool pccbb_suspend(device_t); 221 static bool pccbb_resume(device_t); 222 223 #if defined SHOW_REGS 224 static void cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, 225 bus_space_tag_t memt, bus_space_handle_t memh); 226 #endif 227 228 CFATTACH_DECL(cbb_pci, sizeof(struct pccbb_softc), 229 pcicbbmatch, pccbbattach, pccbbdetach, NULL); 230 231 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 232 pccbb_pcmcia_mem_alloc, 233 pccbb_pcmcia_mem_free, 234 pccbb_pcmcia_mem_map, 235 pccbb_pcmcia_mem_unmap, 236 pccbb_pcmcia_io_alloc, 237 pccbb_pcmcia_io_free, 238 pccbb_pcmcia_io_map, 239 pccbb_pcmcia_io_unmap, 240 pccbb_pcmcia_intr_establish, 241 pccbb_pcmcia_intr_disestablish, 242 pccbb_pcmcia_socket_enable, 243 pccbb_pcmcia_socket_disable, 244 pccbb_pcmcia_socket_settype, 245 pccbb_pcmcia_card_detect 246 }; 247 248 #if rbus 249 static struct cardbus_functions pccbb_funcs = { 250 pccbb_rbus_cb_space_alloc, 251 pccbb_rbus_cb_space_free, 252 pccbb_cb_intr_establish, 253 pccbb_cb_intr_disestablish, 254 pccbb_ctrl, 255 pccbb_power, 256 pccbb_make_tag, 257 pccbb_free_tag, 258 pccbb_conf_read, 259 pccbb_conf_write, 260 }; 261 #else 262 static struct cardbus_functions pccbb_funcs = { 263 pccbb_ctrl, 264 pccbb_power, 265 pccbb_mem_open, 266 pccbb_mem_close, 267 pccbb_io_open, 268 pccbb_io_close, 269 pccbb_cb_intr_establish, 270 pccbb_cb_intr_disestablish, 271 pccbb_make_tag, 272 pccbb_conf_read, 273 pccbb_conf_write, 274 }; 275 #endif 276 277 int 278 pcicbbmatch(struct device *parent, struct cfdata *match, void *aux) 279 { 280 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 281 282 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 283 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 284 PCI_INTERFACE(pa->pa_class) == 0) { 285 return 1; 286 } 287 288 return 0; 289 } 290 291 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 292 | ((prod) << PCI_PRODUCT_SHIFT)) 293 294 const struct yenta_chipinfo { 295 pcireg_t yc_id; /* vendor tag | product tag */ 296 int yc_chiptype; 297 int yc_flags; 298 } yc_chipsets[] = { 299 /* Texas Instruments chips */ 300 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 301 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 302 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 303 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 304 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI125X, 305 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 306 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 307 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 308 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 309 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 310 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 311 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 312 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI125X, 313 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 314 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI125X, 315 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 316 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 317 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 318 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 319 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 320 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI1420, 321 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 322 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI125X, 323 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 324 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 325 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 326 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1520), CB_TI12XX, 327 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 328 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4410YENTA), CB_TI12XX, 329 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 330 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4520YENTA), CB_TI12XX, 331 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 332 333 /* Ricoh chips */ 334 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 335 PCCBB_PCMCIA_MEM_32}, 336 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 337 PCCBB_PCMCIA_MEM_32}, 338 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 339 PCCBB_PCMCIA_MEM_32}, 340 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 341 PCCBB_PCMCIA_MEM_32}, 342 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 343 PCCBB_PCMCIA_MEM_32}, 344 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 345 PCCBB_PCMCIA_MEM_32}, 346 347 /* Toshiba products */ 348 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 349 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 350 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 351 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 352 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 353 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 354 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 355 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 356 357 /* Cirrus Logic products */ 358 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 359 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 360 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 361 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 362 363 /* sentinel, or Generic chip */ 364 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 365 }; 366 367 static int 368 cb_chipset(u_int32_t pci_id, int *flagp) 369 { 370 const struct yenta_chipinfo *yc; 371 372 /* Loop over except the last default entry. */ 373 for (yc = yc_chipsets; yc < yc_chipsets + 374 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 375 if (pci_id == yc->yc_id) 376 break; 377 378 if (flagp != NULL) 379 *flagp = yc->yc_flags; 380 381 return (yc->yc_chiptype); 382 } 383 384 void 385 pccbbattach(struct device *parent, struct device *self, void *aux) 386 { 387 struct pccbb_softc *sc = (void *)self; 388 struct pci_attach_args *pa = aux; 389 pci_chipset_tag_t pc = pa->pa_pc; 390 pcireg_t busreg, reg, sock_base; 391 bus_addr_t sockbase; 392 char devinfo[256]; 393 int flags; 394 395 #ifdef __HAVE_PCCBB_ATTACH_HOOK 396 pccbb_attach_hook(parent, self, pa); 397 #endif 398 399 callout_init(&sc->sc_insert_ch, 0); 400 callout_setfunc(&sc->sc_insert_ch, pci113x_insert, sc); 401 402 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 403 404 aprint_naive("\n"); 405 406 pci_devinfo(pa->pa_id, 0, 0, devinfo, sizeof(devinfo)); 407 aprint_normal(": %s (rev. 0x%02x)", devinfo, 408 PCI_REVISION(pa->pa_class)); 409 DPRINTF((" (chipflags %x)", flags)); 410 aprint_normal("\n"); 411 412 TAILQ_INIT(&sc->sc_memwindow); 413 TAILQ_INIT(&sc->sc_iowindow); 414 415 #if rbus 416 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 417 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 418 419 #if 0 420 printf("pa->pa_memt: %08x vs rbus_mem->rb_bt: %08x\n", 421 pa->pa_memt, sc->sc_rbus_memt->rb_bt); 422 #endif 423 #endif /* rbus */ 424 425 sc->sc_flags &= ~CBB_MEMHMAPPED; 426 427 /* 428 * MAP socket registers and ExCA registers on memory-space 429 * When no valid address is set on socket base registers (on pci 430 * config space), get it not polite way. 431 */ 432 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 433 434 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 435 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 436 /* The address must be valid. */ 437 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 438 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, &sc->sc_base_size)) { 439 aprint_error("%s: can't map socket base address 0x%lx\n", 440 sc->sc_dev.dv_xname, (unsigned long)sock_base); 441 /* 442 * I think it's funny: socket base registers must be 443 * mapped on memory space, but ... 444 */ 445 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 446 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 447 &sc->sc_base_size)) { 448 aprint_error("%s: can't map socket base address" 449 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 450 (unsigned long)sockbase); 451 /* give up... allocate reg space via rbus. */ 452 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 453 } else 454 sc->sc_flags |= CBB_MEMHMAPPED; 455 } else { 456 DPRINTF(("%s: socket base address 0x%lx\n", 457 sc->sc_dev.dv_xname, (unsigned long)sockbase)); 458 sc->sc_flags |= CBB_MEMHMAPPED; 459 } 460 } 461 462 sc->sc_mem_start = 0; /* XXX */ 463 sc->sc_mem_end = 0xffffffff; /* XXX */ 464 465 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 466 467 /* pccbb_machdep.c end */ 468 469 #if defined CBB_DEBUG 470 { 471 static const char *intrname[] = { "NON", "A", "B", "C", "D" }; 472 printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname, 473 intrname[pa->pa_intrpin], pa->pa_intrline); 474 } 475 #endif 476 477 /* setup softc */ 478 sc->sc_pc = pc; 479 sc->sc_iot = pa->pa_iot; 480 sc->sc_memt = pa->pa_memt; 481 sc->sc_dmat = pa->pa_dmat; 482 sc->sc_tag = pa->pa_tag; 483 sc->sc_function = pa->pa_function; 484 485 memcpy(&sc->sc_pa, pa, sizeof(*pa)); 486 487 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 488 489 /* Disable legacy register mapping. */ 490 switch (sc->sc_chipset) { 491 case CB_RX5C46X: /* fallthrough */ 492 #if 0 493 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 494 case CB_RX5C47X: 495 #endif 496 /* 497 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 498 * cannot be disabled by substituting 0 into PCI_LEGACY 499 * register. Ricoh CardBus bridges have special bits on Bridge 500 * control reg (addr 0x3e on PCI config space). 501 */ 502 reg = pci_conf_read(pc, pa->pa_tag, PCI_BRIDGE_CONTROL_REG); 503 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 504 pci_conf_write(pc, pa->pa_tag, PCI_BRIDGE_CONTROL_REG, reg); 505 break; 506 507 default: 508 /* XXX I don't know proper way to kill legacy I/O. */ 509 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 510 break; 511 } 512 513 if (!pmf_device_register(self, pccbb_suspend, pccbb_resume)) 514 aprint_error_dev(self, "couldn't establish power handler\n"); 515 516 config_defer(self, pccbb_pci_callback); 517 } 518 519 int 520 pccbbdetach(device_t self, int flags) 521 { 522 struct pccbb_softc *sc = device_private(self); 523 pci_chipset_tag_t pc = sc->sc_pa.pa_pc; 524 bus_space_tag_t bmt = sc->sc_base_memt; 525 bus_space_handle_t bmh = sc->sc_base_memh; 526 uint32_t sockmask; 527 int rc; 528 529 if ((rc = config_detach_children(self, flags)) != 0) 530 return rc; 531 532 if (sc->sc_ih != NULL) { 533 pci_intr_disestablish(pc, sc->sc_ih); 534 sc->sc_ih = NULL; 535 } 536 537 /* CSC Interrupt: turn off card detect and power cycle interrupts */ 538 sockmask = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 539 sockmask &= ~(CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER); 540 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, sockmask); 541 /* reset interrupt */ 542 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 543 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 544 545 switch (sc->sc_flags & (CBB_MEMHMAPPED|CBB_SPECMAPPED)) { 546 case CBB_MEMHMAPPED: 547 bus_space_unmap(bmt, bmh, sc->sc_base_size); 548 break; 549 case CBB_MEMHMAPPED|CBB_SPECMAPPED: 550 #if rbus 551 { 552 pcireg_t sockbase; 553 554 sockbase = pci_conf_read(pc, sc->sc_tag, PCI_SOCKBASE); 555 rbus_space_free(sc->sc_rbus_memt, bmh, 0x1000, 556 NULL); 557 } 558 #else 559 bus_space_free(bmt, bmh, 0x1000); 560 #endif 561 } 562 sc->sc_flags &= ~(CBB_MEMHMAPPED|CBB_SPECMAPPED); 563 564 if (!TAILQ_EMPTY(&sc->sc_iowindow)) 565 aprint_error_dev(self, "i/o windows not empty"); 566 if (!TAILQ_EMPTY(&sc->sc_memwindow)) 567 aprint_error_dev(self, "memory windows not empty"); 568 569 callout_stop(&sc->sc_insert_ch); 570 callout_destroy(&sc->sc_insert_ch); 571 return 0; 572 } 573 574 /* 575 * static void pccbb_pci_callback(struct device *self) 576 * 577 * The actual attach routine: get memory space for YENTA register 578 * space, setup YENTA register and route interrupt. 579 * 580 * This function should be deferred because this device may obtain 581 * memory space dynamically. This function must avoid obtaining 582 * memory area which has already kept for another device. 583 */ 584 static void 585 pccbb_pci_callback(struct device *self) 586 { 587 struct pccbb_softc *sc = (void *)self; 588 pci_chipset_tag_t pc = sc->sc_pc; 589 pci_intr_handle_t ih; 590 const char *intrstr = NULL; 591 bus_addr_t sockbase; 592 struct cbslot_attach_args cba; 593 struct pcmciabus_attach_args paa; 594 struct cardslot_attach_args caa; 595 struct cardslot_softc *csc; 596 597 if (!(sc->sc_flags & CBB_MEMHMAPPED)) { 598 /* The socket registers aren't mapped correctly. */ 599 #if rbus 600 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 601 (sc->sc_chipset == CB_RX5C47X 602 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 603 0, &sockbase, &sc->sc_base_memh)) { 604 return; 605 } 606 sc->sc_base_memt = sc->sc_memt; 607 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 608 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 609 sc->sc_dev.dv_xname, (unsigned long)sockbase, 610 (unsigned long)pci_conf_read(pc, sc->sc_tag, 611 PCI_SOCKBASE))); 612 #else 613 sc->sc_base_memt = sc->sc_memt; 614 #if !defined CBB_PCI_BASE 615 #define CBB_PCI_BASE 0x20000000 616 #endif 617 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 618 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 619 /* cannot allocate memory space */ 620 return; 621 } 622 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 623 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 624 sc->sc_dev.dv_xname, (unsigned long)sock_base, 625 (unsigned long)pci_conf_read(pc, 626 sc->sc_tag, PCI_SOCKBASE))); 627 #endif 628 sc->sc_flags |= CBB_MEMHMAPPED; 629 } 630 631 /* bus bridge initialization */ 632 pccbb_chipinit(sc); 633 634 /* clear data structure for child device interrupt handlers */ 635 LIST_INIT(&sc->sc_pil); 636 sc->sc_pil_intr_enable = 1; 637 638 /* Map and establish the interrupt. */ 639 if (pci_intr_map(&sc->sc_pa, &ih)) { 640 aprint_error("%s: couldn't map interrupt\n", 641 sc->sc_dev.dv_xname); 642 return; 643 } 644 intrstr = pci_intr_string(pc, ih); 645 646 /* 647 * XXX pccbbintr should be called under the priority lower 648 * than any other hard interupts. 649 */ 650 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 651 652 if (sc->sc_ih == NULL) { 653 aprint_error("%s: couldn't establish interrupt", 654 sc->sc_dev.dv_xname); 655 if (intrstr != NULL) { 656 aprint_normal(" at %s", intrstr); 657 } 658 aprint_normal("\n"); 659 return; 660 } 661 662 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 663 664 { 665 u_int32_t sockstat; 666 667 sockstat = bus_space_read_4(sc->sc_base_memt, 668 sc->sc_base_memh, CB_SOCKET_STAT); 669 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 670 sc->sc_flags |= CBB_CARDEXIST; 671 } 672 } 673 674 /* 675 * attach cardbus 676 */ 677 { 678 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 679 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 680 681 /* initialize cbslot_attach */ 682 cba.cba_busname = "cardbus"; 683 cba.cba_iot = sc->sc_iot; 684 cba.cba_memt = sc->sc_memt; 685 cba.cba_dmat = sc->sc_dmat; 686 cba.cba_bus = (busreg >> 8) & 0x0ff; 687 cba.cba_cc = (void *)sc; 688 cba.cba_cf = &pccbb_funcs; 689 cba.cba_intrline = sc->sc_pa.pa_intrline; 690 691 #if rbus 692 cba.cba_rbus_iot = sc->sc_rbus_iot; 693 cba.cba_rbus_memt = sc->sc_rbus_memt; 694 #endif 695 696 cba.cba_cacheline = PCI_CACHELINE(bhlc); 697 cba.cba_max_lattimer = PCI_LATTIMER(bhlc); 698 699 if (bootverbose) { 700 printf("%s: cacheline 0x%x lattimer 0x%x\n", 701 sc->sc_dev.dv_xname, cba.cba_cacheline, 702 cba.cba_max_lattimer); 703 printf("%s: bhlc 0x%x\n", 704 device_xname(&sc->sc_dev), bhlc); 705 } 706 #if defined SHOW_REGS 707 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 708 sc->sc_base_memh); 709 #endif 710 } 711 712 pccbb_pcmcia_attach_setup(sc, &paa); 713 caa.caa_cb_attach = NULL; 714 if (cba.cba_bus == 0) 715 printf("%s: secondary bus number uninitialized; try PCI_BUS_FIXUP\n", sc->sc_dev.dv_xname); 716 else 717 caa.caa_cb_attach = &cba; 718 caa.caa_16_attach = &paa; 719 caa.caa_ph = &sc->sc_pcmcia_h; 720 721 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 722 DPRINTF(("%s: found cardslot\n", __func__)); 723 sc->sc_csc = csc; 724 } 725 726 return; 727 } 728 729 730 731 732 733 /* 734 * static void pccbb_chipinit(struct pccbb_softc *sc) 735 * 736 * This function initialize YENTA chip registers listed below: 737 * 1) PCI command reg, 738 * 2) PCI and CardBus latency timer, 739 * 3) route PCI interrupt, 740 * 4) close all memory and io windows. 741 * 5) turn off bus power. 742 * 6) card detect and power cycle interrupts on. 743 * 7) clear interrupt 744 */ 745 static void 746 pccbb_chipinit(struct pccbb_softc *sc) 747 { 748 pci_chipset_tag_t pc = sc->sc_pc; 749 pcitag_t tag = sc->sc_tag; 750 bus_space_tag_t bmt = sc->sc_base_memt; 751 bus_space_handle_t bmh = sc->sc_base_memh; 752 pcireg_t bcr, bhlc, cbctl, csr, lscp, mfunc, mrburst, slotctl, sockctl, 753 sockmask, sysctrl; 754 755 /* 756 * Set PCI command reg. 757 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 758 */ 759 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 760 /* I believe it is harmless. */ 761 csr |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 762 PCI_COMMAND_MASTER_ENABLE); 763 csr |= (PCI_COMMAND_PARITY_ENABLE|PCI_COMMAND_SERR_ENABLE); 764 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 765 766 /* 767 * Set CardBus latency timer. 768 */ 769 lscp = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 770 if (PCI_CB_LATENCY(lscp) < 0x20) { 771 lscp &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 772 lscp |= (0x20 << PCI_CB_LATENCY_SHIFT); 773 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, lscp); 774 } 775 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 776 PCI_CB_LATENCY(lscp), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 777 778 /* 779 * Set PCI latency timer. 780 */ 781 bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG); 782 if (PCI_LATTIMER(bhlc) < 0x10) { 783 bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 784 bhlc |= (0x10 << PCI_LATTIMER_SHIFT); 785 pci_conf_write(pc, tag, PCI_BHLC_REG, bhlc); 786 } 787 DPRINTF(("PCI latency timer 0x%x (%x)\n", 788 PCI_LATTIMER(bhlc), pci_conf_read(pc, tag, PCI_BHLC_REG))); 789 790 791 /* Route functional interrupts to PCI. */ 792 bcr = pci_conf_read(pc, tag, PCI_BRIDGE_CONTROL_REG); 793 bcr |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 794 bcr |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 795 /* assert reset */ 796 bcr |= PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT; 797 /* Set master abort mode to 1, forward SERR# from secondary 798 * to primary, and detect parity errors on secondary. 799 */ 800 bcr |= PCI_BRIDGE_CONTROL_MABRT << PCI_BRIDGE_CONTROL_SHIFT; 801 bcr |= PCI_BRIDGE_CONTROL_SERR << PCI_BRIDGE_CONTROL_SHIFT; 802 bcr |= PCI_BRIDGE_CONTROL_PERE << PCI_BRIDGE_CONTROL_SHIFT; 803 pci_conf_write(pc, tag, PCI_BRIDGE_CONTROL_REG, bcr); 804 805 switch (sc->sc_chipset) { 806 case CB_TI113X: 807 cbctl = pci_conf_read(pc, tag, PCI_CBCTRL); 808 /* This bit is shared, but may read as 0 on some chips, so set 809 it explicitly on both functions. */ 810 cbctl |= PCI113X_CBCTRL_PCI_IRQ_ENA; 811 /* CSC intr enable */ 812 cbctl |= PCI113X_CBCTRL_PCI_CSC; 813 /* functional intr prohibit | prohibit ISA routing */ 814 cbctl &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 815 pci_conf_write(pc, tag, PCI_CBCTRL, cbctl); 816 break; 817 818 case CB_TI1420: 819 sysctrl = pci_conf_read(pc, tag, PCI_SYSCTRL); 820 mrburst = pccbb_burstup 821 ? PCI1420_SYSCTRL_MRBURST : PCI1420_SYSCTRL_MRBURSTDN; 822 if ((sysctrl & PCI1420_SYSCTRL_MRBURST) == mrburst) { 823 printf("%s: %swrite bursts enabled\n", 824 device_xname(&sc->sc_dev), 825 pccbb_burstup ? "read/" : ""); 826 } else if (pccbb_burstup) { 827 printf("%s: enabling read/write bursts\n", 828 device_xname(&sc->sc_dev)); 829 sysctrl |= PCI1420_SYSCTRL_MRBURST; 830 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 831 } else { 832 printf("%s: disabling read bursts, " 833 "enabling write bursts\n", 834 device_xname(&sc->sc_dev)); 835 sysctrl |= PCI1420_SYSCTRL_MRBURSTDN; 836 sysctrl &= ~PCI1420_SYSCTRL_MRBURSTUP; 837 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 838 } 839 /*FALLTHROUGH*/ 840 case CB_TI12XX: 841 /* 842 * Some TI 12xx (and [14][45]xx) based pci cards 843 * sometimes have issues with the MFUNC register not 844 * being initialized due to a bad EEPROM on board. 845 * Laptops that this matters on have this register 846 * properly initialized. 847 * 848 * The TI125X parts have a different register. 849 */ 850 mfunc = pci_conf_read(pc, tag, PCI12XX_MFUNC); 851 if (mfunc == 0) { 852 mfunc &= ~PCI12XX_MFUNC_PIN0; 853 mfunc |= PCI12XX_MFUNC_PIN0_INTA; 854 if ((pci_conf_read(pc, tag, PCI_SYSCTRL) & 855 PCI12XX_SYSCTRL_INTRTIE) == 0) { 856 mfunc &= ~PCI12XX_MFUNC_PIN1; 857 mfunc |= PCI12XX_MFUNC_PIN1_INTB; 858 } 859 pci_conf_write(pc, tag, PCI12XX_MFUNC, mfunc); 860 } 861 /* fallthrough */ 862 863 case CB_TI125X: 864 /* 865 * Disable zoom video. Some machines initialize this 866 * improperly and experience has shown that this helps 867 * prevent strange behavior. 868 */ 869 pci_conf_write(pc, tag, PCI12XX_MMCTRL, 0); 870 871 sysctrl = pci_conf_read(pc, tag, PCI_SYSCTRL); 872 sysctrl |= PCI12XX_SYSCTRL_VCCPROT; 873 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 874 cbctl = pci_conf_read(pc, tag, PCI_CBCTRL); 875 cbctl |= PCI12XX_CBCTRL_CSC; 876 pci_conf_write(pc, tag, PCI_CBCTRL, cbctl); 877 break; 878 879 case CB_TOPIC95B: 880 sockctl = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 881 sockctl |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 882 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, sockctl); 883 slotctl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 884 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 885 sc->sc_dev.dv_xname, slotctl)); 886 slotctl |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 887 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 888 slotctl &= ~TOPIC_SLOT_CTRL_SWDETECT; 889 DPRINTF(("0x%x\n", slotctl)); 890 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slotctl); 891 break; 892 893 case CB_TOPIC97: 894 slotctl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 895 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 896 sc->sc_dev.dv_xname, slotctl)); 897 slotctl |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 898 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 899 slotctl &= ~TOPIC_SLOT_CTRL_SWDETECT; 900 slotctl |= TOPIC97_SLOT_CTRL_PCIINT; 901 slotctl &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 902 DPRINTF(("0x%x\n", slotctl)); 903 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slotctl); 904 /* make sure to assert LV card support bits */ 905 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 906 0x800 + 0x3e, 907 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 908 0x800 + 0x3e) | 0x03); 909 break; 910 } 911 912 /* Close all memory and I/O windows. */ 913 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 914 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 915 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 916 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 917 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 918 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 919 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 920 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 921 922 /* reset 16-bit pcmcia bus */ 923 bus_space_write_1(bmt, bmh, 0x800 + PCIC_INTR, 924 bus_space_read_1(bmt, bmh, 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 925 926 /* turn off power */ 927 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 928 929 /* CSC Interrupt: Card detect and power cycle interrupts on */ 930 sockmask = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 931 sockmask |= CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; 932 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, sockmask); 933 /* reset interrupt */ 934 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 935 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 936 } 937 938 939 940 941 /* 942 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 943 * struct pcmciabus_attach_args *paa) 944 * 945 * This function attaches 16-bit PCcard bus. 946 */ 947 STATIC void 948 pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 949 struct pcmciabus_attach_args *paa) 950 { 951 struct pcic_handle *ph = &sc->sc_pcmcia_h; 952 #if rbus 953 rbus_tag_t rb; 954 #endif 955 956 /* initialize pcmcia part in pccbb_softc */ 957 ph->ph_parent = (struct device *)sc; 958 ph->sock = sc->sc_function; 959 ph->flags = 0; 960 ph->shutdown = 0; 961 ph->ih_irq = sc->sc_pa.pa_intrline; 962 ph->ph_bus_t = sc->sc_base_memt; 963 ph->ph_bus_h = sc->sc_base_memh; 964 ph->ph_read = pccbb_pcmcia_read; 965 ph->ph_write = pccbb_pcmcia_write; 966 sc->sc_pct = &pccbb_pcmcia_funcs; 967 968 /* 969 * We need to do a few things here: 970 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 971 * setting the IRQ numbers to 0. 972 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 973 * routing of CSC interrupts (e.g. card removal) to PCI while in 974 * PCMCIA mode. We just leave this set all the time. 975 * 3) Enable card insertion/removal interrupts in case the chip also 976 * needs that while in PCMCIA mode. 977 * 4) Clear any pending CSC interrupt. 978 */ 979 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE); 980 if (sc->sc_chipset == CB_TI113X) { 981 Pcic_write(ph, PCIC_CSC_INTR, 0); 982 } else { 983 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 984 Pcic_read(ph, PCIC_CSC); 985 } 986 987 /* initialize pcmcia bus attachment */ 988 paa->paa_busname = "pcmcia"; 989 paa->pct = sc->sc_pct; 990 paa->pch = ph; 991 paa->iobase = 0; /* I don't use them */ 992 paa->iosize = 0; 993 #if rbus 994 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 995 paa->iobase = rb->rb_start + rb->rb_offset; 996 paa->iosize = rb->rb_end - rb->rb_start; 997 #endif 998 999 return; 1000 } 1001 1002 #if 0 1003 STATIC void 1004 pccbb_pcmcia_attach_card(struct pcic_handle *ph) 1005 { 1006 if (ph->flags & PCIC_FLAG_CARDP) { 1007 panic("pccbb_pcmcia_attach_card: already attached"); 1008 } 1009 1010 /* call the MI attach function */ 1011 pcmcia_card_attach(ph->pcmcia); 1012 1013 ph->flags |= PCIC_FLAG_CARDP; 1014 } 1015 1016 STATIC void 1017 pccbb_pcmcia_detach_card(struct pcic_handle *ph, int flags) 1018 { 1019 if (!(ph->flags & PCIC_FLAG_CARDP)) { 1020 panic("pccbb_pcmcia_detach_card: already detached"); 1021 } 1022 1023 ph->flags &= ~PCIC_FLAG_CARDP; 1024 1025 /* call the MI detach function */ 1026 pcmcia_card_detach(ph->pcmcia, flags); 1027 } 1028 #endif 1029 1030 /* 1031 * int pccbbintr(arg) 1032 * void *arg; 1033 * This routine handles the interrupt from Yenta PCI-CardBus bridge 1034 * itself. 1035 */ 1036 int 1037 pccbbintr(void *arg) 1038 { 1039 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1040 u_int32_t sockevent, sockstate; 1041 bus_space_tag_t memt = sc->sc_base_memt; 1042 bus_space_handle_t memh = sc->sc_base_memh; 1043 struct pcic_handle *ph = &sc->sc_pcmcia_h; 1044 1045 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 1046 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 1047 Pcic_read(ph, PCIC_CSC); 1048 1049 if (sockevent != 0) { 1050 aprint_debug("%s: enter sockevent %" PRIx32 "\n", __func__, 1051 sockevent); 1052 } 1053 1054 /* Sometimes a change of CSTSCHG# accompanies the first 1055 * interrupt from an Atheros WLAN. That generates a 1056 * CB_SOCKET_EVENT_CSTS event on the bridge. The event 1057 * isn't interesting to pccbb(4), so we used to ignore the 1058 * interrupt. Now, let the child devices try to handle 1059 * the interrupt, instead. The Atheros NIC produces 1060 * interrupts more reliably, now: used to be that it would 1061 * only interrupt if the driver avoided powering down the 1062 * NIC's cardslot, and then the NIC would only work after 1063 * it was reset a second time. 1064 */ 1065 if (sockevent == 0 || 1066 (sockevent & ~(CB_SOCKET_EVENT_POWER|CB_SOCKET_EVENT_CD)) != 0) { 1067 /* This intr is not for me: it may be for my child devices. */ 1068 if (sc->sc_pil_intr_enable) { 1069 return pccbbintr_function(sc); 1070 } else { 1071 return 0; 1072 } 1073 } 1074 1075 if (sockevent & CB_SOCKET_EVENT_CD) { 1076 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1077 if (0x00 != (sockstate & CB_SOCKET_STAT_CD)) { 1078 /* A card should be removed. */ 1079 if (sc->sc_flags & CBB_CARDEXIST) { 1080 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 1081 sockevent)); 1082 DPRINTF((" card removed, 0x%08x\n", sockstate)); 1083 sc->sc_flags &= ~CBB_CARDEXIST; 1084 if (sc->sc_csc->sc_status & 1085 CARDSLOT_STATUS_CARD_16) { 1086 #if 0 1087 struct pcic_handle *ph = 1088 &sc->sc_pcmcia_h; 1089 1090 pcmcia_card_deactivate(ph->pcmcia); 1091 pccbb_pcmcia_socket_disable(ph); 1092 pccbb_pcmcia_detach_card(ph, 1093 DETACH_FORCE); 1094 #endif 1095 cardslot_event_throw(sc->sc_csc, 1096 CARDSLOT_EVENT_REMOVAL_16); 1097 } else if (sc->sc_csc->sc_status & 1098 CARDSLOT_STATUS_CARD_CB) { 1099 /* Cardbus intr removed */ 1100 cardslot_event_throw(sc->sc_csc, 1101 CARDSLOT_EVENT_REMOVAL_CB); 1102 } 1103 } else if (sc->sc_flags & CBB_INSERTING) { 1104 sc->sc_flags &= ~CBB_INSERTING; 1105 callout_stop(&sc->sc_insert_ch); 1106 } 1107 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 1108 /* 1109 * The pccbbintr may called from powerdown hook when 1110 * the system resumed, to detect the card 1111 * insertion/removal during suspension. 1112 */ 1113 (sc->sc_flags & CBB_CARDEXIST) == 0) { 1114 if (sc->sc_flags & CBB_INSERTING) { 1115 callout_stop(&sc->sc_insert_ch); 1116 } 1117 callout_schedule(&sc->sc_insert_ch, hz / 5); 1118 sc->sc_flags |= CBB_INSERTING; 1119 } 1120 } 1121 1122 /* XXX sockevent == 9 does occur in the wild. handle it. */ 1123 if (sockevent & CB_SOCKET_EVENT_POWER) { 1124 DPRINTF(("Powercycling because of socket event\n")); 1125 /* XXX: Does not happen when attaching a 16-bit card */ 1126 sc->sc_pwrcycle++; 1127 wakeup(&sc->sc_pwrcycle); 1128 } 1129 1130 return (1); 1131 } 1132 1133 /* 1134 * static int pccbbintr_function(struct pccbb_softc *sc) 1135 * 1136 * This function calls each interrupt handler registered at the 1137 * bridge. The interrupt handlers are called in registered order. 1138 */ 1139 static int 1140 pccbbintr_function(struct pccbb_softc *sc) 1141 { 1142 int retval = 0, val; 1143 struct pccbb_intrhand_list *pil; 1144 int s; 1145 1146 LIST_FOREACH(pil, &sc->sc_pil, pil_next) { 1147 s = splraiseipl(pil->pil_icookie); 1148 val = (*pil->pil_func)(pil->pil_arg); 1149 splx(s); 1150 1151 retval = retval == 1 ? 1 : 1152 retval == 0 ? val : val != 0 ? val : retval; 1153 } 1154 1155 return retval; 1156 } 1157 1158 static void 1159 pci113x_insert(void *arg) 1160 { 1161 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1162 u_int32_t sockevent, sockstate; 1163 1164 if (!(sc->sc_flags & CBB_INSERTING)) { 1165 /* We add a card only under inserting state. */ 1166 return; 1167 } 1168 sc->sc_flags &= ~CBB_INSERTING; 1169 1170 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1171 CB_SOCKET_EVENT); 1172 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1173 CB_SOCKET_STAT); 1174 1175 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1176 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1177 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1178 sc->sc_flags |= CBB_CARDEXIST; 1179 /* call pccard interrupt handler here */ 1180 if (sockstate & CB_SOCKET_STAT_16BIT) { 1181 /* 16-bit card found */ 1182 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1183 cardslot_event_throw(sc->sc_csc, 1184 CARDSLOT_EVENT_INSERTION_16); 1185 } else if (sockstate & CB_SOCKET_STAT_CB) { 1186 /* cardbus card found */ 1187 /* cardbus_attach_card(sc->sc_csc); */ 1188 cardslot_event_throw(sc->sc_csc, 1189 CARDSLOT_EVENT_INSERTION_CB); 1190 } else { 1191 /* who are you? */ 1192 } 1193 } else { 1194 callout_schedule(&sc->sc_insert_ch, hz / 10); 1195 } 1196 } 1197 1198 #define PCCBB_PCMCIA_OFFSET 0x800 1199 static u_int8_t 1200 pccbb_pcmcia_read(struct pcic_handle *ph, int reg) 1201 { 1202 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1203 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1204 1205 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1206 PCCBB_PCMCIA_OFFSET + reg); 1207 } 1208 1209 static void 1210 pccbb_pcmcia_write(struct pcic_handle *ph, int reg, u_int8_t val) 1211 { 1212 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1213 val); 1214 1215 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1216 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1217 } 1218 1219 /* 1220 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1221 */ 1222 STATIC int 1223 pccbb_ctrl(cardbus_chipset_tag_t ct, int command) 1224 { 1225 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1226 1227 switch (command) { 1228 case CARDBUS_CD: 1229 if (2 == pccbb_detect_card(sc)) { 1230 int retval = 0; 1231 int status = cb_detect_voltage(sc); 1232 if (PCCARD_VCC_5V & status) { 1233 retval |= CARDBUS_5V_CARD; 1234 } 1235 if (PCCARD_VCC_3V & status) { 1236 retval |= CARDBUS_3V_CARD; 1237 } 1238 if (PCCARD_VCC_XV & status) { 1239 retval |= CARDBUS_XV_CARD; 1240 } 1241 if (PCCARD_VCC_YV & status) { 1242 retval |= CARDBUS_YV_CARD; 1243 } 1244 return retval; 1245 } else { 1246 return 0; 1247 } 1248 case CARDBUS_RESET: 1249 return cb_reset(sc); 1250 case CARDBUS_IO_ENABLE: /* fallthrough */ 1251 case CARDBUS_IO_DISABLE: /* fallthrough */ 1252 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1253 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1254 case CARDBUS_BM_ENABLE: /* fallthrough */ 1255 case CARDBUS_BM_DISABLE: /* fallthrough */ 1256 /* XXX: I think we don't need to call this function below. */ 1257 return pccbb_cardenable(sc, command); 1258 } 1259 1260 return 0; 1261 } 1262 1263 /* 1264 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1265 * This function returns true when it succeeds and returns false when 1266 * it fails. 1267 */ 1268 STATIC int 1269 pccbb_power(cardbus_chipset_tag_t ct, int command) 1270 { 1271 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1272 u_int32_t status, osock_ctrl, sock_ctrl, reg_ctrl; 1273 bus_space_tag_t memt = sc->sc_base_memt; 1274 bus_space_handle_t memh = sc->sc_base_memh; 1275 int on = 0, pwrcycle, s, times; 1276 struct timeval before, after, diff; 1277 1278 DPRINTF(("pccbb_power: %s and %s [0x%x]\n", 1279 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1280 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1281 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1282 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1283 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1284 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1285 "UNKNOWN", 1286 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1287 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1288 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1289 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1290 "UNKNOWN", command)); 1291 1292 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1293 osock_ctrl = sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1294 1295 switch (command & CARDBUS_VCCMASK) { 1296 case CARDBUS_VCC_UC: 1297 break; 1298 case CARDBUS_VCC_5V: 1299 on++; 1300 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1301 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1302 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1303 } else { 1304 printf("%s: BAD voltage request: no 5 V card\n", 1305 sc->sc_dev.dv_xname); 1306 return 0; 1307 } 1308 break; 1309 case CARDBUS_VCC_3V: 1310 on++; 1311 if (CB_SOCKET_STAT_3VCARD & status) { 1312 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1313 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1314 } else { 1315 printf("%s: BAD voltage request: no 3.3 V card\n", 1316 sc->sc_dev.dv_xname); 1317 return 0; 1318 } 1319 break; 1320 case CARDBUS_VCC_0V: 1321 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1322 break; 1323 default: 1324 return 0; /* power NEVER changed */ 1325 } 1326 1327 switch (command & CARDBUS_VPPMASK) { 1328 case CARDBUS_VPP_UC: 1329 break; 1330 case CARDBUS_VPP_0V: 1331 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1332 break; 1333 case CARDBUS_VPP_VCC: 1334 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1335 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1336 break; 1337 case CARDBUS_VPP_12V: 1338 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1339 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1340 break; 1341 } 1342 1343 pwrcycle = sc->sc_pwrcycle; 1344 aprint_debug("%s: osock_ctrl %#" PRIx32 " sock_ctrl %#" PRIx32 "\n", 1345 device_xname(&sc->sc_dev), osock_ctrl, sock_ctrl); 1346 1347 microtime(&before); 1348 s = splbio(); 1349 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1350 1351 /* 1352 * Wait as long as 200ms for a power-cycle interrupt. If 1353 * interrupts are enabled, but the socket has already 1354 * changed to the desired status, keep waiting for the 1355 * interrupt. "Consuming" the interrupt in this way keeps 1356 * the interrupt from prematurely waking some subsequent 1357 * pccbb_power call. 1358 * 1359 * XXX Not every bridge interrupts on the ->OFF transition. 1360 * XXX That's ok, we will time-out after 200ms. 1361 * 1362 * XXX The power cycle event will never happen when attaching 1363 * XXX a 16-bit card. That's ok, we will time-out after 1364 * XXX 200ms. 1365 */ 1366 for (times = 5; --times >= 0; ) { 1367 if (cold) 1368 DELAY(40 * 1000); 1369 else { 1370 (void)tsleep(&sc->sc_pwrcycle, PWAIT, "pccpwr", 1371 hz / 25); 1372 if (pwrcycle == sc->sc_pwrcycle) 1373 continue; 1374 } 1375 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1376 if ((status & CB_SOCKET_STAT_PWRCYCLE) != 0 && on) 1377 break; 1378 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0 && !on) 1379 break; 1380 } 1381 splx(s); 1382 microtime(&after); 1383 timersub(&after, &before, &diff); 1384 aprint_debug("%s: wait took%s %ld.%06lds\n", sc->sc_dev.dv_xname, 1385 (on && times < 0) ? " too long" : "", diff.tv_sec, diff.tv_usec); 1386 1387 /* 1388 * Ok, wait a bit longer for things to settle. 1389 */ 1390 if (on && sc->sc_chipset == CB_TOPIC95B) 1391 delay_ms(100, sc); 1392 1393 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1394 1395 if (on && sc->sc_chipset != CB_TOPIC95B) { 1396 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0) 1397 printf("%s: power on failed?\n", sc->sc_dev.dv_xname); 1398 } 1399 1400 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1401 printf("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1402 sc->sc_dev.dv_xname, sock_ctrl, status); 1403 printf("%s: disabling socket\n", sc->sc_dev.dv_xname); 1404 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1405 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1406 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1407 status &= ~CB_SOCKET_STAT_BADVCC; 1408 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, status); 1409 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1410 CB_SOCKET_STAT)); 1411 return 0; 1412 } 1413 1414 if (sc->sc_chipset == CB_TOPIC97) { 1415 reg_ctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL); 1416 reg_ctrl &= ~TOPIC97_REG_CTRL_TESTMODE; 1417 if ((command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V) 1418 reg_ctrl &= ~TOPIC97_REG_CTRL_CLKRUN_ENA; 1419 else 1420 reg_ctrl |= TOPIC97_REG_CTRL_CLKRUN_ENA; 1421 pci_conf_write(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL, reg_ctrl); 1422 } 1423 1424 return 1; /* power changed correctly */ 1425 } 1426 1427 #if defined CB_PCMCIA_POLL 1428 struct cb_poll_str { 1429 void *arg; 1430 int (*func)(void *); 1431 int level; 1432 pccard_chipset_tag_t ct; 1433 int count; 1434 struct callout poll_ch; 1435 }; 1436 1437 static struct cb_poll_str cb_poll[10]; 1438 static int cb_poll_n = 0; 1439 1440 static void cb_pcmcia_poll(void *arg); 1441 1442 static void 1443 cb_pcmcia_poll(void *arg) 1444 { 1445 struct cb_poll_str *poll = arg; 1446 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1447 struct pccbb_softc *sc = psc->cpc_parent; 1448 int s; 1449 u_int32_t spsr; /* socket present-state reg */ 1450 1451 callout_reset(&poll->poll_ch, hz / 10, cb_pcmcia_poll, poll); 1452 switch (poll->level) { 1453 case IPL_NET: 1454 s = splnet(); 1455 break; 1456 case IPL_BIO: 1457 s = splbio(); 1458 break; 1459 case IPL_TTY: /* fallthrough */ 1460 default: 1461 s = spltty(); 1462 break; 1463 } 1464 1465 spsr = 1466 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1467 CB_SOCKET_STAT); 1468 1469 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1470 if (!(spsr & 0x40)) { /* CINT low */ 1471 #else 1472 if (1) { 1473 #endif 1474 if ((*poll->func) (poll->arg) == 1) { 1475 ++poll->count; 1476 printf("intr: reported from poller, 0x%x\n", spsr); 1477 #if defined LEVEL2 1478 } else { 1479 printf("intr: miss! 0x%x\n", spsr); 1480 #endif 1481 } 1482 } 1483 splx(s); 1484 } 1485 #endif /* defined CB_PCMCIA_POLL */ 1486 1487 /* 1488 * static int pccbb_detect_card(struct pccbb_softc *sc) 1489 * return value: 0 if no card exists. 1490 * 1 if 16-bit card exists. 1491 * 2 if cardbus card exists. 1492 */ 1493 static int 1494 pccbb_detect_card(struct pccbb_softc *sc) 1495 { 1496 bus_space_handle_t base_memh = sc->sc_base_memh; 1497 bus_space_tag_t base_memt = sc->sc_base_memt; 1498 u_int32_t sockstat = 1499 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1500 int retval = 0; 1501 1502 /* CD1 and CD2 asserted */ 1503 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1504 /* card must be present */ 1505 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1506 /* NOTACARD DEASSERTED */ 1507 if (CB_SOCKET_STAT_CB & sockstat) { 1508 /* CardBus mode */ 1509 retval = 2; 1510 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1511 /* 16-bit mode */ 1512 retval = 1; 1513 } 1514 } 1515 } 1516 return retval; 1517 } 1518 1519 /* 1520 * STATIC int cb_reset(struct pccbb_softc *sc) 1521 * This function resets CardBus card. 1522 */ 1523 STATIC int 1524 cb_reset(struct pccbb_softc *sc) 1525 { 1526 /* 1527 * Reset Assert at least 20 ms 1528 * Some machines request longer duration. 1529 */ 1530 int reset_duration = 1531 (sc->sc_chipset == CB_RX5C47X ? 400 : 50); 1532 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1533 aprint_debug("%s: enter bcr %" PRIx32 "\n", __func__, bcr); 1534 1535 /* Reset bit Assert (bit 6 at 0x3E) */ 1536 bcr |= PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT; 1537 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr); 1538 aprint_debug("%s: wrote bcr %" PRIx32 "\n", __func__, bcr); 1539 delay_ms(reset_duration, sc); 1540 1541 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1542 /* Reset bit Deassert (bit 6 at 0x3E) */ 1543 bcr &= ~(PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT); 1544 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, 1545 bcr); 1546 aprint_debug("%s: wrote bcr %" PRIx32 "\n", __func__, bcr); 1547 delay_ms(reset_duration, sc); 1548 aprint_debug("%s: end of delay\n", __func__); 1549 } 1550 /* No card found on the slot. Keep Reset. */ 1551 return 1; 1552 } 1553 1554 /* 1555 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1556 * This function detect card Voltage. 1557 */ 1558 STATIC int 1559 cb_detect_voltage(struct pccbb_softc *sc) 1560 { 1561 u_int32_t psr; /* socket present-state reg */ 1562 bus_space_tag_t iot = sc->sc_base_memt; 1563 bus_space_handle_t ioh = sc->sc_base_memh; 1564 int vol = PCCARD_VCC_UKN; /* set 0 */ 1565 1566 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1567 1568 if (0x400u & psr) { 1569 vol |= PCCARD_VCC_5V; 1570 } 1571 if (0x800u & psr) { 1572 vol |= PCCARD_VCC_3V; 1573 } 1574 1575 return vol; 1576 } 1577 1578 STATIC int 1579 cbbprint(void *aux, const char *pcic) 1580 { 1581 #if 0 1582 struct cbslot_attach_args *cba = aux; 1583 1584 if (cba->cba_slot >= 0) { 1585 aprint_normal(" slot %d", cba->cba_slot); 1586 } 1587 #endif 1588 return UNCONF; 1589 } 1590 1591 /* 1592 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1593 * This function enables and disables the card 1594 */ 1595 STATIC int 1596 pccbb_cardenable(struct pccbb_softc *sc, int function) 1597 { 1598 u_int32_t command = 1599 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1600 1601 DPRINTF(("pccbb_cardenable:")); 1602 switch (function) { 1603 case CARDBUS_IO_ENABLE: 1604 command |= PCI_COMMAND_IO_ENABLE; 1605 break; 1606 case CARDBUS_IO_DISABLE: 1607 command &= ~PCI_COMMAND_IO_ENABLE; 1608 break; 1609 case CARDBUS_MEM_ENABLE: 1610 command |= PCI_COMMAND_MEM_ENABLE; 1611 break; 1612 case CARDBUS_MEM_DISABLE: 1613 command &= ~PCI_COMMAND_MEM_ENABLE; 1614 break; 1615 case CARDBUS_BM_ENABLE: 1616 command |= PCI_COMMAND_MASTER_ENABLE; 1617 break; 1618 case CARDBUS_BM_DISABLE: 1619 command &= ~PCI_COMMAND_MASTER_ENABLE; 1620 break; 1621 default: 1622 return 0; 1623 } 1624 1625 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1626 DPRINTF((" command reg 0x%x\n", command)); 1627 return 1; 1628 } 1629 1630 #if !rbus 1631 static int 1632 pccbb_io_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 1633 { 1634 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1635 int basereg; 1636 int limitreg; 1637 1638 if ((win < 0) || (win > 2)) { 1639 #if defined DIAGNOSTIC 1640 printf("cardbus_io_open: window out of range %d\n", win); 1641 #endif 1642 return 0; 1643 } 1644 1645 basereg = win * 8 + 0x2c; 1646 limitreg = win * 8 + 0x30; 1647 1648 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1649 start, basereg, end, limitreg)); 1650 1651 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1652 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1653 return 1; 1654 } 1655 1656 /* 1657 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1658 */ 1659 static int 1660 pccbb_io_close(cardbus_chipset_tag_t ct, int win) 1661 { 1662 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1663 int basereg; 1664 int limitreg; 1665 1666 if ((win < 0) || (win > 2)) { 1667 #if defined DIAGNOSTIC 1668 printf("cardbus_io_close: window out of range %d\n", win); 1669 #endif 1670 return 0; 1671 } 1672 1673 basereg = win * 8 + 0x2c; 1674 limitreg = win * 8 + 0x30; 1675 1676 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1677 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1678 return 1; 1679 } 1680 1681 static int 1682 pccbb_mem_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 1683 { 1684 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1685 int basereg; 1686 int limitreg; 1687 1688 if ((win < 0) || (win > 2)) { 1689 #if defined DIAGNOSTIC 1690 printf("cardbus_mem_open: window out of range %d\n", win); 1691 #endif 1692 return 0; 1693 } 1694 1695 basereg = win * 8 + 0x1c; 1696 limitreg = win * 8 + 0x20; 1697 1698 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1699 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1700 return 1; 1701 } 1702 1703 static int 1704 pccbb_mem_close(cardbus_chipset_tag_t ct, int win) 1705 { 1706 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1707 int basereg; 1708 int limitreg; 1709 1710 if ((win < 0) || (win > 2)) { 1711 #if defined DIAGNOSTIC 1712 printf("cardbus_mem_close: window out of range %d\n", win); 1713 #endif 1714 return 0; 1715 } 1716 1717 basereg = win * 8 + 0x1c; 1718 limitreg = win * 8 + 0x20; 1719 1720 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1721 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1722 return 1; 1723 } 1724 #endif 1725 1726 /* 1727 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1728 * int irq, 1729 * int level, 1730 * int (* func)(void *), 1731 * void *arg) 1732 * 1733 * This function registers an interrupt handler at the bridge, in 1734 * order not to call the interrupt handlers of child devices when 1735 * a card-deletion interrupt occurs. 1736 * 1737 * The arguments irq and level are not used. 1738 */ 1739 static void * 1740 pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, int irq, int level, 1741 int (*func)(void *), void *arg) 1742 { 1743 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1744 1745 return pccbb_intr_establish(sc, irq, level, func, arg); 1746 } 1747 1748 1749 /* 1750 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1751 * void *ih) 1752 * 1753 * This function removes an interrupt handler pointed by ih. 1754 */ 1755 static void 1756 pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih) 1757 { 1758 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1759 1760 pccbb_intr_disestablish(sc, ih); 1761 } 1762 1763 1764 void 1765 pccbb_intr_route(struct pccbb_softc *sc) 1766 { 1767 pcireg_t bcr, cbctrl; 1768 1769 /* initialize bridge intr routing */ 1770 bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1771 bcr &= ~CB_BCR_INTR_IREQ_ENABLE; 1772 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr); 1773 1774 switch (sc->sc_chipset) { 1775 case CB_TI113X: 1776 cbctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1777 /* functional intr enabled */ 1778 cbctrl |= PCI113X_CBCTRL_PCI_INTR; 1779 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, cbctrl); 1780 break; 1781 default: 1782 break; 1783 } 1784 } 1785 1786 /* 1787 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1788 * int irq, 1789 * int level, 1790 * int (* func)(void *), 1791 * void *arg) 1792 * 1793 * This function registers an interrupt handler at the bridge, in 1794 * order not to call the interrupt handlers of child devices when 1795 * a card-deletion interrupt occurs. 1796 * 1797 * The arguments irq is not used because pccbb selects intr vector. 1798 */ 1799 static void * 1800 pccbb_intr_establish(struct pccbb_softc *sc, int irq, int level, 1801 int (*func)(void *), void *arg) 1802 { 1803 struct pccbb_intrhand_list *pil, *newpil; 1804 1805 DPRINTF(("pccbb_intr_establish start. %p\n", LIST_FIRST(&sc->sc_pil))); 1806 1807 if (LIST_EMPTY(&sc->sc_pil)) { 1808 pccbb_intr_route(sc); 1809 } 1810 1811 /* 1812 * Allocate a room for interrupt handler structure. 1813 */ 1814 if (NULL == (newpil = 1815 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1816 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1817 return NULL; 1818 } 1819 1820 newpil->pil_func = func; 1821 newpil->pil_arg = arg; 1822 newpil->pil_icookie = makeiplcookie(level); 1823 1824 if (LIST_EMPTY(&sc->sc_pil)) { 1825 LIST_INSERT_HEAD(&sc->sc_pil, newpil, pil_next); 1826 } else { 1827 for (pil = LIST_FIRST(&sc->sc_pil); 1828 LIST_NEXT(pil, pil_next) != NULL; 1829 pil = LIST_NEXT(pil, pil_next)); 1830 LIST_INSERT_AFTER(pil, newpil, pil_next); 1831 } 1832 1833 DPRINTF(("pccbb_intr_establish add pil. %p\n", 1834 LIST_FIRST(&sc->sc_pil))); 1835 1836 return newpil; 1837 } 1838 1839 /* 1840 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1841 * void *ih) 1842 * 1843 * This function removes an interrupt handler pointed by ih. ih 1844 * should be the value returned by cardbus_intr_establish() or 1845 * NULL. 1846 * 1847 * When ih is NULL, this function will do nothing. 1848 */ 1849 static void 1850 pccbb_intr_disestablish(struct pccbb_softc *sc, void *ih) 1851 { 1852 struct pccbb_intrhand_list *pil; 1853 pcireg_t reg; 1854 1855 DPRINTF(("pccbb_intr_disestablish start. %p\n", 1856 LIST_FIRST(&sc->sc_pil))); 1857 1858 if (ih == NULL) { 1859 /* intr handler is not set */ 1860 DPRINTF(("pccbb_intr_disestablish: no ih\n")); 1861 return; 1862 } 1863 1864 #ifdef DIAGNOSTIC 1865 LIST_FOREACH(pil, &sc->sc_pil, pil_next) { 1866 DPRINTF(("pccbb_intr_disestablish: pil %p\n", pil)); 1867 if (pil == ih) { 1868 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1869 break; 1870 } 1871 } 1872 if (pil == NULL) { 1873 panic("pccbb_intr_disestablish: %s cannot find pil %p", 1874 sc->sc_dev.dv_xname, ih); 1875 } 1876 #endif 1877 1878 pil = (struct pccbb_intrhand_list *)ih; 1879 LIST_REMOVE(pil, pil_next); 1880 free(pil, M_DEVBUF); 1881 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1882 1883 if (LIST_EMPTY(&sc->sc_pil)) { 1884 /* No interrupt handlers */ 1885 1886 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1887 1888 /* stop routing PCI intr */ 1889 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1890 reg |= CB_BCR_INTR_IREQ_ENABLE; 1891 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, reg); 1892 1893 switch (sc->sc_chipset) { 1894 case CB_TI113X: 1895 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1896 /* functional intr disabled */ 1897 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1898 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1899 break; 1900 default: 1901 break; 1902 } 1903 } 1904 } 1905 1906 #if defined SHOW_REGS 1907 static void 1908 cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, bus_space_tag_t memt, 1909 bus_space_handle_t memh) 1910 { 1911 int i; 1912 printf("PCI config regs:"); 1913 for (i = 0; i < 0x50; i += 4) { 1914 if (i % 16 == 0) 1915 printf("\n 0x%02x:", i); 1916 printf(" %08x", pci_conf_read(pc, tag, i)); 1917 } 1918 for (i = 0x80; i < 0xb0; i += 4) { 1919 if (i % 16 == 0) 1920 printf("\n 0x%02x:", i); 1921 printf(" %08x", pci_conf_read(pc, tag, i)); 1922 } 1923 1924 if (memh == 0) { 1925 printf("\n"); 1926 return; 1927 } 1928 1929 printf("\nsocket regs:"); 1930 for (i = 0; i <= 0x10; i += 0x04) 1931 printf(" %08x", bus_space_read_4(memt, memh, i)); 1932 printf("\nExCA regs:"); 1933 for (i = 0; i < 0x08; ++i) 1934 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1935 printf("\n"); 1936 return; 1937 } 1938 #endif 1939 1940 /* 1941 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1942 * int busno, int function) 1943 * This is the function to make a tag to access config space of 1944 * a CardBus Card. It works same as pci_conf_read. 1945 */ 1946 static cardbustag_t 1947 pccbb_make_tag(cardbus_chipset_tag_t cc, int busno, int function) 1948 { 1949 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1950 1951 return pci_make_tag(sc->sc_pc, busno, 0, function); 1952 } 1953 1954 static void 1955 pccbb_free_tag(cardbus_chipset_tag_t cc, cardbustag_t tag) 1956 { 1957 } 1958 1959 /* 1960 * pccbb_conf_read 1961 * 1962 * This is the function to read the config space of a CardBus card. 1963 * It works the same as pci_conf_read(9). 1964 */ 1965 static cardbusreg_t 1966 pccbb_conf_read(cardbus_chipset_tag_t cc, cardbustag_t tag, int offset) 1967 { 1968 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1969 1970 return pci_conf_read(sc->sc_pc, tag, offset); 1971 } 1972 1973 /* 1974 * pccbb_conf_write 1975 * 1976 * This is the function to write the config space of a CardBus 1977 * card. It works the same as pci_conf_write(9). 1978 */ 1979 static void 1980 pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, int reg, 1981 cardbusreg_t val) 1982 { 1983 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1984 1985 pci_conf_write(sc->sc_pc, tag, reg, val); 1986 } 1987 1988 #if 0 1989 STATIC int 1990 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1991 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 1992 int speed, int flags, 1993 bus_space_handle_t * iohp) 1994 #endif 1995 /* 1996 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1997 * bus_addr_t start, bus_size_t size, 1998 * bus_size_t align, 1999 * struct pcmcia_io_handle *pcihp 2000 * 2001 * This function only allocates I/O region for pccard. This function 2002 * never maps the allocated region to pccard I/O area. 2003 * 2004 * XXX: The interface of this function is not very good, I believe. 2005 */ 2006 STATIC int 2007 pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, 2008 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 2009 { 2010 struct pcic_handle *ph = (struct pcic_handle *)pch; 2011 bus_addr_t ioaddr; 2012 int flags = 0; 2013 bus_space_tag_t iot; 2014 bus_space_handle_t ioh; 2015 bus_addr_t mask; 2016 #if rbus 2017 rbus_tag_t rb; 2018 #endif 2019 if (align == 0) { 2020 align = size; /* XXX: funny??? */ 2021 } 2022 2023 if (start != 0) { 2024 /* XXX: assume all card decode lower 10 bits by its hardware */ 2025 mask = 0x3ff; 2026 /* enforce to use only masked address */ 2027 start &= mask; 2028 } else { 2029 /* 2030 * calculate mask: 2031 * 1. get the most significant bit of size (call it msb). 2032 * 2. compare msb with the value of size. 2033 * 3. if size is larger, shift msb left once. 2034 * 4. obtain mask value to decrement msb. 2035 */ 2036 bus_size_t size_tmp = size; 2037 int shifts = 0; 2038 2039 mask = 1; 2040 while (size_tmp) { 2041 ++shifts; 2042 size_tmp >>= 1; 2043 } 2044 mask = (1 << shifts); 2045 if (mask < size) { 2046 mask <<= 1; 2047 } 2048 --mask; 2049 } 2050 2051 /* 2052 * Allocate some arbitrary I/O space. 2053 */ 2054 2055 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 2056 2057 #if rbus 2058 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 2059 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 2060 return 1; 2061 } 2062 DPRINTF(("pccbb_pcmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2063 (u_long) ioaddr, (u_long) size)); 2064 #else 2065 if (start) { 2066 ioaddr = start; 2067 if (bus_space_map(iot, start, size, 0, &ioh)) { 2068 return 1; 2069 } 2070 DPRINTF(("pccbb_pcmcia_io_alloc map port 0x%lx+0x%lx\n", 2071 (u_long) ioaddr, (u_long) size)); 2072 } else { 2073 flags |= PCMCIA_IO_ALLOCATED; 2074 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 2075 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 2076 size, align, 0, 0, &ioaddr, &ioh)) { 2077 /* No room be able to be get. */ 2078 return 1; 2079 } 2080 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2081 (u_long) ioaddr, (u_long) size)); 2082 } 2083 #endif 2084 2085 pcihp->iot = iot; 2086 pcihp->ioh = ioh; 2087 pcihp->addr = ioaddr; 2088 pcihp->size = size; 2089 pcihp->flags = flags; 2090 2091 return 0; 2092 } 2093 2094 /* 2095 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2096 * struct pcmcia_io_handle *pcihp) 2097 * 2098 * This function only frees I/O region for pccard. 2099 * 2100 * XXX: The interface of this function is not very good, I believe. 2101 */ 2102 void 2103 pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2104 struct pcmcia_io_handle *pcihp) 2105 { 2106 #if !rbus 2107 bus_space_tag_t iot = pcihp->iot; 2108 #endif 2109 bus_space_handle_t ioh = pcihp->ioh; 2110 bus_size_t size = pcihp->size; 2111 2112 #if rbus 2113 struct pccbb_softc *sc = 2114 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 2115 rbus_tag_t rb = sc->sc_rbus_iot; 2116 2117 rbus_space_free(rb, ioh, size, NULL); 2118 #else 2119 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 2120 bus_space_free(iot, ioh, size); 2121 else 2122 bus_space_unmap(iot, ioh, size); 2123 #endif 2124 } 2125 2126 /* 2127 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 2128 * bus_addr_t offset, bus_size_t size, 2129 * struct pcmcia_io_handle *pcihp, 2130 * int *windowp) 2131 * 2132 * This function maps the allocated I/O region to pccard. This function 2133 * never allocates any I/O region for pccard I/O area. I don't 2134 * understand why the original authors of pcmciabus separated alloc and 2135 * map. I believe the two must be unite. 2136 * 2137 * XXX: no wait timing control? 2138 */ 2139 int 2140 pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, bus_addr_t offset, 2141 bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp) 2142 { 2143 struct pcic_handle *ph = (struct pcic_handle *)pch; 2144 bus_addr_t ioaddr = pcihp->addr + offset; 2145 int i, win; 2146 #if defined CBB_DEBUG 2147 static const char *width_names[] = { "dynamic", "io8", "io16" }; 2148 #endif 2149 2150 /* Sanity check I/O handle. */ 2151 2152 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 2153 panic("pccbb_pcmcia_io_map iot is bogus"); 2154 } 2155 2156 /* XXX Sanity check offset/size. */ 2157 2158 win = -1; 2159 for (i = 0; i < PCIC_IO_WINS; i++) { 2160 if ((ph->ioalloc & (1 << i)) == 0) { 2161 win = i; 2162 ph->ioalloc |= (1 << i); 2163 break; 2164 } 2165 } 2166 2167 if (win == -1) { 2168 return 1; 2169 } 2170 2171 *windowp = win; 2172 2173 /* XXX this is pretty gross */ 2174 2175 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2176 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2177 2178 /* XXX wtf is this doing here? */ 2179 2180 #if 0 2181 printf(" port 0x%lx", (u_long) ioaddr); 2182 if (size > 1) { 2183 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2184 } 2185 #endif 2186 2187 ph->io[win].addr = ioaddr; 2188 ph->io[win].size = size; 2189 ph->io[win].width = width; 2190 2191 /* actual dirty register-value changing in the function below. */ 2192 pccbb_pcmcia_do_io_map(ph, win); 2193 2194 return 0; 2195 } 2196 2197 /* 2198 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2199 * 2200 * This function changes register-value to map I/O region for pccard. 2201 */ 2202 static void 2203 pccbb_pcmcia_do_io_map(struct pcic_handle *ph, int win) 2204 { 2205 static u_int8_t pcic_iowidth[3] = { 2206 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2207 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2208 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2209 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2210 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2211 }; 2212 2213 #define PCIC_SIA_START_LOW 0 2214 #define PCIC_SIA_START_HIGH 1 2215 #define PCIC_SIA_STOP_LOW 2 2216 #define PCIC_SIA_STOP_HIGH 3 2217 2218 int regbase_win = 0x8 + win * 0x04; 2219 u_int8_t ioctl, enable; 2220 2221 DPRINTF(("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx " 2222 "width %d\n", win, (unsigned long)ph->io[win].addr, 2223 (unsigned long)ph->io[win].size, ph->io[win].width * 8)); 2224 2225 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2226 ph->io[win].addr & 0xff); 2227 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2228 (ph->io[win].addr >> 8) & 0xff); 2229 2230 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2231 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2232 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2233 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2234 2235 ioctl = Pcic_read(ph, PCIC_IOCTL); 2236 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2237 switch (win) { 2238 case 0: 2239 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2240 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2241 PCIC_IOCTL_IO0_DATASIZE_MASK); 2242 ioctl |= pcic_iowidth[ph->io[win].width]; 2243 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2244 break; 2245 case 1: 2246 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2247 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2248 PCIC_IOCTL_IO1_DATASIZE_MASK); 2249 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2250 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2251 break; 2252 } 2253 Pcic_write(ph, PCIC_IOCTL, ioctl); 2254 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2255 #if defined(CBB_DEBUG) 2256 { 2257 u_int8_t start_low = 2258 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2259 u_int8_t start_high = 2260 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2261 u_int8_t stop_low = 2262 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2263 u_int8_t stop_high = 2264 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2265 printf("pccbb_pcmcia_do_io_map start %02x %02x, " 2266 "stop %02x %02x, ioctl %02x enable %02x\n", 2267 start_low, start_high, stop_low, stop_high, ioctl, enable); 2268 } 2269 #endif 2270 } 2271 2272 /* 2273 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2274 * 2275 * This function unmaps I/O region. No return value. 2276 */ 2277 STATIC void 2278 pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t pch, int win) 2279 { 2280 struct pcic_handle *ph = (struct pcic_handle *)pch; 2281 int reg; 2282 2283 if (win >= PCIC_IO_WINS || win < 0) { 2284 panic("pccbb_pcmcia_io_unmap: window out of range"); 2285 } 2286 2287 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2288 switch (win) { 2289 case 0: 2290 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2291 break; 2292 case 1: 2293 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2294 break; 2295 } 2296 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2297 2298 ph->ioalloc &= ~(1 << win); 2299 } 2300 2301 static int 2302 pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 2303 { 2304 u_int8_t stat; 2305 int i; 2306 2307 /* wait an initial 10ms for quick cards */ 2308 stat = Pcic_read(ph, PCIC_IF_STATUS); 2309 if (stat & PCIC_IF_STATUS_READY) 2310 return (0); 2311 pccbb_pcmcia_delay(ph, 10, "pccwr0"); 2312 for (i = 0; i < 50; i++) { 2313 stat = Pcic_read(ph, PCIC_IF_STATUS); 2314 if (stat & PCIC_IF_STATUS_READY) 2315 return (0); 2316 if ((stat & PCIC_IF_STATUS_CARDDETECT_MASK) != 2317 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2318 return (ENXIO); 2319 /* wait .1s (100ms) each iteration now */ 2320 pccbb_pcmcia_delay(ph, 100, "pccwr1"); 2321 } 2322 2323 printf("pccbb_pcmcia_wait_ready: ready never happened, status=%02x\n", stat); 2324 return (EWOULDBLOCK); 2325 } 2326 2327 /* 2328 * Perform long (msec order) delay. timo is in milliseconds. 2329 */ 2330 static void 2331 pccbb_pcmcia_delay(struct pcic_handle *ph, int timo, const char *wmesg) 2332 { 2333 #ifdef DIAGNOSTIC 2334 if (timo <= 0) 2335 panic("pccbb_pcmcia_delay: called with timeout %d", timo); 2336 if (!curlwp) 2337 panic("pccbb_pcmcia_delay: called in interrupt context"); 2338 #if 0 2339 if (!ph->event_thread) 2340 panic("pccbb_pcmcia_delay: no event thread"); 2341 #endif 2342 #endif 2343 DPRINTF(("pccbb_pcmcia_delay: \"%s\" %p, sleep %d ms\n", 2344 wmesg, ph->event_thread, timo)); 2345 tsleep(pccbb_pcmcia_delay, PWAIT, wmesg, roundup(timo * hz, 1000) / 1000); 2346 } 2347 2348 /* 2349 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2350 * 2351 * This function enables the card. All information is stored in 2352 * the first argument, pcmcia_chipset_handle_t. 2353 */ 2354 STATIC void 2355 pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2356 { 2357 struct pcic_handle *ph = (struct pcic_handle *)pch; 2358 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2359 pcireg_t spsr; 2360 int voltage; 2361 int win; 2362 u_int8_t power, intr; 2363 #ifdef DIAGNOSTIC 2364 int reg; 2365 #endif 2366 2367 /* this bit is mostly stolen from pcic_attach_card */ 2368 2369 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2370 2371 /* get card Vcc info */ 2372 spsr = 2373 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2374 CB_SOCKET_STAT); 2375 if (spsr & CB_SOCKET_STAT_5VCARD) { 2376 DPRINTF(("5V card\n")); 2377 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2378 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2379 DPRINTF(("3V card\n")); 2380 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2381 } else { 2382 DPRINTF(("?V card, 0x%x\n", spsr)); /* XXX */ 2383 return; 2384 } 2385 2386 /* disable interrupts; assert RESET */ 2387 intr = Pcic_read(ph, PCIC_INTR); 2388 intr &= PCIC_INTR_ENABLE; 2389 Pcic_write(ph, PCIC_INTR, intr); 2390 2391 /* zero out the address windows */ 2392 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2393 2394 /* power down the socket to reset it, clear the card reset pin */ 2395 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2396 2397 /* power off; assert output enable bit */ 2398 power = PCIC_PWRCTL_OE; 2399 Pcic_write(ph, PCIC_PWRCTL, power); 2400 2401 /* power up the socket */ 2402 if (pccbb_power(sc, voltage) == 0) 2403 return; 2404 2405 /* 2406 * Table 4-18 and figure 4-6 of the PC Card specifiction say: 2407 * Vcc Rising Time (Tpr) = 100ms (handled in pccbb_power() above) 2408 * RESET Width (Th (Hi-z RESET)) = 1ms 2409 * RESET Width (Tw (RESET)) = 10us 2410 * 2411 * some machines require some more time to be settled 2412 * for example old toshiba topic bridges! 2413 * (100ms is added here). 2414 */ 2415 pccbb_pcmcia_delay(ph, 200 + 1, "pccen1"); 2416 2417 /* negate RESET */ 2418 intr |= PCIC_INTR_RESET; 2419 Pcic_write(ph, PCIC_INTR, intr); 2420 2421 /* 2422 * RESET Setup Time (Tsu (RESET)) = 20ms 2423 */ 2424 pccbb_pcmcia_delay(ph, 20, "pccen2"); 2425 2426 #ifdef DIAGNOSTIC 2427 reg = Pcic_read(ph, PCIC_IF_STATUS); 2428 if ((reg & PCIC_IF_STATUS_POWERACTIVE) == 0) 2429 printf("pccbb_pcmcia_socket_enable: no power, status=%x\n", reg); 2430 #endif 2431 2432 /* wait for the chip to finish initializing */ 2433 if (pccbb_pcmcia_wait_ready(ph)) { 2434 #ifdef DIAGNOSTIC 2435 printf("pccbb_pcmcia_socket_enable: never became ready\n"); 2436 #endif 2437 /* XXX return a failure status?? */ 2438 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2439 Pcic_write(ph, PCIC_PWRCTL, 0); 2440 return; 2441 } 2442 2443 /* reinstall all the memory and io mappings */ 2444 for (win = 0; win < PCIC_MEM_WINS; ++win) 2445 if (ph->memalloc & (1 << win)) 2446 pccbb_pcmcia_do_mem_map(ph, win); 2447 for (win = 0; win < PCIC_IO_WINS; ++win) 2448 if (ph->ioalloc & (1 << win)) 2449 pccbb_pcmcia_do_io_map(ph, win); 2450 } 2451 2452 /* 2453 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2454 * 2455 * This function disables the card. All information is stored in 2456 * the first argument, pcmcia_chipset_handle_t. 2457 */ 2458 STATIC void 2459 pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t pch) 2460 { 2461 struct pcic_handle *ph = (struct pcic_handle *)pch; 2462 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2463 u_int8_t intr; 2464 2465 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2466 2467 /* disable interrupts; assert RESET */ 2468 intr = Pcic_read(ph, PCIC_INTR); 2469 intr &= PCIC_INTR_ENABLE; 2470 Pcic_write(ph, PCIC_INTR, intr); 2471 2472 /* zero out the address windows */ 2473 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2474 2475 /* power down the socket to reset it, clear the card reset pin */ 2476 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2477 2478 /* disable socket: negate output enable bit and power off */ 2479 Pcic_write(ph, PCIC_PWRCTL, 0); 2480 2481 /* 2482 * Vcc Falling Time (Tpf) = 300ms 2483 */ 2484 pccbb_pcmcia_delay(ph, 300, "pccwr1"); 2485 } 2486 2487 STATIC void 2488 pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t pch, int type) 2489 { 2490 struct pcic_handle *ph = (struct pcic_handle *)pch; 2491 u_int8_t intr; 2492 2493 /* set the card type */ 2494 2495 intr = Pcic_read(ph, PCIC_INTR); 2496 intr &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_CARDTYPE_MASK); 2497 if (type == PCMCIA_IFTYPE_IO) 2498 intr |= PCIC_INTR_CARDTYPE_IO; 2499 else 2500 intr |= PCIC_INTR_CARDTYPE_MEM; 2501 Pcic_write(ph, PCIC_INTR, intr); 2502 2503 DPRINTF(("%s: pccbb_pcmcia_socket_settype %02x type %s %02x\n", 2504 ph->ph_parent->dv_xname, ph->sock, 2505 ((type == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2506 } 2507 2508 /* 2509 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2510 * 2511 * This function detects whether a card is in the slot or not. 2512 * If a card is inserted, return 1. Otherwise, return 0. 2513 */ 2514 STATIC int 2515 pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch) 2516 { 2517 struct pcic_handle *ph = (struct pcic_handle *)pch; 2518 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2519 2520 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2521 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2522 } 2523 2524 #if 0 2525 STATIC int 2526 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2527 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2528 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2529 #endif 2530 /* 2531 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2532 * bus_size_t size, 2533 * struct pcmcia_mem_handle *pcmhp) 2534 * 2535 * This function only allocates memory region for pccard. This 2536 * function never maps the allocated region to pccard memory area. 2537 * 2538 * XXX: Why the argument of start address is not in? 2539 */ 2540 STATIC int 2541 pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 2542 struct pcmcia_mem_handle *pcmhp) 2543 { 2544 struct pcic_handle *ph = (struct pcic_handle *)pch; 2545 bus_space_handle_t memh; 2546 bus_addr_t addr; 2547 bus_size_t sizepg; 2548 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2549 #if rbus 2550 rbus_tag_t rb; 2551 #endif 2552 2553 /* Check that the card is still there. */ 2554 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2555 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2556 return 1; 2557 2558 /* out of sc->memh, allocate as many pages as necessary */ 2559 2560 /* convert size to PCIC pages */ 2561 /* 2562 * This is not enough; when the requested region is on the page 2563 * boundaries, this may calculate wrong result. 2564 */ 2565 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2566 #if 0 2567 if (sizepg > PCIC_MAX_MEM_PAGES) { 2568 return 1; 2569 } 2570 #endif 2571 2572 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2573 return 1; 2574 } 2575 2576 addr = 0; /* XXX gcc -Wuninitialized */ 2577 2578 #if rbus 2579 rb = sc->sc_rbus_memt; 2580 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2581 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2582 &addr, &memh)) { 2583 return 1; 2584 } 2585 #else 2586 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2587 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2588 0, /* boundary */ 2589 0, /* flags */ 2590 &addr, &memh)) { 2591 return 1; 2592 } 2593 #endif 2594 2595 DPRINTF(("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, " 2596 "realsize 0x%lx\n", (unsigned long)addr, (unsigned long)size, 2597 (unsigned long)sizepg * PCIC_MEM_PAGESIZE)); 2598 2599 pcmhp->memt = sc->sc_memt; 2600 pcmhp->memh = memh; 2601 pcmhp->addr = addr; 2602 pcmhp->size = size; 2603 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2604 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2605 pcmhp->mhandle = 0; 2606 /* No offset??? Funny. */ 2607 2608 return 0; 2609 } 2610 2611 /* 2612 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2613 * struct pcmcia_mem_handle *pcmhp) 2614 * 2615 * This function release the memory space allocated by the function 2616 * pccbb_pcmcia_mem_alloc(). 2617 */ 2618 STATIC void 2619 pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2620 struct pcmcia_mem_handle *pcmhp) 2621 { 2622 #if rbus 2623 struct pcic_handle *ph = (struct pcic_handle *)pch; 2624 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2625 2626 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2627 #else 2628 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2629 #endif 2630 } 2631 2632 /* 2633 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2634 * 2635 * This function release the memory space allocated by the function 2636 * pccbb_pcmcia_mem_alloc(). 2637 */ 2638 STATIC void 2639 pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2640 { 2641 int regbase_win; 2642 bus_addr_t phys_addr; 2643 bus_addr_t phys_end; 2644 2645 #define PCIC_SMM_START_LOW 0 2646 #define PCIC_SMM_START_HIGH 1 2647 #define PCIC_SMM_STOP_LOW 2 2648 #define PCIC_SMM_STOP_HIGH 3 2649 #define PCIC_CMA_LOW 4 2650 #define PCIC_CMA_HIGH 5 2651 2652 u_int8_t start_low, start_high = 0; 2653 u_int8_t stop_low, stop_high; 2654 u_int8_t off_low, off_high; 2655 u_int8_t mem_window; 2656 int reg; 2657 2658 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2659 int mem8 = 2660 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2661 || (kind == PCMCIA_MEM_ATTR); 2662 2663 regbase_win = 0x10 + win * 0x08; 2664 2665 phys_addr = ph->mem[win].addr; 2666 phys_end = phys_addr + ph->mem[win].size; 2667 2668 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2669 (unsigned long)phys_addr, (unsigned long)phys_end, 2670 (unsigned long)ph->mem[win].offset)); 2671 2672 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2673 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2674 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2675 2676 /* bit 19:12 */ 2677 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2678 /* bit 23:20 and bit 7 on */ 2679 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2680 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2681 /* bit 31:24, for 32-bit address */ 2682 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2683 2684 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2685 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2686 2687 if (((struct pccbb_softc *)ph-> 2688 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2689 Pcic_write(ph, 0x40 + win, mem_window); 2690 } 2691 2692 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2693 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2694 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2695 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2696 2697 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2698 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2699 2700 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2701 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2702 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2703 | ((kind == PCMCIA_MEM_ATTR) ? 2704 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2705 2706 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2707 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2708 2709 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2710 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2711 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2712 2713 #if defined(CBB_DEBUG) 2714 { 2715 int r1, r2, r3, r4, r5, r6, r7 = 0; 2716 2717 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2718 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2719 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2720 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2721 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2722 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2723 if (((struct pccbb_softc *)(ph-> 2724 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2725 r7 = Pcic_read(ph, 0x40 + win); 2726 } 2727 2728 printf("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2729 "%02x%02x", win, r1, r2, r3, r4, r5, r6); 2730 if (((struct pccbb_softc *)(ph-> 2731 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2732 printf(" %02x", r7); 2733 } 2734 printf("\n"); 2735 } 2736 #endif 2737 } 2738 2739 /* 2740 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2741 * bus_addr_t card_addr, bus_size_t size, 2742 * struct pcmcia_mem_handle *pcmhp, 2743 * bus_addr_t *offsetp, int *windowp) 2744 * 2745 * This function maps memory space allocated by the function 2746 * pccbb_pcmcia_mem_alloc(). 2747 */ 2748 STATIC int 2749 pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2750 bus_addr_t card_addr, bus_size_t size, struct pcmcia_mem_handle *pcmhp, 2751 bus_addr_t *offsetp, int *windowp) 2752 { 2753 struct pcic_handle *ph = (struct pcic_handle *)pch; 2754 bus_addr_t busaddr; 2755 long card_offset; 2756 int win; 2757 2758 /* Check that the card is still there. */ 2759 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2760 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2761 return 1; 2762 2763 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2764 if ((ph->memalloc & (1 << win)) == 0) { 2765 ph->memalloc |= (1 << win); 2766 break; 2767 } 2768 } 2769 2770 if (win == PCIC_MEM_WINS) { 2771 return 1; 2772 } 2773 2774 *windowp = win; 2775 2776 /* XXX this is pretty gross */ 2777 2778 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2779 panic("pccbb_pcmcia_mem_map memt is bogus"); 2780 } 2781 2782 busaddr = pcmhp->addr; 2783 2784 /* 2785 * compute the address offset to the pcmcia address space for the 2786 * pcic. this is intentionally signed. The masks and shifts below 2787 * will cause TRT to happen in the pcic registers. Deal with making 2788 * sure the address is aligned, and return the alignment offset. 2789 */ 2790 2791 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2792 card_addr -= *offsetp; 2793 2794 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2795 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2796 (u_long) card_addr)); 2797 2798 /* 2799 * include the offset in the size, and decrement size by one, since 2800 * the hw wants start/stop 2801 */ 2802 size += *offsetp - 1; 2803 2804 card_offset = (((long)card_addr) - ((long)busaddr)); 2805 2806 ph->mem[win].addr = busaddr; 2807 ph->mem[win].size = size; 2808 ph->mem[win].offset = card_offset; 2809 ph->mem[win].kind = kind; 2810 2811 pccbb_pcmcia_do_mem_map(ph, win); 2812 2813 return 0; 2814 } 2815 2816 /* 2817 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2818 * int window) 2819 * 2820 * This function unmaps memory space which mapped by the function 2821 * pccbb_pcmcia_mem_map(). 2822 */ 2823 STATIC void 2824 pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, int window) 2825 { 2826 struct pcic_handle *ph = (struct pcic_handle *)pch; 2827 int reg; 2828 2829 if (window >= PCIC_MEM_WINS) { 2830 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2831 } 2832 2833 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2834 reg &= ~(1 << window); 2835 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2836 2837 ph->memalloc &= ~(1 << window); 2838 } 2839 2840 #if defined PCCBB_PCMCIA_POLL 2841 struct pccbb_poll_str { 2842 void *arg; 2843 int (*func)(void *); 2844 int level; 2845 struct pcic_handle *ph; 2846 int count; 2847 int num; 2848 struct callout poll_ch; 2849 }; 2850 2851 static struct pccbb_poll_str pccbb_poll[10]; 2852 static int pccbb_poll_n = 0; 2853 2854 static void pccbb_pcmcia_poll(void *arg); 2855 2856 static void 2857 pccbb_pcmcia_poll(void *arg) 2858 { 2859 struct pccbb_poll_str *poll = arg; 2860 struct pcic_handle *ph = poll->ph; 2861 struct pccbb_softc *sc = ph->sc; 2862 int s; 2863 u_int32_t spsr; /* socket present-state reg */ 2864 2865 callout_reset(&poll->poll_ch, hz * 2, pccbb_pcmcia_poll, arg); 2866 switch (poll->level) { 2867 case IPL_NET: 2868 s = splnet(); 2869 break; 2870 case IPL_BIO: 2871 s = splbio(); 2872 break; 2873 case IPL_TTY: /* fallthrough */ 2874 default: 2875 s = spltty(); 2876 break; 2877 } 2878 2879 spsr = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2880 CB_SOCKET_STAT); 2881 2882 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2883 if (!(spsr & 0x40)) /* CINT low */ 2884 #else 2885 if (1) 2886 #endif 2887 { 2888 if ((*poll->func) (poll->arg) > 0) { 2889 ++poll->count; 2890 /* printf("intr: reported from poller, 0x%x\n", spsr); */ 2891 #if defined LEVEL2 2892 } else { 2893 printf("intr: miss! 0x%x\n", spsr); 2894 #endif 2895 } 2896 } 2897 splx(s); 2898 } 2899 #endif /* defined CB_PCMCIA_POLL */ 2900 2901 /* 2902 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2903 * struct pcmcia_function *pf, 2904 * int ipl, 2905 * int (*func)(void *), 2906 * void *arg); 2907 * 2908 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2909 */ 2910 STATIC void * 2911 pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2912 struct pcmcia_function *pf, int ipl, int (*func)(void *), void *arg) 2913 { 2914 struct pcic_handle *ph = (struct pcic_handle *)pch; 2915 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2916 2917 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2918 /* what should I do? */ 2919 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2920 DPRINTF(("%s does not provide edge nor pulse " 2921 "interrupt\n", sc->sc_dev.dv_xname)); 2922 return NULL; 2923 } 2924 /* 2925 * XXX Noooooo! The interrupt flag must set properly!! 2926 * dumb pcmcia driver!! 2927 */ 2928 } 2929 2930 return pccbb_intr_establish(sc, 0, ipl, func, arg); 2931 } 2932 2933 /* 2934 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2935 * void *ih) 2936 * 2937 * This function disables PC-Card interrupt. 2938 */ 2939 STATIC void 2940 pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 2941 { 2942 struct pcic_handle *ph = (struct pcic_handle *)pch; 2943 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2944 2945 pccbb_intr_disestablish(sc, ih); 2946 } 2947 2948 #if rbus 2949 /* 2950 * static int 2951 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2952 * bus_addr_t addr, bus_size_t size, 2953 * bus_addr_t mask, bus_size_t align, 2954 * int flags, bus_addr_t *addrp; 2955 * bus_space_handle_t *bshp) 2956 * 2957 * This function allocates a portion of memory or io space for 2958 * clients. This function is called from CardBus card drivers. 2959 */ 2960 static int 2961 pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2962 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 2963 int flags, bus_addr_t *addrp, bus_space_handle_t *bshp) 2964 { 2965 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2966 2967 DPRINTF(("pccbb_rbus_cb_space_alloc: addr 0x%lx, size 0x%lx, " 2968 "mask 0x%lx, align 0x%lx\n", (unsigned long)addr, 2969 (unsigned long)size, (unsigned long)mask, (unsigned long)align)); 2970 2971 if (align == 0) { 2972 align = size; 2973 } 2974 2975 if (rb->rb_bt == sc->sc_memt) { 2976 if (align < 16) { 2977 return 1; 2978 } 2979 /* 2980 * XXX: align more than 0x1000 to avoid overwrapping 2981 * memory windows for two or more devices. 0x1000 2982 * means memory window's granularity. 2983 * 2984 * Two or more devices should be able to share same 2985 * memory window region. However, overrapping memory 2986 * window is not good because some devices, such as 2987 * 3Com 3C575[BC], have a broken address decoder and 2988 * intrude other's memory region. 2989 */ 2990 if (align < 0x1000) { 2991 align = 0x1000; 2992 } 2993 } else if (rb->rb_bt == sc->sc_iot) { 2994 if (align < 4) { 2995 return 1; 2996 } 2997 /* XXX: hack for avoiding ISA image */ 2998 if (mask < 0x0100) { 2999 mask = 0x3ff; 3000 addr = 0x300; 3001 } 3002 3003 } else { 3004 DPRINTF(("pccbb_rbus_cb_space_alloc: Bus space tag 0x%lx is " 3005 "NOT used. io: 0x%lx, mem: 0x%lx\n", 3006 (unsigned long)rb->rb_bt, (unsigned long)sc->sc_iot, 3007 (unsigned long)sc->sc_memt)); 3008 return 1; 3009 /* XXX: panic here? */ 3010 } 3011 3012 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 3013 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 3014 return 1; 3015 } 3016 3017 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 3018 3019 return 0; 3020 } 3021 3022 /* 3023 * static int 3024 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 3025 * bus_space_handle_t *bshp, bus_size_t size); 3026 * 3027 * This function is called from CardBus card drivers. 3028 */ 3029 static int 3030 pccbb_rbus_cb_space_free(cardbus_chipset_tag_t ct, rbus_tag_t rb, 3031 bus_space_handle_t bsh, bus_size_t size) 3032 { 3033 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 3034 bus_space_tag_t bt = rb->rb_bt; 3035 3036 pccbb_close_win(sc, bt, bsh, size); 3037 3038 if (bt == sc->sc_memt) { 3039 } else if (bt == sc->sc_iot) { 3040 } else { 3041 return 1; 3042 /* XXX: panic here? */ 3043 } 3044 3045 return rbus_space_free(rb, bsh, size, NULL); 3046 } 3047 #endif /* rbus */ 3048 3049 #if rbus 3050 3051 static int 3052 pccbb_open_win(struct pccbb_softc *sc, bus_space_tag_t bst, bus_addr_t addr, 3053 bus_size_t size, bus_space_handle_t bsh, int flags) 3054 { 3055 struct pccbb_win_chain_head *head; 3056 bus_addr_t align; 3057 3058 head = &sc->sc_iowindow; 3059 align = 0x04; 3060 if (sc->sc_memt == bst) { 3061 head = &sc->sc_memwindow; 3062 align = 0x1000; 3063 DPRINTF(("using memory window, 0x%lx 0x%lx 0x%lx\n\n", 3064 (unsigned long)sc->sc_iot, (unsigned long)sc->sc_memt, 3065 (unsigned long)bst)); 3066 } 3067 3068 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 3069 printf("%s: pccbb_open_win: %s winlist insert failed\n", 3070 sc->sc_dev.dv_xname, 3071 (head == &sc->sc_memwindow) ? "mem" : "io"); 3072 } 3073 pccbb_winset(align, sc, bst); 3074 3075 return 0; 3076 } 3077 3078 static int 3079 pccbb_close_win(struct pccbb_softc *sc, bus_space_tag_t bst, 3080 bus_space_handle_t bsh, bus_size_t size) 3081 { 3082 struct pccbb_win_chain_head *head; 3083 bus_addr_t align; 3084 3085 head = &sc->sc_iowindow; 3086 align = 0x04; 3087 if (sc->sc_memt == bst) { 3088 head = &sc->sc_memwindow; 3089 align = 0x1000; 3090 } 3091 3092 if (pccbb_winlist_delete(head, bsh, size)) { 3093 printf("%s: pccbb_close_win: %s winlist delete failed\n", 3094 sc->sc_dev.dv_xname, 3095 (head == &sc->sc_memwindow) ? "mem" : "io"); 3096 } 3097 pccbb_winset(align, sc, bst); 3098 3099 return 0; 3100 } 3101 3102 static int 3103 pccbb_winlist_insert(struct pccbb_win_chain_head *head, bus_addr_t start, 3104 bus_size_t size, bus_space_handle_t bsh, int flags) 3105 { 3106 struct pccbb_win_chain *chainp, *elem; 3107 3108 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 3109 M_NOWAIT)) == NULL) 3110 return (1); /* fail */ 3111 3112 elem->wc_start = start; 3113 elem->wc_end = start + (size - 1); 3114 elem->wc_handle = bsh; 3115 elem->wc_flags = flags; 3116 3117 TAILQ_FOREACH(chainp, head, wc_list) { 3118 if (chainp->wc_end >= start) 3119 break; 3120 } 3121 if (chainp != NULL) 3122 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 3123 else 3124 TAILQ_INSERT_TAIL(head, elem, wc_list); 3125 return (0); 3126 } 3127 3128 static int 3129 pccbb_winlist_delete(struct pccbb_win_chain_head *head, bus_space_handle_t bsh, 3130 bus_size_t size) 3131 { 3132 struct pccbb_win_chain *chainp; 3133 3134 TAILQ_FOREACH(chainp, head, wc_list) { 3135 if (memcmp(&chainp->wc_handle, &bsh, sizeof(bsh)) == 0) 3136 break; 3137 } 3138 if (chainp == NULL) 3139 return 1; /* fail: no candidate to remove */ 3140 3141 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 3142 printf("pccbb_winlist_delete: window 0x%lx size " 3143 "inconsistent: 0x%lx, 0x%lx\n", 3144 (unsigned long)chainp->wc_start, 3145 (unsigned long)(chainp->wc_end - chainp->wc_start), 3146 (unsigned long)(size - 1)); 3147 return 1; 3148 } 3149 3150 TAILQ_REMOVE(head, chainp, wc_list); 3151 free(chainp, M_DEVBUF); 3152 3153 return 0; 3154 } 3155 3156 static void 3157 pccbb_winset(bus_addr_t align, struct pccbb_softc *sc, bus_space_tag_t bst) 3158 { 3159 pci_chipset_tag_t pc; 3160 pcitag_t tag; 3161 bus_addr_t mask = ~(align - 1); 3162 struct { 3163 cardbusreg_t win_start; 3164 cardbusreg_t win_limit; 3165 int win_flags; 3166 } win[2]; 3167 struct pccbb_win_chain *chainp; 3168 int offs; 3169 3170 win[0].win_start = win[1].win_start = 0xffffffff; 3171 win[0].win_limit = win[1].win_limit = 0; 3172 win[0].win_flags = win[1].win_flags = 0; 3173 3174 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3175 offs = 0x2c; 3176 if (sc->sc_memt == bst) { 3177 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3178 offs = 0x1c; 3179 } 3180 3181 if (chainp != NULL) { 3182 win[0].win_start = chainp->wc_start & mask; 3183 win[0].win_limit = chainp->wc_end & mask; 3184 win[0].win_flags = chainp->wc_flags; 3185 chainp = TAILQ_NEXT(chainp, wc_list); 3186 } 3187 3188 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3189 if (win[1].win_start == 0xffffffff) { 3190 /* window 1 is not used */ 3191 if ((win[0].win_flags == chainp->wc_flags) && 3192 (win[0].win_limit + align >= 3193 (chainp->wc_start & mask))) { 3194 /* concatenate */ 3195 win[0].win_limit = chainp->wc_end & mask; 3196 } else { 3197 /* make new window */ 3198 win[1].win_start = chainp->wc_start & mask; 3199 win[1].win_limit = chainp->wc_end & mask; 3200 win[1].win_flags = chainp->wc_flags; 3201 } 3202 continue; 3203 } 3204 3205 /* Both windows are engaged. */ 3206 if (win[0].win_flags == win[1].win_flags) { 3207 /* same flags */ 3208 if (win[0].win_flags == chainp->wc_flags) { 3209 if (win[1].win_start - (win[0].win_limit + 3210 align) < 3211 (chainp->wc_start & mask) - 3212 ((chainp->wc_end & mask) + align)) { 3213 /* 3214 * merge window 0 and 1, and set win1 3215 * to chainp 3216 */ 3217 win[0].win_limit = win[1].win_limit; 3218 win[1].win_start = 3219 chainp->wc_start & mask; 3220 win[1].win_limit = 3221 chainp->wc_end & mask; 3222 } else { 3223 win[1].win_limit = 3224 chainp->wc_end & mask; 3225 } 3226 } else { 3227 /* different flags */ 3228 3229 /* concatenate win0 and win1 */ 3230 win[0].win_limit = win[1].win_limit; 3231 /* allocate win[1] to new space */ 3232 win[1].win_start = chainp->wc_start & mask; 3233 win[1].win_limit = chainp->wc_end & mask; 3234 win[1].win_flags = chainp->wc_flags; 3235 } 3236 } else { 3237 /* the flags of win[0] and win[1] is different */ 3238 if (win[0].win_flags == chainp->wc_flags) { 3239 win[0].win_limit = chainp->wc_end & mask; 3240 /* 3241 * XXX this creates overlapping windows, so 3242 * what should the poor bridge do if one is 3243 * cachable, and the other is not? 3244 */ 3245 printf("%s: overlapping windows\n", 3246 sc->sc_dev.dv_xname); 3247 } else { 3248 win[1].win_limit = chainp->wc_end & mask; 3249 } 3250 } 3251 } 3252 3253 pc = sc->sc_pc; 3254 tag = sc->sc_tag; 3255 pci_conf_write(pc, tag, offs, win[0].win_start); 3256 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3257 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3258 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3259 DPRINTF(("--pccbb_winset: win0 [0x%lx, 0x%lx), win1 [0x%lx, 0x%lx)\n", 3260 (unsigned long)pci_conf_read(pc, tag, offs), 3261 (unsigned long)pci_conf_read(pc, tag, offs + 4) + align, 3262 (unsigned long)pci_conf_read(pc, tag, offs + 8), 3263 (unsigned long)pci_conf_read(pc, tag, offs + 12) + align)); 3264 3265 if (bst == sc->sc_memt) { 3266 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BRIDGE_CONTROL_REG); 3267 3268 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 3269 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 3270 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3271 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 3272 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3273 pci_conf_write(pc, tag, PCI_BRIDGE_CONTROL_REG, bcr); 3274 } 3275 } 3276 3277 #endif /* rbus */ 3278 3279 static bool 3280 pccbb_suspend(device_t dv) 3281 { 3282 struct pccbb_softc *sc = device_private(dv); 3283 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3284 bus_space_handle_t base_memh = sc->sc_base_memh; 3285 pcireg_t reg; 3286 3287 if (sc->sc_pil_intr_enable) 3288 (void)pccbbintr_function(sc); 3289 sc->sc_pil_intr_enable = 0; 3290 3291 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3292 /* Disable interrupts. */ 3293 reg &= ~(CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER); 3294 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3295 /* XXX joerg Disable power to the socket? */ 3296 3297 #ifdef __NO_STRICT_ALIGNMENT 3298 /* XXX - the register is at 0x82, so this access is not valid */ 3299 if (sc->sc_chipset == CB_RX5C47X) 3300 sc->sc_ricoh_misc_ctrl = pci_conf_read(sc->sc_pc, 3301 sc->sc_tag, RICOH_PCI_MISC_CTRL); 3302 #endif 3303 3304 return true; 3305 } 3306 3307 static bool 3308 pccbb_resume(device_t dv) 3309 { 3310 struct pccbb_softc *sc = device_private(dv); 3311 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3312 bus_space_handle_t base_memh = sc->sc_base_memh; 3313 pcireg_t reg; 3314 3315 pccbb_chipinit(sc); 3316 /* setup memory and io space window for CB */ 3317 pccbb_winset(0x1000, sc, sc->sc_memt); 3318 pccbb_winset(0x04, sc, sc->sc_iot); 3319 #ifdef __NO_STRICT_ALIGNMENT 3320 /* XXX - the register is at 0x82, so this access is not valid */ 3321 if (sc->sc_chipset == CB_RX5C47X) 3322 pci_conf_write(sc->sc_pc, sc->sc_tag, 3323 RICOH_PCI_MISC_CTRL, sc->sc_ricoh_misc_ctrl); 3324 #endif 3325 3326 /* CSC Interrupt: Card detect interrupt on */ 3327 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3328 /* Card detect intr is turned on. */ 3329 reg |= CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; 3330 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3331 /* reset interrupt */ 3332 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3333 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3334 3335 /* 3336 * check for card insertion or removal during suspend period. 3337 * XXX: the code can't cope with card swap (remove then 3338 * insert). how can we detect such situation? 3339 */ 3340 (void)pccbbintr(sc); 3341 3342 sc->sc_pil_intr_enable = 1; 3343 3344 return true; 3345 } 3346
Indexes created Fri Sep 26 08:10:20 GMT 2025