pccbb.c revision 1.16
1 /* $NetBSD: pccbb.c,v 1.16 2000/01/23 04:02:19 mycroft Exp $ */ 2 3 /* 4 * Copyright (c) 1998 and 1999 HAYAKAWA Koichi. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by HAYAKAWA Koichi. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 #define CBB_DEBUG 34 #define SHOW_REGS 35 #define PCCBB_PCMCIA_POLL 36 */ 37 /* #define CBB_DEBUG */ 38 39 /* 40 #define CB_PCMCIA_POLL 41 #define CB_PCMCIA_POLL_ONLY 42 #define LEVEL2 43 */ 44 45 #include <sys/types.h> 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/kernel.h> 49 #include <sys/errno.h> 50 #include <sys/ioctl.h> 51 #include <sys/syslog.h> 52 #include <sys/device.h> 53 #include <sys/malloc.h> 54 55 #include <machine/intr.h> 56 #include <machine/bus.h> 57 58 #include <dev/pci/pcivar.h> 59 #include <dev/pci/pcireg.h> 60 #include <dev/pci/pcidevs.h> 61 62 #include <dev/pci/pccbbreg.h> 63 64 #include <dev/cardbus/cardslotvar.h> 65 66 #include <dev/cardbus/cardbusvar.h> 67 68 #include <dev/pcmcia/pcmciareg.h> 69 #include <dev/pcmcia/pcmciavar.h> 70 71 #include <dev/ic/i82365reg.h> 72 #include <dev/ic/i82365var.h> 73 #include <dev/pci/pccbbvar.h> 74 75 #include "locators.h" 76 77 78 #ifndef __NetBSD_Version__ 79 struct cfdriver cbb_cd = { 80 NULL, "cbb", DV_DULL 81 }; 82 #endif 83 84 #if defined CBB_DEBUG 85 #define DPRINTF(x) printf x 86 #define STATIC 87 #else 88 #define DPRINTF(x) 89 #define STATIC static 90 #endif 91 92 93 #ifdef __BROKEN_INDIRECT_CONFIG 94 int pcicbbmatch __P((struct device *, void *, void *)); 95 #else 96 int pcicbbmatch __P((struct device *, struct cfdata *, void *)); 97 #endif 98 void pccbbattach __P((struct device *, struct device *, void *)); 99 int pccbbintr __P((void *)); 100 static void pci113x_insert __P((void *)); 101 102 static int pccbb_detect_card __P((struct pccbb_softc *)); 103 104 static void pccbb_pcmcia_write __P((struct pcic_handle *, int, u_int8_t)); 105 static u_int8_t pccbb_pcmcia_read __P((struct pcic_handle *, int)); 106 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 107 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 108 109 110 STATIC int cb_reset __P((struct pccbb_softc *)); 111 STATIC int cb_detect_voltage __P((struct pccbb_softc *)); 112 STATIC int cbbprint __P((void *, const char *)); 113 114 static int cb_chipset __P((u_int32_t, char const **, int *)); 115 STATIC void pccbb_pcmcia_attach_setup __P((struct pccbb_softc *, struct pcmciabus_attach_args *)); 116 #if 0 117 STATIC void pccbb_pcmcia_attach_card __P((struct pcic_handle *)); 118 STATIC void pccbb_pcmcia_detach_card __P((struct pcic_handle *, int)); 119 STATIC void pccbb_pcmcia_deactivate_card __P((struct pcic_handle *)); 120 #endif 121 122 STATIC int pccbb_ctrl __P((cardbus_chipset_tag_t, int)); 123 STATIC int pccbb_power __P((cardbus_chipset_tag_t, int)); 124 STATIC int pccbb_cardenable __P((struct pccbb_softc *sc, int function)); 125 #if !rbus 126 static int pccbb_io_open __P((cardbus_chipset_tag_t, int, u_int32_t, u_int32_t)); 127 static int pccbb_io_close __P((cardbus_chipset_tag_t, int)); 128 static int pccbb_mem_open __P((cardbus_chipset_tag_t, int, u_int32_t, u_int32_t)); 129 static int pccbb_mem_close __P((cardbus_chipset_tag_t, int)); 130 #endif /* !rbus */ 131 static void *pccbb_intr_establish __P((cardbus_chipset_tag_t, int irq, int level, int (* ih)(void *), void *sc)); 132 static void pccbb_intr_disestablish __P((cardbus_chipset_tag_t ct, void *ih)); 133 134 static cardbustag_t pccbb_make_tag __P((cardbus_chipset_tag_t, int, int, int)); 135 static void pccbb_free_tag __P((cardbus_chipset_tag_t, cardbustag_t)); 136 static cardbusreg_t pccbb_conf_read __P((cardbus_chipset_tag_t, cardbustag_t, int)); 137 static void pccbb_conf_write __P((cardbus_chipset_tag_t, cardbustag_t, int, cardbusreg_t)); 138 static void pccbb_chipinit __P((struct pccbb_softc *)); 139 140 141 STATIC int pccbb_pcmcia_mem_alloc __P((pcmcia_chipset_handle_t, bus_size_t, 142 struct pcmcia_mem_handle *)); 143 STATIC void pccbb_pcmcia_mem_free __P((pcmcia_chipset_handle_t, 144 struct pcmcia_mem_handle *)); 145 STATIC int pccbb_pcmcia_mem_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 146 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *)); 147 STATIC void pccbb_pcmcia_mem_unmap __P((pcmcia_chipset_handle_t, int)); 148 STATIC int pccbb_pcmcia_io_alloc __P((pcmcia_chipset_handle_t, bus_addr_t, 149 bus_size_t, bus_size_t, struct pcmcia_io_handle *)); 150 STATIC void pccbb_pcmcia_io_free __P((pcmcia_chipset_handle_t, 151 struct pcmcia_io_handle *)); 152 STATIC int pccbb_pcmcia_io_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 153 bus_size_t, struct pcmcia_io_handle *, int *)); 154 STATIC void pccbb_pcmcia_io_unmap __P((pcmcia_chipset_handle_t, int)); 155 STATIC void *pccbb_pcmcia_intr_establish __P((pcmcia_chipset_handle_t, 156 struct pcmcia_function *, int, int (*) (void *), void *)); 157 STATIC void pccbb_pcmcia_intr_disestablish __P((pcmcia_chipset_handle_t, void *)); 158 STATIC void pccbb_pcmcia_socket_enable __P((pcmcia_chipset_handle_t)); 159 STATIC void pccbb_pcmcia_socket_disable __P((pcmcia_chipset_handle_t)); 160 STATIC int pccbb_pcmcia_card_detect __P((pcmcia_chipset_handle_t pch)); 161 162 static void pccbb_pcmcia_do_io_map __P((struct pcic_handle *, int)); 163 static void pccbb_pcmcia_wait_ready __P((struct pcic_handle *)); 164 static void pccbb_pcmcia_do_mem_map __P((struct pcic_handle *, int)); 165 166 /* bus-space allocation and disallocation functions */ 167 #if rbus 168 169 static int pccbb_rbus_cb_space_alloc __P((cardbus_chipset_tag_t, rbus_tag_t, 170 bus_addr_t addr, bus_size_t size, 171 bus_addr_t mask, bus_size_t align, 172 int flags, bus_addr_t *addrp, 173 bus_space_handle_t *bshp)); 174 static int pccbb_rbus_cb_space_free __P((cardbus_chipset_tag_t, rbus_tag_t, 175 bus_space_handle_t, bus_size_t)); 176 177 #endif /* rbus */ 178 179 #if rbus 180 181 static int pccbb_open_win __P((struct pccbb_softc *, bus_space_tag_t, bus_addr_t, bus_size_t, bus_space_handle_t, int flags)); 182 static int pccbb_close_win __P((struct pccbb_softc *, bus_space_tag_t, bus_space_handle_t, bus_size_t)); 183 static int pccbb_winlist_insert __P((struct pccbb_win_chain **, bus_addr_t, 184 bus_size_t, bus_space_handle_t, int)); 185 static int pccbb_winlist_delete __P((struct pccbb_win_chain **, 186 bus_space_handle_t, bus_size_t)); 187 static void pccbb_winset __P((bus_addr_t align, struct pccbb_softc *, 188 bus_space_tag_t)); 189 void pccbb_winlist_show(struct pccbb_win_chain *); 190 191 #endif /* rbus */ 192 193 /* for config_defer */ 194 static void pccbb_pci_callback __P((struct device *)); 195 196 197 #if defined SHOW_REGS 198 static void cb_show_regs __P((pci_chipset_tag_t pc, pcitag_t tag, bus_space_tag_t memt, bus_space_handle_t memh)); 199 #endif 200 201 202 203 struct cfattach cbb_pci_ca = { 204 sizeof(struct pccbb_softc), pcicbbmatch, pccbbattach 205 }; 206 207 208 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 209 pccbb_pcmcia_mem_alloc, 210 pccbb_pcmcia_mem_free, 211 pccbb_pcmcia_mem_map, 212 pccbb_pcmcia_mem_unmap, 213 pccbb_pcmcia_io_alloc, 214 pccbb_pcmcia_io_free, 215 pccbb_pcmcia_io_map, 216 pccbb_pcmcia_io_unmap, 217 pccbb_pcmcia_intr_establish, 218 pccbb_pcmcia_intr_disestablish, 219 pccbb_pcmcia_socket_enable, 220 pccbb_pcmcia_socket_disable, 221 pccbb_pcmcia_card_detect 222 }; 223 224 #if rbus 225 static struct cardbus_functions pccbb_funcs = { 226 pccbb_rbus_cb_space_alloc, 227 pccbb_rbus_cb_space_free, 228 pccbb_intr_establish, 229 pccbb_intr_disestablish, 230 pccbb_ctrl, 231 pccbb_power, 232 pccbb_make_tag, 233 pccbb_free_tag, 234 pccbb_conf_read, 235 pccbb_conf_write, 236 }; 237 #else 238 static struct cardbus_functions pccbb_funcs = { 239 pccbb_ctrl, 240 pccbb_power, 241 pccbb_mem_open, 242 pccbb_mem_close, 243 pccbb_io_open, 244 pccbb_io_close, 245 pccbb_intr_establish, 246 pccbb_intr_disestablish, 247 pccbb_make_tag, 248 pccbb_conf_read, 249 pccbb_conf_write, 250 }; 251 #endif 252 253 254 255 256 int 257 pcicbbmatch(parent, match, aux) 258 struct device *parent; 259 #ifdef __BROKEN_INDIRECT_CONFIG 260 void *match; 261 #else 262 struct cfdata *match; 263 #endif 264 void *aux; 265 { 266 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 267 268 if(PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 269 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 270 PCI_INTERFACE(pa->pa_class) == 0) { 271 return 1; 272 } 273 274 return 0; 275 } 276 277 278 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 279 | ((prod) << PCI_PRODUCT_SHIFT)) 280 281 282 struct yenta_chipinfo { 283 pcireg_t yc_id; /* vendor tag | product tag */ 284 const char *yc_name; 285 int yc_chiptype; 286 int yc_flags; 287 } yc_chipsets[] = { 288 /* Texas Instruments chips */ 289 {MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), "TI1130", CB_TI113X, 290 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 291 {MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), "TI1131", CB_TI113X, 292 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 293 294 {MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), "TI1250", CB_TI12XX, 295 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 296 {MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), "TI1220", CB_TI12XX, 297 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 298 {MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), "TI1221", CB_TI12XX, 299 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 300 {MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), "TI1225", CB_TI12XX, 301 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 302 {MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), "TI1251", CB_TI12XX, 303 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 304 {MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), "TI1251B", CB_TI12XX, 305 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 306 {MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), "TI1211", CB_TI12XX, 307 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 308 {MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), "TI1420", CB_TI12XX, 309 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 310 {MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), "TI1450", CB_TI12XX, 311 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 312 {MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI2030), "TI2030", CB_UNKNOWN, 313 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 314 315 /* Ricoh chips */ 316 {MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), "Rx5C475", 317 CB_RX5C47X, PCCBB_PCMCIA_MEM_32}, 318 {MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), "RL5C476", 319 CB_RX5C47X, PCCBB_PCMCIA_MEM_32}, 320 {MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), "Rx5C477", 321 CB_RX5C47X, PCCBB_PCMCIA_MEM_32}, 322 {MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), "Rx5C478", 323 CB_RX5C47X, PCCBB_PCMCIA_MEM_32}, 324 325 {MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), "Rx5C465", 326 CB_RX5C46X, PCCBB_PCMCIA_MEM_32}, 327 {MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), "Rx5C466", 328 CB_RX5C46X, PCCBB_PCMCIA_MEM_32}, 329 330 /* Toshiba products */ 331 {MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), "ToPIC95", 332 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 333 {MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), "ToPIC95B", 334 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 335 {MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), "ToPIC97", 336 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 337 {MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), "ToPIC100", 338 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 339 340 /* Cirrus Logic products */ 341 {MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), "CL-PD683X", 342 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 343 {MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), "CL-PD683X", 344 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 345 346 /* sentinel, or Generic chip */ 347 {0 /* null id */, "unknown", CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 348 }; 349 350 351 352 static int 353 cb_chipset(pci_id, namep, flagp) 354 u_int32_t pci_id; 355 char const **namep; 356 int *flagp; 357 { 358 int loopend = sizeof(yc_chipsets)/sizeof(yc_chipsets[0]); 359 struct yenta_chipinfo *ycp, *ycend; 360 361 ycend = yc_chipsets + loopend; 362 363 for (ycp =yc_chipsets; ycp < ycend && pci_id != ycp->yc_id; ++ycp); 364 365 if (ycp == ycend) { 366 /* not found */ 367 ycp = yc_chipsets + loopend - 1; /* to point the sentinel */ 368 } 369 370 if (namep != NULL) { 371 *namep = ycp->yc_name; 372 } 373 374 if (flagp != NULL) { 375 *flagp = ycp->yc_flags; 376 } 377 378 return ycp->yc_chiptype; 379 } 380 381 382 383 static void 384 pccbb_shutdown(void *arg) 385 { 386 struct pccbb_softc *sc = arg; 387 pcireg_t command; 388 389 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 390 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 0); 391 392 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 393 394 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 395 PCI_COMMAND_MASTER_ENABLE); 396 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 397 398 } 399 400 void 401 pccbbattach(parent, self, aux) 402 struct device *parent; 403 struct device *self; 404 void *aux; 405 { 406 struct pccbb_softc *sc = (void *)self; 407 struct pci_attach_args *pa = aux; 408 pci_chipset_tag_t pc = pa->pa_pc; 409 pcireg_t sock_base, busreg; 410 bus_addr_t sockbase; 411 char const *name; 412 int flags; 413 414 sc->sc_chipset = cb_chipset(pa->pa_id, &name, &flags); 415 printf(" (%s), chipflags %d\n", name, flags); 416 417 #if rbus 418 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 419 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 420 #endif /* rbus */ 421 422 sc->sc_base_memh = 0; 423 424 /* 425 * MAP socket registers and ExCA registers on memory-space 426 * When no valid address is set on socket base registers (on pci 427 * config space), get it not polite way. 428 */ 429 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 430 431 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 432 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 433 /* The address must be valid. */ 434 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 435 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 436 NULL)) { 437 printf("%s: can't map socket base address 0x%x\n", sc->sc_dev.dv_xname, 438 sock_base); 439 /* I think it's funny: socket base registers must be mapped on 440 memory space, but ... */ 441 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 0, 442 &sc->sc_base_memt, &sc->sc_base_memh, 443 &sockbase, NULL)) { 444 printf("%s: can't map socket base address 0x%lx: io mode\n", 445 sc->sc_dev.dv_xname, sockbase); 446 /* give up... allocate register space via rbus. */ 447 sc->sc_base_memh = 0; 448 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 449 } 450 } else { 451 DPRINTF(("%s: socket base address 0x%lx\n", 452 sc->sc_dev.dv_xname, sockbase)); 453 } 454 } 455 456 457 sc->sc_mem_start = 0; /* XXX */ 458 sc->sc_mem_end = 0xffffffff; /* XXX */ 459 460 /* 461 * When interrupt isn't routed correctly, give up probing cbb and do 462 * not kill pcic-compatible port. 463 */ 464 if ((0 == pa->pa_intrline) || (255 == pa->pa_intrline)) { 465 printf(" Do not use %s because of intr unconfig.\n", sc->sc_dev.dv_xname); 466 return; 467 } 468 469 /* 470 * When bus number isn't set correctly, give up using 32-bit CardBus 471 * mode. 472 */ 473 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 474 #if notyet 475 if (((busreg >> 8) & 0xff) == 0) { 476 printf(" CardBus on %s will not be configured, because of bus no unconfig.\n", sc->sc_dev.dv_xname); 477 flags |= PCCBB_PCMCIA_16BITONLY; 478 } 479 #endif 480 481 /* pccbb_machdep.c end */ 482 483 484 #if defined CBB_DEBUG 485 { 486 static char *intrname[5] = {"NON", "A", "B", "C", "D"}; 487 printf(" intrpin %s, intrtag %d\n", intrname[pa->pa_intrpin], 488 pa->pa_intrline); 489 } 490 #endif 491 492 493 /* setup softc */ 494 sc->sc_pc = pc; 495 sc->sc_iot = pa->pa_iot; 496 sc->sc_memt = pa->pa_memt; 497 sc->sc_dmat = pa->pa_dmat; 498 sc->sc_tag = pa->pa_tag; 499 sc->sc_function = pa->pa_function; 500 501 sc->sc_intrline = pa->pa_intrline; 502 sc->sc_intrtag = pa->pa_intrtag; 503 sc->sc_intrpin = pa->pa_intrpin; 504 505 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 506 507 /* bus bridge initialisation */ 508 pccbb_chipinit(sc); 509 510 shutdownhook_establish(pccbb_shutdown, sc); 511 512 #if __NetBSD_Version__ > 103060000 513 config_defer(self, pccbb_pci_callback); 514 #else 515 pccbb_pci_callback(self); 516 #endif 517 } 518 519 520 521 522 static void 523 pccbb_pci_callback(self) 524 struct device *self; 525 { 526 struct pccbb_softc *sc = (void *)self; 527 pci_chipset_tag_t pc = sc->sc_pc; 528 bus_space_tag_t base_memt; 529 bus_space_handle_t base_memh; 530 u_int32_t maskreg; 531 pci_intr_handle_t ih; 532 const char *intrstr = NULL; 533 bus_addr_t sockbase; 534 struct cbslot_attach_args cba; 535 struct pcmciabus_attach_args paa; 536 struct cardslot_attach_args caa; 537 struct cardslot_softc *csc; 538 539 if (0 == sc->sc_base_memh) { 540 /* The socket registers aren't mapped correctly. */ 541 #if rbus 542 if (rbus_space_alloc(sc->sc_rbus_memt, 543 0, /* address: I don't mind where it is mapped */ 544 0x1000, /* size */ 545 0x0fff, /* mask */ 546 (sc->sc_chipset == CB_RX5C47X || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, /* align */ 547 0, /* flags */ 548 &sockbase, &sc->sc_base_memh)) { 549 return; 550 } 551 sc->sc_base_memt = sc->sc_memt; 552 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 553 DPRINTF(("%s: CardBus resister address 0x%lx -> 0x%x\n", 554 sc->sc_dev.dv_xname, sockbase, pci_conf_read(pc, sc->sc_tag, PCI_SOCKBASE))); 555 #else 556 sc->sc_base_memt = sc->sc_memt; 557 #if !defined CBB_PCI_BASE 558 #define CBB_PCI_BASE 0x20000000 559 #endif 560 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 561 0x1000, /* size */ 562 0x1000, /* alignment */ 563 0, /* boundary */ 564 0, /* flags */ 565 &sockbase, &sc->sc_base_memh)) { 566 /* cannot allocate memory space */ 567 return; 568 } 569 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 570 DPRINTF(("%s: CardBus resister address 0x%x -> 0x%x\n",sc->sc_dev.dv_xname, 571 sock_base, pci_conf_read(pc, sc->sc_tag, PCI_SOCKBASE))); 572 #endif 573 } 574 575 base_memt = sc->sc_base_memt; /* socket regs memory tag */ 576 base_memh = sc->sc_base_memh; /* socket regs memory handle */ 577 578 579 /* CSC Interrupt: Card detect interrupt on */ 580 maskreg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 581 maskreg |= CB_SOCKET_MASK_CD; /* Card detect intr is turned on. */ 582 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, maskreg); 583 /* reset interrupt */ 584 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, 585 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT)); 586 587 588 /* Map and establish the interrupt. */ 589 if (pci_intr_map(pc, sc->sc_intrtag, sc->sc_intrpin, 590 sc->sc_intrline, &ih)) { 591 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 592 return; 593 } 594 intrstr = pci_intr_string(pc, ih); 595 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 596 597 if (sc->sc_ih == NULL) { 598 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 599 if (intrstr != NULL) { 600 printf(" at %s", intrstr); 601 } 602 printf("\n"); 603 return; 604 } 605 606 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 607 608 { 609 u_int32_t sockstat = bus_space_read_4(base_memt,base_memh, CB_SOCKET_STAT); 610 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { /* card exist */ 611 sc->sc_flags |= CBB_CARDEXIST; 612 } 613 } 614 615 /* 616 * attach cardbus 617 */ 618 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 619 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 620 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 621 622 /* initialise cbslot_attach */ 623 cba.cba_busname = "cardbus"; 624 cba.cba_iot = sc->sc_iot; 625 cba.cba_memt = sc->sc_memt; 626 cba.cba_dmat = sc->sc_dmat; 627 cba.cba_function = 0; 628 cba.cba_bus = (busreg >> 8) & 0x0ff; 629 cba.cba_cc = (void *)sc; 630 cba.cba_cf = &pccbb_funcs; 631 cba.cba_intrline = sc->sc_intrline; 632 633 #if rbus 634 cba.cba_rbus_iot = sc->sc_rbus_iot; 635 cba.cba_rbus_memt = sc->sc_rbus_memt; 636 #endif 637 638 cba.cba_cacheline = PCI_CACHELINE(bhlc); 639 cba.cba_lattimer = PCI_CB_LATENCY(busreg); 640 641 printf("%s: cacheline 0x%x lattimer 0x%x\n", sc->sc_dev.dv_xname, 642 cba.cba_cacheline, cba.cba_lattimer); 643 printf("%s: bhlc 0x%x lscp 0x%x\n", sc->sc_dev.dv_xname, 644 bhlc, busreg); 645 #if defined SHOW_REGS 646 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, sc->sc_base_memh); 647 #endif 648 } 649 650 pccbb_pcmcia_attach_setup(sc, &paa); 651 caa.caa_cb_attach = NULL; 652 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 653 caa.caa_cb_attach = &cba; 654 } 655 caa.caa_16_attach = &paa; 656 caa.caa_ph = &sc->sc_pcmcia_h; 657 658 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 659 DPRINTF(("pccbbattach: found cardslot\n")); 660 sc->sc_csc = csc; 661 } 662 663 return; 664 } 665 666 667 668 static void 669 pccbb_chipinit(sc) 670 struct pccbb_softc *sc; 671 { 672 pci_chipset_tag_t pc = sc->sc_pc; 673 pcitag_t tag = sc->sc_tag; 674 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory tag */ 675 bus_space_handle_t base_memh = sc->sc_base_memh; /* socket regs memory handle */ 676 pcireg_t cbctrl; 677 678 /* 679 * Set PCI command reg. 680 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 681 */ 682 { 683 pcireg_t command = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 684 685 /* I believe it is harmless. */ 686 command |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 687 PCI_COMMAND_MASTER_ENABLE); 688 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, command); 689 } 690 691 /* 692 * Set CardBus latency timer 693 */ 694 { 695 pcireg_t pci_lscp = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 696 if (PCI_CB_LATENCY(pci_lscp) < 0x20) { 697 pci_lscp &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 698 pci_lscp |= (0x20 << PCI_CB_LATENCY_SHIFT); 699 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, pci_lscp); 700 } 701 DPRINTF(("CardBus latency timer 0x%x (%x)\n", PCI_CB_LATENCY(pci_lscp), 702 pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 703 } 704 705 /* 706 * Set PCI latency timer 707 */ 708 { 709 pcireg_t pci_bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG); 710 if (PCI_LATTIMER(pci_bhlc) < 0x10) { 711 pci_bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 712 pci_bhlc |= (0x10 << PCI_LATTIMER_SHIFT); 713 pci_conf_write(pc, tag, PCI_BHLC_REG, pci_bhlc); 714 } 715 DPRINTF(("PCI latency timer 0x%x (%x)\n", PCI_LATTIMER(pci_bhlc), 716 pci_conf_read(pc, tag, PCI_BHLC_REG))); 717 } 718 719 /* disable Legacy IO */ 720 721 switch (sc->sc_chipset) { 722 case CB_RX5C46X: /* fallthrogh */ 723 #if 0 724 case CB_RX5C47X: 725 #endif 726 /* 727 * The legacy pcic io-port on Ricoh CardBus bridges cannot be 728 * disabled by substituting 0 into PCI_LEGACY register. Ricoh 729 * CardBus bridges have special bits on Bridge control reg (addr 730 * 0x3e on PCI config space). 731 */ 732 { 733 pcireg_t bcri = pci_conf_read(pc, tag, PCI_BCR_INTR); 734 bcri &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 735 pci_conf_write(pc, tag, PCI_BCR_INTR, bcri); 736 } 737 break; 738 default: 739 /* XXX: I don't know proper way to kill Legacy IO properly. */ 740 pci_conf_write(pc, tag, PCI_LEGACY, 0x0); 741 break; 742 } 743 744 745 746 /* 747 * Interrupt routing: use PCI interrupt 748 */ 749 { 750 u_int32_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 751 bcr &= ~CB_BCR_INTR_IREQ_ENABLE; /* use PCI Intr */ 752 bcr |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 753 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 754 } 755 756 if (CB_TI113X == sc->sc_chipset) { 757 cbctrl = pci_conf_read(pc, tag, PCI_CBCTRL); 758 if (0 == sc->sc_function) { 759 cbctrl |= PCI113X_CBCTRL_PCI_IRQ_ENA; 760 } 761 cbctrl |= PCI113X_CBCTRL_PCI_IRQ_ENA; /* XXX: bug in PCI113X */ 762 cbctrl |= PCI113X_CBCTRL_PCI_CSC; /* CSC intr enable */ 763 cbctrl &= ~PCI113X_CBCTRL_PCI_INTR; /* functional intr prohibit */ 764 cbctrl &= ~PCI113X_CBCTRL_INT_MASK; /* prohibit ISA routing */ 765 pci_conf_write(pc, tag, PCI_CBCTRL, cbctrl); 766 767 /* set ExCA regs: PCI113X required to be set bit 4 at Interrupt 768 and General Register, which is IRQ Enable Register, and clear 769 bit 3:0 to zero in order to route CSC interrupt to PCI 770 interrupt pin. */ 771 bus_space_write_1(base_memt, base_memh, 0x0803, 0x10); 772 /* set ExCA regs: prohibit all pcmcia-style CSC intr. */ 773 bus_space_write_1(base_memt, base_memh, 0x0805, 0x00); 774 #if 1 775 DPRINTF(("ExCA regs:")); 776 DPRINTF((" 0x803: %02x", bus_space_read_1(base_memt, base_memh, 0x803))); 777 DPRINTF((" 0x805: %02x", bus_space_read_1(base_memt, base_memh, 0x805))); 778 DPRINTF((" 0x81e: %02x\n", bus_space_read_1(base_memt,base_memh,0x81e))); 779 #endif 780 } else if (sc->sc_chipset == CB_TI12XX) { 781 cbctrl = pci_conf_read(pc, tag, PCI_CBCTRL); 782 cbctrl &= ~PCI12XX_CBCTRL_INT_MASK; /* intr routing reset */ 783 pci_conf_write(pc, tag, PCI_CBCTRL, cbctrl); 784 /* 785 * set ExCA regs: PCI12XX required to be set bit 4 at Interrupt 786 * and General Register, which is IRQ Enable Register, and clear 787 * bit 3:0 to zero in order to route CSC interrupt to PCI 788 * interrupt pin. 789 */ 790 bus_space_write_1(base_memt, base_memh, 0x0803, 0x10); 791 /* set ExCA regs: prohibit all pcmcia-style CSC intr. */ 792 bus_space_write_1(base_memt, base_memh, 0x0805, 0x00); 793 } else if (sc->sc_chipset == CB_TOPIC95B) { 794 cardbusreg_t sock_ctrl, slot_ctrl; 795 796 sock_ctrl = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 797 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, 798 sock_ctrl | TOPIC_SOCKET_CTRL_SCR_IRQSEL); 799 800 slot_ctrl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 801 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", sc->sc_dev.dv_xname, 802 slot_ctrl)); 803 slot_ctrl |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 804 TOPIC_SLOT_CTRL_ID_LOCK); 805 slot_ctrl |= TOPIC_SLOT_CTRL_CARDBUS; 806 slot_ctrl &= ~TOPIC_SLOT_CTRL_SWDETECT; 807 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slot_ctrl); 808 DPRINTF(("0x%x\n", slot_ctrl)); 809 } 810 811 /* close all memory and io windows */ 812 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 813 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 814 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 815 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 816 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 817 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 818 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 819 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 820 821 return; 822 } 823 824 825 826 /* 827 * attach pccard bus 828 */ 829 STATIC void 830 pccbb_pcmcia_attach_setup(sc, paa) 831 struct pccbb_softc *sc; 832 struct pcmciabus_attach_args *paa; 833 { 834 struct pcic_handle *ph = &sc->sc_pcmcia_h; 835 #if rbus 836 rbus_tag_t rb; 837 #endif 838 839 /* initialise pcmcia part in pccbb_softc */ 840 ph->ph_parent = (struct device *)sc; 841 ph->sock = sc->sc_function; 842 ph->flags = 0; 843 ph->shutdown = 0; 844 ph->ih_irq = sc->sc_intrline; 845 ph->ph_bus_t = sc->sc_base_memt; 846 ph->ph_bus_h = sc->sc_base_memh; 847 ph->ph_read = pccbb_pcmcia_read; 848 ph->ph_write = pccbb_pcmcia_write; 849 sc->sc_pct = &pccbb_pcmcia_funcs; 850 851 Pcic_write(ph, PCIC_CSC_INTR, 0); 852 Pcic_read(ph, PCIC_CSC); 853 854 /* initialise pcmcia bus attachment */ 855 paa->paa_busname = "pcmcia"; 856 paa->pct = sc->sc_pct; 857 paa->pch = ph; 858 paa->iobase = 0; /* I don't use them */ 859 paa->iosize = 0; 860 #if rbus 861 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 862 paa->iobase = rb->rb_start + rb->rb_offset; 863 paa->iosize = rb->rb_end - rb->rb_start; 864 #endif 865 866 return; 867 } 868 869 870 #if 0 871 STATIC void 872 pccbb_pcmcia_attach_card(ph) 873 struct pcic_handle *ph; 874 { 875 if (ph->flags & PCIC_FLAG_CARDP) { 876 panic("pccbb_pcmcia_attach_card: already attached"); 877 } 878 879 /* call the MI attach function */ 880 pcmcia_card_attach(ph->pcmcia); 881 882 ph->flags |= PCIC_FLAG_CARDP; 883 } 884 885 886 STATIC void 887 pccbb_pcmcia_detach_card(ph, flags) 888 struct pcic_handle *ph; 889 int flags; 890 { 891 if (!(ph->flags & PCIC_FLAG_CARDP)) { 892 panic("pccbb_pcmcia_detach_card: already detached"); 893 } 894 895 ph->flags &= ~PCIC_FLAG_CARDP; 896 897 /* call the MI detach function */ 898 pcmcia_card_detach(ph->pcmcia, flags); 899 } 900 #endif 901 902 903 904 905 /* 906 * int pccbbintr(arg) 907 * void *arg; 908 * This routine handles the interrupt from Yenta PCI-CardBus bridge 909 * itself. 910 */ 911 int 912 pccbbintr(arg) 913 void *arg; 914 { 915 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 916 u_int32_t sockevent; 917 bus_space_tag_t memt = sc->sc_base_memt; 918 bus_space_handle_t memh = sc->sc_base_memh; 919 u_int32_t sockstate; 920 921 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 922 if (0 == sockevent) { /* not for me */ 923 return 0; 924 } else { 925 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); /* reset bit */ 926 } 927 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 928 929 if (sockevent & CB_SOCKET_EVENT_CD) { 930 if (CB_SOCKET_STAT_CD == (sockstate & CB_SOCKET_STAT_CD)) { 931 /* A card should be removed. */ 932 if (sc->sc_flags & CBB_CARDEXIST) { 933 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 934 DPRINTF((" card removed, 0x%08x\n", sockstate)); 935 sc->sc_flags &= ~CBB_CARDEXIST; 936 if (sc->sc_csc->sc_status & CARDSLOT_STATUS_CARD_16) { 937 #if 0 938 struct pcic_handle *ph = &sc->sc_pcmcia_h; 939 940 pcmcia_card_deactivate(ph->pcmcia); 941 pccbb_pcmcia_socket_disable(ph); 942 pccbb_pcmcia_detach_card(ph, DETACH_FORCE); 943 #endif 944 cardslot_event_throw(sc->sc_csc, CARDSLOT_EVENT_REMOVAL_16); 945 } else if (sc->sc_csc->sc_status & CARDSLOT_STATUS_CARD_CB) { 946 /* Cardbus intr removed */ 947 cardslot_event_throw(sc->sc_csc, CARDSLOT_EVENT_REMOVAL_CB); 948 } 949 } 950 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD)) { 951 if (sc->sc_flags & CBB_INSERTING) { 952 untimeout(pci113x_insert, sc); 953 } 954 timeout(pci113x_insert, sc, hz/10); 955 sc->sc_flags |= CBB_INSERTING; 956 } 957 } else { 958 DPRINTF(("%s: sockevent = %b\n", 959 sc->sc_dev.dv_xname, sockevent, PCCBB_SOCKEVENT_BITS)); 960 DPRINTF(("%s: sockstate = %b\n", 961 sc->sc_dev.dv_xname, 962 sockstate, PCCBB_SOCKSTATE_BITS)); 963 } 964 965 return 1; 966 } 967 968 969 970 static void 971 pci113x_insert(arg) 972 void *arg; 973 { 974 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 975 u_int32_t sockevent, sockstate; 976 977 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 978 CB_SOCKET_EVENT); 979 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 980 CB_SOCKET_STAT); 981 982 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 983 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 984 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 985 sc->sc_flags |= CBB_CARDEXIST; 986 /* call pccard intterupt handler here */ 987 if (sockstate & CB_SOCKET_STAT_16BIT) { 988 /* 16-bit card found */ 989 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 990 cardslot_event_throw(sc->sc_csc, CARDSLOT_EVENT_INSERTION_16); 991 } else if (sockstate & CB_SOCKET_STAT_CB) { 992 /* cardbus card fuond */ 993 /* cardbus_attach_card(sc->sc_csc); */ 994 cardslot_event_throw(sc->sc_csc, CARDSLOT_EVENT_INSERTION_CB); 995 } else { 996 /* who are you? */ 997 } 998 } else { 999 timeout(pci113x_insert, sc, hz/10); 1000 } 1001 } 1002 1003 1004 1005 1006 #define PCCBB_PCMCIA_OFFSET 0x800 1007 static u_int8_t 1008 pccbb_pcmcia_read(ph, reg) 1009 struct pcic_handle *ph; 1010 int reg; 1011 { 1012 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg); 1013 } 1014 1015 1016 1017 static void 1018 pccbb_pcmcia_write(ph, reg, val) 1019 struct pcic_handle *ph; 1020 int reg; 1021 u_int8_t val; 1022 { 1023 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, val); 1024 } 1025 1026 1027 1028 1029 /* 1030 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1031 */ 1032 STATIC int 1033 pccbb_ctrl(ct, command) 1034 cardbus_chipset_tag_t ct; 1035 int command; 1036 { 1037 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1038 1039 switch(command) { 1040 case CARDBUS_CD: 1041 if (2 == pccbb_detect_card(sc)) { 1042 int retval = 0; 1043 int status = cb_detect_voltage(sc); 1044 if (PCCARD_VCC_5V & status) { 1045 retval |= CARDBUS_5V_CARD; 1046 } 1047 if (PCCARD_VCC_3V & status) { 1048 retval |= CARDBUS_3V_CARD; 1049 } 1050 if (PCCARD_VCC_XV & status) { 1051 retval |= CARDBUS_XV_CARD; 1052 } 1053 if (PCCARD_VCC_YV & status) { 1054 retval |= CARDBUS_YV_CARD; 1055 } 1056 return retval; 1057 } else { 1058 return 0; 1059 } 1060 break; 1061 case CARDBUS_RESET: 1062 return cb_reset(sc); 1063 break; 1064 case CARDBUS_IO_ENABLE: /* fallthrough */ 1065 case CARDBUS_IO_DISABLE: /* fallthrough */ 1066 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1067 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1068 case CARDBUS_BM_ENABLE: /* fallthrough */ 1069 case CARDBUS_BM_DISABLE: /* fallthrough */ 1070 return pccbb_cardenable(sc, command); 1071 break; 1072 } 1073 1074 return 0; 1075 } 1076 1077 1078 1079 /* 1080 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1081 * This function returns true when it succeeds and returns false when 1082 * it fails. 1083 */ 1084 STATIC int 1085 pccbb_power(ct, command) 1086 cardbus_chipset_tag_t ct; 1087 int command; 1088 { 1089 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1090 1091 u_int32_t status, sock_ctrl; 1092 bus_space_tag_t memt = sc->sc_base_memt; 1093 bus_space_handle_t memh = sc->sc_base_memh; 1094 1095 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1096 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1097 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1098 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1099 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1100 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1101 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1102 "UNKNOWN", 1103 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1104 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1105 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1106 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1107 "UNKNOWN", 1108 command)); 1109 1110 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1111 sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1112 1113 switch (command & CARDBUS_VCCMASK) { 1114 case CARDBUS_VCC_UC: 1115 break; 1116 case CARDBUS_VCC_5V: 1117 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1118 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1119 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1120 } else { 1121 printf("%s: BAD voltage request: no 5 V card\n", sc->sc_dev.dv_xname); 1122 } 1123 break; 1124 case CARDBUS_VCC_3V: 1125 if (CB_SOCKET_STAT_3VCARD & status) { 1126 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1127 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1128 } else { 1129 printf("%s: BAD voltage request: no 3.3 V card\n", sc->sc_dev.dv_xname); 1130 } 1131 break; 1132 case CARDBUS_VCC_0V: 1133 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1134 break; 1135 default: 1136 return 0; /* power NEVER changed */ 1137 break; 1138 } 1139 1140 switch (command & CARDBUS_VPPMASK) { 1141 case CARDBUS_VPP_UC: 1142 break; 1143 case CARDBUS_VPP_0V: 1144 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1145 break; 1146 case CARDBUS_VPP_VCC: 1147 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1148 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1149 break; 1150 case CARDBUS_VPP_12V: 1151 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1152 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1153 break; 1154 } 1155 1156 #if 0 1157 DPRINTF(("sock_ctrl: %x\n", sock_ctrl)); 1158 #endif 1159 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1160 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1161 1162 delay(20*1000); /* wait 20 ms: Vcc setup time */ 1163 /* XXX 1164 delay 200 ms: though the standard defines that the Vcc set-up time 1165 is 20 ms, some PC-Card bridge requires longer duration. 1166 */ 1167 delay(200*1000); 1168 1169 1170 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1171 printf("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1172 sc->sc_dev.dv_xname, sock_ctrl ,status); 1173 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1174 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1175 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V": 1176 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V": 1177 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV": 1178 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV": 1179 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V": 1180 "UNKNOWN", 1181 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC": 1182 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ?"CARDBUS_VPP_12V": 1183 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ?"CARDBUS_VPP_VCC": 1184 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1185 "UNKNOWN", 1186 command)); 1187 #if 0 1188 if (command == (CARDBUS_VCC_0V | CARDBUS_VPP_0V)) { 1189 u_int32_t force = bus_space_read_4(memt, memh, CB_SOCKET_FORCE); 1190 /* Reset Bad Vcc request */ 1191 force &= ~CB_SOCKET_FORCE_BADVCC; 1192 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, force); 1193 printf("new status 0x%x\n", bus_space_read_4(memt, memh,CB_SOCKET_STAT)); 1194 return 1; 1195 } 1196 #endif 1197 return 0; 1198 } 1199 return 1; /* power changed correctly */ 1200 } 1201 1202 1203 1204 1205 1206 1207 #if defined CB_PCMCIA_POLL 1208 struct cb_poll_str { 1209 void *arg; 1210 int (* func) __P((void *)); 1211 int level; 1212 pccard_chipset_tag_t ct; 1213 int count; 1214 }; 1215 1216 static struct cb_poll_str cb_poll[10]; 1217 static int cb_poll_n = 0; 1218 1219 static void cb_pcmcia_poll __P((void *arg)); 1220 1221 static void 1222 cb_pcmcia_poll(arg) 1223 void *arg; 1224 { 1225 struct cb_poll_str *poll = arg; 1226 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1227 struct pccbb_softc *sc = psc->cpc_parent; 1228 int s; 1229 u_int32_t spsr; /* socket present-state reg */ 1230 1231 timeout(cb_pcmcia_poll, arg, hz/10); 1232 switch (poll->level) { 1233 case IPL_NET: 1234 s = splnet(); 1235 break; 1236 case IPL_BIO: 1237 s = splbio(); 1238 break; 1239 case IPL_TTY: /* fallthrough */ 1240 default: 1241 s = spltty(); 1242 break; 1243 } 1244 1245 spsr = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_STAT); 1246 1247 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1248 if (!(spsr & 0x40)) { /* CINT low */ 1249 #else 1250 if (1) { 1251 #endif 1252 if ((*poll->func)(poll->arg) == 1) { 1253 ++poll->count; 1254 printf("intr: reported from poller, 0x%x\n", spsr); 1255 #if defined LEVEL2 1256 } else { 1257 printf("intr: miss! 0x%x\n", spsr); 1258 #endif 1259 } 1260 } 1261 splx(s); 1262 } 1263 #endif /* defined CB_PCMCIA_POLL */ 1264 1265 1266 1267 1268 /* 1269 * static int pccbb_detect_card(struct pccbb_softc *sc) 1270 * return value: 0 if no card exists. 1271 * 1 if 16-bit card exists. 1272 * 2 if cardbus card exists. 1273 */ 1274 static int 1275 pccbb_detect_card(sc) 1276 struct pccbb_softc *sc; 1277 { 1278 bus_space_handle_t base_memh = sc->sc_base_memh; 1279 bus_space_tag_t base_memt = sc->sc_base_memt; 1280 u_int32_t sockstat = bus_space_read_4(base_memt,base_memh, CB_SOCKET_STAT); 1281 int retval = 0; 1282 1283 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { /* CD1 and CD2 asserted */ 1284 /* card must be present */ 1285 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { /* NOTACARD DEASSERTED */ 1286 if (CB_SOCKET_STAT_CB & sockstat) { /* CardBus mode */ 1287 retval = 2; 1288 } else if (CB_SOCKET_STAT_16BIT & sockstat) { /* 16-bit mode */ 1289 retval = 1; 1290 } 1291 } 1292 } 1293 return retval; 1294 } 1295 1296 1297 1298 1299 /* 1300 * STATIC int cb_reset(struct pccbb_softc *sc) 1301 * This function resets CardBus card. 1302 */ 1303 STATIC int 1304 cb_reset(sc) 1305 struct pccbb_softc *sc; 1306 { 1307 /* 1308 * Reset Assert at least 20 ms 1309 * Some machines request longer duration. 1310 */ 1311 int reset_duration = (sc->sc_chipset == CB_RX5C47X ? 400*1000 : 40*1000); 1312 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1313 1314 bcr |= (0x40 << 16); /* Reset bit Assert (bit 6 at 0x3E) */ 1315 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1316 delay(reset_duration); 1317 1318 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1319 bcr &= ~(0x40 << 16); /* Reset bit Deassert (bit 6 at 0x3E) */ 1320 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1321 delay(reset_duration); 1322 } 1323 /* No card found on the slot. Keep Reset. */ 1324 return 1; 1325 } 1326 1327 1328 1329 1330 /* 1331 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1332 * This function detect card Voltage. 1333 */ 1334 STATIC int 1335 cb_detect_voltage(sc) 1336 struct pccbb_softc *sc; 1337 { 1338 u_int32_t psr; /* socket present-state reg */ 1339 bus_space_tag_t iot = sc->sc_base_memt; 1340 bus_space_handle_t ioh = sc->sc_base_memh; 1341 int vol = PCCARD_VCC_UKN; /* set 0 */ 1342 1343 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1344 1345 if (0x400u & psr) { 1346 vol |= PCCARD_VCC_5V; 1347 } 1348 if (0x800u & psr) { 1349 vol |= PCCARD_VCC_3V; 1350 } 1351 1352 return vol; 1353 } 1354 1355 1356 1357 1358 1359 1360 STATIC int 1361 cbbprint(aux, pcic) 1362 void *aux; 1363 const char *pcic; 1364 { 1365 /* 1366 struct cbslot_attach_args *cba = aux; 1367 1368 if (cba->cba_slot >= 0) { 1369 printf(" slot %d", cba->cba_slot); 1370 } 1371 */ 1372 return UNCONF; 1373 } 1374 1375 1376 1377 1378 /* 1379 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1380 * This function enables and disables the card 1381 */ 1382 STATIC int 1383 pccbb_cardenable(sc, function) 1384 struct pccbb_softc *sc; 1385 int function; 1386 { 1387 u_int32_t command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1388 1389 DPRINTF(("pccbb_cardenable:")); 1390 switch (function) { 1391 case CARDBUS_IO_ENABLE: 1392 command |= PCI_COMMAND_IO_ENABLE; 1393 break; 1394 case CARDBUS_IO_DISABLE: 1395 command &= ~PCI_COMMAND_IO_ENABLE; 1396 break; 1397 case CARDBUS_MEM_ENABLE: 1398 command |= PCI_COMMAND_MEM_ENABLE; 1399 break; 1400 case CARDBUS_MEM_DISABLE: 1401 command &= ~PCI_COMMAND_MEM_ENABLE; 1402 break; 1403 case CARDBUS_BM_ENABLE: 1404 command |= PCI_COMMAND_MASTER_ENABLE; 1405 break; 1406 case CARDBUS_BM_DISABLE: 1407 command &= ~PCI_COMMAND_MASTER_ENABLE; 1408 break; 1409 default: 1410 return 0; 1411 } 1412 1413 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1414 DPRINTF((" command reg 0x%x\n", command)); 1415 return 1; 1416 } 1417 1418 1419 1420 1421 1422 1423 #if !rbus 1424 /* 1425 * int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1426 */ 1427 static int 1428 pccbb_io_open(ct, win, start, end) 1429 cardbus_chipset_tag_t ct; 1430 int win; 1431 u_int32_t start, end; 1432 { 1433 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1434 int basereg; 1435 int limitreg; 1436 1437 if ((win < 0) || (win > 2)) { 1438 #if defined DIAGNOSTIC 1439 printf("cardbus_io_open: window out of range %d\n", win); 1440 #endif 1441 return 0; 1442 } 1443 1444 basereg = win*8 + 0x2c; 1445 limitreg = win*8 + 0x30; 1446 1447 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1448 start, basereg, end, limitreg)); 1449 1450 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1451 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1452 return 1; 1453 } 1454 1455 /* 1456 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1457 */ 1458 static int 1459 pccbb_io_close(ct, win) 1460 cardbus_chipset_tag_t ct; 1461 int win; 1462 { 1463 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1464 int basereg; 1465 int limitreg; 1466 1467 if ((win < 0) || (win > 2)) { 1468 #if defined DIAGNOSTIC 1469 printf("cardbus_io_close: window out of range %d\n", win); 1470 #endif 1471 return 0; 1472 } 1473 1474 basereg = win*8 + 0x2c; 1475 limitreg = win*8 + 0x30; 1476 1477 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1478 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1479 return 1; 1480 } 1481 1482 /* 1483 * int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1484 */ 1485 static int 1486 pccbb_mem_open(ct, win, start, end) 1487 cardbus_chipset_tag_t ct; 1488 int win; 1489 u_int32_t start, end; 1490 { 1491 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1492 int basereg; 1493 int limitreg; 1494 1495 if ((win < 0) || (win > 2)) { 1496 #if defined DIAGNOSTIC 1497 printf("cardbus_mem_open: window out of range %d\n", win); 1498 #endif 1499 return 0; 1500 } 1501 1502 basereg = win*8 + 0x1c; 1503 limitreg = win*8 + 0x20; 1504 1505 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1506 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1507 return 1; 1508 } 1509 1510 1511 /* 1512 * int pccbb_mem_close(cardbus_chipset_tag_t, int) 1513 */ 1514 static int 1515 pccbb_mem_close(ct, win) 1516 cardbus_chipset_tag_t ct; 1517 int win; 1518 { 1519 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1520 int basereg; 1521 int limitreg; 1522 1523 if ((win < 0) || (win > 2)) { 1524 #if defined DIAGNOSTIC 1525 printf("cardbus_mem_close: window out of range %d\n", win); 1526 #endif 1527 return 0; 1528 } 1529 1530 basereg = win*8 + 0x1c; 1531 limitreg = win*8 + 0x20; 1532 1533 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1534 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1535 return 1; 1536 } 1537 #endif 1538 1539 1540 1541 static void * 1542 pccbb_intr_establish(ct, irq, level, func, arg) 1543 cardbus_chipset_tag_t ct; 1544 int irq, level; 1545 int (* func) __P((void *)); 1546 void *arg; 1547 { 1548 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1549 1550 switch (sc->sc_chipset) { 1551 case CB_TI113X: 1552 { 1553 pcireg_t cbctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1554 cbctrl |= PCI113X_CBCTRL_PCI_INTR; /* functional intr enabled */ 1555 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, cbctrl); 1556 } 1557 break; 1558 default: 1559 break; 1560 } 1561 1562 return pci_intr_establish(sc->sc_pc, irq, level, func, arg); 1563 } 1564 1565 1566 1567 1568 static void 1569 pccbb_intr_disestablish(ct, ih) 1570 cardbus_chipset_tag_t ct; 1571 void *ih; 1572 { 1573 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1574 1575 switch (sc->sc_chipset) { 1576 case CB_TI113X: 1577 { 1578 pcireg_t cbctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1579 cbctrl &= ~PCI113X_CBCTRL_PCI_INTR; /* functional intr disabled */ 1580 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, cbctrl); 1581 } 1582 break; 1583 default: 1584 break; 1585 } 1586 1587 pci_intr_disestablish(sc->sc_pc, ih); 1588 } 1589 1590 1591 1592 1593 1594 #if defined SHOW_REGS 1595 static void 1596 cb_show_regs(pc, tag, memt, memh) 1597 pci_chipset_tag_t pc; 1598 pcitag_t tag; 1599 bus_space_tag_t memt; 1600 bus_space_handle_t memh; 1601 { 1602 int i; 1603 printf("PCI config regs:"); 1604 for (i = 0; i < 0x50; i += 4) { 1605 if (i % 16 == 0) { 1606 printf("\n 0x%02x:", i); 1607 } 1608 printf(" %08x", pci_conf_read(pc, tag, i)); 1609 } 1610 for (i = 0x80; i < 0xb0; i += 4) { 1611 if (i % 16 == 0) { 1612 printf("\n 0x%02x:", i); 1613 } 1614 printf(" %08x", pci_conf_read(pc, tag, i)); 1615 } 1616 1617 if (memh == 0) { 1618 printf("\n"); 1619 return; 1620 } 1621 1622 printf("\nsocket regs:"); 1623 for (i = 0; i <= 0x10; i += 0x04) { 1624 printf(" %08x", bus_space_read_4(memt, memh, i)); 1625 } 1626 printf("\nExCA regs:"); 1627 for (i = 0; i < 0x08; ++i) { 1628 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1629 } 1630 printf("\n"); 1631 return; 1632 } 1633 #endif 1634 1635 1636 1637 /* 1638 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1639 * int busno, int devno, int function) 1640 * This is the function to make a tag to access config space of 1641 * a CardBus Card. It works same as pci_conf_read. 1642 */ 1643 static cardbustag_t 1644 pccbb_make_tag(cc, busno, devno, function) 1645 cardbus_chipset_tag_t cc; 1646 int busno, devno, function; 1647 { 1648 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1649 1650 return pci_make_tag(sc->sc_pc, busno, devno, function); 1651 } 1652 1653 1654 static void 1655 pccbb_free_tag(cc, tag) 1656 cardbus_chipset_tag_t cc; 1657 cardbustag_t tag; 1658 { 1659 } 1660 1661 1662 /* 1663 * static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t cc, 1664 * cardbustag_t tag, int offset) 1665 * This is the function to read the config space of a CardBus Card. 1666 * It works same as pci_conf_read. 1667 */ 1668 static cardbusreg_t 1669 pccbb_conf_read(cc, tag, offset) 1670 cardbus_chipset_tag_t cc; 1671 cardbustag_t tag; 1672 int offset; /* register offset */ 1673 { 1674 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1675 1676 return pci_conf_read(sc->sc_pc, tag, offset); 1677 } 1678 1679 1680 1681 /* 1682 * static void pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, 1683 * int offs, cardbusreg_t val) 1684 * This is the function to write the config space of a CardBus Card. 1685 * It works same as pci_conf_write. 1686 */ 1687 static void 1688 pccbb_conf_write(cc, tag, reg, val) 1689 cardbus_chipset_tag_t cc; 1690 cardbustag_t tag; 1691 int reg; /* register offset */ 1692 cardbusreg_t val; 1693 { 1694 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1695 1696 pci_conf_write(sc->sc_pc, tag, reg, val); 1697 } 1698 1699 1700 1701 1702 1703 #if 0 1704 STATIC int 1705 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1706 bus_addr_t start, bus_size_t size, 1707 bus_size_t align, bus_addr_t mask, /* address line width */ 1708 int speed, int flags, /* bus width */ 1709 bus_space_handle_t *iohp) 1710 #endif 1711 1712 1713 /* 1714 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1715 * bus_addr_t start, bus_size_t size, 1716 * bus_size_t align, 1717 * struct pcmcia_io_handle *pcihp 1718 * 1719 * This function only allocates I/O region for pccard. This function 1720 * never maps the allcated region to pccard I/O area. 1721 * 1722 * XXX: The interface of this function is not very good, I believe. 1723 */ 1724 STATIC int 1725 pccbb_pcmcia_io_alloc(pch, start, size, align, pcihp) 1726 pcmcia_chipset_handle_t pch; 1727 bus_addr_t start; /* start address */ 1728 bus_size_t size; 1729 bus_size_t align; 1730 struct pcmcia_io_handle *pcihp; 1731 { 1732 struct pcic_handle *ph = (struct pcic_handle *)pch; 1733 bus_addr_t ioaddr; 1734 int flags = 0; 1735 bus_space_tag_t iot; 1736 bus_space_handle_t ioh; 1737 #if rbus 1738 rbus_tag_t rb; 1739 #endif 1740 if (align == 0) { 1741 align = size; /* XXX: funny??? */ 1742 } 1743 1744 1745 /* 1746 * Allocate some arbitrary I/O space. 1747 */ 1748 1749 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 1750 1751 #if rbus 1752 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 1753 if (rbus_space_alloc(rb, start, size, 0x3ff /* XXX: I assume all card decode lower 10 bits by its hardware */, 1754 align, 0, &ioaddr, &ioh)) { 1755 return 1; 1756 } 1757 #else 1758 if (start) { 1759 ioaddr = start; 1760 if (bus_space_map(iot, start, size, 0, &ioh)) { 1761 return 1; 1762 } 1763 DPRINTF(("pccbb_pcmcia_io_alloc map port %lx+%lx\n", 1764 (u_long) ioaddr, (u_long) size)); 1765 } else { 1766 flags |= PCMCIA_IO_ALLOCATED; 1767 if (bus_space_alloc(iot, 0x700/* ph->sc->sc_iobase */, 1768 0x800/* ph->sc->sc_iobase + ph->sc->sc_iosize*/, 1769 size, align, 0, 0, &ioaddr, &ioh)) { 1770 /* No room be able to be get. */ 1771 return 1; 1772 } 1773 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 1774 (u_long) ioaddr, (u_long) size)); 1775 } 1776 #endif 1777 1778 pcihp->iot = iot; 1779 pcihp->ioh = ioh; 1780 pcihp->addr = ioaddr; 1781 pcihp->size = size; 1782 pcihp->flags = flags; 1783 1784 return 0; 1785 } 1786 1787 1788 1789 1790 1791 /* 1792 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 1793 * struct pcmcia_io_handle *pcihp) 1794 * 1795 * This function only frees I/O region for pccard. 1796 * 1797 * XXX: The interface of this function is not very good, I believe. 1798 */ 1799 void 1800 pccbb_pcmcia_io_free(pch, pcihp) 1801 pcmcia_chipset_handle_t pch; 1802 struct pcmcia_io_handle *pcihp; 1803 { 1804 #if !rbus 1805 bus_space_tag_t iot = pcihp->iot; 1806 #endif 1807 bus_space_handle_t ioh = pcihp->ioh; 1808 bus_size_t size = pcihp->size; 1809 1810 #if rbus 1811 struct pccbb_softc *sc = (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 1812 rbus_tag_t rb = sc->sc_rbus_iot; 1813 1814 rbus_space_free(rb, ioh, size, NULL); 1815 #else 1816 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 1817 bus_space_free(iot, ioh, size); 1818 else 1819 bus_space_unmap(iot, ioh, size); 1820 #endif 1821 } 1822 1823 1824 1825 /* 1826 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 1827 * bus_addr_t offset, bus_size_t size, 1828 * struct pcmcia_io_handle *pcihp, 1829 * int *windowp) 1830 * 1831 * This function maps the allocated I/O region to pccard. This function 1832 * never allocates any I/O region for pccard I/O area. I don't 1833 * understand why the original authors of pcmciabus separated alloc and 1834 * map. I believe the two must be unite. 1835 * 1836 * XXX: no wait timing control? 1837 */ 1838 int 1839 pccbb_pcmcia_io_map(pch, width, offset, size, pcihp, windowp) 1840 pcmcia_chipset_handle_t pch; 1841 int width; 1842 bus_addr_t offset; 1843 bus_size_t size; 1844 struct pcmcia_io_handle *pcihp; 1845 int *windowp; 1846 { 1847 struct pcic_handle *ph = (struct pcic_handle *) pch; 1848 bus_addr_t ioaddr = pcihp->addr + offset; 1849 int i, win; 1850 #if defined CBB_DEBUG 1851 static char *width_names[] = { "dynamic", "io8", "io16" }; 1852 #endif 1853 1854 /* Sanity check I/O handle. */ 1855 1856 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 1857 panic("pccbb_pcmcia_io_map iot is bogus"); 1858 } 1859 1860 /* XXX Sanity check offset/size. */ 1861 1862 win = -1; 1863 for (i = 0; i < PCIC_IO_WINS; i++) { 1864 if ((ph->ioalloc & (1 << i)) == 0) { 1865 win = i; 1866 ph->ioalloc |= (1 << i); 1867 break; 1868 } 1869 } 1870 1871 if (win == -1) { 1872 return 1; 1873 } 1874 1875 *windowp = win; 1876 1877 /* XXX this is pretty gross */ 1878 1879 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 1880 win, width_names[width], (u_long) ioaddr, (u_long) size)); 1881 1882 /* XXX wtf is this doing here? */ 1883 1884 #if 0 1885 printf(" port 0x%lx", (u_long) ioaddr); 1886 if (size > 1) { 1887 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 1888 } 1889 #endif 1890 1891 ph->io[win].addr = ioaddr; 1892 ph->io[win].size = size; 1893 ph->io[win].width = width; 1894 1895 /* actual dirty register-value changing in the function below. */ 1896 pccbb_pcmcia_do_io_map(ph, win); 1897 1898 return 0; 1899 } 1900 1901 1902 1903 /* 1904 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 1905 * 1906 * This function changes register-value to map I/O region for pccard. 1907 */ 1908 static void 1909 pccbb_pcmcia_do_io_map(ph, win) 1910 struct pcic_handle *ph; 1911 int win; 1912 { 1913 static u_int8_t pcic_iowidth[3] = { 1914 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 1915 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | PCIC_IOCTL_IO0_DATASIZE_8BIT, 1916 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | PCIC_IOCTL_IO0_DATASIZE_16BIT, 1917 }; 1918 1919 #define PCIC_SIA_START_LOW 0 1920 #define PCIC_SIA_START_HIGH 1 1921 #define PCIC_SIA_STOP_LOW 2 1922 #define PCIC_SIA_STOP_HIGH 3 1923 1924 int regbase_win = 0x8 + win*0x04; 1925 u_int8_t ioctl, enable; 1926 1927 DPRINTF(("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx width %d\n", 1928 win, (long) ph->io[win].addr, (long) ph->io[win].size, 1929 ph->io[win].width * 8)); 1930 1931 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 1932 ph->io[win].addr & 0xff); 1933 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 1934 (ph->io[win].addr >> 8) & 0xff); 1935 1936 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 1937 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 1938 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 1939 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 1940 1941 ioctl = Pcic_read(ph, PCIC_IOCTL); 1942 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 1943 switch (win) { 1944 case 0: 1945 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 1946 PCIC_IOCTL_IO0_IOCS16SRC_MASK | PCIC_IOCTL_IO0_DATASIZE_MASK); 1947 ioctl |= pcic_iowidth[ph->io[win].width]; 1948 enable |= PCIC_ADDRWIN_ENABLE_IO0; 1949 break; 1950 case 1: 1951 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 1952 PCIC_IOCTL_IO1_IOCS16SRC_MASK | PCIC_IOCTL_IO1_DATASIZE_MASK); 1953 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 1954 enable |= PCIC_ADDRWIN_ENABLE_IO1; 1955 break; 1956 } 1957 Pcic_write(ph, PCIC_IOCTL, ioctl); 1958 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 1959 #if defined CBB_DEBUG 1960 { 1961 u_int8_t start_low = Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 1962 u_int8_t start_high = Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 1963 u_int8_t stop_low = Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 1964 u_int8_t stop_high = Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 1965 printf(" start %02x %02x, stop %02x %02x, ioctl %02x enable %02x\n", 1966 start_low, start_high, stop_low, stop_high, ioctl, enable); 1967 } 1968 #endif 1969 } 1970 1971 1972 1973 /* 1974 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 1975 * 1976 * This function unmapss I/O region. No return value. 1977 */ 1978 STATIC void 1979 pccbb_pcmcia_io_unmap(pch, win) 1980 pcmcia_chipset_handle_t pch; 1981 int win; 1982 { 1983 struct pcic_handle *ph = (struct pcic_handle *)pch; 1984 int reg; 1985 1986 if (win >= PCIC_IO_WINS || win < 0) { 1987 panic("pccbb_pcmcia_io_unmap: window out of range"); 1988 } 1989 1990 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 1991 switch (win) { 1992 case 0: 1993 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 1994 break; 1995 case 1: 1996 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 1997 break; 1998 } 1999 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2000 2001 ph->ioalloc &= ~(1 << win); 2002 } 2003 2004 2005 2006 2007 2008 /* 2009 * static void pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 2010 * 2011 * This function enables the card. All information is stored in 2012 * the first argument, pcmcia_chipset_handle_t. 2013 */ 2014 static void 2015 pccbb_pcmcia_wait_ready(ph) 2016 struct pcic_handle *ph; 2017 { 2018 int i; 2019 2020 DPRINTF(("pccbb_pcmcia_wait_ready: status 0x%02x\n", 2021 Pcic_read(ph, PCIC_IF_STATUS))); 2022 2023 for (i = 0; i < 10000; i++) { 2024 if (Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) { 2025 return; 2026 } 2027 delay(500); 2028 #ifdef CBB_DEBUG 2029 if ((i > 5000) && (i%100 == 99)) 2030 printf("."); 2031 #endif 2032 } 2033 2034 #ifdef DIAGNOSTIC 2035 printf("pcic_wait_ready: ready never happened, status = %02x\n", 2036 Pcic_read(ph, PCIC_IF_STATUS)); 2037 #endif 2038 } 2039 2040 2041 2042 /* 2043 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2044 * 2045 * This function enables the card. All information is stored in 2046 * the first argument, pcmcia_chipset_handle_t. 2047 */ 2048 STATIC void 2049 pccbb_pcmcia_socket_enable(pch) 2050 pcmcia_chipset_handle_t pch; 2051 { 2052 struct pcic_handle *ph = (struct pcic_handle *)pch; 2053 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2054 int cardtype, win; 2055 u_int8_t power, intr; 2056 pcireg_t spsr; 2057 int voltage; 2058 #define PCIC_INTR_PCI PCIC_INTR_ENABLE 2059 2060 /* this bit is mostly stolen from pcic_attach_card */ 2061 2062 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2063 2064 /* get card Vcc info */ 2065 2066 spsr = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_STAT); 2067 if (spsr & CB_SOCKET_STAT_5VCARD) { 2068 DPRINTF(("5V card\n")); 2069 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2070 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2071 DPRINTF(("3V card\n")); 2072 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2073 } else { 2074 printf("?V card, 0x%x\n", spsr); /* XXX */ 2075 return; 2076 } 2077 2078 /* assert reset bit */ 2079 2080 intr = Pcic_read(ph, PCIC_INTR); 2081 intr &= ~PCIC_INTR_RESET; 2082 intr |= PCIC_INTR_PCI; /* XXX */ 2083 Pcic_write(ph, PCIC_INTR, intr); 2084 2085 /* disable socket i/o: negate output enable bit */ 2086 2087 power = Pcic_read(ph, PCIC_PWRCTL); 2088 power &= ~PCIC_PWRCTL_OE; 2089 Pcic_write(ph, PCIC_PWRCTL, power); 2090 2091 /* power down the socket to reset it, clear the card reset pin */ 2092 2093 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2094 2095 /* 2096 * wait 200ms until power fails (Tpf). Then, wait 100ms since 2097 * we are changing Vcc (Toff). 2098 */ 2099 /* delay(300*1000); too much */ 2100 2101 /* power up the socket */ 2102 pccbb_power(sc, voltage); 2103 2104 /* 2105 * wait 100ms until power raise (Tpr) and 20ms to become 2106 * stable (Tsu(Vcc)). 2107 * 2108 * some machines require some more time to be settled 2109 * (another 200ms is added here). 2110 */ 2111 /* delay((100 + 20 + 200)*1000); too much */ 2112 2113 power = Pcic_read(ph, PCIC_PWRCTL); 2114 Pcic_write(ph, PCIC_PWRCTL, power | PCIC_PWRCTL_OE); 2115 2116 /* 2117 * hold RESET at least 10us. 2118 */ 2119 delay(10); 2120 delay(2*1000); /* XXX: TI1130 requires it. */ 2121 delay(20*1000); /* XXX: TI1130 requires it. */ 2122 2123 /* clear the reset flag */ 2124 2125 intr = Pcic_read(ph, PCIC_INTR); 2126 Pcic_write(ph, PCIC_INTR, intr | PCIC_INTR_RESET); 2127 2128 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 2129 2130 delay(20000); 2131 2132 /* wait for the chip to finish initializing */ 2133 2134 pccbb_pcmcia_wait_ready(ph); 2135 2136 /* zero out the address windows */ 2137 2138 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2139 2140 /* set the card type */ 2141 2142 cardtype = pcmcia_card_gettype(ph->pcmcia); 2143 2144 intr = Pcic_read(ph, PCIC_INTR); 2145 intr &= ~PCIC_INTR_CARDTYPE_MASK; 2146 intr |= ((cardtype == PCMCIA_IFTYPE_IO) ? 2147 PCIC_INTR_CARDTYPE_IO : 2148 PCIC_INTR_CARDTYPE_MEM); 2149 Pcic_write(ph, PCIC_INTR, intr); 2150 2151 DPRINTF(("%s: pccbb_pcmcia_socket_enable %02x cardtype %s %02x\n", 2152 ph->ph_parent->dv_xname, ph->sock, 2153 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2154 2155 /* reinstall all the memory and io mappings */ 2156 2157 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2158 if (ph->memalloc & (1 << win)) { 2159 pccbb_pcmcia_do_mem_map(ph, win); 2160 } 2161 } 2162 2163 for (win = 0; win < PCIC_IO_WINS; ++win) { 2164 if (ph->ioalloc & (1 << win)) { 2165 pccbb_pcmcia_do_io_map(ph, win); 2166 } 2167 } 2168 } 2169 2170 2171 2172 /* 2173 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2174 * 2175 * This function disables the card. All information is stored in 2176 * the first argument, pcmcia_chipset_handle_t. 2177 */ 2178 STATIC void 2179 pccbb_pcmcia_socket_disable(pch) 2180 pcmcia_chipset_handle_t pch; 2181 { 2182 struct pcic_handle *ph = (struct pcic_handle *)pch; 2183 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2184 u_int8_t power, intr; 2185 2186 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2187 2188 /* reset signal asserting... */ 2189 2190 intr = Pcic_read(ph, PCIC_INTR); 2191 intr &= ~PCIC_INTR_RESET; 2192 Pcic_write(ph, PCIC_INTR, intr); 2193 delay(2*1000); 2194 2195 /* power down the socket */ 2196 power = Pcic_read(ph, PCIC_PWRCTL); 2197 power &= ~PCIC_PWRCTL_OE; 2198 Pcic_write(ph, PCIC_PWRCTL, power); 2199 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2200 /* 2201 * wait 300ms until power fails (Tpf). 2202 */ 2203 delay(300 * 1000); 2204 } 2205 2206 2207 2208 /* 2209 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2210 * 2211 * This function detects whether a card is in the slot or not. 2212 * If a card is inserted, return 1. Otherwise, return 0. 2213 */ 2214 STATIC int 2215 pccbb_pcmcia_card_detect(pch) 2216 pcmcia_chipset_handle_t pch; 2217 { 2218 struct pcic_handle *ph = (struct pcic_handle *)pch; 2219 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2220 2221 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2222 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2223 } 2224 2225 2226 2227 #if 0 2228 STATIC int 2229 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2230 bus_addr_t start, bus_size_t size, 2231 bus_size_t align, 2232 int speed, int flags, /* bus width */ 2233 bus_space_tag_t *memtp 2234 bus_space_handle_t *memhp) 2235 #endif 2236 2237 2238 /* 2239 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2240 * bus_size_t size, 2241 * struct pcmcia_mem_handle *pcmhp) 2242 * 2243 * This function only allocates memory region for pccard. This 2244 * function never maps the allcated region to pccard memory area. 2245 * 2246 * XXX: Why the argument of start address is not in? 2247 */ 2248 STATIC int 2249 pccbb_pcmcia_mem_alloc(pch, size, pcmhp) 2250 pcmcia_chipset_handle_t pch; 2251 bus_size_t size; 2252 struct pcmcia_mem_handle *pcmhp; 2253 { 2254 struct pcic_handle *ph = (struct pcic_handle *)pch; 2255 bus_space_handle_t memh; 2256 bus_addr_t addr; 2257 bus_size_t sizepg; 2258 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2259 #if rbus 2260 rbus_tag_t rb; 2261 #endif 2262 2263 /* out of sc->memh, allocate as many pages as necessary */ 2264 2265 /* convert size to PCIC pages */ 2266 /* 2267 This is not enough; when the requested region is on the 2268 page boundaries, this may calculate wrong result. 2269 */ 2270 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2271 #if 0 2272 if (sizepg > PCIC_MAX_MEM_PAGES) { 2273 return 1; 2274 } 2275 #endif 2276 2277 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2278 return 1; 2279 } 2280 2281 addr = 0; /* XXX gcc -Wuninitialized */ 2282 2283 #if rbus 2284 rb = sc->sc_rbus_memt; 2285 if (rbus_space_alloc(rb, 0, sizepg*PCIC_MEM_PAGESIZE, 2286 sizepg*PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 2287 0, &addr, &memh)) { 2288 return 1; 2289 } 2290 2291 #else 2292 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2293 sizepg*PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2294 0 /* boundary */, 0 /* flags */, 2295 &addr, &memh)) { 2296 return 1; 2297 } 2298 #endif 2299 2300 DPRINTF(("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, realsize 0x%lx\n", 2301 addr, size, sizepg*PCIC_MEM_PAGESIZE)); 2302 2303 pcmhp->memt = sc->sc_memt; 2304 pcmhp->memh = memh; 2305 pcmhp->addr = addr; 2306 pcmhp->size = size; 2307 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2308 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2309 pcmhp->mhandle = 0; 2310 /* No offset??? Funny. */ 2311 2312 return 0; 2313 } 2314 2315 2316 2317 2318 /* 2319 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2320 * struct pcmcia_mem_handle *pcmhp) 2321 * 2322 * This function release the memory space allocated by the fuction 2323 * pccbb_pcmcia_mem_alloc(). 2324 */ 2325 STATIC void 2326 pccbb_pcmcia_mem_free(pch, pcmhp) 2327 pcmcia_chipset_handle_t pch; 2328 struct pcmcia_mem_handle *pcmhp; 2329 { 2330 #if rbus 2331 struct pcic_handle *ph = (struct pcic_handle *)pch; 2332 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2333 2334 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2335 #else 2336 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2337 #endif 2338 } 2339 2340 2341 2342 2343 /* 2344 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2345 * 2346 * This function release the memory space allocated by the fuction 2347 * pccbb_pcmcia_mem_alloc(). 2348 */ 2349 STATIC void 2350 pccbb_pcmcia_do_mem_map(ph, win) 2351 struct pcic_handle *ph; 2352 int win; 2353 { 2354 int regbase_win; 2355 bus_addr_t phys_addr; 2356 bus_addr_t phys_end; 2357 2358 #define PCIC_SMM_START_LOW 0 2359 #define PCIC_SMM_START_HIGH 1 2360 #define PCIC_SMM_STOP_LOW 2 2361 #define PCIC_SMM_STOP_HIGH 3 2362 #define PCIC_CMA_LOW 4 2363 #define PCIC_CMA_HIGH 5 2364 2365 u_int8_t start_low, start_high = 0; 2366 u_int8_t stop_low, stop_high; 2367 u_int8_t off_low, off_high; 2368 u_int8_t mem_window; 2369 int reg; 2370 2371 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2372 int mem8 = (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8; 2373 2374 regbase_win = 0x10 + win*0x08; 2375 2376 phys_addr = ph->mem[win].addr; 2377 phys_end = phys_addr + ph->mem[win].size; 2378 2379 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2380 phys_addr, phys_end, ph->mem[win].offset)); 2381 2382 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2383 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2384 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2385 2386 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; /* bit 19:12 */ 2387 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) /* bit 23:20 */ 2388 | (mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); /* bit 7 on */ 2389 /* bit 31:24, for 32-bit address */ 2390 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; /* bit 31:24 */ 2391 2392 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2393 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2394 2395 if (((struct pccbb_softc *)ph->ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2396 Pcic_write(ph, 0x40 + win, mem_window); 2397 } 2398 2399 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2400 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2401 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2402 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2403 2404 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2405 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2406 2407 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2408 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2409 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2410 | ((kind == PCMCIA_MEM_ATTR) ? 2411 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2412 2413 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2414 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2415 2416 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2417 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2418 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2419 2420 #if defined CBB_DEBUG 2421 { 2422 int r1, r2, r3, r4, r5, r6, r7 = 0; 2423 2424 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2425 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2426 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2427 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2428 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2429 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2430 if (((struct pccbb_softc *)(ph->ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2431 r7 = Pcic_read(ph, 0x40 + win); 2432 } 2433 2434 DPRINTF(("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2435 "%02x%02x", win, r1, r2, r3, r4, r5, r6)); 2436 if (((struct pccbb_softc *)(ph->ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2437 DPRINTF((" %02x",r7)); 2438 } 2439 DPRINTF(("\n")); 2440 } 2441 #endif 2442 } 2443 2444 2445 2446 2447 /* 2448 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2449 * bus_addr_t card_addr, bus_size_t size, 2450 * struct pcmcia_mem_handle *pcmhp, 2451 * bus_addr_t *offsetp, int *windowp) 2452 * 2453 * This function maps memory space allocated by the fuction 2454 * pccbb_pcmcia_mem_alloc(). 2455 */ 2456 STATIC int 2457 pccbb_pcmcia_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 2458 pcmcia_chipset_handle_t pch; 2459 int kind; 2460 bus_addr_t card_addr; 2461 bus_size_t size; 2462 struct pcmcia_mem_handle *pcmhp; 2463 bus_addr_t *offsetp; 2464 int *windowp; 2465 { 2466 struct pcic_handle *ph = (struct pcic_handle *)pch; 2467 bus_addr_t busaddr; 2468 long card_offset; 2469 int win; 2470 2471 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2472 if ((ph->memalloc & (1 << win)) == 0) { 2473 ph->memalloc |= (1 << win); 2474 break; 2475 } 2476 } 2477 2478 if (win == PCIC_MEM_WINS) { 2479 return 1; 2480 } 2481 2482 *windowp = win; 2483 2484 /* XXX this is pretty gross */ 2485 2486 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2487 panic("pccbb_pcmcia_mem_map memt is bogus"); 2488 } 2489 2490 busaddr = pcmhp->addr; 2491 2492 /* 2493 * compute the address offset to the pcmcia address space for the 2494 * pcic. this is intentionally signed. The masks and shifts below 2495 * will cause TRT to happen in the pcic registers. Deal with making 2496 * sure the address is aligned, and return the alignment offset. 2497 */ 2498 2499 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2500 card_addr -= *offsetp; 2501 2502 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2503 "%lx\n", win, (u_long)busaddr, (u_long)*offsetp, (u_long)size, 2504 (u_long)card_addr)); 2505 2506 /* 2507 * include the offset in the size, and decrement size by one, since 2508 * the hw wants start/stop 2509 */ 2510 size += *offsetp - 1; 2511 2512 card_offset = (((long) card_addr) - ((long) busaddr)); 2513 2514 ph->mem[win].addr = busaddr; 2515 ph->mem[win].size = size; 2516 ph->mem[win].offset = card_offset; 2517 ph->mem[win].kind = kind; 2518 2519 pccbb_pcmcia_do_mem_map(ph, win); 2520 2521 return 0; 2522 } 2523 2524 2525 2526 /* 2527 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2528 * int window) 2529 * 2530 * This function unmaps memory space which mapped by the fuction 2531 * pccbb_pcmcia_mem_map(). 2532 */ 2533 STATIC void 2534 pccbb_pcmcia_mem_unmap(pch, window) 2535 pcmcia_chipset_handle_t pch; 2536 int window; 2537 { 2538 struct pcic_handle *ph = (struct pcic_handle *)pch; 2539 int reg; 2540 2541 if (window >= PCIC_MEM_WINS) { 2542 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2543 } 2544 2545 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2546 reg &= ~(1 << window); 2547 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2548 2549 ph->memalloc &= ~(1 << window); 2550 } 2551 2552 2553 2554 #if defined PCCBB_PCMCIA_POLL 2555 struct pccbb_poll_str { 2556 void *arg; 2557 int (* func) __P((void *)); 2558 int level; 2559 struct pcic_handle *ph; 2560 int count; 2561 int num; 2562 }; 2563 2564 static struct pccbb_poll_str pccbb_poll[10]; 2565 static int pccbb_poll_n = 0; 2566 2567 static void pccbb_pcmcia_poll __P((void *arg)); 2568 2569 static void 2570 pccbb_pcmcia_poll(arg) 2571 void *arg; 2572 { 2573 struct pccbb_poll_str *poll = arg; 2574 struct pcic_handle *ph = poll->ph; 2575 struct pccbb_softc *sc = ph->sc; 2576 int s; 2577 u_int32_t spsr; /* socket present-state reg */ 2578 2579 timeout(pccbb_pcmcia_poll, arg, hz*2); 2580 switch (poll->level) { 2581 case IPL_NET: 2582 s = splnet(); 2583 break; 2584 case IPL_BIO: 2585 s = splbio(); 2586 break; 2587 case IPL_TTY: /* fallthrough */ 2588 default: 2589 s = spltty(); 2590 break; 2591 } 2592 2593 spsr = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_STAT); 2594 2595 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2596 if (!(spsr & 0x40)) /* CINT low */ 2597 #else 2598 if (1) 2599 #endif 2600 { 2601 if ((*poll->func)(poll->arg) > 0) { 2602 ++poll->count; 2603 // printf("intr: reported from poller, 0x%x\n", spsr); 2604 #if defined LEVEL2 2605 } else { 2606 printf("intr: miss! 0x%x\n", spsr); 2607 #endif 2608 } 2609 } 2610 splx(s); 2611 } 2612 #endif /* defined CB_PCMCIA_POLL */ 2613 2614 2615 2616 /* 2617 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2618 * struct pcmcia_function *pf, 2619 * int ipl, 2620 * int (*func)(void *), 2621 * void *arg); 2622 * 2623 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2624 */ 2625 STATIC void * 2626 pccbb_pcmcia_intr_establish(pch, pf, ipl, func, arg) 2627 pcmcia_chipset_handle_t pch; 2628 struct pcmcia_function *pf; 2629 int ipl; 2630 int (*func) __P((void *)); 2631 void *arg; 2632 { 2633 struct pcic_handle *ph = (struct pcic_handle *)pch; 2634 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2635 pci_intr_handle_t handle; 2636 void *ih; 2637 2638 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2639 /* what should I do? */ 2640 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2641 DPRINTF(("%s does not provide edge nor pulse interrupt\n", 2642 sc->sc_dev.dv_xname)); 2643 return NULL; 2644 } 2645 /* 2646 * XXX Noooooo! The interrupt flag must set properly!! 2647 * dumb pcmcia driver!! 2648 */ 2649 } 2650 2651 if (pci_intr_map(sc->sc_pc, sc->sc_intrtag, sc->sc_intrpin, 2652 sc->sc_intrline, &handle)) { 2653 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 2654 return NULL; 2655 } 2656 DPRINTF(("pccbb_pcmcia_intr_establish: line %d, handle %d\n", 2657 sc->sc_intrline, handle)); 2658 2659 if (NULL != (ih = pci_intr_establish(sc->sc_pc, handle, ipl, func, arg))) 2660 { 2661 u_int32_t cbctrl; 2662 2663 if ((CB_TI113X == sc->sc_chipset)) { 2664 cbctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 2665 cbctrl |= PCI113X_CBCTRL_PCI_INTR; /* PCI functional intr req */ 2666 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, cbctrl); 2667 } 2668 } 2669 #if defined PCCBB_PCMCIA_POLL 2670 if (pccbb_poll_n < 10) { 2671 pccbb_poll[pccbb_poll_n].arg = arg; 2672 pccbb_poll[pccbb_poll_n].func = func; 2673 pccbb_poll[pccbb_poll_n].level = ipl; 2674 pccbb_poll[pccbb_poll_n].count = 0; 2675 pccbb_poll[pccbb_poll_n].num = pccbb_poll_n; 2676 pccbb_poll[pccbb_poll_n].ph = ph; 2677 timeout(pccbb_pcmcia_poll, &pccbb_poll[pccbb_poll_n++], hz*2); 2678 printf("polling set\n"); 2679 } 2680 #endif 2681 #if defined SHOW_REGS 2682 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, sc->sc_base_memh); 2683 #endif 2684 2685 return ih; 2686 } 2687 2688 2689 2690 2691 /* 2692 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2693 * void *ih) 2694 * 2695 * This function disables PC-Card interrupt. 2696 */ 2697 STATIC void 2698 pccbb_pcmcia_intr_disestablish(pch, ih) 2699 pcmcia_chipset_handle_t pch; 2700 void *ih; 2701 { 2702 struct pcic_handle *ph = (struct pcic_handle *)pch; 2703 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2704 2705 pci_intr_disestablish(sc->sc_pc, ih); 2706 } 2707 2708 2709 2710 2711 #if rbus 2712 /* 2713 * static int 2714 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2715 * bus_addr_t addr, bus_size_t size, 2716 * bus_addr_t mask, bus_size_t align, 2717 * int flags, bus_addr_t *addrp; 2718 * bus_space_handle_t *bshp) 2719 * 2720 * This function allocates a portion of memory or io space for 2721 * clients. This function is called from CardBus card drivers. 2722 */ 2723 static int 2724 pccbb_rbus_cb_space_alloc(ct, rb, addr, size, mask, align, flags, addrp, bshp) 2725 cardbus_chipset_tag_t ct; 2726 rbus_tag_t rb; 2727 bus_addr_t addr; 2728 bus_size_t size; 2729 bus_addr_t mask; 2730 bus_size_t align; 2731 int flags; 2732 bus_addr_t *addrp; 2733 bus_space_handle_t *bshp; 2734 { 2735 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2736 2737 DPRINTF(("pccbb_rbus_cb_space_alloc: adr %lx, size %lx, mask %lx, align %lx\n", addr, size, mask, align)); 2738 2739 if (align == 0) { 2740 align = size; 2741 } 2742 2743 if (rb->rb_bt == sc->sc_memt) { 2744 if (align < 16) { 2745 return 1; 2746 } 2747 } else if (rb->rb_bt == sc->sc_iot) { 2748 if (align < 4) { 2749 return 1; 2750 } 2751 } else { 2752 DPRINTF(("pccbb_rbus_cb_space_alloc: Bus space tag %x is NOT used.\n", 2753 rb->rb_bt)); 2754 return 1; 2755 /* XXX: panic here? */ 2756 } 2757 2758 /* XXX: hack for avoiding ISA image */ 2759 if (mask < 0x3ff) { 2760 mask = 0x3ff; 2761 addr = 0x300; 2762 } 2763 2764 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 2765 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 2766 return 1; 2767 } 2768 2769 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 2770 2771 return 0; 2772 } 2773 2774 2775 2776 2777 2778 /* 2779 * static int 2780 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 2781 * bus_space_handle_t *bshp, bus_size_t size); 2782 * 2783 * This function is called from CardBus card drivers. 2784 */ 2785 static int 2786 pccbb_rbus_cb_space_free(ct, rb, bsh, size) 2787 cardbus_chipset_tag_t ct; 2788 rbus_tag_t rb; 2789 bus_space_handle_t bsh; 2790 bus_size_t size; 2791 { 2792 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2793 bus_space_tag_t bt = rb->rb_bt; 2794 2795 pccbb_close_win(sc, bt, bsh, size); 2796 2797 if (bt == sc->sc_memt) { 2798 } else if (bt == sc->sc_iot) { 2799 } else { 2800 return 1; 2801 /* XXX: panic here? */ 2802 } 2803 2804 return rbus_space_free(rb, bsh, size, NULL); 2805 } 2806 #endif /* rbus */ 2807 2808 2809 #if rbus 2810 2811 static int 2812 pccbb_open_win(sc, bst, addr, size, bsh, flags) 2813 struct pccbb_softc *sc; 2814 bus_space_tag_t bst; 2815 bus_addr_t addr; 2816 bus_size_t size; 2817 bus_space_handle_t bsh; 2818 int flags; 2819 { 2820 struct pccbb_win_chain **top; 2821 bus_addr_t align; 2822 2823 top = &sc->sc_iowindow; 2824 align = 0x04; 2825 if (sc->sc_memt == bst) { 2826 top = &sc->sc_memwindow; 2827 align = 0x1000; 2828 DPRINTF(("using memory window, %x %x %x\n\n", 2829 sc->sc_iot, sc->sc_memt, bst)); 2830 } 2831 2832 if (pccbb_winlist_insert(top, addr, size, bsh, flags)) { 2833 printf("winlist insert fails:\n"); 2834 } 2835 pccbb_winset(align, sc, bst); 2836 2837 return 0; 2838 } 2839 2840 2841 2842 static int 2843 pccbb_close_win(sc, bst, bsh, size) 2844 struct pccbb_softc *sc; 2845 bus_space_tag_t bst; 2846 bus_space_handle_t bsh; 2847 bus_size_t size; 2848 { 2849 struct pccbb_win_chain **top; 2850 bus_addr_t align; 2851 2852 top = &sc->sc_iowindow; 2853 align = 0x04; 2854 if (sc->sc_memt == bst) { 2855 top = &sc->sc_memwindow; 2856 align = 0x1000; 2857 } 2858 2859 if (pccbb_winlist_delete(top, bsh, size)) { 2860 printf("winlist delete fails:\n"); 2861 } 2862 pccbb_winset(align, sc, bst); 2863 2864 return 0; 2865 } 2866 2867 2868 static int 2869 pccbb_winlist_insert(top, start, size, bsh, flags) 2870 struct pccbb_win_chain **top; 2871 bus_addr_t start; 2872 bus_size_t size; 2873 bus_space_handle_t bsh; 2874 int flags; 2875 { 2876 struct pccbb_win_chain *chainp = *top; 2877 struct pccbb_win_chain *before = *top; 2878 struct pccbb_win_chain *elem; 2879 2880 if (*top == NULL) { 2881 if (NULL == (elem = (struct pccbb_win_chain *)malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, M_NOWAIT))) { 2882 return 1; /* fail */ 2883 } 2884 2885 elem->wc_start = start; 2886 elem->wc_end = start + size - 1; 2887 elem->wc_handle = bsh; 2888 elem->wc_flags = flags; 2889 2890 *top = elem; 2891 elem->wc_next = NULL; 2892 return 0; 2893 } 2894 2895 for(; chainp && chainp->wc_start <= start; chainp = chainp->wc_next) { 2896 before = chainp; 2897 } 2898 2899 if (chainp != NULL) { 2900 if (chainp->wc_start < start + size) { 2901 printf("fatal! 0x%lx 0x%lx\n", chainp->wc_start, start+size); 2902 return 1; 2903 } 2904 } 2905 if ((before != *top) && (before->wc_end >= start)) { 2906 printf("fatal!! 0x%lx 0x%lx\n", before->wc_end, start); 2907 return 1; 2908 } 2909 2910 if (NULL == (elem = (struct pccbb_win_chain *)malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, M_NOWAIT))) { 2911 return 1; /* fail */ 2912 } 2913 2914 elem->wc_start = start; 2915 elem->wc_end = start + size - 1; 2916 elem->wc_handle = bsh; 2917 elem->wc_flags = flags; 2918 2919 elem->wc_next = chainp; 2920 if (chainp == *top) { 2921 *top = elem; 2922 } else { 2923 before->wc_next = elem; 2924 } 2925 return 0; 2926 } 2927 2928 2929 2930 2931 static int 2932 pccbb_winlist_delete(top, bsh, size) 2933 struct pccbb_win_chain **top; 2934 bus_space_handle_t bsh; 2935 bus_size_t size; 2936 { 2937 struct pccbb_win_chain *chainp = *top; 2938 struct pccbb_win_chain **before = top; 2939 2940 for (; chainp && chainp->wc_handle != bsh; chainp = chainp->wc_next) { 2941 before = &chainp->wc_next; 2942 } 2943 2944 if (chainp == NULL) { 2945 return 1; /* fail: no candidate to remove */ 2946 } 2947 2948 if (chainp->wc_end - chainp->wc_start != size - 1) { 2949 printf("fatal!!! 0x%lx\n", chainp->wc_start); 2950 return 1; /* fail: no candidate to remove */ 2951 } 2952 2953 *before = chainp->wc_next; 2954 free(chainp, M_DEVBUF); 2955 2956 return 0; 2957 } 2958 2959 2960 2961 static void 2962 pccbb_winset(align, sc, bst) 2963 bus_addr_t align; 2964 struct pccbb_softc *sc; 2965 bus_space_tag_t bst; 2966 { 2967 pci_chipset_tag_t pc; 2968 pcitag_t tag; 2969 bus_addr_t mask = ~(align - 1); 2970 struct { 2971 cardbusreg_t win_start; 2972 cardbusreg_t win_limit; 2973 int win_flags; 2974 } win[2]; 2975 struct pccbb_win_chain *chainp; 2976 int offs; 2977 2978 win[0].win_start = 0xffffffff; 2979 win[0].win_limit = 0; 2980 win[1].win_start = 0xffffffff; 2981 win[1].win_limit = 0; 2982 2983 chainp = sc->sc_iowindow; 2984 offs = 0x2c; 2985 if (sc->sc_memt == bst) { 2986 chainp = sc->sc_memwindow; 2987 offs = 0x1c; 2988 } 2989 2990 if (chainp) { 2991 win[0].win_start = chainp->wc_start & mask; 2992 win[0].win_limit = chainp->wc_end & mask; 2993 win[0].win_flags = chainp->wc_flags; 2994 chainp = chainp->wc_next; 2995 } 2996 2997 for(; chainp; chainp = chainp->wc_next) { 2998 if (win[1].win_start == 0xffffffff) { 2999 /* window 1 is not used */ 3000 if ((win[0].win_flags == chainp->wc_flags) && 3001 (win[0].win_limit + align >= (chainp->wc_start & mask))) { 3002 /* concatinate */ 3003 win[0].win_limit = chainp->wc_end & mask; 3004 } else { 3005 /* make new window */ 3006 win[1].win_start = chainp->wc_start & mask; 3007 win[1].win_limit = chainp->wc_end & mask; 3008 win[1].win_flags = chainp->wc_flags; 3009 } 3010 continue; 3011 } 3012 3013 /* Both windows are engagad. */ 3014 if (win[0].win_flags == win[1].win_flags) { 3015 /* same flags */ 3016 if (win[0].win_flags == chainp->wc_flags) { 3017 if (win[1].win_start - (win[0].win_limit + align) 3018 < (chainp->wc_start & mask) - ((chainp->wc_end & mask) + align)) { 3019 /* merge window 0 and 1, and set win1 to chainp */ 3020 win[0].win_limit = win[1].win_limit; 3021 win[1].win_start = chainp->wc_start & mask; 3022 win[1].win_limit = chainp->wc_end & mask; 3023 } else { 3024 win[1].win_limit = chainp->wc_end & mask; 3025 } 3026 } else { 3027 /* different flags */ 3028 3029 /* concatinate win0 and win1 */ 3030 win[0].win_limit = win[1].win_limit; 3031 /* allocate win[1] to new space */ 3032 win[1].win_start = chainp->wc_start & mask; 3033 win[1].win_limit = chainp->wc_end & mask; 3034 win[1].win_flags = chainp->wc_flags; 3035 } 3036 } else { 3037 /* the flags of win[0] and win[1] is different */ 3038 if (win[0].win_flags == chainp->wc_flags) { 3039 win[0].win_limit = chainp->wc_end & mask; 3040 /* XXX this creates overlapping windows, so what should the 3041 poor bridge do if one is cachable, and the other is not? */ 3042 printf("%s: overlapping windows\n", sc->sc_dev.dv_xname); 3043 } else { 3044 win[1].win_limit = chainp->wc_end & mask; 3045 } 3046 } 3047 } 3048 3049 pc = sc->sc_pc; 3050 tag = sc->sc_tag; 3051 pci_conf_write(pc, tag, offs, win[0].win_start); 3052 pci_conf_write(pc, tag, offs+4, win[0].win_limit); 3053 pci_conf_write(pc, tag, offs+8, win[1].win_start); 3054 pci_conf_write(pc, tag, offs+12, win[1].win_limit); 3055 DPRINTF(("--pccbb_winset: win0 [%x, %lx), win1 [%x, %lx)\n", 3056 pci_conf_read(pc, tag, offs), 3057 pci_conf_read(pc, tag, offs+4) + align, 3058 pci_conf_read(pc, tag, offs+8), 3059 pci_conf_read(pc, tag, offs+12) + align)); 3060 3061 if (bst == sc->sc_memt) { 3062 if (win[0].win_flags & PCCBB_MEM_CACHABLE) { 3063 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3064 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3065 pci_conf_write(pc,tag, PCI_BCR_INTR, bcr); 3066 } 3067 if (win[1].win_flags & PCCBB_MEM_CACHABLE) { 3068 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3069 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3070 pci_conf_write(pc,tag, PCI_BCR_INTR, bcr); 3071 } 3072 } 3073 } 3074 3075 #endif /* rbus */ 3076
Indexes created Mon Sep 29 03:10:08 GMT 2025