pccbb.c revision 1.160
1 /* $NetBSD: pccbb.c,v 1.160 2008/01/02 23:11:34 dyoung Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: pccbb.c,v 1.160 2008/01/02 23:11:34 dyoung Exp $"); 35 36 /* 37 #define CBB_DEBUG 38 #define SHOW_REGS 39 */ 40 41 /* 42 * BROKEN! 43 #define PCCBB_PCMCIA_POLL 44 #define CB_PCMCIA_POLL 45 #define CB_PCMCIA_POLL_ONLY 46 #define LEVEL2 47 */ 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/kernel.h> 52 #include <sys/errno.h> 53 #include <sys/ioctl.h> 54 #include <sys/reboot.h> /* for bootverbose */ 55 #include <sys/syslog.h> 56 #include <sys/device.h> 57 #include <sys/malloc.h> 58 #include <sys/proc.h> 59 60 #include <sys/intr.h> 61 #include <sys/bus.h> 62 63 #include <dev/pci/pcivar.h> 64 #include <dev/pci/pcireg.h> 65 #include <dev/pci/pcidevs.h> 66 67 #include <dev/pci/pccbbreg.h> 68 69 #include <dev/cardbus/cardslotvar.h> 70 71 #include <dev/cardbus/cardbusvar.h> 72 73 #include <dev/pcmcia/pcmciareg.h> 74 #include <dev/pcmcia/pcmciavar.h> 75 76 #include <dev/ic/i82365reg.h> 77 #include <dev/ic/i82365var.h> 78 #include <dev/pci/pccbbvar.h> 79 80 #include "locators.h" 81 82 #ifndef __NetBSD_Version__ 83 struct cfdriver cbb_cd = { 84 NULL, "cbb", DV_DULL 85 }; 86 #endif 87 88 #ifdef CBB_DEBUG 89 #define DPRINTF(x) printf x 90 #define STATIC 91 #else 92 #define DPRINTF(x) 93 #define STATIC static 94 #endif 95 96 int pccbb_burstup = 1; 97 98 /* 99 * delay_ms() is wait in milliseconds. It should be used instead 100 * of delay() if you want to wait more than 1 ms. 101 */ 102 static inline void 103 delay_ms(int millis, void *param) 104 { 105 if (cold) 106 delay(millis * 1000); 107 else 108 tsleep(param, PWAIT, "pccbb", MAX(2, hz * millis / 1000)); 109 } 110 111 int pcicbbmatch(struct device *, struct cfdata *, void *); 112 void pccbbattach(struct device *, struct device *, void *); 113 int pccbbdetach(device_t, int); 114 int pccbbintr(void *); 115 static void pci113x_insert(void *); 116 static int pccbbintr_function(struct pccbb_softc *); 117 118 static int pccbb_detect_card(struct pccbb_softc *); 119 120 static void pccbb_pcmcia_write(struct pcic_handle *, int, u_int8_t); 121 static u_int8_t pccbb_pcmcia_read(struct pcic_handle *, int); 122 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 123 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 124 125 STATIC int cb_reset(struct pccbb_softc *); 126 STATIC int cb_detect_voltage(struct pccbb_softc *); 127 STATIC int cbbprint(void *, const char *); 128 129 static int cb_chipset(u_int32_t, int *); 130 STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *, 131 struct pcmciabus_attach_args *); 132 #if 0 133 STATIC void pccbb_pcmcia_attach_card(struct pcic_handle *); 134 STATIC void pccbb_pcmcia_detach_card(struct pcic_handle *, int); 135 STATIC void pccbb_pcmcia_deactivate_card(struct pcic_handle *); 136 #endif 137 138 STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int); 139 STATIC int pccbb_power(struct pccbb_softc *sc, int); 140 STATIC int pccbb_power_ct(cardbus_chipset_tag_t, int); 141 STATIC int pccbb_cardenable(struct pccbb_softc * sc, int function); 142 #if !rbus 143 static int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 144 static int pccbb_io_close(cardbus_chipset_tag_t, int); 145 static int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 146 static int pccbb_mem_close(cardbus_chipset_tag_t, int); 147 #endif /* !rbus */ 148 static void *pccbb_intr_establish(struct pccbb_softc *, int irq, 149 int level, int (*ih) (void *), void *sc); 150 static void pccbb_intr_disestablish(struct pccbb_softc *, void *ih); 151 152 static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t, int irq, 153 int level, int (*ih) (void *), void *sc); 154 static void pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih); 155 156 static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t, int, int); 157 static void pccbb_free_tag(cardbus_chipset_tag_t, cardbustag_t); 158 static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t, cardbustag_t, int); 159 static void pccbb_conf_write(cardbus_chipset_tag_t, cardbustag_t, int, 160 cardbusreg_t); 161 static void pccbb_chipinit(struct pccbb_softc *); 162 163 STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 164 struct pcmcia_mem_handle *); 165 STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t, 166 struct pcmcia_mem_handle *); 167 STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 168 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *); 169 STATIC void pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t, int); 170 STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 171 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 172 STATIC void pccbb_pcmcia_io_free(pcmcia_chipset_handle_t, 173 struct pcmcia_io_handle *); 174 STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 175 bus_size_t, struct pcmcia_io_handle *, int *); 176 STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t, int); 177 STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t, 178 struct pcmcia_function *, int, int (*)(void *), void *); 179 STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t, void *); 180 STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t); 181 STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t); 182 STATIC void pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t, int); 183 STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch); 184 185 static int pccbb_pcmcia_wait_ready(struct pcic_handle *); 186 static void pccbb_pcmcia_delay(struct pcic_handle *, int, const char *); 187 188 static void pccbb_pcmcia_do_io_map(struct pcic_handle *, int); 189 static void pccbb_pcmcia_do_mem_map(struct pcic_handle *, int); 190 191 /* bus-space allocation and deallocation functions */ 192 #if rbus 193 194 static int pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t, rbus_tag_t, 195 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 196 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp); 197 static int pccbb_rbus_cb_space_free(cardbus_chipset_tag_t, rbus_tag_t, 198 bus_space_handle_t, bus_size_t); 199 200 #endif /* rbus */ 201 202 #if rbus 203 204 static int pccbb_open_win(struct pccbb_softc *, bus_space_tag_t, 205 bus_addr_t, bus_size_t, bus_space_handle_t, int flags); 206 static int pccbb_close_win(struct pccbb_softc *, bus_space_tag_t, 207 bus_space_handle_t, bus_size_t); 208 static int pccbb_winlist_insert(struct pccbb_win_chain_head *, bus_addr_t, 209 bus_size_t, bus_space_handle_t, int); 210 static int pccbb_winlist_delete(struct pccbb_win_chain_head *, 211 bus_space_handle_t, bus_size_t); 212 static void pccbb_winset(bus_addr_t align, struct pccbb_softc *, 213 bus_space_tag_t); 214 void pccbb_winlist_show(struct pccbb_win_chain *); 215 216 #endif /* rbus */ 217 218 /* for config_defer */ 219 static void pccbb_pci_callback(struct device *); 220 221 static bool pccbb_suspend(device_t); 222 static bool pccbb_resume(device_t); 223 224 #if defined SHOW_REGS 225 static void cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, 226 bus_space_tag_t memt, bus_space_handle_t memh); 227 #endif 228 229 CFATTACH_DECL(cbb_pci, sizeof(struct pccbb_softc), 230 pcicbbmatch, pccbbattach, pccbbdetach, NULL); 231 232 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 233 pccbb_pcmcia_mem_alloc, 234 pccbb_pcmcia_mem_free, 235 pccbb_pcmcia_mem_map, 236 pccbb_pcmcia_mem_unmap, 237 pccbb_pcmcia_io_alloc, 238 pccbb_pcmcia_io_free, 239 pccbb_pcmcia_io_map, 240 pccbb_pcmcia_io_unmap, 241 pccbb_pcmcia_intr_establish, 242 pccbb_pcmcia_intr_disestablish, 243 pccbb_pcmcia_socket_enable, 244 pccbb_pcmcia_socket_disable, 245 pccbb_pcmcia_socket_settype, 246 pccbb_pcmcia_card_detect 247 }; 248 249 #if rbus 250 static struct cardbus_functions pccbb_funcs = { 251 pccbb_rbus_cb_space_alloc, 252 pccbb_rbus_cb_space_free, 253 pccbb_cb_intr_establish, 254 pccbb_cb_intr_disestablish, 255 pccbb_ctrl, 256 pccbb_power_ct, 257 pccbb_make_tag, 258 pccbb_free_tag, 259 pccbb_conf_read, 260 pccbb_conf_write, 261 }; 262 #else 263 static struct cardbus_functions pccbb_funcs = { 264 pccbb_ctrl, 265 pccbb_power_ct, 266 pccbb_mem_open, 267 pccbb_mem_close, 268 pccbb_io_open, 269 pccbb_io_close, 270 pccbb_cb_intr_establish, 271 pccbb_cb_intr_disestablish, 272 pccbb_make_tag, 273 pccbb_conf_read, 274 pccbb_conf_write, 275 }; 276 #endif 277 278 int 279 pcicbbmatch(struct device *parent, struct cfdata *match, void *aux) 280 { 281 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 282 283 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 284 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 285 PCI_INTERFACE(pa->pa_class) == 0) { 286 return 1; 287 } 288 289 return 0; 290 } 291 292 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 293 | ((prod) << PCI_PRODUCT_SHIFT)) 294 295 const struct yenta_chipinfo { 296 pcireg_t yc_id; /* vendor tag | product tag */ 297 int yc_chiptype; 298 int yc_flags; 299 } yc_chipsets[] = { 300 /* Texas Instruments chips */ 301 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 302 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 303 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 304 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 305 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI125X, 306 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 307 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 308 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 309 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 310 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 311 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 312 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 313 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI125X, 314 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 315 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI125X, 316 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 317 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 318 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 319 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 320 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 321 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI1420, 322 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 323 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI125X, 324 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 325 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 326 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 327 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1520), CB_TI12XX, 328 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 329 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4410YENTA), CB_TI12XX, 330 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 331 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4520YENTA), CB_TI12XX, 332 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 333 334 /* Ricoh chips */ 335 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 336 PCCBB_PCMCIA_MEM_32}, 337 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 338 PCCBB_PCMCIA_MEM_32}, 339 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 340 PCCBB_PCMCIA_MEM_32}, 341 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 342 PCCBB_PCMCIA_MEM_32}, 343 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 344 PCCBB_PCMCIA_MEM_32}, 345 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 346 PCCBB_PCMCIA_MEM_32}, 347 348 /* Toshiba products */ 349 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 350 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 351 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 352 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 353 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 354 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 355 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 356 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 357 358 /* Cirrus Logic products */ 359 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 360 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 361 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 362 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 363 364 /* sentinel, or Generic chip */ 365 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 366 }; 367 368 static int 369 cb_chipset(u_int32_t pci_id, int *flagp) 370 { 371 const struct yenta_chipinfo *yc; 372 373 /* Loop over except the last default entry. */ 374 for (yc = yc_chipsets; yc < yc_chipsets + 375 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 376 if (pci_id == yc->yc_id) 377 break; 378 379 if (flagp != NULL) 380 *flagp = yc->yc_flags; 381 382 return (yc->yc_chiptype); 383 } 384 385 void 386 pccbbattach(struct device *parent, struct device *self, void *aux) 387 { 388 struct pccbb_softc *sc = (void *)self; 389 struct pci_attach_args *pa = aux; 390 pci_chipset_tag_t pc = pa->pa_pc; 391 pcireg_t busreg, reg, sock_base; 392 bus_addr_t sockbase; 393 char devinfo[256]; 394 int flags; 395 396 #ifdef __HAVE_PCCBB_ATTACH_HOOK 397 pccbb_attach_hook(parent, self, pa); 398 #endif 399 400 callout_init(&sc->sc_insert_ch, 0); 401 callout_setfunc(&sc->sc_insert_ch, pci113x_insert, sc); 402 403 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 404 405 aprint_naive("\n"); 406 407 pci_devinfo(pa->pa_id, 0, 0, devinfo, sizeof(devinfo)); 408 aprint_normal(": %s (rev. 0x%02x)", devinfo, 409 PCI_REVISION(pa->pa_class)); 410 DPRINTF((" (chipflags %x)", flags)); 411 aprint_normal("\n"); 412 413 TAILQ_INIT(&sc->sc_memwindow); 414 TAILQ_INIT(&sc->sc_iowindow); 415 416 #if rbus 417 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 418 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 419 420 #if 0 421 printf("pa->pa_memt: %08x vs rbus_mem->rb_bt: %08x\n", 422 pa->pa_memt, sc->sc_rbus_memt->rb_bt); 423 #endif 424 #endif /* rbus */ 425 426 sc->sc_flags &= ~CBB_MEMHMAPPED; 427 428 /* 429 * MAP socket registers and ExCA registers on memory-space 430 * When no valid address is set on socket base registers (on pci 431 * config space), get it not polite way. 432 */ 433 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 434 435 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 436 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 437 /* The address must be valid. */ 438 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 439 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, &sc->sc_base_size)) { 440 aprint_error("%s: can't map socket base address 0x%lx\n", 441 sc->sc_dev.dv_xname, (unsigned long)sock_base); 442 /* 443 * I think it's funny: socket base registers must be 444 * mapped on memory space, but ... 445 */ 446 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 447 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 448 &sc->sc_base_size)) { 449 aprint_error("%s: can't map socket base address" 450 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 451 (unsigned long)sockbase); 452 /* give up... allocate reg space via rbus. */ 453 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 454 } else 455 sc->sc_flags |= CBB_MEMHMAPPED; 456 } else { 457 DPRINTF(("%s: socket base address 0x%lx\n", 458 sc->sc_dev.dv_xname, (unsigned long)sockbase)); 459 sc->sc_flags |= CBB_MEMHMAPPED; 460 } 461 } 462 463 sc->sc_mem_start = 0; /* XXX */ 464 sc->sc_mem_end = 0xffffffff; /* XXX */ 465 466 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 467 468 /* pccbb_machdep.c end */ 469 470 #if defined CBB_DEBUG 471 { 472 static const char *intrname[] = { "NON", "A", "B", "C", "D" }; 473 printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname, 474 intrname[pa->pa_intrpin], pa->pa_intrline); 475 } 476 #endif 477 478 /* setup softc */ 479 sc->sc_pc = pc; 480 sc->sc_iot = pa->pa_iot; 481 sc->sc_memt = pa->pa_memt; 482 sc->sc_dmat = pa->pa_dmat; 483 sc->sc_tag = pa->pa_tag; 484 sc->sc_function = pa->pa_function; 485 486 memcpy(&sc->sc_pa, pa, sizeof(*pa)); 487 488 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 489 490 /* Disable legacy register mapping. */ 491 switch (sc->sc_chipset) { 492 case CB_RX5C46X: /* fallthrough */ 493 #if 0 494 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 495 case CB_RX5C47X: 496 #endif 497 /* 498 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 499 * cannot be disabled by substituting 0 into PCI_LEGACY 500 * register. Ricoh CardBus bridges have special bits on Bridge 501 * control reg (addr 0x3e on PCI config space). 502 */ 503 reg = pci_conf_read(pc, pa->pa_tag, PCI_BRIDGE_CONTROL_REG); 504 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 505 pci_conf_write(pc, pa->pa_tag, PCI_BRIDGE_CONTROL_REG, reg); 506 break; 507 508 default: 509 /* XXX I don't know proper way to kill legacy I/O. */ 510 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 511 break; 512 } 513 514 if (!pmf_device_register(self, pccbb_suspend, pccbb_resume)) 515 aprint_error_dev(self, "couldn't establish power handler\n"); 516 517 config_defer(self, pccbb_pci_callback); 518 } 519 520 int 521 pccbbdetach(device_t self, int flags) 522 { 523 struct pccbb_softc *sc = device_private(self); 524 pci_chipset_tag_t pc = sc->sc_pa.pa_pc; 525 bus_space_tag_t bmt = sc->sc_base_memt; 526 bus_space_handle_t bmh = sc->sc_base_memh; 527 uint32_t sockmask; 528 int rc; 529 530 if ((rc = config_detach_children(self, flags)) != 0) 531 return rc; 532 533 if (sc->sc_ih != NULL) { 534 pci_intr_disestablish(pc, sc->sc_ih); 535 sc->sc_ih = NULL; 536 } 537 538 /* CSC Interrupt: turn off card detect and power cycle interrupts */ 539 sockmask = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 540 sockmask &= ~(CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER); 541 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, sockmask); 542 /* reset interrupt */ 543 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 544 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 545 546 switch (sc->sc_flags & (CBB_MEMHMAPPED|CBB_SPECMAPPED)) { 547 case CBB_MEMHMAPPED: 548 bus_space_unmap(bmt, bmh, sc->sc_base_size); 549 break; 550 case CBB_MEMHMAPPED|CBB_SPECMAPPED: 551 #if rbus 552 { 553 pcireg_t sockbase; 554 555 sockbase = pci_conf_read(pc, sc->sc_tag, PCI_SOCKBASE); 556 rbus_space_free(sc->sc_rbus_memt, bmh, 0x1000, 557 NULL); 558 } 559 #else 560 bus_space_free(bmt, bmh, 0x1000); 561 #endif 562 } 563 sc->sc_flags &= ~(CBB_MEMHMAPPED|CBB_SPECMAPPED); 564 565 if (!TAILQ_EMPTY(&sc->sc_iowindow)) 566 aprint_error_dev(self, "i/o windows not empty"); 567 if (!TAILQ_EMPTY(&sc->sc_memwindow)) 568 aprint_error_dev(self, "memory windows not empty"); 569 570 callout_stop(&sc->sc_insert_ch); 571 callout_destroy(&sc->sc_insert_ch); 572 return 0; 573 } 574 575 /* 576 * static void pccbb_pci_callback(struct device *self) 577 * 578 * The actual attach routine: get memory space for YENTA register 579 * space, setup YENTA register and route interrupt. 580 * 581 * This function should be deferred because this device may obtain 582 * memory space dynamically. This function must avoid obtaining 583 * memory area which has already kept for another device. 584 */ 585 static void 586 pccbb_pci_callback(struct device *self) 587 { 588 struct pccbb_softc *sc = (void *)self; 589 pci_chipset_tag_t pc = sc->sc_pc; 590 pci_intr_handle_t ih; 591 const char *intrstr = NULL; 592 bus_addr_t sockbase; 593 struct cbslot_attach_args cba; 594 struct pcmciabus_attach_args paa; 595 struct cardslot_attach_args caa; 596 struct cardslot_softc *csc; 597 598 if (!(sc->sc_flags & CBB_MEMHMAPPED)) { 599 /* The socket registers aren't mapped correctly. */ 600 #if rbus 601 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 602 (sc->sc_chipset == CB_RX5C47X 603 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 604 0, &sockbase, &sc->sc_base_memh)) { 605 return; 606 } 607 sc->sc_base_memt = sc->sc_memt; 608 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 609 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 610 sc->sc_dev.dv_xname, (unsigned long)sockbase, 611 (unsigned long)pci_conf_read(pc, sc->sc_tag, 612 PCI_SOCKBASE))); 613 #else 614 sc->sc_base_memt = sc->sc_memt; 615 #if !defined CBB_PCI_BASE 616 #define CBB_PCI_BASE 0x20000000 617 #endif 618 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 619 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 620 /* cannot allocate memory space */ 621 return; 622 } 623 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 624 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 625 sc->sc_dev.dv_xname, (unsigned long)sock_base, 626 (unsigned long)pci_conf_read(pc, 627 sc->sc_tag, PCI_SOCKBASE))); 628 #endif 629 sc->sc_flags |= CBB_MEMHMAPPED; 630 } 631 632 /* bus bridge initialization */ 633 pccbb_chipinit(sc); 634 635 /* clear data structure for child device interrupt handlers */ 636 LIST_INIT(&sc->sc_pil); 637 sc->sc_pil_intr_enable = 1; 638 639 /* Map and establish the interrupt. */ 640 if (pci_intr_map(&sc->sc_pa, &ih)) { 641 aprint_error("%s: couldn't map interrupt\n", 642 sc->sc_dev.dv_xname); 643 return; 644 } 645 intrstr = pci_intr_string(pc, ih); 646 647 /* 648 * XXX pccbbintr should be called under the priority lower 649 * than any other hard interupts. 650 */ 651 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 652 653 if (sc->sc_ih == NULL) { 654 aprint_error("%s: couldn't establish interrupt", 655 sc->sc_dev.dv_xname); 656 if (intrstr != NULL) { 657 aprint_normal(" at %s", intrstr); 658 } 659 aprint_normal("\n"); 660 return; 661 } 662 663 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 664 665 { 666 u_int32_t sockstat; 667 668 sockstat = bus_space_read_4(sc->sc_base_memt, 669 sc->sc_base_memh, CB_SOCKET_STAT); 670 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 671 sc->sc_flags |= CBB_CARDEXIST; 672 } 673 } 674 675 /* 676 * attach cardbus 677 */ 678 { 679 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 680 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 681 682 /* initialize cbslot_attach */ 683 cba.cba_busname = "cardbus"; 684 cba.cba_iot = sc->sc_iot; 685 cba.cba_memt = sc->sc_memt; 686 cba.cba_dmat = sc->sc_dmat; 687 cba.cba_bus = (busreg >> 8) & 0x0ff; 688 cba.cba_cc = (void *)sc; 689 cba.cba_cf = &pccbb_funcs; 690 cba.cba_intrline = sc->sc_pa.pa_intrline; 691 692 #if rbus 693 cba.cba_rbus_iot = sc->sc_rbus_iot; 694 cba.cba_rbus_memt = sc->sc_rbus_memt; 695 #endif 696 697 cba.cba_cacheline = PCI_CACHELINE(bhlc); 698 cba.cba_max_lattimer = PCI_LATTIMER(bhlc); 699 700 if (bootverbose) { 701 printf("%s: cacheline 0x%x lattimer 0x%x\n", 702 sc->sc_dev.dv_xname, cba.cba_cacheline, 703 cba.cba_max_lattimer); 704 printf("%s: bhlc 0x%x\n", 705 device_xname(&sc->sc_dev), bhlc); 706 } 707 #if defined SHOW_REGS 708 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 709 sc->sc_base_memh); 710 #endif 711 } 712 713 pccbb_pcmcia_attach_setup(sc, &paa); 714 caa.caa_cb_attach = NULL; 715 if (cba.cba_bus == 0) 716 printf("%s: secondary bus number uninitialized; try PCI_BUS_FIXUP\n", sc->sc_dev.dv_xname); 717 else 718 caa.caa_cb_attach = &cba; 719 caa.caa_16_attach = &paa; 720 caa.caa_ph = &sc->sc_pcmcia_h; 721 722 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 723 DPRINTF(("%s: found cardslot\n", __func__)); 724 sc->sc_csc = csc; 725 } 726 727 return; 728 } 729 730 731 732 733 734 /* 735 * static void pccbb_chipinit(struct pccbb_softc *sc) 736 * 737 * This function initialize YENTA chip registers listed below: 738 * 1) PCI command reg, 739 * 2) PCI and CardBus latency timer, 740 * 3) route PCI interrupt, 741 * 4) close all memory and io windows. 742 * 5) turn off bus power. 743 * 6) card detect and power cycle interrupts on. 744 * 7) clear interrupt 745 */ 746 static void 747 pccbb_chipinit(struct pccbb_softc *sc) 748 { 749 pci_chipset_tag_t pc = sc->sc_pc; 750 pcitag_t tag = sc->sc_tag; 751 bus_space_tag_t bmt = sc->sc_base_memt; 752 bus_space_handle_t bmh = sc->sc_base_memh; 753 pcireg_t bcr, bhlc, cbctl, csr, lscp, mfunc, mrburst, slotctl, sockctl, 754 sockmask, sysctrl; 755 756 /* 757 * Set PCI command reg. 758 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 759 */ 760 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 761 /* I believe it is harmless. */ 762 csr |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 763 PCI_COMMAND_MASTER_ENABLE); 764 csr |= (PCI_COMMAND_PARITY_ENABLE|PCI_COMMAND_SERR_ENABLE); 765 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 766 767 /* 768 * Set CardBus latency timer. 769 */ 770 lscp = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 771 if (PCI_CB_LATENCY(lscp) < 0x20) { 772 lscp &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 773 lscp |= (0x20 << PCI_CB_LATENCY_SHIFT); 774 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, lscp); 775 } 776 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 777 PCI_CB_LATENCY(lscp), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 778 779 /* 780 * Set PCI latency timer. 781 */ 782 bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG); 783 if (PCI_LATTIMER(bhlc) < 0x10) { 784 bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 785 bhlc |= (0x10 << PCI_LATTIMER_SHIFT); 786 pci_conf_write(pc, tag, PCI_BHLC_REG, bhlc); 787 } 788 DPRINTF(("PCI latency timer 0x%x (%x)\n", 789 PCI_LATTIMER(bhlc), pci_conf_read(pc, tag, PCI_BHLC_REG))); 790 791 792 /* Route functional interrupts to PCI. */ 793 bcr = pci_conf_read(pc, tag, PCI_BRIDGE_CONTROL_REG); 794 bcr |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 795 bcr |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 796 /* assert reset */ 797 bcr |= PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT; 798 /* Set master abort mode to 1, forward SERR# from secondary 799 * to primary, and detect parity errors on secondary. 800 */ 801 bcr |= PCI_BRIDGE_CONTROL_MABRT << PCI_BRIDGE_CONTROL_SHIFT; 802 bcr |= PCI_BRIDGE_CONTROL_SERR << PCI_BRIDGE_CONTROL_SHIFT; 803 bcr |= PCI_BRIDGE_CONTROL_PERE << PCI_BRIDGE_CONTROL_SHIFT; 804 pci_conf_write(pc, tag, PCI_BRIDGE_CONTROL_REG, bcr); 805 806 switch (sc->sc_chipset) { 807 case CB_TI113X: 808 cbctl = pci_conf_read(pc, tag, PCI_CBCTRL); 809 /* This bit is shared, but may read as 0 on some chips, so set 810 it explicitly on both functions. */ 811 cbctl |= PCI113X_CBCTRL_PCI_IRQ_ENA; 812 /* CSC intr enable */ 813 cbctl |= PCI113X_CBCTRL_PCI_CSC; 814 /* functional intr prohibit | prohibit ISA routing */ 815 cbctl &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 816 pci_conf_write(pc, tag, PCI_CBCTRL, cbctl); 817 break; 818 819 case CB_TI1420: 820 sysctrl = pci_conf_read(pc, tag, PCI_SYSCTRL); 821 mrburst = pccbb_burstup 822 ? PCI1420_SYSCTRL_MRBURST : PCI1420_SYSCTRL_MRBURSTDN; 823 if ((sysctrl & PCI1420_SYSCTRL_MRBURST) == mrburst) { 824 printf("%s: %swrite bursts enabled\n", 825 device_xname(&sc->sc_dev), 826 pccbb_burstup ? "read/" : ""); 827 } else if (pccbb_burstup) { 828 printf("%s: enabling read/write bursts\n", 829 device_xname(&sc->sc_dev)); 830 sysctrl |= PCI1420_SYSCTRL_MRBURST; 831 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 832 } else { 833 printf("%s: disabling read bursts, " 834 "enabling write bursts\n", 835 device_xname(&sc->sc_dev)); 836 sysctrl |= PCI1420_SYSCTRL_MRBURSTDN; 837 sysctrl &= ~PCI1420_SYSCTRL_MRBURSTUP; 838 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 839 } 840 /*FALLTHROUGH*/ 841 case CB_TI12XX: 842 /* 843 * Some TI 12xx (and [14][45]xx) based pci cards 844 * sometimes have issues with the MFUNC register not 845 * being initialized due to a bad EEPROM on board. 846 * Laptops that this matters on have this register 847 * properly initialized. 848 * 849 * The TI125X parts have a different register. 850 */ 851 mfunc = pci_conf_read(pc, tag, PCI12XX_MFUNC); 852 if (mfunc == 0) { 853 mfunc &= ~PCI12XX_MFUNC_PIN0; 854 mfunc |= PCI12XX_MFUNC_PIN0_INTA; 855 if ((pci_conf_read(pc, tag, PCI_SYSCTRL) & 856 PCI12XX_SYSCTRL_INTRTIE) == 0) { 857 mfunc &= ~PCI12XX_MFUNC_PIN1; 858 mfunc |= PCI12XX_MFUNC_PIN1_INTB; 859 } 860 pci_conf_write(pc, tag, PCI12XX_MFUNC, mfunc); 861 } 862 /* fallthrough */ 863 864 case CB_TI125X: 865 /* 866 * Disable zoom video. Some machines initialize this 867 * improperly and experience has shown that this helps 868 * prevent strange behavior. 869 */ 870 pci_conf_write(pc, tag, PCI12XX_MMCTRL, 0); 871 872 sysctrl = pci_conf_read(pc, tag, PCI_SYSCTRL); 873 sysctrl |= PCI12XX_SYSCTRL_VCCPROT; 874 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 875 cbctl = pci_conf_read(pc, tag, PCI_CBCTRL); 876 cbctl |= PCI12XX_CBCTRL_CSC; 877 pci_conf_write(pc, tag, PCI_CBCTRL, cbctl); 878 break; 879 880 case CB_TOPIC95B: 881 sockctl = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 882 sockctl |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 883 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, sockctl); 884 slotctl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 885 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 886 sc->sc_dev.dv_xname, slotctl)); 887 slotctl |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 888 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 889 slotctl &= ~TOPIC_SLOT_CTRL_SWDETECT; 890 DPRINTF(("0x%x\n", slotctl)); 891 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slotctl); 892 break; 893 894 case CB_TOPIC97: 895 slotctl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 896 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 897 sc->sc_dev.dv_xname, slotctl)); 898 slotctl |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 899 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 900 slotctl &= ~TOPIC_SLOT_CTRL_SWDETECT; 901 slotctl |= TOPIC97_SLOT_CTRL_PCIINT; 902 slotctl &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 903 DPRINTF(("0x%x\n", slotctl)); 904 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slotctl); 905 /* make sure to assert LV card support bits */ 906 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 907 0x800 + 0x3e, 908 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 909 0x800 + 0x3e) | 0x03); 910 break; 911 } 912 913 /* Close all memory and I/O windows. */ 914 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 915 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 916 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 917 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 918 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 919 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 920 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 921 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 922 923 /* reset 16-bit pcmcia bus */ 924 bus_space_write_1(bmt, bmh, 0x800 + PCIC_INTR, 925 bus_space_read_1(bmt, bmh, 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 926 927 /* turn off power */ 928 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 929 930 /* CSC Interrupt: Card detect and power cycle interrupts on */ 931 sockmask = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 932 sockmask |= CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; 933 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, sockmask); 934 /* reset interrupt */ 935 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 936 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 937 } 938 939 940 941 942 /* 943 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 944 * struct pcmciabus_attach_args *paa) 945 * 946 * This function attaches 16-bit PCcard bus. 947 */ 948 STATIC void 949 pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 950 struct pcmciabus_attach_args *paa) 951 { 952 struct pcic_handle *ph = &sc->sc_pcmcia_h; 953 #if rbus 954 rbus_tag_t rb; 955 #endif 956 957 /* initialize pcmcia part in pccbb_softc */ 958 ph->ph_parent = (struct device *)sc; 959 ph->sock = sc->sc_function; 960 ph->flags = 0; 961 ph->shutdown = 0; 962 ph->ih_irq = sc->sc_pa.pa_intrline; 963 ph->ph_bus_t = sc->sc_base_memt; 964 ph->ph_bus_h = sc->sc_base_memh; 965 ph->ph_read = pccbb_pcmcia_read; 966 ph->ph_write = pccbb_pcmcia_write; 967 sc->sc_pct = &pccbb_pcmcia_funcs; 968 969 /* 970 * We need to do a few things here: 971 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 972 * setting the IRQ numbers to 0. 973 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 974 * routing of CSC interrupts (e.g. card removal) to PCI while in 975 * PCMCIA mode. We just leave this set all the time. 976 * 3) Enable card insertion/removal interrupts in case the chip also 977 * needs that while in PCMCIA mode. 978 * 4) Clear any pending CSC interrupt. 979 */ 980 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE); 981 if (sc->sc_chipset == CB_TI113X) { 982 Pcic_write(ph, PCIC_CSC_INTR, 0); 983 } else { 984 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 985 Pcic_read(ph, PCIC_CSC); 986 } 987 988 /* initialize pcmcia bus attachment */ 989 paa->paa_busname = "pcmcia"; 990 paa->pct = sc->sc_pct; 991 paa->pch = ph; 992 paa->iobase = 0; /* I don't use them */ 993 paa->iosize = 0; 994 #if rbus 995 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 996 paa->iobase = rb->rb_start + rb->rb_offset; 997 paa->iosize = rb->rb_end - rb->rb_start; 998 #endif 999 1000 return; 1001 } 1002 1003 #if 0 1004 STATIC void 1005 pccbb_pcmcia_attach_card(struct pcic_handle *ph) 1006 { 1007 if (ph->flags & PCIC_FLAG_CARDP) { 1008 panic("pccbb_pcmcia_attach_card: already attached"); 1009 } 1010 1011 /* call the MI attach function */ 1012 pcmcia_card_attach(ph->pcmcia); 1013 1014 ph->flags |= PCIC_FLAG_CARDP; 1015 } 1016 1017 STATIC void 1018 pccbb_pcmcia_detach_card(struct pcic_handle *ph, int flags) 1019 { 1020 if (!(ph->flags & PCIC_FLAG_CARDP)) { 1021 panic("pccbb_pcmcia_detach_card: already detached"); 1022 } 1023 1024 ph->flags &= ~PCIC_FLAG_CARDP; 1025 1026 /* call the MI detach function */ 1027 pcmcia_card_detach(ph->pcmcia, flags); 1028 } 1029 #endif 1030 1031 /* 1032 * int pccbbintr(arg) 1033 * void *arg; 1034 * This routine handles the interrupt from Yenta PCI-CardBus bridge 1035 * itself. 1036 */ 1037 int 1038 pccbbintr(void *arg) 1039 { 1040 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1041 u_int32_t sockevent, sockstate; 1042 bus_space_tag_t memt = sc->sc_base_memt; 1043 bus_space_handle_t memh = sc->sc_base_memh; 1044 struct pcic_handle *ph = &sc->sc_pcmcia_h; 1045 1046 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 1047 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 1048 Pcic_read(ph, PCIC_CSC); 1049 1050 if (sockevent != 0) { 1051 aprint_debug("%s: enter sockevent %" PRIx32 "\n", __func__, 1052 sockevent); 1053 } 1054 1055 /* Sometimes a change of CSTSCHG# accompanies the first 1056 * interrupt from an Atheros WLAN. That generates a 1057 * CB_SOCKET_EVENT_CSTS event on the bridge. The event 1058 * isn't interesting to pccbb(4), so we used to ignore the 1059 * interrupt. Now, let the child devices try to handle 1060 * the interrupt, instead. The Atheros NIC produces 1061 * interrupts more reliably, now: used to be that it would 1062 * only interrupt if the driver avoided powering down the 1063 * NIC's cardslot, and then the NIC would only work after 1064 * it was reset a second time. 1065 */ 1066 if (sockevent == 0 || 1067 (sockevent & ~(CB_SOCKET_EVENT_POWER|CB_SOCKET_EVENT_CD)) != 0) { 1068 /* This intr is not for me: it may be for my child devices. */ 1069 if (sc->sc_pil_intr_enable) { 1070 return pccbbintr_function(sc); 1071 } else { 1072 return 0; 1073 } 1074 } 1075 1076 if (sockevent & CB_SOCKET_EVENT_CD) { 1077 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1078 if (0x00 != (sockstate & CB_SOCKET_STAT_CD)) { 1079 /* A card should be removed. */ 1080 if (sc->sc_flags & CBB_CARDEXIST) { 1081 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 1082 sockevent)); 1083 DPRINTF((" card removed, 0x%08x\n", sockstate)); 1084 sc->sc_flags &= ~CBB_CARDEXIST; 1085 if (sc->sc_csc->sc_status & 1086 CARDSLOT_STATUS_CARD_16) { 1087 #if 0 1088 struct pcic_handle *ph = 1089 &sc->sc_pcmcia_h; 1090 1091 pcmcia_card_deactivate(ph->pcmcia); 1092 pccbb_pcmcia_socket_disable(ph); 1093 pccbb_pcmcia_detach_card(ph, 1094 DETACH_FORCE); 1095 #endif 1096 cardslot_event_throw(sc->sc_csc, 1097 CARDSLOT_EVENT_REMOVAL_16); 1098 } else if (sc->sc_csc->sc_status & 1099 CARDSLOT_STATUS_CARD_CB) { 1100 /* Cardbus intr removed */ 1101 cardslot_event_throw(sc->sc_csc, 1102 CARDSLOT_EVENT_REMOVAL_CB); 1103 } 1104 } else if (sc->sc_flags & CBB_INSERTING) { 1105 sc->sc_flags &= ~CBB_INSERTING; 1106 callout_stop(&sc->sc_insert_ch); 1107 } 1108 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 1109 /* 1110 * The pccbbintr may called from powerdown hook when 1111 * the system resumed, to detect the card 1112 * insertion/removal during suspension. 1113 */ 1114 (sc->sc_flags & CBB_CARDEXIST) == 0) { 1115 if (sc->sc_flags & CBB_INSERTING) { 1116 callout_stop(&sc->sc_insert_ch); 1117 } 1118 callout_schedule(&sc->sc_insert_ch, hz / 5); 1119 sc->sc_flags |= CBB_INSERTING; 1120 } 1121 } 1122 1123 /* XXX sockevent == 9 does occur in the wild. handle it. */ 1124 if (sockevent & CB_SOCKET_EVENT_POWER) { 1125 DPRINTF(("Powercycling because of socket event\n")); 1126 /* XXX: Does not happen when attaching a 16-bit card */ 1127 sc->sc_pwrcycle++; 1128 wakeup(&sc->sc_pwrcycle); 1129 } 1130 1131 return (1); 1132 } 1133 1134 /* 1135 * static int pccbbintr_function(struct pccbb_softc *sc) 1136 * 1137 * This function calls each interrupt handler registered at the 1138 * bridge. The interrupt handlers are called in registered order. 1139 */ 1140 static int 1141 pccbbintr_function(struct pccbb_softc *sc) 1142 { 1143 int retval = 0, val; 1144 struct pccbb_intrhand_list *pil; 1145 int s; 1146 1147 LIST_FOREACH(pil, &sc->sc_pil, pil_next) { 1148 s = splraiseipl(pil->pil_icookie); 1149 val = (*pil->pil_func)(pil->pil_arg); 1150 splx(s); 1151 1152 retval = retval == 1 ? 1 : 1153 retval == 0 ? val : val != 0 ? val : retval; 1154 } 1155 1156 return retval; 1157 } 1158 1159 static void 1160 pci113x_insert(void *arg) 1161 { 1162 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1163 u_int32_t sockevent, sockstate; 1164 1165 if (!(sc->sc_flags & CBB_INSERTING)) { 1166 /* We add a card only under inserting state. */ 1167 return; 1168 } 1169 sc->sc_flags &= ~CBB_INSERTING; 1170 1171 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1172 CB_SOCKET_EVENT); 1173 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1174 CB_SOCKET_STAT); 1175 1176 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1177 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1178 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1179 sc->sc_flags |= CBB_CARDEXIST; 1180 /* call pccard interrupt handler here */ 1181 if (sockstate & CB_SOCKET_STAT_16BIT) { 1182 /* 16-bit card found */ 1183 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1184 cardslot_event_throw(sc->sc_csc, 1185 CARDSLOT_EVENT_INSERTION_16); 1186 } else if (sockstate & CB_SOCKET_STAT_CB) { 1187 /* cardbus card found */ 1188 /* cardbus_attach_card(sc->sc_csc); */ 1189 cardslot_event_throw(sc->sc_csc, 1190 CARDSLOT_EVENT_INSERTION_CB); 1191 } else { 1192 /* who are you? */ 1193 } 1194 } else { 1195 callout_schedule(&sc->sc_insert_ch, hz / 10); 1196 } 1197 } 1198 1199 #define PCCBB_PCMCIA_OFFSET 0x800 1200 static u_int8_t 1201 pccbb_pcmcia_read(struct pcic_handle *ph, int reg) 1202 { 1203 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1204 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1205 1206 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1207 PCCBB_PCMCIA_OFFSET + reg); 1208 } 1209 1210 static void 1211 pccbb_pcmcia_write(struct pcic_handle *ph, int reg, u_int8_t val) 1212 { 1213 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1214 val); 1215 1216 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1217 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1218 } 1219 1220 /* 1221 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1222 */ 1223 STATIC int 1224 pccbb_ctrl(cardbus_chipset_tag_t ct, int command) 1225 { 1226 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1227 1228 switch (command) { 1229 case CARDBUS_CD: 1230 if (2 == pccbb_detect_card(sc)) { 1231 int retval = 0; 1232 int status = cb_detect_voltage(sc); 1233 if (PCCARD_VCC_5V & status) { 1234 retval |= CARDBUS_5V_CARD; 1235 } 1236 if (PCCARD_VCC_3V & status) { 1237 retval |= CARDBUS_3V_CARD; 1238 } 1239 if (PCCARD_VCC_XV & status) { 1240 retval |= CARDBUS_XV_CARD; 1241 } 1242 if (PCCARD_VCC_YV & status) { 1243 retval |= CARDBUS_YV_CARD; 1244 } 1245 return retval; 1246 } else { 1247 return 0; 1248 } 1249 case CARDBUS_RESET: 1250 return cb_reset(sc); 1251 case CARDBUS_IO_ENABLE: /* fallthrough */ 1252 case CARDBUS_IO_DISABLE: /* fallthrough */ 1253 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1254 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1255 case CARDBUS_BM_ENABLE: /* fallthrough */ 1256 case CARDBUS_BM_DISABLE: /* fallthrough */ 1257 /* XXX: I think we don't need to call this function below. */ 1258 return pccbb_cardenable(sc, command); 1259 } 1260 1261 return 0; 1262 } 1263 1264 STATIC int 1265 pccbb_power_ct(cardbus_chipset_tag_t ct, int command) 1266 { 1267 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1268 1269 return pccbb_power(sc, command); 1270 } 1271 1272 /* 1273 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1274 * This function returns true when it succeeds and returns false when 1275 * it fails. 1276 */ 1277 STATIC int 1278 pccbb_power(struct pccbb_softc *sc, int command) 1279 { 1280 u_int32_t status, osock_ctrl, sock_ctrl, reg_ctrl; 1281 bus_space_tag_t memt = sc->sc_base_memt; 1282 bus_space_handle_t memh = sc->sc_base_memh; 1283 int on = 0, pwrcycle, s, times; 1284 struct timeval before, after, diff; 1285 1286 DPRINTF(("pccbb_power: %s and %s [0x%x]\n", 1287 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1288 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1289 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1290 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1291 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1292 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1293 "UNKNOWN", 1294 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1295 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1296 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1297 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1298 "UNKNOWN", command)); 1299 1300 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1301 osock_ctrl = sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1302 1303 switch (command & CARDBUS_VCCMASK) { 1304 case CARDBUS_VCC_UC: 1305 break; 1306 case CARDBUS_VCC_5V: 1307 on++; 1308 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1309 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1310 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1311 } else { 1312 printf("%s: BAD voltage request: no 5 V card\n", 1313 sc->sc_dev.dv_xname); 1314 return 0; 1315 } 1316 break; 1317 case CARDBUS_VCC_3V: 1318 on++; 1319 if (CB_SOCKET_STAT_3VCARD & status) { 1320 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1321 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1322 } else { 1323 printf("%s: BAD voltage request: no 3.3 V card\n", 1324 sc->sc_dev.dv_xname); 1325 return 0; 1326 } 1327 break; 1328 case CARDBUS_VCC_0V: 1329 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1330 break; 1331 default: 1332 return 0; /* power NEVER changed */ 1333 } 1334 1335 switch (command & CARDBUS_VPPMASK) { 1336 case CARDBUS_VPP_UC: 1337 break; 1338 case CARDBUS_VPP_0V: 1339 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1340 break; 1341 case CARDBUS_VPP_VCC: 1342 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1343 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1344 break; 1345 case CARDBUS_VPP_12V: 1346 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1347 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1348 break; 1349 } 1350 1351 pwrcycle = sc->sc_pwrcycle; 1352 aprint_debug("%s: osock_ctrl %#" PRIx32 " sock_ctrl %#" PRIx32 "\n", 1353 device_xname(&sc->sc_dev), osock_ctrl, sock_ctrl); 1354 1355 microtime(&before); 1356 s = splbio(); 1357 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1358 1359 /* 1360 * Wait as long as 200ms for a power-cycle interrupt. If 1361 * interrupts are enabled, but the socket has already 1362 * changed to the desired status, keep waiting for the 1363 * interrupt. "Consuming" the interrupt in this way keeps 1364 * the interrupt from prematurely waking some subsequent 1365 * pccbb_power call. 1366 * 1367 * XXX Not every bridge interrupts on the ->OFF transition. 1368 * XXX That's ok, we will time-out after 200ms. 1369 * 1370 * XXX The power cycle event will never happen when attaching 1371 * XXX a 16-bit card. That's ok, we will time-out after 1372 * XXX 200ms. 1373 */ 1374 for (times = 5; --times >= 0; ) { 1375 if (cold) 1376 DELAY(40 * 1000); 1377 else { 1378 (void)tsleep(&sc->sc_pwrcycle, PWAIT, "pccpwr", 1379 hz / 25); 1380 if (pwrcycle == sc->sc_pwrcycle) 1381 continue; 1382 } 1383 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1384 if ((status & CB_SOCKET_STAT_PWRCYCLE) != 0 && on) 1385 break; 1386 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0 && !on) 1387 break; 1388 } 1389 splx(s); 1390 microtime(&after); 1391 timersub(&after, &before, &diff); 1392 aprint_debug("%s: wait took%s %ld.%06lds\n", sc->sc_dev.dv_xname, 1393 (on && times < 0) ? " too long" : "", diff.tv_sec, diff.tv_usec); 1394 1395 /* 1396 * Ok, wait a bit longer for things to settle. 1397 */ 1398 if (on && sc->sc_chipset == CB_TOPIC95B) 1399 delay_ms(100, sc); 1400 1401 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1402 1403 if (on && sc->sc_chipset != CB_TOPIC95B) { 1404 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0) 1405 printf("%s: power on failed?\n", sc->sc_dev.dv_xname); 1406 } 1407 1408 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1409 printf("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1410 sc->sc_dev.dv_xname, sock_ctrl, status); 1411 printf("%s: disabling socket\n", sc->sc_dev.dv_xname); 1412 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1413 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1414 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1415 status &= ~CB_SOCKET_STAT_BADVCC; 1416 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, status); 1417 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1418 CB_SOCKET_STAT)); 1419 return 0; 1420 } 1421 1422 if (sc->sc_chipset == CB_TOPIC97) { 1423 reg_ctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL); 1424 reg_ctrl &= ~TOPIC97_REG_CTRL_TESTMODE; 1425 if ((command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V) 1426 reg_ctrl &= ~TOPIC97_REG_CTRL_CLKRUN_ENA; 1427 else 1428 reg_ctrl |= TOPIC97_REG_CTRL_CLKRUN_ENA; 1429 pci_conf_write(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL, reg_ctrl); 1430 } 1431 1432 return 1; /* power changed correctly */ 1433 } 1434 1435 #if defined CB_PCMCIA_POLL 1436 struct cb_poll_str { 1437 void *arg; 1438 int (*func)(void *); 1439 int level; 1440 pccard_chipset_tag_t ct; 1441 int count; 1442 struct callout poll_ch; 1443 }; 1444 1445 static struct cb_poll_str cb_poll[10]; 1446 static int cb_poll_n = 0; 1447 1448 static void cb_pcmcia_poll(void *arg); 1449 1450 static void 1451 cb_pcmcia_poll(void *arg) 1452 { 1453 struct cb_poll_str *poll = arg; 1454 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1455 struct pccbb_softc *sc = psc->cpc_parent; 1456 int s; 1457 u_int32_t spsr; /* socket present-state reg */ 1458 1459 callout_reset(&poll->poll_ch, hz / 10, cb_pcmcia_poll, poll); 1460 switch (poll->level) { 1461 case IPL_NET: 1462 s = splnet(); 1463 break; 1464 case IPL_BIO: 1465 s = splbio(); 1466 break; 1467 case IPL_TTY: /* fallthrough */ 1468 default: 1469 s = spltty(); 1470 break; 1471 } 1472 1473 spsr = 1474 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1475 CB_SOCKET_STAT); 1476 1477 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1478 if (!(spsr & 0x40)) { /* CINT low */ 1479 #else 1480 if (1) { 1481 #endif 1482 if ((*poll->func) (poll->arg) == 1) { 1483 ++poll->count; 1484 printf("intr: reported from poller, 0x%x\n", spsr); 1485 #if defined LEVEL2 1486 } else { 1487 printf("intr: miss! 0x%x\n", spsr); 1488 #endif 1489 } 1490 } 1491 splx(s); 1492 } 1493 #endif /* defined CB_PCMCIA_POLL */ 1494 1495 /* 1496 * static int pccbb_detect_card(struct pccbb_softc *sc) 1497 * return value: 0 if no card exists. 1498 * 1 if 16-bit card exists. 1499 * 2 if cardbus card exists. 1500 */ 1501 static int 1502 pccbb_detect_card(struct pccbb_softc *sc) 1503 { 1504 bus_space_handle_t base_memh = sc->sc_base_memh; 1505 bus_space_tag_t base_memt = sc->sc_base_memt; 1506 u_int32_t sockstat = 1507 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1508 int retval = 0; 1509 1510 /* CD1 and CD2 asserted */ 1511 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1512 /* card must be present */ 1513 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1514 /* NOTACARD DEASSERTED */ 1515 if (CB_SOCKET_STAT_CB & sockstat) { 1516 /* CardBus mode */ 1517 retval = 2; 1518 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1519 /* 16-bit mode */ 1520 retval = 1; 1521 } 1522 } 1523 } 1524 return retval; 1525 } 1526 1527 /* 1528 * STATIC int cb_reset(struct pccbb_softc *sc) 1529 * This function resets CardBus card. 1530 */ 1531 STATIC int 1532 cb_reset(struct pccbb_softc *sc) 1533 { 1534 /* 1535 * Reset Assert at least 20 ms 1536 * Some machines request longer duration. 1537 */ 1538 int reset_duration = 1539 (sc->sc_chipset == CB_RX5C47X ? 400 : 50); 1540 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1541 aprint_debug("%s: enter bcr %" PRIx32 "\n", __func__, bcr); 1542 1543 /* Reset bit Assert (bit 6 at 0x3E) */ 1544 bcr |= PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT; 1545 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr); 1546 aprint_debug("%s: wrote bcr %" PRIx32 "\n", __func__, bcr); 1547 delay_ms(reset_duration, sc); 1548 1549 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1550 /* Reset bit Deassert (bit 6 at 0x3E) */ 1551 bcr &= ~(PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT); 1552 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, 1553 bcr); 1554 aprint_debug("%s: wrote bcr %" PRIx32 "\n", __func__, bcr); 1555 delay_ms(reset_duration, sc); 1556 aprint_debug("%s: end of delay\n", __func__); 1557 } 1558 /* No card found on the slot. Keep Reset. */ 1559 return 1; 1560 } 1561 1562 /* 1563 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1564 * This function detect card Voltage. 1565 */ 1566 STATIC int 1567 cb_detect_voltage(struct pccbb_softc *sc) 1568 { 1569 u_int32_t psr; /* socket present-state reg */ 1570 bus_space_tag_t iot = sc->sc_base_memt; 1571 bus_space_handle_t ioh = sc->sc_base_memh; 1572 int vol = PCCARD_VCC_UKN; /* set 0 */ 1573 1574 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1575 1576 if (0x400u & psr) { 1577 vol |= PCCARD_VCC_5V; 1578 } 1579 if (0x800u & psr) { 1580 vol |= PCCARD_VCC_3V; 1581 } 1582 1583 return vol; 1584 } 1585 1586 STATIC int 1587 cbbprint(void *aux, const char *pcic) 1588 { 1589 #if 0 1590 struct cbslot_attach_args *cba = aux; 1591 1592 if (cba->cba_slot >= 0) { 1593 aprint_normal(" slot %d", cba->cba_slot); 1594 } 1595 #endif 1596 return UNCONF; 1597 } 1598 1599 /* 1600 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1601 * This function enables and disables the card 1602 */ 1603 STATIC int 1604 pccbb_cardenable(struct pccbb_softc *sc, int function) 1605 { 1606 u_int32_t command = 1607 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1608 1609 DPRINTF(("pccbb_cardenable:")); 1610 switch (function) { 1611 case CARDBUS_IO_ENABLE: 1612 command |= PCI_COMMAND_IO_ENABLE; 1613 break; 1614 case CARDBUS_IO_DISABLE: 1615 command &= ~PCI_COMMAND_IO_ENABLE; 1616 break; 1617 case CARDBUS_MEM_ENABLE: 1618 command |= PCI_COMMAND_MEM_ENABLE; 1619 break; 1620 case CARDBUS_MEM_DISABLE: 1621 command &= ~PCI_COMMAND_MEM_ENABLE; 1622 break; 1623 case CARDBUS_BM_ENABLE: 1624 command |= PCI_COMMAND_MASTER_ENABLE; 1625 break; 1626 case CARDBUS_BM_DISABLE: 1627 command &= ~PCI_COMMAND_MASTER_ENABLE; 1628 break; 1629 default: 1630 return 0; 1631 } 1632 1633 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1634 DPRINTF((" command reg 0x%x\n", command)); 1635 return 1; 1636 } 1637 1638 #if !rbus 1639 static int 1640 pccbb_io_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 1641 { 1642 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1643 int basereg; 1644 int limitreg; 1645 1646 if ((win < 0) || (win > 2)) { 1647 #if defined DIAGNOSTIC 1648 printf("cardbus_io_open: window out of range %d\n", win); 1649 #endif 1650 return 0; 1651 } 1652 1653 basereg = win * 8 + 0x2c; 1654 limitreg = win * 8 + 0x30; 1655 1656 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1657 start, basereg, end, limitreg)); 1658 1659 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1660 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1661 return 1; 1662 } 1663 1664 /* 1665 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1666 */ 1667 static int 1668 pccbb_io_close(cardbus_chipset_tag_t ct, int win) 1669 { 1670 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1671 int basereg; 1672 int limitreg; 1673 1674 if ((win < 0) || (win > 2)) { 1675 #if defined DIAGNOSTIC 1676 printf("cardbus_io_close: window out of range %d\n", win); 1677 #endif 1678 return 0; 1679 } 1680 1681 basereg = win * 8 + 0x2c; 1682 limitreg = win * 8 + 0x30; 1683 1684 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1685 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1686 return 1; 1687 } 1688 1689 static int 1690 pccbb_mem_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 1691 { 1692 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1693 int basereg; 1694 int limitreg; 1695 1696 if ((win < 0) || (win > 2)) { 1697 #if defined DIAGNOSTIC 1698 printf("cardbus_mem_open: window out of range %d\n", win); 1699 #endif 1700 return 0; 1701 } 1702 1703 basereg = win * 8 + 0x1c; 1704 limitreg = win * 8 + 0x20; 1705 1706 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1707 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1708 return 1; 1709 } 1710 1711 static int 1712 pccbb_mem_close(cardbus_chipset_tag_t ct, int win) 1713 { 1714 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1715 int basereg; 1716 int limitreg; 1717 1718 if ((win < 0) || (win > 2)) { 1719 #if defined DIAGNOSTIC 1720 printf("cardbus_mem_close: window out of range %d\n", win); 1721 #endif 1722 return 0; 1723 } 1724 1725 basereg = win * 8 + 0x1c; 1726 limitreg = win * 8 + 0x20; 1727 1728 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1729 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1730 return 1; 1731 } 1732 #endif 1733 1734 /* 1735 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1736 * int irq, 1737 * int level, 1738 * int (* func)(void *), 1739 * void *arg) 1740 * 1741 * This function registers an interrupt handler at the bridge, in 1742 * order not to call the interrupt handlers of child devices when 1743 * a card-deletion interrupt occurs. 1744 * 1745 * The arguments irq and level are not used. 1746 */ 1747 static void * 1748 pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, int irq, int level, 1749 int (*func)(void *), void *arg) 1750 { 1751 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1752 1753 return pccbb_intr_establish(sc, irq, level, func, arg); 1754 } 1755 1756 1757 /* 1758 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1759 * void *ih) 1760 * 1761 * This function removes an interrupt handler pointed by ih. 1762 */ 1763 static void 1764 pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih) 1765 { 1766 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1767 1768 pccbb_intr_disestablish(sc, ih); 1769 } 1770 1771 1772 void 1773 pccbb_intr_route(struct pccbb_softc *sc) 1774 { 1775 pcireg_t bcr, cbctrl; 1776 1777 /* initialize bridge intr routing */ 1778 bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1779 bcr &= ~CB_BCR_INTR_IREQ_ENABLE; 1780 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr); 1781 1782 switch (sc->sc_chipset) { 1783 case CB_TI113X: 1784 cbctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1785 /* functional intr enabled */ 1786 cbctrl |= PCI113X_CBCTRL_PCI_INTR; 1787 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, cbctrl); 1788 break; 1789 default: 1790 break; 1791 } 1792 } 1793 1794 /* 1795 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1796 * int irq, 1797 * int level, 1798 * int (* func)(void *), 1799 * void *arg) 1800 * 1801 * This function registers an interrupt handler at the bridge, in 1802 * order not to call the interrupt handlers of child devices when 1803 * a card-deletion interrupt occurs. 1804 * 1805 * The arguments irq is not used because pccbb selects intr vector. 1806 */ 1807 static void * 1808 pccbb_intr_establish(struct pccbb_softc *sc, int irq, int level, 1809 int (*func)(void *), void *arg) 1810 { 1811 struct pccbb_intrhand_list *pil, *newpil; 1812 1813 DPRINTF(("pccbb_intr_establish start. %p\n", LIST_FIRST(&sc->sc_pil))); 1814 1815 if (LIST_EMPTY(&sc->sc_pil)) { 1816 pccbb_intr_route(sc); 1817 } 1818 1819 /* 1820 * Allocate a room for interrupt handler structure. 1821 */ 1822 if (NULL == (newpil = 1823 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1824 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1825 return NULL; 1826 } 1827 1828 newpil->pil_func = func; 1829 newpil->pil_arg = arg; 1830 newpil->pil_icookie = makeiplcookie(level); 1831 1832 if (LIST_EMPTY(&sc->sc_pil)) { 1833 LIST_INSERT_HEAD(&sc->sc_pil, newpil, pil_next); 1834 } else { 1835 for (pil = LIST_FIRST(&sc->sc_pil); 1836 LIST_NEXT(pil, pil_next) != NULL; 1837 pil = LIST_NEXT(pil, pil_next)); 1838 LIST_INSERT_AFTER(pil, newpil, pil_next); 1839 } 1840 1841 DPRINTF(("pccbb_intr_establish add pil. %p\n", 1842 LIST_FIRST(&sc->sc_pil))); 1843 1844 return newpil; 1845 } 1846 1847 /* 1848 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1849 * void *ih) 1850 * 1851 * This function removes an interrupt handler pointed by ih. ih 1852 * should be the value returned by cardbus_intr_establish() or 1853 * NULL. 1854 * 1855 * When ih is NULL, this function will do nothing. 1856 */ 1857 static void 1858 pccbb_intr_disestablish(struct pccbb_softc *sc, void *ih) 1859 { 1860 struct pccbb_intrhand_list *pil; 1861 pcireg_t reg; 1862 1863 DPRINTF(("pccbb_intr_disestablish start. %p\n", 1864 LIST_FIRST(&sc->sc_pil))); 1865 1866 if (ih == NULL) { 1867 /* intr handler is not set */ 1868 DPRINTF(("pccbb_intr_disestablish: no ih\n")); 1869 return; 1870 } 1871 1872 #ifdef DIAGNOSTIC 1873 LIST_FOREACH(pil, &sc->sc_pil, pil_next) { 1874 DPRINTF(("pccbb_intr_disestablish: pil %p\n", pil)); 1875 if (pil == ih) { 1876 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1877 break; 1878 } 1879 } 1880 if (pil == NULL) { 1881 panic("pccbb_intr_disestablish: %s cannot find pil %p", 1882 sc->sc_dev.dv_xname, ih); 1883 } 1884 #endif 1885 1886 pil = (struct pccbb_intrhand_list *)ih; 1887 LIST_REMOVE(pil, pil_next); 1888 free(pil, M_DEVBUF); 1889 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1890 1891 if (LIST_EMPTY(&sc->sc_pil)) { 1892 /* No interrupt handlers */ 1893 1894 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1895 1896 /* stop routing PCI intr */ 1897 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1898 reg |= CB_BCR_INTR_IREQ_ENABLE; 1899 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, reg); 1900 1901 switch (sc->sc_chipset) { 1902 case CB_TI113X: 1903 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1904 /* functional intr disabled */ 1905 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1906 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1907 break; 1908 default: 1909 break; 1910 } 1911 } 1912 } 1913 1914 #if defined SHOW_REGS 1915 static void 1916 cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, bus_space_tag_t memt, 1917 bus_space_handle_t memh) 1918 { 1919 int i; 1920 printf("PCI config regs:"); 1921 for (i = 0; i < 0x50; i += 4) { 1922 if (i % 16 == 0) 1923 printf("\n 0x%02x:", i); 1924 printf(" %08x", pci_conf_read(pc, tag, i)); 1925 } 1926 for (i = 0x80; i < 0xb0; i += 4) { 1927 if (i % 16 == 0) 1928 printf("\n 0x%02x:", i); 1929 printf(" %08x", pci_conf_read(pc, tag, i)); 1930 } 1931 1932 if (memh == 0) { 1933 printf("\n"); 1934 return; 1935 } 1936 1937 printf("\nsocket regs:"); 1938 for (i = 0; i <= 0x10; i += 0x04) 1939 printf(" %08x", bus_space_read_4(memt, memh, i)); 1940 printf("\nExCA regs:"); 1941 for (i = 0; i < 0x08; ++i) 1942 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1943 printf("\n"); 1944 return; 1945 } 1946 #endif 1947 1948 /* 1949 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1950 * int busno, int function) 1951 * This is the function to make a tag to access config space of 1952 * a CardBus Card. It works same as pci_conf_read. 1953 */ 1954 static cardbustag_t 1955 pccbb_make_tag(cardbus_chipset_tag_t cc, int busno, int function) 1956 { 1957 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1958 1959 return pci_make_tag(sc->sc_pc, busno, 0, function); 1960 } 1961 1962 static void 1963 pccbb_free_tag(cardbus_chipset_tag_t cc, cardbustag_t tag) 1964 { 1965 } 1966 1967 /* 1968 * pccbb_conf_read 1969 * 1970 * This is the function to read the config space of a CardBus card. 1971 * It works the same as pci_conf_read(9). 1972 */ 1973 static cardbusreg_t 1974 pccbb_conf_read(cardbus_chipset_tag_t cc, cardbustag_t tag, int offset) 1975 { 1976 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1977 1978 return pci_conf_read(sc->sc_pc, tag, offset); 1979 } 1980 1981 /* 1982 * pccbb_conf_write 1983 * 1984 * This is the function to write the config space of a CardBus 1985 * card. It works the same as pci_conf_write(9). 1986 */ 1987 static void 1988 pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, int reg, 1989 cardbusreg_t val) 1990 { 1991 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1992 1993 pci_conf_write(sc->sc_pc, tag, reg, val); 1994 } 1995 1996 #if 0 1997 STATIC int 1998 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1999 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 2000 int speed, int flags, 2001 bus_space_handle_t * iohp) 2002 #endif 2003 /* 2004 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 2005 * bus_addr_t start, bus_size_t size, 2006 * bus_size_t align, 2007 * struct pcmcia_io_handle *pcihp 2008 * 2009 * This function only allocates I/O region for pccard. This function 2010 * never maps the allocated region to pccard I/O area. 2011 * 2012 * XXX: The interface of this function is not very good, I believe. 2013 */ 2014 STATIC int 2015 pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, 2016 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 2017 { 2018 struct pcic_handle *ph = (struct pcic_handle *)pch; 2019 bus_addr_t ioaddr; 2020 int flags = 0; 2021 bus_space_tag_t iot; 2022 bus_space_handle_t ioh; 2023 bus_addr_t mask; 2024 #if rbus 2025 rbus_tag_t rb; 2026 #endif 2027 if (align == 0) { 2028 align = size; /* XXX: funny??? */ 2029 } 2030 2031 if (start != 0) { 2032 /* XXX: assume all card decode lower 10 bits by its hardware */ 2033 mask = 0x3ff; 2034 /* enforce to use only masked address */ 2035 start &= mask; 2036 } else { 2037 /* 2038 * calculate mask: 2039 * 1. get the most significant bit of size (call it msb). 2040 * 2. compare msb with the value of size. 2041 * 3. if size is larger, shift msb left once. 2042 * 4. obtain mask value to decrement msb. 2043 */ 2044 bus_size_t size_tmp = size; 2045 int shifts = 0; 2046 2047 mask = 1; 2048 while (size_tmp) { 2049 ++shifts; 2050 size_tmp >>= 1; 2051 } 2052 mask = (1 << shifts); 2053 if (mask < size) { 2054 mask <<= 1; 2055 } 2056 --mask; 2057 } 2058 2059 /* 2060 * Allocate some arbitrary I/O space. 2061 */ 2062 2063 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 2064 2065 #if rbus 2066 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 2067 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 2068 return 1; 2069 } 2070 DPRINTF(("pccbb_pcmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2071 (u_long) ioaddr, (u_long) size)); 2072 #else 2073 if (start) { 2074 ioaddr = start; 2075 if (bus_space_map(iot, start, size, 0, &ioh)) { 2076 return 1; 2077 } 2078 DPRINTF(("pccbb_pcmcia_io_alloc map port 0x%lx+0x%lx\n", 2079 (u_long) ioaddr, (u_long) size)); 2080 } else { 2081 flags |= PCMCIA_IO_ALLOCATED; 2082 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 2083 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 2084 size, align, 0, 0, &ioaddr, &ioh)) { 2085 /* No room be able to be get. */ 2086 return 1; 2087 } 2088 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2089 (u_long) ioaddr, (u_long) size)); 2090 } 2091 #endif 2092 2093 pcihp->iot = iot; 2094 pcihp->ioh = ioh; 2095 pcihp->addr = ioaddr; 2096 pcihp->size = size; 2097 pcihp->flags = flags; 2098 2099 return 0; 2100 } 2101 2102 /* 2103 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2104 * struct pcmcia_io_handle *pcihp) 2105 * 2106 * This function only frees I/O region for pccard. 2107 * 2108 * XXX: The interface of this function is not very good, I believe. 2109 */ 2110 void 2111 pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2112 struct pcmcia_io_handle *pcihp) 2113 { 2114 #if !rbus 2115 bus_space_tag_t iot = pcihp->iot; 2116 #endif 2117 bus_space_handle_t ioh = pcihp->ioh; 2118 bus_size_t size = pcihp->size; 2119 2120 #if rbus 2121 struct pccbb_softc *sc = 2122 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 2123 rbus_tag_t rb = sc->sc_rbus_iot; 2124 2125 rbus_space_free(rb, ioh, size, NULL); 2126 #else 2127 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 2128 bus_space_free(iot, ioh, size); 2129 else 2130 bus_space_unmap(iot, ioh, size); 2131 #endif 2132 } 2133 2134 /* 2135 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 2136 * bus_addr_t offset, bus_size_t size, 2137 * struct pcmcia_io_handle *pcihp, 2138 * int *windowp) 2139 * 2140 * This function maps the allocated I/O region to pccard. This function 2141 * never allocates any I/O region for pccard I/O area. I don't 2142 * understand why the original authors of pcmciabus separated alloc and 2143 * map. I believe the two must be unite. 2144 * 2145 * XXX: no wait timing control? 2146 */ 2147 int 2148 pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, bus_addr_t offset, 2149 bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp) 2150 { 2151 struct pcic_handle *ph = (struct pcic_handle *)pch; 2152 bus_addr_t ioaddr = pcihp->addr + offset; 2153 int i, win; 2154 #if defined CBB_DEBUG 2155 static const char *width_names[] = { "dynamic", "io8", "io16" }; 2156 #endif 2157 2158 /* Sanity check I/O handle. */ 2159 2160 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 2161 panic("pccbb_pcmcia_io_map iot is bogus"); 2162 } 2163 2164 /* XXX Sanity check offset/size. */ 2165 2166 win = -1; 2167 for (i = 0; i < PCIC_IO_WINS; i++) { 2168 if ((ph->ioalloc & (1 << i)) == 0) { 2169 win = i; 2170 ph->ioalloc |= (1 << i); 2171 break; 2172 } 2173 } 2174 2175 if (win == -1) { 2176 return 1; 2177 } 2178 2179 *windowp = win; 2180 2181 /* XXX this is pretty gross */ 2182 2183 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2184 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2185 2186 /* XXX wtf is this doing here? */ 2187 2188 #if 0 2189 printf(" port 0x%lx", (u_long) ioaddr); 2190 if (size > 1) { 2191 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2192 } 2193 #endif 2194 2195 ph->io[win].addr = ioaddr; 2196 ph->io[win].size = size; 2197 ph->io[win].width = width; 2198 2199 /* actual dirty register-value changing in the function below. */ 2200 pccbb_pcmcia_do_io_map(ph, win); 2201 2202 return 0; 2203 } 2204 2205 /* 2206 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2207 * 2208 * This function changes register-value to map I/O region for pccard. 2209 */ 2210 static void 2211 pccbb_pcmcia_do_io_map(struct pcic_handle *ph, int win) 2212 { 2213 static u_int8_t pcic_iowidth[3] = { 2214 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2215 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2216 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2217 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2218 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2219 }; 2220 2221 #define PCIC_SIA_START_LOW 0 2222 #define PCIC_SIA_START_HIGH 1 2223 #define PCIC_SIA_STOP_LOW 2 2224 #define PCIC_SIA_STOP_HIGH 3 2225 2226 int regbase_win = 0x8 + win * 0x04; 2227 u_int8_t ioctl, enable; 2228 2229 DPRINTF(("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx " 2230 "width %d\n", win, (unsigned long)ph->io[win].addr, 2231 (unsigned long)ph->io[win].size, ph->io[win].width * 8)); 2232 2233 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2234 ph->io[win].addr & 0xff); 2235 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2236 (ph->io[win].addr >> 8) & 0xff); 2237 2238 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2239 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2240 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2241 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2242 2243 ioctl = Pcic_read(ph, PCIC_IOCTL); 2244 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2245 switch (win) { 2246 case 0: 2247 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2248 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2249 PCIC_IOCTL_IO0_DATASIZE_MASK); 2250 ioctl |= pcic_iowidth[ph->io[win].width]; 2251 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2252 break; 2253 case 1: 2254 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2255 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2256 PCIC_IOCTL_IO1_DATASIZE_MASK); 2257 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2258 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2259 break; 2260 } 2261 Pcic_write(ph, PCIC_IOCTL, ioctl); 2262 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2263 #if defined(CBB_DEBUG) 2264 { 2265 u_int8_t start_low = 2266 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2267 u_int8_t start_high = 2268 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2269 u_int8_t stop_low = 2270 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2271 u_int8_t stop_high = 2272 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2273 printf("pccbb_pcmcia_do_io_map start %02x %02x, " 2274 "stop %02x %02x, ioctl %02x enable %02x\n", 2275 start_low, start_high, stop_low, stop_high, ioctl, enable); 2276 } 2277 #endif 2278 } 2279 2280 /* 2281 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2282 * 2283 * This function unmaps I/O region. No return value. 2284 */ 2285 STATIC void 2286 pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t pch, int win) 2287 { 2288 struct pcic_handle *ph = (struct pcic_handle *)pch; 2289 int reg; 2290 2291 if (win >= PCIC_IO_WINS || win < 0) { 2292 panic("pccbb_pcmcia_io_unmap: window out of range"); 2293 } 2294 2295 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2296 switch (win) { 2297 case 0: 2298 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2299 break; 2300 case 1: 2301 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2302 break; 2303 } 2304 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2305 2306 ph->ioalloc &= ~(1 << win); 2307 } 2308 2309 static int 2310 pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 2311 { 2312 u_int8_t stat; 2313 int i; 2314 2315 /* wait an initial 10ms for quick cards */ 2316 stat = Pcic_read(ph, PCIC_IF_STATUS); 2317 if (stat & PCIC_IF_STATUS_READY) 2318 return (0); 2319 pccbb_pcmcia_delay(ph, 10, "pccwr0"); 2320 for (i = 0; i < 50; i++) { 2321 stat = Pcic_read(ph, PCIC_IF_STATUS); 2322 if (stat & PCIC_IF_STATUS_READY) 2323 return (0); 2324 if ((stat & PCIC_IF_STATUS_CARDDETECT_MASK) != 2325 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2326 return (ENXIO); 2327 /* wait .1s (100ms) each iteration now */ 2328 pccbb_pcmcia_delay(ph, 100, "pccwr1"); 2329 } 2330 2331 printf("pccbb_pcmcia_wait_ready: ready never happened, status=%02x\n", stat); 2332 return (EWOULDBLOCK); 2333 } 2334 2335 /* 2336 * Perform long (msec order) delay. timo is in milliseconds. 2337 */ 2338 static void 2339 pccbb_pcmcia_delay(struct pcic_handle *ph, int timo, const char *wmesg) 2340 { 2341 #ifdef DIAGNOSTIC 2342 if (timo <= 0) 2343 panic("pccbb_pcmcia_delay: called with timeout %d", timo); 2344 if (!curlwp) 2345 panic("pccbb_pcmcia_delay: called in interrupt context"); 2346 #if 0 2347 if (!ph->event_thread) 2348 panic("pccbb_pcmcia_delay: no event thread"); 2349 #endif 2350 #endif 2351 DPRINTF(("pccbb_pcmcia_delay: \"%s\" %p, sleep %d ms\n", 2352 wmesg, ph->event_thread, timo)); 2353 tsleep(pccbb_pcmcia_delay, PWAIT, wmesg, roundup(timo * hz, 1000) / 1000); 2354 } 2355 2356 /* 2357 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2358 * 2359 * This function enables the card. All information is stored in 2360 * the first argument, pcmcia_chipset_handle_t. 2361 */ 2362 STATIC void 2363 pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2364 { 2365 struct pcic_handle *ph = (struct pcic_handle *)pch; 2366 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2367 pcireg_t spsr; 2368 int voltage; 2369 int win; 2370 u_int8_t power, intr; 2371 #ifdef DIAGNOSTIC 2372 int reg; 2373 #endif 2374 2375 /* this bit is mostly stolen from pcic_attach_card */ 2376 2377 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2378 2379 /* get card Vcc info */ 2380 spsr = 2381 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2382 CB_SOCKET_STAT); 2383 if (spsr & CB_SOCKET_STAT_5VCARD) { 2384 DPRINTF(("5V card\n")); 2385 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2386 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2387 DPRINTF(("3V card\n")); 2388 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2389 } else { 2390 DPRINTF(("?V card, 0x%x\n", spsr)); /* XXX */ 2391 return; 2392 } 2393 2394 /* disable interrupts; assert RESET */ 2395 intr = Pcic_read(ph, PCIC_INTR); 2396 intr &= PCIC_INTR_ENABLE; 2397 Pcic_write(ph, PCIC_INTR, intr); 2398 2399 /* zero out the address windows */ 2400 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2401 2402 /* power down the socket to reset it, clear the card reset pin */ 2403 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2404 2405 /* power off; assert output enable bit */ 2406 power = PCIC_PWRCTL_OE; 2407 Pcic_write(ph, PCIC_PWRCTL, power); 2408 2409 /* power up the socket */ 2410 if (pccbb_power(sc, voltage) == 0) 2411 return; 2412 2413 /* 2414 * Table 4-18 and figure 4-6 of the PC Card specifiction say: 2415 * Vcc Rising Time (Tpr) = 100ms (handled in pccbb_power() above) 2416 * RESET Width (Th (Hi-z RESET)) = 1ms 2417 * RESET Width (Tw (RESET)) = 10us 2418 * 2419 * some machines require some more time to be settled 2420 * for example old toshiba topic bridges! 2421 * (100ms is added here). 2422 */ 2423 pccbb_pcmcia_delay(ph, 200 + 1, "pccen1"); 2424 2425 /* negate RESET */ 2426 intr |= PCIC_INTR_RESET; 2427 Pcic_write(ph, PCIC_INTR, intr); 2428 2429 /* 2430 * RESET Setup Time (Tsu (RESET)) = 20ms 2431 */ 2432 pccbb_pcmcia_delay(ph, 20, "pccen2"); 2433 2434 #ifdef DIAGNOSTIC 2435 reg = Pcic_read(ph, PCIC_IF_STATUS); 2436 if ((reg & PCIC_IF_STATUS_POWERACTIVE) == 0) 2437 printf("pccbb_pcmcia_socket_enable: no power, status=%x\n", reg); 2438 #endif 2439 2440 /* wait for the chip to finish initializing */ 2441 if (pccbb_pcmcia_wait_ready(ph)) { 2442 #ifdef DIAGNOSTIC 2443 printf("pccbb_pcmcia_socket_enable: never became ready\n"); 2444 #endif 2445 /* XXX return a failure status?? */ 2446 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2447 Pcic_write(ph, PCIC_PWRCTL, 0); 2448 return; 2449 } 2450 2451 /* reinstall all the memory and io mappings */ 2452 for (win = 0; win < PCIC_MEM_WINS; ++win) 2453 if (ph->memalloc & (1 << win)) 2454 pccbb_pcmcia_do_mem_map(ph, win); 2455 for (win = 0; win < PCIC_IO_WINS; ++win) 2456 if (ph->ioalloc & (1 << win)) 2457 pccbb_pcmcia_do_io_map(ph, win); 2458 } 2459 2460 /* 2461 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2462 * 2463 * This function disables the card. All information is stored in 2464 * the first argument, pcmcia_chipset_handle_t. 2465 */ 2466 STATIC void 2467 pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t pch) 2468 { 2469 struct pcic_handle *ph = (struct pcic_handle *)pch; 2470 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2471 u_int8_t intr; 2472 2473 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2474 2475 /* disable interrupts; assert RESET */ 2476 intr = Pcic_read(ph, PCIC_INTR); 2477 intr &= PCIC_INTR_ENABLE; 2478 Pcic_write(ph, PCIC_INTR, intr); 2479 2480 /* zero out the address windows */ 2481 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2482 2483 /* power down the socket to reset it, clear the card reset pin */ 2484 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2485 2486 /* disable socket: negate output enable bit and power off */ 2487 Pcic_write(ph, PCIC_PWRCTL, 0); 2488 2489 /* 2490 * Vcc Falling Time (Tpf) = 300ms 2491 */ 2492 pccbb_pcmcia_delay(ph, 300, "pccwr1"); 2493 } 2494 2495 STATIC void 2496 pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t pch, int type) 2497 { 2498 struct pcic_handle *ph = (struct pcic_handle *)pch; 2499 u_int8_t intr; 2500 2501 /* set the card type */ 2502 2503 intr = Pcic_read(ph, PCIC_INTR); 2504 intr &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_CARDTYPE_MASK); 2505 if (type == PCMCIA_IFTYPE_IO) 2506 intr |= PCIC_INTR_CARDTYPE_IO; 2507 else 2508 intr |= PCIC_INTR_CARDTYPE_MEM; 2509 Pcic_write(ph, PCIC_INTR, intr); 2510 2511 DPRINTF(("%s: pccbb_pcmcia_socket_settype %02x type %s %02x\n", 2512 ph->ph_parent->dv_xname, ph->sock, 2513 ((type == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2514 } 2515 2516 /* 2517 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2518 * 2519 * This function detects whether a card is in the slot or not. 2520 * If a card is inserted, return 1. Otherwise, return 0. 2521 */ 2522 STATIC int 2523 pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch) 2524 { 2525 struct pcic_handle *ph = (struct pcic_handle *)pch; 2526 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2527 2528 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2529 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2530 } 2531 2532 #if 0 2533 STATIC int 2534 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2535 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2536 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2537 #endif 2538 /* 2539 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2540 * bus_size_t size, 2541 * struct pcmcia_mem_handle *pcmhp) 2542 * 2543 * This function only allocates memory region for pccard. This 2544 * function never maps the allocated region to pccard memory area. 2545 * 2546 * XXX: Why the argument of start address is not in? 2547 */ 2548 STATIC int 2549 pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 2550 struct pcmcia_mem_handle *pcmhp) 2551 { 2552 struct pcic_handle *ph = (struct pcic_handle *)pch; 2553 bus_space_handle_t memh; 2554 bus_addr_t addr; 2555 bus_size_t sizepg; 2556 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2557 #if rbus 2558 rbus_tag_t rb; 2559 #endif 2560 2561 /* Check that the card is still there. */ 2562 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2563 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2564 return 1; 2565 2566 /* out of sc->memh, allocate as many pages as necessary */ 2567 2568 /* convert size to PCIC pages */ 2569 /* 2570 * This is not enough; when the requested region is on the page 2571 * boundaries, this may calculate wrong result. 2572 */ 2573 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2574 #if 0 2575 if (sizepg > PCIC_MAX_MEM_PAGES) { 2576 return 1; 2577 } 2578 #endif 2579 2580 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2581 return 1; 2582 } 2583 2584 addr = 0; /* XXX gcc -Wuninitialized */ 2585 2586 #if rbus 2587 rb = sc->sc_rbus_memt; 2588 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2589 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2590 &addr, &memh)) { 2591 return 1; 2592 } 2593 #else 2594 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2595 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2596 0, /* boundary */ 2597 0, /* flags */ 2598 &addr, &memh)) { 2599 return 1; 2600 } 2601 #endif 2602 2603 DPRINTF(("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, " 2604 "realsize 0x%lx\n", (unsigned long)addr, (unsigned long)size, 2605 (unsigned long)sizepg * PCIC_MEM_PAGESIZE)); 2606 2607 pcmhp->memt = sc->sc_memt; 2608 pcmhp->memh = memh; 2609 pcmhp->addr = addr; 2610 pcmhp->size = size; 2611 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2612 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2613 pcmhp->mhandle = 0; 2614 /* No offset??? Funny. */ 2615 2616 return 0; 2617 } 2618 2619 /* 2620 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2621 * struct pcmcia_mem_handle *pcmhp) 2622 * 2623 * This function release the memory space allocated by the function 2624 * pccbb_pcmcia_mem_alloc(). 2625 */ 2626 STATIC void 2627 pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2628 struct pcmcia_mem_handle *pcmhp) 2629 { 2630 #if rbus 2631 struct pcic_handle *ph = (struct pcic_handle *)pch; 2632 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2633 2634 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2635 #else 2636 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2637 #endif 2638 } 2639 2640 /* 2641 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2642 * 2643 * This function release the memory space allocated by the function 2644 * pccbb_pcmcia_mem_alloc(). 2645 */ 2646 STATIC void 2647 pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2648 { 2649 int regbase_win; 2650 bus_addr_t phys_addr; 2651 bus_addr_t phys_end; 2652 2653 #define PCIC_SMM_START_LOW 0 2654 #define PCIC_SMM_START_HIGH 1 2655 #define PCIC_SMM_STOP_LOW 2 2656 #define PCIC_SMM_STOP_HIGH 3 2657 #define PCIC_CMA_LOW 4 2658 #define PCIC_CMA_HIGH 5 2659 2660 u_int8_t start_low, start_high = 0; 2661 u_int8_t stop_low, stop_high; 2662 u_int8_t off_low, off_high; 2663 u_int8_t mem_window; 2664 int reg; 2665 2666 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2667 int mem8 = 2668 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2669 || (kind == PCMCIA_MEM_ATTR); 2670 2671 regbase_win = 0x10 + win * 0x08; 2672 2673 phys_addr = ph->mem[win].addr; 2674 phys_end = phys_addr + ph->mem[win].size; 2675 2676 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2677 (unsigned long)phys_addr, (unsigned long)phys_end, 2678 (unsigned long)ph->mem[win].offset)); 2679 2680 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2681 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2682 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2683 2684 /* bit 19:12 */ 2685 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2686 /* bit 23:20 and bit 7 on */ 2687 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2688 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2689 /* bit 31:24, for 32-bit address */ 2690 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2691 2692 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2693 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2694 2695 if (((struct pccbb_softc *)ph-> 2696 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2697 Pcic_write(ph, 0x40 + win, mem_window); 2698 } 2699 2700 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2701 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2702 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2703 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2704 2705 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2706 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2707 2708 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2709 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2710 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2711 | ((kind == PCMCIA_MEM_ATTR) ? 2712 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2713 2714 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2715 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2716 2717 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2718 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2719 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2720 2721 #if defined(CBB_DEBUG) 2722 { 2723 int r1, r2, r3, r4, r5, r6, r7 = 0; 2724 2725 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2726 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2727 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2728 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2729 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2730 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2731 if (((struct pccbb_softc *)(ph-> 2732 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2733 r7 = Pcic_read(ph, 0x40 + win); 2734 } 2735 2736 printf("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2737 "%02x%02x", win, r1, r2, r3, r4, r5, r6); 2738 if (((struct pccbb_softc *)(ph-> 2739 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2740 printf(" %02x", r7); 2741 } 2742 printf("\n"); 2743 } 2744 #endif 2745 } 2746 2747 /* 2748 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2749 * bus_addr_t card_addr, bus_size_t size, 2750 * struct pcmcia_mem_handle *pcmhp, 2751 * bus_addr_t *offsetp, int *windowp) 2752 * 2753 * This function maps memory space allocated by the function 2754 * pccbb_pcmcia_mem_alloc(). 2755 */ 2756 STATIC int 2757 pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2758 bus_addr_t card_addr, bus_size_t size, struct pcmcia_mem_handle *pcmhp, 2759 bus_addr_t *offsetp, int *windowp) 2760 { 2761 struct pcic_handle *ph = (struct pcic_handle *)pch; 2762 bus_addr_t busaddr; 2763 long card_offset; 2764 int win; 2765 2766 /* Check that the card is still there. */ 2767 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2768 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2769 return 1; 2770 2771 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2772 if ((ph->memalloc & (1 << win)) == 0) { 2773 ph->memalloc |= (1 << win); 2774 break; 2775 } 2776 } 2777 2778 if (win == PCIC_MEM_WINS) { 2779 return 1; 2780 } 2781 2782 *windowp = win; 2783 2784 /* XXX this is pretty gross */ 2785 2786 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2787 panic("pccbb_pcmcia_mem_map memt is bogus"); 2788 } 2789 2790 busaddr = pcmhp->addr; 2791 2792 /* 2793 * compute the address offset to the pcmcia address space for the 2794 * pcic. this is intentionally signed. The masks and shifts below 2795 * will cause TRT to happen in the pcic registers. Deal with making 2796 * sure the address is aligned, and return the alignment offset. 2797 */ 2798 2799 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2800 card_addr -= *offsetp; 2801 2802 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2803 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2804 (u_long) card_addr)); 2805 2806 /* 2807 * include the offset in the size, and decrement size by one, since 2808 * the hw wants start/stop 2809 */ 2810 size += *offsetp - 1; 2811 2812 card_offset = (((long)card_addr) - ((long)busaddr)); 2813 2814 ph->mem[win].addr = busaddr; 2815 ph->mem[win].size = size; 2816 ph->mem[win].offset = card_offset; 2817 ph->mem[win].kind = kind; 2818 2819 pccbb_pcmcia_do_mem_map(ph, win); 2820 2821 return 0; 2822 } 2823 2824 /* 2825 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2826 * int window) 2827 * 2828 * This function unmaps memory space which mapped by the function 2829 * pccbb_pcmcia_mem_map(). 2830 */ 2831 STATIC void 2832 pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, int window) 2833 { 2834 struct pcic_handle *ph = (struct pcic_handle *)pch; 2835 int reg; 2836 2837 if (window >= PCIC_MEM_WINS) { 2838 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2839 } 2840 2841 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2842 reg &= ~(1 << window); 2843 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2844 2845 ph->memalloc &= ~(1 << window); 2846 } 2847 2848 #if defined PCCBB_PCMCIA_POLL 2849 struct pccbb_poll_str { 2850 void *arg; 2851 int (*func)(void *); 2852 int level; 2853 struct pcic_handle *ph; 2854 int count; 2855 int num; 2856 struct callout poll_ch; 2857 }; 2858 2859 static struct pccbb_poll_str pccbb_poll[10]; 2860 static int pccbb_poll_n = 0; 2861 2862 static void pccbb_pcmcia_poll(void *arg); 2863 2864 static void 2865 pccbb_pcmcia_poll(void *arg) 2866 { 2867 struct pccbb_poll_str *poll = arg; 2868 struct pcic_handle *ph = poll->ph; 2869 struct pccbb_softc *sc = ph->sc; 2870 int s; 2871 u_int32_t spsr; /* socket present-state reg */ 2872 2873 callout_reset(&poll->poll_ch, hz * 2, pccbb_pcmcia_poll, arg); 2874 switch (poll->level) { 2875 case IPL_NET: 2876 s = splnet(); 2877 break; 2878 case IPL_BIO: 2879 s = splbio(); 2880 break; 2881 case IPL_TTY: /* fallthrough */ 2882 default: 2883 s = spltty(); 2884 break; 2885 } 2886 2887 spsr = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2888 CB_SOCKET_STAT); 2889 2890 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2891 if (!(spsr & 0x40)) /* CINT low */ 2892 #else 2893 if (1) 2894 #endif 2895 { 2896 if ((*poll->func) (poll->arg) > 0) { 2897 ++poll->count; 2898 /* printf("intr: reported from poller, 0x%x\n", spsr); */ 2899 #if defined LEVEL2 2900 } else { 2901 printf("intr: miss! 0x%x\n", spsr); 2902 #endif 2903 } 2904 } 2905 splx(s); 2906 } 2907 #endif /* defined CB_PCMCIA_POLL */ 2908 2909 /* 2910 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2911 * struct pcmcia_function *pf, 2912 * int ipl, 2913 * int (*func)(void *), 2914 * void *arg); 2915 * 2916 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2917 */ 2918 STATIC void * 2919 pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2920 struct pcmcia_function *pf, int ipl, int (*func)(void *), void *arg) 2921 { 2922 struct pcic_handle *ph = (struct pcic_handle *)pch; 2923 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2924 2925 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2926 /* what should I do? */ 2927 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2928 DPRINTF(("%s does not provide edge nor pulse " 2929 "interrupt\n", sc->sc_dev.dv_xname)); 2930 return NULL; 2931 } 2932 /* 2933 * XXX Noooooo! The interrupt flag must set properly!! 2934 * dumb pcmcia driver!! 2935 */ 2936 } 2937 2938 return pccbb_intr_establish(sc, 0, ipl, func, arg); 2939 } 2940 2941 /* 2942 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2943 * void *ih) 2944 * 2945 * This function disables PC-Card interrupt. 2946 */ 2947 STATIC void 2948 pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 2949 { 2950 struct pcic_handle *ph = (struct pcic_handle *)pch; 2951 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2952 2953 pccbb_intr_disestablish(sc, ih); 2954 } 2955 2956 #if rbus 2957 /* 2958 * static int 2959 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2960 * bus_addr_t addr, bus_size_t size, 2961 * bus_addr_t mask, bus_size_t align, 2962 * int flags, bus_addr_t *addrp; 2963 * bus_space_handle_t *bshp) 2964 * 2965 * This function allocates a portion of memory or io space for 2966 * clients. This function is called from CardBus card drivers. 2967 */ 2968 static int 2969 pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2970 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 2971 int flags, bus_addr_t *addrp, bus_space_handle_t *bshp) 2972 { 2973 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2974 2975 DPRINTF(("pccbb_rbus_cb_space_alloc: addr 0x%lx, size 0x%lx, " 2976 "mask 0x%lx, align 0x%lx\n", (unsigned long)addr, 2977 (unsigned long)size, (unsigned long)mask, (unsigned long)align)); 2978 2979 if (align == 0) { 2980 align = size; 2981 } 2982 2983 if (rb->rb_bt == sc->sc_memt) { 2984 if (align < 16) { 2985 return 1; 2986 } 2987 /* 2988 * XXX: align more than 0x1000 to avoid overwrapping 2989 * memory windows for two or more devices. 0x1000 2990 * means memory window's granularity. 2991 * 2992 * Two or more devices should be able to share same 2993 * memory window region. However, overrapping memory 2994 * window is not good because some devices, such as 2995 * 3Com 3C575[BC], have a broken address decoder and 2996 * intrude other's memory region. 2997 */ 2998 if (align < 0x1000) { 2999 align = 0x1000; 3000 } 3001 } else if (rb->rb_bt == sc->sc_iot) { 3002 if (align < 4) { 3003 return 1; 3004 } 3005 /* XXX: hack for avoiding ISA image */ 3006 if (mask < 0x0100) { 3007 mask = 0x3ff; 3008 addr = 0x300; 3009 } 3010 3011 } else { 3012 DPRINTF(("pccbb_rbus_cb_space_alloc: Bus space tag 0x%lx is " 3013 "NOT used. io: 0x%lx, mem: 0x%lx\n", 3014 (unsigned long)rb->rb_bt, (unsigned long)sc->sc_iot, 3015 (unsigned long)sc->sc_memt)); 3016 return 1; 3017 /* XXX: panic here? */ 3018 } 3019 3020 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 3021 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 3022 return 1; 3023 } 3024 3025 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 3026 3027 return 0; 3028 } 3029 3030 /* 3031 * static int 3032 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 3033 * bus_space_handle_t *bshp, bus_size_t size); 3034 * 3035 * This function is called from CardBus card drivers. 3036 */ 3037 static int 3038 pccbb_rbus_cb_space_free(cardbus_chipset_tag_t ct, rbus_tag_t rb, 3039 bus_space_handle_t bsh, bus_size_t size) 3040 { 3041 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 3042 bus_space_tag_t bt = rb->rb_bt; 3043 3044 pccbb_close_win(sc, bt, bsh, size); 3045 3046 if (bt == sc->sc_memt) { 3047 } else if (bt == sc->sc_iot) { 3048 } else { 3049 return 1; 3050 /* XXX: panic here? */ 3051 } 3052 3053 return rbus_space_free(rb, bsh, size, NULL); 3054 } 3055 #endif /* rbus */ 3056 3057 #if rbus 3058 3059 static int 3060 pccbb_open_win(struct pccbb_softc *sc, bus_space_tag_t bst, bus_addr_t addr, 3061 bus_size_t size, bus_space_handle_t bsh, int flags) 3062 { 3063 struct pccbb_win_chain_head *head; 3064 bus_addr_t align; 3065 3066 head = &sc->sc_iowindow; 3067 align = 0x04; 3068 if (sc->sc_memt == bst) { 3069 head = &sc->sc_memwindow; 3070 align = 0x1000; 3071 DPRINTF(("using memory window, 0x%lx 0x%lx 0x%lx\n\n", 3072 (unsigned long)sc->sc_iot, (unsigned long)sc->sc_memt, 3073 (unsigned long)bst)); 3074 } 3075 3076 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 3077 printf("%s: pccbb_open_win: %s winlist insert failed\n", 3078 sc->sc_dev.dv_xname, 3079 (head == &sc->sc_memwindow) ? "mem" : "io"); 3080 } 3081 pccbb_winset(align, sc, bst); 3082 3083 return 0; 3084 } 3085 3086 static int 3087 pccbb_close_win(struct pccbb_softc *sc, bus_space_tag_t bst, 3088 bus_space_handle_t bsh, bus_size_t size) 3089 { 3090 struct pccbb_win_chain_head *head; 3091 bus_addr_t align; 3092 3093 head = &sc->sc_iowindow; 3094 align = 0x04; 3095 if (sc->sc_memt == bst) { 3096 head = &sc->sc_memwindow; 3097 align = 0x1000; 3098 } 3099 3100 if (pccbb_winlist_delete(head, bsh, size)) { 3101 printf("%s: pccbb_close_win: %s winlist delete failed\n", 3102 sc->sc_dev.dv_xname, 3103 (head == &sc->sc_memwindow) ? "mem" : "io"); 3104 } 3105 pccbb_winset(align, sc, bst); 3106 3107 return 0; 3108 } 3109 3110 static int 3111 pccbb_winlist_insert(struct pccbb_win_chain_head *head, bus_addr_t start, 3112 bus_size_t size, bus_space_handle_t bsh, int flags) 3113 { 3114 struct pccbb_win_chain *chainp, *elem; 3115 3116 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 3117 M_NOWAIT)) == NULL) 3118 return (1); /* fail */ 3119 3120 elem->wc_start = start; 3121 elem->wc_end = start + (size - 1); 3122 elem->wc_handle = bsh; 3123 elem->wc_flags = flags; 3124 3125 TAILQ_FOREACH(chainp, head, wc_list) { 3126 if (chainp->wc_end >= start) 3127 break; 3128 } 3129 if (chainp != NULL) 3130 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 3131 else 3132 TAILQ_INSERT_TAIL(head, elem, wc_list); 3133 return (0); 3134 } 3135 3136 static int 3137 pccbb_winlist_delete(struct pccbb_win_chain_head *head, bus_space_handle_t bsh, 3138 bus_size_t size) 3139 { 3140 struct pccbb_win_chain *chainp; 3141 3142 TAILQ_FOREACH(chainp, head, wc_list) { 3143 if (memcmp(&chainp->wc_handle, &bsh, sizeof(bsh)) == 0) 3144 break; 3145 } 3146 if (chainp == NULL) 3147 return 1; /* fail: no candidate to remove */ 3148 3149 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 3150 printf("pccbb_winlist_delete: window 0x%lx size " 3151 "inconsistent: 0x%lx, 0x%lx\n", 3152 (unsigned long)chainp->wc_start, 3153 (unsigned long)(chainp->wc_end - chainp->wc_start), 3154 (unsigned long)(size - 1)); 3155 return 1; 3156 } 3157 3158 TAILQ_REMOVE(head, chainp, wc_list); 3159 free(chainp, M_DEVBUF); 3160 3161 return 0; 3162 } 3163 3164 static void 3165 pccbb_winset(bus_addr_t align, struct pccbb_softc *sc, bus_space_tag_t bst) 3166 { 3167 pci_chipset_tag_t pc; 3168 pcitag_t tag; 3169 bus_addr_t mask = ~(align - 1); 3170 struct { 3171 cardbusreg_t win_start; 3172 cardbusreg_t win_limit; 3173 int win_flags; 3174 } win[2]; 3175 struct pccbb_win_chain *chainp; 3176 int offs; 3177 3178 win[0].win_start = win[1].win_start = 0xffffffff; 3179 win[0].win_limit = win[1].win_limit = 0; 3180 win[0].win_flags = win[1].win_flags = 0; 3181 3182 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3183 offs = 0x2c; 3184 if (sc->sc_memt == bst) { 3185 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3186 offs = 0x1c; 3187 } 3188 3189 if (chainp != NULL) { 3190 win[0].win_start = chainp->wc_start & mask; 3191 win[0].win_limit = chainp->wc_end & mask; 3192 win[0].win_flags = chainp->wc_flags; 3193 chainp = TAILQ_NEXT(chainp, wc_list); 3194 } 3195 3196 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3197 if (win[1].win_start == 0xffffffff) { 3198 /* window 1 is not used */ 3199 if ((win[0].win_flags == chainp->wc_flags) && 3200 (win[0].win_limit + align >= 3201 (chainp->wc_start & mask))) { 3202 /* concatenate */ 3203 win[0].win_limit = chainp->wc_end & mask; 3204 } else { 3205 /* make new window */ 3206 win[1].win_start = chainp->wc_start & mask; 3207 win[1].win_limit = chainp->wc_end & mask; 3208 win[1].win_flags = chainp->wc_flags; 3209 } 3210 continue; 3211 } 3212 3213 /* Both windows are engaged. */ 3214 if (win[0].win_flags == win[1].win_flags) { 3215 /* same flags */ 3216 if (win[0].win_flags == chainp->wc_flags) { 3217 if (win[1].win_start - (win[0].win_limit + 3218 align) < 3219 (chainp->wc_start & mask) - 3220 ((chainp->wc_end & mask) + align)) { 3221 /* 3222 * merge window 0 and 1, and set win1 3223 * to chainp 3224 */ 3225 win[0].win_limit = win[1].win_limit; 3226 win[1].win_start = 3227 chainp->wc_start & mask; 3228 win[1].win_limit = 3229 chainp->wc_end & mask; 3230 } else { 3231 win[1].win_limit = 3232 chainp->wc_end & mask; 3233 } 3234 } else { 3235 /* different flags */ 3236 3237 /* concatenate win0 and win1 */ 3238 win[0].win_limit = win[1].win_limit; 3239 /* allocate win[1] to new space */ 3240 win[1].win_start = chainp->wc_start & mask; 3241 win[1].win_limit = chainp->wc_end & mask; 3242 win[1].win_flags = chainp->wc_flags; 3243 } 3244 } else { 3245 /* the flags of win[0] and win[1] is different */ 3246 if (win[0].win_flags == chainp->wc_flags) { 3247 win[0].win_limit = chainp->wc_end & mask; 3248 /* 3249 * XXX this creates overlapping windows, so 3250 * what should the poor bridge do if one is 3251 * cachable, and the other is not? 3252 */ 3253 printf("%s: overlapping windows\n", 3254 sc->sc_dev.dv_xname); 3255 } else { 3256 win[1].win_limit = chainp->wc_end & mask; 3257 } 3258 } 3259 } 3260 3261 pc = sc->sc_pc; 3262 tag = sc->sc_tag; 3263 pci_conf_write(pc, tag, offs, win[0].win_start); 3264 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3265 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3266 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3267 DPRINTF(("--pccbb_winset: win0 [0x%lx, 0x%lx), win1 [0x%lx, 0x%lx)\n", 3268 (unsigned long)pci_conf_read(pc, tag, offs), 3269 (unsigned long)pci_conf_read(pc, tag, offs + 4) + align, 3270 (unsigned long)pci_conf_read(pc, tag, offs + 8), 3271 (unsigned long)pci_conf_read(pc, tag, offs + 12) + align)); 3272 3273 if (bst == sc->sc_memt) { 3274 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BRIDGE_CONTROL_REG); 3275 3276 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 3277 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 3278 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3279 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 3280 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3281 pci_conf_write(pc, tag, PCI_BRIDGE_CONTROL_REG, bcr); 3282 } 3283 } 3284 3285 #endif /* rbus */ 3286 3287 static bool 3288 pccbb_suspend(device_t dv) 3289 { 3290 struct pccbb_softc *sc = device_private(dv); 3291 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3292 bus_space_handle_t base_memh = sc->sc_base_memh; 3293 pcireg_t reg; 3294 3295 if (sc->sc_pil_intr_enable) 3296 (void)pccbbintr_function(sc); 3297 sc->sc_pil_intr_enable = 0; 3298 3299 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3300 /* Disable interrupts. */ 3301 reg &= ~(CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER); 3302 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3303 /* XXX joerg Disable power to the socket? */ 3304 3305 #ifdef __NO_STRICT_ALIGNMENT 3306 /* XXX - the register is at 0x82, so this access is not valid */ 3307 if (sc->sc_chipset == CB_RX5C47X) 3308 sc->sc_ricoh_misc_ctrl = pci_conf_read(sc->sc_pc, 3309 sc->sc_tag, RICOH_PCI_MISC_CTRL); 3310 #endif 3311 3312 return true; 3313 } 3314 3315 static bool 3316 pccbb_resume(device_t dv) 3317 { 3318 struct pccbb_softc *sc = device_private(dv); 3319 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3320 bus_space_handle_t base_memh = sc->sc_base_memh; 3321 pcireg_t reg; 3322 3323 pccbb_chipinit(sc); 3324 /* setup memory and io space window for CB */ 3325 pccbb_winset(0x1000, sc, sc->sc_memt); 3326 pccbb_winset(0x04, sc, sc->sc_iot); 3327 #ifdef __NO_STRICT_ALIGNMENT 3328 /* XXX - the register is at 0x82, so this access is not valid */ 3329 if (sc->sc_chipset == CB_RX5C47X) 3330 pci_conf_write(sc->sc_pc, sc->sc_tag, 3331 RICOH_PCI_MISC_CTRL, sc->sc_ricoh_misc_ctrl); 3332 #endif 3333 3334 /* CSC Interrupt: Card detect interrupt on */ 3335 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3336 /* Card detect intr is turned on. */ 3337 reg |= CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; 3338 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3339 /* reset interrupt */ 3340 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3341 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3342 3343 /* 3344 * check for card insertion or removal during suspend period. 3345 * XXX: the code can't cope with card swap (remove then 3346 * insert). how can we detect such situation? 3347 */ 3348 (void)pccbbintr(sc); 3349 3350 sc->sc_pil_intr_enable = 1; 3351 3352 return true; 3353 } 3354
Indexes created Fri Sep 26 20:09:58 GMT 2025