pccbb.c revision 1.162
1 /* $NetBSD: pccbb.c,v 1.162 2008/01/14 06:12:13 dyoung Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: pccbb.c,v 1.162 2008/01/14 06:12:13 dyoung Exp $"); 35 36 /* 37 #define CBB_DEBUG 38 #define SHOW_REGS 39 */ 40 41 /* 42 * BROKEN! 43 #define PCCBB_PCMCIA_POLL 44 #define CB_PCMCIA_POLL 45 #define CB_PCMCIA_POLL_ONLY 46 #define LEVEL2 47 */ 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/kernel.h> 52 #include <sys/errno.h> 53 #include <sys/ioctl.h> 54 #include <sys/reboot.h> /* for bootverbose */ 55 #include <sys/syslog.h> 56 #include <sys/device.h> 57 #include <sys/malloc.h> 58 #include <sys/proc.h> 59 60 #include <sys/intr.h> 61 #include <sys/bus.h> 62 63 #include <dev/pci/pcivar.h> 64 #include <dev/pci/pcireg.h> 65 #include <dev/pci/pcidevs.h> 66 67 #include <dev/pci/pccbbreg.h> 68 69 #include <dev/cardbus/cardslotvar.h> 70 71 #include <dev/cardbus/cardbusvar.h> 72 73 #include <dev/pcmcia/pcmciareg.h> 74 #include <dev/pcmcia/pcmciavar.h> 75 76 #include <dev/ic/i82365reg.h> 77 #include <dev/ic/i82365var.h> 78 #include <dev/pci/pccbbvar.h> 79 80 #include "locators.h" 81 82 #ifndef __NetBSD_Version__ 83 struct cfdriver cbb_cd = { 84 NULL, "cbb", DV_DULL 85 }; 86 #endif 87 88 #ifdef CBB_DEBUG 89 #define DPRINTF(x) printf x 90 #define STATIC 91 #else 92 #define DPRINTF(x) 93 #define STATIC static 94 #endif 95 96 int pccbb_burstup = 1; 97 98 /* 99 * delay_ms() is wait in milliseconds. It should be used instead 100 * of delay() if you want to wait more than 1 ms. 101 */ 102 static inline void 103 delay_ms(int millis, void *param) 104 { 105 if (cold) 106 delay(millis * 1000); 107 else 108 tsleep(param, PWAIT, "pccbb", MAX(2, hz * millis / 1000)); 109 } 110 111 int pcicbbmatch(device_t, struct cfdata *, void *); 112 void pccbbattach(device_t, device_t, void *); 113 int pccbbdetach(device_t, int); 114 int pccbbintr(void *); 115 static void pci113x_insert(void *); 116 static int pccbbintr_function(struct pccbb_softc *); 117 118 static int pccbb_detect_card(struct pccbb_softc *); 119 120 static void pccbb_pcmcia_write(struct pcic_handle *, int, u_int8_t); 121 static u_int8_t pccbb_pcmcia_read(struct pcic_handle *, int); 122 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 123 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 124 125 STATIC int cb_reset(struct pccbb_softc *); 126 STATIC int cb_detect_voltage(struct pccbb_softc *); 127 STATIC int cbbprint(void *, const char *); 128 129 static int cb_chipset(u_int32_t, int *); 130 STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *, 131 struct pcmciabus_attach_args *); 132 #if 0 133 STATIC void pccbb_pcmcia_attach_card(struct pcic_handle *); 134 STATIC void pccbb_pcmcia_detach_card(struct pcic_handle *, int); 135 STATIC void pccbb_pcmcia_deactivate_card(struct pcic_handle *); 136 #endif 137 138 STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int); 139 STATIC int pccbb_power(struct pccbb_softc *sc, int); 140 STATIC int pccbb_power_ct(cardbus_chipset_tag_t, int); 141 STATIC int pccbb_cardenable(struct pccbb_softc * sc, int function); 142 #if !rbus 143 static int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 144 static int pccbb_io_close(cardbus_chipset_tag_t, int); 145 static int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 146 static int pccbb_mem_close(cardbus_chipset_tag_t, int); 147 #endif /* !rbus */ 148 static void *pccbb_intr_establish(struct pccbb_softc *, int irq, 149 int level, int (*ih) (void *), void *sc); 150 static void pccbb_intr_disestablish(struct pccbb_softc *, void *ih); 151 152 static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t, int irq, 153 int level, int (*ih) (void *), void *sc); 154 static void pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih); 155 156 static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t, int, int); 157 static void pccbb_free_tag(cardbus_chipset_tag_t, cardbustag_t); 158 static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t, cardbustag_t, int); 159 static void pccbb_conf_write(cardbus_chipset_tag_t, cardbustag_t, int, 160 cardbusreg_t); 161 static void pccbb_chipinit(struct pccbb_softc *); 162 163 STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 164 struct pcmcia_mem_handle *); 165 STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t, 166 struct pcmcia_mem_handle *); 167 STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 168 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *); 169 STATIC void pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t, int); 170 STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 171 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 172 STATIC void pccbb_pcmcia_io_free(pcmcia_chipset_handle_t, 173 struct pcmcia_io_handle *); 174 STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 175 bus_size_t, struct pcmcia_io_handle *, int *); 176 STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t, int); 177 STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t, 178 struct pcmcia_function *, int, int (*)(void *), void *); 179 STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t, void *); 180 STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t); 181 STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t); 182 STATIC void pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t, int); 183 STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch); 184 185 static int pccbb_pcmcia_wait_ready(struct pcic_handle *); 186 static void pccbb_pcmcia_delay(struct pcic_handle *, int, const char *); 187 188 static void pccbb_pcmcia_do_io_map(struct pcic_handle *, int); 189 static void pccbb_pcmcia_do_mem_map(struct pcic_handle *, int); 190 191 /* bus-space allocation and deallocation functions */ 192 #if rbus 193 194 static int pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t, rbus_tag_t, 195 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 196 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp); 197 static int pccbb_rbus_cb_space_free(cardbus_chipset_tag_t, rbus_tag_t, 198 bus_space_handle_t, bus_size_t); 199 200 #endif /* rbus */ 201 202 #if rbus 203 204 static int pccbb_open_win(struct pccbb_softc *, bus_space_tag_t, 205 bus_addr_t, bus_size_t, bus_space_handle_t, int flags); 206 static int pccbb_close_win(struct pccbb_softc *, bus_space_tag_t, 207 bus_space_handle_t, bus_size_t); 208 static int pccbb_winlist_insert(struct pccbb_win_chain_head *, bus_addr_t, 209 bus_size_t, bus_space_handle_t, int); 210 static int pccbb_winlist_delete(struct pccbb_win_chain_head *, 211 bus_space_handle_t, bus_size_t); 212 static void pccbb_winset(bus_addr_t align, struct pccbb_softc *, 213 bus_space_tag_t); 214 void pccbb_winlist_show(struct pccbb_win_chain *); 215 216 #endif /* rbus */ 217 218 /* for config_defer */ 219 static void pccbb_pci_callback(device_t); 220 221 static bool pccbb_suspend(device_t); 222 static bool pccbb_resume(device_t); 223 224 #if defined SHOW_REGS 225 static void cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, 226 bus_space_tag_t memt, bus_space_handle_t memh); 227 #endif 228 229 CFATTACH_DECL(cbb_pci, sizeof(struct pccbb_softc), 230 pcicbbmatch, pccbbattach, pccbbdetach, NULL); 231 232 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 233 pccbb_pcmcia_mem_alloc, 234 pccbb_pcmcia_mem_free, 235 pccbb_pcmcia_mem_map, 236 pccbb_pcmcia_mem_unmap, 237 pccbb_pcmcia_io_alloc, 238 pccbb_pcmcia_io_free, 239 pccbb_pcmcia_io_map, 240 pccbb_pcmcia_io_unmap, 241 pccbb_pcmcia_intr_establish, 242 pccbb_pcmcia_intr_disestablish, 243 pccbb_pcmcia_socket_enable, 244 pccbb_pcmcia_socket_disable, 245 pccbb_pcmcia_socket_settype, 246 pccbb_pcmcia_card_detect 247 }; 248 249 #if rbus 250 static struct cardbus_functions pccbb_funcs = { 251 pccbb_rbus_cb_space_alloc, 252 pccbb_rbus_cb_space_free, 253 pccbb_cb_intr_establish, 254 pccbb_cb_intr_disestablish, 255 pccbb_ctrl, 256 pccbb_power_ct, 257 pccbb_make_tag, 258 pccbb_free_tag, 259 pccbb_conf_read, 260 pccbb_conf_write, 261 }; 262 #else 263 static struct cardbus_functions pccbb_funcs = { 264 pccbb_ctrl, 265 pccbb_power_ct, 266 pccbb_mem_open, 267 pccbb_mem_close, 268 pccbb_io_open, 269 pccbb_io_close, 270 pccbb_cb_intr_establish, 271 pccbb_cb_intr_disestablish, 272 pccbb_make_tag, 273 pccbb_conf_read, 274 pccbb_conf_write, 275 }; 276 #endif 277 278 int 279 pcicbbmatch(device_t parent, struct cfdata *match, void *aux) 280 { 281 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 282 283 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 284 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 285 PCI_INTERFACE(pa->pa_class) == 0) { 286 return 1; 287 } 288 289 return 0; 290 } 291 292 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 293 | ((prod) << PCI_PRODUCT_SHIFT)) 294 295 const struct yenta_chipinfo { 296 pcireg_t yc_id; /* vendor tag | product tag */ 297 int yc_chiptype; 298 int yc_flags; 299 } yc_chipsets[] = { 300 /* Texas Instruments chips */ 301 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 302 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 303 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 304 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 305 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI125X, 306 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 307 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 308 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 309 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 310 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 311 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 312 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 313 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI125X, 314 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 315 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI125X, 316 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 317 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 318 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 319 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 320 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 321 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI1420, 322 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 323 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI125X, 324 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 325 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 326 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 327 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1520), CB_TI12XX, 328 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 329 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4410YENTA), CB_TI12XX, 330 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 331 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4520YENTA), CB_TI12XX, 332 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 333 334 /* Ricoh chips */ 335 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 336 PCCBB_PCMCIA_MEM_32}, 337 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 338 PCCBB_PCMCIA_MEM_32}, 339 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 340 PCCBB_PCMCIA_MEM_32}, 341 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 342 PCCBB_PCMCIA_MEM_32}, 343 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 344 PCCBB_PCMCIA_MEM_32}, 345 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 346 PCCBB_PCMCIA_MEM_32}, 347 348 /* Toshiba products */ 349 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 350 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 351 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 352 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 353 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 354 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 355 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 356 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 357 358 /* Cirrus Logic products */ 359 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 360 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 361 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 362 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 363 364 /* sentinel, or Generic chip */ 365 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 366 }; 367 368 static int 369 cb_chipset(u_int32_t pci_id, int *flagp) 370 { 371 const struct yenta_chipinfo *yc; 372 373 /* Loop over except the last default entry. */ 374 for (yc = yc_chipsets; yc < yc_chipsets + 375 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 376 if (pci_id == yc->yc_id) 377 break; 378 379 if (flagp != NULL) 380 *flagp = yc->yc_flags; 381 382 return (yc->yc_chiptype); 383 } 384 385 void 386 pccbbattach(device_t parent, device_t self, void *aux) 387 { 388 struct pccbb_softc *sc = device_private(self); 389 struct pci_attach_args *pa = aux; 390 pci_chipset_tag_t pc = pa->pa_pc; 391 pcireg_t busreg, reg, sock_base; 392 bus_addr_t sockbase; 393 char devinfo[256]; 394 int flags; 395 396 #ifdef __HAVE_PCCBB_ATTACH_HOOK 397 pccbb_attach_hook(parent, self, pa); 398 #endif 399 400 callout_init(&sc->sc_insert_ch, 0); 401 callout_setfunc(&sc->sc_insert_ch, pci113x_insert, sc); 402 403 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 404 405 aprint_naive("\n"); 406 407 pci_devinfo(pa->pa_id, 0, 0, devinfo, sizeof(devinfo)); 408 aprint_normal(": %s (rev. 0x%02x)", devinfo, 409 PCI_REVISION(pa->pa_class)); 410 DPRINTF((" (chipflags %x)", flags)); 411 aprint_normal("\n"); 412 413 TAILQ_INIT(&sc->sc_memwindow); 414 TAILQ_INIT(&sc->sc_iowindow); 415 416 #if rbus 417 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 418 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 419 420 #if 0 421 printf("pa->pa_memt: %08x vs rbus_mem->rb_bt: %08x\n", 422 pa->pa_memt, sc->sc_rbus_memt->rb_bt); 423 #endif 424 #endif /* rbus */ 425 426 sc->sc_flags &= ~CBB_MEMHMAPPED; 427 428 /* 429 * MAP socket registers and ExCA registers on memory-space 430 * When no valid address is set on socket base registers (on pci 431 * config space), get it not polite way. 432 */ 433 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 434 435 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 436 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 437 /* The address must be valid. */ 438 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 439 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, &sc->sc_base_size)) { 440 aprint_error("%s: can't map socket base address 0x%lx\n", 441 sc->sc_dev.dv_xname, (unsigned long)sock_base); 442 /* 443 * I think it's funny: socket base registers must be 444 * mapped on memory space, but ... 445 */ 446 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 447 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 448 &sc->sc_base_size)) { 449 aprint_error("%s: can't map socket base address" 450 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 451 (unsigned long)sockbase); 452 /* give up... allocate reg space via rbus. */ 453 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 454 } else 455 sc->sc_flags |= CBB_MEMHMAPPED; 456 } else { 457 DPRINTF(("%s: socket base address 0x%lx\n", 458 sc->sc_dev.dv_xname, (unsigned long)sockbase)); 459 sc->sc_flags |= CBB_MEMHMAPPED; 460 } 461 } 462 463 sc->sc_mem_start = 0; /* XXX */ 464 sc->sc_mem_end = 0xffffffff; /* XXX */ 465 466 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 467 468 /* pccbb_machdep.c end */ 469 470 #if defined CBB_DEBUG 471 { 472 static const char *intrname[] = { "NON", "A", "B", "C", "D" }; 473 printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname, 474 intrname[pa->pa_intrpin], pa->pa_intrline); 475 } 476 #endif 477 478 /* setup softc */ 479 sc->sc_pc = pc; 480 sc->sc_iot = pa->pa_iot; 481 sc->sc_memt = pa->pa_memt; 482 sc->sc_dmat = pa->pa_dmat; 483 sc->sc_tag = pa->pa_tag; 484 sc->sc_function = pa->pa_function; 485 486 memcpy(&sc->sc_pa, pa, sizeof(*pa)); 487 488 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 489 490 /* Disable legacy register mapping. */ 491 switch (sc->sc_chipset) { 492 case CB_RX5C46X: /* fallthrough */ 493 #if 0 494 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 495 case CB_RX5C47X: 496 #endif 497 /* 498 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 499 * cannot be disabled by substituting 0 into PCI_LEGACY 500 * register. Ricoh CardBus bridges have special bits on Bridge 501 * control reg (addr 0x3e on PCI config space). 502 */ 503 reg = pci_conf_read(pc, pa->pa_tag, PCI_BRIDGE_CONTROL_REG); 504 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 505 pci_conf_write(pc, pa->pa_tag, PCI_BRIDGE_CONTROL_REG, reg); 506 break; 507 508 default: 509 /* XXX I don't know proper way to kill legacy I/O. */ 510 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 511 break; 512 } 513 514 if (!pmf_device_register(self, pccbb_suspend, pccbb_resume)) 515 aprint_error_dev(self, "couldn't establish power handler\n"); 516 517 config_defer(self, pccbb_pci_callback); 518 } 519 520 int 521 pccbbdetach(device_t self, int flags) 522 { 523 struct pccbb_softc *sc = device_private(self); 524 pci_chipset_tag_t pc = sc->sc_pa.pa_pc; 525 bus_space_tag_t bmt = sc->sc_base_memt; 526 bus_space_handle_t bmh = sc->sc_base_memh; 527 uint32_t sockmask; 528 int rc; 529 530 if ((rc = config_detach_children(self, flags)) != 0) 531 return rc; 532 533 if (!LIST_EMPTY(&sc->sc_pil)) { 534 panic("%s: interrupt handlers still registered", 535 device_xname(&sc->sc_dev)); 536 return EBUSY; 537 } 538 539 if (sc->sc_ih != NULL) { 540 pci_intr_disestablish(pc, sc->sc_ih); 541 sc->sc_ih = NULL; 542 } 543 544 /* CSC Interrupt: turn off card detect and power cycle interrupts */ 545 sockmask = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 546 sockmask &= ~(CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER); 547 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, sockmask); 548 /* reset interrupt */ 549 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 550 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 551 552 switch (sc->sc_flags & (CBB_MEMHMAPPED|CBB_SPECMAPPED)) { 553 case CBB_MEMHMAPPED: 554 bus_space_unmap(bmt, bmh, sc->sc_base_size); 555 break; 556 case CBB_MEMHMAPPED|CBB_SPECMAPPED: 557 #if rbus 558 { 559 pcireg_t sockbase; 560 561 sockbase = pci_conf_read(pc, sc->sc_tag, PCI_SOCKBASE); 562 rbus_space_free(sc->sc_rbus_memt, bmh, 0x1000, 563 NULL); 564 } 565 #else 566 bus_space_free(bmt, bmh, 0x1000); 567 #endif 568 } 569 sc->sc_flags &= ~(CBB_MEMHMAPPED|CBB_SPECMAPPED); 570 571 if (!TAILQ_EMPTY(&sc->sc_iowindow)) 572 aprint_error_dev(self, "i/o windows not empty"); 573 if (!TAILQ_EMPTY(&sc->sc_memwindow)) 574 aprint_error_dev(self, "memory windows not empty"); 575 576 callout_stop(&sc->sc_insert_ch); 577 callout_destroy(&sc->sc_insert_ch); 578 return 0; 579 } 580 581 /* 582 * static void pccbb_pci_callback(device_t self) 583 * 584 * The actual attach routine: get memory space for YENTA register 585 * space, setup YENTA register and route interrupt. 586 * 587 * This function should be deferred because this device may obtain 588 * memory space dynamically. This function must avoid obtaining 589 * memory area which has already kept for another device. 590 */ 591 static void 592 pccbb_pci_callback(device_t self) 593 { 594 struct pccbb_softc *sc = device_private(self); 595 pci_chipset_tag_t pc = sc->sc_pc; 596 pci_intr_handle_t ih; 597 const char *intrstr = NULL; 598 bus_addr_t sockbase; 599 struct cbslot_attach_args cba; 600 struct pcmciabus_attach_args paa; 601 struct cardslot_attach_args caa; 602 struct cardslot_softc *csc; 603 604 if (!(sc->sc_flags & CBB_MEMHMAPPED)) { 605 /* The socket registers aren't mapped correctly. */ 606 #if rbus 607 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 608 (sc->sc_chipset == CB_RX5C47X 609 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 610 0, &sockbase, &sc->sc_base_memh)) { 611 return; 612 } 613 sc->sc_base_memt = sc->sc_memt; 614 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 615 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 616 sc->sc_dev.dv_xname, (unsigned long)sockbase, 617 (unsigned long)pci_conf_read(pc, sc->sc_tag, 618 PCI_SOCKBASE))); 619 #else 620 sc->sc_base_memt = sc->sc_memt; 621 #if !defined CBB_PCI_BASE 622 #define CBB_PCI_BASE 0x20000000 623 #endif 624 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 625 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 626 /* cannot allocate memory space */ 627 return; 628 } 629 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 630 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 631 sc->sc_dev.dv_xname, (unsigned long)sock_base, 632 (unsigned long)pci_conf_read(pc, 633 sc->sc_tag, PCI_SOCKBASE))); 634 #endif 635 sc->sc_flags |= CBB_MEMHMAPPED; 636 } 637 638 /* bus bridge initialization */ 639 pccbb_chipinit(sc); 640 641 /* clear data structure for child device interrupt handlers */ 642 LIST_INIT(&sc->sc_pil); 643 sc->sc_pil_intr_enable = 1; 644 645 /* Map and establish the interrupt. */ 646 if (pci_intr_map(&sc->sc_pa, &ih)) { 647 aprint_error("%s: couldn't map interrupt\n", 648 sc->sc_dev.dv_xname); 649 return; 650 } 651 intrstr = pci_intr_string(pc, ih); 652 653 /* 654 * XXX pccbbintr should be called under the priority lower 655 * than any other hard interupts. 656 */ 657 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 658 659 if (sc->sc_ih == NULL) { 660 aprint_error("%s: couldn't establish interrupt", 661 sc->sc_dev.dv_xname); 662 if (intrstr != NULL) { 663 aprint_normal(" at %s", intrstr); 664 } 665 aprint_normal("\n"); 666 return; 667 } 668 669 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 670 671 { 672 u_int32_t sockstat; 673 674 sockstat = bus_space_read_4(sc->sc_base_memt, 675 sc->sc_base_memh, CB_SOCKET_STAT); 676 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 677 sc->sc_flags |= CBB_CARDEXIST; 678 } 679 } 680 681 /* 682 * attach cardbus 683 */ 684 { 685 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 686 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 687 688 /* initialize cbslot_attach */ 689 cba.cba_busname = "cardbus"; 690 cba.cba_iot = sc->sc_iot; 691 cba.cba_memt = sc->sc_memt; 692 cba.cba_dmat = sc->sc_dmat; 693 cba.cba_bus = (busreg >> 8) & 0x0ff; 694 cba.cba_cc = (void *)sc; 695 cba.cba_cf = &pccbb_funcs; 696 cba.cba_intrline = sc->sc_pa.pa_intrline; 697 698 #if rbus 699 cba.cba_rbus_iot = sc->sc_rbus_iot; 700 cba.cba_rbus_memt = sc->sc_rbus_memt; 701 #endif 702 703 cba.cba_cacheline = PCI_CACHELINE(bhlc); 704 cba.cba_max_lattimer = PCI_LATTIMER(bhlc); 705 706 if (bootverbose) { 707 printf("%s: cacheline 0x%x lattimer 0x%x\n", 708 sc->sc_dev.dv_xname, cba.cba_cacheline, 709 cba.cba_max_lattimer); 710 printf("%s: bhlc 0x%x\n", 711 device_xname(&sc->sc_dev), bhlc); 712 } 713 #if defined SHOW_REGS 714 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 715 sc->sc_base_memh); 716 #endif 717 } 718 719 pccbb_pcmcia_attach_setup(sc, &paa); 720 caa.caa_cb_attach = NULL; 721 if (cba.cba_bus == 0) 722 printf("%s: secondary bus number uninitialized; try PCI_BUS_FIXUP\n", sc->sc_dev.dv_xname); 723 else 724 caa.caa_cb_attach = &cba; 725 caa.caa_16_attach = &paa; 726 caa.caa_ph = &sc->sc_pcmcia_h; 727 728 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 729 DPRINTF(("%s: found cardslot\n", __func__)); 730 sc->sc_csc = csc; 731 } 732 733 return; 734 } 735 736 737 738 739 740 /* 741 * static void pccbb_chipinit(struct pccbb_softc *sc) 742 * 743 * This function initialize YENTA chip registers listed below: 744 * 1) PCI command reg, 745 * 2) PCI and CardBus latency timer, 746 * 3) route PCI interrupt, 747 * 4) close all memory and io windows. 748 * 5) turn off bus power. 749 * 6) card detect and power cycle interrupts on. 750 * 7) clear interrupt 751 */ 752 static void 753 pccbb_chipinit(struct pccbb_softc *sc) 754 { 755 pci_chipset_tag_t pc = sc->sc_pc; 756 pcitag_t tag = sc->sc_tag; 757 bus_space_tag_t bmt = sc->sc_base_memt; 758 bus_space_handle_t bmh = sc->sc_base_memh; 759 pcireg_t bcr, bhlc, cbctl, csr, lscp, mfunc, mrburst, slotctl, sockctl, 760 sockmask, sysctrl; 761 762 /* 763 * Set PCI command reg. 764 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 765 */ 766 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 767 /* I believe it is harmless. */ 768 csr |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 769 PCI_COMMAND_MASTER_ENABLE); 770 csr |= (PCI_COMMAND_PARITY_ENABLE|PCI_COMMAND_SERR_ENABLE); 771 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 772 773 /* 774 * Set CardBus latency timer. 775 */ 776 lscp = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 777 if (PCI_CB_LATENCY(lscp) < 0x20) { 778 lscp &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 779 lscp |= (0x20 << PCI_CB_LATENCY_SHIFT); 780 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, lscp); 781 } 782 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 783 PCI_CB_LATENCY(lscp), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 784 785 /* 786 * Set PCI latency timer. 787 */ 788 bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG); 789 if (PCI_LATTIMER(bhlc) < 0x10) { 790 bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 791 bhlc |= (0x10 << PCI_LATTIMER_SHIFT); 792 pci_conf_write(pc, tag, PCI_BHLC_REG, bhlc); 793 } 794 DPRINTF(("PCI latency timer 0x%x (%x)\n", 795 PCI_LATTIMER(bhlc), pci_conf_read(pc, tag, PCI_BHLC_REG))); 796 797 798 /* Route functional interrupts to PCI. */ 799 bcr = pci_conf_read(pc, tag, PCI_BRIDGE_CONTROL_REG); 800 bcr |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 801 bcr |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 802 /* assert reset */ 803 bcr |= PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT; 804 /* Set master abort mode to 1, forward SERR# from secondary 805 * to primary, and detect parity errors on secondary. 806 */ 807 bcr |= PCI_BRIDGE_CONTROL_MABRT << PCI_BRIDGE_CONTROL_SHIFT; 808 bcr |= PCI_BRIDGE_CONTROL_SERR << PCI_BRIDGE_CONTROL_SHIFT; 809 bcr |= PCI_BRIDGE_CONTROL_PERE << PCI_BRIDGE_CONTROL_SHIFT; 810 pci_conf_write(pc, tag, PCI_BRIDGE_CONTROL_REG, bcr); 811 812 switch (sc->sc_chipset) { 813 case CB_TI113X: 814 cbctl = pci_conf_read(pc, tag, PCI_CBCTRL); 815 /* This bit is shared, but may read as 0 on some chips, so set 816 it explicitly on both functions. */ 817 cbctl |= PCI113X_CBCTRL_PCI_IRQ_ENA; 818 /* CSC intr enable */ 819 cbctl |= PCI113X_CBCTRL_PCI_CSC; 820 /* functional intr prohibit | prohibit ISA routing */ 821 cbctl &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 822 pci_conf_write(pc, tag, PCI_CBCTRL, cbctl); 823 break; 824 825 case CB_TI1420: 826 sysctrl = pci_conf_read(pc, tag, PCI_SYSCTRL); 827 mrburst = pccbb_burstup 828 ? PCI1420_SYSCTRL_MRBURST : PCI1420_SYSCTRL_MRBURSTDN; 829 if ((sysctrl & PCI1420_SYSCTRL_MRBURST) == mrburst) { 830 printf("%s: %swrite bursts enabled\n", 831 device_xname(&sc->sc_dev), 832 pccbb_burstup ? "read/" : ""); 833 } else if (pccbb_burstup) { 834 printf("%s: enabling read/write bursts\n", 835 device_xname(&sc->sc_dev)); 836 sysctrl |= PCI1420_SYSCTRL_MRBURST; 837 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 838 } else { 839 printf("%s: disabling read bursts, " 840 "enabling write bursts\n", 841 device_xname(&sc->sc_dev)); 842 sysctrl |= PCI1420_SYSCTRL_MRBURSTDN; 843 sysctrl &= ~PCI1420_SYSCTRL_MRBURSTUP; 844 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 845 } 846 /*FALLTHROUGH*/ 847 case CB_TI12XX: 848 /* 849 * Some TI 12xx (and [14][45]xx) based pci cards 850 * sometimes have issues with the MFUNC register not 851 * being initialized due to a bad EEPROM on board. 852 * Laptops that this matters on have this register 853 * properly initialized. 854 * 855 * The TI125X parts have a different register. 856 */ 857 mfunc = pci_conf_read(pc, tag, PCI12XX_MFUNC); 858 if (mfunc == 0) { 859 mfunc &= ~PCI12XX_MFUNC_PIN0; 860 mfunc |= PCI12XX_MFUNC_PIN0_INTA; 861 if ((pci_conf_read(pc, tag, PCI_SYSCTRL) & 862 PCI12XX_SYSCTRL_INTRTIE) == 0) { 863 mfunc &= ~PCI12XX_MFUNC_PIN1; 864 mfunc |= PCI12XX_MFUNC_PIN1_INTB; 865 } 866 pci_conf_write(pc, tag, PCI12XX_MFUNC, mfunc); 867 } 868 /* fallthrough */ 869 870 case CB_TI125X: 871 /* 872 * Disable zoom video. Some machines initialize this 873 * improperly and experience has shown that this helps 874 * prevent strange behavior. 875 */ 876 pci_conf_write(pc, tag, PCI12XX_MMCTRL, 0); 877 878 sysctrl = pci_conf_read(pc, tag, PCI_SYSCTRL); 879 sysctrl |= PCI12XX_SYSCTRL_VCCPROT; 880 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 881 cbctl = pci_conf_read(pc, tag, PCI_CBCTRL); 882 cbctl |= PCI12XX_CBCTRL_CSC; 883 pci_conf_write(pc, tag, PCI_CBCTRL, cbctl); 884 break; 885 886 case CB_TOPIC95B: 887 sockctl = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 888 sockctl |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 889 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, sockctl); 890 slotctl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 891 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 892 sc->sc_dev.dv_xname, slotctl)); 893 slotctl |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 894 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 895 slotctl &= ~TOPIC_SLOT_CTRL_SWDETECT; 896 DPRINTF(("0x%x\n", slotctl)); 897 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slotctl); 898 break; 899 900 case CB_TOPIC97: 901 slotctl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 902 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 903 sc->sc_dev.dv_xname, slotctl)); 904 slotctl |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 905 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 906 slotctl &= ~TOPIC_SLOT_CTRL_SWDETECT; 907 slotctl |= TOPIC97_SLOT_CTRL_PCIINT; 908 slotctl &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 909 DPRINTF(("0x%x\n", slotctl)); 910 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slotctl); 911 /* make sure to assert LV card support bits */ 912 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 913 0x800 + 0x3e, 914 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 915 0x800 + 0x3e) | 0x03); 916 break; 917 } 918 919 /* Close all memory and I/O windows. */ 920 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 921 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 922 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 923 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 924 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 925 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 926 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 927 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 928 929 /* reset 16-bit pcmcia bus */ 930 bus_space_write_1(bmt, bmh, 0x800 + PCIC_INTR, 931 bus_space_read_1(bmt, bmh, 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 932 933 /* turn off power */ 934 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 935 936 /* CSC Interrupt: Card detect and power cycle interrupts on */ 937 sockmask = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 938 sockmask |= CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; 939 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, sockmask); 940 /* reset interrupt */ 941 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 942 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 943 } 944 945 946 947 948 /* 949 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 950 * struct pcmciabus_attach_args *paa) 951 * 952 * This function attaches 16-bit PCcard bus. 953 */ 954 STATIC void 955 pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 956 struct pcmciabus_attach_args *paa) 957 { 958 struct pcic_handle *ph = &sc->sc_pcmcia_h; 959 #if rbus 960 rbus_tag_t rb; 961 #endif 962 963 /* initialize pcmcia part in pccbb_softc */ 964 ph->ph_parent = &sc->sc_dev; 965 ph->sock = sc->sc_function; 966 ph->flags = 0; 967 ph->shutdown = 0; 968 ph->ih_irq = sc->sc_pa.pa_intrline; 969 ph->ph_bus_t = sc->sc_base_memt; 970 ph->ph_bus_h = sc->sc_base_memh; 971 ph->ph_read = pccbb_pcmcia_read; 972 ph->ph_write = pccbb_pcmcia_write; 973 sc->sc_pct = &pccbb_pcmcia_funcs; 974 975 /* 976 * We need to do a few things here: 977 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 978 * setting the IRQ numbers to 0. 979 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 980 * routing of CSC interrupts (e.g. card removal) to PCI while in 981 * PCMCIA mode. We just leave this set all the time. 982 * 3) Enable card insertion/removal interrupts in case the chip also 983 * needs that while in PCMCIA mode. 984 * 4) Clear any pending CSC interrupt. 985 */ 986 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE); 987 if (sc->sc_chipset == CB_TI113X) { 988 Pcic_write(ph, PCIC_CSC_INTR, 0); 989 } else { 990 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 991 Pcic_read(ph, PCIC_CSC); 992 } 993 994 /* initialize pcmcia bus attachment */ 995 paa->paa_busname = "pcmcia"; 996 paa->pct = sc->sc_pct; 997 paa->pch = ph; 998 paa->iobase = 0; /* I don't use them */ 999 paa->iosize = 0; 1000 #if rbus 1001 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 1002 paa->iobase = rb->rb_start + rb->rb_offset; 1003 paa->iosize = rb->rb_end - rb->rb_start; 1004 #endif 1005 1006 return; 1007 } 1008 1009 #if 0 1010 STATIC void 1011 pccbb_pcmcia_attach_card(struct pcic_handle *ph) 1012 { 1013 if (ph->flags & PCIC_FLAG_CARDP) { 1014 panic("pccbb_pcmcia_attach_card: already attached"); 1015 } 1016 1017 /* call the MI attach function */ 1018 pcmcia_card_attach(ph->pcmcia); 1019 1020 ph->flags |= PCIC_FLAG_CARDP; 1021 } 1022 1023 STATIC void 1024 pccbb_pcmcia_detach_card(struct pcic_handle *ph, int flags) 1025 { 1026 if (!(ph->flags & PCIC_FLAG_CARDP)) { 1027 panic("pccbb_pcmcia_detach_card: already detached"); 1028 } 1029 1030 ph->flags &= ~PCIC_FLAG_CARDP; 1031 1032 /* call the MI detach function */ 1033 pcmcia_card_detach(ph->pcmcia, flags); 1034 } 1035 #endif 1036 1037 /* 1038 * int pccbbintr(arg) 1039 * void *arg; 1040 * This routine handles the interrupt from Yenta PCI-CardBus bridge 1041 * itself. 1042 */ 1043 int 1044 pccbbintr(void *arg) 1045 { 1046 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1047 u_int32_t sockevent, sockstate; 1048 bus_space_tag_t memt = sc->sc_base_memt; 1049 bus_space_handle_t memh = sc->sc_base_memh; 1050 struct pcic_handle *ph = &sc->sc_pcmcia_h; 1051 1052 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 1053 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 1054 Pcic_read(ph, PCIC_CSC); 1055 1056 if (sockevent != 0) { 1057 aprint_debug("%s: enter sockevent %" PRIx32 "\n", __func__, 1058 sockevent); 1059 } 1060 1061 /* Sometimes a change of CSTSCHG# accompanies the first 1062 * interrupt from an Atheros WLAN. That generates a 1063 * CB_SOCKET_EVENT_CSTS event on the bridge. The event 1064 * isn't interesting to pccbb(4), so we used to ignore the 1065 * interrupt. Now, let the child devices try to handle 1066 * the interrupt, instead. The Atheros NIC produces 1067 * interrupts more reliably, now: used to be that it would 1068 * only interrupt if the driver avoided powering down the 1069 * NIC's cardslot, and then the NIC would only work after 1070 * it was reset a second time. 1071 */ 1072 if (sockevent == 0 || 1073 (sockevent & ~(CB_SOCKET_EVENT_POWER|CB_SOCKET_EVENT_CD)) != 0) { 1074 /* This intr is not for me: it may be for my child devices. */ 1075 if (sc->sc_pil_intr_enable) { 1076 return pccbbintr_function(sc); 1077 } else { 1078 return 0; 1079 } 1080 } 1081 1082 if (sockevent & CB_SOCKET_EVENT_CD) { 1083 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1084 if (0x00 != (sockstate & CB_SOCKET_STAT_CD)) { 1085 /* A card should be removed. */ 1086 if (sc->sc_flags & CBB_CARDEXIST) { 1087 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 1088 sockevent)); 1089 DPRINTF((" card removed, 0x%08x\n", sockstate)); 1090 sc->sc_flags &= ~CBB_CARDEXIST; 1091 if (sc->sc_csc->sc_status & 1092 CARDSLOT_STATUS_CARD_16) { 1093 #if 0 1094 struct pcic_handle *ph = 1095 &sc->sc_pcmcia_h; 1096 1097 pcmcia_card_deactivate(ph->pcmcia); 1098 pccbb_pcmcia_socket_disable(ph); 1099 pccbb_pcmcia_detach_card(ph, 1100 DETACH_FORCE); 1101 #endif 1102 cardslot_event_throw(sc->sc_csc, 1103 CARDSLOT_EVENT_REMOVAL_16); 1104 } else if (sc->sc_csc->sc_status & 1105 CARDSLOT_STATUS_CARD_CB) { 1106 /* Cardbus intr removed */ 1107 cardslot_event_throw(sc->sc_csc, 1108 CARDSLOT_EVENT_REMOVAL_CB); 1109 } 1110 } else if (sc->sc_flags & CBB_INSERTING) { 1111 sc->sc_flags &= ~CBB_INSERTING; 1112 callout_stop(&sc->sc_insert_ch); 1113 } 1114 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 1115 /* 1116 * The pccbbintr may called from powerdown hook when 1117 * the system resumed, to detect the card 1118 * insertion/removal during suspension. 1119 */ 1120 (sc->sc_flags & CBB_CARDEXIST) == 0) { 1121 if (sc->sc_flags & CBB_INSERTING) { 1122 callout_stop(&sc->sc_insert_ch); 1123 } 1124 callout_schedule(&sc->sc_insert_ch, hz / 5); 1125 sc->sc_flags |= CBB_INSERTING; 1126 } 1127 } 1128 1129 /* XXX sockevent == 9 does occur in the wild. handle it. */ 1130 if (sockevent & CB_SOCKET_EVENT_POWER) { 1131 DPRINTF(("Powercycling because of socket event\n")); 1132 /* XXX: Does not happen when attaching a 16-bit card */ 1133 sc->sc_pwrcycle++; 1134 wakeup(&sc->sc_pwrcycle); 1135 } 1136 1137 return (1); 1138 } 1139 1140 /* 1141 * static int pccbbintr_function(struct pccbb_softc *sc) 1142 * 1143 * This function calls each interrupt handler registered at the 1144 * bridge. The interrupt handlers are called in registered order. 1145 */ 1146 static int 1147 pccbbintr_function(struct pccbb_softc *sc) 1148 { 1149 int retval = 0, val; 1150 struct pccbb_intrhand_list *pil; 1151 int s; 1152 1153 LIST_FOREACH(pil, &sc->sc_pil, pil_next) { 1154 s = splraiseipl(pil->pil_icookie); 1155 val = (*pil->pil_func)(pil->pil_arg); 1156 splx(s); 1157 1158 retval = retval == 1 ? 1 : 1159 retval == 0 ? val : val != 0 ? val : retval; 1160 } 1161 1162 return retval; 1163 } 1164 1165 static void 1166 pci113x_insert(void *arg) 1167 { 1168 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1169 u_int32_t sockevent, sockstate; 1170 1171 if (!(sc->sc_flags & CBB_INSERTING)) { 1172 /* We add a card only under inserting state. */ 1173 return; 1174 } 1175 sc->sc_flags &= ~CBB_INSERTING; 1176 1177 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1178 CB_SOCKET_EVENT); 1179 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1180 CB_SOCKET_STAT); 1181 1182 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1183 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1184 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1185 sc->sc_flags |= CBB_CARDEXIST; 1186 /* call pccard interrupt handler here */ 1187 if (sockstate & CB_SOCKET_STAT_16BIT) { 1188 /* 16-bit card found */ 1189 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1190 cardslot_event_throw(sc->sc_csc, 1191 CARDSLOT_EVENT_INSERTION_16); 1192 } else if (sockstate & CB_SOCKET_STAT_CB) { 1193 /* cardbus card found */ 1194 /* cardbus_attach_card(sc->sc_csc); */ 1195 cardslot_event_throw(sc->sc_csc, 1196 CARDSLOT_EVENT_INSERTION_CB); 1197 } else { 1198 /* who are you? */ 1199 } 1200 } else { 1201 callout_schedule(&sc->sc_insert_ch, hz / 10); 1202 } 1203 } 1204 1205 #define PCCBB_PCMCIA_OFFSET 0x800 1206 static u_int8_t 1207 pccbb_pcmcia_read(struct pcic_handle *ph, int reg) 1208 { 1209 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1210 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1211 1212 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1213 PCCBB_PCMCIA_OFFSET + reg); 1214 } 1215 1216 static void 1217 pccbb_pcmcia_write(struct pcic_handle *ph, int reg, u_int8_t val) 1218 { 1219 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1220 val); 1221 1222 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1223 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1224 } 1225 1226 /* 1227 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1228 */ 1229 STATIC int 1230 pccbb_ctrl(cardbus_chipset_tag_t ct, int command) 1231 { 1232 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1233 1234 switch (command) { 1235 case CARDBUS_CD: 1236 if (2 == pccbb_detect_card(sc)) { 1237 int retval = 0; 1238 int status = cb_detect_voltage(sc); 1239 if (PCCARD_VCC_5V & status) { 1240 retval |= CARDBUS_5V_CARD; 1241 } 1242 if (PCCARD_VCC_3V & status) { 1243 retval |= CARDBUS_3V_CARD; 1244 } 1245 if (PCCARD_VCC_XV & status) { 1246 retval |= CARDBUS_XV_CARD; 1247 } 1248 if (PCCARD_VCC_YV & status) { 1249 retval |= CARDBUS_YV_CARD; 1250 } 1251 return retval; 1252 } else { 1253 return 0; 1254 } 1255 case CARDBUS_RESET: 1256 return cb_reset(sc); 1257 case CARDBUS_IO_ENABLE: /* fallthrough */ 1258 case CARDBUS_IO_DISABLE: /* fallthrough */ 1259 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1260 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1261 case CARDBUS_BM_ENABLE: /* fallthrough */ 1262 case CARDBUS_BM_DISABLE: /* fallthrough */ 1263 /* XXX: I think we don't need to call this function below. */ 1264 return pccbb_cardenable(sc, command); 1265 } 1266 1267 return 0; 1268 } 1269 1270 STATIC int 1271 pccbb_power_ct(cardbus_chipset_tag_t ct, int command) 1272 { 1273 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1274 1275 return pccbb_power(sc, command); 1276 } 1277 1278 /* 1279 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1280 * This function returns true when it succeeds and returns false when 1281 * it fails. 1282 */ 1283 STATIC int 1284 pccbb_power(struct pccbb_softc *sc, int command) 1285 { 1286 u_int32_t status, osock_ctrl, sock_ctrl, reg_ctrl; 1287 bus_space_tag_t memt = sc->sc_base_memt; 1288 bus_space_handle_t memh = sc->sc_base_memh; 1289 int on = 0, pwrcycle, s, times; 1290 struct timeval before, after, diff; 1291 1292 DPRINTF(("pccbb_power: %s and %s [0x%x]\n", 1293 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1294 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1295 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1296 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1297 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1298 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1299 "UNKNOWN", 1300 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1301 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1302 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1303 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1304 "UNKNOWN", command)); 1305 1306 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1307 osock_ctrl = sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1308 1309 switch (command & CARDBUS_VCCMASK) { 1310 case CARDBUS_VCC_UC: 1311 break; 1312 case CARDBUS_VCC_5V: 1313 on++; 1314 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1315 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1316 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1317 } else { 1318 printf("%s: BAD voltage request: no 5 V card\n", 1319 sc->sc_dev.dv_xname); 1320 return 0; 1321 } 1322 break; 1323 case CARDBUS_VCC_3V: 1324 on++; 1325 if (CB_SOCKET_STAT_3VCARD & status) { 1326 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1327 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1328 } else { 1329 printf("%s: BAD voltage request: no 3.3 V card\n", 1330 sc->sc_dev.dv_xname); 1331 return 0; 1332 } 1333 break; 1334 case CARDBUS_VCC_0V: 1335 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1336 break; 1337 default: 1338 return 0; /* power NEVER changed */ 1339 } 1340 1341 switch (command & CARDBUS_VPPMASK) { 1342 case CARDBUS_VPP_UC: 1343 break; 1344 case CARDBUS_VPP_0V: 1345 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1346 break; 1347 case CARDBUS_VPP_VCC: 1348 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1349 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1350 break; 1351 case CARDBUS_VPP_12V: 1352 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1353 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1354 break; 1355 } 1356 1357 pwrcycle = sc->sc_pwrcycle; 1358 aprint_debug("%s: osock_ctrl %#" PRIx32 " sock_ctrl %#" PRIx32 "\n", 1359 device_xname(&sc->sc_dev), osock_ctrl, sock_ctrl); 1360 1361 microtime(&before); 1362 s = splbio(); 1363 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1364 1365 /* 1366 * Wait as long as 200ms for a power-cycle interrupt. If 1367 * interrupts are enabled, but the socket has already 1368 * changed to the desired status, keep waiting for the 1369 * interrupt. "Consuming" the interrupt in this way keeps 1370 * the interrupt from prematurely waking some subsequent 1371 * pccbb_power call. 1372 * 1373 * XXX Not every bridge interrupts on the ->OFF transition. 1374 * XXX That's ok, we will time-out after 200ms. 1375 * 1376 * XXX The power cycle event will never happen when attaching 1377 * XXX a 16-bit card. That's ok, we will time-out after 1378 * XXX 200ms. 1379 */ 1380 for (times = 5; --times >= 0; ) { 1381 if (cold) 1382 DELAY(40 * 1000); 1383 else { 1384 (void)tsleep(&sc->sc_pwrcycle, PWAIT, "pccpwr", 1385 hz / 25); 1386 if (pwrcycle == sc->sc_pwrcycle) 1387 continue; 1388 } 1389 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1390 if ((status & CB_SOCKET_STAT_PWRCYCLE) != 0 && on) 1391 break; 1392 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0 && !on) 1393 break; 1394 } 1395 splx(s); 1396 microtime(&after); 1397 timersub(&after, &before, &diff); 1398 aprint_debug("%s: wait took%s %ld.%06lds\n", sc->sc_dev.dv_xname, 1399 (on && times < 0) ? " too long" : "", diff.tv_sec, diff.tv_usec); 1400 1401 /* 1402 * Ok, wait a bit longer for things to settle. 1403 */ 1404 if (on && sc->sc_chipset == CB_TOPIC95B) 1405 delay_ms(100, sc); 1406 1407 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1408 1409 if (on && sc->sc_chipset != CB_TOPIC95B) { 1410 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0) 1411 printf("%s: power on failed?\n", sc->sc_dev.dv_xname); 1412 } 1413 1414 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1415 printf("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1416 sc->sc_dev.dv_xname, sock_ctrl, status); 1417 printf("%s: disabling socket\n", sc->sc_dev.dv_xname); 1418 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1419 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1420 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1421 status &= ~CB_SOCKET_STAT_BADVCC; 1422 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, status); 1423 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1424 CB_SOCKET_STAT)); 1425 return 0; 1426 } 1427 1428 if (sc->sc_chipset == CB_TOPIC97) { 1429 reg_ctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL); 1430 reg_ctrl &= ~TOPIC97_REG_CTRL_TESTMODE; 1431 if ((command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V) 1432 reg_ctrl &= ~TOPIC97_REG_CTRL_CLKRUN_ENA; 1433 else 1434 reg_ctrl |= TOPIC97_REG_CTRL_CLKRUN_ENA; 1435 pci_conf_write(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL, reg_ctrl); 1436 } 1437 1438 return 1; /* power changed correctly */ 1439 } 1440 1441 #if defined CB_PCMCIA_POLL 1442 struct cb_poll_str { 1443 void *arg; 1444 int (*func)(void *); 1445 int level; 1446 pccard_chipset_tag_t ct; 1447 int count; 1448 struct callout poll_ch; 1449 }; 1450 1451 static struct cb_poll_str cb_poll[10]; 1452 static int cb_poll_n = 0; 1453 1454 static void cb_pcmcia_poll(void *arg); 1455 1456 static void 1457 cb_pcmcia_poll(void *arg) 1458 { 1459 struct cb_poll_str *poll = arg; 1460 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1461 struct pccbb_softc *sc = psc->cpc_parent; 1462 int s; 1463 u_int32_t spsr; /* socket present-state reg */ 1464 1465 callout_reset(&poll->poll_ch, hz / 10, cb_pcmcia_poll, poll); 1466 switch (poll->level) { 1467 case IPL_NET: 1468 s = splnet(); 1469 break; 1470 case IPL_BIO: 1471 s = splbio(); 1472 break; 1473 case IPL_TTY: /* fallthrough */ 1474 default: 1475 s = spltty(); 1476 break; 1477 } 1478 1479 spsr = 1480 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1481 CB_SOCKET_STAT); 1482 1483 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1484 if (!(spsr & 0x40)) { /* CINT low */ 1485 #else 1486 if (1) { 1487 #endif 1488 if ((*poll->func) (poll->arg) == 1) { 1489 ++poll->count; 1490 printf("intr: reported from poller, 0x%x\n", spsr); 1491 #if defined LEVEL2 1492 } else { 1493 printf("intr: miss! 0x%x\n", spsr); 1494 #endif 1495 } 1496 } 1497 splx(s); 1498 } 1499 #endif /* defined CB_PCMCIA_POLL */ 1500 1501 /* 1502 * static int pccbb_detect_card(struct pccbb_softc *sc) 1503 * return value: 0 if no card exists. 1504 * 1 if 16-bit card exists. 1505 * 2 if cardbus card exists. 1506 */ 1507 static int 1508 pccbb_detect_card(struct pccbb_softc *sc) 1509 { 1510 bus_space_handle_t base_memh = sc->sc_base_memh; 1511 bus_space_tag_t base_memt = sc->sc_base_memt; 1512 u_int32_t sockstat = 1513 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1514 int retval = 0; 1515 1516 /* CD1 and CD2 asserted */ 1517 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1518 /* card must be present */ 1519 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1520 /* NOTACARD DEASSERTED */ 1521 if (CB_SOCKET_STAT_CB & sockstat) { 1522 /* CardBus mode */ 1523 retval = 2; 1524 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1525 /* 16-bit mode */ 1526 retval = 1; 1527 } 1528 } 1529 } 1530 return retval; 1531 } 1532 1533 /* 1534 * STATIC int cb_reset(struct pccbb_softc *sc) 1535 * This function resets CardBus card. 1536 */ 1537 STATIC int 1538 cb_reset(struct pccbb_softc *sc) 1539 { 1540 /* 1541 * Reset Assert at least 20 ms 1542 * Some machines request longer duration. 1543 */ 1544 int reset_duration = 1545 (sc->sc_chipset == CB_RX5C47X ? 400 : 50); 1546 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1547 aprint_debug("%s: enter bcr %" PRIx32 "\n", __func__, bcr); 1548 1549 /* Reset bit Assert (bit 6 at 0x3E) */ 1550 bcr |= PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT; 1551 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr); 1552 aprint_debug("%s: wrote bcr %" PRIx32 "\n", __func__, bcr); 1553 delay_ms(reset_duration, sc); 1554 1555 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1556 /* Reset bit Deassert (bit 6 at 0x3E) */ 1557 bcr &= ~(PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT); 1558 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, 1559 bcr); 1560 aprint_debug("%s: wrote bcr %" PRIx32 "\n", __func__, bcr); 1561 delay_ms(reset_duration, sc); 1562 aprint_debug("%s: end of delay\n", __func__); 1563 } 1564 /* No card found on the slot. Keep Reset. */ 1565 return 1; 1566 } 1567 1568 /* 1569 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1570 * This function detect card Voltage. 1571 */ 1572 STATIC int 1573 cb_detect_voltage(struct pccbb_softc *sc) 1574 { 1575 u_int32_t psr; /* socket present-state reg */ 1576 bus_space_tag_t iot = sc->sc_base_memt; 1577 bus_space_handle_t ioh = sc->sc_base_memh; 1578 int vol = PCCARD_VCC_UKN; /* set 0 */ 1579 1580 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1581 1582 if (0x400u & psr) { 1583 vol |= PCCARD_VCC_5V; 1584 } 1585 if (0x800u & psr) { 1586 vol |= PCCARD_VCC_3V; 1587 } 1588 1589 return vol; 1590 } 1591 1592 STATIC int 1593 cbbprint(void *aux, const char *pcic) 1594 { 1595 #if 0 1596 struct cbslot_attach_args *cba = aux; 1597 1598 if (cba->cba_slot >= 0) { 1599 aprint_normal(" slot %d", cba->cba_slot); 1600 } 1601 #endif 1602 return UNCONF; 1603 } 1604 1605 /* 1606 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1607 * This function enables and disables the card 1608 */ 1609 STATIC int 1610 pccbb_cardenable(struct pccbb_softc *sc, int function) 1611 { 1612 u_int32_t command = 1613 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1614 1615 DPRINTF(("pccbb_cardenable:")); 1616 switch (function) { 1617 case CARDBUS_IO_ENABLE: 1618 command |= PCI_COMMAND_IO_ENABLE; 1619 break; 1620 case CARDBUS_IO_DISABLE: 1621 command &= ~PCI_COMMAND_IO_ENABLE; 1622 break; 1623 case CARDBUS_MEM_ENABLE: 1624 command |= PCI_COMMAND_MEM_ENABLE; 1625 break; 1626 case CARDBUS_MEM_DISABLE: 1627 command &= ~PCI_COMMAND_MEM_ENABLE; 1628 break; 1629 case CARDBUS_BM_ENABLE: 1630 command |= PCI_COMMAND_MASTER_ENABLE; 1631 break; 1632 case CARDBUS_BM_DISABLE: 1633 command &= ~PCI_COMMAND_MASTER_ENABLE; 1634 break; 1635 default: 1636 return 0; 1637 } 1638 1639 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1640 DPRINTF((" command reg 0x%x\n", command)); 1641 return 1; 1642 } 1643 1644 #if !rbus 1645 static int 1646 pccbb_io_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 1647 { 1648 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1649 int basereg; 1650 int limitreg; 1651 1652 if ((win < 0) || (win > 2)) { 1653 #if defined DIAGNOSTIC 1654 printf("cardbus_io_open: window out of range %d\n", win); 1655 #endif 1656 return 0; 1657 } 1658 1659 basereg = win * 8 + PCI_CB_IOBASE0; 1660 limitreg = win * 8 + PCI_CB_IOLIMIT0; 1661 1662 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1663 start, basereg, end, limitreg)); 1664 1665 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1666 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1667 return 1; 1668 } 1669 1670 /* 1671 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1672 */ 1673 static int 1674 pccbb_io_close(cardbus_chipset_tag_t ct, int win) 1675 { 1676 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1677 int basereg; 1678 int limitreg; 1679 1680 if ((win < 0) || (win > 2)) { 1681 #if defined DIAGNOSTIC 1682 printf("cardbus_io_close: window out of range %d\n", win); 1683 #endif 1684 return 0; 1685 } 1686 1687 basereg = win * 8 + PCI_CB_IOBASE0; 1688 limitreg = win * 8 + PCI_CB_IOLIMIT0; 1689 1690 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1691 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1692 return 1; 1693 } 1694 1695 static int 1696 pccbb_mem_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 1697 { 1698 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1699 int basereg; 1700 int limitreg; 1701 1702 if ((win < 0) || (win > 2)) { 1703 #if defined DIAGNOSTIC 1704 printf("cardbus_mem_open: window out of range %d\n", win); 1705 #endif 1706 return 0; 1707 } 1708 1709 basereg = win * 8 + PCI_CB_MEMBASE0; 1710 limitreg = win * 8 + PCI_CB_MEMLIMIT0; 1711 1712 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1713 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1714 return 1; 1715 } 1716 1717 static int 1718 pccbb_mem_close(cardbus_chipset_tag_t ct, int win) 1719 { 1720 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1721 int basereg; 1722 int limitreg; 1723 1724 if ((win < 0) || (win > 2)) { 1725 #if defined DIAGNOSTIC 1726 printf("cardbus_mem_close: window out of range %d\n", win); 1727 #endif 1728 return 0; 1729 } 1730 1731 basereg = win * 8 + PCI_CB_MEMBASE0; 1732 limitreg = win * 8 + PCI_CB_MEMLIMIT0; 1733 1734 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1735 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1736 return 1; 1737 } 1738 #endif 1739 1740 /* 1741 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1742 * int irq, 1743 * int level, 1744 * int (* func)(void *), 1745 * void *arg) 1746 * 1747 * This function registers an interrupt handler at the bridge, in 1748 * order not to call the interrupt handlers of child devices when 1749 * a card-deletion interrupt occurs. 1750 * 1751 * The arguments irq and level are not used. 1752 */ 1753 static void * 1754 pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, int irq, int level, 1755 int (*func)(void *), void *arg) 1756 { 1757 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1758 1759 return pccbb_intr_establish(sc, irq, level, func, arg); 1760 } 1761 1762 1763 /* 1764 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1765 * void *ih) 1766 * 1767 * This function removes an interrupt handler pointed by ih. 1768 */ 1769 static void 1770 pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih) 1771 { 1772 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1773 1774 pccbb_intr_disestablish(sc, ih); 1775 } 1776 1777 1778 void 1779 pccbb_intr_route(struct pccbb_softc *sc) 1780 { 1781 pcireg_t bcr, cbctrl; 1782 1783 /* initialize bridge intr routing */ 1784 bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1785 bcr &= ~CB_BCR_INTR_IREQ_ENABLE; 1786 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr); 1787 1788 switch (sc->sc_chipset) { 1789 case CB_TI113X: 1790 cbctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1791 /* functional intr enabled */ 1792 cbctrl |= PCI113X_CBCTRL_PCI_INTR; 1793 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, cbctrl); 1794 break; 1795 default: 1796 break; 1797 } 1798 } 1799 1800 /* 1801 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1802 * int irq, 1803 * int level, 1804 * int (* func)(void *), 1805 * void *arg) 1806 * 1807 * This function registers an interrupt handler at the bridge, in 1808 * order not to call the interrupt handlers of child devices when 1809 * a card-deletion interrupt occurs. 1810 * 1811 * The arguments irq is not used because pccbb selects intr vector. 1812 */ 1813 static void * 1814 pccbb_intr_establish(struct pccbb_softc *sc, int irq, int level, 1815 int (*func)(void *), void *arg) 1816 { 1817 struct pccbb_intrhand_list *pil, *newpil; 1818 1819 DPRINTF(("pccbb_intr_establish start. %p\n", LIST_FIRST(&sc->sc_pil))); 1820 1821 if (LIST_EMPTY(&sc->sc_pil)) { 1822 pccbb_intr_route(sc); 1823 } 1824 1825 /* 1826 * Allocate a room for interrupt handler structure. 1827 */ 1828 if (NULL == (newpil = 1829 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1830 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1831 return NULL; 1832 } 1833 1834 newpil->pil_func = func; 1835 newpil->pil_arg = arg; 1836 newpil->pil_icookie = makeiplcookie(level); 1837 1838 if (LIST_EMPTY(&sc->sc_pil)) { 1839 LIST_INSERT_HEAD(&sc->sc_pil, newpil, pil_next); 1840 } else { 1841 for (pil = LIST_FIRST(&sc->sc_pil); 1842 LIST_NEXT(pil, pil_next) != NULL; 1843 pil = LIST_NEXT(pil, pil_next)); 1844 LIST_INSERT_AFTER(pil, newpil, pil_next); 1845 } 1846 1847 DPRINTF(("pccbb_intr_establish add pil. %p\n", 1848 LIST_FIRST(&sc->sc_pil))); 1849 1850 return newpil; 1851 } 1852 1853 /* 1854 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1855 * void *ih) 1856 * 1857 * This function removes an interrupt handler pointed by ih. ih 1858 * should be the value returned by cardbus_intr_establish() or 1859 * NULL. 1860 * 1861 * When ih is NULL, this function will do nothing. 1862 */ 1863 static void 1864 pccbb_intr_disestablish(struct pccbb_softc *sc, void *ih) 1865 { 1866 struct pccbb_intrhand_list *pil; 1867 pcireg_t reg; 1868 1869 DPRINTF(("pccbb_intr_disestablish start. %p\n", 1870 LIST_FIRST(&sc->sc_pil))); 1871 1872 if (ih == NULL) { 1873 /* intr handler is not set */ 1874 DPRINTF(("pccbb_intr_disestablish: no ih\n")); 1875 return; 1876 } 1877 1878 #ifdef DIAGNOSTIC 1879 LIST_FOREACH(pil, &sc->sc_pil, pil_next) { 1880 DPRINTF(("pccbb_intr_disestablish: pil %p\n", pil)); 1881 if (pil == ih) { 1882 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1883 break; 1884 } 1885 } 1886 if (pil == NULL) { 1887 panic("pccbb_intr_disestablish: %s cannot find pil %p", 1888 sc->sc_dev.dv_xname, ih); 1889 } 1890 #endif 1891 1892 pil = (struct pccbb_intrhand_list *)ih; 1893 LIST_REMOVE(pil, pil_next); 1894 free(pil, M_DEVBUF); 1895 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1896 1897 if (LIST_EMPTY(&sc->sc_pil)) { 1898 /* No interrupt handlers */ 1899 1900 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1901 1902 /* stop routing PCI intr */ 1903 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1904 reg |= CB_BCR_INTR_IREQ_ENABLE; 1905 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, reg); 1906 1907 switch (sc->sc_chipset) { 1908 case CB_TI113X: 1909 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1910 /* functional intr disabled */ 1911 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1912 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1913 break; 1914 default: 1915 break; 1916 } 1917 } 1918 } 1919 1920 #if defined SHOW_REGS 1921 static void 1922 cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, bus_space_tag_t memt, 1923 bus_space_handle_t memh) 1924 { 1925 int i; 1926 printf("PCI config regs:"); 1927 for (i = 0; i < 0x50; i += 4) { 1928 if (i % 16 == 0) 1929 printf("\n 0x%02x:", i); 1930 printf(" %08x", pci_conf_read(pc, tag, i)); 1931 } 1932 for (i = 0x80; i < 0xb0; i += 4) { 1933 if (i % 16 == 0) 1934 printf("\n 0x%02x:", i); 1935 printf(" %08x", pci_conf_read(pc, tag, i)); 1936 } 1937 1938 if (memh == 0) { 1939 printf("\n"); 1940 return; 1941 } 1942 1943 printf("\nsocket regs:"); 1944 for (i = 0; i <= 0x10; i += 0x04) 1945 printf(" %08x", bus_space_read_4(memt, memh, i)); 1946 printf("\nExCA regs:"); 1947 for (i = 0; i < 0x08; ++i) 1948 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1949 printf("\n"); 1950 return; 1951 } 1952 #endif 1953 1954 /* 1955 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1956 * int busno, int function) 1957 * This is the function to make a tag to access config space of 1958 * a CardBus Card. It works same as pci_conf_read. 1959 */ 1960 static cardbustag_t 1961 pccbb_make_tag(cardbus_chipset_tag_t cc, int busno, int function) 1962 { 1963 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1964 1965 return pci_make_tag(sc->sc_pc, busno, 0, function); 1966 } 1967 1968 static void 1969 pccbb_free_tag(cardbus_chipset_tag_t cc, cardbustag_t tag) 1970 { 1971 } 1972 1973 /* 1974 * pccbb_conf_read 1975 * 1976 * This is the function to read the config space of a CardBus card. 1977 * It works the same as pci_conf_read(9). 1978 */ 1979 static cardbusreg_t 1980 pccbb_conf_read(cardbus_chipset_tag_t cc, cardbustag_t tag, int offset) 1981 { 1982 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1983 1984 return pci_conf_read(sc->sc_pc, tag, offset); 1985 } 1986 1987 /* 1988 * pccbb_conf_write 1989 * 1990 * This is the function to write the config space of a CardBus 1991 * card. It works the same as pci_conf_write(9). 1992 */ 1993 static void 1994 pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, int reg, 1995 cardbusreg_t val) 1996 { 1997 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1998 1999 pci_conf_write(sc->sc_pc, tag, reg, val); 2000 } 2001 2002 #if 0 2003 STATIC int 2004 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 2005 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 2006 int speed, int flags, 2007 bus_space_handle_t * iohp) 2008 #endif 2009 /* 2010 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 2011 * bus_addr_t start, bus_size_t size, 2012 * bus_size_t align, 2013 * struct pcmcia_io_handle *pcihp 2014 * 2015 * This function only allocates I/O region for pccard. This function 2016 * never maps the allocated region to pccard I/O area. 2017 * 2018 * XXX: The interface of this function is not very good, I believe. 2019 */ 2020 STATIC int 2021 pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, 2022 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 2023 { 2024 struct pcic_handle *ph = (struct pcic_handle *)pch; 2025 bus_addr_t ioaddr; 2026 int flags = 0; 2027 bus_space_tag_t iot; 2028 bus_space_handle_t ioh; 2029 bus_addr_t mask; 2030 #if rbus 2031 rbus_tag_t rb; 2032 #endif 2033 if (align == 0) { 2034 align = size; /* XXX: funny??? */ 2035 } 2036 2037 if (start != 0) { 2038 /* XXX: assume all card decode lower 10 bits by its hardware */ 2039 mask = 0x3ff; 2040 /* enforce to use only masked address */ 2041 start &= mask; 2042 } else { 2043 /* 2044 * calculate mask: 2045 * 1. get the most significant bit of size (call it msb). 2046 * 2. compare msb with the value of size. 2047 * 3. if size is larger, shift msb left once. 2048 * 4. obtain mask value to decrement msb. 2049 */ 2050 bus_size_t size_tmp = size; 2051 int shifts = 0; 2052 2053 mask = 1; 2054 while (size_tmp) { 2055 ++shifts; 2056 size_tmp >>= 1; 2057 } 2058 mask = (1 << shifts); 2059 if (mask < size) { 2060 mask <<= 1; 2061 } 2062 --mask; 2063 } 2064 2065 /* 2066 * Allocate some arbitrary I/O space. 2067 */ 2068 2069 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 2070 2071 #if rbus 2072 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 2073 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 2074 return 1; 2075 } 2076 DPRINTF(("pccbb_pcmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2077 (u_long) ioaddr, (u_long) size)); 2078 #else 2079 if (start) { 2080 ioaddr = start; 2081 if (bus_space_map(iot, start, size, 0, &ioh)) { 2082 return 1; 2083 } 2084 DPRINTF(("pccbb_pcmcia_io_alloc map port 0x%lx+0x%lx\n", 2085 (u_long) ioaddr, (u_long) size)); 2086 } else { 2087 flags |= PCMCIA_IO_ALLOCATED; 2088 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 2089 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 2090 size, align, 0, 0, &ioaddr, &ioh)) { 2091 /* No room be able to be get. */ 2092 return 1; 2093 } 2094 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2095 (u_long) ioaddr, (u_long) size)); 2096 } 2097 #endif 2098 2099 pcihp->iot = iot; 2100 pcihp->ioh = ioh; 2101 pcihp->addr = ioaddr; 2102 pcihp->size = size; 2103 pcihp->flags = flags; 2104 2105 return 0; 2106 } 2107 2108 /* 2109 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2110 * struct pcmcia_io_handle *pcihp) 2111 * 2112 * This function only frees I/O region for pccard. 2113 * 2114 * XXX: The interface of this function is not very good, I believe. 2115 */ 2116 void 2117 pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2118 struct pcmcia_io_handle *pcihp) 2119 { 2120 #if !rbus 2121 bus_space_tag_t iot = pcihp->iot; 2122 #endif 2123 bus_space_handle_t ioh = pcihp->ioh; 2124 bus_size_t size = pcihp->size; 2125 2126 #if rbus 2127 struct pccbb_softc *sc = 2128 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 2129 rbus_tag_t rb = sc->sc_rbus_iot; 2130 2131 rbus_space_free(rb, ioh, size, NULL); 2132 #else 2133 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 2134 bus_space_free(iot, ioh, size); 2135 else 2136 bus_space_unmap(iot, ioh, size); 2137 #endif 2138 } 2139 2140 /* 2141 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 2142 * bus_addr_t offset, bus_size_t size, 2143 * struct pcmcia_io_handle *pcihp, 2144 * int *windowp) 2145 * 2146 * This function maps the allocated I/O region to pccard. This function 2147 * never allocates any I/O region for pccard I/O area. I don't 2148 * understand why the original authors of pcmciabus separated alloc and 2149 * map. I believe the two must be unite. 2150 * 2151 * XXX: no wait timing control? 2152 */ 2153 int 2154 pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, bus_addr_t offset, 2155 bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp) 2156 { 2157 struct pcic_handle *ph = (struct pcic_handle *)pch; 2158 bus_addr_t ioaddr = pcihp->addr + offset; 2159 int i, win; 2160 #if defined CBB_DEBUG 2161 static const char *width_names[] = { "dynamic", "io8", "io16" }; 2162 #endif 2163 2164 /* Sanity check I/O handle. */ 2165 2166 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 2167 panic("pccbb_pcmcia_io_map iot is bogus"); 2168 } 2169 2170 /* XXX Sanity check offset/size. */ 2171 2172 win = -1; 2173 for (i = 0; i < PCIC_IO_WINS; i++) { 2174 if ((ph->ioalloc & (1 << i)) == 0) { 2175 win = i; 2176 ph->ioalloc |= (1 << i); 2177 break; 2178 } 2179 } 2180 2181 if (win == -1) { 2182 return 1; 2183 } 2184 2185 *windowp = win; 2186 2187 /* XXX this is pretty gross */ 2188 2189 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2190 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2191 2192 /* XXX wtf is this doing here? */ 2193 2194 #if 0 2195 printf(" port 0x%lx", (u_long) ioaddr); 2196 if (size > 1) { 2197 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2198 } 2199 #endif 2200 2201 ph->io[win].addr = ioaddr; 2202 ph->io[win].size = size; 2203 ph->io[win].width = width; 2204 2205 /* actual dirty register-value changing in the function below. */ 2206 pccbb_pcmcia_do_io_map(ph, win); 2207 2208 return 0; 2209 } 2210 2211 /* 2212 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2213 * 2214 * This function changes register-value to map I/O region for pccard. 2215 */ 2216 static void 2217 pccbb_pcmcia_do_io_map(struct pcic_handle *ph, int win) 2218 { 2219 static u_int8_t pcic_iowidth[3] = { 2220 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2221 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2222 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2223 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2224 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2225 }; 2226 2227 #define PCIC_SIA_START_LOW 0 2228 #define PCIC_SIA_START_HIGH 1 2229 #define PCIC_SIA_STOP_LOW 2 2230 #define PCIC_SIA_STOP_HIGH 3 2231 2232 int regbase_win = 0x8 + win * 0x04; 2233 u_int8_t ioctl, enable; 2234 2235 DPRINTF(("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx " 2236 "width %d\n", win, (unsigned long)ph->io[win].addr, 2237 (unsigned long)ph->io[win].size, ph->io[win].width * 8)); 2238 2239 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2240 ph->io[win].addr & 0xff); 2241 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2242 (ph->io[win].addr >> 8) & 0xff); 2243 2244 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2245 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2246 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2247 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2248 2249 ioctl = Pcic_read(ph, PCIC_IOCTL); 2250 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2251 switch (win) { 2252 case 0: 2253 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2254 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2255 PCIC_IOCTL_IO0_DATASIZE_MASK); 2256 ioctl |= pcic_iowidth[ph->io[win].width]; 2257 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2258 break; 2259 case 1: 2260 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2261 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2262 PCIC_IOCTL_IO1_DATASIZE_MASK); 2263 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2264 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2265 break; 2266 } 2267 Pcic_write(ph, PCIC_IOCTL, ioctl); 2268 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2269 #if defined(CBB_DEBUG) 2270 { 2271 u_int8_t start_low = 2272 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2273 u_int8_t start_high = 2274 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2275 u_int8_t stop_low = 2276 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2277 u_int8_t stop_high = 2278 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2279 printf("pccbb_pcmcia_do_io_map start %02x %02x, " 2280 "stop %02x %02x, ioctl %02x enable %02x\n", 2281 start_low, start_high, stop_low, stop_high, ioctl, enable); 2282 } 2283 #endif 2284 } 2285 2286 /* 2287 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2288 * 2289 * This function unmaps I/O region. No return value. 2290 */ 2291 STATIC void 2292 pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t pch, int win) 2293 { 2294 struct pcic_handle *ph = (struct pcic_handle *)pch; 2295 int reg; 2296 2297 if (win >= PCIC_IO_WINS || win < 0) { 2298 panic("pccbb_pcmcia_io_unmap: window out of range"); 2299 } 2300 2301 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2302 switch (win) { 2303 case 0: 2304 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2305 break; 2306 case 1: 2307 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2308 break; 2309 } 2310 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2311 2312 ph->ioalloc &= ~(1 << win); 2313 } 2314 2315 static int 2316 pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 2317 { 2318 u_int8_t stat; 2319 int i; 2320 2321 /* wait an initial 10ms for quick cards */ 2322 stat = Pcic_read(ph, PCIC_IF_STATUS); 2323 if (stat & PCIC_IF_STATUS_READY) 2324 return (0); 2325 pccbb_pcmcia_delay(ph, 10, "pccwr0"); 2326 for (i = 0; i < 50; i++) { 2327 stat = Pcic_read(ph, PCIC_IF_STATUS); 2328 if (stat & PCIC_IF_STATUS_READY) 2329 return (0); 2330 if ((stat & PCIC_IF_STATUS_CARDDETECT_MASK) != 2331 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2332 return (ENXIO); 2333 /* wait .1s (100ms) each iteration now */ 2334 pccbb_pcmcia_delay(ph, 100, "pccwr1"); 2335 } 2336 2337 printf("pccbb_pcmcia_wait_ready: ready never happened, status=%02x\n", stat); 2338 return (EWOULDBLOCK); 2339 } 2340 2341 /* 2342 * Perform long (msec order) delay. timo is in milliseconds. 2343 */ 2344 static void 2345 pccbb_pcmcia_delay(struct pcic_handle *ph, int timo, const char *wmesg) 2346 { 2347 #ifdef DIAGNOSTIC 2348 if (timo <= 0) 2349 panic("pccbb_pcmcia_delay: called with timeout %d", timo); 2350 if (!curlwp) 2351 panic("pccbb_pcmcia_delay: called in interrupt context"); 2352 #if 0 2353 if (!ph->event_thread) 2354 panic("pccbb_pcmcia_delay: no event thread"); 2355 #endif 2356 #endif 2357 DPRINTF(("pccbb_pcmcia_delay: \"%s\" %p, sleep %d ms\n", 2358 wmesg, ph->event_thread, timo)); 2359 tsleep(pccbb_pcmcia_delay, PWAIT, wmesg, roundup(timo * hz, 1000) / 1000); 2360 } 2361 2362 /* 2363 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2364 * 2365 * This function enables the card. All information is stored in 2366 * the first argument, pcmcia_chipset_handle_t. 2367 */ 2368 STATIC void 2369 pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2370 { 2371 struct pcic_handle *ph = (struct pcic_handle *)pch; 2372 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2373 pcireg_t spsr; 2374 int voltage; 2375 int win; 2376 u_int8_t power, intr; 2377 #ifdef DIAGNOSTIC 2378 int reg; 2379 #endif 2380 2381 /* this bit is mostly stolen from pcic_attach_card */ 2382 2383 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2384 2385 /* get card Vcc info */ 2386 spsr = 2387 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2388 CB_SOCKET_STAT); 2389 if (spsr & CB_SOCKET_STAT_5VCARD) { 2390 DPRINTF(("5V card\n")); 2391 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2392 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2393 DPRINTF(("3V card\n")); 2394 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2395 } else { 2396 DPRINTF(("?V card, 0x%x\n", spsr)); /* XXX */ 2397 return; 2398 } 2399 2400 /* disable interrupts; assert RESET */ 2401 intr = Pcic_read(ph, PCIC_INTR); 2402 intr &= PCIC_INTR_ENABLE; 2403 Pcic_write(ph, PCIC_INTR, intr); 2404 2405 /* zero out the address windows */ 2406 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2407 2408 /* power down the socket to reset it, clear the card reset pin */ 2409 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2410 2411 /* power off; assert output enable bit */ 2412 power = PCIC_PWRCTL_OE; 2413 Pcic_write(ph, PCIC_PWRCTL, power); 2414 2415 /* power up the socket */ 2416 if (pccbb_power(sc, voltage) == 0) 2417 return; 2418 2419 /* 2420 * Table 4-18 and figure 4-6 of the PC Card specifiction say: 2421 * Vcc Rising Time (Tpr) = 100ms (handled in pccbb_power() above) 2422 * RESET Width (Th (Hi-z RESET)) = 1ms 2423 * RESET Width (Tw (RESET)) = 10us 2424 * 2425 * some machines require some more time to be settled 2426 * for example old toshiba topic bridges! 2427 * (100ms is added here). 2428 */ 2429 pccbb_pcmcia_delay(ph, 200 + 1, "pccen1"); 2430 2431 /* negate RESET */ 2432 intr |= PCIC_INTR_RESET; 2433 Pcic_write(ph, PCIC_INTR, intr); 2434 2435 /* 2436 * RESET Setup Time (Tsu (RESET)) = 20ms 2437 */ 2438 pccbb_pcmcia_delay(ph, 20, "pccen2"); 2439 2440 #ifdef DIAGNOSTIC 2441 reg = Pcic_read(ph, PCIC_IF_STATUS); 2442 if ((reg & PCIC_IF_STATUS_POWERACTIVE) == 0) 2443 printf("pccbb_pcmcia_socket_enable: no power, status=%x\n", reg); 2444 #endif 2445 2446 /* wait for the chip to finish initializing */ 2447 if (pccbb_pcmcia_wait_ready(ph)) { 2448 #ifdef DIAGNOSTIC 2449 printf("pccbb_pcmcia_socket_enable: never became ready\n"); 2450 #endif 2451 /* XXX return a failure status?? */ 2452 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2453 Pcic_write(ph, PCIC_PWRCTL, 0); 2454 return; 2455 } 2456 2457 /* reinstall all the memory and io mappings */ 2458 for (win = 0; win < PCIC_MEM_WINS; ++win) 2459 if (ph->memalloc & (1 << win)) 2460 pccbb_pcmcia_do_mem_map(ph, win); 2461 for (win = 0; win < PCIC_IO_WINS; ++win) 2462 if (ph->ioalloc & (1 << win)) 2463 pccbb_pcmcia_do_io_map(ph, win); 2464 } 2465 2466 /* 2467 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2468 * 2469 * This function disables the card. All information is stored in 2470 * the first argument, pcmcia_chipset_handle_t. 2471 */ 2472 STATIC void 2473 pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t pch) 2474 { 2475 struct pcic_handle *ph = (struct pcic_handle *)pch; 2476 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2477 u_int8_t intr; 2478 2479 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2480 2481 /* disable interrupts; assert RESET */ 2482 intr = Pcic_read(ph, PCIC_INTR); 2483 intr &= PCIC_INTR_ENABLE; 2484 Pcic_write(ph, PCIC_INTR, intr); 2485 2486 /* zero out the address windows */ 2487 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2488 2489 /* power down the socket to reset it, clear the card reset pin */ 2490 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2491 2492 /* disable socket: negate output enable bit and power off */ 2493 Pcic_write(ph, PCIC_PWRCTL, 0); 2494 2495 /* 2496 * Vcc Falling Time (Tpf) = 300ms 2497 */ 2498 pccbb_pcmcia_delay(ph, 300, "pccwr1"); 2499 } 2500 2501 STATIC void 2502 pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t pch, int type) 2503 { 2504 struct pcic_handle *ph = (struct pcic_handle *)pch; 2505 u_int8_t intr; 2506 2507 /* set the card type */ 2508 2509 intr = Pcic_read(ph, PCIC_INTR); 2510 intr &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_CARDTYPE_MASK); 2511 if (type == PCMCIA_IFTYPE_IO) 2512 intr |= PCIC_INTR_CARDTYPE_IO; 2513 else 2514 intr |= PCIC_INTR_CARDTYPE_MEM; 2515 Pcic_write(ph, PCIC_INTR, intr); 2516 2517 DPRINTF(("%s: pccbb_pcmcia_socket_settype %02x type %s %02x\n", 2518 ph->ph_parent->dv_xname, ph->sock, 2519 ((type == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2520 } 2521 2522 /* 2523 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2524 * 2525 * This function detects whether a card is in the slot or not. 2526 * If a card is inserted, return 1. Otherwise, return 0. 2527 */ 2528 STATIC int 2529 pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch) 2530 { 2531 struct pcic_handle *ph = (struct pcic_handle *)pch; 2532 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2533 2534 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2535 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2536 } 2537 2538 #if 0 2539 STATIC int 2540 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2541 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2542 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2543 #endif 2544 /* 2545 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2546 * bus_size_t size, 2547 * struct pcmcia_mem_handle *pcmhp) 2548 * 2549 * This function only allocates memory region for pccard. This 2550 * function never maps the allocated region to pccard memory area. 2551 * 2552 * XXX: Why the argument of start address is not in? 2553 */ 2554 STATIC int 2555 pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 2556 struct pcmcia_mem_handle *pcmhp) 2557 { 2558 struct pcic_handle *ph = (struct pcic_handle *)pch; 2559 bus_space_handle_t memh; 2560 bus_addr_t addr; 2561 bus_size_t sizepg; 2562 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2563 #if rbus 2564 rbus_tag_t rb; 2565 #endif 2566 2567 /* Check that the card is still there. */ 2568 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2569 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2570 return 1; 2571 2572 /* out of sc->memh, allocate as many pages as necessary */ 2573 2574 /* convert size to PCIC pages */ 2575 /* 2576 * This is not enough; when the requested region is on the page 2577 * boundaries, this may calculate wrong result. 2578 */ 2579 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2580 #if 0 2581 if (sizepg > PCIC_MAX_MEM_PAGES) { 2582 return 1; 2583 } 2584 #endif 2585 2586 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2587 return 1; 2588 } 2589 2590 addr = 0; /* XXX gcc -Wuninitialized */ 2591 2592 #if rbus 2593 rb = sc->sc_rbus_memt; 2594 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2595 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2596 &addr, &memh)) { 2597 return 1; 2598 } 2599 #else 2600 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2601 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2602 0, /* boundary */ 2603 0, /* flags */ 2604 &addr, &memh)) { 2605 return 1; 2606 } 2607 #endif 2608 2609 DPRINTF(("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, " 2610 "realsize 0x%lx\n", (unsigned long)addr, (unsigned long)size, 2611 (unsigned long)sizepg * PCIC_MEM_PAGESIZE)); 2612 2613 pcmhp->memt = sc->sc_memt; 2614 pcmhp->memh = memh; 2615 pcmhp->addr = addr; 2616 pcmhp->size = size; 2617 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2618 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2619 pcmhp->mhandle = 0; 2620 /* No offset??? Funny. */ 2621 2622 return 0; 2623 } 2624 2625 /* 2626 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2627 * struct pcmcia_mem_handle *pcmhp) 2628 * 2629 * This function release the memory space allocated by the function 2630 * pccbb_pcmcia_mem_alloc(). 2631 */ 2632 STATIC void 2633 pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2634 struct pcmcia_mem_handle *pcmhp) 2635 { 2636 #if rbus 2637 struct pcic_handle *ph = (struct pcic_handle *)pch; 2638 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2639 2640 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2641 #else 2642 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2643 #endif 2644 } 2645 2646 /* 2647 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2648 * 2649 * This function release the memory space allocated by the function 2650 * pccbb_pcmcia_mem_alloc(). 2651 */ 2652 STATIC void 2653 pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2654 { 2655 int regbase_win; 2656 bus_addr_t phys_addr; 2657 bus_addr_t phys_end; 2658 2659 #define PCIC_SMM_START_LOW 0 2660 #define PCIC_SMM_START_HIGH 1 2661 #define PCIC_SMM_STOP_LOW 2 2662 #define PCIC_SMM_STOP_HIGH 3 2663 #define PCIC_CMA_LOW 4 2664 #define PCIC_CMA_HIGH 5 2665 2666 u_int8_t start_low, start_high = 0; 2667 u_int8_t stop_low, stop_high; 2668 u_int8_t off_low, off_high; 2669 u_int8_t mem_window; 2670 int reg; 2671 2672 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2673 int mem8 = 2674 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2675 || (kind == PCMCIA_MEM_ATTR); 2676 2677 regbase_win = 0x10 + win * 0x08; 2678 2679 phys_addr = ph->mem[win].addr; 2680 phys_end = phys_addr + ph->mem[win].size; 2681 2682 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2683 (unsigned long)phys_addr, (unsigned long)phys_end, 2684 (unsigned long)ph->mem[win].offset)); 2685 2686 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2687 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2688 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2689 2690 /* bit 19:12 */ 2691 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2692 /* bit 23:20 and bit 7 on */ 2693 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2694 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2695 /* bit 31:24, for 32-bit address */ 2696 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2697 2698 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2699 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2700 2701 if (((struct pccbb_softc *)ph-> 2702 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2703 Pcic_write(ph, 0x40 + win, mem_window); 2704 } 2705 2706 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2707 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2708 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2709 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2710 2711 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2712 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2713 2714 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2715 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2716 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2717 | ((kind == PCMCIA_MEM_ATTR) ? 2718 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2719 2720 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2721 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2722 2723 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2724 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2725 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2726 2727 #if defined(CBB_DEBUG) 2728 { 2729 int r1, r2, r3, r4, r5, r6, r7 = 0; 2730 2731 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2732 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2733 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2734 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2735 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2736 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2737 if (((struct pccbb_softc *)(ph-> 2738 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2739 r7 = Pcic_read(ph, 0x40 + win); 2740 } 2741 2742 printf("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2743 "%02x%02x", win, r1, r2, r3, r4, r5, r6); 2744 if (((struct pccbb_softc *)(ph-> 2745 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2746 printf(" %02x", r7); 2747 } 2748 printf("\n"); 2749 } 2750 #endif 2751 } 2752 2753 /* 2754 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2755 * bus_addr_t card_addr, bus_size_t size, 2756 * struct pcmcia_mem_handle *pcmhp, 2757 * bus_addr_t *offsetp, int *windowp) 2758 * 2759 * This function maps memory space allocated by the function 2760 * pccbb_pcmcia_mem_alloc(). 2761 */ 2762 STATIC int 2763 pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2764 bus_addr_t card_addr, bus_size_t size, struct pcmcia_mem_handle *pcmhp, 2765 bus_addr_t *offsetp, int *windowp) 2766 { 2767 struct pcic_handle *ph = (struct pcic_handle *)pch; 2768 bus_addr_t busaddr; 2769 long card_offset; 2770 int win; 2771 2772 /* Check that the card is still there. */ 2773 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2774 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2775 return 1; 2776 2777 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2778 if ((ph->memalloc & (1 << win)) == 0) { 2779 ph->memalloc |= (1 << win); 2780 break; 2781 } 2782 } 2783 2784 if (win == PCIC_MEM_WINS) { 2785 return 1; 2786 } 2787 2788 *windowp = win; 2789 2790 /* XXX this is pretty gross */ 2791 2792 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2793 panic("pccbb_pcmcia_mem_map memt is bogus"); 2794 } 2795 2796 busaddr = pcmhp->addr; 2797 2798 /* 2799 * compute the address offset to the pcmcia address space for the 2800 * pcic. this is intentionally signed. The masks and shifts below 2801 * will cause TRT to happen in the pcic registers. Deal with making 2802 * sure the address is aligned, and return the alignment offset. 2803 */ 2804 2805 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2806 card_addr -= *offsetp; 2807 2808 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2809 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2810 (u_long) card_addr)); 2811 2812 /* 2813 * include the offset in the size, and decrement size by one, since 2814 * the hw wants start/stop 2815 */ 2816 size += *offsetp - 1; 2817 2818 card_offset = (((long)card_addr) - ((long)busaddr)); 2819 2820 ph->mem[win].addr = busaddr; 2821 ph->mem[win].size = size; 2822 ph->mem[win].offset = card_offset; 2823 ph->mem[win].kind = kind; 2824 2825 pccbb_pcmcia_do_mem_map(ph, win); 2826 2827 return 0; 2828 } 2829 2830 /* 2831 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2832 * int window) 2833 * 2834 * This function unmaps memory space which mapped by the function 2835 * pccbb_pcmcia_mem_map(). 2836 */ 2837 STATIC void 2838 pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, int window) 2839 { 2840 struct pcic_handle *ph = (struct pcic_handle *)pch; 2841 int reg; 2842 2843 if (window >= PCIC_MEM_WINS) { 2844 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2845 } 2846 2847 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2848 reg &= ~(1 << window); 2849 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2850 2851 ph->memalloc &= ~(1 << window); 2852 } 2853 2854 #if defined PCCBB_PCMCIA_POLL 2855 struct pccbb_poll_str { 2856 void *arg; 2857 int (*func)(void *); 2858 int level; 2859 struct pcic_handle *ph; 2860 int count; 2861 int num; 2862 struct callout poll_ch; 2863 }; 2864 2865 static struct pccbb_poll_str pccbb_poll[10]; 2866 static int pccbb_poll_n = 0; 2867 2868 static void pccbb_pcmcia_poll(void *arg); 2869 2870 static void 2871 pccbb_pcmcia_poll(void *arg) 2872 { 2873 struct pccbb_poll_str *poll = arg; 2874 struct pcic_handle *ph = poll->ph; 2875 struct pccbb_softc *sc = ph->sc; 2876 int s; 2877 u_int32_t spsr; /* socket present-state reg */ 2878 2879 callout_reset(&poll->poll_ch, hz * 2, pccbb_pcmcia_poll, arg); 2880 switch (poll->level) { 2881 case IPL_NET: 2882 s = splnet(); 2883 break; 2884 case IPL_BIO: 2885 s = splbio(); 2886 break; 2887 case IPL_TTY: /* fallthrough */ 2888 default: 2889 s = spltty(); 2890 break; 2891 } 2892 2893 spsr = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2894 CB_SOCKET_STAT); 2895 2896 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2897 if (!(spsr & 0x40)) /* CINT low */ 2898 #else 2899 if (1) 2900 #endif 2901 { 2902 if ((*poll->func) (poll->arg) > 0) { 2903 ++poll->count; 2904 /* printf("intr: reported from poller, 0x%x\n", spsr); */ 2905 #if defined LEVEL2 2906 } else { 2907 printf("intr: miss! 0x%x\n", spsr); 2908 #endif 2909 } 2910 } 2911 splx(s); 2912 } 2913 #endif /* defined CB_PCMCIA_POLL */ 2914 2915 /* 2916 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2917 * struct pcmcia_function *pf, 2918 * int ipl, 2919 * int (*func)(void *), 2920 * void *arg); 2921 * 2922 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2923 */ 2924 STATIC void * 2925 pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2926 struct pcmcia_function *pf, int ipl, int (*func)(void *), void *arg) 2927 { 2928 struct pcic_handle *ph = (struct pcic_handle *)pch; 2929 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2930 2931 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2932 /* what should I do? */ 2933 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2934 DPRINTF(("%s does not provide edge nor pulse " 2935 "interrupt\n", sc->sc_dev.dv_xname)); 2936 return NULL; 2937 } 2938 /* 2939 * XXX Noooooo! The interrupt flag must set properly!! 2940 * dumb pcmcia driver!! 2941 */ 2942 } 2943 2944 return pccbb_intr_establish(sc, 0, ipl, func, arg); 2945 } 2946 2947 /* 2948 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2949 * void *ih) 2950 * 2951 * This function disables PC-Card interrupt. 2952 */ 2953 STATIC void 2954 pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 2955 { 2956 struct pcic_handle *ph = (struct pcic_handle *)pch; 2957 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2958 2959 pccbb_intr_disestablish(sc, ih); 2960 } 2961 2962 #if rbus 2963 /* 2964 * static int 2965 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2966 * bus_addr_t addr, bus_size_t size, 2967 * bus_addr_t mask, bus_size_t align, 2968 * int flags, bus_addr_t *addrp; 2969 * bus_space_handle_t *bshp) 2970 * 2971 * This function allocates a portion of memory or io space for 2972 * clients. This function is called from CardBus card drivers. 2973 */ 2974 static int 2975 pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2976 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 2977 int flags, bus_addr_t *addrp, bus_space_handle_t *bshp) 2978 { 2979 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2980 2981 DPRINTF(("pccbb_rbus_cb_space_alloc: addr 0x%lx, size 0x%lx, " 2982 "mask 0x%lx, align 0x%lx\n", (unsigned long)addr, 2983 (unsigned long)size, (unsigned long)mask, (unsigned long)align)); 2984 2985 if (align == 0) { 2986 align = size; 2987 } 2988 2989 if (rb->rb_bt == sc->sc_memt) { 2990 if (align < 16) { 2991 return 1; 2992 } 2993 /* 2994 * XXX: align more than 0x1000 to avoid overwrapping 2995 * memory windows for two or more devices. 0x1000 2996 * means memory window's granularity. 2997 * 2998 * Two or more devices should be able to share same 2999 * memory window region. However, overrapping memory 3000 * window is not good because some devices, such as 3001 * 3Com 3C575[BC], have a broken address decoder and 3002 * intrude other's memory region. 3003 */ 3004 if (align < 0x1000) { 3005 align = 0x1000; 3006 } 3007 } else if (rb->rb_bt == sc->sc_iot) { 3008 if (align < 4) { 3009 return 1; 3010 } 3011 /* XXX: hack for avoiding ISA image */ 3012 if (mask < 0x0100) { 3013 mask = 0x3ff; 3014 addr = 0x300; 3015 } 3016 3017 } else { 3018 DPRINTF(("pccbb_rbus_cb_space_alloc: Bus space tag 0x%lx is " 3019 "NOT used. io: 0x%lx, mem: 0x%lx\n", 3020 (unsigned long)rb->rb_bt, (unsigned long)sc->sc_iot, 3021 (unsigned long)sc->sc_memt)); 3022 return 1; 3023 /* XXX: panic here? */ 3024 } 3025 3026 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 3027 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 3028 return 1; 3029 } 3030 3031 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 3032 3033 return 0; 3034 } 3035 3036 /* 3037 * static int 3038 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 3039 * bus_space_handle_t *bshp, bus_size_t size); 3040 * 3041 * This function is called from CardBus card drivers. 3042 */ 3043 static int 3044 pccbb_rbus_cb_space_free(cardbus_chipset_tag_t ct, rbus_tag_t rb, 3045 bus_space_handle_t bsh, bus_size_t size) 3046 { 3047 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 3048 bus_space_tag_t bt = rb->rb_bt; 3049 3050 pccbb_close_win(sc, bt, bsh, size); 3051 3052 if (bt == sc->sc_memt) { 3053 } else if (bt == sc->sc_iot) { 3054 } else { 3055 return 1; 3056 /* XXX: panic here? */ 3057 } 3058 3059 return rbus_space_free(rb, bsh, size, NULL); 3060 } 3061 #endif /* rbus */ 3062 3063 #if rbus 3064 3065 static int 3066 pccbb_open_win(struct pccbb_softc *sc, bus_space_tag_t bst, bus_addr_t addr, 3067 bus_size_t size, bus_space_handle_t bsh, int flags) 3068 { 3069 struct pccbb_win_chain_head *head; 3070 bus_addr_t align; 3071 3072 head = &sc->sc_iowindow; 3073 align = 0x04; 3074 if (sc->sc_memt == bst) { 3075 head = &sc->sc_memwindow; 3076 align = 0x1000; 3077 DPRINTF(("using memory window, 0x%lx 0x%lx 0x%lx\n\n", 3078 (unsigned long)sc->sc_iot, (unsigned long)sc->sc_memt, 3079 (unsigned long)bst)); 3080 } 3081 3082 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 3083 printf("%s: pccbb_open_win: %s winlist insert failed\n", 3084 sc->sc_dev.dv_xname, 3085 (head == &sc->sc_memwindow) ? "mem" : "io"); 3086 } 3087 pccbb_winset(align, sc, bst); 3088 3089 return 0; 3090 } 3091 3092 static int 3093 pccbb_close_win(struct pccbb_softc *sc, bus_space_tag_t bst, 3094 bus_space_handle_t bsh, bus_size_t size) 3095 { 3096 struct pccbb_win_chain_head *head; 3097 bus_addr_t align; 3098 3099 head = &sc->sc_iowindow; 3100 align = 0x04; 3101 if (sc->sc_memt == bst) { 3102 head = &sc->sc_memwindow; 3103 align = 0x1000; 3104 } 3105 3106 if (pccbb_winlist_delete(head, bsh, size)) { 3107 printf("%s: pccbb_close_win: %s winlist delete failed\n", 3108 sc->sc_dev.dv_xname, 3109 (head == &sc->sc_memwindow) ? "mem" : "io"); 3110 } 3111 pccbb_winset(align, sc, bst); 3112 3113 return 0; 3114 } 3115 3116 static int 3117 pccbb_winlist_insert(struct pccbb_win_chain_head *head, bus_addr_t start, 3118 bus_size_t size, bus_space_handle_t bsh, int flags) 3119 { 3120 struct pccbb_win_chain *chainp, *elem; 3121 3122 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 3123 M_NOWAIT)) == NULL) 3124 return (1); /* fail */ 3125 3126 elem->wc_start = start; 3127 elem->wc_end = start + (size - 1); 3128 elem->wc_handle = bsh; 3129 elem->wc_flags = flags; 3130 3131 TAILQ_FOREACH(chainp, head, wc_list) { 3132 if (chainp->wc_end >= start) 3133 break; 3134 } 3135 if (chainp != NULL) 3136 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 3137 else 3138 TAILQ_INSERT_TAIL(head, elem, wc_list); 3139 return (0); 3140 } 3141 3142 static int 3143 pccbb_winlist_delete(struct pccbb_win_chain_head *head, bus_space_handle_t bsh, 3144 bus_size_t size) 3145 { 3146 struct pccbb_win_chain *chainp; 3147 3148 TAILQ_FOREACH(chainp, head, wc_list) { 3149 if (memcmp(&chainp->wc_handle, &bsh, sizeof(bsh)) == 0) 3150 break; 3151 } 3152 if (chainp == NULL) 3153 return 1; /* fail: no candidate to remove */ 3154 3155 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 3156 printf("pccbb_winlist_delete: window 0x%lx size " 3157 "inconsistent: 0x%lx, 0x%lx\n", 3158 (unsigned long)chainp->wc_start, 3159 (unsigned long)(chainp->wc_end - chainp->wc_start), 3160 (unsigned long)(size - 1)); 3161 return 1; 3162 } 3163 3164 TAILQ_REMOVE(head, chainp, wc_list); 3165 free(chainp, M_DEVBUF); 3166 3167 return 0; 3168 } 3169 3170 static void 3171 pccbb_winset(bus_addr_t align, struct pccbb_softc *sc, bus_space_tag_t bst) 3172 { 3173 pci_chipset_tag_t pc; 3174 pcitag_t tag; 3175 bus_addr_t mask = ~(align - 1); 3176 struct { 3177 cardbusreg_t win_start; 3178 cardbusreg_t win_limit; 3179 int win_flags; 3180 } win[2]; 3181 struct pccbb_win_chain *chainp; 3182 int offs; 3183 3184 win[0].win_start = win[1].win_start = 0xffffffff; 3185 win[0].win_limit = win[1].win_limit = 0; 3186 win[0].win_flags = win[1].win_flags = 0; 3187 3188 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3189 offs = PCI_CB_IOBASE0; 3190 if (sc->sc_memt == bst) { 3191 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3192 offs = PCI_CB_MEMBASE0; 3193 } 3194 3195 if (chainp != NULL) { 3196 win[0].win_start = chainp->wc_start & mask; 3197 win[0].win_limit = chainp->wc_end & mask; 3198 win[0].win_flags = chainp->wc_flags; 3199 chainp = TAILQ_NEXT(chainp, wc_list); 3200 } 3201 3202 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3203 if (win[1].win_start == 0xffffffff) { 3204 /* window 1 is not used */ 3205 if ((win[0].win_flags == chainp->wc_flags) && 3206 (win[0].win_limit + align >= 3207 (chainp->wc_start & mask))) { 3208 /* concatenate */ 3209 win[0].win_limit = chainp->wc_end & mask; 3210 } else { 3211 /* make new window */ 3212 win[1].win_start = chainp->wc_start & mask; 3213 win[1].win_limit = chainp->wc_end & mask; 3214 win[1].win_flags = chainp->wc_flags; 3215 } 3216 continue; 3217 } 3218 3219 /* Both windows are engaged. */ 3220 if (win[0].win_flags == win[1].win_flags) { 3221 /* same flags */ 3222 if (win[0].win_flags == chainp->wc_flags) { 3223 if (win[1].win_start - (win[0].win_limit + 3224 align) < 3225 (chainp->wc_start & mask) - 3226 ((chainp->wc_end & mask) + align)) { 3227 /* 3228 * merge window 0 and 1, and set win1 3229 * to chainp 3230 */ 3231 win[0].win_limit = win[1].win_limit; 3232 win[1].win_start = 3233 chainp->wc_start & mask; 3234 win[1].win_limit = 3235 chainp->wc_end & mask; 3236 } else { 3237 win[1].win_limit = 3238 chainp->wc_end & mask; 3239 } 3240 } else { 3241 /* different flags */ 3242 3243 /* concatenate win0 and win1 */ 3244 win[0].win_limit = win[1].win_limit; 3245 /* allocate win[1] to new space */ 3246 win[1].win_start = chainp->wc_start & mask; 3247 win[1].win_limit = chainp->wc_end & mask; 3248 win[1].win_flags = chainp->wc_flags; 3249 } 3250 } else { 3251 /* the flags of win[0] and win[1] is different */ 3252 if (win[0].win_flags == chainp->wc_flags) { 3253 win[0].win_limit = chainp->wc_end & mask; 3254 /* 3255 * XXX this creates overlapping windows, so 3256 * what should the poor bridge do if one is 3257 * cachable, and the other is not? 3258 */ 3259 printf("%s: overlapping windows\n", 3260 sc->sc_dev.dv_xname); 3261 } else { 3262 win[1].win_limit = chainp->wc_end & mask; 3263 } 3264 } 3265 } 3266 3267 pc = sc->sc_pc; 3268 tag = sc->sc_tag; 3269 pci_conf_write(pc, tag, offs, win[0].win_start); 3270 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3271 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3272 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3273 DPRINTF(("--pccbb_winset: win0 [0x%lx, 0x%lx), win1 [0x%lx, 0x%lx)\n", 3274 (unsigned long)pci_conf_read(pc, tag, offs), 3275 (unsigned long)pci_conf_read(pc, tag, offs + 4) + align, 3276 (unsigned long)pci_conf_read(pc, tag, offs + 8), 3277 (unsigned long)pci_conf_read(pc, tag, offs + 12) + align)); 3278 3279 if (bst == sc->sc_memt) { 3280 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BRIDGE_CONTROL_REG); 3281 3282 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 3283 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 3284 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3285 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 3286 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3287 pci_conf_write(pc, tag, PCI_BRIDGE_CONTROL_REG, bcr); 3288 } 3289 } 3290 3291 #endif /* rbus */ 3292 3293 static bool 3294 pccbb_suspend(device_t dv) 3295 { 3296 struct pccbb_softc *sc = device_private(dv); 3297 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3298 bus_space_handle_t base_memh = sc->sc_base_memh; 3299 pcireg_t reg; 3300 3301 if (sc->sc_pil_intr_enable) 3302 (void)pccbbintr_function(sc); 3303 sc->sc_pil_intr_enable = 0; 3304 3305 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3306 /* Disable interrupts. */ 3307 reg &= ~(CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER); 3308 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3309 /* XXX joerg Disable power to the socket? */ 3310 3311 #ifdef __NO_STRICT_ALIGNMENT 3312 /* XXX - the register is at 0x82, so this access is not valid */ 3313 if (sc->sc_chipset == CB_RX5C47X) 3314 sc->sc_ricoh_misc_ctrl = pci_conf_read(sc->sc_pc, 3315 sc->sc_tag, RICOH_PCI_MISC_CTRL); 3316 #endif 3317 3318 return true; 3319 } 3320 3321 static bool 3322 pccbb_resume(device_t dv) 3323 { 3324 struct pccbb_softc *sc = device_private(dv); 3325 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3326 bus_space_handle_t base_memh = sc->sc_base_memh; 3327 pcireg_t reg; 3328 3329 pccbb_chipinit(sc); 3330 /* setup memory and io space window for CB */ 3331 pccbb_winset(0x1000, sc, sc->sc_memt); 3332 pccbb_winset(0x04, sc, sc->sc_iot); 3333 #ifdef __NO_STRICT_ALIGNMENT 3334 /* XXX - the register is at 0x82, so this access is not valid */ 3335 if (sc->sc_chipset == CB_RX5C47X) 3336 pci_conf_write(sc->sc_pc, sc->sc_tag, 3337 RICOH_PCI_MISC_CTRL, sc->sc_ricoh_misc_ctrl); 3338 #endif 3339 3340 /* CSC Interrupt: Card detect interrupt on */ 3341 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3342 /* Card detect intr is turned on. */ 3343 reg |= CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; 3344 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3345 /* reset interrupt */ 3346 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3347 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3348 3349 /* 3350 * check for card insertion or removal during suspend period. 3351 * XXX: the code can't cope with card swap (remove then 3352 * insert). how can we detect such situation? 3353 */ 3354 (void)pccbbintr(sc); 3355 3356 sc->sc_pil_intr_enable = 1; 3357 3358 return true; 3359 } 3360
Indexes created Fri Sep 26 08:10:20 GMT 2025