pccbb.c revision 1.167
1 /* $NetBSD: pccbb.c,v 1.167 2008/03/04 22:15:16 dyoung Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: pccbb.c,v 1.167 2008/03/04 22:15:16 dyoung Exp $"); 35 36 /* 37 #define CBB_DEBUG 38 #define SHOW_REGS 39 */ 40 41 /* 42 * BROKEN! 43 #define PCCBB_PCMCIA_POLL 44 #define CB_PCMCIA_POLL 45 #define CB_PCMCIA_POLL_ONLY 46 #define LEVEL2 47 */ 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/kernel.h> 52 #include <sys/errno.h> 53 #include <sys/ioctl.h> 54 #include <sys/reboot.h> /* for bootverbose */ 55 #include <sys/syslog.h> 56 #include <sys/device.h> 57 #include <sys/malloc.h> 58 #include <sys/proc.h> 59 60 #include <sys/intr.h> 61 #include <sys/bus.h> 62 63 #include <dev/pci/pcivar.h> 64 #include <dev/pci/pcireg.h> 65 #include <dev/pci/pcidevs.h> 66 67 #include <dev/pci/pccbbreg.h> 68 69 #include <dev/cardbus/cardslotvar.h> 70 71 #include <dev/cardbus/cardbusvar.h> 72 73 #include <dev/pcmcia/pcmciareg.h> 74 #include <dev/pcmcia/pcmciavar.h> 75 76 #include <dev/ic/i82365reg.h> 77 #include <dev/ic/i82365var.h> 78 #include <dev/pci/pccbbvar.h> 79 80 #include "locators.h" 81 82 #ifndef __NetBSD_Version__ 83 struct cfdriver cbb_cd = { 84 NULL, "cbb", DV_DULL 85 }; 86 #endif 87 88 #ifdef CBB_DEBUG 89 #define DPRINTF(x) printf x 90 #define STATIC 91 #else 92 #define DPRINTF(x) 93 #define STATIC static 94 #endif 95 96 int pccbb_burstup = 1; 97 98 /* 99 * delay_ms() is wait in milliseconds. It should be used instead 100 * of delay() if you want to wait more than 1 ms. 101 */ 102 static inline void 103 delay_ms(int millis, void *param) 104 { 105 if (cold) 106 delay(millis * 1000); 107 else 108 tsleep(param, PWAIT, "pccbb", MAX(2, hz * millis / 1000)); 109 } 110 111 int pcicbbmatch(device_t, struct cfdata *, void *); 112 void pccbbattach(device_t, device_t, void *); 113 int pccbbdetach(device_t, int); 114 int pccbbintr(void *); 115 static void pci113x_insert(void *); 116 static int pccbbintr_function(struct pccbb_softc *); 117 118 static int pccbb_detect_card(struct pccbb_softc *); 119 120 static void pccbb_pcmcia_write(struct pcic_handle *, int, u_int8_t); 121 static u_int8_t pccbb_pcmcia_read(struct pcic_handle *, int); 122 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 123 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 124 125 STATIC int cb_reset(struct pccbb_softc *); 126 STATIC int cb_detect_voltage(struct pccbb_softc *); 127 STATIC int cbbprint(void *, const char *); 128 129 static int cb_chipset(u_int32_t, int *); 130 STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *, 131 struct pcmciabus_attach_args *); 132 #if 0 133 STATIC void pccbb_pcmcia_attach_card(struct pcic_handle *); 134 STATIC void pccbb_pcmcia_detach_card(struct pcic_handle *, int); 135 STATIC void pccbb_pcmcia_deactivate_card(struct pcic_handle *); 136 #endif 137 138 STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int); 139 STATIC int pccbb_power(struct pccbb_softc *sc, int); 140 STATIC int pccbb_power_ct(cardbus_chipset_tag_t, int); 141 STATIC int pccbb_cardenable(struct pccbb_softc * sc, int function); 142 #if !rbus 143 static int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 144 static int pccbb_io_close(cardbus_chipset_tag_t, int); 145 static int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 146 static int pccbb_mem_close(cardbus_chipset_tag_t, int); 147 #endif /* !rbus */ 148 static void *pccbb_intr_establish(struct pccbb_softc *, int irq, 149 int level, int (*ih) (void *), void *sc); 150 static void pccbb_intr_disestablish(struct pccbb_softc *, void *ih); 151 152 static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t, int irq, 153 int level, int (*ih) (void *), void *sc); 154 static void pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih); 155 156 static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t, int, int); 157 static void pccbb_free_tag(cardbus_chipset_tag_t, cardbustag_t); 158 static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t, cardbustag_t, int); 159 static void pccbb_conf_write(cardbus_chipset_tag_t, cardbustag_t, int, 160 cardbusreg_t); 161 static void pccbb_chipinit(struct pccbb_softc *); 162 static void pccbb_intrinit(struct pccbb_softc *); 163 164 STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 165 struct pcmcia_mem_handle *); 166 STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t, 167 struct pcmcia_mem_handle *); 168 STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 169 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *); 170 STATIC void pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t, int); 171 STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 172 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 173 STATIC void pccbb_pcmcia_io_free(pcmcia_chipset_handle_t, 174 struct pcmcia_io_handle *); 175 STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 176 bus_size_t, struct pcmcia_io_handle *, int *); 177 STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t, int); 178 STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t, 179 struct pcmcia_function *, int, int (*)(void *), void *); 180 STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t, void *); 181 STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t); 182 STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t); 183 STATIC void pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t, int); 184 STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch); 185 186 static int pccbb_pcmcia_wait_ready(struct pcic_handle *); 187 static void pccbb_pcmcia_delay(struct pcic_handle *, int, const char *); 188 189 static void pccbb_pcmcia_do_io_map(struct pcic_handle *, int); 190 static void pccbb_pcmcia_do_mem_map(struct pcic_handle *, int); 191 192 /* bus-space allocation and deallocation functions */ 193 #if rbus 194 195 static int pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t, rbus_tag_t, 196 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 197 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp); 198 static int pccbb_rbus_cb_space_free(cardbus_chipset_tag_t, rbus_tag_t, 199 bus_space_handle_t, bus_size_t); 200 201 #endif /* rbus */ 202 203 #if rbus 204 205 static int pccbb_open_win(struct pccbb_softc *, bus_space_tag_t, 206 bus_addr_t, bus_size_t, bus_space_handle_t, int flags); 207 static int pccbb_close_win(struct pccbb_softc *, bus_space_tag_t, 208 bus_space_handle_t, bus_size_t); 209 static int pccbb_winlist_insert(struct pccbb_win_chain_head *, bus_addr_t, 210 bus_size_t, bus_space_handle_t, int); 211 static int pccbb_winlist_delete(struct pccbb_win_chain_head *, 212 bus_space_handle_t, bus_size_t); 213 static void pccbb_winset(bus_addr_t align, struct pccbb_softc *, 214 bus_space_tag_t); 215 void pccbb_winlist_show(struct pccbb_win_chain *); 216 217 #endif /* rbus */ 218 219 /* for config_defer */ 220 static void pccbb_pci_callback(device_t); 221 222 static bool pccbb_suspend(device_t PMF_FN_PROTO); 223 static bool pccbb_resume(device_t PMF_FN_PROTO); 224 225 #if defined SHOW_REGS 226 static void cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, 227 bus_space_tag_t memt, bus_space_handle_t memh); 228 #endif 229 230 CFATTACH_DECL(cbb_pci, sizeof(struct pccbb_softc), 231 pcicbbmatch, pccbbattach, pccbbdetach, NULL); 232 233 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 234 pccbb_pcmcia_mem_alloc, 235 pccbb_pcmcia_mem_free, 236 pccbb_pcmcia_mem_map, 237 pccbb_pcmcia_mem_unmap, 238 pccbb_pcmcia_io_alloc, 239 pccbb_pcmcia_io_free, 240 pccbb_pcmcia_io_map, 241 pccbb_pcmcia_io_unmap, 242 pccbb_pcmcia_intr_establish, 243 pccbb_pcmcia_intr_disestablish, 244 pccbb_pcmcia_socket_enable, 245 pccbb_pcmcia_socket_disable, 246 pccbb_pcmcia_socket_settype, 247 pccbb_pcmcia_card_detect 248 }; 249 250 #if rbus 251 static struct cardbus_functions pccbb_funcs = { 252 pccbb_rbus_cb_space_alloc, 253 pccbb_rbus_cb_space_free, 254 pccbb_cb_intr_establish, 255 pccbb_cb_intr_disestablish, 256 pccbb_ctrl, 257 pccbb_power_ct, 258 pccbb_make_tag, 259 pccbb_free_tag, 260 pccbb_conf_read, 261 pccbb_conf_write, 262 }; 263 #else 264 static struct cardbus_functions pccbb_funcs = { 265 pccbb_ctrl, 266 pccbb_power_ct, 267 pccbb_mem_open, 268 pccbb_mem_close, 269 pccbb_io_open, 270 pccbb_io_close, 271 pccbb_cb_intr_establish, 272 pccbb_cb_intr_disestablish, 273 pccbb_make_tag, 274 pccbb_conf_read, 275 pccbb_conf_write, 276 }; 277 #endif 278 279 int 280 pcicbbmatch(device_t parent, struct cfdata *match, void *aux) 281 { 282 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 283 284 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 285 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 286 PCI_INTERFACE(pa->pa_class) == 0) { 287 return 1; 288 } 289 290 return 0; 291 } 292 293 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 294 | ((prod) << PCI_PRODUCT_SHIFT)) 295 296 const struct yenta_chipinfo { 297 pcireg_t yc_id; /* vendor tag | product tag */ 298 int yc_chiptype; 299 int yc_flags; 300 } yc_chipsets[] = { 301 /* Texas Instruments chips */ 302 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 303 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 304 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 305 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 306 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI125X, 307 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 308 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 309 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 310 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 311 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 312 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 313 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 314 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI125X, 315 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 316 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI125X, 317 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 318 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 319 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 320 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 321 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 322 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI1420, 323 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 324 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI125X, 325 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 326 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 327 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 328 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1520), CB_TI12XX, 329 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 330 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4410YENTA), CB_TI12XX, 331 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 332 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4520YENTA), CB_TI12XX, 333 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 334 335 /* Ricoh chips */ 336 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 337 PCCBB_PCMCIA_MEM_32}, 338 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 339 PCCBB_PCMCIA_MEM_32}, 340 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 341 PCCBB_PCMCIA_MEM_32}, 342 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 343 PCCBB_PCMCIA_MEM_32}, 344 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 345 PCCBB_PCMCIA_MEM_32}, 346 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 347 PCCBB_PCMCIA_MEM_32}, 348 349 /* Toshiba products */ 350 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 351 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 352 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 353 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 354 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 355 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 356 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 357 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 358 359 /* Cirrus Logic products */ 360 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 361 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 362 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 363 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 364 365 /* sentinel, or Generic chip */ 366 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 367 }; 368 369 static int 370 cb_chipset(u_int32_t pci_id, int *flagp) 371 { 372 const struct yenta_chipinfo *yc; 373 374 /* Loop over except the last default entry. */ 375 for (yc = yc_chipsets; yc < yc_chipsets + 376 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 377 if (pci_id == yc->yc_id) 378 break; 379 380 if (flagp != NULL) 381 *flagp = yc->yc_flags; 382 383 return (yc->yc_chiptype); 384 } 385 386 void 387 pccbbattach(device_t parent, device_t self, void *aux) 388 { 389 struct pccbb_softc *sc = device_private(self); 390 struct pci_attach_args *pa = aux; 391 pci_chipset_tag_t pc = pa->pa_pc; 392 pcireg_t busreg, reg, sock_base; 393 bus_addr_t sockbase; 394 char devinfo[256]; 395 int flags; 396 397 #ifdef __HAVE_PCCBB_ATTACH_HOOK 398 pccbb_attach_hook(parent, self, pa); 399 #endif 400 401 callout_init(&sc->sc_insert_ch, 0); 402 callout_setfunc(&sc->sc_insert_ch, pci113x_insert, sc); 403 404 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 405 406 aprint_naive("\n"); 407 408 pci_devinfo(pa->pa_id, 0, 0, devinfo, sizeof(devinfo)); 409 aprint_normal(": %s (rev. 0x%02x)", devinfo, 410 PCI_REVISION(pa->pa_class)); 411 DPRINTF((" (chipflags %x)", flags)); 412 aprint_normal("\n"); 413 414 TAILQ_INIT(&sc->sc_memwindow); 415 TAILQ_INIT(&sc->sc_iowindow); 416 417 #if rbus 418 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 419 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 420 421 #if 0 422 printf("pa->pa_memt: %08x vs rbus_mem->rb_bt: %08x\n", 423 pa->pa_memt, sc->sc_rbus_memt->rb_bt); 424 #endif 425 #endif /* rbus */ 426 427 sc->sc_flags &= ~CBB_MEMHMAPPED; 428 429 /* 430 * MAP socket registers and ExCA registers on memory-space 431 * When no valid address is set on socket base registers (on pci 432 * config space), get it not polite way. 433 */ 434 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 435 436 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 437 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 438 /* The address must be valid. */ 439 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 440 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, &sc->sc_base_size)) { 441 aprint_error_dev(&sc->sc_dev, 442 "can't map socket base address 0x%lx\n", 443 (unsigned long)sock_base); 444 /* 445 * I think it's funny: socket base registers must be 446 * mapped on memory space, but ... 447 */ 448 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 449 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 450 &sc->sc_base_size)) { 451 aprint_error_dev(&sc->sc_dev, 452 "can't map socket base address" 453 " 0x%lx: io mode\n", 454 (unsigned long)sockbase); 455 /* give up... allocate reg space via rbus. */ 456 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 457 } else 458 sc->sc_flags |= CBB_MEMHMAPPED; 459 } else { 460 DPRINTF(("%s: socket base address 0x%lx\n", 461 device_xname(&sc->sc_dev), 462 (unsigned long)sockbase)); 463 sc->sc_flags |= CBB_MEMHMAPPED; 464 } 465 } 466 467 sc->sc_mem_start = 0; /* XXX */ 468 sc->sc_mem_end = 0xffffffff; /* XXX */ 469 470 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 471 472 /* pccbb_machdep.c end */ 473 474 #if defined CBB_DEBUG 475 { 476 static const char *intrname[] = { "NON", "A", "B", "C", "D" }; 477 aprint_debug_dev(&sc->sc_dev, "intrpin %s, intrtag %d\n", 478 intrname[pa->pa_intrpin], pa->pa_intrline); 479 } 480 #endif 481 482 /* setup softc */ 483 sc->sc_pc = pc; 484 sc->sc_iot = pa->pa_iot; 485 sc->sc_memt = pa->pa_memt; 486 sc->sc_dmat = pa->pa_dmat; 487 sc->sc_tag = pa->pa_tag; 488 sc->sc_function = pa->pa_function; 489 490 memcpy(&sc->sc_pa, pa, sizeof(*pa)); 491 492 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 493 494 /* Disable legacy register mapping. */ 495 switch (sc->sc_chipset) { 496 case CB_RX5C46X: /* fallthrough */ 497 #if 0 498 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 499 case CB_RX5C47X: 500 #endif 501 /* 502 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 503 * cannot be disabled by substituting 0 into PCI_LEGACY 504 * register. Ricoh CardBus bridges have special bits on Bridge 505 * control reg (addr 0x3e on PCI config space). 506 */ 507 reg = pci_conf_read(pc, pa->pa_tag, PCI_BRIDGE_CONTROL_REG); 508 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 509 pci_conf_write(pc, pa->pa_tag, PCI_BRIDGE_CONTROL_REG, reg); 510 break; 511 512 default: 513 /* XXX I don't know proper way to kill legacy I/O. */ 514 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 515 break; 516 } 517 518 if (!pmf_device_register(self, pccbb_suspend, pccbb_resume)) 519 aprint_error_dev(self, "couldn't establish power handler\n"); 520 521 config_defer(self, pccbb_pci_callback); 522 } 523 524 int 525 pccbbdetach(device_t self, int flags) 526 { 527 struct pccbb_softc *sc = device_private(self); 528 pci_chipset_tag_t pc = sc->sc_pa.pa_pc; 529 bus_space_tag_t bmt = sc->sc_base_memt; 530 bus_space_handle_t bmh = sc->sc_base_memh; 531 uint32_t sockmask; 532 int rc; 533 534 if ((rc = config_detach_children(self, flags)) != 0) 535 return rc; 536 537 if (!LIST_EMPTY(&sc->sc_pil)) { 538 panic("%s: interrupt handlers still registered", 539 device_xname(&sc->sc_dev)); 540 return EBUSY; 541 } 542 543 if (sc->sc_ih != NULL) { 544 pci_intr_disestablish(pc, sc->sc_ih); 545 sc->sc_ih = NULL; 546 } 547 548 /* CSC Interrupt: turn off card detect and power cycle interrupts */ 549 sockmask = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 550 sockmask &= ~(CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | 551 CB_SOCKET_MASK_POWER); 552 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, sockmask); 553 /* reset interrupt */ 554 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 555 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 556 557 switch (sc->sc_flags & (CBB_MEMHMAPPED|CBB_SPECMAPPED)) { 558 case CBB_MEMHMAPPED: 559 bus_space_unmap(bmt, bmh, sc->sc_base_size); 560 break; 561 case CBB_MEMHMAPPED|CBB_SPECMAPPED: 562 #if rbus 563 { 564 pcireg_t sockbase; 565 566 sockbase = pci_conf_read(pc, sc->sc_tag, PCI_SOCKBASE); 567 rbus_space_free(sc->sc_rbus_memt, bmh, 0x1000, 568 NULL); 569 } 570 #else 571 bus_space_free(bmt, bmh, 0x1000); 572 #endif 573 } 574 sc->sc_flags &= ~(CBB_MEMHMAPPED|CBB_SPECMAPPED); 575 576 if (!TAILQ_EMPTY(&sc->sc_iowindow)) 577 aprint_error_dev(self, "i/o windows not empty"); 578 if (!TAILQ_EMPTY(&sc->sc_memwindow)) 579 aprint_error_dev(self, "memory windows not empty"); 580 581 callout_stop(&sc->sc_insert_ch); 582 callout_destroy(&sc->sc_insert_ch); 583 return 0; 584 } 585 586 /* 587 * static void pccbb_pci_callback(device_t self) 588 * 589 * The actual attach routine: get memory space for YENTA register 590 * space, setup YENTA register and route interrupt. 591 * 592 * This function should be deferred because this device may obtain 593 * memory space dynamically. This function must avoid obtaining 594 * memory area which has already kept for another device. 595 */ 596 static void 597 pccbb_pci_callback(device_t self) 598 { 599 struct pccbb_softc *sc = device_private(self); 600 pci_chipset_tag_t pc = sc->sc_pc; 601 bus_addr_t sockbase; 602 struct cbslot_attach_args cba; 603 struct pcmciabus_attach_args paa; 604 struct cardslot_attach_args caa; 605 struct cardslot_softc *csc; 606 607 if (!(sc->sc_flags & CBB_MEMHMAPPED)) { 608 /* The socket registers aren't mapped correctly. */ 609 #if rbus 610 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 611 (sc->sc_chipset == CB_RX5C47X 612 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 613 0, &sockbase, &sc->sc_base_memh)) { 614 return; 615 } 616 sc->sc_base_memt = sc->sc_memt; 617 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 618 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 619 device_xname(&sc->sc_dev), (unsigned long)sockbase, 620 (unsigned long)pci_conf_read(pc, sc->sc_tag, 621 PCI_SOCKBASE))); 622 #else 623 sc->sc_base_memt = sc->sc_memt; 624 #if !defined CBB_PCI_BASE 625 #define CBB_PCI_BASE 0x20000000 626 #endif 627 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 628 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 629 /* cannot allocate memory space */ 630 return; 631 } 632 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 633 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 634 device_xname(&sc->sc_dev), (unsigned long)sock_base, 635 (unsigned long)pci_conf_read(pc, 636 sc->sc_tag, PCI_SOCKBASE))); 637 #endif 638 sc->sc_flags |= CBB_MEMHMAPPED; 639 } 640 641 /* clear data structure for child device interrupt handlers */ 642 LIST_INIT(&sc->sc_pil); 643 644 /* bus bridge initialization */ 645 pccbb_chipinit(sc); 646 647 sc->sc_pil_intr_enable = 1; 648 649 { 650 u_int32_t sockstat; 651 652 sockstat = bus_space_read_4(sc->sc_base_memt, 653 sc->sc_base_memh, CB_SOCKET_STAT); 654 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 655 sc->sc_flags |= CBB_CARDEXIST; 656 } 657 } 658 659 /* 660 * attach cardbus 661 */ 662 { 663 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 664 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 665 666 /* initialize cbslot_attach */ 667 cba.cba_busname = "cardbus"; 668 cba.cba_iot = sc->sc_iot; 669 cba.cba_memt = sc->sc_memt; 670 cba.cba_dmat = sc->sc_dmat; 671 cba.cba_bus = (busreg >> 8) & 0x0ff; 672 cba.cba_cc = (void *)sc; 673 cba.cba_cf = &pccbb_funcs; 674 cba.cba_intrline = sc->sc_pa.pa_intrline; 675 676 #if rbus 677 cba.cba_rbus_iot = sc->sc_rbus_iot; 678 cba.cba_rbus_memt = sc->sc_rbus_memt; 679 #endif 680 681 cba.cba_cacheline = PCI_CACHELINE(bhlc); 682 cba.cba_max_lattimer = PCI_LATTIMER(bhlc); 683 684 aprint_verbose_dev(&sc->sc_dev, 685 "cacheline 0x%x lattimer 0x%x\n", 686 cba.cba_cacheline, 687 cba.cba_max_lattimer); 688 aprint_verbose_dev(&sc->sc_dev, "bhlc 0x%x\n", bhlc); 689 #if defined SHOW_REGS 690 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 691 sc->sc_base_memh); 692 #endif 693 } 694 695 pccbb_pcmcia_attach_setup(sc, &paa); 696 caa.caa_cb_attach = NULL; 697 if (cba.cba_bus == 0) 698 aprint_error_dev(&sc->sc_dev, 699 "secondary bus number uninitialized; try PCI_BUS_FIXUP\n"); 700 else 701 caa.caa_cb_attach = &cba; 702 caa.caa_16_attach = &paa; 703 caa.caa_ph = &sc->sc_pcmcia_h; 704 705 pccbb_intrinit(sc); 706 707 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 708 DPRINTF(("%s: found cardslot\n", __func__)); 709 sc->sc_csc = csc; 710 } 711 712 return; 713 } 714 715 716 717 718 719 /* 720 * static void pccbb_chipinit(struct pccbb_softc *sc) 721 * 722 * This function initialize YENTA chip registers listed below: 723 * 1) PCI command reg, 724 * 2) PCI and CardBus latency timer, 725 * 3) route PCI interrupt, 726 * 4) close all memory and io windows. 727 * 5) turn off bus power. 728 * 6) card detect and power cycle interrupts on. 729 * 7) clear interrupt 730 */ 731 static void 732 pccbb_chipinit(struct pccbb_softc *sc) 733 { 734 pci_chipset_tag_t pc = sc->sc_pc; 735 pcitag_t tag = sc->sc_tag; 736 bus_space_tag_t bmt = sc->sc_base_memt; 737 bus_space_handle_t bmh = sc->sc_base_memh; 738 pcireg_t bcr, bhlc, cbctl, csr, lscp, mfunc, mrburst, slotctl, sockctl, 739 sysctrl; 740 741 /* 742 * Set PCI command reg. 743 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 744 */ 745 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 746 /* I believe it is harmless. */ 747 csr |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 748 PCI_COMMAND_MASTER_ENABLE); 749 csr |= (PCI_COMMAND_PARITY_ENABLE|PCI_COMMAND_SERR_ENABLE); 750 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 751 752 /* 753 * Set CardBus latency timer. 754 */ 755 lscp = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 756 if (PCI_CB_LATENCY(lscp) < 0x20) { 757 lscp &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 758 lscp |= (0x20 << PCI_CB_LATENCY_SHIFT); 759 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, lscp); 760 } 761 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 762 PCI_CB_LATENCY(lscp), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 763 764 /* 765 * Set PCI latency timer. 766 */ 767 bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG); 768 if (PCI_LATTIMER(bhlc) < 0x10) { 769 bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 770 bhlc |= (0x10 << PCI_LATTIMER_SHIFT); 771 pci_conf_write(pc, tag, PCI_BHLC_REG, bhlc); 772 } 773 DPRINTF(("PCI latency timer 0x%x (%x)\n", 774 PCI_LATTIMER(bhlc), pci_conf_read(pc, tag, PCI_BHLC_REG))); 775 776 777 /* Route functional interrupts to PCI. */ 778 bcr = pci_conf_read(pc, tag, PCI_BRIDGE_CONTROL_REG); 779 bcr |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 780 bcr |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 781 /* assert reset */ 782 bcr |= PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT; 783 /* Set master abort mode to 1, forward SERR# from secondary 784 * to primary, and detect parity errors on secondary. 785 */ 786 bcr |= PCI_BRIDGE_CONTROL_MABRT << PCI_BRIDGE_CONTROL_SHIFT; 787 bcr |= PCI_BRIDGE_CONTROL_SERR << PCI_BRIDGE_CONTROL_SHIFT; 788 bcr |= PCI_BRIDGE_CONTROL_PERE << PCI_BRIDGE_CONTROL_SHIFT; 789 pci_conf_write(pc, tag, PCI_BRIDGE_CONTROL_REG, bcr); 790 791 switch (sc->sc_chipset) { 792 case CB_TI113X: 793 cbctl = pci_conf_read(pc, tag, PCI_CBCTRL); 794 /* This bit is shared, but may read as 0 on some chips, so set 795 it explicitly on both functions. */ 796 cbctl |= PCI113X_CBCTRL_PCI_IRQ_ENA; 797 /* CSC intr enable */ 798 cbctl |= PCI113X_CBCTRL_PCI_CSC; 799 /* functional intr prohibit | prohibit ISA routing */ 800 cbctl &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 801 pci_conf_write(pc, tag, PCI_CBCTRL, cbctl); 802 break; 803 804 case CB_TI1420: 805 sysctrl = pci_conf_read(pc, tag, PCI_SYSCTRL); 806 mrburst = pccbb_burstup 807 ? PCI1420_SYSCTRL_MRBURST : PCI1420_SYSCTRL_MRBURSTDN; 808 if ((sysctrl & PCI1420_SYSCTRL_MRBURST) == mrburst) { 809 printf("%s: %swrite bursts enabled\n", 810 device_xname(&sc->sc_dev), 811 pccbb_burstup ? "read/" : ""); 812 } else if (pccbb_burstup) { 813 printf("%s: enabling read/write bursts\n", 814 device_xname(&sc->sc_dev)); 815 sysctrl |= PCI1420_SYSCTRL_MRBURST; 816 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 817 } else { 818 printf("%s: disabling read bursts, " 819 "enabling write bursts\n", 820 device_xname(&sc->sc_dev)); 821 sysctrl |= PCI1420_SYSCTRL_MRBURSTDN; 822 sysctrl &= ~PCI1420_SYSCTRL_MRBURSTUP; 823 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 824 } 825 /*FALLTHROUGH*/ 826 case CB_TI12XX: 827 /* 828 * Some TI 12xx (and [14][45]xx) based pci cards 829 * sometimes have issues with the MFUNC register not 830 * being initialized due to a bad EEPROM on board. 831 * Laptops that this matters on have this register 832 * properly initialized. 833 * 834 * The TI125X parts have a different register. 835 */ 836 mfunc = pci_conf_read(pc, tag, PCI12XX_MFUNC); 837 if (mfunc == 0) { 838 mfunc &= ~PCI12XX_MFUNC_PIN0; 839 mfunc |= PCI12XX_MFUNC_PIN0_INTA; 840 if ((pci_conf_read(pc, tag, PCI_SYSCTRL) & 841 PCI12XX_SYSCTRL_INTRTIE) == 0) { 842 mfunc &= ~PCI12XX_MFUNC_PIN1; 843 mfunc |= PCI12XX_MFUNC_PIN1_INTB; 844 } 845 pci_conf_write(pc, tag, PCI12XX_MFUNC, mfunc); 846 } 847 /* fallthrough */ 848 849 case CB_TI125X: 850 /* 851 * Disable zoom video. Some machines initialize this 852 * improperly and experience has shown that this helps 853 * prevent strange behavior. 854 */ 855 pci_conf_write(pc, tag, PCI12XX_MMCTRL, 0); 856 857 sysctrl = pci_conf_read(pc, tag, PCI_SYSCTRL); 858 sysctrl |= PCI12XX_SYSCTRL_VCCPROT; 859 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 860 cbctl = pci_conf_read(pc, tag, PCI_CBCTRL); 861 cbctl |= PCI12XX_CBCTRL_CSC; 862 pci_conf_write(pc, tag, PCI_CBCTRL, cbctl); 863 break; 864 865 case CB_TOPIC95B: 866 sockctl = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 867 sockctl |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 868 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, sockctl); 869 slotctl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 870 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 871 device_xname(&sc->sc_dev), slotctl)); 872 slotctl |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 873 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 874 slotctl &= ~TOPIC_SLOT_CTRL_SWDETECT; 875 DPRINTF(("0x%x\n", slotctl)); 876 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slotctl); 877 break; 878 879 case CB_TOPIC97: 880 slotctl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 881 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 882 device_xname(&sc->sc_dev), slotctl)); 883 slotctl |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 884 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 885 slotctl &= ~TOPIC_SLOT_CTRL_SWDETECT; 886 slotctl |= TOPIC97_SLOT_CTRL_PCIINT; 887 slotctl &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 888 DPRINTF(("0x%x\n", slotctl)); 889 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slotctl); 890 /* make sure to assert LV card support bits */ 891 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 892 0x800 + 0x3e, 893 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 894 0x800 + 0x3e) | 0x03); 895 break; 896 } 897 898 /* Close all memory and I/O windows. */ 899 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 900 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 901 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 902 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 903 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 904 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 905 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 906 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 907 908 /* reset 16-bit pcmcia bus */ 909 bus_space_write_1(bmt, bmh, 0x800 + PCIC_INTR, 910 bus_space_read_1(bmt, bmh, 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 911 912 /* turn off power */ 913 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 914 } 915 916 static void 917 pccbb_intrinit(struct pccbb_softc *sc) 918 { 919 pcireg_t sockmask; 920 const char *intrstr = NULL; 921 pci_intr_handle_t ih; 922 pci_chipset_tag_t pc = sc->sc_pc; 923 bus_space_tag_t bmt = sc->sc_base_memt; 924 bus_space_handle_t bmh = sc->sc_base_memh; 925 926 /* Map and establish the interrupt. */ 927 if (pci_intr_map(&sc->sc_pa, &ih)) { 928 aprint_error_dev(&sc->sc_dev, "couldn't map interrupt\n"); 929 return; 930 } 931 intrstr = pci_intr_string(pc, ih); 932 933 /* 934 * XXX pccbbintr should be called under the priority lower 935 * than any other hard interupts. 936 */ 937 KASSERT(sc->sc_ih == NULL); 938 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 939 940 if (sc->sc_ih == NULL) { 941 aprint_error_dev(&sc->sc_dev, "couldn't establish interrupt"); 942 if (intrstr != NULL) 943 aprint_error(" at %s\n", intrstr); 944 else 945 aprint_error("\n"); 946 return; 947 } 948 949 aprint_normal_dev(&sc->sc_dev, "interrupting at %s\n", intrstr); 950 951 /* CSC Interrupt: Card detect and power cycle interrupts on */ 952 sockmask = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 953 sockmask |= CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | 954 CB_SOCKET_MASK_POWER; 955 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, sockmask); 956 /* reset interrupt */ 957 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 958 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 959 } 960 961 /* 962 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 963 * struct pcmciabus_attach_args *paa) 964 * 965 * This function attaches 16-bit PCcard bus. 966 */ 967 STATIC void 968 pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 969 struct pcmciabus_attach_args *paa) 970 { 971 struct pcic_handle *ph = &sc->sc_pcmcia_h; 972 #if rbus 973 rbus_tag_t rb; 974 #endif 975 976 /* initialize pcmcia part in pccbb_softc */ 977 ph->ph_parent = &sc->sc_dev; 978 ph->sock = sc->sc_function; 979 ph->flags = 0; 980 ph->shutdown = 0; 981 ph->ih_irq = sc->sc_pa.pa_intrline; 982 ph->ph_bus_t = sc->sc_base_memt; 983 ph->ph_bus_h = sc->sc_base_memh; 984 ph->ph_read = pccbb_pcmcia_read; 985 ph->ph_write = pccbb_pcmcia_write; 986 sc->sc_pct = &pccbb_pcmcia_funcs; 987 988 /* 989 * We need to do a few things here: 990 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 991 * setting the IRQ numbers to 0. 992 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 993 * routing of CSC interrupts (e.g. card removal) to PCI while in 994 * PCMCIA mode. We just leave this set all the time. 995 * 3) Enable card insertion/removal interrupts in case the chip also 996 * needs that while in PCMCIA mode. 997 * 4) Clear any pending CSC interrupt. 998 */ 999 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE); 1000 if (sc->sc_chipset == CB_TI113X) { 1001 Pcic_write(ph, PCIC_CSC_INTR, 0); 1002 } else { 1003 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 1004 Pcic_read(ph, PCIC_CSC); 1005 } 1006 1007 /* initialize pcmcia bus attachment */ 1008 paa->paa_busname = "pcmcia"; 1009 paa->pct = sc->sc_pct; 1010 paa->pch = ph; 1011 paa->iobase = 0; /* I don't use them */ 1012 paa->iosize = 0; 1013 #if rbus 1014 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 1015 paa->iobase = rb->rb_start + rb->rb_offset; 1016 paa->iosize = rb->rb_end - rb->rb_start; 1017 #endif 1018 1019 return; 1020 } 1021 1022 #if 0 1023 STATIC void 1024 pccbb_pcmcia_attach_card(struct pcic_handle *ph) 1025 { 1026 if (ph->flags & PCIC_FLAG_CARDP) { 1027 panic("pccbb_pcmcia_attach_card: already attached"); 1028 } 1029 1030 /* call the MI attach function */ 1031 pcmcia_card_attach(ph->pcmcia); 1032 1033 ph->flags |= PCIC_FLAG_CARDP; 1034 } 1035 1036 STATIC void 1037 pccbb_pcmcia_detach_card(struct pcic_handle *ph, int flags) 1038 { 1039 if (!(ph->flags & PCIC_FLAG_CARDP)) { 1040 panic("pccbb_pcmcia_detach_card: already detached"); 1041 } 1042 1043 ph->flags &= ~PCIC_FLAG_CARDP; 1044 1045 /* call the MI detach function */ 1046 pcmcia_card_detach(ph->pcmcia, flags); 1047 } 1048 #endif 1049 1050 /* 1051 * int pccbbintr(arg) 1052 * void *arg; 1053 * This routine handles the interrupt from Yenta PCI-CardBus bridge 1054 * itself. 1055 */ 1056 int 1057 pccbbintr(void *arg) 1058 { 1059 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1060 u_int32_t sockevent, sockstate; 1061 bus_space_tag_t memt = sc->sc_base_memt; 1062 bus_space_handle_t memh = sc->sc_base_memh; 1063 struct pcic_handle *ph = &sc->sc_pcmcia_h; 1064 1065 if (!device_has_power(&sc->sc_dev)) 1066 return 0; 1067 1068 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 1069 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 1070 Pcic_read(ph, PCIC_CSC); 1071 1072 if (sockevent != 0) { 1073 aprint_debug("%s: enter sockevent %" PRIx32 "\n", __func__, 1074 sockevent); 1075 } 1076 1077 /* Sometimes a change of CSTSCHG# accompanies the first 1078 * interrupt from an Atheros WLAN. That generates a 1079 * CB_SOCKET_EVENT_CSTS event on the bridge. The event 1080 * isn't interesting to pccbb(4), so we used to ignore the 1081 * interrupt. Now, let the child devices try to handle 1082 * the interrupt, instead. The Atheros NIC produces 1083 * interrupts more reliably, now: used to be that it would 1084 * only interrupt if the driver avoided powering down the 1085 * NIC's cardslot, and then the NIC would only work after 1086 * it was reset a second time. 1087 */ 1088 if (sockevent == 0 || 1089 (sockevent & ~(CB_SOCKET_EVENT_POWER|CB_SOCKET_EVENT_CD)) != 0) { 1090 /* This intr is not for me: it may be for my child devices. */ 1091 if (sc->sc_pil_intr_enable) { 1092 return pccbbintr_function(sc); 1093 } else { 1094 return 0; 1095 } 1096 } 1097 1098 if (sockevent & CB_SOCKET_EVENT_CD) { 1099 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1100 if (0x00 != (sockstate & CB_SOCKET_STAT_CD)) { 1101 /* A card should be removed. */ 1102 if (sc->sc_flags & CBB_CARDEXIST) { 1103 DPRINTF(("%s: 0x%08x", 1104 device_xname(&sc->sc_dev), sockevent)); 1105 DPRINTF((" card removed, 0x%08x\n", sockstate)); 1106 sc->sc_flags &= ~CBB_CARDEXIST; 1107 if (sc->sc_csc->sc_status & 1108 CARDSLOT_STATUS_CARD_16) { 1109 #if 0 1110 struct pcic_handle *ph = 1111 &sc->sc_pcmcia_h; 1112 1113 pcmcia_card_deactivate(ph->pcmcia); 1114 pccbb_pcmcia_socket_disable(ph); 1115 pccbb_pcmcia_detach_card(ph, 1116 DETACH_FORCE); 1117 #endif 1118 cardslot_event_throw(sc->sc_csc, 1119 CARDSLOT_EVENT_REMOVAL_16); 1120 } else if (sc->sc_csc->sc_status & 1121 CARDSLOT_STATUS_CARD_CB) { 1122 /* Cardbus intr removed */ 1123 cardslot_event_throw(sc->sc_csc, 1124 CARDSLOT_EVENT_REMOVAL_CB); 1125 } 1126 } else if (sc->sc_flags & CBB_INSERTING) { 1127 sc->sc_flags &= ~CBB_INSERTING; 1128 callout_stop(&sc->sc_insert_ch); 1129 } 1130 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 1131 /* 1132 * The pccbbintr may called from powerdown hook when 1133 * the system resumed, to detect the card 1134 * insertion/removal during suspension. 1135 */ 1136 (sc->sc_flags & CBB_CARDEXIST) == 0) { 1137 if (sc->sc_flags & CBB_INSERTING) { 1138 callout_stop(&sc->sc_insert_ch); 1139 } 1140 callout_schedule(&sc->sc_insert_ch, hz / 5); 1141 sc->sc_flags |= CBB_INSERTING; 1142 } 1143 } 1144 1145 /* XXX sockevent == 9 does occur in the wild. handle it. */ 1146 if (sockevent & CB_SOCKET_EVENT_POWER) { 1147 DPRINTF(("Powercycling because of socket event\n")); 1148 /* XXX: Does not happen when attaching a 16-bit card */ 1149 sc->sc_pwrcycle++; 1150 wakeup(&sc->sc_pwrcycle); 1151 } 1152 1153 return (1); 1154 } 1155 1156 /* 1157 * static int pccbbintr_function(struct pccbb_softc *sc) 1158 * 1159 * This function calls each interrupt handler registered at the 1160 * bridge. The interrupt handlers are called in registered order. 1161 */ 1162 static int 1163 pccbbintr_function(struct pccbb_softc *sc) 1164 { 1165 int retval = 0, val; 1166 struct pccbb_intrhand_list *pil; 1167 int s; 1168 1169 LIST_FOREACH(pil, &sc->sc_pil, pil_next) { 1170 s = splraiseipl(pil->pil_icookie); 1171 val = (*pil->pil_func)(pil->pil_arg); 1172 splx(s); 1173 1174 retval = retval == 1 ? 1 : 1175 retval == 0 ? val : val != 0 ? val : retval; 1176 } 1177 1178 return retval; 1179 } 1180 1181 static void 1182 pci113x_insert(void *arg) 1183 { 1184 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1185 u_int32_t sockevent, sockstate; 1186 1187 if (!(sc->sc_flags & CBB_INSERTING)) { 1188 /* We add a card only under inserting state. */ 1189 return; 1190 } 1191 sc->sc_flags &= ~CBB_INSERTING; 1192 1193 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1194 CB_SOCKET_EVENT); 1195 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1196 CB_SOCKET_STAT); 1197 1198 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1199 DPRINTF(("%s: 0x%08x", device_xname(&sc->sc_dev), sockevent)); 1200 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1201 sc->sc_flags |= CBB_CARDEXIST; 1202 /* call pccard interrupt handler here */ 1203 if (sockstate & CB_SOCKET_STAT_16BIT) { 1204 /* 16-bit card found */ 1205 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1206 cardslot_event_throw(sc->sc_csc, 1207 CARDSLOT_EVENT_INSERTION_16); 1208 } else if (sockstate & CB_SOCKET_STAT_CB) { 1209 /* cardbus card found */ 1210 /* cardbus_attach_card(sc->sc_csc); */ 1211 cardslot_event_throw(sc->sc_csc, 1212 CARDSLOT_EVENT_INSERTION_CB); 1213 } else { 1214 /* who are you? */ 1215 } 1216 } else { 1217 callout_schedule(&sc->sc_insert_ch, hz / 10); 1218 } 1219 } 1220 1221 #define PCCBB_PCMCIA_OFFSET 0x800 1222 static u_int8_t 1223 pccbb_pcmcia_read(struct pcic_handle *ph, int reg) 1224 { 1225 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1226 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1227 1228 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1229 PCCBB_PCMCIA_OFFSET + reg); 1230 } 1231 1232 static void 1233 pccbb_pcmcia_write(struct pcic_handle *ph, int reg, u_int8_t val) 1234 { 1235 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1236 val); 1237 1238 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1239 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1240 } 1241 1242 /* 1243 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1244 */ 1245 STATIC int 1246 pccbb_ctrl(cardbus_chipset_tag_t ct, int command) 1247 { 1248 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1249 1250 switch (command) { 1251 case CARDBUS_CD: 1252 if (2 == pccbb_detect_card(sc)) { 1253 int retval = 0; 1254 int status = cb_detect_voltage(sc); 1255 if (PCCARD_VCC_5V & status) { 1256 retval |= CARDBUS_5V_CARD; 1257 } 1258 if (PCCARD_VCC_3V & status) { 1259 retval |= CARDBUS_3V_CARD; 1260 } 1261 if (PCCARD_VCC_XV & status) { 1262 retval |= CARDBUS_XV_CARD; 1263 } 1264 if (PCCARD_VCC_YV & status) { 1265 retval |= CARDBUS_YV_CARD; 1266 } 1267 return retval; 1268 } else { 1269 return 0; 1270 } 1271 case CARDBUS_RESET: 1272 return cb_reset(sc); 1273 case CARDBUS_IO_ENABLE: /* fallthrough */ 1274 case CARDBUS_IO_DISABLE: /* fallthrough */ 1275 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1276 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1277 case CARDBUS_BM_ENABLE: /* fallthrough */ 1278 case CARDBUS_BM_DISABLE: /* fallthrough */ 1279 /* XXX: I think we don't need to call this function below. */ 1280 return pccbb_cardenable(sc, command); 1281 } 1282 1283 return 0; 1284 } 1285 1286 STATIC int 1287 pccbb_power_ct(cardbus_chipset_tag_t ct, int command) 1288 { 1289 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1290 1291 return pccbb_power(sc, command); 1292 } 1293 1294 /* 1295 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1296 * This function returns true when it succeeds and returns false when 1297 * it fails. 1298 */ 1299 STATIC int 1300 pccbb_power(struct pccbb_softc *sc, int command) 1301 { 1302 u_int32_t status, osock_ctrl, sock_ctrl, reg_ctrl; 1303 bus_space_tag_t memt = sc->sc_base_memt; 1304 bus_space_handle_t memh = sc->sc_base_memh; 1305 int on = 0, pwrcycle, s, times; 1306 struct timeval before, after, diff; 1307 1308 DPRINTF(("pccbb_power: %s and %s [0x%x]\n", 1309 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1310 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1311 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1312 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1313 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1314 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1315 "UNKNOWN", 1316 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1317 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1318 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1319 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1320 "UNKNOWN", command)); 1321 1322 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1323 osock_ctrl = sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1324 1325 switch (command & CARDBUS_VCCMASK) { 1326 case CARDBUS_VCC_UC: 1327 break; 1328 case CARDBUS_VCC_5V: 1329 on++; 1330 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1331 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1332 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1333 } else { 1334 aprint_error_dev(&sc->sc_dev, 1335 "BAD voltage request: no 5 V card\n"); 1336 return 0; 1337 } 1338 break; 1339 case CARDBUS_VCC_3V: 1340 on++; 1341 if (CB_SOCKET_STAT_3VCARD & status) { 1342 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1343 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1344 } else { 1345 aprint_error_dev(&sc->sc_dev, 1346 "BAD voltage request: no 3.3 V card\n"); 1347 return 0; 1348 } 1349 break; 1350 case CARDBUS_VCC_0V: 1351 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1352 break; 1353 default: 1354 return 0; /* power NEVER changed */ 1355 } 1356 1357 switch (command & CARDBUS_VPPMASK) { 1358 case CARDBUS_VPP_UC: 1359 break; 1360 case CARDBUS_VPP_0V: 1361 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1362 break; 1363 case CARDBUS_VPP_VCC: 1364 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1365 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1366 break; 1367 case CARDBUS_VPP_12V: 1368 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1369 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1370 break; 1371 } 1372 1373 pwrcycle = sc->sc_pwrcycle; 1374 aprint_debug_dev(&sc->sc_dev, "osock_ctrl %#" PRIx32 1375 " sock_ctrl %#" PRIx32 "\n", osock_ctrl, sock_ctrl); 1376 1377 microtime(&before); 1378 s = splbio(); 1379 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1380 1381 /* 1382 * Wait as long as 200ms for a power-cycle interrupt. If 1383 * interrupts are enabled, but the socket has already 1384 * changed to the desired status, keep waiting for the 1385 * interrupt. "Consuming" the interrupt in this way keeps 1386 * the interrupt from prematurely waking some subsequent 1387 * pccbb_power call. 1388 * 1389 * XXX Not every bridge interrupts on the ->OFF transition. 1390 * XXX That's ok, we will time-out after 200ms. 1391 * 1392 * XXX The power cycle event will never happen when attaching 1393 * XXX a 16-bit card. That's ok, we will time-out after 1394 * XXX 200ms. 1395 */ 1396 for (times = 5; --times >= 0; ) { 1397 if (cold) 1398 DELAY(40 * 1000); 1399 else { 1400 (void)tsleep(&sc->sc_pwrcycle, PWAIT, "pccpwr", 1401 hz / 25); 1402 if (pwrcycle == sc->sc_pwrcycle) 1403 continue; 1404 } 1405 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1406 if ((status & CB_SOCKET_STAT_PWRCYCLE) != 0 && on) 1407 break; 1408 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0 && !on) 1409 break; 1410 } 1411 splx(s); 1412 microtime(&after); 1413 timersub(&after, &before, &diff); 1414 aprint_debug_dev(&sc->sc_dev, "wait took%s %ld.%06lds\n", 1415 (on && times < 0) ? " too long" : "", diff.tv_sec, diff.tv_usec); 1416 1417 /* 1418 * Ok, wait a bit longer for things to settle. 1419 */ 1420 if (on && sc->sc_chipset == CB_TOPIC95B) 1421 delay_ms(100, sc); 1422 1423 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1424 1425 if (on && sc->sc_chipset != CB_TOPIC95B) { 1426 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0) 1427 aprint_error_dev(&sc->sc_dev, "power on failed?\n"); 1428 } 1429 1430 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1431 aprint_error_dev(&sc->sc_dev, 1432 "bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1433 sock_ctrl, status); 1434 aprint_error_dev(&sc->sc_dev, "disabling socket\n"); 1435 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1436 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1437 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1438 status &= ~CB_SOCKET_STAT_BADVCC; 1439 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, status); 1440 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1441 CB_SOCKET_STAT)); 1442 return 0; 1443 } 1444 1445 if (sc->sc_chipset == CB_TOPIC97) { 1446 reg_ctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL); 1447 reg_ctrl &= ~TOPIC97_REG_CTRL_TESTMODE; 1448 if ((command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V) 1449 reg_ctrl &= ~TOPIC97_REG_CTRL_CLKRUN_ENA; 1450 else 1451 reg_ctrl |= TOPIC97_REG_CTRL_CLKRUN_ENA; 1452 pci_conf_write(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL, reg_ctrl); 1453 } 1454 1455 return 1; /* power changed correctly */ 1456 } 1457 1458 #if defined CB_PCMCIA_POLL 1459 struct cb_poll_str { 1460 void *arg; 1461 int (*func)(void *); 1462 int level; 1463 pccard_chipset_tag_t ct; 1464 int count; 1465 struct callout poll_ch; 1466 }; 1467 1468 static struct cb_poll_str cb_poll[10]; 1469 static int cb_poll_n = 0; 1470 1471 static void cb_pcmcia_poll(void *arg); 1472 1473 static void 1474 cb_pcmcia_poll(void *arg) 1475 { 1476 struct cb_poll_str *poll = arg; 1477 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1478 struct pccbb_softc *sc = psc->cpc_parent; 1479 int s; 1480 u_int32_t spsr; /* socket present-state reg */ 1481 1482 callout_reset(&poll->poll_ch, hz / 10, cb_pcmcia_poll, poll); 1483 switch (poll->level) { 1484 case IPL_NET: 1485 s = splnet(); 1486 break; 1487 case IPL_BIO: 1488 s = splbio(); 1489 break; 1490 case IPL_TTY: /* fallthrough */ 1491 default: 1492 s = spltty(); 1493 break; 1494 } 1495 1496 spsr = 1497 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1498 CB_SOCKET_STAT); 1499 1500 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1501 if (!(spsr & 0x40)) { /* CINT low */ 1502 #else 1503 if (1) { 1504 #endif 1505 if ((*poll->func) (poll->arg) == 1) { 1506 ++poll->count; 1507 printf("intr: reported from poller, 0x%x\n", spsr); 1508 #if defined LEVEL2 1509 } else { 1510 printf("intr: miss! 0x%x\n", spsr); 1511 #endif 1512 } 1513 } 1514 splx(s); 1515 } 1516 #endif /* defined CB_PCMCIA_POLL */ 1517 1518 /* 1519 * static int pccbb_detect_card(struct pccbb_softc *sc) 1520 * return value: 0 if no card exists. 1521 * 1 if 16-bit card exists. 1522 * 2 if cardbus card exists. 1523 */ 1524 static int 1525 pccbb_detect_card(struct pccbb_softc *sc) 1526 { 1527 bus_space_handle_t base_memh = sc->sc_base_memh; 1528 bus_space_tag_t base_memt = sc->sc_base_memt; 1529 u_int32_t sockstat = 1530 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1531 int retval = 0; 1532 1533 /* CD1 and CD2 asserted */ 1534 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1535 /* card must be present */ 1536 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1537 /* NOTACARD DEASSERTED */ 1538 if (CB_SOCKET_STAT_CB & sockstat) { 1539 /* CardBus mode */ 1540 retval = 2; 1541 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1542 /* 16-bit mode */ 1543 retval = 1; 1544 } 1545 } 1546 } 1547 return retval; 1548 } 1549 1550 /* 1551 * STATIC int cb_reset(struct pccbb_softc *sc) 1552 * This function resets CardBus card. 1553 */ 1554 STATIC int 1555 cb_reset(struct pccbb_softc *sc) 1556 { 1557 /* 1558 * Reset Assert at least 20 ms 1559 * Some machines request longer duration. 1560 */ 1561 int reset_duration = 1562 (sc->sc_chipset == CB_RX5C47X ? 400 : 50); 1563 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1564 aprint_debug("%s: enter bcr %" PRIx32 "\n", __func__, bcr); 1565 1566 /* Reset bit Assert (bit 6 at 0x3E) */ 1567 bcr |= PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT; 1568 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr); 1569 aprint_debug("%s: wrote bcr %" PRIx32 "\n", __func__, bcr); 1570 delay_ms(reset_duration, sc); 1571 1572 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1573 /* Reset bit Deassert (bit 6 at 0x3E) */ 1574 bcr &= ~(PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT); 1575 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, 1576 bcr); 1577 aprint_debug("%s: wrote bcr %" PRIx32 "\n", __func__, bcr); 1578 delay_ms(reset_duration, sc); 1579 aprint_debug("%s: end of delay\n", __func__); 1580 } 1581 /* No card found on the slot. Keep Reset. */ 1582 return 1; 1583 } 1584 1585 /* 1586 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1587 * This function detect card Voltage. 1588 */ 1589 STATIC int 1590 cb_detect_voltage(struct pccbb_softc *sc) 1591 { 1592 u_int32_t psr; /* socket present-state reg */ 1593 bus_space_tag_t iot = sc->sc_base_memt; 1594 bus_space_handle_t ioh = sc->sc_base_memh; 1595 int vol = PCCARD_VCC_UKN; /* set 0 */ 1596 1597 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1598 1599 if (0x400u & psr) { 1600 vol |= PCCARD_VCC_5V; 1601 } 1602 if (0x800u & psr) { 1603 vol |= PCCARD_VCC_3V; 1604 } 1605 1606 return vol; 1607 } 1608 1609 STATIC int 1610 cbbprint(void *aux, const char *pcic) 1611 { 1612 #if 0 1613 struct cbslot_attach_args *cba = aux; 1614 1615 if (cba->cba_slot >= 0) { 1616 aprint_normal(" slot %d", cba->cba_slot); 1617 } 1618 #endif 1619 return UNCONF; 1620 } 1621 1622 /* 1623 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1624 * This function enables and disables the card 1625 */ 1626 STATIC int 1627 pccbb_cardenable(struct pccbb_softc *sc, int function) 1628 { 1629 u_int32_t command = 1630 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1631 1632 DPRINTF(("pccbb_cardenable:")); 1633 switch (function) { 1634 case CARDBUS_IO_ENABLE: 1635 command |= PCI_COMMAND_IO_ENABLE; 1636 break; 1637 case CARDBUS_IO_DISABLE: 1638 command &= ~PCI_COMMAND_IO_ENABLE; 1639 break; 1640 case CARDBUS_MEM_ENABLE: 1641 command |= PCI_COMMAND_MEM_ENABLE; 1642 break; 1643 case CARDBUS_MEM_DISABLE: 1644 command &= ~PCI_COMMAND_MEM_ENABLE; 1645 break; 1646 case CARDBUS_BM_ENABLE: 1647 command |= PCI_COMMAND_MASTER_ENABLE; 1648 break; 1649 case CARDBUS_BM_DISABLE: 1650 command &= ~PCI_COMMAND_MASTER_ENABLE; 1651 break; 1652 default: 1653 return 0; 1654 } 1655 1656 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1657 DPRINTF((" command reg 0x%x\n", command)); 1658 return 1; 1659 } 1660 1661 #if !rbus 1662 static int 1663 pccbb_io_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 1664 { 1665 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1666 int basereg; 1667 int limitreg; 1668 1669 if ((win < 0) || (win > 2)) { 1670 #if defined DIAGNOSTIC 1671 printf("cardbus_io_open: window out of range %d\n", win); 1672 #endif 1673 return 0; 1674 } 1675 1676 basereg = win * 8 + PCI_CB_IOBASE0; 1677 limitreg = win * 8 + PCI_CB_IOLIMIT0; 1678 1679 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1680 start, basereg, end, limitreg)); 1681 1682 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1683 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1684 return 1; 1685 } 1686 1687 /* 1688 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1689 */ 1690 static int 1691 pccbb_io_close(cardbus_chipset_tag_t ct, int win) 1692 { 1693 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1694 int basereg; 1695 int limitreg; 1696 1697 if ((win < 0) || (win > 2)) { 1698 #if defined DIAGNOSTIC 1699 printf("cardbus_io_close: window out of range %d\n", win); 1700 #endif 1701 return 0; 1702 } 1703 1704 basereg = win * 8 + PCI_CB_IOBASE0; 1705 limitreg = win * 8 + PCI_CB_IOLIMIT0; 1706 1707 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1708 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1709 return 1; 1710 } 1711 1712 static int 1713 pccbb_mem_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 1714 { 1715 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1716 int basereg; 1717 int limitreg; 1718 1719 if ((win < 0) || (win > 2)) { 1720 #if defined DIAGNOSTIC 1721 printf("cardbus_mem_open: window out of range %d\n", win); 1722 #endif 1723 return 0; 1724 } 1725 1726 basereg = win * 8 + PCI_CB_MEMBASE0; 1727 limitreg = win * 8 + PCI_CB_MEMLIMIT0; 1728 1729 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1730 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1731 return 1; 1732 } 1733 1734 static int 1735 pccbb_mem_close(cardbus_chipset_tag_t ct, int win) 1736 { 1737 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1738 int basereg; 1739 int limitreg; 1740 1741 if ((win < 0) || (win > 2)) { 1742 #if defined DIAGNOSTIC 1743 printf("cardbus_mem_close: window out of range %d\n", win); 1744 #endif 1745 return 0; 1746 } 1747 1748 basereg = win * 8 + PCI_CB_MEMBASE0; 1749 limitreg = win * 8 + PCI_CB_MEMLIMIT0; 1750 1751 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1752 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1753 return 1; 1754 } 1755 #endif 1756 1757 /* 1758 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1759 * int irq, 1760 * int level, 1761 * int (* func)(void *), 1762 * void *arg) 1763 * 1764 * This function registers an interrupt handler at the bridge, in 1765 * order not to call the interrupt handlers of child devices when 1766 * a card-deletion interrupt occurs. 1767 * 1768 * The arguments irq and level are not used. 1769 */ 1770 static void * 1771 pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, int irq, int level, 1772 int (*func)(void *), void *arg) 1773 { 1774 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1775 1776 return pccbb_intr_establish(sc, irq, level, func, arg); 1777 } 1778 1779 1780 /* 1781 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1782 * void *ih) 1783 * 1784 * This function removes an interrupt handler pointed by ih. 1785 */ 1786 static void 1787 pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih) 1788 { 1789 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1790 1791 pccbb_intr_disestablish(sc, ih); 1792 } 1793 1794 1795 void 1796 pccbb_intr_route(struct pccbb_softc *sc) 1797 { 1798 pcireg_t bcr, cbctrl; 1799 1800 /* initialize bridge intr routing */ 1801 bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1802 bcr &= ~CB_BCR_INTR_IREQ_ENABLE; 1803 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr); 1804 1805 switch (sc->sc_chipset) { 1806 case CB_TI113X: 1807 cbctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1808 /* functional intr enabled */ 1809 cbctrl |= PCI113X_CBCTRL_PCI_INTR; 1810 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, cbctrl); 1811 break; 1812 default: 1813 break; 1814 } 1815 } 1816 1817 /* 1818 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1819 * int irq, 1820 * int level, 1821 * int (* func)(void *), 1822 * void *arg) 1823 * 1824 * This function registers an interrupt handler at the bridge, in 1825 * order not to call the interrupt handlers of child devices when 1826 * a card-deletion interrupt occurs. 1827 * 1828 * The arguments irq is not used because pccbb selects intr vector. 1829 */ 1830 static void * 1831 pccbb_intr_establish(struct pccbb_softc *sc, int irq, int level, 1832 int (*func)(void *), void *arg) 1833 { 1834 struct pccbb_intrhand_list *pil, *newpil; 1835 1836 DPRINTF(("pccbb_intr_establish start. %p\n", LIST_FIRST(&sc->sc_pil))); 1837 1838 if (LIST_EMPTY(&sc->sc_pil)) { 1839 pccbb_intr_route(sc); 1840 } 1841 1842 /* 1843 * Allocate a room for interrupt handler structure. 1844 */ 1845 if (NULL == (newpil = 1846 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1847 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1848 return NULL; 1849 } 1850 1851 newpil->pil_func = func; 1852 newpil->pil_arg = arg; 1853 newpil->pil_icookie = makeiplcookie(level); 1854 1855 if (LIST_EMPTY(&sc->sc_pil)) { 1856 LIST_INSERT_HEAD(&sc->sc_pil, newpil, pil_next); 1857 } else { 1858 for (pil = LIST_FIRST(&sc->sc_pil); 1859 LIST_NEXT(pil, pil_next) != NULL; 1860 pil = LIST_NEXT(pil, pil_next)); 1861 LIST_INSERT_AFTER(pil, newpil, pil_next); 1862 } 1863 1864 DPRINTF(("pccbb_intr_establish add pil. %p\n", 1865 LIST_FIRST(&sc->sc_pil))); 1866 1867 return newpil; 1868 } 1869 1870 /* 1871 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1872 * void *ih) 1873 * 1874 * This function removes an interrupt handler pointed by ih. ih 1875 * should be the value returned by cardbus_intr_establish() or 1876 * NULL. 1877 * 1878 * When ih is NULL, this function will do nothing. 1879 */ 1880 static void 1881 pccbb_intr_disestablish(struct pccbb_softc *sc, void *ih) 1882 { 1883 struct pccbb_intrhand_list *pil; 1884 pcireg_t reg; 1885 1886 DPRINTF(("pccbb_intr_disestablish start. %p\n", 1887 LIST_FIRST(&sc->sc_pil))); 1888 1889 if (ih == NULL) { 1890 /* intr handler is not set */ 1891 DPRINTF(("pccbb_intr_disestablish: no ih\n")); 1892 return; 1893 } 1894 1895 #ifdef DIAGNOSTIC 1896 LIST_FOREACH(pil, &sc->sc_pil, pil_next) { 1897 DPRINTF(("pccbb_intr_disestablish: pil %p\n", pil)); 1898 if (pil == ih) { 1899 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1900 break; 1901 } 1902 } 1903 if (pil == NULL) { 1904 panic("pccbb_intr_disestablish: %s cannot find pil %p", 1905 device_xname(&sc->sc_dev), ih); 1906 } 1907 #endif 1908 1909 pil = (struct pccbb_intrhand_list *)ih; 1910 LIST_REMOVE(pil, pil_next); 1911 free(pil, M_DEVBUF); 1912 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1913 1914 if (LIST_EMPTY(&sc->sc_pil)) { 1915 /* No interrupt handlers */ 1916 1917 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1918 1919 /* stop routing PCI intr */ 1920 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1921 reg |= CB_BCR_INTR_IREQ_ENABLE; 1922 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, reg); 1923 1924 switch (sc->sc_chipset) { 1925 case CB_TI113X: 1926 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1927 /* functional intr disabled */ 1928 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1929 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1930 break; 1931 default: 1932 break; 1933 } 1934 } 1935 } 1936 1937 #if defined SHOW_REGS 1938 static void 1939 cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, bus_space_tag_t memt, 1940 bus_space_handle_t memh) 1941 { 1942 int i; 1943 printf("PCI config regs:"); 1944 for (i = 0; i < 0x50; i += 4) { 1945 if (i % 16 == 0) 1946 printf("\n 0x%02x:", i); 1947 printf(" %08x", pci_conf_read(pc, tag, i)); 1948 } 1949 for (i = 0x80; i < 0xb0; i += 4) { 1950 if (i % 16 == 0) 1951 printf("\n 0x%02x:", i); 1952 printf(" %08x", pci_conf_read(pc, tag, i)); 1953 } 1954 1955 if (memh == 0) { 1956 printf("\n"); 1957 return; 1958 } 1959 1960 printf("\nsocket regs:"); 1961 for (i = 0; i <= 0x10; i += 0x04) 1962 printf(" %08x", bus_space_read_4(memt, memh, i)); 1963 printf("\nExCA regs:"); 1964 for (i = 0; i < 0x08; ++i) 1965 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1966 printf("\n"); 1967 return; 1968 } 1969 #endif 1970 1971 /* 1972 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1973 * int busno, int function) 1974 * This is the function to make a tag to access config space of 1975 * a CardBus Card. It works same as pci_conf_read. 1976 */ 1977 static cardbustag_t 1978 pccbb_make_tag(cardbus_chipset_tag_t cc, int busno, int function) 1979 { 1980 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1981 1982 return pci_make_tag(sc->sc_pc, busno, 0, function); 1983 } 1984 1985 static void 1986 pccbb_free_tag(cardbus_chipset_tag_t cc, cardbustag_t tag) 1987 { 1988 } 1989 1990 /* 1991 * pccbb_conf_read 1992 * 1993 * This is the function to read the config space of a CardBus card. 1994 * It works the same as pci_conf_read(9). 1995 */ 1996 static cardbusreg_t 1997 pccbb_conf_read(cardbus_chipset_tag_t cc, cardbustag_t tag, int offset) 1998 { 1999 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 2000 2001 return pci_conf_read(sc->sc_pc, tag, offset); 2002 } 2003 2004 /* 2005 * pccbb_conf_write 2006 * 2007 * This is the function to write the config space of a CardBus 2008 * card. It works the same as pci_conf_write(9). 2009 */ 2010 static void 2011 pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, int reg, 2012 cardbusreg_t val) 2013 { 2014 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 2015 2016 pci_conf_write(sc->sc_pc, tag, reg, val); 2017 } 2018 2019 #if 0 2020 STATIC int 2021 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 2022 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 2023 int speed, int flags, 2024 bus_space_handle_t * iohp) 2025 #endif 2026 /* 2027 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 2028 * bus_addr_t start, bus_size_t size, 2029 * bus_size_t align, 2030 * struct pcmcia_io_handle *pcihp 2031 * 2032 * This function only allocates I/O region for pccard. This function 2033 * never maps the allocated region to pccard I/O area. 2034 * 2035 * XXX: The interface of this function is not very good, I believe. 2036 */ 2037 STATIC int 2038 pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, 2039 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 2040 { 2041 struct pcic_handle *ph = (struct pcic_handle *)pch; 2042 bus_addr_t ioaddr; 2043 int flags = 0; 2044 bus_space_tag_t iot; 2045 bus_space_handle_t ioh; 2046 bus_addr_t mask; 2047 #if rbus 2048 rbus_tag_t rb; 2049 #endif 2050 if (align == 0) { 2051 align = size; /* XXX: funny??? */ 2052 } 2053 2054 if (start != 0) { 2055 /* XXX: assume all card decode lower 10 bits by its hardware */ 2056 mask = 0x3ff; 2057 /* enforce to use only masked address */ 2058 start &= mask; 2059 } else { 2060 /* 2061 * calculate mask: 2062 * 1. get the most significant bit of size (call it msb). 2063 * 2. compare msb with the value of size. 2064 * 3. if size is larger, shift msb left once. 2065 * 4. obtain mask value to decrement msb. 2066 */ 2067 bus_size_t size_tmp = size; 2068 int shifts = 0; 2069 2070 mask = 1; 2071 while (size_tmp) { 2072 ++shifts; 2073 size_tmp >>= 1; 2074 } 2075 mask = (1 << shifts); 2076 if (mask < size) { 2077 mask <<= 1; 2078 } 2079 --mask; 2080 } 2081 2082 /* 2083 * Allocate some arbitrary I/O space. 2084 */ 2085 2086 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 2087 2088 #if rbus 2089 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 2090 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 2091 return 1; 2092 } 2093 DPRINTF(("pccbb_pcmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2094 (u_long) ioaddr, (u_long) size)); 2095 #else 2096 if (start) { 2097 ioaddr = start; 2098 if (bus_space_map(iot, start, size, 0, &ioh)) { 2099 return 1; 2100 } 2101 DPRINTF(("pccbb_pcmcia_io_alloc map port 0x%lx+0x%lx\n", 2102 (u_long) ioaddr, (u_long) size)); 2103 } else { 2104 flags |= PCMCIA_IO_ALLOCATED; 2105 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 2106 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 2107 size, align, 0, 0, &ioaddr, &ioh)) { 2108 /* No room be able to be get. */ 2109 return 1; 2110 } 2111 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2112 (u_long) ioaddr, (u_long) size)); 2113 } 2114 #endif 2115 2116 pcihp->iot = iot; 2117 pcihp->ioh = ioh; 2118 pcihp->addr = ioaddr; 2119 pcihp->size = size; 2120 pcihp->flags = flags; 2121 2122 return 0; 2123 } 2124 2125 /* 2126 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2127 * struct pcmcia_io_handle *pcihp) 2128 * 2129 * This function only frees I/O region for pccard. 2130 * 2131 * XXX: The interface of this function is not very good, I believe. 2132 */ 2133 void 2134 pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2135 struct pcmcia_io_handle *pcihp) 2136 { 2137 #if !rbus 2138 bus_space_tag_t iot = pcihp->iot; 2139 #endif 2140 bus_space_handle_t ioh = pcihp->ioh; 2141 bus_size_t size = pcihp->size; 2142 2143 #if rbus 2144 struct pccbb_softc *sc = 2145 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 2146 rbus_tag_t rb = sc->sc_rbus_iot; 2147 2148 rbus_space_free(rb, ioh, size, NULL); 2149 #else 2150 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 2151 bus_space_free(iot, ioh, size); 2152 else 2153 bus_space_unmap(iot, ioh, size); 2154 #endif 2155 } 2156 2157 /* 2158 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 2159 * bus_addr_t offset, bus_size_t size, 2160 * struct pcmcia_io_handle *pcihp, 2161 * int *windowp) 2162 * 2163 * This function maps the allocated I/O region to pccard. This function 2164 * never allocates any I/O region for pccard I/O area. I don't 2165 * understand why the original authors of pcmciabus separated alloc and 2166 * map. I believe the two must be unite. 2167 * 2168 * XXX: no wait timing control? 2169 */ 2170 int 2171 pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, bus_addr_t offset, 2172 bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp) 2173 { 2174 struct pcic_handle *ph = (struct pcic_handle *)pch; 2175 bus_addr_t ioaddr = pcihp->addr + offset; 2176 int i, win; 2177 #if defined CBB_DEBUG 2178 static const char *width_names[] = { "dynamic", "io8", "io16" }; 2179 #endif 2180 2181 /* Sanity check I/O handle. */ 2182 2183 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 2184 panic("pccbb_pcmcia_io_map iot is bogus"); 2185 } 2186 2187 /* XXX Sanity check offset/size. */ 2188 2189 win = -1; 2190 for (i = 0; i < PCIC_IO_WINS; i++) { 2191 if ((ph->ioalloc & (1 << i)) == 0) { 2192 win = i; 2193 ph->ioalloc |= (1 << i); 2194 break; 2195 } 2196 } 2197 2198 if (win == -1) { 2199 return 1; 2200 } 2201 2202 *windowp = win; 2203 2204 /* XXX this is pretty gross */ 2205 2206 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2207 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2208 2209 /* XXX wtf is this doing here? */ 2210 2211 #if 0 2212 printf(" port 0x%lx", (u_long) ioaddr); 2213 if (size > 1) { 2214 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2215 } 2216 #endif 2217 2218 ph->io[win].addr = ioaddr; 2219 ph->io[win].size = size; 2220 ph->io[win].width = width; 2221 2222 /* actual dirty register-value changing in the function below. */ 2223 pccbb_pcmcia_do_io_map(ph, win); 2224 2225 return 0; 2226 } 2227 2228 /* 2229 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2230 * 2231 * This function changes register-value to map I/O region for pccard. 2232 */ 2233 static void 2234 pccbb_pcmcia_do_io_map(struct pcic_handle *ph, int win) 2235 { 2236 static u_int8_t pcic_iowidth[3] = { 2237 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2238 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2239 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2240 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2241 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2242 }; 2243 2244 #define PCIC_SIA_START_LOW 0 2245 #define PCIC_SIA_START_HIGH 1 2246 #define PCIC_SIA_STOP_LOW 2 2247 #define PCIC_SIA_STOP_HIGH 3 2248 2249 int regbase_win = 0x8 + win * 0x04; 2250 u_int8_t ioctl, enable; 2251 2252 DPRINTF(("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx " 2253 "width %d\n", win, (unsigned long)ph->io[win].addr, 2254 (unsigned long)ph->io[win].size, ph->io[win].width * 8)); 2255 2256 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2257 ph->io[win].addr & 0xff); 2258 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2259 (ph->io[win].addr >> 8) & 0xff); 2260 2261 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2262 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2263 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2264 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2265 2266 ioctl = Pcic_read(ph, PCIC_IOCTL); 2267 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2268 switch (win) { 2269 case 0: 2270 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2271 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2272 PCIC_IOCTL_IO0_DATASIZE_MASK); 2273 ioctl |= pcic_iowidth[ph->io[win].width]; 2274 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2275 break; 2276 case 1: 2277 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2278 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2279 PCIC_IOCTL_IO1_DATASIZE_MASK); 2280 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2281 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2282 break; 2283 } 2284 Pcic_write(ph, PCIC_IOCTL, ioctl); 2285 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2286 #if defined(CBB_DEBUG) 2287 { 2288 u_int8_t start_low = 2289 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2290 u_int8_t start_high = 2291 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2292 u_int8_t stop_low = 2293 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2294 u_int8_t stop_high = 2295 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2296 printf("pccbb_pcmcia_do_io_map start %02x %02x, " 2297 "stop %02x %02x, ioctl %02x enable %02x\n", 2298 start_low, start_high, stop_low, stop_high, ioctl, enable); 2299 } 2300 #endif 2301 } 2302 2303 /* 2304 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2305 * 2306 * This function unmaps I/O region. No return value. 2307 */ 2308 STATIC void 2309 pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t pch, int win) 2310 { 2311 struct pcic_handle *ph = (struct pcic_handle *)pch; 2312 int reg; 2313 2314 if (win >= PCIC_IO_WINS || win < 0) { 2315 panic("pccbb_pcmcia_io_unmap: window out of range"); 2316 } 2317 2318 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2319 switch (win) { 2320 case 0: 2321 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2322 break; 2323 case 1: 2324 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2325 break; 2326 } 2327 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2328 2329 ph->ioalloc &= ~(1 << win); 2330 } 2331 2332 static int 2333 pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 2334 { 2335 u_int8_t stat; 2336 int i; 2337 2338 /* wait an initial 10ms for quick cards */ 2339 stat = Pcic_read(ph, PCIC_IF_STATUS); 2340 if (stat & PCIC_IF_STATUS_READY) 2341 return (0); 2342 pccbb_pcmcia_delay(ph, 10, "pccwr0"); 2343 for (i = 0; i < 50; i++) { 2344 stat = Pcic_read(ph, PCIC_IF_STATUS); 2345 if (stat & PCIC_IF_STATUS_READY) 2346 return (0); 2347 if ((stat & PCIC_IF_STATUS_CARDDETECT_MASK) != 2348 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2349 return (ENXIO); 2350 /* wait .1s (100ms) each iteration now */ 2351 pccbb_pcmcia_delay(ph, 100, "pccwr1"); 2352 } 2353 2354 printf("pccbb_pcmcia_wait_ready: ready never happened, status=%02x\n", stat); 2355 return (EWOULDBLOCK); 2356 } 2357 2358 /* 2359 * Perform long (msec order) delay. timo is in milliseconds. 2360 */ 2361 static void 2362 pccbb_pcmcia_delay(struct pcic_handle *ph, int timo, const char *wmesg) 2363 { 2364 #ifdef DIAGNOSTIC 2365 if (timo <= 0) 2366 panic("pccbb_pcmcia_delay: called with timeout %d", timo); 2367 if (!curlwp) 2368 panic("pccbb_pcmcia_delay: called in interrupt context"); 2369 #if 0 2370 if (!ph->event_thread) 2371 panic("pccbb_pcmcia_delay: no event thread"); 2372 #endif 2373 #endif 2374 DPRINTF(("pccbb_pcmcia_delay: \"%s\" %p, sleep %d ms\n", 2375 wmesg, ph->event_thread, timo)); 2376 tsleep(pccbb_pcmcia_delay, PWAIT, wmesg, roundup(timo * hz, 1000) / 1000); 2377 } 2378 2379 /* 2380 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2381 * 2382 * This function enables the card. All information is stored in 2383 * the first argument, pcmcia_chipset_handle_t. 2384 */ 2385 STATIC void 2386 pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2387 { 2388 struct pcic_handle *ph = (struct pcic_handle *)pch; 2389 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2390 pcireg_t spsr; 2391 int voltage; 2392 int win; 2393 u_int8_t power, intr; 2394 #ifdef DIAGNOSTIC 2395 int reg; 2396 #endif 2397 2398 /* this bit is mostly stolen from pcic_attach_card */ 2399 2400 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2401 2402 /* get card Vcc info */ 2403 spsr = 2404 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2405 CB_SOCKET_STAT); 2406 if (spsr & CB_SOCKET_STAT_5VCARD) { 2407 DPRINTF(("5V card\n")); 2408 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2409 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2410 DPRINTF(("3V card\n")); 2411 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2412 } else { 2413 DPRINTF(("?V card, 0x%x\n", spsr)); /* XXX */ 2414 return; 2415 } 2416 2417 /* disable interrupts; assert RESET */ 2418 intr = Pcic_read(ph, PCIC_INTR); 2419 intr &= PCIC_INTR_ENABLE; 2420 Pcic_write(ph, PCIC_INTR, intr); 2421 2422 /* zero out the address windows */ 2423 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2424 2425 /* power down the socket to reset it, clear the card reset pin */ 2426 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2427 2428 /* power off; assert output enable bit */ 2429 power = PCIC_PWRCTL_OE; 2430 Pcic_write(ph, PCIC_PWRCTL, power); 2431 2432 /* power up the socket */ 2433 if (pccbb_power(sc, voltage) == 0) 2434 return; 2435 2436 /* 2437 * Table 4-18 and figure 4-6 of the PC Card specifiction say: 2438 * Vcc Rising Time (Tpr) = 100ms (handled in pccbb_power() above) 2439 * RESET Width (Th (Hi-z RESET)) = 1ms 2440 * RESET Width (Tw (RESET)) = 10us 2441 * 2442 * some machines require some more time to be settled 2443 * for example old toshiba topic bridges! 2444 * (100ms is added here). 2445 */ 2446 pccbb_pcmcia_delay(ph, 200 + 1, "pccen1"); 2447 2448 /* negate RESET */ 2449 intr |= PCIC_INTR_RESET; 2450 Pcic_write(ph, PCIC_INTR, intr); 2451 2452 /* 2453 * RESET Setup Time (Tsu (RESET)) = 20ms 2454 */ 2455 pccbb_pcmcia_delay(ph, 20, "pccen2"); 2456 2457 #ifdef DIAGNOSTIC 2458 reg = Pcic_read(ph, PCIC_IF_STATUS); 2459 if ((reg & PCIC_IF_STATUS_POWERACTIVE) == 0) 2460 printf("pccbb_pcmcia_socket_enable: no power, status=%x\n", reg); 2461 #endif 2462 2463 /* wait for the chip to finish initializing */ 2464 if (pccbb_pcmcia_wait_ready(ph)) { 2465 #ifdef DIAGNOSTIC 2466 printf("pccbb_pcmcia_socket_enable: never became ready\n"); 2467 #endif 2468 /* XXX return a failure status?? */ 2469 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2470 Pcic_write(ph, PCIC_PWRCTL, 0); 2471 return; 2472 } 2473 2474 /* reinstall all the memory and io mappings */ 2475 for (win = 0; win < PCIC_MEM_WINS; ++win) 2476 if (ph->memalloc & (1 << win)) 2477 pccbb_pcmcia_do_mem_map(ph, win); 2478 for (win = 0; win < PCIC_IO_WINS; ++win) 2479 if (ph->ioalloc & (1 << win)) 2480 pccbb_pcmcia_do_io_map(ph, win); 2481 } 2482 2483 /* 2484 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2485 * 2486 * This function disables the card. All information is stored in 2487 * the first argument, pcmcia_chipset_handle_t. 2488 */ 2489 STATIC void 2490 pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t pch) 2491 { 2492 struct pcic_handle *ph = (struct pcic_handle *)pch; 2493 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2494 u_int8_t intr; 2495 2496 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2497 2498 /* disable interrupts; assert RESET */ 2499 intr = Pcic_read(ph, PCIC_INTR); 2500 intr &= PCIC_INTR_ENABLE; 2501 Pcic_write(ph, PCIC_INTR, intr); 2502 2503 /* zero out the address windows */ 2504 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2505 2506 /* power down the socket to reset it, clear the card reset pin */ 2507 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2508 2509 /* disable socket: negate output enable bit and power off */ 2510 Pcic_write(ph, PCIC_PWRCTL, 0); 2511 2512 /* 2513 * Vcc Falling Time (Tpf) = 300ms 2514 */ 2515 pccbb_pcmcia_delay(ph, 300, "pccwr1"); 2516 } 2517 2518 STATIC void 2519 pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t pch, int type) 2520 { 2521 struct pcic_handle *ph = (struct pcic_handle *)pch; 2522 u_int8_t intr; 2523 2524 /* set the card type */ 2525 2526 intr = Pcic_read(ph, PCIC_INTR); 2527 intr &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_CARDTYPE_MASK); 2528 if (type == PCMCIA_IFTYPE_IO) 2529 intr |= PCIC_INTR_CARDTYPE_IO; 2530 else 2531 intr |= PCIC_INTR_CARDTYPE_MEM; 2532 Pcic_write(ph, PCIC_INTR, intr); 2533 2534 DPRINTF(("%s: pccbb_pcmcia_socket_settype %02x type %s %02x\n", 2535 device_xname(ph->ph_parent), ph->sock, 2536 ((type == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2537 } 2538 2539 /* 2540 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2541 * 2542 * This function detects whether a card is in the slot or not. 2543 * If a card is inserted, return 1. Otherwise, return 0. 2544 */ 2545 STATIC int 2546 pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch) 2547 { 2548 struct pcic_handle *ph = (struct pcic_handle *)pch; 2549 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2550 2551 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2552 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2553 } 2554 2555 #if 0 2556 STATIC int 2557 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2558 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2559 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2560 #endif 2561 /* 2562 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2563 * bus_size_t size, 2564 * struct pcmcia_mem_handle *pcmhp) 2565 * 2566 * This function only allocates memory region for pccard. This 2567 * function never maps the allocated region to pccard memory area. 2568 * 2569 * XXX: Why the argument of start address is not in? 2570 */ 2571 STATIC int 2572 pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 2573 struct pcmcia_mem_handle *pcmhp) 2574 { 2575 struct pcic_handle *ph = (struct pcic_handle *)pch; 2576 bus_space_handle_t memh; 2577 bus_addr_t addr; 2578 bus_size_t sizepg; 2579 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2580 #if rbus 2581 rbus_tag_t rb; 2582 #endif 2583 2584 /* Check that the card is still there. */ 2585 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2586 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2587 return 1; 2588 2589 /* out of sc->memh, allocate as many pages as necessary */ 2590 2591 /* convert size to PCIC pages */ 2592 /* 2593 * This is not enough; when the requested region is on the page 2594 * boundaries, this may calculate wrong result. 2595 */ 2596 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2597 #if 0 2598 if (sizepg > PCIC_MAX_MEM_PAGES) { 2599 return 1; 2600 } 2601 #endif 2602 2603 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2604 return 1; 2605 } 2606 2607 addr = 0; /* XXX gcc -Wuninitialized */ 2608 2609 #if rbus 2610 rb = sc->sc_rbus_memt; 2611 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2612 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2613 &addr, &memh)) { 2614 return 1; 2615 } 2616 #else 2617 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2618 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2619 0, /* boundary */ 2620 0, /* flags */ 2621 &addr, &memh)) { 2622 return 1; 2623 } 2624 #endif 2625 2626 DPRINTF(("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, " 2627 "realsize 0x%lx\n", (unsigned long)addr, (unsigned long)size, 2628 (unsigned long)sizepg * PCIC_MEM_PAGESIZE)); 2629 2630 pcmhp->memt = sc->sc_memt; 2631 pcmhp->memh = memh; 2632 pcmhp->addr = addr; 2633 pcmhp->size = size; 2634 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2635 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2636 pcmhp->mhandle = 0; 2637 /* No offset??? Funny. */ 2638 2639 return 0; 2640 } 2641 2642 /* 2643 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2644 * struct pcmcia_mem_handle *pcmhp) 2645 * 2646 * This function release the memory space allocated by the function 2647 * pccbb_pcmcia_mem_alloc(). 2648 */ 2649 STATIC void 2650 pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2651 struct pcmcia_mem_handle *pcmhp) 2652 { 2653 #if rbus 2654 struct pcic_handle *ph = (struct pcic_handle *)pch; 2655 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2656 2657 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2658 #else 2659 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2660 #endif 2661 } 2662 2663 /* 2664 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2665 * 2666 * This function release the memory space allocated by the function 2667 * pccbb_pcmcia_mem_alloc(). 2668 */ 2669 STATIC void 2670 pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2671 { 2672 int regbase_win; 2673 bus_addr_t phys_addr; 2674 bus_addr_t phys_end; 2675 2676 #define PCIC_SMM_START_LOW 0 2677 #define PCIC_SMM_START_HIGH 1 2678 #define PCIC_SMM_STOP_LOW 2 2679 #define PCIC_SMM_STOP_HIGH 3 2680 #define PCIC_CMA_LOW 4 2681 #define PCIC_CMA_HIGH 5 2682 2683 u_int8_t start_low, start_high = 0; 2684 u_int8_t stop_low, stop_high; 2685 u_int8_t off_low, off_high; 2686 u_int8_t mem_window; 2687 int reg; 2688 2689 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2690 int mem8 = 2691 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2692 || (kind == PCMCIA_MEM_ATTR); 2693 2694 regbase_win = 0x10 + win * 0x08; 2695 2696 phys_addr = ph->mem[win].addr; 2697 phys_end = phys_addr + ph->mem[win].size; 2698 2699 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2700 (unsigned long)phys_addr, (unsigned long)phys_end, 2701 (unsigned long)ph->mem[win].offset)); 2702 2703 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2704 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2705 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2706 2707 /* bit 19:12 */ 2708 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2709 /* bit 23:20 and bit 7 on */ 2710 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2711 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2712 /* bit 31:24, for 32-bit address */ 2713 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2714 2715 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2716 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2717 2718 if (((struct pccbb_softc *)ph-> 2719 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2720 Pcic_write(ph, 0x40 + win, mem_window); 2721 } 2722 2723 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2724 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2725 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2726 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2727 2728 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2729 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2730 2731 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2732 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2733 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2734 | ((kind == PCMCIA_MEM_ATTR) ? 2735 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2736 2737 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2738 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2739 2740 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2741 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2742 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2743 2744 #if defined(CBB_DEBUG) 2745 { 2746 int r1, r2, r3, r4, r5, r6, r7 = 0; 2747 2748 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2749 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2750 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2751 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2752 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2753 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2754 if (((struct pccbb_softc *)(ph-> 2755 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2756 r7 = Pcic_read(ph, 0x40 + win); 2757 } 2758 2759 printf("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2760 "%02x%02x", win, r1, r2, r3, r4, r5, r6); 2761 if (((struct pccbb_softc *)(ph-> 2762 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2763 printf(" %02x", r7); 2764 } 2765 printf("\n"); 2766 } 2767 #endif 2768 } 2769 2770 /* 2771 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2772 * bus_addr_t card_addr, bus_size_t size, 2773 * struct pcmcia_mem_handle *pcmhp, 2774 * bus_addr_t *offsetp, int *windowp) 2775 * 2776 * This function maps memory space allocated by the function 2777 * pccbb_pcmcia_mem_alloc(). 2778 */ 2779 STATIC int 2780 pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2781 bus_addr_t card_addr, bus_size_t size, struct pcmcia_mem_handle *pcmhp, 2782 bus_addr_t *offsetp, int *windowp) 2783 { 2784 struct pcic_handle *ph = (struct pcic_handle *)pch; 2785 bus_addr_t busaddr; 2786 long card_offset; 2787 int win; 2788 2789 /* Check that the card is still there. */ 2790 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2791 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2792 return 1; 2793 2794 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2795 if ((ph->memalloc & (1 << win)) == 0) { 2796 ph->memalloc |= (1 << win); 2797 break; 2798 } 2799 } 2800 2801 if (win == PCIC_MEM_WINS) { 2802 return 1; 2803 } 2804 2805 *windowp = win; 2806 2807 /* XXX this is pretty gross */ 2808 2809 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2810 panic("pccbb_pcmcia_mem_map memt is bogus"); 2811 } 2812 2813 busaddr = pcmhp->addr; 2814 2815 /* 2816 * compute the address offset to the pcmcia address space for the 2817 * pcic. this is intentionally signed. The masks and shifts below 2818 * will cause TRT to happen in the pcic registers. Deal with making 2819 * sure the address is aligned, and return the alignment offset. 2820 */ 2821 2822 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2823 card_addr -= *offsetp; 2824 2825 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2826 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2827 (u_long) card_addr)); 2828 2829 /* 2830 * include the offset in the size, and decrement size by one, since 2831 * the hw wants start/stop 2832 */ 2833 size += *offsetp - 1; 2834 2835 card_offset = (((long)card_addr) - ((long)busaddr)); 2836 2837 ph->mem[win].addr = busaddr; 2838 ph->mem[win].size = size; 2839 ph->mem[win].offset = card_offset; 2840 ph->mem[win].kind = kind; 2841 2842 pccbb_pcmcia_do_mem_map(ph, win); 2843 2844 return 0; 2845 } 2846 2847 /* 2848 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2849 * int window) 2850 * 2851 * This function unmaps memory space which mapped by the function 2852 * pccbb_pcmcia_mem_map(). 2853 */ 2854 STATIC void 2855 pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, int window) 2856 { 2857 struct pcic_handle *ph = (struct pcic_handle *)pch; 2858 int reg; 2859 2860 if (window >= PCIC_MEM_WINS) { 2861 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2862 } 2863 2864 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2865 reg &= ~(1 << window); 2866 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2867 2868 ph->memalloc &= ~(1 << window); 2869 } 2870 2871 #if defined PCCBB_PCMCIA_POLL 2872 struct pccbb_poll_str { 2873 void *arg; 2874 int (*func)(void *); 2875 int level; 2876 struct pcic_handle *ph; 2877 int count; 2878 int num; 2879 struct callout poll_ch; 2880 }; 2881 2882 static struct pccbb_poll_str pccbb_poll[10]; 2883 static int pccbb_poll_n = 0; 2884 2885 static void pccbb_pcmcia_poll(void *arg); 2886 2887 static void 2888 pccbb_pcmcia_poll(void *arg) 2889 { 2890 struct pccbb_poll_str *poll = arg; 2891 struct pcic_handle *ph = poll->ph; 2892 struct pccbb_softc *sc = ph->sc; 2893 int s; 2894 u_int32_t spsr; /* socket present-state reg */ 2895 2896 callout_reset(&poll->poll_ch, hz * 2, pccbb_pcmcia_poll, arg); 2897 switch (poll->level) { 2898 case IPL_NET: 2899 s = splnet(); 2900 break; 2901 case IPL_BIO: 2902 s = splbio(); 2903 break; 2904 case IPL_TTY: /* fallthrough */ 2905 default: 2906 s = spltty(); 2907 break; 2908 } 2909 2910 spsr = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2911 CB_SOCKET_STAT); 2912 2913 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2914 if (!(spsr & 0x40)) /* CINT low */ 2915 #else 2916 if (1) 2917 #endif 2918 { 2919 if ((*poll->func) (poll->arg) > 0) { 2920 ++poll->count; 2921 /* printf("intr: reported from poller, 0x%x\n", spsr); */ 2922 #if defined LEVEL2 2923 } else { 2924 printf("intr: miss! 0x%x\n", spsr); 2925 #endif 2926 } 2927 } 2928 splx(s); 2929 } 2930 #endif /* defined CB_PCMCIA_POLL */ 2931 2932 /* 2933 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2934 * struct pcmcia_function *pf, 2935 * int ipl, 2936 * int (*func)(void *), 2937 * void *arg); 2938 * 2939 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2940 */ 2941 STATIC void * 2942 pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2943 struct pcmcia_function *pf, int ipl, int (*func)(void *), void *arg) 2944 { 2945 struct pcic_handle *ph = (struct pcic_handle *)pch; 2946 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2947 2948 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2949 /* what should I do? */ 2950 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2951 DPRINTF(("%s does not provide edge nor pulse " 2952 "interrupt\n", device_xname(&sc->sc_dev))); 2953 return NULL; 2954 } 2955 /* 2956 * XXX Noooooo! The interrupt flag must set properly!! 2957 * dumb pcmcia driver!! 2958 */ 2959 } 2960 2961 return pccbb_intr_establish(sc, 0, ipl, func, arg); 2962 } 2963 2964 /* 2965 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2966 * void *ih) 2967 * 2968 * This function disables PC-Card interrupt. 2969 */ 2970 STATIC void 2971 pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 2972 { 2973 struct pcic_handle *ph = (struct pcic_handle *)pch; 2974 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2975 2976 pccbb_intr_disestablish(sc, ih); 2977 } 2978 2979 #if rbus 2980 /* 2981 * static int 2982 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2983 * bus_addr_t addr, bus_size_t size, 2984 * bus_addr_t mask, bus_size_t align, 2985 * int flags, bus_addr_t *addrp; 2986 * bus_space_handle_t *bshp) 2987 * 2988 * This function allocates a portion of memory or io space for 2989 * clients. This function is called from CardBus card drivers. 2990 */ 2991 static int 2992 pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2993 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 2994 int flags, bus_addr_t *addrp, bus_space_handle_t *bshp) 2995 { 2996 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2997 2998 DPRINTF(("pccbb_rbus_cb_space_alloc: addr 0x%lx, size 0x%lx, " 2999 "mask 0x%lx, align 0x%lx\n", (unsigned long)addr, 3000 (unsigned long)size, (unsigned long)mask, (unsigned long)align)); 3001 3002 if (align == 0) { 3003 align = size; 3004 } 3005 3006 if (rb->rb_bt == sc->sc_memt) { 3007 if (align < 16) { 3008 return 1; 3009 } 3010 /* 3011 * XXX: align more than 0x1000 to avoid overwrapping 3012 * memory windows for two or more devices. 0x1000 3013 * means memory window's granularity. 3014 * 3015 * Two or more devices should be able to share same 3016 * memory window region. However, overrapping memory 3017 * window is not good because some devices, such as 3018 * 3Com 3C575[BC], have a broken address decoder and 3019 * intrude other's memory region. 3020 */ 3021 if (align < 0x1000) { 3022 align = 0x1000; 3023 } 3024 } else if (rb->rb_bt == sc->sc_iot) { 3025 if (align < 4) { 3026 return 1; 3027 } 3028 /* XXX: hack for avoiding ISA image */ 3029 if (mask < 0x0100) { 3030 mask = 0x3ff; 3031 addr = 0x300; 3032 } 3033 3034 } else { 3035 DPRINTF(("pccbb_rbus_cb_space_alloc: Bus space tag 0x%lx is " 3036 "NOT used. io: 0x%lx, mem: 0x%lx\n", 3037 (unsigned long)rb->rb_bt, (unsigned long)sc->sc_iot, 3038 (unsigned long)sc->sc_memt)); 3039 return 1; 3040 /* XXX: panic here? */ 3041 } 3042 3043 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 3044 aprint_normal_dev(&sc->sc_dev, "<rbus> no bus space\n"); 3045 return 1; 3046 } 3047 3048 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 3049 3050 return 0; 3051 } 3052 3053 /* 3054 * static int 3055 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 3056 * bus_space_handle_t *bshp, bus_size_t size); 3057 * 3058 * This function is called from CardBus card drivers. 3059 */ 3060 static int 3061 pccbb_rbus_cb_space_free(cardbus_chipset_tag_t ct, rbus_tag_t rb, 3062 bus_space_handle_t bsh, bus_size_t size) 3063 { 3064 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 3065 bus_space_tag_t bt = rb->rb_bt; 3066 3067 pccbb_close_win(sc, bt, bsh, size); 3068 3069 if (bt == sc->sc_memt) { 3070 } else if (bt == sc->sc_iot) { 3071 } else { 3072 return 1; 3073 /* XXX: panic here? */ 3074 } 3075 3076 return rbus_space_free(rb, bsh, size, NULL); 3077 } 3078 #endif /* rbus */ 3079 3080 #if rbus 3081 3082 static int 3083 pccbb_open_win(struct pccbb_softc *sc, bus_space_tag_t bst, bus_addr_t addr, 3084 bus_size_t size, bus_space_handle_t bsh, int flags) 3085 { 3086 struct pccbb_win_chain_head *head; 3087 bus_addr_t align; 3088 3089 head = &sc->sc_iowindow; 3090 align = 0x04; 3091 if (sc->sc_memt == bst) { 3092 head = &sc->sc_memwindow; 3093 align = 0x1000; 3094 DPRINTF(("using memory window, 0x%lx 0x%lx 0x%lx\n\n", 3095 (unsigned long)sc->sc_iot, (unsigned long)sc->sc_memt, 3096 (unsigned long)bst)); 3097 } 3098 3099 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 3100 aprint_error_dev(&sc->sc_dev, 3101 "pccbb_open_win: %s winlist insert failed\n", 3102 (head == &sc->sc_memwindow) ? "mem" : "io"); 3103 } 3104 pccbb_winset(align, sc, bst); 3105 3106 return 0; 3107 } 3108 3109 static int 3110 pccbb_close_win(struct pccbb_softc *sc, bus_space_tag_t bst, 3111 bus_space_handle_t bsh, bus_size_t size) 3112 { 3113 struct pccbb_win_chain_head *head; 3114 bus_addr_t align; 3115 3116 head = &sc->sc_iowindow; 3117 align = 0x04; 3118 if (sc->sc_memt == bst) { 3119 head = &sc->sc_memwindow; 3120 align = 0x1000; 3121 } 3122 3123 if (pccbb_winlist_delete(head, bsh, size)) { 3124 aprint_error_dev(&sc->sc_dev, 3125 "pccbb_close_win: %s winlist delete failed\n", 3126 (head == &sc->sc_memwindow) ? "mem" : "io"); 3127 } 3128 pccbb_winset(align, sc, bst); 3129 3130 return 0; 3131 } 3132 3133 static int 3134 pccbb_winlist_insert(struct pccbb_win_chain_head *head, bus_addr_t start, 3135 bus_size_t size, bus_space_handle_t bsh, int flags) 3136 { 3137 struct pccbb_win_chain *chainp, *elem; 3138 3139 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 3140 M_NOWAIT)) == NULL) 3141 return (1); /* fail */ 3142 3143 elem->wc_start = start; 3144 elem->wc_end = start + (size - 1); 3145 elem->wc_handle = bsh; 3146 elem->wc_flags = flags; 3147 3148 TAILQ_FOREACH(chainp, head, wc_list) { 3149 if (chainp->wc_end >= start) 3150 break; 3151 } 3152 if (chainp != NULL) 3153 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 3154 else 3155 TAILQ_INSERT_TAIL(head, elem, wc_list); 3156 return (0); 3157 } 3158 3159 static int 3160 pccbb_winlist_delete(struct pccbb_win_chain_head *head, bus_space_handle_t bsh, 3161 bus_size_t size) 3162 { 3163 struct pccbb_win_chain *chainp; 3164 3165 TAILQ_FOREACH(chainp, head, wc_list) { 3166 if (memcmp(&chainp->wc_handle, &bsh, sizeof(bsh)) == 0) 3167 break; 3168 } 3169 if (chainp == NULL) 3170 return 1; /* fail: no candidate to remove */ 3171 3172 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 3173 printf("pccbb_winlist_delete: window 0x%lx size " 3174 "inconsistent: 0x%lx, 0x%lx\n", 3175 (unsigned long)chainp->wc_start, 3176 (unsigned long)(chainp->wc_end - chainp->wc_start), 3177 (unsigned long)(size - 1)); 3178 return 1; 3179 } 3180 3181 TAILQ_REMOVE(head, chainp, wc_list); 3182 free(chainp, M_DEVBUF); 3183 3184 return 0; 3185 } 3186 3187 static void 3188 pccbb_winset(bus_addr_t align, struct pccbb_softc *sc, bus_space_tag_t bst) 3189 { 3190 pci_chipset_tag_t pc; 3191 pcitag_t tag; 3192 bus_addr_t mask = ~(align - 1); 3193 struct { 3194 cardbusreg_t win_start; 3195 cardbusreg_t win_limit; 3196 int win_flags; 3197 } win[2]; 3198 struct pccbb_win_chain *chainp; 3199 int offs; 3200 3201 win[0].win_start = win[1].win_start = 0xffffffff; 3202 win[0].win_limit = win[1].win_limit = 0; 3203 win[0].win_flags = win[1].win_flags = 0; 3204 3205 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3206 offs = PCI_CB_IOBASE0; 3207 if (sc->sc_memt == bst) { 3208 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3209 offs = PCI_CB_MEMBASE0; 3210 } 3211 3212 if (chainp != NULL) { 3213 win[0].win_start = chainp->wc_start & mask; 3214 win[0].win_limit = chainp->wc_end & mask; 3215 win[0].win_flags = chainp->wc_flags; 3216 chainp = TAILQ_NEXT(chainp, wc_list); 3217 } 3218 3219 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3220 if (win[1].win_start == 0xffffffff) { 3221 /* window 1 is not used */ 3222 if ((win[0].win_flags == chainp->wc_flags) && 3223 (win[0].win_limit + align >= 3224 (chainp->wc_start & mask))) { 3225 /* concatenate */ 3226 win[0].win_limit = chainp->wc_end & mask; 3227 } else { 3228 /* make new window */ 3229 win[1].win_start = chainp->wc_start & mask; 3230 win[1].win_limit = chainp->wc_end & mask; 3231 win[1].win_flags = chainp->wc_flags; 3232 } 3233 continue; 3234 } 3235 3236 /* Both windows are engaged. */ 3237 if (win[0].win_flags == win[1].win_flags) { 3238 /* same flags */ 3239 if (win[0].win_flags == chainp->wc_flags) { 3240 if (win[1].win_start - (win[0].win_limit + 3241 align) < 3242 (chainp->wc_start & mask) - 3243 ((chainp->wc_end & mask) + align)) { 3244 /* 3245 * merge window 0 and 1, and set win1 3246 * to chainp 3247 */ 3248 win[0].win_limit = win[1].win_limit; 3249 win[1].win_start = 3250 chainp->wc_start & mask; 3251 win[1].win_limit = 3252 chainp->wc_end & mask; 3253 } else { 3254 win[1].win_limit = 3255 chainp->wc_end & mask; 3256 } 3257 } else { 3258 /* different flags */ 3259 3260 /* concatenate win0 and win1 */ 3261 win[0].win_limit = win[1].win_limit; 3262 /* allocate win[1] to new space */ 3263 win[1].win_start = chainp->wc_start & mask; 3264 win[1].win_limit = chainp->wc_end & mask; 3265 win[1].win_flags = chainp->wc_flags; 3266 } 3267 } else { 3268 /* the flags of win[0] and win[1] is different */ 3269 if (win[0].win_flags == chainp->wc_flags) { 3270 win[0].win_limit = chainp->wc_end & mask; 3271 /* 3272 * XXX this creates overlapping windows, so 3273 * what should the poor bridge do if one is 3274 * cachable, and the other is not? 3275 */ 3276 aprint_error_dev(&sc->sc_dev, 3277 "overlapping windows\n"); 3278 } else { 3279 win[1].win_limit = chainp->wc_end & mask; 3280 } 3281 } 3282 } 3283 3284 pc = sc->sc_pc; 3285 tag = sc->sc_tag; 3286 pci_conf_write(pc, tag, offs, win[0].win_start); 3287 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3288 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3289 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3290 DPRINTF(("--pccbb_winset: win0 [0x%lx, 0x%lx), win1 [0x%lx, 0x%lx)\n", 3291 (unsigned long)pci_conf_read(pc, tag, offs), 3292 (unsigned long)pci_conf_read(pc, tag, offs + 4) + align, 3293 (unsigned long)pci_conf_read(pc, tag, offs + 8), 3294 (unsigned long)pci_conf_read(pc, tag, offs + 12) + align)); 3295 3296 if (bst == sc->sc_memt) { 3297 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BRIDGE_CONTROL_REG); 3298 3299 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 3300 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 3301 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3302 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 3303 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3304 pci_conf_write(pc, tag, PCI_BRIDGE_CONTROL_REG, bcr); 3305 } 3306 } 3307 3308 #endif /* rbus */ 3309 3310 static bool 3311 pccbb_suspend(device_t dv PMF_FN_ARGS) 3312 { 3313 struct pccbb_softc *sc = device_private(dv); 3314 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3315 bus_space_handle_t base_memh = sc->sc_base_memh; 3316 pcireg_t reg; 3317 3318 if (sc->sc_pil_intr_enable) 3319 (void)pccbbintr_function(sc); 3320 sc->sc_pil_intr_enable = 0; 3321 3322 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3323 /* Disable interrupts. */ 3324 reg &= ~(CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER); 3325 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3326 /* XXX joerg Disable power to the socket? */ 3327 3328 /* XXX flush PCI write */ 3329 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3330 3331 /* reset interrupt */ 3332 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, 3333 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT)); 3334 /* XXX flush PCI write */ 3335 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3336 3337 if (sc->sc_ih != NULL) { 3338 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 3339 sc->sc_ih = NULL; 3340 } 3341 3342 return true; 3343 } 3344 3345 static bool 3346 pccbb_resume(device_t dv PMF_FN_ARGS) 3347 { 3348 struct pccbb_softc *sc = device_private(dv); 3349 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3350 bus_space_handle_t base_memh = sc->sc_base_memh; 3351 pcireg_t reg; 3352 3353 pccbb_chipinit(sc); 3354 pccbb_intrinit(sc); 3355 /* setup memory and io space window for CB */ 3356 pccbb_winset(0x1000, sc, sc->sc_memt); 3357 pccbb_winset(0x04, sc, sc->sc_iot); 3358 3359 /* CSC Interrupt: Card detect interrupt on */ 3360 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3361 /* Card detect intr is turned on. */ 3362 reg |= CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; 3363 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3364 /* reset interrupt */ 3365 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3366 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3367 3368 /* 3369 * check for card insertion or removal during suspend period. 3370 * XXX: the code can't cope with card swap (remove then 3371 * insert). how can we detect such situation? 3372 */ 3373 (void)pccbbintr(sc); 3374 3375 sc->sc_pil_intr_enable = 1; 3376 3377 return true; 3378 } 3379
Indexes created Thu Sep 25 16:09:42 GMT 2025