pccbb.c revision 1.167.4.4
1 /* $NetBSD: pccbb.c,v 1.167.4.4 2009/08/19 18:47:12 yamt Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: pccbb.c,v 1.167.4.4 2009/08/19 18:47:12 yamt Exp $"); 35 36 /* 37 #define CBB_DEBUG 38 #define SHOW_REGS 39 */ 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/kernel.h> 44 #include <sys/errno.h> 45 #include <sys/ioctl.h> 46 #include <sys/reboot.h> /* for bootverbose */ 47 #include <sys/syslog.h> 48 #include <sys/device.h> 49 #include <sys/malloc.h> 50 #include <sys/proc.h> 51 52 #include <sys/intr.h> 53 #include <sys/bus.h> 54 55 #include <dev/pci/pcivar.h> 56 #include <dev/pci/pcireg.h> 57 #include <dev/pci/pcidevs.h> 58 59 #include <dev/pci/pccbbreg.h> 60 61 #include <dev/cardbus/cardslotvar.h> 62 63 #include <dev/cardbus/cardbusvar.h> 64 65 #include <dev/pcmcia/pcmciareg.h> 66 #include <dev/pcmcia/pcmciavar.h> 67 68 #include <dev/ic/i82365reg.h> 69 #include <dev/pci/pccbbvar.h> 70 71 #ifndef __NetBSD_Version__ 72 struct cfdriver cbb_cd = { 73 NULL, "cbb", DV_DULL 74 }; 75 #endif 76 77 #ifdef CBB_DEBUG 78 #define DPRINTF(x) printf x 79 #define STATIC 80 #else 81 #define DPRINTF(x) 82 #define STATIC static 83 #endif 84 85 int pccbb_burstup = 1; 86 87 /* 88 * delay_ms() is wait in milliseconds. It should be used instead 89 * of delay() if you want to wait more than 1 ms. 90 */ 91 static inline void 92 delay_ms(int millis, struct pccbb_softc *sc) 93 { 94 if (cold) 95 delay(millis * 1000); 96 else 97 kpause("pccbb", false, mstohz(millis), NULL); 98 } 99 100 int pcicbbmatch(device_t, cfdata_t, void *); 101 void pccbbattach(device_t, device_t, void *); 102 void pccbbchilddet(device_t, device_t); 103 int pccbbdetach(device_t, int); 104 int pccbbintr(void *); 105 static void pci113x_insert(void *); 106 static int pccbbintr_function(struct pccbb_softc *); 107 108 static int pccbb_detect_card(struct pccbb_softc *); 109 110 static void pccbb_pcmcia_write(struct pccbb_softc *, int, u_int8_t); 111 static u_int8_t pccbb_pcmcia_read(struct pccbb_softc *, int); 112 #define Pcic_read(sc, reg) pccbb_pcmcia_read((sc), (reg)) 113 #define Pcic_write(sc, reg, val) pccbb_pcmcia_write((sc), (reg), (val)) 114 115 STATIC int cb_reset(struct pccbb_softc *); 116 STATIC int cb_detect_voltage(struct pccbb_softc *); 117 STATIC int cbbprint(void *, const char *); 118 119 static int cb_chipset(u_int32_t, int *); 120 STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *, 121 struct pcmciabus_attach_args *); 122 123 STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int); 124 STATIC int pccbb_power(struct pccbb_softc *sc, int); 125 STATIC int pccbb_power_ct(cardbus_chipset_tag_t, int); 126 STATIC int pccbb_cardenable(struct pccbb_softc * sc, int function); 127 #if !rbus 128 static int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 129 static int pccbb_io_close(cardbus_chipset_tag_t, int); 130 static int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 131 static int pccbb_mem_close(cardbus_chipset_tag_t, int); 132 #endif /* !rbus */ 133 static void *pccbb_intr_establish(struct pccbb_softc *, 134 cardbus_intr_line_t irq, int level, int (*ih) (void *), void *sc); 135 static void pccbb_intr_disestablish(struct pccbb_softc *, void *ih); 136 137 static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t, 138 cardbus_intr_line_t irq, int level, int (*ih) (void *), void *sc); 139 static void pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih); 140 141 static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t, int, int); 142 static void pccbb_free_tag(cardbus_chipset_tag_t, cardbustag_t); 143 static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t, cardbustag_t, int); 144 static void pccbb_conf_write(cardbus_chipset_tag_t, cardbustag_t, int, 145 cardbusreg_t); 146 static void pccbb_chipinit(struct pccbb_softc *); 147 static void pccbb_intrinit(struct pccbb_softc *); 148 149 STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 150 struct pcmcia_mem_handle *); 151 STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t, 152 struct pcmcia_mem_handle *); 153 STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 154 bus_size_t, struct pcmcia_mem_handle *, bus_size_t *, int *); 155 STATIC void pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t, int); 156 STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 157 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 158 STATIC void pccbb_pcmcia_io_free(pcmcia_chipset_handle_t, 159 struct pcmcia_io_handle *); 160 STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 161 bus_size_t, struct pcmcia_io_handle *, int *); 162 STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t, int); 163 STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t, 164 struct pcmcia_function *, int, int (*)(void *), void *); 165 STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t, void *); 166 STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t); 167 STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t); 168 STATIC void pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t, int); 169 STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch); 170 171 static int pccbb_pcmcia_wait_ready(struct pccbb_softc *); 172 static void pccbb_pcmcia_delay(struct pccbb_softc *, int, const char *); 173 174 static void pccbb_pcmcia_do_io_map(struct pccbb_softc *, int); 175 static void pccbb_pcmcia_do_mem_map(struct pccbb_softc *, int); 176 177 /* bus-space allocation and deallocation functions */ 178 #if rbus 179 180 static int pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t, rbus_tag_t, 181 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 182 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp); 183 static int pccbb_rbus_cb_space_free(cardbus_chipset_tag_t, rbus_tag_t, 184 bus_space_handle_t, bus_size_t); 185 186 #endif /* rbus */ 187 188 #if rbus 189 190 static int pccbb_open_win(struct pccbb_softc *, bus_space_tag_t, 191 bus_addr_t, bus_size_t, bus_space_handle_t, int flags); 192 static int pccbb_close_win(struct pccbb_softc *, bus_space_tag_t, 193 bus_space_handle_t, bus_size_t); 194 static int pccbb_winlist_insert(struct pccbb_win_chain_head *, bus_addr_t, 195 bus_size_t, bus_space_handle_t, int); 196 static int pccbb_winlist_delete(struct pccbb_win_chain_head *, 197 bus_space_handle_t, bus_size_t); 198 static void pccbb_winset(bus_addr_t align, struct pccbb_softc *, 199 bus_space_tag_t); 200 void pccbb_winlist_show(struct pccbb_win_chain *); 201 202 #endif /* rbus */ 203 204 /* for config_defer */ 205 static void pccbb_pci_callback(device_t); 206 207 static bool pccbb_suspend(device_t PMF_FN_PROTO); 208 static bool pccbb_resume(device_t PMF_FN_PROTO); 209 210 #if defined SHOW_REGS 211 static void cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, 212 bus_space_tag_t memt, bus_space_handle_t memh); 213 #endif 214 215 CFATTACH_DECL3_NEW(cbb_pci, sizeof(struct pccbb_softc), 216 pcicbbmatch, pccbbattach, pccbbdetach, NULL, NULL, pccbbchilddet, 217 DVF_DETACH_SHUTDOWN); 218 219 static const struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 220 pccbb_pcmcia_mem_alloc, 221 pccbb_pcmcia_mem_free, 222 pccbb_pcmcia_mem_map, 223 pccbb_pcmcia_mem_unmap, 224 pccbb_pcmcia_io_alloc, 225 pccbb_pcmcia_io_free, 226 pccbb_pcmcia_io_map, 227 pccbb_pcmcia_io_unmap, 228 pccbb_pcmcia_intr_establish, 229 pccbb_pcmcia_intr_disestablish, 230 pccbb_pcmcia_socket_enable, 231 pccbb_pcmcia_socket_disable, 232 pccbb_pcmcia_socket_settype, 233 pccbb_pcmcia_card_detect 234 }; 235 236 #if rbus 237 static const struct cardbus_functions pccbb_funcs = { 238 pccbb_rbus_cb_space_alloc, 239 pccbb_rbus_cb_space_free, 240 pccbb_cb_intr_establish, 241 pccbb_cb_intr_disestablish, 242 pccbb_ctrl, 243 pccbb_power_ct, 244 pccbb_make_tag, 245 pccbb_free_tag, 246 pccbb_conf_read, 247 pccbb_conf_write, 248 }; 249 #else 250 static const struct cardbus_functions pccbb_funcs = { 251 pccbb_ctrl, 252 pccbb_power_ct, 253 pccbb_mem_open, 254 pccbb_mem_close, 255 pccbb_io_open, 256 pccbb_io_close, 257 pccbb_cb_intr_establish, 258 pccbb_cb_intr_disestablish, 259 pccbb_make_tag, 260 pccbb_conf_read, 261 pccbb_conf_write, 262 }; 263 #endif 264 265 int 266 pcicbbmatch(device_t parent, cfdata_t match, void *aux) 267 { 268 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 269 270 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 271 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 272 PCI_INTERFACE(pa->pa_class) == 0) { 273 return 1; 274 } 275 276 return 0; 277 } 278 279 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 280 | ((prod) << PCI_PRODUCT_SHIFT)) 281 282 const struct yenta_chipinfo { 283 pcireg_t yc_id; /* vendor tag | product tag */ 284 int yc_chiptype; 285 int yc_flags; 286 } yc_chipsets[] = { 287 /* Texas Instruments chips */ 288 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 289 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 290 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 291 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 292 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI125X, 293 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 294 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 295 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 296 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 297 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 298 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 299 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 300 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI125X, 301 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 302 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI125X, 303 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 304 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 305 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 306 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 307 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 308 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI1420, 309 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 310 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI125X, 311 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 312 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 313 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 314 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1520), CB_TI12XX, 315 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 316 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4410YENTA), CB_TI12XX, 317 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 318 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4520YENTA), CB_TI12XX, 319 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 320 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI7420YENTA), CB_TI12XX, 321 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 322 323 /* Ricoh chips */ 324 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 325 PCCBB_PCMCIA_MEM_32}, 326 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 327 PCCBB_PCMCIA_MEM_32}, 328 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 329 PCCBB_PCMCIA_MEM_32}, 330 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 331 PCCBB_PCMCIA_MEM_32}, 332 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 333 PCCBB_PCMCIA_MEM_32}, 334 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 335 PCCBB_PCMCIA_MEM_32}, 336 337 /* Toshiba products */ 338 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 339 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 340 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 341 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 342 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 343 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 344 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 345 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 346 347 /* Cirrus Logic products */ 348 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 349 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 350 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 351 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 352 353 /* O2 Micro products */ 354 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6729), 355 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 356 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6730), 357 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 358 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6832), 359 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 360 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6836), 361 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 362 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6872), 363 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 364 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6922), 365 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 366 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6933), 367 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 368 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6972), 369 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 370 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_7223), 371 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 372 373 /* sentinel, or Generic chip */ 374 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 375 }; 376 377 static int 378 cb_chipset(u_int32_t pci_id, int *flagp) 379 { 380 const struct yenta_chipinfo *yc; 381 382 /* Loop over except the last default entry. */ 383 for (yc = yc_chipsets; yc < yc_chipsets + 384 __arraycount(yc_chipsets) - 1; yc++) 385 if (pci_id == yc->yc_id) 386 break; 387 388 if (flagp != NULL) 389 *flagp = yc->yc_flags; 390 391 return (yc->yc_chiptype); 392 } 393 394 void 395 pccbbchilddet(device_t self, device_t child) 396 { 397 struct pccbb_softc *sc = device_private(self); 398 int s; 399 400 KASSERT(sc->sc_csc == device_private(child)); 401 402 s = splbio(); 403 if (sc->sc_csc == device_private(child)) 404 sc->sc_csc = NULL; 405 splx(s); 406 } 407 408 void 409 pccbbattach(device_t parent, device_t self, void *aux) 410 { 411 struct pccbb_softc *sc = device_private(self); 412 struct pci_attach_args *pa = aux; 413 pci_chipset_tag_t pc = pa->pa_pc; 414 pcireg_t busreg, reg, sock_base; 415 bus_addr_t sockbase; 416 char devinfo[256]; 417 int flags; 418 419 #ifdef __HAVE_PCCBB_ATTACH_HOOK 420 pccbb_attach_hook(parent, self, pa); 421 #endif 422 423 sc->sc_dev = self; 424 425 mutex_init(&sc->sc_pwr_mtx, MUTEX_DEFAULT, IPL_BIO); 426 cv_init(&sc->sc_pwr_cv, "pccpwr"); 427 428 callout_init(&sc->sc_insert_ch, 0); 429 callout_setfunc(&sc->sc_insert_ch, pci113x_insert, sc); 430 431 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 432 433 aprint_naive("\n"); 434 435 pci_devinfo(pa->pa_id, 0, 0, devinfo, sizeof(devinfo)); 436 aprint_normal(": %s (rev. 0x%02x)", devinfo, 437 PCI_REVISION(pa->pa_class)); 438 DPRINTF((" (chipflags %x)", flags)); 439 aprint_normal("\n"); 440 441 TAILQ_INIT(&sc->sc_memwindow); 442 TAILQ_INIT(&sc->sc_iowindow); 443 444 #if rbus 445 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 446 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 447 448 #if 0 449 printf("pa->pa_memt: %08x vs rbus_mem->rb_bt: %08x\n", 450 pa->pa_memt, sc->sc_rbus_memt->rb_bt); 451 #endif 452 #endif /* rbus */ 453 454 sc->sc_flags &= ~CBB_MEMHMAPPED; 455 456 /* 457 * MAP socket registers and ExCA registers on memory-space 458 * When no valid address is set on socket base registers (on pci 459 * config space), get it not polite way. 460 */ 461 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 462 463 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 464 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 465 /* The address must be valid. */ 466 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 467 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, &sc->sc_base_size)) { 468 aprint_error_dev(self, 469 "can't map socket base address 0x%lx\n", 470 (unsigned long)sock_base); 471 /* 472 * I think it's funny: socket base registers must be 473 * mapped on memory space, but ... 474 */ 475 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 476 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 477 &sc->sc_base_size)) { 478 aprint_error_dev(self, 479 "can't map socket base address" 480 " 0x%lx: io mode\n", 481 (unsigned long)sockbase); 482 /* give up... allocate reg space via rbus. */ 483 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 484 } else 485 sc->sc_flags |= CBB_MEMHMAPPED; 486 } else { 487 DPRINTF(("%s: socket base address 0x%lx\n", 488 device_xname(self), 489 (unsigned long)sockbase)); 490 sc->sc_flags |= CBB_MEMHMAPPED; 491 } 492 } 493 494 sc->sc_mem_start = 0; /* XXX */ 495 sc->sc_mem_end = 0xffffffff; /* XXX */ 496 497 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 498 499 /* pccbb_machdep.c end */ 500 501 #if defined CBB_DEBUG 502 { 503 static const char *intrname[] = { "NON", "A", "B", "C", "D" }; 504 aprint_debug_dev(self, "intrpin %s, intrtag %d\n", 505 intrname[pa->pa_intrpin], pa->pa_intrline); 506 } 507 #endif 508 509 /* setup softc */ 510 sc->sc_pc = pc; 511 sc->sc_iot = pa->pa_iot; 512 sc->sc_memt = pa->pa_memt; 513 sc->sc_dmat = pa->pa_dmat; 514 sc->sc_tag = pa->pa_tag; 515 516 memcpy(&sc->sc_pa, pa, sizeof(*pa)); 517 518 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 519 520 /* Disable legacy register mapping. */ 521 switch (sc->sc_chipset) { 522 case CB_RX5C46X: /* fallthrough */ 523 #if 0 524 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 525 case CB_RX5C47X: 526 #endif 527 /* 528 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 529 * cannot be disabled by substituting 0 into PCI_LEGACY 530 * register. Ricoh CardBus bridges have special bits on Bridge 531 * control reg (addr 0x3e on PCI config space). 532 */ 533 reg = pci_conf_read(pc, pa->pa_tag, PCI_BRIDGE_CONTROL_REG); 534 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 535 pci_conf_write(pc, pa->pa_tag, PCI_BRIDGE_CONTROL_REG, reg); 536 break; 537 538 default: 539 /* XXX I don't know proper way to kill legacy I/O. */ 540 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 541 break; 542 } 543 544 if (!pmf_device_register(self, pccbb_suspend, pccbb_resume)) 545 aprint_error_dev(self, "couldn't establish power handler\n"); 546 547 config_defer(self, pccbb_pci_callback); 548 } 549 550 int 551 pccbbdetach(device_t self, int flags) 552 { 553 struct pccbb_softc *sc = device_private(self); 554 pci_chipset_tag_t pc = sc->sc_pa.pa_pc; 555 bus_space_tag_t bmt = sc->sc_base_memt; 556 bus_space_handle_t bmh = sc->sc_base_memh; 557 uint32_t sockmask; 558 int rc; 559 560 if ((rc = config_detach_children(self, flags)) != 0) 561 return rc; 562 563 if (!LIST_EMPTY(&sc->sc_pil)) { 564 panic("%s: interrupt handlers still registered", 565 device_xname(self)); 566 return EBUSY; 567 } 568 569 if (sc->sc_ih != NULL) { 570 pci_intr_disestablish(pc, sc->sc_ih); 571 sc->sc_ih = NULL; 572 } 573 574 /* CSC Interrupt: turn off card detect and power cycle interrupts */ 575 sockmask = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 576 sockmask &= ~(CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | 577 CB_SOCKET_MASK_POWER); 578 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, sockmask); 579 /* reset interrupt */ 580 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 581 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 582 583 switch (sc->sc_flags & (CBB_MEMHMAPPED|CBB_SPECMAPPED)) { 584 case CBB_MEMHMAPPED: 585 bus_space_unmap(bmt, bmh, sc->sc_base_size); 586 break; 587 case CBB_MEMHMAPPED|CBB_SPECMAPPED: 588 #if rbus 589 { 590 pcireg_t sockbase; 591 592 sockbase = pci_conf_read(pc, sc->sc_tag, PCI_SOCKBASE); 593 rbus_space_free(sc->sc_rbus_memt, bmh, 0x1000, 594 NULL); 595 } 596 #else 597 bus_space_free(bmt, bmh, 0x1000); 598 #endif 599 } 600 sc->sc_flags &= ~(CBB_MEMHMAPPED|CBB_SPECMAPPED); 601 602 if (!TAILQ_EMPTY(&sc->sc_iowindow)) 603 aprint_error_dev(self, "i/o windows not empty"); 604 if (!TAILQ_EMPTY(&sc->sc_memwindow)) 605 aprint_error_dev(self, "memory windows not empty"); 606 607 callout_stop(&sc->sc_insert_ch); 608 callout_destroy(&sc->sc_insert_ch); 609 610 mutex_destroy(&sc->sc_pwr_mtx); 611 cv_destroy(&sc->sc_pwr_cv); 612 613 return 0; 614 } 615 616 /* 617 * static void pccbb_pci_callback(device_t self) 618 * 619 * The actual attach routine: get memory space for YENTA register 620 * space, setup YENTA register and route interrupt. 621 * 622 * This function should be deferred because this device may obtain 623 * memory space dynamically. This function must avoid obtaining 624 * memory area which has already kept for another device. 625 */ 626 static void 627 pccbb_pci_callback(device_t self) 628 { 629 struct pccbb_softc *sc = device_private(self); 630 pci_chipset_tag_t pc = sc->sc_pc; 631 bus_addr_t sockbase; 632 struct cbslot_attach_args cba; 633 struct pcmciabus_attach_args paa; 634 struct cardslot_attach_args caa; 635 device_t csc; 636 637 if (!(sc->sc_flags & CBB_MEMHMAPPED)) { 638 /* The socket registers aren't mapped correctly. */ 639 #if rbus 640 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 641 (sc->sc_chipset == CB_RX5C47X 642 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 643 0, &sockbase, &sc->sc_base_memh)) { 644 return; 645 } 646 sc->sc_base_memt = sc->sc_memt; 647 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 648 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 649 device_xname(self), (unsigned long)sockbase, 650 (unsigned long)pci_conf_read(pc, sc->sc_tag, 651 PCI_SOCKBASE))); 652 #else 653 sc->sc_base_memt = sc->sc_memt; 654 #if !defined CBB_PCI_BASE 655 #define CBB_PCI_BASE 0x20000000 656 #endif 657 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 658 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 659 /* cannot allocate memory space */ 660 return; 661 } 662 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 663 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 664 device_xname(self), (unsigned long)sock_base, 665 (unsigned long)pci_conf_read(pc, 666 sc->sc_tag, PCI_SOCKBASE))); 667 #endif 668 sc->sc_flags |= CBB_MEMHMAPPED|CBB_SPECMAPPED; 669 } 670 671 /* clear data structure for child device interrupt handlers */ 672 LIST_INIT(&sc->sc_pil); 673 674 /* bus bridge initialization */ 675 pccbb_chipinit(sc); 676 677 sc->sc_pil_intr_enable = 1; 678 679 { 680 u_int32_t sockstat; 681 682 sockstat = bus_space_read_4(sc->sc_base_memt, 683 sc->sc_base_memh, CB_SOCKET_STAT); 684 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 685 sc->sc_flags |= CBB_CARDEXIST; 686 } 687 } 688 689 /* 690 * attach cardbus 691 */ 692 { 693 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 694 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 695 696 /* initialize cbslot_attach */ 697 cba.cba_iot = sc->sc_iot; 698 cba.cba_memt = sc->sc_memt; 699 cba.cba_dmat = sc->sc_dmat; 700 cba.cba_bus = (busreg >> 8) & 0x0ff; 701 cba.cba_cc = (void *)sc; 702 cba.cba_cf = &pccbb_funcs; 703 cba.cba_intrline = 0; /* XXX dummy */ 704 705 #if rbus 706 cba.cba_rbus_iot = sc->sc_rbus_iot; 707 cba.cba_rbus_memt = sc->sc_rbus_memt; 708 #endif 709 710 cba.cba_cacheline = PCI_CACHELINE(bhlc); 711 cba.cba_max_lattimer = PCI_LATTIMER(bhlc); 712 713 aprint_verbose_dev(self, 714 "cacheline 0x%x lattimer 0x%x\n", 715 cba.cba_cacheline, 716 cba.cba_max_lattimer); 717 aprint_verbose_dev(self, "bhlc 0x%x\n", bhlc); 718 #if defined SHOW_REGS 719 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 720 sc->sc_base_memh); 721 #endif 722 } 723 724 pccbb_pcmcia_attach_setup(sc, &paa); 725 caa.caa_cb_attach = NULL; 726 if (cba.cba_bus == 0) 727 aprint_error_dev(self, 728 "secondary bus number uninitialized; try PCI_BUS_FIXUP\n"); 729 else 730 caa.caa_cb_attach = &cba; 731 caa.caa_16_attach = &paa; 732 733 pccbb_intrinit(sc); 734 735 if (NULL != (csc = config_found_ia(self, "pcmciaslot", &caa, 736 cbbprint))) { 737 DPRINTF(("%s: found cardslot\n", __func__)); 738 sc->sc_csc = device_private(csc); 739 } 740 741 return; 742 } 743 744 745 746 747 748 /* 749 * static void pccbb_chipinit(struct pccbb_softc *sc) 750 * 751 * This function initialize YENTA chip registers listed below: 752 * 1) PCI command reg, 753 * 2) PCI and CardBus latency timer, 754 * 3) route PCI interrupt, 755 * 4) close all memory and io windows. 756 * 5) turn off bus power. 757 * 6) card detect and power cycle interrupts on. 758 * 7) clear interrupt 759 */ 760 static void 761 pccbb_chipinit(struct pccbb_softc *sc) 762 { 763 pci_chipset_tag_t pc = sc->sc_pc; 764 pcitag_t tag = sc->sc_tag; 765 bus_space_tag_t bmt = sc->sc_base_memt; 766 bus_space_handle_t bmh = sc->sc_base_memh; 767 pcireg_t bcr, bhlc, cbctl, csr, lscp, mfunc, mrburst, slotctl, sockctl, 768 sysctrl; 769 770 /* 771 * Set PCI command reg. 772 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 773 */ 774 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 775 /* I believe it is harmless. */ 776 csr |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 777 PCI_COMMAND_MASTER_ENABLE); 778 779 /* All O2 Micro chips have broken parity-error reporting 780 * until proven otherwise. The OZ6933 PCI-CardBus Bridge 781 * is known to have the defect---see PR kern/38698. 782 */ 783 if (sc->sc_chipset != CB_O2MICRO) 784 csr |= PCI_COMMAND_PARITY_ENABLE; 785 786 csr |= PCI_COMMAND_SERR_ENABLE; 787 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 788 789 /* 790 * Set CardBus latency timer. 791 */ 792 lscp = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 793 if (PCI_CB_LATENCY(lscp) < 0x20) { 794 lscp &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 795 lscp |= (0x20 << PCI_CB_LATENCY_SHIFT); 796 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, lscp); 797 } 798 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 799 PCI_CB_LATENCY(lscp), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 800 801 /* 802 * Set PCI latency timer. 803 */ 804 bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG); 805 if (PCI_LATTIMER(bhlc) < 0x10) { 806 bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 807 bhlc |= (0x10 << PCI_LATTIMER_SHIFT); 808 pci_conf_write(pc, tag, PCI_BHLC_REG, bhlc); 809 } 810 DPRINTF(("PCI latency timer 0x%x (%x)\n", 811 PCI_LATTIMER(bhlc), pci_conf_read(pc, tag, PCI_BHLC_REG))); 812 813 814 /* Route functional interrupts to PCI. */ 815 bcr = pci_conf_read(pc, tag, PCI_BRIDGE_CONTROL_REG); 816 bcr |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 817 bcr |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 818 /* assert reset */ 819 bcr |= PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT; 820 /* Set master abort mode to 1, forward SERR# from secondary 821 * to primary, and detect parity errors on secondary. 822 */ 823 bcr |= PCI_BRIDGE_CONTROL_MABRT << PCI_BRIDGE_CONTROL_SHIFT; 824 bcr |= PCI_BRIDGE_CONTROL_SERR << PCI_BRIDGE_CONTROL_SHIFT; 825 bcr |= PCI_BRIDGE_CONTROL_PERE << PCI_BRIDGE_CONTROL_SHIFT; 826 pci_conf_write(pc, tag, PCI_BRIDGE_CONTROL_REG, bcr); 827 828 switch (sc->sc_chipset) { 829 case CB_TI113X: 830 cbctl = pci_conf_read(pc, tag, PCI_CBCTRL); 831 /* This bit is shared, but may read as 0 on some chips, so set 832 it explicitly on both functions. */ 833 cbctl |= PCI113X_CBCTRL_PCI_IRQ_ENA; 834 /* CSC intr enable */ 835 cbctl |= PCI113X_CBCTRL_PCI_CSC; 836 /* functional intr prohibit | prohibit ISA routing */ 837 cbctl &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 838 pci_conf_write(pc, tag, PCI_CBCTRL, cbctl); 839 break; 840 841 case CB_TI1420: 842 sysctrl = pci_conf_read(pc, tag, PCI_SYSCTRL); 843 mrburst = pccbb_burstup 844 ? PCI1420_SYSCTRL_MRBURST : PCI1420_SYSCTRL_MRBURSTDN; 845 if ((sysctrl & PCI1420_SYSCTRL_MRBURST) == mrburst) { 846 printf("%s: %swrite bursts enabled\n", 847 device_xname(sc->sc_dev), 848 pccbb_burstup ? "read/" : ""); 849 } else if (pccbb_burstup) { 850 printf("%s: enabling read/write bursts\n", 851 device_xname(sc->sc_dev)); 852 sysctrl |= PCI1420_SYSCTRL_MRBURST; 853 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 854 } else { 855 printf("%s: disabling read bursts, " 856 "enabling write bursts\n", 857 device_xname(sc->sc_dev)); 858 sysctrl |= PCI1420_SYSCTRL_MRBURSTDN; 859 sysctrl &= ~PCI1420_SYSCTRL_MRBURSTUP; 860 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 861 } 862 /*FALLTHROUGH*/ 863 case CB_TI12XX: 864 /* 865 * Some TI 12xx (and [14][45]xx) based pci cards 866 * sometimes have issues with the MFUNC register not 867 * being initialized due to a bad EEPROM on board. 868 * Laptops that this matters on have this register 869 * properly initialized. 870 * 871 * The TI125X parts have a different register. 872 */ 873 mfunc = pci_conf_read(pc, tag, PCI12XX_MFUNC); 874 if (mfunc == 0) { 875 mfunc &= ~PCI12XX_MFUNC_PIN0; 876 mfunc |= PCI12XX_MFUNC_PIN0_INTA; 877 if ((pci_conf_read(pc, tag, PCI_SYSCTRL) & 878 PCI12XX_SYSCTRL_INTRTIE) == 0) { 879 mfunc &= ~PCI12XX_MFUNC_PIN1; 880 mfunc |= PCI12XX_MFUNC_PIN1_INTB; 881 } 882 pci_conf_write(pc, tag, PCI12XX_MFUNC, mfunc); 883 } 884 /* fallthrough */ 885 886 case CB_TI125X: 887 /* 888 * Disable zoom video. Some machines initialize this 889 * improperly and experience has shown that this helps 890 * prevent strange behavior. 891 */ 892 pci_conf_write(pc, tag, PCI12XX_MMCTRL, 0); 893 894 sysctrl = pci_conf_read(pc, tag, PCI_SYSCTRL); 895 sysctrl |= PCI12XX_SYSCTRL_VCCPROT; 896 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 897 cbctl = pci_conf_read(pc, tag, PCI_CBCTRL); 898 cbctl |= PCI12XX_CBCTRL_CSC; 899 pci_conf_write(pc, tag, PCI_CBCTRL, cbctl); 900 break; 901 902 case CB_TOPIC95B: 903 sockctl = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 904 sockctl |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 905 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, sockctl); 906 slotctl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 907 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 908 device_xname(sc->sc_dev), slotctl)); 909 slotctl |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 910 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 911 slotctl &= ~TOPIC_SLOT_CTRL_SWDETECT; 912 DPRINTF(("0x%x\n", slotctl)); 913 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slotctl); 914 break; 915 916 case CB_TOPIC97: 917 slotctl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 918 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 919 device_xname(sc->sc_dev), slotctl)); 920 slotctl |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 921 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 922 slotctl &= ~TOPIC_SLOT_CTRL_SWDETECT; 923 slotctl |= TOPIC97_SLOT_CTRL_PCIINT; 924 slotctl &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 925 DPRINTF(("0x%x\n", slotctl)); 926 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slotctl); 927 /* make sure to assert LV card support bits */ 928 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 929 0x800 + 0x3e, 930 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 931 0x800 + 0x3e) | 0x03); 932 break; 933 } 934 935 /* Close all memory and I/O windows. */ 936 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 937 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 938 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 939 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 940 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 941 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 942 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 943 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 944 945 /* reset 16-bit pcmcia bus */ 946 bus_space_write_1(bmt, bmh, 0x800 + PCIC_INTR, 947 bus_space_read_1(bmt, bmh, 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 948 949 /* turn off power */ 950 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 951 } 952 953 static void 954 pccbb_intrinit(struct pccbb_softc *sc) 955 { 956 pcireg_t sockmask; 957 const char *intrstr = NULL; 958 pci_intr_handle_t ih; 959 pci_chipset_tag_t pc = sc->sc_pc; 960 bus_space_tag_t bmt = sc->sc_base_memt; 961 bus_space_handle_t bmh = sc->sc_base_memh; 962 963 /* Map and establish the interrupt. */ 964 if (pci_intr_map(&sc->sc_pa, &ih)) { 965 aprint_error_dev(sc->sc_dev, "couldn't map interrupt\n"); 966 return; 967 } 968 intrstr = pci_intr_string(pc, ih); 969 970 /* 971 * XXX pccbbintr should be called under the priority lower 972 * than any other hard interrupts. 973 */ 974 KASSERT(sc->sc_ih == NULL); 975 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 976 977 if (sc->sc_ih == NULL) { 978 aprint_error_dev(sc->sc_dev, "couldn't establish interrupt"); 979 if (intrstr != NULL) 980 aprint_error(" at %s\n", intrstr); 981 else 982 aprint_error("\n"); 983 return; 984 } 985 986 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 987 988 /* CSC Interrupt: Card detect and power cycle interrupts on */ 989 sockmask = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 990 sockmask |= CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | 991 CB_SOCKET_MASK_POWER; 992 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, sockmask); 993 /* reset interrupt */ 994 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 995 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 996 } 997 998 /* 999 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 1000 * struct pcmciabus_attach_args *paa) 1001 * 1002 * This function attaches 16-bit PCcard bus. 1003 */ 1004 STATIC void 1005 pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 1006 struct pcmciabus_attach_args *paa) 1007 { 1008 #if rbus 1009 rbus_tag_t rb; 1010 #endif 1011 /* 1012 * We need to do a few things here: 1013 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 1014 * setting the IRQ numbers to 0. 1015 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 1016 * routing of CSC interrupts (e.g. card removal) to PCI while in 1017 * PCMCIA mode. We just leave this set all the time. 1018 * 3) Enable card insertion/removal interrupts in case the chip also 1019 * needs that while in PCMCIA mode. 1020 * 4) Clear any pending CSC interrupt. 1021 */ 1022 Pcic_write(sc, PCIC_INTR, PCIC_INTR_ENABLE); 1023 if (sc->sc_chipset == CB_TI113X) { 1024 Pcic_write(sc, PCIC_CSC_INTR, 0); 1025 } else { 1026 Pcic_write(sc, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 1027 Pcic_read(sc, PCIC_CSC); 1028 } 1029 1030 /* initialize pcmcia bus attachment */ 1031 paa->paa_busname = "pcmcia"; 1032 paa->pct = &pccbb_pcmcia_funcs; 1033 paa->pch = sc; 1034 paa->iobase = 0; /* I don't use them */ 1035 paa->iosize = 0; 1036 #if rbus 1037 rb = sc->sc_rbus_iot; 1038 paa->iobase = rb->rb_start + rb->rb_offset; 1039 paa->iosize = rb->rb_end - rb->rb_start; 1040 #endif 1041 1042 return; 1043 } 1044 1045 /* 1046 * int pccbbintr(arg) 1047 * void *arg; 1048 * This routine handles the interrupt from Yenta PCI-CardBus bridge 1049 * itself. 1050 */ 1051 int 1052 pccbbintr(void *arg) 1053 { 1054 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1055 struct cardslot_softc *csc; 1056 u_int32_t sockevent, sockstate; 1057 bus_space_tag_t memt = sc->sc_base_memt; 1058 bus_space_handle_t memh = sc->sc_base_memh; 1059 1060 if (!device_has_power(sc->sc_dev)) 1061 return 0; 1062 1063 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 1064 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 1065 Pcic_read(sc, PCIC_CSC); 1066 1067 if (sockevent != 0) { 1068 aprint_debug("%s: enter sockevent %" PRIx32 "\n", __func__, 1069 sockevent); 1070 } 1071 1072 /* XXX sockevent == CB_SOCKET_EVENT_CSTS|CB_SOCKET_EVENT_POWER 1073 * does occur in the wild. Check for a _POWER event before 1074 * possibly exiting because of an _CSTS event. 1075 */ 1076 if (sockevent & CB_SOCKET_EVENT_POWER) { 1077 DPRINTF(("Powercycling because of socket event\n")); 1078 /* XXX: Does not happen when attaching a 16-bit card */ 1079 mutex_enter(&sc->sc_pwr_mtx); 1080 sc->sc_pwrcycle++; 1081 cv_signal(&sc->sc_pwr_cv); 1082 mutex_exit(&sc->sc_pwr_mtx); 1083 } 1084 1085 /* Sometimes a change of CSTSCHG# accompanies the first 1086 * interrupt from an Atheros WLAN. That generates a 1087 * CB_SOCKET_EVENT_CSTS event on the bridge. The event 1088 * isn't interesting to pccbb(4), so we used to ignore the 1089 * interrupt. Now, let the child devices try to handle 1090 * the interrupt, instead. The Atheros NIC produces 1091 * interrupts more reliably, now: used to be that it would 1092 * only interrupt if the driver avoided powering down the 1093 * NIC's cardslot, and then the NIC would only work after 1094 * it was reset a second time. 1095 */ 1096 if (sockevent == 0 || 1097 (sockevent & ~(CB_SOCKET_EVENT_POWER|CB_SOCKET_EVENT_CD)) != 0) { 1098 /* This intr is not for me: it may be for my child devices. */ 1099 if (sc->sc_pil_intr_enable) { 1100 return pccbbintr_function(sc); 1101 } else { 1102 return 0; 1103 } 1104 } 1105 1106 if (sockevent & CB_SOCKET_EVENT_CD) { 1107 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1108 if (0x00 != (sockstate & CB_SOCKET_STAT_CD)) { 1109 /* A card should be removed. */ 1110 if (sc->sc_flags & CBB_CARDEXIST) { 1111 DPRINTF(("%s: 0x%08x", 1112 device_xname(sc->sc_dev), sockevent)); 1113 DPRINTF((" card removed, 0x%08x\n", sockstate)); 1114 sc->sc_flags &= ~CBB_CARDEXIST; 1115 if ((csc = sc->sc_csc) == NULL) 1116 ; 1117 else if (csc->sc_status & 1118 CARDSLOT_STATUS_CARD_16) { 1119 cardslot_event_throw(csc, 1120 CARDSLOT_EVENT_REMOVAL_16); 1121 } else if (csc->sc_status & 1122 CARDSLOT_STATUS_CARD_CB) { 1123 /* Cardbus intr removed */ 1124 cardslot_event_throw(csc, 1125 CARDSLOT_EVENT_REMOVAL_CB); 1126 } 1127 } else if (sc->sc_flags & CBB_INSERTING) { 1128 sc->sc_flags &= ~CBB_INSERTING; 1129 callout_stop(&sc->sc_insert_ch); 1130 } 1131 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 1132 /* 1133 * The pccbbintr may called from powerdown hook when 1134 * the system resumed, to detect the card 1135 * insertion/removal during suspension. 1136 */ 1137 (sc->sc_flags & CBB_CARDEXIST) == 0) { 1138 if (sc->sc_flags & CBB_INSERTING) { 1139 callout_stop(&sc->sc_insert_ch); 1140 } 1141 callout_schedule(&sc->sc_insert_ch, mstohz(200)); 1142 sc->sc_flags |= CBB_INSERTING; 1143 } 1144 } 1145 1146 return (1); 1147 } 1148 1149 /* 1150 * static int pccbbintr_function(struct pccbb_softc *sc) 1151 * 1152 * This function calls each interrupt handler registered at the 1153 * bridge. The interrupt handlers are called in registered order. 1154 */ 1155 static int 1156 pccbbintr_function(struct pccbb_softc *sc) 1157 { 1158 int retval = 0, val; 1159 struct pccbb_intrhand_list *pil; 1160 int s; 1161 1162 LIST_FOREACH(pil, &sc->sc_pil, pil_next) { 1163 s = splraiseipl(pil->pil_icookie); 1164 val = (*pil->pil_func)(pil->pil_arg); 1165 splx(s); 1166 1167 retval = retval == 1 ? 1 : 1168 retval == 0 ? val : val != 0 ? val : retval; 1169 } 1170 1171 return retval; 1172 } 1173 1174 static void 1175 pci113x_insert(void *arg) 1176 { 1177 struct pccbb_softc *sc = arg; 1178 struct cardslot_softc *csc; 1179 u_int32_t sockevent, sockstate; 1180 1181 if (!(sc->sc_flags & CBB_INSERTING)) { 1182 /* We add a card only under inserting state. */ 1183 return; 1184 } 1185 sc->sc_flags &= ~CBB_INSERTING; 1186 1187 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1188 CB_SOCKET_EVENT); 1189 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1190 CB_SOCKET_STAT); 1191 1192 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1193 DPRINTF(("%s: 0x%08x", device_xname(sc->sc_dev), sockevent)); 1194 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1195 sc->sc_flags |= CBB_CARDEXIST; 1196 /* call pccard interrupt handler here */ 1197 if ((csc = sc->sc_csc) == NULL) 1198 ; 1199 else if (sockstate & CB_SOCKET_STAT_16BIT) { 1200 /* 16-bit card found */ 1201 cardslot_event_throw(csc, CARDSLOT_EVENT_INSERTION_16); 1202 } else if (sockstate & CB_SOCKET_STAT_CB) { 1203 /* cardbus card found */ 1204 cardslot_event_throw(csc, CARDSLOT_EVENT_INSERTION_CB); 1205 } else { 1206 /* who are you? */ 1207 } 1208 } else { 1209 callout_schedule(&sc->sc_insert_ch, mstohz(100)); 1210 } 1211 } 1212 1213 #define PCCBB_PCMCIA_OFFSET 0x800 1214 static u_int8_t 1215 pccbb_pcmcia_read(struct pccbb_softc *sc, int reg) 1216 { 1217 bus_space_barrier(sc->sc_base_memt, sc->sc_base_memh, 1218 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1219 1220 return bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 1221 PCCBB_PCMCIA_OFFSET + reg); 1222 } 1223 1224 static void 1225 pccbb_pcmcia_write(struct pccbb_softc *sc, int reg, u_int8_t val) 1226 { 1227 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 1228 PCCBB_PCMCIA_OFFSET + reg, val); 1229 1230 bus_space_barrier(sc->sc_base_memt, sc->sc_base_memh, 1231 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1232 } 1233 1234 /* 1235 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1236 */ 1237 STATIC int 1238 pccbb_ctrl(cardbus_chipset_tag_t ct, int command) 1239 { 1240 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1241 1242 switch (command) { 1243 case CARDBUS_CD: 1244 if (2 == pccbb_detect_card(sc)) { 1245 int retval = 0; 1246 int status = cb_detect_voltage(sc); 1247 if (PCCARD_VCC_5V & status) { 1248 retval |= CARDBUS_5V_CARD; 1249 } 1250 if (PCCARD_VCC_3V & status) { 1251 retval |= CARDBUS_3V_CARD; 1252 } 1253 if (PCCARD_VCC_XV & status) { 1254 retval |= CARDBUS_XV_CARD; 1255 } 1256 if (PCCARD_VCC_YV & status) { 1257 retval |= CARDBUS_YV_CARD; 1258 } 1259 return retval; 1260 } else { 1261 return 0; 1262 } 1263 case CARDBUS_RESET: 1264 return cb_reset(sc); 1265 case CARDBUS_IO_ENABLE: /* fallthrough */ 1266 case CARDBUS_IO_DISABLE: /* fallthrough */ 1267 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1268 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1269 case CARDBUS_BM_ENABLE: /* fallthrough */ 1270 case CARDBUS_BM_DISABLE: /* fallthrough */ 1271 /* XXX: I think we don't need to call this function below. */ 1272 return pccbb_cardenable(sc, command); 1273 } 1274 1275 return 0; 1276 } 1277 1278 STATIC int 1279 pccbb_power_ct(cardbus_chipset_tag_t ct, int command) 1280 { 1281 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1282 1283 return pccbb_power(sc, command); 1284 } 1285 1286 /* 1287 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1288 * This function returns true when it succeeds and returns false when 1289 * it fails. 1290 */ 1291 STATIC int 1292 pccbb_power(struct pccbb_softc *sc, int command) 1293 { 1294 u_int32_t status, osock_ctrl, sock_ctrl, reg_ctrl; 1295 bus_space_tag_t memt = sc->sc_base_memt; 1296 bus_space_handle_t memh = sc->sc_base_memh; 1297 int on = 0, pwrcycle, times; 1298 struct timeval before, after, diff; 1299 1300 DPRINTF(("pccbb_power: %s and %s [0x%x]\n", 1301 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1302 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1303 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1304 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1305 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1306 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1307 "UNKNOWN", 1308 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1309 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1310 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1311 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1312 "UNKNOWN", command)); 1313 1314 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1315 osock_ctrl = sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1316 1317 switch (command & CARDBUS_VCCMASK) { 1318 case CARDBUS_VCC_UC: 1319 break; 1320 case CARDBUS_VCC_5V: 1321 on++; 1322 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1323 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1324 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1325 } else { 1326 aprint_error_dev(sc->sc_dev, 1327 "BAD voltage request: no 5 V card\n"); 1328 return 0; 1329 } 1330 break; 1331 case CARDBUS_VCC_3V: 1332 on++; 1333 if (CB_SOCKET_STAT_3VCARD & status) { 1334 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1335 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1336 } else { 1337 aprint_error_dev(sc->sc_dev, 1338 "BAD voltage request: no 3.3 V card\n"); 1339 return 0; 1340 } 1341 break; 1342 case CARDBUS_VCC_0V: 1343 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1344 break; 1345 default: 1346 return 0; /* power NEVER changed */ 1347 } 1348 1349 switch (command & CARDBUS_VPPMASK) { 1350 case CARDBUS_VPP_UC: 1351 break; 1352 case CARDBUS_VPP_0V: 1353 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1354 break; 1355 case CARDBUS_VPP_VCC: 1356 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1357 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1358 break; 1359 case CARDBUS_VPP_12V: 1360 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1361 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1362 break; 1363 } 1364 aprint_debug_dev(sc->sc_dev, "osock_ctrl %#" PRIx32 1365 " sock_ctrl %#" PRIx32 "\n", osock_ctrl, sock_ctrl); 1366 1367 microtime(&before); 1368 mutex_enter(&sc->sc_pwr_mtx); 1369 pwrcycle = sc->sc_pwrcycle; 1370 1371 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1372 1373 /* 1374 * Wait as long as 200ms for a power-cycle interrupt. If 1375 * interrupts are enabled, but the socket has already 1376 * changed to the desired status, keep waiting for the 1377 * interrupt. "Consuming" the interrupt in this way keeps 1378 * the interrupt from prematurely waking some subsequent 1379 * pccbb_power call. 1380 * 1381 * XXX Not every bridge interrupts on the ->OFF transition. 1382 * XXX That's ok, we will time-out after 200ms. 1383 * 1384 * XXX The power cycle event will never happen when attaching 1385 * XXX a 16-bit card. That's ok, we will time-out after 1386 * XXX 200ms. 1387 */ 1388 for (times = 5; --times >= 0; ) { 1389 if (cold) 1390 DELAY(40 * 1000); 1391 else { 1392 (void)cv_timedwait(&sc->sc_pwr_cv, &sc->sc_pwr_mtx, 1393 mstohz(40)); 1394 if (pwrcycle == sc->sc_pwrcycle) 1395 continue; 1396 } 1397 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1398 if ((status & CB_SOCKET_STAT_PWRCYCLE) != 0 && on) 1399 break; 1400 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0 && !on) 1401 break; 1402 } 1403 mutex_exit(&sc->sc_pwr_mtx); 1404 microtime(&after); 1405 timersub(&after, &before, &diff); 1406 aprint_debug_dev(sc->sc_dev, "wait took%s %lld.%06lds\n", 1407 (on && times < 0) ? " too long" : "", (long long)diff.tv_sec, 1408 (long)diff.tv_usec); 1409 1410 /* 1411 * Ok, wait a bit longer for things to settle. 1412 */ 1413 if (on && sc->sc_chipset == CB_TOPIC95B) 1414 delay_ms(100, sc); 1415 1416 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1417 1418 if (on && sc->sc_chipset != CB_TOPIC95B) { 1419 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0) 1420 aprint_error_dev(sc->sc_dev, "power on failed?\n"); 1421 } 1422 1423 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1424 aprint_error_dev(sc->sc_dev, 1425 "bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1426 sock_ctrl, status); 1427 aprint_error_dev(sc->sc_dev, "disabling socket\n"); 1428 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1429 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1430 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1431 status &= ~CB_SOCKET_STAT_BADVCC; 1432 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, status); 1433 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1434 CB_SOCKET_STAT)); 1435 return 0; 1436 } 1437 1438 if (sc->sc_chipset == CB_TOPIC97) { 1439 reg_ctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL); 1440 reg_ctrl &= ~TOPIC97_REG_CTRL_TESTMODE; 1441 if ((command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V) 1442 reg_ctrl &= ~TOPIC97_REG_CTRL_CLKRUN_ENA; 1443 else 1444 reg_ctrl |= TOPIC97_REG_CTRL_CLKRUN_ENA; 1445 pci_conf_write(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL, reg_ctrl); 1446 } 1447 1448 return 1; /* power changed correctly */ 1449 } 1450 1451 /* 1452 * static int pccbb_detect_card(struct pccbb_softc *sc) 1453 * return value: 0 if no card exists. 1454 * 1 if 16-bit card exists. 1455 * 2 if cardbus card exists. 1456 */ 1457 static int 1458 pccbb_detect_card(struct pccbb_softc *sc) 1459 { 1460 bus_space_handle_t base_memh = sc->sc_base_memh; 1461 bus_space_tag_t base_memt = sc->sc_base_memt; 1462 u_int32_t sockstat = 1463 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1464 int retval = 0; 1465 1466 /* CD1 and CD2 asserted */ 1467 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1468 /* card must be present */ 1469 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1470 /* NOTACARD DEASSERTED */ 1471 if (CB_SOCKET_STAT_CB & sockstat) { 1472 /* CardBus mode */ 1473 retval = 2; 1474 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1475 /* 16-bit mode */ 1476 retval = 1; 1477 } 1478 } 1479 } 1480 return retval; 1481 } 1482 1483 /* 1484 * STATIC int cb_reset(struct pccbb_softc *sc) 1485 * This function resets CardBus card. 1486 */ 1487 STATIC int 1488 cb_reset(struct pccbb_softc *sc) 1489 { 1490 /* 1491 * Reset Assert at least 20 ms 1492 * Some machines request longer duration. 1493 */ 1494 int reset_duration = 1495 (sc->sc_chipset == CB_RX5C47X ? 400 : 50); 1496 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1497 aprint_debug("%s: enter bcr %" PRIx32 "\n", __func__, bcr); 1498 1499 /* Reset bit Assert (bit 6 at 0x3E) */ 1500 bcr |= PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT; 1501 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr); 1502 aprint_debug("%s: wrote bcr %" PRIx32 "\n", __func__, bcr); 1503 delay_ms(reset_duration, sc); 1504 1505 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1506 /* Reset bit Deassert (bit 6 at 0x3E) */ 1507 bcr &= ~(PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT); 1508 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, 1509 bcr); 1510 aprint_debug("%s: wrote bcr %" PRIx32 "\n", __func__, bcr); 1511 delay_ms(reset_duration, sc); 1512 aprint_debug("%s: end of delay\n", __func__); 1513 } 1514 /* No card found on the slot. Keep Reset. */ 1515 return 1; 1516 } 1517 1518 /* 1519 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1520 * This function detect card Voltage. 1521 */ 1522 STATIC int 1523 cb_detect_voltage(struct pccbb_softc *sc) 1524 { 1525 u_int32_t psr; /* socket present-state reg */ 1526 bus_space_tag_t iot = sc->sc_base_memt; 1527 bus_space_handle_t ioh = sc->sc_base_memh; 1528 int vol = PCCARD_VCC_UKN; /* set 0 */ 1529 1530 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1531 1532 if (0x400u & psr) { 1533 vol |= PCCARD_VCC_5V; 1534 } 1535 if (0x800u & psr) { 1536 vol |= PCCARD_VCC_3V; 1537 } 1538 1539 return vol; 1540 } 1541 1542 STATIC int 1543 cbbprint(void *aux, const char *pcic) 1544 { 1545 #if 0 1546 struct cbslot_attach_args *cba = aux; 1547 1548 if (cba->cba_slot >= 0) { 1549 aprint_normal(" slot %d", cba->cba_slot); 1550 } 1551 #endif 1552 return UNCONF; 1553 } 1554 1555 /* 1556 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1557 * This function enables and disables the card 1558 */ 1559 STATIC int 1560 pccbb_cardenable(struct pccbb_softc *sc, int function) 1561 { 1562 u_int32_t command = 1563 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1564 1565 DPRINTF(("pccbb_cardenable:")); 1566 switch (function) { 1567 case CARDBUS_IO_ENABLE: 1568 command |= PCI_COMMAND_IO_ENABLE; 1569 break; 1570 case CARDBUS_IO_DISABLE: 1571 command &= ~PCI_COMMAND_IO_ENABLE; 1572 break; 1573 case CARDBUS_MEM_ENABLE: 1574 command |= PCI_COMMAND_MEM_ENABLE; 1575 break; 1576 case CARDBUS_MEM_DISABLE: 1577 command &= ~PCI_COMMAND_MEM_ENABLE; 1578 break; 1579 case CARDBUS_BM_ENABLE: 1580 command |= PCI_COMMAND_MASTER_ENABLE; 1581 break; 1582 case CARDBUS_BM_DISABLE: 1583 command &= ~PCI_COMMAND_MASTER_ENABLE; 1584 break; 1585 default: 1586 return 0; 1587 } 1588 1589 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1590 DPRINTF((" command reg 0x%x\n", command)); 1591 return 1; 1592 } 1593 1594 #if !rbus 1595 static int 1596 pccbb_io_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 1597 { 1598 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1599 int basereg; 1600 int limitreg; 1601 1602 if ((win < 0) || (win > 2)) { 1603 #if defined DIAGNOSTIC 1604 printf("cardbus_io_open: window out of range %d\n", win); 1605 #endif 1606 return 0; 1607 } 1608 1609 basereg = win * 8 + PCI_CB_IOBASE0; 1610 limitreg = win * 8 + PCI_CB_IOLIMIT0; 1611 1612 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1613 start, basereg, end, limitreg)); 1614 1615 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1616 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1617 return 1; 1618 } 1619 1620 /* 1621 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1622 */ 1623 static int 1624 pccbb_io_close(cardbus_chipset_tag_t ct, int win) 1625 { 1626 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1627 int basereg; 1628 int limitreg; 1629 1630 if ((win < 0) || (win > 2)) { 1631 #if defined DIAGNOSTIC 1632 printf("cardbus_io_close: window out of range %d\n", win); 1633 #endif 1634 return 0; 1635 } 1636 1637 basereg = win * 8 + PCI_CB_IOBASE0; 1638 limitreg = win * 8 + PCI_CB_IOLIMIT0; 1639 1640 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1641 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1642 return 1; 1643 } 1644 1645 static int 1646 pccbb_mem_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 1647 { 1648 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1649 int basereg; 1650 int limitreg; 1651 1652 if ((win < 0) || (win > 2)) { 1653 #if defined DIAGNOSTIC 1654 printf("cardbus_mem_open: window out of range %d\n", win); 1655 #endif 1656 return 0; 1657 } 1658 1659 basereg = win * 8 + PCI_CB_MEMBASE0; 1660 limitreg = win * 8 + PCI_CB_MEMLIMIT0; 1661 1662 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1663 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1664 return 1; 1665 } 1666 1667 static int 1668 pccbb_mem_close(cardbus_chipset_tag_t ct, int win) 1669 { 1670 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1671 int basereg; 1672 int limitreg; 1673 1674 if ((win < 0) || (win > 2)) { 1675 #if defined DIAGNOSTIC 1676 printf("cardbus_mem_close: window out of range %d\n", win); 1677 #endif 1678 return 0; 1679 } 1680 1681 basereg = win * 8 + PCI_CB_MEMBASE0; 1682 limitreg = win * 8 + PCI_CB_MEMLIMIT0; 1683 1684 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1685 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1686 return 1; 1687 } 1688 #endif 1689 1690 /* 1691 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1692 * int irq, 1693 * int level, 1694 * int (* func)(void *), 1695 * void *arg) 1696 * 1697 * This function registers an interrupt handler at the bridge, in 1698 * order not to call the interrupt handlers of child devices when 1699 * a card-deletion interrupt occurs. 1700 * 1701 * The arguments irq and level are not used. 1702 */ 1703 static void * 1704 pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, cardbus_intr_line_t irq, 1705 int level, int (*func)(void *), void *arg) 1706 { 1707 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1708 1709 return pccbb_intr_establish(sc, irq, level, func, arg); 1710 } 1711 1712 1713 /* 1714 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1715 * void *ih) 1716 * 1717 * This function removes an interrupt handler pointed by ih. 1718 */ 1719 static void 1720 pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih) 1721 { 1722 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1723 1724 pccbb_intr_disestablish(sc, ih); 1725 } 1726 1727 1728 void 1729 pccbb_intr_route(struct pccbb_softc *sc) 1730 { 1731 pcireg_t bcr, cbctrl; 1732 1733 /* initialize bridge intr routing */ 1734 bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1735 bcr &= ~CB_BCR_INTR_IREQ_ENABLE; 1736 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr); 1737 1738 switch (sc->sc_chipset) { 1739 case CB_TI113X: 1740 cbctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1741 /* functional intr enabled */ 1742 cbctrl |= PCI113X_CBCTRL_PCI_INTR; 1743 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, cbctrl); 1744 break; 1745 default: 1746 break; 1747 } 1748 } 1749 1750 /* 1751 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1752 * int irq, 1753 * int level, 1754 * int (* func)(void *), 1755 * void *arg) 1756 * 1757 * This function registers an interrupt handler at the bridge, in 1758 * order not to call the interrupt handlers of child devices when 1759 * a card-deletion interrupt occurs. 1760 * 1761 * The arguments irq is not used because pccbb selects intr vector. 1762 */ 1763 static void * 1764 pccbb_intr_establish(struct pccbb_softc *sc, cardbus_intr_line_t irq, 1765 int level, int (*func)(void *), void *arg) 1766 { 1767 struct pccbb_intrhand_list *pil, *newpil; 1768 1769 DPRINTF(("pccbb_intr_establish start. %p\n", LIST_FIRST(&sc->sc_pil))); 1770 1771 if (LIST_EMPTY(&sc->sc_pil)) { 1772 pccbb_intr_route(sc); 1773 } 1774 1775 /* 1776 * Allocate a room for interrupt handler structure. 1777 */ 1778 if (NULL == (newpil = 1779 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1780 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1781 return NULL; 1782 } 1783 1784 newpil->pil_func = func; 1785 newpil->pil_arg = arg; 1786 newpil->pil_icookie = makeiplcookie(level); 1787 1788 if (LIST_EMPTY(&sc->sc_pil)) { 1789 LIST_INSERT_HEAD(&sc->sc_pil, newpil, pil_next); 1790 } else { 1791 for (pil = LIST_FIRST(&sc->sc_pil); 1792 LIST_NEXT(pil, pil_next) != NULL; 1793 pil = LIST_NEXT(pil, pil_next)); 1794 LIST_INSERT_AFTER(pil, newpil, pil_next); 1795 } 1796 1797 DPRINTF(("pccbb_intr_establish add pil. %p\n", 1798 LIST_FIRST(&sc->sc_pil))); 1799 1800 return newpil; 1801 } 1802 1803 /* 1804 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1805 * void *ih) 1806 * 1807 * This function removes an interrupt handler pointed by ih. ih 1808 * should be the value returned by cardbus_intr_establish() or 1809 * NULL. 1810 * 1811 * When ih is NULL, this function will do nothing. 1812 */ 1813 static void 1814 pccbb_intr_disestablish(struct pccbb_softc *sc, void *ih) 1815 { 1816 struct pccbb_intrhand_list *pil; 1817 pcireg_t reg; 1818 1819 DPRINTF(("pccbb_intr_disestablish start. %p\n", 1820 LIST_FIRST(&sc->sc_pil))); 1821 1822 if (ih == NULL) { 1823 /* intr handler is not set */ 1824 DPRINTF(("pccbb_intr_disestablish: no ih\n")); 1825 return; 1826 } 1827 1828 #ifdef DIAGNOSTIC 1829 LIST_FOREACH(pil, &sc->sc_pil, pil_next) { 1830 DPRINTF(("pccbb_intr_disestablish: pil %p\n", pil)); 1831 if (pil == ih) { 1832 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1833 break; 1834 } 1835 } 1836 if (pil == NULL) { 1837 panic("pccbb_intr_disestablish: %s cannot find pil %p", 1838 device_xname(sc->sc_dev), ih); 1839 } 1840 #endif 1841 1842 pil = (struct pccbb_intrhand_list *)ih; 1843 LIST_REMOVE(pil, pil_next); 1844 free(pil, M_DEVBUF); 1845 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1846 1847 if (LIST_EMPTY(&sc->sc_pil)) { 1848 /* No interrupt handlers */ 1849 1850 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1851 1852 /* stop routing PCI intr */ 1853 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1854 reg |= CB_BCR_INTR_IREQ_ENABLE; 1855 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, reg); 1856 1857 switch (sc->sc_chipset) { 1858 case CB_TI113X: 1859 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1860 /* functional intr disabled */ 1861 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1862 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1863 break; 1864 default: 1865 break; 1866 } 1867 } 1868 } 1869 1870 #if defined SHOW_REGS 1871 static void 1872 cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, bus_space_tag_t memt, 1873 bus_space_handle_t memh) 1874 { 1875 int i; 1876 printf("PCI config regs:"); 1877 for (i = 0; i < 0x50; i += 4) { 1878 if (i % 16 == 0) 1879 printf("\n 0x%02x:", i); 1880 printf(" %08x", pci_conf_read(pc, tag, i)); 1881 } 1882 for (i = 0x80; i < 0xb0; i += 4) { 1883 if (i % 16 == 0) 1884 printf("\n 0x%02x:", i); 1885 printf(" %08x", pci_conf_read(pc, tag, i)); 1886 } 1887 1888 if (memh == 0) { 1889 printf("\n"); 1890 return; 1891 } 1892 1893 printf("\nsocket regs:"); 1894 for (i = 0; i <= 0x10; i += 0x04) 1895 printf(" %08x", bus_space_read_4(memt, memh, i)); 1896 printf("\nExCA regs:"); 1897 for (i = 0; i < 0x08; ++i) 1898 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1899 printf("\n"); 1900 return; 1901 } 1902 #endif 1903 1904 /* 1905 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1906 * int busno, int function) 1907 * This is the function to make a tag to access config space of 1908 * a CardBus Card. It works same as pci_conf_read. 1909 */ 1910 static cardbustag_t 1911 pccbb_make_tag(cardbus_chipset_tag_t cc, int busno, int function) 1912 { 1913 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1914 1915 return pci_make_tag(sc->sc_pc, busno, 0, function); 1916 } 1917 1918 static void 1919 pccbb_free_tag(cardbus_chipset_tag_t cc, cardbustag_t tag) 1920 { 1921 } 1922 1923 /* 1924 * pccbb_conf_read 1925 * 1926 * This is the function to read the config space of a CardBus card. 1927 * It works the same as pci_conf_read(9). 1928 */ 1929 static cardbusreg_t 1930 pccbb_conf_read(cardbus_chipset_tag_t cc, cardbustag_t tag, int offset) 1931 { 1932 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1933 pcitag_t brtag = sc->sc_tag; 1934 cardbusreg_t reg; 1935 1936 /* 1937 * clear cardbus master abort status; it is OK to write without 1938 * reading before because all bits are r/o or w1tc 1939 */ 1940 pci_conf_write(sc->sc_pc, brtag, PCI_CBB_SECSTATUS, 1941 CBB_SECSTATUS_CBMABORT); 1942 reg = pci_conf_read(sc->sc_pc, tag, offset); 1943 /* check cardbus master abort status */ 1944 if (pci_conf_read(sc->sc_pc, brtag, PCI_CBB_SECSTATUS) 1945 & CBB_SECSTATUS_CBMABORT) 1946 return (0xffffffff); 1947 return reg; 1948 } 1949 1950 /* 1951 * pccbb_conf_write 1952 * 1953 * This is the function to write the config space of a CardBus 1954 * card. It works the same as pci_conf_write(9). 1955 */ 1956 static void 1957 pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, int reg, 1958 cardbusreg_t val) 1959 { 1960 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1961 1962 pci_conf_write(sc->sc_pc, tag, reg, val); 1963 } 1964 1965 #if 0 1966 STATIC int 1967 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1968 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 1969 int speed, int flags, 1970 bus_space_handle_t * iohp) 1971 #endif 1972 /* 1973 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1974 * bus_addr_t start, bus_size_t size, 1975 * bus_size_t align, 1976 * struct pcmcia_io_handle *pcihp 1977 * 1978 * This function only allocates I/O region for pccard. This function 1979 * never maps the allocated region to pccard I/O area. 1980 * 1981 * XXX: The interface of this function is not very good, I believe. 1982 */ 1983 STATIC int 1984 pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, 1985 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 1986 { 1987 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 1988 bus_addr_t ioaddr; 1989 int flags = 0; 1990 bus_space_tag_t iot; 1991 bus_space_handle_t ioh; 1992 bus_addr_t mask; 1993 #if rbus 1994 rbus_tag_t rb; 1995 #endif 1996 if (align == 0) { 1997 align = size; /* XXX: funny??? */ 1998 } 1999 2000 if (start != 0) { 2001 /* XXX: assume all card decode lower 10 bits by its hardware */ 2002 mask = 0x3ff; 2003 /* enforce to use only masked address */ 2004 start &= mask; 2005 } else { 2006 /* 2007 * calculate mask: 2008 * 1. get the most significant bit of size (call it msb). 2009 * 2. compare msb with the value of size. 2010 * 3. if size is larger, shift msb left once. 2011 * 4. obtain mask value to decrement msb. 2012 */ 2013 bus_size_t size_tmp = size; 2014 int shifts = 0; 2015 2016 mask = 1; 2017 while (size_tmp) { 2018 ++shifts; 2019 size_tmp >>= 1; 2020 } 2021 mask = (1 << shifts); 2022 if (mask < size) { 2023 mask <<= 1; 2024 } 2025 --mask; 2026 } 2027 2028 /* 2029 * Allocate some arbitrary I/O space. 2030 */ 2031 2032 iot = sc->sc_iot; 2033 2034 #if rbus 2035 rb = sc->sc_rbus_iot; 2036 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 2037 return 1; 2038 } 2039 DPRINTF(("pccbb_pcmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2040 (u_long) ioaddr, (u_long) size)); 2041 #else 2042 if (start) { 2043 ioaddr = start; 2044 if (bus_space_map(iot, start, size, 0, &ioh)) { 2045 return 1; 2046 } 2047 DPRINTF(("pccbb_pcmcia_io_alloc map port 0x%lx+0x%lx\n", 2048 (u_long) ioaddr, (u_long) size)); 2049 } else { 2050 flags |= PCMCIA_IO_ALLOCATED; 2051 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 2052 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 2053 size, align, 0, 0, &ioaddr, &ioh)) { 2054 /* No room be able to be get. */ 2055 return 1; 2056 } 2057 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2058 (u_long) ioaddr, (u_long) size)); 2059 } 2060 #endif 2061 2062 pcihp->iot = iot; 2063 pcihp->ioh = ioh; 2064 pcihp->addr = ioaddr; 2065 pcihp->size = size; 2066 pcihp->flags = flags; 2067 2068 return 0; 2069 } 2070 2071 /* 2072 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2073 * struct pcmcia_io_handle *pcihp) 2074 * 2075 * This function only frees I/O region for pccard. 2076 * 2077 * XXX: The interface of this function is not very good, I believe. 2078 */ 2079 void 2080 pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2081 struct pcmcia_io_handle *pcihp) 2082 { 2083 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2084 #if !rbus 2085 bus_space_tag_t iot = pcihp->iot; 2086 #endif 2087 bus_space_handle_t ioh = pcihp->ioh; 2088 bus_size_t size = pcihp->size; 2089 2090 #if rbus 2091 rbus_tag_t rb = sc->sc_rbus_iot; 2092 2093 rbus_space_free(rb, ioh, size, NULL); 2094 #else 2095 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 2096 bus_space_free(iot, ioh, size); 2097 else 2098 bus_space_unmap(iot, ioh, size); 2099 #endif 2100 } 2101 2102 /* 2103 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 2104 * bus_addr_t offset, bus_size_t size, 2105 * struct pcmcia_io_handle *pcihp, 2106 * int *windowp) 2107 * 2108 * This function maps the allocated I/O region to pccard. This function 2109 * never allocates any I/O region for pccard I/O area. I don't 2110 * understand why the original authors of pcmciabus separated alloc and 2111 * map. I believe the two must be unite. 2112 * 2113 * XXX: no wait timing control? 2114 */ 2115 int 2116 pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, bus_addr_t offset, 2117 bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp) 2118 { 2119 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2120 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2121 bus_addr_t ioaddr = pcihp->addr + offset; 2122 int i, win; 2123 #if defined CBB_DEBUG 2124 static const char *width_names[] = { "dynamic", "io8", "io16" }; 2125 #endif 2126 2127 /* Sanity check I/O handle. */ 2128 2129 if (sc->sc_iot != pcihp->iot) { 2130 panic("pccbb_pcmcia_io_map iot is bogus"); 2131 } 2132 2133 /* XXX Sanity check offset/size. */ 2134 2135 win = -1; 2136 for (i = 0; i < PCIC_IO_WINS; i++) { 2137 if ((ph->ioalloc & (1 << i)) == 0) { 2138 win = i; 2139 ph->ioalloc |= (1 << i); 2140 break; 2141 } 2142 } 2143 2144 if (win == -1) { 2145 return 1; 2146 } 2147 2148 *windowp = win; 2149 2150 /* XXX this is pretty gross */ 2151 2152 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2153 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2154 2155 /* XXX wtf is this doing here? */ 2156 2157 #if 0 2158 printf(" port 0x%lx", (u_long) ioaddr); 2159 if (size > 1) { 2160 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2161 } 2162 #endif 2163 2164 ph->io[win].addr = ioaddr; 2165 ph->io[win].size = size; 2166 ph->io[win].width = width; 2167 2168 /* actual dirty register-value changing in the function below. */ 2169 pccbb_pcmcia_do_io_map(sc, win); 2170 2171 return 0; 2172 } 2173 2174 /* 2175 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2176 * 2177 * This function changes register-value to map I/O region for pccard. 2178 */ 2179 static void 2180 pccbb_pcmcia_do_io_map(struct pccbb_softc *sc, int win) 2181 { 2182 static u_int8_t pcic_iowidth[3] = { 2183 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2184 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2185 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2186 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2187 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2188 }; 2189 2190 #define PCIC_SIA_START_LOW 0 2191 #define PCIC_SIA_START_HIGH 1 2192 #define PCIC_SIA_STOP_LOW 2 2193 #define PCIC_SIA_STOP_HIGH 3 2194 2195 int regbase_win = 0x8 + win * 0x04; 2196 u_int8_t ioctl, enable; 2197 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2198 2199 DPRINTF(("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx " 2200 "width %d\n", win, (unsigned long)ph->io[win].addr, 2201 (unsigned long)ph->io[win].size, ph->io[win].width * 8)); 2202 2203 Pcic_write(sc, regbase_win + PCIC_SIA_START_LOW, 2204 ph->io[win].addr & 0xff); 2205 Pcic_write(sc, regbase_win + PCIC_SIA_START_HIGH, 2206 (ph->io[win].addr >> 8) & 0xff); 2207 2208 Pcic_write(sc, regbase_win + PCIC_SIA_STOP_LOW, 2209 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2210 Pcic_write(sc, regbase_win + PCIC_SIA_STOP_HIGH, 2211 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2212 2213 ioctl = Pcic_read(sc, PCIC_IOCTL); 2214 enable = Pcic_read(sc, PCIC_ADDRWIN_ENABLE); 2215 switch (win) { 2216 case 0: 2217 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2218 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2219 PCIC_IOCTL_IO0_DATASIZE_MASK); 2220 ioctl |= pcic_iowidth[ph->io[win].width]; 2221 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2222 break; 2223 case 1: 2224 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2225 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2226 PCIC_IOCTL_IO1_DATASIZE_MASK); 2227 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2228 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2229 break; 2230 } 2231 Pcic_write(sc, PCIC_IOCTL, ioctl); 2232 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, enable); 2233 #if defined(CBB_DEBUG) 2234 { 2235 u_int8_t start_low = 2236 Pcic_read(sc, regbase_win + PCIC_SIA_START_LOW); 2237 u_int8_t start_high = 2238 Pcic_read(sc, regbase_win + PCIC_SIA_START_HIGH); 2239 u_int8_t stop_low = 2240 Pcic_read(sc, regbase_win + PCIC_SIA_STOP_LOW); 2241 u_int8_t stop_high = 2242 Pcic_read(sc, regbase_win + PCIC_SIA_STOP_HIGH); 2243 printf("pccbb_pcmcia_do_io_map start %02x %02x, " 2244 "stop %02x %02x, ioctl %02x enable %02x\n", 2245 start_low, start_high, stop_low, stop_high, ioctl, enable); 2246 } 2247 #endif 2248 } 2249 2250 /* 2251 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2252 * 2253 * This function unmaps I/O region. No return value. 2254 */ 2255 STATIC void 2256 pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t pch, int win) 2257 { 2258 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2259 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2260 int reg; 2261 2262 if (win >= PCIC_IO_WINS || win < 0) { 2263 panic("pccbb_pcmcia_io_unmap: window out of range"); 2264 } 2265 2266 reg = Pcic_read(sc, PCIC_ADDRWIN_ENABLE); 2267 switch (win) { 2268 case 0: 2269 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2270 break; 2271 case 1: 2272 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2273 break; 2274 } 2275 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, reg); 2276 2277 ph->ioalloc &= ~(1 << win); 2278 } 2279 2280 static int 2281 pccbb_pcmcia_wait_ready(struct pccbb_softc *sc) 2282 { 2283 u_int8_t stat; 2284 int i; 2285 2286 /* wait an initial 10ms for quick cards */ 2287 stat = Pcic_read(sc, PCIC_IF_STATUS); 2288 if (stat & PCIC_IF_STATUS_READY) 2289 return (0); 2290 pccbb_pcmcia_delay(sc, 10, "pccwr0"); 2291 for (i = 0; i < 50; i++) { 2292 stat = Pcic_read(sc, PCIC_IF_STATUS); 2293 if (stat & PCIC_IF_STATUS_READY) 2294 return (0); 2295 if ((stat & PCIC_IF_STATUS_CARDDETECT_MASK) != 2296 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2297 return (ENXIO); 2298 /* wait .1s (100ms) each iteration now */ 2299 pccbb_pcmcia_delay(sc, 100, "pccwr1"); 2300 } 2301 2302 printf("pccbb_pcmcia_wait_ready: ready never happened, status=%02x\n", stat); 2303 return (EWOULDBLOCK); 2304 } 2305 2306 /* 2307 * Perform long (msec order) delay. timo is in milliseconds. 2308 */ 2309 static void 2310 pccbb_pcmcia_delay(struct pccbb_softc *sc, int timo, const char *wmesg) 2311 { 2312 #ifdef DIAGNOSTIC 2313 if (timo <= 0) 2314 panic("pccbb_pcmcia_delay: called with timeout %d", timo); 2315 if (!curlwp) 2316 panic("pccbb_pcmcia_delay: called in interrupt context"); 2317 #endif 2318 DPRINTF(("pccbb_pcmcia_delay: \"%s\", sleep %d ms\n", wmesg, timo)); 2319 kpause(wmesg, false, max(mstohz(timo), 1), NULL); 2320 } 2321 2322 /* 2323 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2324 * 2325 * This function enables the card. All information is stored in 2326 * the first argument, pcmcia_chipset_handle_t. 2327 */ 2328 STATIC void 2329 pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2330 { 2331 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2332 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2333 pcireg_t spsr; 2334 int voltage; 2335 int win; 2336 u_int8_t power, intr; 2337 #ifdef DIAGNOSTIC 2338 int reg; 2339 #endif 2340 2341 /* this bit is mostly stolen from pcic_attach_card */ 2342 2343 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2344 2345 /* get card Vcc info */ 2346 spsr = 2347 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2348 CB_SOCKET_STAT); 2349 if (spsr & CB_SOCKET_STAT_5VCARD) { 2350 DPRINTF(("5V card\n")); 2351 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2352 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2353 DPRINTF(("3V card\n")); 2354 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2355 } else { 2356 DPRINTF(("?V card, 0x%x\n", spsr)); /* XXX */ 2357 return; 2358 } 2359 2360 /* disable interrupts; assert RESET */ 2361 intr = Pcic_read(sc, PCIC_INTR); 2362 intr &= PCIC_INTR_ENABLE; 2363 Pcic_write(sc, PCIC_INTR, intr); 2364 2365 /* zero out the address windows */ 2366 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, 0); 2367 2368 /* power down the socket to reset it, clear the card reset pin */ 2369 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2370 2371 /* power off; assert output enable bit */ 2372 power = PCIC_PWRCTL_OE; 2373 Pcic_write(sc, PCIC_PWRCTL, power); 2374 2375 /* power up the socket */ 2376 if (pccbb_power(sc, voltage) == 0) 2377 return; 2378 2379 /* 2380 * Table 4-18 and figure 4-6 of the PC Card specifiction say: 2381 * Vcc Rising Time (Tpr) = 100ms (handled in pccbb_power() above) 2382 * RESET Width (Th (Hi-z RESET)) = 1ms 2383 * RESET Width (Tw (RESET)) = 10us 2384 * 2385 * some machines require some more time to be settled 2386 * for example old toshiba topic bridges! 2387 * (100ms is added here). 2388 */ 2389 pccbb_pcmcia_delay(sc, 200 + 1, "pccen1"); 2390 2391 /* negate RESET */ 2392 intr |= PCIC_INTR_RESET; 2393 Pcic_write(sc, PCIC_INTR, intr); 2394 2395 /* 2396 * RESET Setup Time (Tsu (RESET)) = 20ms 2397 */ 2398 pccbb_pcmcia_delay(sc, 20, "pccen2"); 2399 2400 #ifdef DIAGNOSTIC 2401 reg = Pcic_read(sc, PCIC_IF_STATUS); 2402 if ((reg & PCIC_IF_STATUS_POWERACTIVE) == 0) 2403 printf("pccbb_pcmcia_socket_enable: no power, status=%x\n", reg); 2404 #endif 2405 2406 /* wait for the chip to finish initializing */ 2407 if (pccbb_pcmcia_wait_ready(sc)) { 2408 #ifdef DIAGNOSTIC 2409 printf("pccbb_pcmcia_socket_enable: never became ready\n"); 2410 #endif 2411 /* XXX return a failure status?? */ 2412 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2413 Pcic_write(sc, PCIC_PWRCTL, 0); 2414 return; 2415 } 2416 2417 /* reinstall all the memory and io mappings */ 2418 for (win = 0; win < PCIC_MEM_WINS; ++win) 2419 if (ph->memalloc & (1 << win)) 2420 pccbb_pcmcia_do_mem_map(sc, win); 2421 for (win = 0; win < PCIC_IO_WINS; ++win) 2422 if (ph->ioalloc & (1 << win)) 2423 pccbb_pcmcia_do_io_map(sc, win); 2424 } 2425 2426 /* 2427 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2428 * 2429 * This function disables the card. All information is stored in 2430 * the first argument, pcmcia_chipset_handle_t. 2431 */ 2432 STATIC void 2433 pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t pch) 2434 { 2435 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2436 u_int8_t intr; 2437 2438 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2439 2440 /* disable interrupts; assert RESET */ 2441 intr = Pcic_read(sc, PCIC_INTR); 2442 intr &= PCIC_INTR_ENABLE; 2443 Pcic_write(sc, PCIC_INTR, intr); 2444 2445 /* zero out the address windows */ 2446 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, 0); 2447 2448 /* power down the socket to reset it, clear the card reset pin */ 2449 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2450 2451 /* disable socket: negate output enable bit and power off */ 2452 Pcic_write(sc, PCIC_PWRCTL, 0); 2453 2454 /* 2455 * Vcc Falling Time (Tpf) = 300ms 2456 */ 2457 pccbb_pcmcia_delay(sc, 300, "pccwr1"); 2458 } 2459 2460 STATIC void 2461 pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t pch, int type) 2462 { 2463 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2464 u_int8_t intr; 2465 2466 /* set the card type */ 2467 2468 intr = Pcic_read(sc, PCIC_INTR); 2469 intr &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_CARDTYPE_MASK); 2470 if (type == PCMCIA_IFTYPE_IO) 2471 intr |= PCIC_INTR_CARDTYPE_IO; 2472 else 2473 intr |= PCIC_INTR_CARDTYPE_MEM; 2474 Pcic_write(sc, PCIC_INTR, intr); 2475 2476 DPRINTF(("%s: pccbb_pcmcia_socket_settype type %s %02x\n", 2477 device_xname(sc->sc_dev), 2478 ((type == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2479 } 2480 2481 /* 2482 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2483 * 2484 * This function detects whether a card is in the slot or not. 2485 * If a card is inserted, return 1. Otherwise, return 0. 2486 */ 2487 STATIC int 2488 pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch) 2489 { 2490 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2491 2492 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2493 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2494 } 2495 2496 #if 0 2497 STATIC int 2498 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2499 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2500 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2501 #endif 2502 /* 2503 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2504 * bus_size_t size, 2505 * struct pcmcia_mem_handle *pcmhp) 2506 * 2507 * This function only allocates memory region for pccard. This 2508 * function never maps the allocated region to pccard memory area. 2509 * 2510 * XXX: Why the argument of start address is not in? 2511 */ 2512 STATIC int 2513 pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 2514 struct pcmcia_mem_handle *pcmhp) 2515 { 2516 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2517 bus_space_handle_t memh; 2518 bus_addr_t addr; 2519 bus_size_t sizepg; 2520 #if rbus 2521 rbus_tag_t rb; 2522 #endif 2523 2524 /* Check that the card is still there. */ 2525 if ((Pcic_read(sc, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2526 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2527 return 1; 2528 2529 /* out of sc->memh, allocate as many pages as necessary */ 2530 2531 /* convert size to PCIC pages */ 2532 /* 2533 * This is not enough; when the requested region is on the page 2534 * boundaries, this may calculate wrong result. 2535 */ 2536 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2537 #if 0 2538 if (sizepg > PCIC_MAX_MEM_PAGES) { 2539 return 1; 2540 } 2541 #endif 2542 2543 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2544 return 1; 2545 } 2546 2547 addr = 0; /* XXX gcc -Wuninitialized */ 2548 2549 #if rbus 2550 rb = sc->sc_rbus_memt; 2551 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2552 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2553 &addr, &memh)) { 2554 return 1; 2555 } 2556 #else 2557 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2558 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2559 0, /* boundary */ 2560 0, /* flags */ 2561 &addr, &memh)) { 2562 return 1; 2563 } 2564 #endif 2565 2566 DPRINTF(("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, " 2567 "realsize 0x%lx\n", (unsigned long)addr, (unsigned long)size, 2568 (unsigned long)sizepg * PCIC_MEM_PAGESIZE)); 2569 2570 pcmhp->memt = sc->sc_memt; 2571 pcmhp->memh = memh; 2572 pcmhp->addr = addr; 2573 pcmhp->size = size; 2574 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2575 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2576 pcmhp->mhandle = 0; 2577 /* No offset??? Funny. */ 2578 2579 return 0; 2580 } 2581 2582 /* 2583 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2584 * struct pcmcia_mem_handle *pcmhp) 2585 * 2586 * This function release the memory space allocated by the function 2587 * pccbb_pcmcia_mem_alloc(). 2588 */ 2589 STATIC void 2590 pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2591 struct pcmcia_mem_handle *pcmhp) 2592 { 2593 #if rbus 2594 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2595 2596 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2597 #else 2598 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2599 #endif 2600 } 2601 2602 /* 2603 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2604 * 2605 * This function release the memory space allocated by the function 2606 * pccbb_pcmcia_mem_alloc(). 2607 */ 2608 STATIC void 2609 pccbb_pcmcia_do_mem_map(struct pccbb_softc *sc, int win) 2610 { 2611 int regbase_win; 2612 bus_addr_t phys_addr; 2613 bus_addr_t phys_end; 2614 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2615 2616 #define PCIC_SMM_START_LOW 0 2617 #define PCIC_SMM_START_HIGH 1 2618 #define PCIC_SMM_STOP_LOW 2 2619 #define PCIC_SMM_STOP_HIGH 3 2620 #define PCIC_CMA_LOW 4 2621 #define PCIC_CMA_HIGH 5 2622 2623 u_int8_t start_low, start_high = 0; 2624 u_int8_t stop_low, stop_high; 2625 u_int8_t off_low, off_high; 2626 u_int8_t mem_window; 2627 int reg; 2628 2629 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2630 int mem8 = 2631 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2632 || (kind == PCMCIA_MEM_ATTR); 2633 2634 regbase_win = 0x10 + win * 0x08; 2635 2636 phys_addr = ph->mem[win].addr; 2637 phys_end = phys_addr + ph->mem[win].size; 2638 2639 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2640 (unsigned long)phys_addr, (unsigned long)phys_end, 2641 (unsigned long)ph->mem[win].offset)); 2642 2643 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2644 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2645 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2646 2647 /* bit 19:12 */ 2648 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2649 /* bit 23:20 and bit 7 on */ 2650 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2651 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2652 /* bit 31:24, for 32-bit address */ 2653 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2654 2655 Pcic_write(sc, regbase_win + PCIC_SMM_START_LOW, start_low); 2656 Pcic_write(sc, regbase_win + PCIC_SMM_START_HIGH, start_high); 2657 2658 if (sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2659 Pcic_write(sc, 0x40 + win, mem_window); 2660 } 2661 2662 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2663 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2664 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2665 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2666 2667 Pcic_write(sc, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2668 Pcic_write(sc, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2669 2670 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2671 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2672 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2673 | ((kind == PCMCIA_MEM_ATTR) ? 2674 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2675 2676 Pcic_write(sc, regbase_win + PCIC_CMA_LOW, off_low); 2677 Pcic_write(sc, regbase_win + PCIC_CMA_HIGH, off_high); 2678 2679 reg = Pcic_read(sc, PCIC_ADDRWIN_ENABLE); 2680 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2681 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, reg); 2682 2683 #if defined(CBB_DEBUG) 2684 { 2685 int r1, r2, r3, r4, r5, r6, r7 = 0; 2686 2687 r1 = Pcic_read(sc, regbase_win + PCIC_SMM_START_LOW); 2688 r2 = Pcic_read(sc, regbase_win + PCIC_SMM_START_HIGH); 2689 r3 = Pcic_read(sc, regbase_win + PCIC_SMM_STOP_LOW); 2690 r4 = Pcic_read(sc, regbase_win + PCIC_SMM_STOP_HIGH); 2691 r5 = Pcic_read(sc, regbase_win + PCIC_CMA_LOW); 2692 r6 = Pcic_read(sc, regbase_win + PCIC_CMA_HIGH); 2693 if (sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2694 r7 = Pcic_read(sc, 0x40 + win); 2695 } 2696 2697 printf("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2698 "%02x%02x", win, r1, r2, r3, r4, r5, r6); 2699 if (sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2700 printf(" %02x", r7); 2701 } 2702 printf("\n"); 2703 } 2704 #endif 2705 } 2706 2707 /* 2708 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2709 * bus_addr_t card_addr, bus_size_t size, 2710 * struct pcmcia_mem_handle *pcmhp, 2711 * bus_addr_t *offsetp, int *windowp) 2712 * 2713 * This function maps memory space allocated by the function 2714 * pccbb_pcmcia_mem_alloc(). 2715 */ 2716 STATIC int 2717 pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2718 bus_addr_t card_addr, bus_size_t size, struct pcmcia_mem_handle *pcmhp, 2719 bus_size_t *offsetp, int *windowp) 2720 { 2721 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2722 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2723 bus_addr_t busaddr; 2724 long card_offset; 2725 int win; 2726 2727 /* Check that the card is still there. */ 2728 if ((Pcic_read(sc, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2729 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2730 return 1; 2731 2732 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2733 if ((ph->memalloc & (1 << win)) == 0) { 2734 ph->memalloc |= (1 << win); 2735 break; 2736 } 2737 } 2738 2739 if (win == PCIC_MEM_WINS) { 2740 return 1; 2741 } 2742 2743 *windowp = win; 2744 2745 /* XXX this is pretty gross */ 2746 2747 if (sc->sc_memt != pcmhp->memt) { 2748 panic("pccbb_pcmcia_mem_map memt is bogus"); 2749 } 2750 2751 busaddr = pcmhp->addr; 2752 2753 /* 2754 * compute the address offset to the pcmcia address space for the 2755 * pcic. this is intentionally signed. The masks and shifts below 2756 * will cause TRT to happen in the pcic registers. Deal with making 2757 * sure the address is aligned, and return the alignment offset. 2758 */ 2759 2760 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2761 card_addr -= *offsetp; 2762 2763 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2764 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2765 (u_long) card_addr)); 2766 2767 /* 2768 * include the offset in the size, and decrement size by one, since 2769 * the hw wants start/stop 2770 */ 2771 size += *offsetp - 1; 2772 2773 card_offset = (((long)card_addr) - ((long)busaddr)); 2774 2775 ph->mem[win].addr = busaddr; 2776 ph->mem[win].size = size; 2777 ph->mem[win].offset = card_offset; 2778 ph->mem[win].kind = kind; 2779 2780 pccbb_pcmcia_do_mem_map(sc, win); 2781 2782 return 0; 2783 } 2784 2785 /* 2786 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2787 * int window) 2788 * 2789 * This function unmaps memory space which mapped by the function 2790 * pccbb_pcmcia_mem_map(). 2791 */ 2792 STATIC void 2793 pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, int window) 2794 { 2795 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2796 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2797 int reg; 2798 2799 if (window >= PCIC_MEM_WINS) { 2800 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2801 } 2802 2803 reg = Pcic_read(sc, PCIC_ADDRWIN_ENABLE); 2804 reg &= ~(1 << window); 2805 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, reg); 2806 2807 ph->memalloc &= ~(1 << window); 2808 } 2809 2810 /* 2811 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2812 * struct pcmcia_function *pf, 2813 * int ipl, 2814 * int (*func)(void *), 2815 * void *arg); 2816 * 2817 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2818 */ 2819 STATIC void * 2820 pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2821 struct pcmcia_function *pf, int ipl, int (*func)(void *), void *arg) 2822 { 2823 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2824 2825 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2826 /* what should I do? */ 2827 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2828 DPRINTF(("%s does not provide edge nor pulse " 2829 "interrupt\n", device_xname(sc->sc_dev))); 2830 return NULL; 2831 } 2832 /* 2833 * XXX Noooooo! The interrupt flag must set properly!! 2834 * dumb pcmcia driver!! 2835 */ 2836 } 2837 2838 return pccbb_intr_establish(sc, 0, ipl, func, arg); 2839 } 2840 2841 /* 2842 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2843 * void *ih) 2844 * 2845 * This function disables PC-Card interrupt. 2846 */ 2847 STATIC void 2848 pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 2849 { 2850 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2851 2852 pccbb_intr_disestablish(sc, ih); 2853 } 2854 2855 #if rbus 2856 /* 2857 * static int 2858 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2859 * bus_addr_t addr, bus_size_t size, 2860 * bus_addr_t mask, bus_size_t align, 2861 * int flags, bus_addr_t *addrp; 2862 * bus_space_handle_t *bshp) 2863 * 2864 * This function allocates a portion of memory or io space for 2865 * clients. This function is called from CardBus card drivers. 2866 */ 2867 static int 2868 pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2869 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 2870 int flags, bus_addr_t *addrp, bus_space_handle_t *bshp) 2871 { 2872 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2873 2874 DPRINTF(("pccbb_rbus_cb_space_alloc: addr 0x%lx, size 0x%lx, " 2875 "mask 0x%lx, align 0x%lx\n", (unsigned long)addr, 2876 (unsigned long)size, (unsigned long)mask, (unsigned long)align)); 2877 2878 if (align == 0) { 2879 align = size; 2880 } 2881 2882 if (rb->rb_bt == sc->sc_memt) { 2883 if (align < 16) { 2884 return 1; 2885 } 2886 /* 2887 * XXX: align more than 0x1000 to avoid overwrapping 2888 * memory windows for two or more devices. 0x1000 2889 * means memory window's granularity. 2890 * 2891 * Two or more devices should be able to share same 2892 * memory window region. However, overrapping memory 2893 * window is not good because some devices, such as 2894 * 3Com 3C575[BC], have a broken address decoder and 2895 * intrude other's memory region. 2896 */ 2897 if (align < 0x1000) { 2898 align = 0x1000; 2899 } 2900 } else if (rb->rb_bt == sc->sc_iot) { 2901 if (align < 4) { 2902 return 1; 2903 } 2904 /* XXX: hack for avoiding ISA image */ 2905 if (mask < 0x0100) { 2906 mask = 0x3ff; 2907 addr = 0x300; 2908 } 2909 2910 } else { 2911 DPRINTF(("pccbb_rbus_cb_space_alloc: Bus space tag 0x%lx is " 2912 "NOT used. io: 0x%lx, mem: 0x%lx\n", 2913 (unsigned long)rb->rb_bt, (unsigned long)sc->sc_iot, 2914 (unsigned long)sc->sc_memt)); 2915 return 1; 2916 /* XXX: panic here? */ 2917 } 2918 2919 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 2920 aprint_normal_dev(sc->sc_dev, "<rbus> no bus space\n"); 2921 return 1; 2922 } 2923 2924 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 2925 2926 return 0; 2927 } 2928 2929 /* 2930 * static int 2931 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 2932 * bus_space_handle_t *bshp, bus_size_t size); 2933 * 2934 * This function is called from CardBus card drivers. 2935 */ 2936 static int 2937 pccbb_rbus_cb_space_free(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2938 bus_space_handle_t bsh, bus_size_t size) 2939 { 2940 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2941 bus_space_tag_t bt = rb->rb_bt; 2942 2943 pccbb_close_win(sc, bt, bsh, size); 2944 2945 if (bt == sc->sc_memt) { 2946 } else if (bt == sc->sc_iot) { 2947 } else { 2948 return 1; 2949 /* XXX: panic here? */ 2950 } 2951 2952 return rbus_space_free(rb, bsh, size, NULL); 2953 } 2954 #endif /* rbus */ 2955 2956 #if rbus 2957 2958 static int 2959 pccbb_open_win(struct pccbb_softc *sc, bus_space_tag_t bst, bus_addr_t addr, 2960 bus_size_t size, bus_space_handle_t bsh, int flags) 2961 { 2962 struct pccbb_win_chain_head *head; 2963 bus_addr_t align; 2964 2965 head = &sc->sc_iowindow; 2966 align = 0x04; 2967 if (sc->sc_memt == bst) { 2968 head = &sc->sc_memwindow; 2969 align = 0x1000; 2970 DPRINTF(("using memory window, 0x%lx 0x%lx 0x%lx\n\n", 2971 (unsigned long)sc->sc_iot, (unsigned long)sc->sc_memt, 2972 (unsigned long)bst)); 2973 } 2974 2975 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 2976 aprint_error_dev(sc->sc_dev, 2977 "pccbb_open_win: %s winlist insert failed\n", 2978 (head == &sc->sc_memwindow) ? "mem" : "io"); 2979 } 2980 pccbb_winset(align, sc, bst); 2981 2982 return 0; 2983 } 2984 2985 static int 2986 pccbb_close_win(struct pccbb_softc *sc, bus_space_tag_t bst, 2987 bus_space_handle_t bsh, bus_size_t size) 2988 { 2989 struct pccbb_win_chain_head *head; 2990 bus_addr_t align; 2991 2992 head = &sc->sc_iowindow; 2993 align = 0x04; 2994 if (sc->sc_memt == bst) { 2995 head = &sc->sc_memwindow; 2996 align = 0x1000; 2997 } 2998 2999 if (pccbb_winlist_delete(head, bsh, size)) { 3000 aprint_error_dev(sc->sc_dev, 3001 "pccbb_close_win: %s winlist delete failed\n", 3002 (head == &sc->sc_memwindow) ? "mem" : "io"); 3003 } 3004 pccbb_winset(align, sc, bst); 3005 3006 return 0; 3007 } 3008 3009 static int 3010 pccbb_winlist_insert(struct pccbb_win_chain_head *head, bus_addr_t start, 3011 bus_size_t size, bus_space_handle_t bsh, int flags) 3012 { 3013 struct pccbb_win_chain *chainp, *elem; 3014 3015 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 3016 M_NOWAIT)) == NULL) 3017 return (1); /* fail */ 3018 3019 elem->wc_start = start; 3020 elem->wc_end = start + (size - 1); 3021 elem->wc_handle = bsh; 3022 elem->wc_flags = flags; 3023 3024 TAILQ_FOREACH(chainp, head, wc_list) { 3025 if (chainp->wc_end >= start) 3026 break; 3027 } 3028 if (chainp != NULL) 3029 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 3030 else 3031 TAILQ_INSERT_TAIL(head, elem, wc_list); 3032 return (0); 3033 } 3034 3035 static int 3036 pccbb_winlist_delete(struct pccbb_win_chain_head *head, bus_space_handle_t bsh, 3037 bus_size_t size) 3038 { 3039 struct pccbb_win_chain *chainp; 3040 3041 TAILQ_FOREACH(chainp, head, wc_list) { 3042 if (memcmp(&chainp->wc_handle, &bsh, sizeof(bsh)) == 0) 3043 break; 3044 } 3045 if (chainp == NULL) 3046 return 1; /* fail: no candidate to remove */ 3047 3048 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 3049 printf("pccbb_winlist_delete: window 0x%lx size " 3050 "inconsistent: 0x%lx, 0x%lx\n", 3051 (unsigned long)chainp->wc_start, 3052 (unsigned long)(chainp->wc_end - chainp->wc_start), 3053 (unsigned long)(size - 1)); 3054 return 1; 3055 } 3056 3057 TAILQ_REMOVE(head, chainp, wc_list); 3058 free(chainp, M_DEVBUF); 3059 3060 return 0; 3061 } 3062 3063 static void 3064 pccbb_winset(bus_addr_t align, struct pccbb_softc *sc, bus_space_tag_t bst) 3065 { 3066 pci_chipset_tag_t pc; 3067 pcitag_t tag; 3068 bus_addr_t mask = ~(align - 1); 3069 struct { 3070 cardbusreg_t win_start; 3071 cardbusreg_t win_limit; 3072 int win_flags; 3073 } win[2]; 3074 struct pccbb_win_chain *chainp; 3075 int offs; 3076 3077 win[0].win_start = win[1].win_start = 0xffffffff; 3078 win[0].win_limit = win[1].win_limit = 0; 3079 win[0].win_flags = win[1].win_flags = 0; 3080 3081 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3082 offs = PCI_CB_IOBASE0; 3083 if (sc->sc_memt == bst) { 3084 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3085 offs = PCI_CB_MEMBASE0; 3086 } 3087 3088 if (chainp != NULL) { 3089 win[0].win_start = chainp->wc_start & mask; 3090 win[0].win_limit = chainp->wc_end & mask; 3091 win[0].win_flags = chainp->wc_flags; 3092 chainp = TAILQ_NEXT(chainp, wc_list); 3093 } 3094 3095 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3096 if (win[1].win_start == 0xffffffff) { 3097 /* window 1 is not used */ 3098 if ((win[0].win_flags == chainp->wc_flags) && 3099 (win[0].win_limit + align >= 3100 (chainp->wc_start & mask))) { 3101 /* concatenate */ 3102 win[0].win_limit = chainp->wc_end & mask; 3103 } else { 3104 /* make new window */ 3105 win[1].win_start = chainp->wc_start & mask; 3106 win[1].win_limit = chainp->wc_end & mask; 3107 win[1].win_flags = chainp->wc_flags; 3108 } 3109 continue; 3110 } 3111 3112 /* Both windows are engaged. */ 3113 if (win[0].win_flags == win[1].win_flags) { 3114 /* same flags */ 3115 if (win[0].win_flags == chainp->wc_flags) { 3116 if (win[1].win_start - (win[0].win_limit + 3117 align) < 3118 (chainp->wc_start & mask) - 3119 ((chainp->wc_end & mask) + align)) { 3120 /* 3121 * merge window 0 and 1, and set win1 3122 * to chainp 3123 */ 3124 win[0].win_limit = win[1].win_limit; 3125 win[1].win_start = 3126 chainp->wc_start & mask; 3127 win[1].win_limit = 3128 chainp->wc_end & mask; 3129 } else { 3130 win[1].win_limit = 3131 chainp->wc_end & mask; 3132 } 3133 } else { 3134 /* different flags */ 3135 3136 /* concatenate win0 and win1 */ 3137 win[0].win_limit = win[1].win_limit; 3138 /* allocate win[1] to new space */ 3139 win[1].win_start = chainp->wc_start & mask; 3140 win[1].win_limit = chainp->wc_end & mask; 3141 win[1].win_flags = chainp->wc_flags; 3142 } 3143 } else { 3144 /* the flags of win[0] and win[1] is different */ 3145 if (win[0].win_flags == chainp->wc_flags) { 3146 win[0].win_limit = chainp->wc_end & mask; 3147 /* 3148 * XXX this creates overlapping windows, so 3149 * what should the poor bridge do if one is 3150 * cachable, and the other is not? 3151 */ 3152 aprint_error_dev(sc->sc_dev, 3153 "overlapping windows\n"); 3154 } else { 3155 win[1].win_limit = chainp->wc_end & mask; 3156 } 3157 } 3158 } 3159 3160 pc = sc->sc_pc; 3161 tag = sc->sc_tag; 3162 pci_conf_write(pc, tag, offs, win[0].win_start); 3163 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3164 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3165 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3166 DPRINTF(("--pccbb_winset: win0 [0x%lx, 0x%lx), win1 [0x%lx, 0x%lx)\n", 3167 (unsigned long)pci_conf_read(pc, tag, offs), 3168 (unsigned long)pci_conf_read(pc, tag, offs + 4) + align, 3169 (unsigned long)pci_conf_read(pc, tag, offs + 8), 3170 (unsigned long)pci_conf_read(pc, tag, offs + 12) + align)); 3171 3172 if (bst == sc->sc_memt) { 3173 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BRIDGE_CONTROL_REG); 3174 3175 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 3176 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 3177 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3178 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 3179 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3180 pci_conf_write(pc, tag, PCI_BRIDGE_CONTROL_REG, bcr); 3181 } 3182 } 3183 3184 #endif /* rbus */ 3185 3186 static bool 3187 pccbb_suspend(device_t dv PMF_FN_ARGS) 3188 { 3189 struct pccbb_softc *sc = device_private(dv); 3190 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3191 bus_space_handle_t base_memh = sc->sc_base_memh; 3192 pcireg_t reg; 3193 3194 if (sc->sc_pil_intr_enable) 3195 (void)pccbbintr_function(sc); 3196 sc->sc_pil_intr_enable = 0; 3197 3198 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3199 /* Disable interrupts. */ 3200 reg &= ~(CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER); 3201 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3202 /* XXX joerg Disable power to the socket? */ 3203 3204 /* XXX flush PCI write */ 3205 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3206 3207 /* reset interrupt */ 3208 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, 3209 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT)); 3210 /* XXX flush PCI write */ 3211 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3212 3213 if (sc->sc_ih != NULL) { 3214 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 3215 sc->sc_ih = NULL; 3216 } 3217 3218 return true; 3219 } 3220 3221 static bool 3222 pccbb_resume(device_t dv PMF_FN_ARGS) 3223 { 3224 struct pccbb_softc *sc = device_private(dv); 3225 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3226 bus_space_handle_t base_memh = sc->sc_base_memh; 3227 pcireg_t reg; 3228 3229 pccbb_chipinit(sc); 3230 pccbb_intrinit(sc); 3231 /* setup memory and io space window for CB */ 3232 pccbb_winset(0x1000, sc, sc->sc_memt); 3233 pccbb_winset(0x04, sc, sc->sc_iot); 3234 3235 /* CSC Interrupt: Card detect interrupt on */ 3236 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3237 /* Card detect intr is turned on. */ 3238 reg |= CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; 3239 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3240 /* reset interrupt */ 3241 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3242 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3243 3244 /* 3245 * check for card insertion or removal during suspend period. 3246 * XXX: the code can't cope with card swap (remove then 3247 * insert). how can we detect such situation? 3248 */ 3249 (void)pccbbintr(sc); 3250 3251 sc->sc_pil_intr_enable = 1; 3252 3253 return true; 3254 } 3255
Indexes created Tue Oct 14 06:10:07 GMT 2025