pccbb.c revision 1.167.4.5
1 /* $NetBSD: pccbb.c,v 1.167.4.5 2010/03/11 15:03:49 yamt Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: pccbb.c,v 1.167.4.5 2010/03/11 15:03:49 yamt Exp $"); 30 31 /* 32 #define CBB_DEBUG 33 #define SHOW_REGS 34 */ 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/kernel.h> 39 #include <sys/errno.h> 40 #include <sys/ioctl.h> 41 #include <sys/reboot.h> /* for bootverbose */ 42 #include <sys/syslog.h> 43 #include <sys/device.h> 44 #include <sys/malloc.h> 45 #include <sys/proc.h> 46 47 #include <sys/intr.h> 48 #include <sys/bus.h> 49 50 #include <dev/pci/pcivar.h> 51 #include <dev/pci/pcireg.h> 52 #include <dev/pci/pcidevs.h> 53 54 #include <dev/pci/pccbbreg.h> 55 56 #include <dev/cardbus/cardslotvar.h> 57 58 #include <dev/cardbus/cardbusvar.h> 59 60 #include <dev/pcmcia/pcmciareg.h> 61 #include <dev/pcmcia/pcmciavar.h> 62 63 #include <dev/ic/i82365reg.h> 64 #include <dev/pci/pccbbvar.h> 65 66 #ifndef __NetBSD_Version__ 67 struct cfdriver cbb_cd = { 68 NULL, "cbb", DV_DULL 69 }; 70 #endif 71 72 #ifdef CBB_DEBUG 73 #define DPRINTF(x) printf x 74 #define STATIC 75 #else 76 #define DPRINTF(x) 77 #define STATIC static 78 #endif 79 80 int pccbb_burstup = 1; 81 82 /* 83 * delay_ms() is wait in milliseconds. It should be used instead 84 * of delay() if you want to wait more than 1 ms. 85 */ 86 static inline void 87 delay_ms(int millis, struct pccbb_softc *sc) 88 { 89 if (cold) 90 delay(millis * 1000); 91 else 92 kpause("pccbb", false, mstohz(millis), NULL); 93 } 94 95 int pcicbbmatch(device_t, cfdata_t, void *); 96 void pccbbattach(device_t, device_t, void *); 97 void pccbbchilddet(device_t, device_t); 98 int pccbbdetach(device_t, int); 99 int pccbbintr(void *); 100 static void pci113x_insert(void *); 101 static int pccbbintr_function(struct pccbb_softc *); 102 103 static int pccbb_detect_card(struct pccbb_softc *); 104 105 static void pccbb_pcmcia_write(struct pccbb_softc *, int, u_int8_t); 106 static u_int8_t pccbb_pcmcia_read(struct pccbb_softc *, int); 107 #define Pcic_read(sc, reg) pccbb_pcmcia_read((sc), (reg)) 108 #define Pcic_write(sc, reg, val) pccbb_pcmcia_write((sc), (reg), (val)) 109 110 STATIC int cb_reset(struct pccbb_softc *); 111 STATIC int cb_detect_voltage(struct pccbb_softc *); 112 STATIC int cbbprint(void *, const char *); 113 114 static int cb_chipset(u_int32_t, int *); 115 STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *, 116 struct pcmciabus_attach_args *); 117 118 STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int); 119 STATIC int pccbb_power(struct pccbb_softc *sc, int); 120 STATIC int pccbb_power_ct(cardbus_chipset_tag_t, int); 121 STATIC int pccbb_cardenable(struct pccbb_softc * sc, int function); 122 #if !rbus 123 static int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 124 static int pccbb_io_close(cardbus_chipset_tag_t, int); 125 static int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 126 static int pccbb_mem_close(cardbus_chipset_tag_t, int); 127 #endif /* !rbus */ 128 static void *pccbb_intr_establish(struct pccbb_softc *, 129 cardbus_intr_line_t irq, int level, int (*ih) (void *), void *sc); 130 static void pccbb_intr_disestablish(struct pccbb_softc *, void *ih); 131 132 static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t, 133 cardbus_intr_line_t irq, int level, int (*ih) (void *), void *sc); 134 static void pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih); 135 136 static pcitag_t pccbb_make_tag(cardbus_chipset_tag_t, int, int); 137 static pcireg_t pccbb_conf_read(cardbus_chipset_tag_t, pcitag_t, int); 138 static void pccbb_conf_write(cardbus_chipset_tag_t, pcitag_t, int, 139 pcireg_t); 140 static void pccbb_chipinit(struct pccbb_softc *); 141 static void pccbb_intrinit(struct pccbb_softc *); 142 143 STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 144 struct pcmcia_mem_handle *); 145 STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t, 146 struct pcmcia_mem_handle *); 147 STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 148 bus_size_t, struct pcmcia_mem_handle *, bus_size_t *, int *); 149 STATIC void pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t, int); 150 STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 151 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 152 STATIC void pccbb_pcmcia_io_free(pcmcia_chipset_handle_t, 153 struct pcmcia_io_handle *); 154 STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 155 bus_size_t, struct pcmcia_io_handle *, int *); 156 STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t, int); 157 STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t, 158 struct pcmcia_function *, int, int (*)(void *), void *); 159 STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t, void *); 160 STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t); 161 STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t); 162 STATIC void pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t, int); 163 STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch); 164 165 static int pccbb_pcmcia_wait_ready(struct pccbb_softc *); 166 static void pccbb_pcmcia_delay(struct pccbb_softc *, int, const char *); 167 168 static void pccbb_pcmcia_do_io_map(struct pccbb_softc *, int); 169 static void pccbb_pcmcia_do_mem_map(struct pccbb_softc *, int); 170 171 /* bus-space allocation and deallocation functions */ 172 #if rbus 173 174 static int pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t, rbus_tag_t, 175 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 176 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp); 177 static int pccbb_rbus_cb_space_free(cardbus_chipset_tag_t, rbus_tag_t, 178 bus_space_handle_t, bus_size_t); 179 180 #endif /* rbus */ 181 182 #if rbus 183 184 static int pccbb_open_win(struct pccbb_softc *, bus_space_tag_t, 185 bus_addr_t, bus_size_t, bus_space_handle_t, int flags); 186 static int pccbb_close_win(struct pccbb_softc *, bus_space_tag_t, 187 bus_space_handle_t, bus_size_t); 188 static int pccbb_winlist_insert(struct pccbb_win_chain_head *, bus_addr_t, 189 bus_size_t, bus_space_handle_t, int); 190 static int pccbb_winlist_delete(struct pccbb_win_chain_head *, 191 bus_space_handle_t, bus_size_t); 192 static void pccbb_winset(bus_addr_t align, struct pccbb_softc *, 193 bus_space_tag_t); 194 void pccbb_winlist_show(struct pccbb_win_chain *); 195 196 #endif /* rbus */ 197 198 /* for config_defer */ 199 static void pccbb_pci_callback(device_t); 200 201 static bool pccbb_suspend(device_t, const pmf_qual_t *); 202 static bool pccbb_resume(device_t, const pmf_qual_t *); 203 204 #if defined SHOW_REGS 205 static void cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, 206 bus_space_tag_t memt, bus_space_handle_t memh); 207 #endif 208 209 CFATTACH_DECL3_NEW(cbb_pci, sizeof(struct pccbb_softc), 210 pcicbbmatch, pccbbattach, pccbbdetach, NULL, NULL, pccbbchilddet, 211 DVF_DETACH_SHUTDOWN); 212 213 static const struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 214 pccbb_pcmcia_mem_alloc, 215 pccbb_pcmcia_mem_free, 216 pccbb_pcmcia_mem_map, 217 pccbb_pcmcia_mem_unmap, 218 pccbb_pcmcia_io_alloc, 219 pccbb_pcmcia_io_free, 220 pccbb_pcmcia_io_map, 221 pccbb_pcmcia_io_unmap, 222 pccbb_pcmcia_intr_establish, 223 pccbb_pcmcia_intr_disestablish, 224 pccbb_pcmcia_socket_enable, 225 pccbb_pcmcia_socket_disable, 226 pccbb_pcmcia_socket_settype, 227 pccbb_pcmcia_card_detect 228 }; 229 230 #if rbus 231 static const struct cardbus_functions pccbb_funcs = { 232 pccbb_rbus_cb_space_alloc, 233 pccbb_rbus_cb_space_free, 234 pccbb_cb_intr_establish, 235 pccbb_cb_intr_disestablish, 236 pccbb_ctrl, 237 pccbb_power_ct, 238 pccbb_make_tag, 239 pccbb_conf_read, 240 pccbb_conf_write, 241 }; 242 #else 243 static const struct cardbus_functions pccbb_funcs = { 244 pccbb_ctrl, 245 pccbb_power_ct, 246 pccbb_mem_open, 247 pccbb_mem_close, 248 pccbb_io_open, 249 pccbb_io_close, 250 pccbb_cb_intr_establish, 251 pccbb_cb_intr_disestablish, 252 pccbb_make_tag, 253 pccbb_conf_read, 254 pccbb_conf_write, 255 }; 256 #endif 257 258 int 259 pcicbbmatch(device_t parent, cfdata_t match, void *aux) 260 { 261 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 262 263 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 264 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 265 PCI_INTERFACE(pa->pa_class) == 0) { 266 return 1; 267 } 268 269 return 0; 270 } 271 272 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 273 | ((prod) << PCI_PRODUCT_SHIFT)) 274 275 const struct yenta_chipinfo { 276 pcireg_t yc_id; /* vendor tag | product tag */ 277 int yc_chiptype; 278 int yc_flags; 279 } yc_chipsets[] = { 280 /* Texas Instruments chips */ 281 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 282 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 283 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 284 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 285 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI125X, 286 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 287 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 288 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 289 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 290 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 291 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 292 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 293 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI125X, 294 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 295 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI125X, 296 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 297 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 298 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 299 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 300 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 301 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI1420, 302 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 303 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI125X, 304 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 305 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 306 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 307 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1520), CB_TI12XX, 308 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 309 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4410YENTA), CB_TI12XX, 310 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 311 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4520YENTA), CB_TI12XX, 312 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 313 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI7420YENTA), CB_TI12XX, 314 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 315 316 /* Ricoh chips */ 317 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 318 PCCBB_PCMCIA_MEM_32}, 319 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 320 PCCBB_PCMCIA_MEM_32}, 321 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 322 PCCBB_PCMCIA_MEM_32}, 323 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 324 PCCBB_PCMCIA_MEM_32}, 325 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 326 PCCBB_PCMCIA_MEM_32}, 327 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 328 PCCBB_PCMCIA_MEM_32}, 329 330 /* Toshiba products */ 331 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 332 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 333 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 334 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 335 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 336 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 337 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 338 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 339 340 /* Cirrus Logic products */ 341 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 342 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 343 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 344 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 345 346 /* O2 Micro products */ 347 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6729), 348 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 349 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6730), 350 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 351 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6832), 352 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 353 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6836), 354 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 355 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6872), 356 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 357 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6922), 358 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 359 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6933), 360 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 361 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6972), 362 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 363 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_7223), 364 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 365 366 /* sentinel, or Generic chip */ 367 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 368 }; 369 370 static int 371 cb_chipset(u_int32_t pci_id, int *flagp) 372 { 373 const struct yenta_chipinfo *yc; 374 375 /* Loop over except the last default entry. */ 376 for (yc = yc_chipsets; yc < yc_chipsets + 377 __arraycount(yc_chipsets) - 1; yc++) 378 if (pci_id == yc->yc_id) 379 break; 380 381 if (flagp != NULL) 382 *flagp = yc->yc_flags; 383 384 return (yc->yc_chiptype); 385 } 386 387 void 388 pccbbchilddet(device_t self, device_t child) 389 { 390 struct pccbb_softc *sc = device_private(self); 391 int s; 392 393 KASSERT(sc->sc_csc == device_private(child)); 394 395 s = splbio(); 396 if (sc->sc_csc == device_private(child)) 397 sc->sc_csc = NULL; 398 splx(s); 399 } 400 401 void 402 pccbbattach(device_t parent, device_t self, void *aux) 403 { 404 struct pccbb_softc *sc = device_private(self); 405 struct pci_attach_args *pa = aux; 406 pci_chipset_tag_t pc = pa->pa_pc; 407 pcireg_t busreg, reg, sock_base; 408 bus_addr_t sockbase; 409 char devinfo[256]; 410 int flags; 411 412 #ifdef __HAVE_PCCBB_ATTACH_HOOK 413 pccbb_attach_hook(parent, self, pa); 414 #endif 415 416 sc->sc_dev = self; 417 418 mutex_init(&sc->sc_pwr_mtx, MUTEX_DEFAULT, IPL_BIO); 419 cv_init(&sc->sc_pwr_cv, "pccpwr"); 420 421 callout_init(&sc->sc_insert_ch, 0); 422 callout_setfunc(&sc->sc_insert_ch, pci113x_insert, sc); 423 424 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 425 426 aprint_naive("\n"); 427 428 pci_devinfo(pa->pa_id, 0, 0, devinfo, sizeof(devinfo)); 429 aprint_normal(": %s (rev. 0x%02x)", devinfo, 430 PCI_REVISION(pa->pa_class)); 431 DPRINTF((" (chipflags %x)", flags)); 432 aprint_normal("\n"); 433 434 TAILQ_INIT(&sc->sc_memwindow); 435 TAILQ_INIT(&sc->sc_iowindow); 436 437 #if rbus 438 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 439 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 440 441 #if 0 442 printf("pa->pa_memt: %08x vs rbus_mem->rb_bt: %08x\n", 443 pa->pa_memt, sc->sc_rbus_memt->rb_bt); 444 #endif 445 #endif /* rbus */ 446 447 sc->sc_flags &= ~CBB_MEMHMAPPED; 448 449 /* 450 * MAP socket registers and ExCA registers on memory-space 451 * When no valid address is set on socket base registers (on pci 452 * config space), get it not polite way. 453 */ 454 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 455 456 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 457 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 458 /* The address must be valid. */ 459 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 460 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, &sc->sc_base_size)) { 461 aprint_error_dev(self, 462 "can't map socket base address 0x%lx\n", 463 (unsigned long)sock_base); 464 /* 465 * I think it's funny: socket base registers must be 466 * mapped on memory space, but ... 467 */ 468 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 469 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 470 &sc->sc_base_size)) { 471 aprint_error_dev(self, 472 "can't map socket base address" 473 " 0x%lx: io mode\n", 474 (unsigned long)sockbase); 475 /* give up... allocate reg space via rbus. */ 476 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 477 } else 478 sc->sc_flags |= CBB_MEMHMAPPED; 479 } else { 480 DPRINTF(("%s: socket base address 0x%lx\n", 481 device_xname(self), 482 (unsigned long)sockbase)); 483 sc->sc_flags |= CBB_MEMHMAPPED; 484 } 485 } 486 487 sc->sc_mem_start = 0; /* XXX */ 488 sc->sc_mem_end = 0xffffffff; /* XXX */ 489 490 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 491 492 /* pccbb_machdep.c end */ 493 494 #if defined CBB_DEBUG 495 { 496 static const char *intrname[] = { "NON", "A", "B", "C", "D" }; 497 aprint_debug_dev(self, "intrpin %s, intrtag %d\n", 498 intrname[pa->pa_intrpin], pa->pa_intrline); 499 } 500 #endif 501 502 /* setup softc */ 503 sc->sc_pc = pc; 504 sc->sc_iot = pa->pa_iot; 505 sc->sc_memt = pa->pa_memt; 506 sc->sc_dmat = pa->pa_dmat; 507 sc->sc_tag = pa->pa_tag; 508 509 memcpy(&sc->sc_pa, pa, sizeof(*pa)); 510 511 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 512 513 /* Disable legacy register mapping. */ 514 switch (sc->sc_chipset) { 515 case CB_RX5C46X: /* fallthrough */ 516 #if 0 517 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 518 case CB_RX5C47X: 519 #endif 520 /* 521 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 522 * cannot be disabled by substituting 0 into PCI_LEGACY 523 * register. Ricoh CardBus bridges have special bits on Bridge 524 * control reg (addr 0x3e on PCI config space). 525 */ 526 reg = pci_conf_read(pc, pa->pa_tag, PCI_BRIDGE_CONTROL_REG); 527 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 528 pci_conf_write(pc, pa->pa_tag, PCI_BRIDGE_CONTROL_REG, reg); 529 break; 530 531 default: 532 /* XXX I don't know proper way to kill legacy I/O. */ 533 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 534 break; 535 } 536 537 if (!pmf_device_register(self, pccbb_suspend, pccbb_resume)) 538 aprint_error_dev(self, "couldn't establish power handler\n"); 539 540 config_defer(self, pccbb_pci_callback); 541 } 542 543 int 544 pccbbdetach(device_t self, int flags) 545 { 546 struct pccbb_softc *sc = device_private(self); 547 pci_chipset_tag_t pc = sc->sc_pa.pa_pc; 548 bus_space_tag_t bmt = sc->sc_base_memt; 549 bus_space_handle_t bmh = sc->sc_base_memh; 550 uint32_t sockmask; 551 int rc; 552 553 if ((rc = config_detach_children(self, flags)) != 0) 554 return rc; 555 556 if (!LIST_EMPTY(&sc->sc_pil)) { 557 panic("%s: interrupt handlers still registered", 558 device_xname(self)); 559 return EBUSY; 560 } 561 562 if (sc->sc_ih != NULL) { 563 pci_intr_disestablish(pc, sc->sc_ih); 564 sc->sc_ih = NULL; 565 } 566 567 /* CSC Interrupt: turn off card detect and power cycle interrupts */ 568 sockmask = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 569 sockmask &= ~(CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | 570 CB_SOCKET_MASK_POWER); 571 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, sockmask); 572 /* reset interrupt */ 573 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 574 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 575 576 switch (sc->sc_flags & (CBB_MEMHMAPPED|CBB_SPECMAPPED)) { 577 case CBB_MEMHMAPPED: 578 bus_space_unmap(bmt, bmh, sc->sc_base_size); 579 break; 580 case CBB_MEMHMAPPED|CBB_SPECMAPPED: 581 #if rbus 582 { 583 pcireg_t sockbase; 584 585 sockbase = pci_conf_read(pc, sc->sc_tag, PCI_SOCKBASE); 586 rbus_space_free(sc->sc_rbus_memt, bmh, 0x1000, 587 NULL); 588 } 589 #else 590 bus_space_free(bmt, bmh, 0x1000); 591 #endif 592 } 593 sc->sc_flags &= ~(CBB_MEMHMAPPED|CBB_SPECMAPPED); 594 595 if (!TAILQ_EMPTY(&sc->sc_iowindow)) 596 aprint_error_dev(self, "i/o windows not empty"); 597 if (!TAILQ_EMPTY(&sc->sc_memwindow)) 598 aprint_error_dev(self, "memory windows not empty"); 599 600 callout_stop(&sc->sc_insert_ch); 601 callout_destroy(&sc->sc_insert_ch); 602 603 mutex_destroy(&sc->sc_pwr_mtx); 604 cv_destroy(&sc->sc_pwr_cv); 605 606 return 0; 607 } 608 609 /* 610 * static void pccbb_pci_callback(device_t self) 611 * 612 * The actual attach routine: get memory space for YENTA register 613 * space, setup YENTA register and route interrupt. 614 * 615 * This function should be deferred because this device may obtain 616 * memory space dynamically. This function must avoid obtaining 617 * memory area which has already kept for another device. 618 */ 619 static void 620 pccbb_pci_callback(device_t self) 621 { 622 struct pccbb_softc *sc = device_private(self); 623 pci_chipset_tag_t pc = sc->sc_pc; 624 bus_addr_t sockbase; 625 struct cbslot_attach_args cba; 626 struct pcmciabus_attach_args paa; 627 struct cardslot_attach_args caa; 628 device_t csc; 629 630 if (!(sc->sc_flags & CBB_MEMHMAPPED)) { 631 /* The socket registers aren't mapped correctly. */ 632 #if rbus 633 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 634 (sc->sc_chipset == CB_RX5C47X 635 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 636 0, &sockbase, &sc->sc_base_memh)) { 637 return; 638 } 639 sc->sc_base_memt = sc->sc_memt; 640 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 641 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 642 device_xname(self), (unsigned long)sockbase, 643 (unsigned long)pci_conf_read(pc, sc->sc_tag, 644 PCI_SOCKBASE))); 645 #else 646 sc->sc_base_memt = sc->sc_memt; 647 #if !defined CBB_PCI_BASE 648 #define CBB_PCI_BASE 0x20000000 649 #endif 650 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 651 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 652 /* cannot allocate memory space */ 653 return; 654 } 655 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 656 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 657 device_xname(self), (unsigned long)sock_base, 658 (unsigned long)pci_conf_read(pc, 659 sc->sc_tag, PCI_SOCKBASE))); 660 #endif 661 sc->sc_flags |= CBB_MEMHMAPPED|CBB_SPECMAPPED; 662 } 663 664 /* clear data structure for child device interrupt handlers */ 665 LIST_INIT(&sc->sc_pil); 666 667 /* bus bridge initialization */ 668 pccbb_chipinit(sc); 669 670 sc->sc_pil_intr_enable = 1; 671 672 { 673 u_int32_t sockstat; 674 675 sockstat = bus_space_read_4(sc->sc_base_memt, 676 sc->sc_base_memh, CB_SOCKET_STAT); 677 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 678 sc->sc_flags |= CBB_CARDEXIST; 679 } 680 } 681 682 /* 683 * attach cardbus 684 */ 685 { 686 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 687 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 688 689 /* initialize cbslot_attach */ 690 cba.cba_iot = sc->sc_iot; 691 cba.cba_memt = sc->sc_memt; 692 cba.cba_dmat = sc->sc_dmat; 693 cba.cba_bus = (busreg >> 8) & 0x0ff; 694 cba.cba_cc = (void *)sc; 695 cba.cba_cf = &pccbb_funcs; 696 cba.cba_intrline = 0; /* XXX dummy */ 697 698 #if rbus 699 cba.cba_rbus_iot = sc->sc_rbus_iot; 700 cba.cba_rbus_memt = sc->sc_rbus_memt; 701 #endif 702 703 cba.cba_cacheline = PCI_CACHELINE(bhlc); 704 cba.cba_max_lattimer = PCI_LATTIMER(bhlc); 705 706 aprint_verbose_dev(self, 707 "cacheline 0x%x lattimer 0x%x\n", 708 cba.cba_cacheline, 709 cba.cba_max_lattimer); 710 aprint_verbose_dev(self, "bhlc 0x%x\n", bhlc); 711 #if defined SHOW_REGS 712 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 713 sc->sc_base_memh); 714 #endif 715 } 716 717 pccbb_pcmcia_attach_setup(sc, &paa); 718 caa.caa_cb_attach = NULL; 719 if (cba.cba_bus == 0) 720 aprint_error_dev(self, 721 "secondary bus number uninitialized; try PCI_BUS_FIXUP\n"); 722 else 723 caa.caa_cb_attach = &cba; 724 caa.caa_16_attach = &paa; 725 726 pccbb_intrinit(sc); 727 728 if (NULL != (csc = config_found_ia(self, "pcmciaslot", &caa, 729 cbbprint))) { 730 DPRINTF(("%s: found cardslot\n", __func__)); 731 sc->sc_csc = device_private(csc); 732 } 733 734 return; 735 } 736 737 738 739 740 741 /* 742 * static void pccbb_chipinit(struct pccbb_softc *sc) 743 * 744 * This function initialize YENTA chip registers listed below: 745 * 1) PCI command reg, 746 * 2) PCI and CardBus latency timer, 747 * 3) route PCI interrupt, 748 * 4) close all memory and io windows. 749 * 5) turn off bus power. 750 * 6) card detect and power cycle interrupts on. 751 * 7) clear interrupt 752 */ 753 static void 754 pccbb_chipinit(struct pccbb_softc *sc) 755 { 756 pci_chipset_tag_t pc = sc->sc_pc; 757 pcitag_t tag = sc->sc_tag; 758 bus_space_tag_t bmt = sc->sc_base_memt; 759 bus_space_handle_t bmh = sc->sc_base_memh; 760 pcireg_t bcr, bhlc, cbctl, csr, lscp, mfunc, mrburst, slotctl, sockctl, 761 sysctrl; 762 763 /* 764 * Set PCI command reg. 765 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 766 */ 767 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 768 /* I believe it is harmless. */ 769 csr |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 770 PCI_COMMAND_MASTER_ENABLE); 771 772 /* All O2 Micro chips have broken parity-error reporting 773 * until proven otherwise. The OZ6933 PCI-CardBus Bridge 774 * is known to have the defect---see PR kern/38698. 775 */ 776 if (sc->sc_chipset != CB_O2MICRO) 777 csr |= PCI_COMMAND_PARITY_ENABLE; 778 779 csr |= PCI_COMMAND_SERR_ENABLE; 780 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 781 782 /* 783 * Set CardBus latency timer. 784 */ 785 lscp = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 786 if (PCI_CB_LATENCY(lscp) < 0x20) { 787 lscp &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 788 lscp |= (0x20 << PCI_CB_LATENCY_SHIFT); 789 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, lscp); 790 } 791 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 792 PCI_CB_LATENCY(lscp), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 793 794 /* 795 * Set PCI latency timer. 796 */ 797 bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG); 798 if (PCI_LATTIMER(bhlc) < 0x10) { 799 bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 800 bhlc |= (0x10 << PCI_LATTIMER_SHIFT); 801 pci_conf_write(pc, tag, PCI_BHLC_REG, bhlc); 802 } 803 DPRINTF(("PCI latency timer 0x%x (%x)\n", 804 PCI_LATTIMER(bhlc), pci_conf_read(pc, tag, PCI_BHLC_REG))); 805 806 807 /* Route functional interrupts to PCI. */ 808 bcr = pci_conf_read(pc, tag, PCI_BRIDGE_CONTROL_REG); 809 bcr |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 810 bcr |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 811 /* assert reset */ 812 bcr |= PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT; 813 /* Set master abort mode to 1, forward SERR# from secondary 814 * to primary, and detect parity errors on secondary. 815 */ 816 bcr |= PCI_BRIDGE_CONTROL_MABRT << PCI_BRIDGE_CONTROL_SHIFT; 817 bcr |= PCI_BRIDGE_CONTROL_SERR << PCI_BRIDGE_CONTROL_SHIFT; 818 bcr |= PCI_BRIDGE_CONTROL_PERE << PCI_BRIDGE_CONTROL_SHIFT; 819 pci_conf_write(pc, tag, PCI_BRIDGE_CONTROL_REG, bcr); 820 821 switch (sc->sc_chipset) { 822 case CB_TI113X: 823 cbctl = pci_conf_read(pc, tag, PCI_CBCTRL); 824 /* This bit is shared, but may read as 0 on some chips, so set 825 it explicitly on both functions. */ 826 cbctl |= PCI113X_CBCTRL_PCI_IRQ_ENA; 827 /* CSC intr enable */ 828 cbctl |= PCI113X_CBCTRL_PCI_CSC; 829 /* functional intr prohibit | prohibit ISA routing */ 830 cbctl &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 831 pci_conf_write(pc, tag, PCI_CBCTRL, cbctl); 832 break; 833 834 case CB_TI1420: 835 sysctrl = pci_conf_read(pc, tag, PCI_SYSCTRL); 836 mrburst = pccbb_burstup 837 ? PCI1420_SYSCTRL_MRBURST : PCI1420_SYSCTRL_MRBURSTDN; 838 if ((sysctrl & PCI1420_SYSCTRL_MRBURST) == mrburst) { 839 printf("%s: %swrite bursts enabled\n", 840 device_xname(sc->sc_dev), 841 pccbb_burstup ? "read/" : ""); 842 } else if (pccbb_burstup) { 843 printf("%s: enabling read/write bursts\n", 844 device_xname(sc->sc_dev)); 845 sysctrl |= PCI1420_SYSCTRL_MRBURST; 846 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 847 } else { 848 printf("%s: disabling read bursts, " 849 "enabling write bursts\n", 850 device_xname(sc->sc_dev)); 851 sysctrl |= PCI1420_SYSCTRL_MRBURSTDN; 852 sysctrl &= ~PCI1420_SYSCTRL_MRBURSTUP; 853 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 854 } 855 /*FALLTHROUGH*/ 856 case CB_TI12XX: 857 /* 858 * Some TI 12xx (and [14][45]xx) based pci cards 859 * sometimes have issues with the MFUNC register not 860 * being initialized due to a bad EEPROM on board. 861 * Laptops that this matters on have this register 862 * properly initialized. 863 * 864 * The TI125X parts have a different register. 865 */ 866 mfunc = pci_conf_read(pc, tag, PCI12XX_MFUNC); 867 if (mfunc == 0) { 868 mfunc &= ~PCI12XX_MFUNC_PIN0; 869 mfunc |= PCI12XX_MFUNC_PIN0_INTA; 870 if ((pci_conf_read(pc, tag, PCI_SYSCTRL) & 871 PCI12XX_SYSCTRL_INTRTIE) == 0) { 872 mfunc &= ~PCI12XX_MFUNC_PIN1; 873 mfunc |= PCI12XX_MFUNC_PIN1_INTB; 874 } 875 pci_conf_write(pc, tag, PCI12XX_MFUNC, mfunc); 876 } 877 /* fallthrough */ 878 879 case CB_TI125X: 880 /* 881 * Disable zoom video. Some machines initialize this 882 * improperly and experience has shown that this helps 883 * prevent strange behavior. 884 */ 885 pci_conf_write(pc, tag, PCI12XX_MMCTRL, 0); 886 887 sysctrl = pci_conf_read(pc, tag, PCI_SYSCTRL); 888 sysctrl |= PCI12XX_SYSCTRL_VCCPROT; 889 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 890 cbctl = pci_conf_read(pc, tag, PCI_CBCTRL); 891 cbctl |= PCI12XX_CBCTRL_CSC; 892 pci_conf_write(pc, tag, PCI_CBCTRL, cbctl); 893 break; 894 895 case CB_TOPIC95B: 896 sockctl = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 897 sockctl |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 898 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, sockctl); 899 slotctl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 900 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 901 device_xname(sc->sc_dev), slotctl)); 902 slotctl |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 903 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 904 slotctl &= ~TOPIC_SLOT_CTRL_SWDETECT; 905 DPRINTF(("0x%x\n", slotctl)); 906 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slotctl); 907 break; 908 909 case CB_TOPIC97: 910 slotctl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 911 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 912 device_xname(sc->sc_dev), slotctl)); 913 slotctl |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 914 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 915 slotctl &= ~TOPIC_SLOT_CTRL_SWDETECT; 916 slotctl |= TOPIC97_SLOT_CTRL_PCIINT; 917 slotctl &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 918 DPRINTF(("0x%x\n", slotctl)); 919 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slotctl); 920 /* make sure to assert LV card support bits */ 921 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 922 0x800 + 0x3e, 923 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 924 0x800 + 0x3e) | 0x03); 925 break; 926 } 927 928 /* Close all memory and I/O windows. */ 929 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 930 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 931 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 932 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 933 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 934 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 935 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 936 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 937 938 /* reset 16-bit pcmcia bus */ 939 bus_space_write_1(bmt, bmh, 0x800 + PCIC_INTR, 940 bus_space_read_1(bmt, bmh, 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 941 942 /* turn off power */ 943 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 944 } 945 946 static void 947 pccbb_intrinit(struct pccbb_softc *sc) 948 { 949 pcireg_t sockmask; 950 const char *intrstr = NULL; 951 pci_intr_handle_t ih; 952 pci_chipset_tag_t pc = sc->sc_pc; 953 bus_space_tag_t bmt = sc->sc_base_memt; 954 bus_space_handle_t bmh = sc->sc_base_memh; 955 956 /* Map and establish the interrupt. */ 957 if (pci_intr_map(&sc->sc_pa, &ih)) { 958 aprint_error_dev(sc->sc_dev, "couldn't map interrupt\n"); 959 return; 960 } 961 intrstr = pci_intr_string(pc, ih); 962 963 /* 964 * XXX pccbbintr should be called under the priority lower 965 * than any other hard interrupts. 966 */ 967 KASSERT(sc->sc_ih == NULL); 968 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 969 970 if (sc->sc_ih == NULL) { 971 aprint_error_dev(sc->sc_dev, "couldn't establish interrupt"); 972 if (intrstr != NULL) 973 aprint_error(" at %s\n", intrstr); 974 else 975 aprint_error("\n"); 976 return; 977 } 978 979 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 980 981 /* CSC Interrupt: Card detect and power cycle interrupts on */ 982 sockmask = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 983 sockmask |= CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | 984 CB_SOCKET_MASK_POWER; 985 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, sockmask); 986 /* reset interrupt */ 987 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 988 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 989 } 990 991 /* 992 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 993 * struct pcmciabus_attach_args *paa) 994 * 995 * This function attaches 16-bit PCcard bus. 996 */ 997 STATIC void 998 pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 999 struct pcmciabus_attach_args *paa) 1000 { 1001 #if rbus 1002 rbus_tag_t rb; 1003 #endif 1004 /* 1005 * We need to do a few things here: 1006 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 1007 * setting the IRQ numbers to 0. 1008 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 1009 * routing of CSC interrupts (e.g. card removal) to PCI while in 1010 * PCMCIA mode. We just leave this set all the time. 1011 * 3) Enable card insertion/removal interrupts in case the chip also 1012 * needs that while in PCMCIA mode. 1013 * 4) Clear any pending CSC interrupt. 1014 */ 1015 Pcic_write(sc, PCIC_INTR, PCIC_INTR_ENABLE); 1016 if (sc->sc_chipset == CB_TI113X) { 1017 Pcic_write(sc, PCIC_CSC_INTR, 0); 1018 } else { 1019 Pcic_write(sc, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 1020 Pcic_read(sc, PCIC_CSC); 1021 } 1022 1023 /* initialize pcmcia bus attachment */ 1024 paa->paa_busname = "pcmcia"; 1025 paa->pct = &pccbb_pcmcia_funcs; 1026 paa->pch = sc; 1027 paa->iobase = 0; /* I don't use them */ 1028 paa->iosize = 0; 1029 #if rbus 1030 rb = sc->sc_rbus_iot; 1031 paa->iobase = rb->rb_start + rb->rb_offset; 1032 paa->iosize = rb->rb_end - rb->rb_start; 1033 #endif 1034 1035 return; 1036 } 1037 1038 /* 1039 * int pccbbintr(arg) 1040 * void *arg; 1041 * This routine handles the interrupt from Yenta PCI-CardBus bridge 1042 * itself. 1043 */ 1044 int 1045 pccbbintr(void *arg) 1046 { 1047 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1048 struct cardslot_softc *csc; 1049 u_int32_t sockevent, sockstate; 1050 bus_space_tag_t memt = sc->sc_base_memt; 1051 bus_space_handle_t memh = sc->sc_base_memh; 1052 1053 if (!device_has_power(sc->sc_dev)) 1054 return 0; 1055 1056 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 1057 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 1058 Pcic_read(sc, PCIC_CSC); 1059 1060 if (sockevent != 0) { 1061 aprint_debug("%s: enter sockevent %" PRIx32 "\n", __func__, 1062 sockevent); 1063 } 1064 1065 /* XXX sockevent == CB_SOCKET_EVENT_CSTS|CB_SOCKET_EVENT_POWER 1066 * does occur in the wild. Check for a _POWER event before 1067 * possibly exiting because of an _CSTS event. 1068 */ 1069 if (sockevent & CB_SOCKET_EVENT_POWER) { 1070 DPRINTF(("Powercycling because of socket event\n")); 1071 /* XXX: Does not happen when attaching a 16-bit card */ 1072 mutex_enter(&sc->sc_pwr_mtx); 1073 sc->sc_pwrcycle++; 1074 cv_signal(&sc->sc_pwr_cv); 1075 mutex_exit(&sc->sc_pwr_mtx); 1076 } 1077 1078 /* Sometimes a change of CSTSCHG# accompanies the first 1079 * interrupt from an Atheros WLAN. That generates a 1080 * CB_SOCKET_EVENT_CSTS event on the bridge. The event 1081 * isn't interesting to pccbb(4), so we used to ignore the 1082 * interrupt. Now, let the child devices try to handle 1083 * the interrupt, instead. The Atheros NIC produces 1084 * interrupts more reliably, now: used to be that it would 1085 * only interrupt if the driver avoided powering down the 1086 * NIC's cardslot, and then the NIC would only work after 1087 * it was reset a second time. 1088 */ 1089 if (sockevent == 0 || 1090 (sockevent & ~(CB_SOCKET_EVENT_POWER|CB_SOCKET_EVENT_CD)) != 0) { 1091 /* This intr is not for me: it may be for my child devices. */ 1092 if (sc->sc_pil_intr_enable) { 1093 return pccbbintr_function(sc); 1094 } else { 1095 return 0; 1096 } 1097 } 1098 1099 if (sockevent & CB_SOCKET_EVENT_CD) { 1100 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1101 if (0x00 != (sockstate & CB_SOCKET_STAT_CD)) { 1102 /* A card should be removed. */ 1103 if (sc->sc_flags & CBB_CARDEXIST) { 1104 DPRINTF(("%s: 0x%08x", 1105 device_xname(sc->sc_dev), sockevent)); 1106 DPRINTF((" card removed, 0x%08x\n", sockstate)); 1107 sc->sc_flags &= ~CBB_CARDEXIST; 1108 if ((csc = sc->sc_csc) == NULL) 1109 ; 1110 else if (csc->sc_status & 1111 CARDSLOT_STATUS_CARD_16) { 1112 cardslot_event_throw(csc, 1113 CARDSLOT_EVENT_REMOVAL_16); 1114 } else if (csc->sc_status & 1115 CARDSLOT_STATUS_CARD_CB) { 1116 /* Cardbus intr removed */ 1117 cardslot_event_throw(csc, 1118 CARDSLOT_EVENT_REMOVAL_CB); 1119 } 1120 } else if (sc->sc_flags & CBB_INSERTING) { 1121 sc->sc_flags &= ~CBB_INSERTING; 1122 callout_stop(&sc->sc_insert_ch); 1123 } 1124 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 1125 /* 1126 * The pccbbintr may called from powerdown hook when 1127 * the system resumed, to detect the card 1128 * insertion/removal during suspension. 1129 */ 1130 (sc->sc_flags & CBB_CARDEXIST) == 0) { 1131 if (sc->sc_flags & CBB_INSERTING) { 1132 callout_stop(&sc->sc_insert_ch); 1133 } 1134 callout_schedule(&sc->sc_insert_ch, mstohz(200)); 1135 sc->sc_flags |= CBB_INSERTING; 1136 } 1137 } 1138 1139 return (1); 1140 } 1141 1142 /* 1143 * static int pccbbintr_function(struct pccbb_softc *sc) 1144 * 1145 * This function calls each interrupt handler registered at the 1146 * bridge. The interrupt handlers are called in registered order. 1147 */ 1148 static int 1149 pccbbintr_function(struct pccbb_softc *sc) 1150 { 1151 int retval = 0, val; 1152 struct pccbb_intrhand_list *pil; 1153 int s; 1154 1155 LIST_FOREACH(pil, &sc->sc_pil, pil_next) { 1156 s = splraiseipl(pil->pil_icookie); 1157 val = (*pil->pil_func)(pil->pil_arg); 1158 splx(s); 1159 1160 retval = retval == 1 ? 1 : 1161 retval == 0 ? val : val != 0 ? val : retval; 1162 } 1163 1164 return retval; 1165 } 1166 1167 static void 1168 pci113x_insert(void *arg) 1169 { 1170 struct pccbb_softc *sc = arg; 1171 struct cardslot_softc *csc; 1172 u_int32_t sockevent, sockstate; 1173 1174 if (!(sc->sc_flags & CBB_INSERTING)) { 1175 /* We add a card only under inserting state. */ 1176 return; 1177 } 1178 sc->sc_flags &= ~CBB_INSERTING; 1179 1180 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1181 CB_SOCKET_EVENT); 1182 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1183 CB_SOCKET_STAT); 1184 1185 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1186 DPRINTF(("%s: 0x%08x", device_xname(sc->sc_dev), sockevent)); 1187 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1188 sc->sc_flags |= CBB_CARDEXIST; 1189 /* call pccard interrupt handler here */ 1190 if ((csc = sc->sc_csc) == NULL) 1191 ; 1192 else if (sockstate & CB_SOCKET_STAT_16BIT) { 1193 /* 16-bit card found */ 1194 cardslot_event_throw(csc, CARDSLOT_EVENT_INSERTION_16); 1195 } else if (sockstate & CB_SOCKET_STAT_CB) { 1196 /* cardbus card found */ 1197 cardslot_event_throw(csc, CARDSLOT_EVENT_INSERTION_CB); 1198 } else { 1199 /* who are you? */ 1200 } 1201 } else { 1202 callout_schedule(&sc->sc_insert_ch, mstohz(100)); 1203 } 1204 } 1205 1206 #define PCCBB_PCMCIA_OFFSET 0x800 1207 static u_int8_t 1208 pccbb_pcmcia_read(struct pccbb_softc *sc, int reg) 1209 { 1210 bus_space_barrier(sc->sc_base_memt, sc->sc_base_memh, 1211 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1212 1213 return bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 1214 PCCBB_PCMCIA_OFFSET + reg); 1215 } 1216 1217 static void 1218 pccbb_pcmcia_write(struct pccbb_softc *sc, int reg, u_int8_t val) 1219 { 1220 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 1221 PCCBB_PCMCIA_OFFSET + reg, val); 1222 1223 bus_space_barrier(sc->sc_base_memt, sc->sc_base_memh, 1224 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1225 } 1226 1227 /* 1228 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1229 */ 1230 STATIC int 1231 pccbb_ctrl(cardbus_chipset_tag_t ct, int command) 1232 { 1233 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1234 1235 switch (command) { 1236 case CARDBUS_CD: 1237 if (2 == pccbb_detect_card(sc)) { 1238 int retval = 0; 1239 int status = cb_detect_voltage(sc); 1240 if (PCCARD_VCC_5V & status) { 1241 retval |= CARDBUS_5V_CARD; 1242 } 1243 if (PCCARD_VCC_3V & status) { 1244 retval |= CARDBUS_3V_CARD; 1245 } 1246 if (PCCARD_VCC_XV & status) { 1247 retval |= CARDBUS_XV_CARD; 1248 } 1249 if (PCCARD_VCC_YV & status) { 1250 retval |= CARDBUS_YV_CARD; 1251 } 1252 return retval; 1253 } else { 1254 return 0; 1255 } 1256 case CARDBUS_RESET: 1257 return cb_reset(sc); 1258 case CARDBUS_IO_ENABLE: /* fallthrough */ 1259 case CARDBUS_IO_DISABLE: /* fallthrough */ 1260 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1261 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1262 case CARDBUS_BM_ENABLE: /* fallthrough */ 1263 case CARDBUS_BM_DISABLE: /* fallthrough */ 1264 /* XXX: I think we don't need to call this function below. */ 1265 return pccbb_cardenable(sc, command); 1266 } 1267 1268 return 0; 1269 } 1270 1271 STATIC int 1272 pccbb_power_ct(cardbus_chipset_tag_t ct, int command) 1273 { 1274 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1275 1276 return pccbb_power(sc, command); 1277 } 1278 1279 /* 1280 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1281 * This function returns true when it succeeds and returns false when 1282 * it fails. 1283 */ 1284 STATIC int 1285 pccbb_power(struct pccbb_softc *sc, int command) 1286 { 1287 u_int32_t status, osock_ctrl, sock_ctrl, reg_ctrl; 1288 bus_space_tag_t memt = sc->sc_base_memt; 1289 bus_space_handle_t memh = sc->sc_base_memh; 1290 int on = 0, pwrcycle, times; 1291 struct timeval before, after, diff; 1292 1293 DPRINTF(("pccbb_power: %s and %s [0x%x]\n", 1294 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1295 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1296 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1297 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1298 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1299 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1300 "UNKNOWN", 1301 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1302 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1303 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1304 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1305 "UNKNOWN", command)); 1306 1307 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1308 osock_ctrl = sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1309 1310 switch (command & CARDBUS_VCCMASK) { 1311 case CARDBUS_VCC_UC: 1312 break; 1313 case CARDBUS_VCC_5V: 1314 on++; 1315 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1316 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1317 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1318 } else { 1319 aprint_error_dev(sc->sc_dev, 1320 "BAD voltage request: no 5 V card\n"); 1321 return 0; 1322 } 1323 break; 1324 case CARDBUS_VCC_3V: 1325 on++; 1326 if (CB_SOCKET_STAT_3VCARD & status) { 1327 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1328 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1329 } else { 1330 aprint_error_dev(sc->sc_dev, 1331 "BAD voltage request: no 3.3 V card\n"); 1332 return 0; 1333 } 1334 break; 1335 case CARDBUS_VCC_0V: 1336 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1337 break; 1338 default: 1339 return 0; /* power NEVER changed */ 1340 } 1341 1342 switch (command & CARDBUS_VPPMASK) { 1343 case CARDBUS_VPP_UC: 1344 break; 1345 case CARDBUS_VPP_0V: 1346 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1347 break; 1348 case CARDBUS_VPP_VCC: 1349 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1350 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1351 break; 1352 case CARDBUS_VPP_12V: 1353 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1354 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1355 break; 1356 } 1357 aprint_debug_dev(sc->sc_dev, "osock_ctrl %#" PRIx32 1358 " sock_ctrl %#" PRIx32 "\n", osock_ctrl, sock_ctrl); 1359 1360 microtime(&before); 1361 mutex_enter(&sc->sc_pwr_mtx); 1362 pwrcycle = sc->sc_pwrcycle; 1363 1364 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1365 1366 /* 1367 * Wait as long as 200ms for a power-cycle interrupt. If 1368 * interrupts are enabled, but the socket has already 1369 * changed to the desired status, keep waiting for the 1370 * interrupt. "Consuming" the interrupt in this way keeps 1371 * the interrupt from prematurely waking some subsequent 1372 * pccbb_power call. 1373 * 1374 * XXX Not every bridge interrupts on the ->OFF transition. 1375 * XXX That's ok, we will time-out after 200ms. 1376 * 1377 * XXX The power cycle event will never happen when attaching 1378 * XXX a 16-bit card. That's ok, we will time-out after 1379 * XXX 200ms. 1380 */ 1381 for (times = 5; --times >= 0; ) { 1382 if (cold) 1383 DELAY(40 * 1000); 1384 else { 1385 (void)cv_timedwait(&sc->sc_pwr_cv, &sc->sc_pwr_mtx, 1386 mstohz(40)); 1387 if (pwrcycle == sc->sc_pwrcycle) 1388 continue; 1389 } 1390 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1391 if ((status & CB_SOCKET_STAT_PWRCYCLE) != 0 && on) 1392 break; 1393 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0 && !on) 1394 break; 1395 } 1396 mutex_exit(&sc->sc_pwr_mtx); 1397 microtime(&after); 1398 timersub(&after, &before, &diff); 1399 aprint_debug_dev(sc->sc_dev, "wait took%s %lld.%06lds\n", 1400 (on && times < 0) ? " too long" : "", (long long)diff.tv_sec, 1401 (long)diff.tv_usec); 1402 1403 /* 1404 * Ok, wait a bit longer for things to settle. 1405 */ 1406 if (on && sc->sc_chipset == CB_TOPIC95B) 1407 delay_ms(100, sc); 1408 1409 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1410 1411 if (on && sc->sc_chipset != CB_TOPIC95B) { 1412 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0) 1413 aprint_error_dev(sc->sc_dev, "power on failed?\n"); 1414 } 1415 1416 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1417 aprint_error_dev(sc->sc_dev, 1418 "bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1419 sock_ctrl, status); 1420 aprint_error_dev(sc->sc_dev, "disabling socket\n"); 1421 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1422 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1423 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1424 status &= ~CB_SOCKET_STAT_BADVCC; 1425 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, status); 1426 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1427 CB_SOCKET_STAT)); 1428 return 0; 1429 } 1430 1431 if (sc->sc_chipset == CB_TOPIC97) { 1432 reg_ctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL); 1433 reg_ctrl &= ~TOPIC97_REG_CTRL_TESTMODE; 1434 if ((command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V) 1435 reg_ctrl &= ~TOPIC97_REG_CTRL_CLKRUN_ENA; 1436 else 1437 reg_ctrl |= TOPIC97_REG_CTRL_CLKRUN_ENA; 1438 pci_conf_write(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL, reg_ctrl); 1439 } 1440 1441 return 1; /* power changed correctly */ 1442 } 1443 1444 /* 1445 * static int pccbb_detect_card(struct pccbb_softc *sc) 1446 * return value: 0 if no card exists. 1447 * 1 if 16-bit card exists. 1448 * 2 if cardbus card exists. 1449 */ 1450 static int 1451 pccbb_detect_card(struct pccbb_softc *sc) 1452 { 1453 bus_space_handle_t base_memh = sc->sc_base_memh; 1454 bus_space_tag_t base_memt = sc->sc_base_memt; 1455 u_int32_t sockstat = 1456 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1457 int retval = 0; 1458 1459 /* CD1 and CD2 asserted */ 1460 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1461 /* card must be present */ 1462 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1463 /* NOTACARD DEASSERTED */ 1464 if (CB_SOCKET_STAT_CB & sockstat) { 1465 /* CardBus mode */ 1466 retval = 2; 1467 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1468 /* 16-bit mode */ 1469 retval = 1; 1470 } 1471 } 1472 } 1473 return retval; 1474 } 1475 1476 /* 1477 * STATIC int cb_reset(struct pccbb_softc *sc) 1478 * This function resets CardBus card. 1479 */ 1480 STATIC int 1481 cb_reset(struct pccbb_softc *sc) 1482 { 1483 /* 1484 * Reset Assert at least 20 ms 1485 * Some machines request longer duration. 1486 */ 1487 int reset_duration = 1488 (sc->sc_chipset == CB_RX5C47X ? 400 : 50); 1489 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1490 aprint_debug("%s: enter bcr %" PRIx32 "\n", __func__, bcr); 1491 1492 /* Reset bit Assert (bit 6 at 0x3E) */ 1493 bcr |= PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT; 1494 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr); 1495 aprint_debug("%s: wrote bcr %" PRIx32 "\n", __func__, bcr); 1496 delay_ms(reset_duration, sc); 1497 1498 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1499 /* Reset bit Deassert (bit 6 at 0x3E) */ 1500 bcr &= ~(PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT); 1501 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, 1502 bcr); 1503 aprint_debug("%s: wrote bcr %" PRIx32 "\n", __func__, bcr); 1504 delay_ms(reset_duration, sc); 1505 aprint_debug("%s: end of delay\n", __func__); 1506 } 1507 /* No card found on the slot. Keep Reset. */ 1508 return 1; 1509 } 1510 1511 /* 1512 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1513 * This function detect card Voltage. 1514 */ 1515 STATIC int 1516 cb_detect_voltage(struct pccbb_softc *sc) 1517 { 1518 u_int32_t psr; /* socket present-state reg */ 1519 bus_space_tag_t iot = sc->sc_base_memt; 1520 bus_space_handle_t ioh = sc->sc_base_memh; 1521 int vol = PCCARD_VCC_UKN; /* set 0 */ 1522 1523 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1524 1525 if (0x400u & psr) { 1526 vol |= PCCARD_VCC_5V; 1527 } 1528 if (0x800u & psr) { 1529 vol |= PCCARD_VCC_3V; 1530 } 1531 1532 return vol; 1533 } 1534 1535 STATIC int 1536 cbbprint(void *aux, const char *pcic) 1537 { 1538 #if 0 1539 struct cbslot_attach_args *cba = aux; 1540 1541 if (cba->cba_slot >= 0) { 1542 aprint_normal(" slot %d", cba->cba_slot); 1543 } 1544 #endif 1545 return UNCONF; 1546 } 1547 1548 /* 1549 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1550 * This function enables and disables the card 1551 */ 1552 STATIC int 1553 pccbb_cardenable(struct pccbb_softc *sc, int function) 1554 { 1555 u_int32_t command = 1556 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1557 1558 DPRINTF(("pccbb_cardenable:")); 1559 switch (function) { 1560 case CARDBUS_IO_ENABLE: 1561 command |= PCI_COMMAND_IO_ENABLE; 1562 break; 1563 case CARDBUS_IO_DISABLE: 1564 command &= ~PCI_COMMAND_IO_ENABLE; 1565 break; 1566 case CARDBUS_MEM_ENABLE: 1567 command |= PCI_COMMAND_MEM_ENABLE; 1568 break; 1569 case CARDBUS_MEM_DISABLE: 1570 command &= ~PCI_COMMAND_MEM_ENABLE; 1571 break; 1572 case CARDBUS_BM_ENABLE: 1573 command |= PCI_COMMAND_MASTER_ENABLE; 1574 break; 1575 case CARDBUS_BM_DISABLE: 1576 command &= ~PCI_COMMAND_MASTER_ENABLE; 1577 break; 1578 default: 1579 return 0; 1580 } 1581 1582 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1583 DPRINTF((" command reg 0x%x\n", command)); 1584 return 1; 1585 } 1586 1587 #if !rbus 1588 static int 1589 pccbb_io_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 1590 { 1591 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1592 int basereg; 1593 int limitreg; 1594 1595 if ((win < 0) || (win > 2)) { 1596 #if defined DIAGNOSTIC 1597 printf("cardbus_io_open: window out of range %d\n", win); 1598 #endif 1599 return 0; 1600 } 1601 1602 basereg = win * 8 + PCI_CB_IOBASE0; 1603 limitreg = win * 8 + PCI_CB_IOLIMIT0; 1604 1605 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1606 start, basereg, end, limitreg)); 1607 1608 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1609 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1610 return 1; 1611 } 1612 1613 /* 1614 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1615 */ 1616 static int 1617 pccbb_io_close(cardbus_chipset_tag_t ct, int win) 1618 { 1619 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1620 int basereg; 1621 int limitreg; 1622 1623 if ((win < 0) || (win > 2)) { 1624 #if defined DIAGNOSTIC 1625 printf("cardbus_io_close: window out of range %d\n", win); 1626 #endif 1627 return 0; 1628 } 1629 1630 basereg = win * 8 + PCI_CB_IOBASE0; 1631 limitreg = win * 8 + PCI_CB_IOLIMIT0; 1632 1633 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1634 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1635 return 1; 1636 } 1637 1638 static int 1639 pccbb_mem_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 1640 { 1641 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1642 int basereg; 1643 int limitreg; 1644 1645 if ((win < 0) || (win > 2)) { 1646 #if defined DIAGNOSTIC 1647 printf("cardbus_mem_open: window out of range %d\n", win); 1648 #endif 1649 return 0; 1650 } 1651 1652 basereg = win * 8 + PCI_CB_MEMBASE0; 1653 limitreg = win * 8 + PCI_CB_MEMLIMIT0; 1654 1655 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1656 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1657 return 1; 1658 } 1659 1660 static int 1661 pccbb_mem_close(cardbus_chipset_tag_t ct, int win) 1662 { 1663 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1664 int basereg; 1665 int limitreg; 1666 1667 if ((win < 0) || (win > 2)) { 1668 #if defined DIAGNOSTIC 1669 printf("cardbus_mem_close: window out of range %d\n", win); 1670 #endif 1671 return 0; 1672 } 1673 1674 basereg = win * 8 + PCI_CB_MEMBASE0; 1675 limitreg = win * 8 + PCI_CB_MEMLIMIT0; 1676 1677 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1678 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1679 return 1; 1680 } 1681 #endif 1682 1683 /* 1684 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1685 * int irq, 1686 * int level, 1687 * int (* func)(void *), 1688 * void *arg) 1689 * 1690 * This function registers an interrupt handler at the bridge, in 1691 * order not to call the interrupt handlers of child devices when 1692 * a card-deletion interrupt occurs. 1693 * 1694 * The arguments irq and level are not used. 1695 */ 1696 static void * 1697 pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, cardbus_intr_line_t irq, 1698 int level, int (*func)(void *), void *arg) 1699 { 1700 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1701 1702 return pccbb_intr_establish(sc, irq, level, func, arg); 1703 } 1704 1705 1706 /* 1707 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1708 * void *ih) 1709 * 1710 * This function removes an interrupt handler pointed by ih. 1711 */ 1712 static void 1713 pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih) 1714 { 1715 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1716 1717 pccbb_intr_disestablish(sc, ih); 1718 } 1719 1720 1721 void 1722 pccbb_intr_route(struct pccbb_softc *sc) 1723 { 1724 pcireg_t bcr, cbctrl; 1725 1726 /* initialize bridge intr routing */ 1727 bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1728 bcr &= ~CB_BCR_INTR_IREQ_ENABLE; 1729 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr); 1730 1731 switch (sc->sc_chipset) { 1732 case CB_TI113X: 1733 cbctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1734 /* functional intr enabled */ 1735 cbctrl |= PCI113X_CBCTRL_PCI_INTR; 1736 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, cbctrl); 1737 break; 1738 default: 1739 break; 1740 } 1741 } 1742 1743 /* 1744 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1745 * int irq, 1746 * int level, 1747 * int (* func)(void *), 1748 * void *arg) 1749 * 1750 * This function registers an interrupt handler at the bridge, in 1751 * order not to call the interrupt handlers of child devices when 1752 * a card-deletion interrupt occurs. 1753 * 1754 * The arguments irq is not used because pccbb selects intr vector. 1755 */ 1756 static void * 1757 pccbb_intr_establish(struct pccbb_softc *sc, cardbus_intr_line_t irq, 1758 int level, int (*func)(void *), void *arg) 1759 { 1760 struct pccbb_intrhand_list *pil, *newpil; 1761 1762 DPRINTF(("pccbb_intr_establish start. %p\n", LIST_FIRST(&sc->sc_pil))); 1763 1764 if (LIST_EMPTY(&sc->sc_pil)) { 1765 pccbb_intr_route(sc); 1766 } 1767 1768 /* 1769 * Allocate a room for interrupt handler structure. 1770 */ 1771 if (NULL == (newpil = 1772 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1773 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1774 return NULL; 1775 } 1776 1777 newpil->pil_func = func; 1778 newpil->pil_arg = arg; 1779 newpil->pil_icookie = makeiplcookie(level); 1780 1781 if (LIST_EMPTY(&sc->sc_pil)) { 1782 LIST_INSERT_HEAD(&sc->sc_pil, newpil, pil_next); 1783 } else { 1784 for (pil = LIST_FIRST(&sc->sc_pil); 1785 LIST_NEXT(pil, pil_next) != NULL; 1786 pil = LIST_NEXT(pil, pil_next)); 1787 LIST_INSERT_AFTER(pil, newpil, pil_next); 1788 } 1789 1790 DPRINTF(("pccbb_intr_establish add pil. %p\n", 1791 LIST_FIRST(&sc->sc_pil))); 1792 1793 return newpil; 1794 } 1795 1796 /* 1797 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1798 * void *ih) 1799 * 1800 * This function removes an interrupt handler pointed by ih. ih 1801 * should be the value returned by cardbus_intr_establish() or 1802 * NULL. 1803 * 1804 * When ih is NULL, this function will do nothing. 1805 */ 1806 static void 1807 pccbb_intr_disestablish(struct pccbb_softc *sc, void *ih) 1808 { 1809 struct pccbb_intrhand_list *pil; 1810 pcireg_t reg; 1811 1812 DPRINTF(("pccbb_intr_disestablish start. %p\n", 1813 LIST_FIRST(&sc->sc_pil))); 1814 1815 if (ih == NULL) { 1816 /* intr handler is not set */ 1817 DPRINTF(("pccbb_intr_disestablish: no ih\n")); 1818 return; 1819 } 1820 1821 #ifdef DIAGNOSTIC 1822 LIST_FOREACH(pil, &sc->sc_pil, pil_next) { 1823 DPRINTF(("pccbb_intr_disestablish: pil %p\n", pil)); 1824 if (pil == ih) { 1825 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1826 break; 1827 } 1828 } 1829 if (pil == NULL) { 1830 panic("pccbb_intr_disestablish: %s cannot find pil %p", 1831 device_xname(sc->sc_dev), ih); 1832 } 1833 #endif 1834 1835 pil = (struct pccbb_intrhand_list *)ih; 1836 LIST_REMOVE(pil, pil_next); 1837 free(pil, M_DEVBUF); 1838 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1839 1840 if (LIST_EMPTY(&sc->sc_pil)) { 1841 /* No interrupt handlers */ 1842 1843 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1844 1845 /* stop routing PCI intr */ 1846 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1847 reg |= CB_BCR_INTR_IREQ_ENABLE; 1848 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, reg); 1849 1850 switch (sc->sc_chipset) { 1851 case CB_TI113X: 1852 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1853 /* functional intr disabled */ 1854 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1855 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1856 break; 1857 default: 1858 break; 1859 } 1860 } 1861 } 1862 1863 #if defined SHOW_REGS 1864 static void 1865 cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, bus_space_tag_t memt, 1866 bus_space_handle_t memh) 1867 { 1868 int i; 1869 printf("PCI config regs:"); 1870 for (i = 0; i < 0x50; i += 4) { 1871 if (i % 16 == 0) 1872 printf("\n 0x%02x:", i); 1873 printf(" %08x", pci_conf_read(pc, tag, i)); 1874 } 1875 for (i = 0x80; i < 0xb0; i += 4) { 1876 if (i % 16 == 0) 1877 printf("\n 0x%02x:", i); 1878 printf(" %08x", pci_conf_read(pc, tag, i)); 1879 } 1880 1881 if (memh == 0) { 1882 printf("\n"); 1883 return; 1884 } 1885 1886 printf("\nsocket regs:"); 1887 for (i = 0; i <= 0x10; i += 0x04) 1888 printf(" %08x", bus_space_read_4(memt, memh, i)); 1889 printf("\nExCA regs:"); 1890 for (i = 0; i < 0x08; ++i) 1891 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1892 printf("\n"); 1893 return; 1894 } 1895 #endif 1896 1897 /* 1898 * static pcitag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1899 * int busno, int function) 1900 * This is the function to make a tag to access config space of 1901 * a CardBus Card. It works same as pci_conf_read. 1902 */ 1903 static pcitag_t 1904 pccbb_make_tag(cardbus_chipset_tag_t cc, int busno, int function) 1905 { 1906 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1907 1908 return pci_make_tag(sc->sc_pc, busno, 0, function); 1909 } 1910 1911 /* 1912 * pccbb_conf_read 1913 * 1914 * This is the function to read the config space of a CardBus card. 1915 * It works the same as pci_conf_read(9). 1916 */ 1917 static pcireg_t 1918 pccbb_conf_read(cardbus_chipset_tag_t cc, pcitag_t tag, int offset) 1919 { 1920 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1921 pcitag_t brtag = sc->sc_tag; 1922 pcireg_t reg; 1923 1924 /* 1925 * clear cardbus master abort status; it is OK to write without 1926 * reading before because all bits are r/o or w1tc 1927 */ 1928 pci_conf_write(sc->sc_pc, brtag, PCI_CBB_SECSTATUS, 1929 CBB_SECSTATUS_CBMABORT); 1930 reg = pci_conf_read(sc->sc_pc, tag, offset); 1931 /* check cardbus master abort status */ 1932 if (pci_conf_read(sc->sc_pc, brtag, PCI_CBB_SECSTATUS) 1933 & CBB_SECSTATUS_CBMABORT) 1934 return (0xffffffff); 1935 return reg; 1936 } 1937 1938 /* 1939 * pccbb_conf_write 1940 * 1941 * This is the function to write the config space of a CardBus 1942 * card. It works the same as pci_conf_write(9). 1943 */ 1944 static void 1945 pccbb_conf_write(cardbus_chipset_tag_t cc, pcitag_t tag, int reg, pcireg_t val) 1946 { 1947 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1948 1949 pci_conf_write(sc->sc_pc, tag, reg, val); 1950 } 1951 1952 #if 0 1953 STATIC int 1954 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1955 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 1956 int speed, int flags, 1957 bus_space_handle_t * iohp) 1958 #endif 1959 /* 1960 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1961 * bus_addr_t start, bus_size_t size, 1962 * bus_size_t align, 1963 * struct pcmcia_io_handle *pcihp 1964 * 1965 * This function only allocates I/O region for pccard. This function 1966 * never maps the allocated region to pccard I/O area. 1967 * 1968 * XXX: The interface of this function is not very good, I believe. 1969 */ 1970 STATIC int 1971 pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, 1972 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 1973 { 1974 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 1975 bus_addr_t ioaddr; 1976 int flags = 0; 1977 bus_space_tag_t iot; 1978 bus_space_handle_t ioh; 1979 bus_addr_t mask; 1980 #if rbus 1981 rbus_tag_t rb; 1982 #endif 1983 if (align == 0) { 1984 align = size; /* XXX: funny??? */ 1985 } 1986 1987 if (start != 0) { 1988 /* XXX: assume all card decode lower 10 bits by its hardware */ 1989 mask = 0x3ff; 1990 /* enforce to use only masked address */ 1991 start &= mask; 1992 } else { 1993 /* 1994 * calculate mask: 1995 * 1. get the most significant bit of size (call it msb). 1996 * 2. compare msb with the value of size. 1997 * 3. if size is larger, shift msb left once. 1998 * 4. obtain mask value to decrement msb. 1999 */ 2000 bus_size_t size_tmp = size; 2001 int shifts = 0; 2002 2003 mask = 1; 2004 while (size_tmp) { 2005 ++shifts; 2006 size_tmp >>= 1; 2007 } 2008 mask = (1 << shifts); 2009 if (mask < size) { 2010 mask <<= 1; 2011 } 2012 --mask; 2013 } 2014 2015 /* 2016 * Allocate some arbitrary I/O space. 2017 */ 2018 2019 iot = sc->sc_iot; 2020 2021 #if rbus 2022 rb = sc->sc_rbus_iot; 2023 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 2024 return 1; 2025 } 2026 DPRINTF(("pccbb_pcmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2027 (u_long) ioaddr, (u_long) size)); 2028 #else 2029 if (start) { 2030 ioaddr = start; 2031 if (bus_space_map(iot, start, size, 0, &ioh)) { 2032 return 1; 2033 } 2034 DPRINTF(("pccbb_pcmcia_io_alloc map port 0x%lx+0x%lx\n", 2035 (u_long) ioaddr, (u_long) size)); 2036 } else { 2037 flags |= PCMCIA_IO_ALLOCATED; 2038 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 2039 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 2040 size, align, 0, 0, &ioaddr, &ioh)) { 2041 /* No room be able to be get. */ 2042 return 1; 2043 } 2044 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2045 (u_long) ioaddr, (u_long) size)); 2046 } 2047 #endif 2048 2049 pcihp->iot = iot; 2050 pcihp->ioh = ioh; 2051 pcihp->addr = ioaddr; 2052 pcihp->size = size; 2053 pcihp->flags = flags; 2054 2055 return 0; 2056 } 2057 2058 /* 2059 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2060 * struct pcmcia_io_handle *pcihp) 2061 * 2062 * This function only frees I/O region for pccard. 2063 * 2064 * XXX: The interface of this function is not very good, I believe. 2065 */ 2066 void 2067 pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2068 struct pcmcia_io_handle *pcihp) 2069 { 2070 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2071 #if !rbus 2072 bus_space_tag_t iot = pcihp->iot; 2073 #endif 2074 bus_space_handle_t ioh = pcihp->ioh; 2075 bus_size_t size = pcihp->size; 2076 2077 #if rbus 2078 rbus_tag_t rb = sc->sc_rbus_iot; 2079 2080 rbus_space_free(rb, ioh, size, NULL); 2081 #else 2082 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 2083 bus_space_free(iot, ioh, size); 2084 else 2085 bus_space_unmap(iot, ioh, size); 2086 #endif 2087 } 2088 2089 /* 2090 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 2091 * bus_addr_t offset, bus_size_t size, 2092 * struct pcmcia_io_handle *pcihp, 2093 * int *windowp) 2094 * 2095 * This function maps the allocated I/O region to pccard. This function 2096 * never allocates any I/O region for pccard I/O area. I don't 2097 * understand why the original authors of pcmciabus separated alloc and 2098 * map. I believe the two must be unite. 2099 * 2100 * XXX: no wait timing control? 2101 */ 2102 int 2103 pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, bus_addr_t offset, 2104 bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp) 2105 { 2106 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2107 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2108 bus_addr_t ioaddr = pcihp->addr + offset; 2109 int i, win; 2110 #if defined CBB_DEBUG 2111 static const char *width_names[] = { "dynamic", "io8", "io16" }; 2112 #endif 2113 2114 /* Sanity check I/O handle. */ 2115 2116 if (sc->sc_iot != pcihp->iot) { 2117 panic("pccbb_pcmcia_io_map iot is bogus"); 2118 } 2119 2120 /* XXX Sanity check offset/size. */ 2121 2122 win = -1; 2123 for (i = 0; i < PCIC_IO_WINS; i++) { 2124 if ((ph->ioalloc & (1 << i)) == 0) { 2125 win = i; 2126 ph->ioalloc |= (1 << i); 2127 break; 2128 } 2129 } 2130 2131 if (win == -1) { 2132 return 1; 2133 } 2134 2135 *windowp = win; 2136 2137 /* XXX this is pretty gross */ 2138 2139 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2140 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2141 2142 /* XXX wtf is this doing here? */ 2143 2144 #if 0 2145 printf(" port 0x%lx", (u_long) ioaddr); 2146 if (size > 1) { 2147 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2148 } 2149 #endif 2150 2151 ph->io[win].addr = ioaddr; 2152 ph->io[win].size = size; 2153 ph->io[win].width = width; 2154 2155 /* actual dirty register-value changing in the function below. */ 2156 pccbb_pcmcia_do_io_map(sc, win); 2157 2158 return 0; 2159 } 2160 2161 /* 2162 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2163 * 2164 * This function changes register-value to map I/O region for pccard. 2165 */ 2166 static void 2167 pccbb_pcmcia_do_io_map(struct pccbb_softc *sc, int win) 2168 { 2169 static u_int8_t pcic_iowidth[3] = { 2170 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2171 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2172 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2173 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2174 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2175 }; 2176 2177 #define PCIC_SIA_START_LOW 0 2178 #define PCIC_SIA_START_HIGH 1 2179 #define PCIC_SIA_STOP_LOW 2 2180 #define PCIC_SIA_STOP_HIGH 3 2181 2182 int regbase_win = 0x8 + win * 0x04; 2183 u_int8_t ioctl, enable; 2184 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2185 2186 DPRINTF(("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx " 2187 "width %d\n", win, (unsigned long)ph->io[win].addr, 2188 (unsigned long)ph->io[win].size, ph->io[win].width * 8)); 2189 2190 Pcic_write(sc, regbase_win + PCIC_SIA_START_LOW, 2191 ph->io[win].addr & 0xff); 2192 Pcic_write(sc, regbase_win + PCIC_SIA_START_HIGH, 2193 (ph->io[win].addr >> 8) & 0xff); 2194 2195 Pcic_write(sc, regbase_win + PCIC_SIA_STOP_LOW, 2196 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2197 Pcic_write(sc, regbase_win + PCIC_SIA_STOP_HIGH, 2198 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2199 2200 ioctl = Pcic_read(sc, PCIC_IOCTL); 2201 enable = Pcic_read(sc, PCIC_ADDRWIN_ENABLE); 2202 switch (win) { 2203 case 0: 2204 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2205 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2206 PCIC_IOCTL_IO0_DATASIZE_MASK); 2207 ioctl |= pcic_iowidth[ph->io[win].width]; 2208 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2209 break; 2210 case 1: 2211 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2212 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2213 PCIC_IOCTL_IO1_DATASIZE_MASK); 2214 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2215 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2216 break; 2217 } 2218 Pcic_write(sc, PCIC_IOCTL, ioctl); 2219 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, enable); 2220 #if defined(CBB_DEBUG) 2221 { 2222 u_int8_t start_low = 2223 Pcic_read(sc, regbase_win + PCIC_SIA_START_LOW); 2224 u_int8_t start_high = 2225 Pcic_read(sc, regbase_win + PCIC_SIA_START_HIGH); 2226 u_int8_t stop_low = 2227 Pcic_read(sc, regbase_win + PCIC_SIA_STOP_LOW); 2228 u_int8_t stop_high = 2229 Pcic_read(sc, regbase_win + PCIC_SIA_STOP_HIGH); 2230 printf("pccbb_pcmcia_do_io_map start %02x %02x, " 2231 "stop %02x %02x, ioctl %02x enable %02x\n", 2232 start_low, start_high, stop_low, stop_high, ioctl, enable); 2233 } 2234 #endif 2235 } 2236 2237 /* 2238 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2239 * 2240 * This function unmaps I/O region. No return value. 2241 */ 2242 STATIC void 2243 pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t pch, int win) 2244 { 2245 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2246 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2247 int reg; 2248 2249 if (win >= PCIC_IO_WINS || win < 0) { 2250 panic("pccbb_pcmcia_io_unmap: window out of range"); 2251 } 2252 2253 reg = Pcic_read(sc, PCIC_ADDRWIN_ENABLE); 2254 switch (win) { 2255 case 0: 2256 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2257 break; 2258 case 1: 2259 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2260 break; 2261 } 2262 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, reg); 2263 2264 ph->ioalloc &= ~(1 << win); 2265 } 2266 2267 static int 2268 pccbb_pcmcia_wait_ready(struct pccbb_softc *sc) 2269 { 2270 u_int8_t stat; 2271 int i; 2272 2273 /* wait an initial 10ms for quick cards */ 2274 stat = Pcic_read(sc, PCIC_IF_STATUS); 2275 if (stat & PCIC_IF_STATUS_READY) 2276 return (0); 2277 pccbb_pcmcia_delay(sc, 10, "pccwr0"); 2278 for (i = 0; i < 50; i++) { 2279 stat = Pcic_read(sc, PCIC_IF_STATUS); 2280 if (stat & PCIC_IF_STATUS_READY) 2281 return (0); 2282 if ((stat & PCIC_IF_STATUS_CARDDETECT_MASK) != 2283 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2284 return (ENXIO); 2285 /* wait .1s (100ms) each iteration now */ 2286 pccbb_pcmcia_delay(sc, 100, "pccwr1"); 2287 } 2288 2289 printf("pccbb_pcmcia_wait_ready: ready never happened, status=%02x\n", stat); 2290 return (EWOULDBLOCK); 2291 } 2292 2293 /* 2294 * Perform long (msec order) delay. timo is in milliseconds. 2295 */ 2296 static void 2297 pccbb_pcmcia_delay(struct pccbb_softc *sc, int timo, const char *wmesg) 2298 { 2299 #ifdef DIAGNOSTIC 2300 if (timo <= 0) 2301 panic("pccbb_pcmcia_delay: called with timeout %d", timo); 2302 if (!curlwp) 2303 panic("pccbb_pcmcia_delay: called in interrupt context"); 2304 #endif 2305 DPRINTF(("pccbb_pcmcia_delay: \"%s\", sleep %d ms\n", wmesg, timo)); 2306 kpause(wmesg, false, max(mstohz(timo), 1), NULL); 2307 } 2308 2309 /* 2310 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2311 * 2312 * This function enables the card. All information is stored in 2313 * the first argument, pcmcia_chipset_handle_t. 2314 */ 2315 STATIC void 2316 pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2317 { 2318 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2319 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2320 pcireg_t spsr; 2321 int voltage; 2322 int win; 2323 u_int8_t power, intr; 2324 #ifdef DIAGNOSTIC 2325 int reg; 2326 #endif 2327 2328 /* this bit is mostly stolen from pcic_attach_card */ 2329 2330 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2331 2332 /* get card Vcc info */ 2333 spsr = 2334 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2335 CB_SOCKET_STAT); 2336 if (spsr & CB_SOCKET_STAT_5VCARD) { 2337 DPRINTF(("5V card\n")); 2338 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2339 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2340 DPRINTF(("3V card\n")); 2341 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2342 } else { 2343 DPRINTF(("?V card, 0x%x\n", spsr)); /* XXX */ 2344 return; 2345 } 2346 2347 /* disable interrupts; assert RESET */ 2348 intr = Pcic_read(sc, PCIC_INTR); 2349 intr &= PCIC_INTR_ENABLE; 2350 Pcic_write(sc, PCIC_INTR, intr); 2351 2352 /* zero out the address windows */ 2353 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, 0); 2354 2355 /* power down the socket to reset it, clear the card reset pin */ 2356 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2357 2358 /* power off; assert output enable bit */ 2359 power = PCIC_PWRCTL_OE; 2360 Pcic_write(sc, PCIC_PWRCTL, power); 2361 2362 /* power up the socket */ 2363 if (pccbb_power(sc, voltage) == 0) 2364 return; 2365 2366 /* 2367 * Table 4-18 and figure 4-6 of the PC Card specifiction say: 2368 * Vcc Rising Time (Tpr) = 100ms (handled in pccbb_power() above) 2369 * RESET Width (Th (Hi-z RESET)) = 1ms 2370 * RESET Width (Tw (RESET)) = 10us 2371 * 2372 * some machines require some more time to be settled 2373 * for example old toshiba topic bridges! 2374 * (100ms is added here). 2375 */ 2376 pccbb_pcmcia_delay(sc, 200 + 1, "pccen1"); 2377 2378 /* negate RESET */ 2379 intr |= PCIC_INTR_RESET; 2380 Pcic_write(sc, PCIC_INTR, intr); 2381 2382 /* 2383 * RESET Setup Time (Tsu (RESET)) = 20ms 2384 */ 2385 pccbb_pcmcia_delay(sc, 20, "pccen2"); 2386 2387 #ifdef DIAGNOSTIC 2388 reg = Pcic_read(sc, PCIC_IF_STATUS); 2389 if ((reg & PCIC_IF_STATUS_POWERACTIVE) == 0) 2390 printf("pccbb_pcmcia_socket_enable: no power, status=%x\n", reg); 2391 #endif 2392 2393 /* wait for the chip to finish initializing */ 2394 if (pccbb_pcmcia_wait_ready(sc)) { 2395 #ifdef DIAGNOSTIC 2396 printf("pccbb_pcmcia_socket_enable: never became ready\n"); 2397 #endif 2398 /* XXX return a failure status?? */ 2399 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2400 Pcic_write(sc, PCIC_PWRCTL, 0); 2401 return; 2402 } 2403 2404 /* reinstall all the memory and io mappings */ 2405 for (win = 0; win < PCIC_MEM_WINS; ++win) 2406 if (ph->memalloc & (1 << win)) 2407 pccbb_pcmcia_do_mem_map(sc, win); 2408 for (win = 0; win < PCIC_IO_WINS; ++win) 2409 if (ph->ioalloc & (1 << win)) 2410 pccbb_pcmcia_do_io_map(sc, win); 2411 } 2412 2413 /* 2414 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2415 * 2416 * This function disables the card. All information is stored in 2417 * the first argument, pcmcia_chipset_handle_t. 2418 */ 2419 STATIC void 2420 pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t pch) 2421 { 2422 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2423 u_int8_t intr; 2424 2425 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2426 2427 /* disable interrupts; assert RESET */ 2428 intr = Pcic_read(sc, PCIC_INTR); 2429 intr &= PCIC_INTR_ENABLE; 2430 Pcic_write(sc, PCIC_INTR, intr); 2431 2432 /* zero out the address windows */ 2433 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, 0); 2434 2435 /* power down the socket to reset it, clear the card reset pin */ 2436 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2437 2438 /* disable socket: negate output enable bit and power off */ 2439 Pcic_write(sc, PCIC_PWRCTL, 0); 2440 2441 /* 2442 * Vcc Falling Time (Tpf) = 300ms 2443 */ 2444 pccbb_pcmcia_delay(sc, 300, "pccwr1"); 2445 } 2446 2447 STATIC void 2448 pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t pch, int type) 2449 { 2450 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2451 u_int8_t intr; 2452 2453 /* set the card type */ 2454 2455 intr = Pcic_read(sc, PCIC_INTR); 2456 intr &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_CARDTYPE_MASK); 2457 if (type == PCMCIA_IFTYPE_IO) 2458 intr |= PCIC_INTR_CARDTYPE_IO; 2459 else 2460 intr |= PCIC_INTR_CARDTYPE_MEM; 2461 Pcic_write(sc, PCIC_INTR, intr); 2462 2463 DPRINTF(("%s: pccbb_pcmcia_socket_settype type %s %02x\n", 2464 device_xname(sc->sc_dev), 2465 ((type == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2466 } 2467 2468 /* 2469 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2470 * 2471 * This function detects whether a card is in the slot or not. 2472 * If a card is inserted, return 1. Otherwise, return 0. 2473 */ 2474 STATIC int 2475 pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch) 2476 { 2477 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2478 2479 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2480 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2481 } 2482 2483 #if 0 2484 STATIC int 2485 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2486 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2487 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2488 #endif 2489 /* 2490 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2491 * bus_size_t size, 2492 * struct pcmcia_mem_handle *pcmhp) 2493 * 2494 * This function only allocates memory region for pccard. This 2495 * function never maps the allocated region to pccard memory area. 2496 * 2497 * XXX: Why the argument of start address is not in? 2498 */ 2499 STATIC int 2500 pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 2501 struct pcmcia_mem_handle *pcmhp) 2502 { 2503 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2504 bus_space_handle_t memh; 2505 bus_addr_t addr; 2506 bus_size_t sizepg; 2507 #if rbus 2508 rbus_tag_t rb; 2509 #endif 2510 2511 /* Check that the card is still there. */ 2512 if ((Pcic_read(sc, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2513 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2514 return 1; 2515 2516 /* out of sc->memh, allocate as many pages as necessary */ 2517 2518 /* convert size to PCIC pages */ 2519 /* 2520 * This is not enough; when the requested region is on the page 2521 * boundaries, this may calculate wrong result. 2522 */ 2523 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2524 #if 0 2525 if (sizepg > PCIC_MAX_MEM_PAGES) { 2526 return 1; 2527 } 2528 #endif 2529 2530 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2531 return 1; 2532 } 2533 2534 addr = 0; /* XXX gcc -Wuninitialized */ 2535 2536 #if rbus 2537 rb = sc->sc_rbus_memt; 2538 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2539 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2540 &addr, &memh)) { 2541 return 1; 2542 } 2543 #else 2544 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2545 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2546 0, /* boundary */ 2547 0, /* flags */ 2548 &addr, &memh)) { 2549 return 1; 2550 } 2551 #endif 2552 2553 DPRINTF(("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, " 2554 "realsize 0x%lx\n", (unsigned long)addr, (unsigned long)size, 2555 (unsigned long)sizepg * PCIC_MEM_PAGESIZE)); 2556 2557 pcmhp->memt = sc->sc_memt; 2558 pcmhp->memh = memh; 2559 pcmhp->addr = addr; 2560 pcmhp->size = size; 2561 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2562 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2563 pcmhp->mhandle = 0; 2564 /* No offset??? Funny. */ 2565 2566 return 0; 2567 } 2568 2569 /* 2570 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2571 * struct pcmcia_mem_handle *pcmhp) 2572 * 2573 * This function release the memory space allocated by the function 2574 * pccbb_pcmcia_mem_alloc(). 2575 */ 2576 STATIC void 2577 pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2578 struct pcmcia_mem_handle *pcmhp) 2579 { 2580 #if rbus 2581 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2582 2583 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2584 #else 2585 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2586 #endif 2587 } 2588 2589 /* 2590 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2591 * 2592 * This function release the memory space allocated by the function 2593 * pccbb_pcmcia_mem_alloc(). 2594 */ 2595 STATIC void 2596 pccbb_pcmcia_do_mem_map(struct pccbb_softc *sc, int win) 2597 { 2598 int regbase_win; 2599 bus_addr_t phys_addr; 2600 bus_addr_t phys_end; 2601 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2602 2603 #define PCIC_SMM_START_LOW 0 2604 #define PCIC_SMM_START_HIGH 1 2605 #define PCIC_SMM_STOP_LOW 2 2606 #define PCIC_SMM_STOP_HIGH 3 2607 #define PCIC_CMA_LOW 4 2608 #define PCIC_CMA_HIGH 5 2609 2610 u_int8_t start_low, start_high = 0; 2611 u_int8_t stop_low, stop_high; 2612 u_int8_t off_low, off_high; 2613 u_int8_t mem_window; 2614 int reg; 2615 2616 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2617 int mem8 = 2618 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2619 || (kind == PCMCIA_MEM_ATTR); 2620 2621 regbase_win = 0x10 + win * 0x08; 2622 2623 phys_addr = ph->mem[win].addr; 2624 phys_end = phys_addr + ph->mem[win].size; 2625 2626 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2627 (unsigned long)phys_addr, (unsigned long)phys_end, 2628 (unsigned long)ph->mem[win].offset)); 2629 2630 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2631 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2632 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2633 2634 /* bit 19:12 */ 2635 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2636 /* bit 23:20 and bit 7 on */ 2637 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2638 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2639 /* bit 31:24, for 32-bit address */ 2640 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2641 2642 Pcic_write(sc, regbase_win + PCIC_SMM_START_LOW, start_low); 2643 Pcic_write(sc, regbase_win + PCIC_SMM_START_HIGH, start_high); 2644 2645 if (sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2646 Pcic_write(sc, 0x40 + win, mem_window); 2647 } 2648 2649 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2650 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2651 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2652 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2653 2654 Pcic_write(sc, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2655 Pcic_write(sc, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2656 2657 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2658 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2659 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2660 | ((kind == PCMCIA_MEM_ATTR) ? 2661 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2662 2663 Pcic_write(sc, regbase_win + PCIC_CMA_LOW, off_low); 2664 Pcic_write(sc, regbase_win + PCIC_CMA_HIGH, off_high); 2665 2666 reg = Pcic_read(sc, PCIC_ADDRWIN_ENABLE); 2667 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2668 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, reg); 2669 2670 #if defined(CBB_DEBUG) 2671 { 2672 int r1, r2, r3, r4, r5, r6, r7 = 0; 2673 2674 r1 = Pcic_read(sc, regbase_win + PCIC_SMM_START_LOW); 2675 r2 = Pcic_read(sc, regbase_win + PCIC_SMM_START_HIGH); 2676 r3 = Pcic_read(sc, regbase_win + PCIC_SMM_STOP_LOW); 2677 r4 = Pcic_read(sc, regbase_win + PCIC_SMM_STOP_HIGH); 2678 r5 = Pcic_read(sc, regbase_win + PCIC_CMA_LOW); 2679 r6 = Pcic_read(sc, regbase_win + PCIC_CMA_HIGH); 2680 if (sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2681 r7 = Pcic_read(sc, 0x40 + win); 2682 } 2683 2684 printf("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2685 "%02x%02x", win, r1, r2, r3, r4, r5, r6); 2686 if (sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2687 printf(" %02x", r7); 2688 } 2689 printf("\n"); 2690 } 2691 #endif 2692 } 2693 2694 /* 2695 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2696 * bus_addr_t card_addr, bus_size_t size, 2697 * struct pcmcia_mem_handle *pcmhp, 2698 * bus_addr_t *offsetp, int *windowp) 2699 * 2700 * This function maps memory space allocated by the function 2701 * pccbb_pcmcia_mem_alloc(). 2702 */ 2703 STATIC int 2704 pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2705 bus_addr_t card_addr, bus_size_t size, struct pcmcia_mem_handle *pcmhp, 2706 bus_size_t *offsetp, int *windowp) 2707 { 2708 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2709 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2710 bus_addr_t busaddr; 2711 long card_offset; 2712 int win; 2713 2714 /* Check that the card is still there. */ 2715 if ((Pcic_read(sc, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2716 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2717 return 1; 2718 2719 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2720 if ((ph->memalloc & (1 << win)) == 0) { 2721 ph->memalloc |= (1 << win); 2722 break; 2723 } 2724 } 2725 2726 if (win == PCIC_MEM_WINS) { 2727 return 1; 2728 } 2729 2730 *windowp = win; 2731 2732 /* XXX this is pretty gross */ 2733 2734 if (sc->sc_memt != pcmhp->memt) { 2735 panic("pccbb_pcmcia_mem_map memt is bogus"); 2736 } 2737 2738 busaddr = pcmhp->addr; 2739 2740 /* 2741 * compute the address offset to the pcmcia address space for the 2742 * pcic. this is intentionally signed. The masks and shifts below 2743 * will cause TRT to happen in the pcic registers. Deal with making 2744 * sure the address is aligned, and return the alignment offset. 2745 */ 2746 2747 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2748 card_addr -= *offsetp; 2749 2750 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2751 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2752 (u_long) card_addr)); 2753 2754 /* 2755 * include the offset in the size, and decrement size by one, since 2756 * the hw wants start/stop 2757 */ 2758 size += *offsetp - 1; 2759 2760 card_offset = (((long)card_addr) - ((long)busaddr)); 2761 2762 ph->mem[win].addr = busaddr; 2763 ph->mem[win].size = size; 2764 ph->mem[win].offset = card_offset; 2765 ph->mem[win].kind = kind; 2766 2767 pccbb_pcmcia_do_mem_map(sc, win); 2768 2769 return 0; 2770 } 2771 2772 /* 2773 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2774 * int window) 2775 * 2776 * This function unmaps memory space which mapped by the function 2777 * pccbb_pcmcia_mem_map(). 2778 */ 2779 STATIC void 2780 pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, int window) 2781 { 2782 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2783 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2784 int reg; 2785 2786 if (window >= PCIC_MEM_WINS) { 2787 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2788 } 2789 2790 reg = Pcic_read(sc, PCIC_ADDRWIN_ENABLE); 2791 reg &= ~(1 << window); 2792 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, reg); 2793 2794 ph->memalloc &= ~(1 << window); 2795 } 2796 2797 /* 2798 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2799 * struct pcmcia_function *pf, 2800 * int ipl, 2801 * int (*func)(void *), 2802 * void *arg); 2803 * 2804 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2805 */ 2806 STATIC void * 2807 pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2808 struct pcmcia_function *pf, int ipl, int (*func)(void *), void *arg) 2809 { 2810 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2811 2812 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2813 /* what should I do? */ 2814 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2815 DPRINTF(("%s does not provide edge nor pulse " 2816 "interrupt\n", device_xname(sc->sc_dev))); 2817 return NULL; 2818 } 2819 /* 2820 * XXX Noooooo! The interrupt flag must set properly!! 2821 * dumb pcmcia driver!! 2822 */ 2823 } 2824 2825 return pccbb_intr_establish(sc, 0, ipl, func, arg); 2826 } 2827 2828 /* 2829 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2830 * void *ih) 2831 * 2832 * This function disables PC-Card interrupt. 2833 */ 2834 STATIC void 2835 pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 2836 { 2837 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2838 2839 pccbb_intr_disestablish(sc, ih); 2840 } 2841 2842 #if rbus 2843 /* 2844 * static int 2845 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2846 * bus_addr_t addr, bus_size_t size, 2847 * bus_addr_t mask, bus_size_t align, 2848 * int flags, bus_addr_t *addrp; 2849 * bus_space_handle_t *bshp) 2850 * 2851 * This function allocates a portion of memory or io space for 2852 * clients. This function is called from CardBus card drivers. 2853 */ 2854 static int 2855 pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2856 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 2857 int flags, bus_addr_t *addrp, bus_space_handle_t *bshp) 2858 { 2859 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2860 2861 DPRINTF(("pccbb_rbus_cb_space_alloc: addr 0x%lx, size 0x%lx, " 2862 "mask 0x%lx, align 0x%lx\n", (unsigned long)addr, 2863 (unsigned long)size, (unsigned long)mask, (unsigned long)align)); 2864 2865 if (align == 0) { 2866 align = size; 2867 } 2868 2869 if (rb->rb_bt == sc->sc_memt) { 2870 if (align < 16) { 2871 return 1; 2872 } 2873 /* 2874 * XXX: align more than 0x1000 to avoid overwrapping 2875 * memory windows for two or more devices. 0x1000 2876 * means memory window's granularity. 2877 * 2878 * Two or more devices should be able to share same 2879 * memory window region. However, overrapping memory 2880 * window is not good because some devices, such as 2881 * 3Com 3C575[BC], have a broken address decoder and 2882 * intrude other's memory region. 2883 */ 2884 if (align < 0x1000) { 2885 align = 0x1000; 2886 } 2887 } else if (rb->rb_bt == sc->sc_iot) { 2888 if (align < 4) { 2889 return 1; 2890 } 2891 /* XXX: hack for avoiding ISA image */ 2892 if (mask < 0x0100) { 2893 mask = 0x3ff; 2894 addr = 0x300; 2895 } 2896 2897 } else { 2898 DPRINTF(("pccbb_rbus_cb_space_alloc: Bus space tag 0x%lx is " 2899 "NOT used. io: 0x%lx, mem: 0x%lx\n", 2900 (unsigned long)rb->rb_bt, (unsigned long)sc->sc_iot, 2901 (unsigned long)sc->sc_memt)); 2902 return 1; 2903 /* XXX: panic here? */ 2904 } 2905 2906 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 2907 aprint_normal_dev(sc->sc_dev, "<rbus> no bus space\n"); 2908 return 1; 2909 } 2910 2911 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 2912 2913 return 0; 2914 } 2915 2916 /* 2917 * static int 2918 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 2919 * bus_space_handle_t *bshp, bus_size_t size); 2920 * 2921 * This function is called from CardBus card drivers. 2922 */ 2923 static int 2924 pccbb_rbus_cb_space_free(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2925 bus_space_handle_t bsh, bus_size_t size) 2926 { 2927 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2928 bus_space_tag_t bt = rb->rb_bt; 2929 2930 pccbb_close_win(sc, bt, bsh, size); 2931 2932 if (bt == sc->sc_memt) { 2933 } else if (bt == sc->sc_iot) { 2934 } else { 2935 return 1; 2936 /* XXX: panic here? */ 2937 } 2938 2939 return rbus_space_free(rb, bsh, size, NULL); 2940 } 2941 #endif /* rbus */ 2942 2943 #if rbus 2944 2945 static int 2946 pccbb_open_win(struct pccbb_softc *sc, bus_space_tag_t bst, bus_addr_t addr, 2947 bus_size_t size, bus_space_handle_t bsh, int flags) 2948 { 2949 struct pccbb_win_chain_head *head; 2950 bus_addr_t align; 2951 2952 head = &sc->sc_iowindow; 2953 align = 0x04; 2954 if (sc->sc_memt == bst) { 2955 head = &sc->sc_memwindow; 2956 align = 0x1000; 2957 DPRINTF(("using memory window, 0x%lx 0x%lx 0x%lx\n\n", 2958 (unsigned long)sc->sc_iot, (unsigned long)sc->sc_memt, 2959 (unsigned long)bst)); 2960 } 2961 2962 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 2963 aprint_error_dev(sc->sc_dev, 2964 "pccbb_open_win: %s winlist insert failed\n", 2965 (head == &sc->sc_memwindow) ? "mem" : "io"); 2966 } 2967 pccbb_winset(align, sc, bst); 2968 2969 return 0; 2970 } 2971 2972 static int 2973 pccbb_close_win(struct pccbb_softc *sc, bus_space_tag_t bst, 2974 bus_space_handle_t bsh, bus_size_t size) 2975 { 2976 struct pccbb_win_chain_head *head; 2977 bus_addr_t align; 2978 2979 head = &sc->sc_iowindow; 2980 align = 0x04; 2981 if (sc->sc_memt == bst) { 2982 head = &sc->sc_memwindow; 2983 align = 0x1000; 2984 } 2985 2986 if (pccbb_winlist_delete(head, bsh, size)) { 2987 aprint_error_dev(sc->sc_dev, 2988 "pccbb_close_win: %s winlist delete failed\n", 2989 (head == &sc->sc_memwindow) ? "mem" : "io"); 2990 } 2991 pccbb_winset(align, sc, bst); 2992 2993 return 0; 2994 } 2995 2996 static int 2997 pccbb_winlist_insert(struct pccbb_win_chain_head *head, bus_addr_t start, 2998 bus_size_t size, bus_space_handle_t bsh, int flags) 2999 { 3000 struct pccbb_win_chain *chainp, *elem; 3001 3002 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 3003 M_NOWAIT)) == NULL) 3004 return (1); /* fail */ 3005 3006 elem->wc_start = start; 3007 elem->wc_end = start + (size - 1); 3008 elem->wc_handle = bsh; 3009 elem->wc_flags = flags; 3010 3011 TAILQ_FOREACH(chainp, head, wc_list) { 3012 if (chainp->wc_end >= start) 3013 break; 3014 } 3015 if (chainp != NULL) 3016 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 3017 else 3018 TAILQ_INSERT_TAIL(head, elem, wc_list); 3019 return (0); 3020 } 3021 3022 static int 3023 pccbb_winlist_delete(struct pccbb_win_chain_head *head, bus_space_handle_t bsh, 3024 bus_size_t size) 3025 { 3026 struct pccbb_win_chain *chainp; 3027 3028 TAILQ_FOREACH(chainp, head, wc_list) { 3029 if (memcmp(&chainp->wc_handle, &bsh, sizeof(bsh)) == 0) 3030 break; 3031 } 3032 if (chainp == NULL) 3033 return 1; /* fail: no candidate to remove */ 3034 3035 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 3036 printf("pccbb_winlist_delete: window 0x%lx size " 3037 "inconsistent: 0x%lx, 0x%lx\n", 3038 (unsigned long)chainp->wc_start, 3039 (unsigned long)(chainp->wc_end - chainp->wc_start), 3040 (unsigned long)(size - 1)); 3041 return 1; 3042 } 3043 3044 TAILQ_REMOVE(head, chainp, wc_list); 3045 free(chainp, M_DEVBUF); 3046 3047 return 0; 3048 } 3049 3050 static void 3051 pccbb_winset(bus_addr_t align, struct pccbb_softc *sc, bus_space_tag_t bst) 3052 { 3053 pci_chipset_tag_t pc; 3054 pcitag_t tag; 3055 bus_addr_t mask = ~(align - 1); 3056 struct { 3057 pcireg_t win_start; 3058 pcireg_t win_limit; 3059 int win_flags; 3060 } win[2]; 3061 struct pccbb_win_chain *chainp; 3062 int offs; 3063 3064 win[0].win_start = win[1].win_start = 0xffffffff; 3065 win[0].win_limit = win[1].win_limit = 0; 3066 win[0].win_flags = win[1].win_flags = 0; 3067 3068 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3069 offs = PCI_CB_IOBASE0; 3070 if (sc->sc_memt == bst) { 3071 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3072 offs = PCI_CB_MEMBASE0; 3073 } 3074 3075 if (chainp != NULL) { 3076 win[0].win_start = chainp->wc_start & mask; 3077 win[0].win_limit = chainp->wc_end & mask; 3078 win[0].win_flags = chainp->wc_flags; 3079 chainp = TAILQ_NEXT(chainp, wc_list); 3080 } 3081 3082 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3083 if (win[1].win_start == 0xffffffff) { 3084 /* window 1 is not used */ 3085 if ((win[0].win_flags == chainp->wc_flags) && 3086 (win[0].win_limit + align >= 3087 (chainp->wc_start & mask))) { 3088 /* concatenate */ 3089 win[0].win_limit = chainp->wc_end & mask; 3090 } else { 3091 /* make new window */ 3092 win[1].win_start = chainp->wc_start & mask; 3093 win[1].win_limit = chainp->wc_end & mask; 3094 win[1].win_flags = chainp->wc_flags; 3095 } 3096 continue; 3097 } 3098 3099 /* Both windows are engaged. */ 3100 if (win[0].win_flags == win[1].win_flags) { 3101 /* same flags */ 3102 if (win[0].win_flags == chainp->wc_flags) { 3103 if (win[1].win_start - (win[0].win_limit + 3104 align) < 3105 (chainp->wc_start & mask) - 3106 ((chainp->wc_end & mask) + align)) { 3107 /* 3108 * merge window 0 and 1, and set win1 3109 * to chainp 3110 */ 3111 win[0].win_limit = win[1].win_limit; 3112 win[1].win_start = 3113 chainp->wc_start & mask; 3114 win[1].win_limit = 3115 chainp->wc_end & mask; 3116 } else { 3117 win[1].win_limit = 3118 chainp->wc_end & mask; 3119 } 3120 } else { 3121 /* different flags */ 3122 3123 /* concatenate win0 and win1 */ 3124 win[0].win_limit = win[1].win_limit; 3125 /* allocate win[1] to new space */ 3126 win[1].win_start = chainp->wc_start & mask; 3127 win[1].win_limit = chainp->wc_end & mask; 3128 win[1].win_flags = chainp->wc_flags; 3129 } 3130 } else { 3131 /* the flags of win[0] and win[1] is different */ 3132 if (win[0].win_flags == chainp->wc_flags) { 3133 win[0].win_limit = chainp->wc_end & mask; 3134 /* 3135 * XXX this creates overlapping windows, so 3136 * what should the poor bridge do if one is 3137 * cachable, and the other is not? 3138 */ 3139 aprint_error_dev(sc->sc_dev, 3140 "overlapping windows\n"); 3141 } else { 3142 win[1].win_limit = chainp->wc_end & mask; 3143 } 3144 } 3145 } 3146 3147 pc = sc->sc_pc; 3148 tag = sc->sc_tag; 3149 pci_conf_write(pc, tag, offs, win[0].win_start); 3150 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3151 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3152 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3153 DPRINTF(("--pccbb_winset: win0 [0x%lx, 0x%lx), win1 [0x%lx, 0x%lx)\n", 3154 (unsigned long)pci_conf_read(pc, tag, offs), 3155 (unsigned long)pci_conf_read(pc, tag, offs + 4) + align, 3156 (unsigned long)pci_conf_read(pc, tag, offs + 8), 3157 (unsigned long)pci_conf_read(pc, tag, offs + 12) + align)); 3158 3159 if (bst == sc->sc_memt) { 3160 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BRIDGE_CONTROL_REG); 3161 3162 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 3163 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 3164 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3165 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 3166 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3167 pci_conf_write(pc, tag, PCI_BRIDGE_CONTROL_REG, bcr); 3168 } 3169 } 3170 3171 #endif /* rbus */ 3172 3173 static bool 3174 pccbb_suspend(device_t dv, const pmf_qual_t *qual) 3175 { 3176 struct pccbb_softc *sc = device_private(dv); 3177 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3178 bus_space_handle_t base_memh = sc->sc_base_memh; 3179 pcireg_t reg; 3180 3181 if (sc->sc_pil_intr_enable) 3182 (void)pccbbintr_function(sc); 3183 sc->sc_pil_intr_enable = 0; 3184 3185 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3186 /* Disable interrupts. */ 3187 reg &= ~(CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER); 3188 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3189 /* XXX joerg Disable power to the socket? */ 3190 3191 /* XXX flush PCI write */ 3192 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3193 3194 /* reset interrupt */ 3195 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, 3196 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT)); 3197 /* XXX flush PCI write */ 3198 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3199 3200 if (sc->sc_ih != NULL) { 3201 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 3202 sc->sc_ih = NULL; 3203 } 3204 3205 return true; 3206 } 3207 3208 static bool 3209 pccbb_resume(device_t dv, const pmf_qual_t *qual) 3210 { 3211 struct pccbb_softc *sc = device_private(dv); 3212 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3213 bus_space_handle_t base_memh = sc->sc_base_memh; 3214 pcireg_t reg; 3215 3216 pccbb_chipinit(sc); 3217 pccbb_intrinit(sc); 3218 /* setup memory and io space window for CB */ 3219 pccbb_winset(0x1000, sc, sc->sc_memt); 3220 pccbb_winset(0x04, sc, sc->sc_iot); 3221 3222 /* CSC Interrupt: Card detect interrupt on */ 3223 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3224 /* Card detect intr is turned on. */ 3225 reg |= CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; 3226 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3227 /* reset interrupt */ 3228 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3229 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3230 3231 /* 3232 * check for card insertion or removal during suspend period. 3233 * XXX: the code can't cope with card swap (remove then 3234 * insert). how can we detect such situation? 3235 */ 3236 (void)pccbbintr(sc); 3237 3238 sc->sc_pil_intr_enable = 1; 3239 3240 return true; 3241 } 3242
Indexes created Wed Oct 15 16:09:53 GMT 2025