pccbb.c revision 1.17
1 /* $NetBSD: pccbb.c,v 1.17 2000/01/24 15:51:59 joda Exp $ */ 2 3 /* 4 * Copyright (c) 1998 and 1999 HAYAKAWA Koichi. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by HAYAKAWA Koichi. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 #define CBB_DEBUG 34 #define SHOW_REGS 35 #define PCCBB_PCMCIA_POLL 36 */ 37 /* #define CBB_DEBUG */ 38 39 /* 40 #define CB_PCMCIA_POLL 41 #define CB_PCMCIA_POLL_ONLY 42 #define LEVEL2 43 */ 44 45 #include <sys/types.h> 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/kernel.h> 49 #include <sys/errno.h> 50 #include <sys/ioctl.h> 51 #include <sys/syslog.h> 52 #include <sys/device.h> 53 #include <sys/malloc.h> 54 55 #include <machine/intr.h> 56 #include <machine/bus.h> 57 58 #include <dev/pci/pcivar.h> 59 #include <dev/pci/pcireg.h> 60 #include <dev/pci/pcidevs.h> 61 62 #include <dev/pci/pccbbreg.h> 63 64 #include <dev/cardbus/cardslotvar.h> 65 66 #include <dev/cardbus/cardbusvar.h> 67 68 #include <dev/pcmcia/pcmciareg.h> 69 #include <dev/pcmcia/pcmciavar.h> 70 71 #include <dev/ic/i82365reg.h> 72 #include <dev/ic/i82365var.h> 73 #include <dev/pci/pccbbvar.h> 74 75 #include "locators.h" 76 77 78 #ifndef __NetBSD_Version__ 79 struct cfdriver cbb_cd = { 80 NULL, "cbb", DV_DULL 81 }; 82 #endif 83 84 #if defined CBB_DEBUG 85 #define DPRINTF(x) printf x 86 #define STATIC 87 #else 88 #define DPRINTF(x) 89 #define STATIC static 90 #endif 91 92 93 #ifdef __BROKEN_INDIRECT_CONFIG 94 int pcicbbmatch __P((struct device *, void *, void *)); 95 #else 96 int pcicbbmatch __P((struct device *, struct cfdata *, void *)); 97 #endif 98 void pccbbattach __P((struct device *, struct device *, void *)); 99 int pccbbintr __P((void *)); 100 static void pci113x_insert __P((void *)); 101 102 static int pccbb_detect_card __P((struct pccbb_softc *)); 103 104 static void pccbb_pcmcia_write __P((struct pcic_handle *, int, u_int8_t)); 105 static u_int8_t pccbb_pcmcia_read __P((struct pcic_handle *, int)); 106 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 107 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 108 109 110 STATIC int cb_reset __P((struct pccbb_softc *)); 111 STATIC int cb_detect_voltage __P((struct pccbb_softc *)); 112 STATIC int cbbprint __P((void *, const char *)); 113 114 static int cb_chipset __P((u_int32_t, char const **, int *)); 115 STATIC void pccbb_pcmcia_attach_setup __P((struct pccbb_softc *, struct pcmciabus_attach_args *)); 116 #if 0 117 STATIC void pccbb_pcmcia_attach_card __P((struct pcic_handle *)); 118 STATIC void pccbb_pcmcia_detach_card __P((struct pcic_handle *, int)); 119 STATIC void pccbb_pcmcia_deactivate_card __P((struct pcic_handle *)); 120 #endif 121 122 STATIC int pccbb_ctrl __P((cardbus_chipset_tag_t, int)); 123 STATIC int pccbb_power __P((cardbus_chipset_tag_t, int)); 124 STATIC int pccbb_cardenable __P((struct pccbb_softc *sc, int function)); 125 #if !rbus 126 static int pccbb_io_open __P((cardbus_chipset_tag_t, int, u_int32_t, u_int32_t)); 127 static int pccbb_io_close __P((cardbus_chipset_tag_t, int)); 128 static int pccbb_mem_open __P((cardbus_chipset_tag_t, int, u_int32_t, u_int32_t)); 129 static int pccbb_mem_close __P((cardbus_chipset_tag_t, int)); 130 #endif /* !rbus */ 131 static void *pccbb_intr_establish __P((cardbus_chipset_tag_t, int irq, int level, int (* ih)(void *), void *sc)); 132 static void pccbb_intr_disestablish __P((cardbus_chipset_tag_t ct, void *ih)); 133 134 static cardbustag_t pccbb_make_tag __P((cardbus_chipset_tag_t, int, int, int)); 135 static void pccbb_free_tag __P((cardbus_chipset_tag_t, cardbustag_t)); 136 static cardbusreg_t pccbb_conf_read __P((cardbus_chipset_tag_t, cardbustag_t, int)); 137 static void pccbb_conf_write __P((cardbus_chipset_tag_t, cardbustag_t, int, cardbusreg_t)); 138 static void pccbb_chipinit __P((struct pccbb_softc *)); 139 140 141 STATIC int pccbb_pcmcia_mem_alloc __P((pcmcia_chipset_handle_t, bus_size_t, 142 struct pcmcia_mem_handle *)); 143 STATIC void pccbb_pcmcia_mem_free __P((pcmcia_chipset_handle_t, 144 struct pcmcia_mem_handle *)); 145 STATIC int pccbb_pcmcia_mem_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 146 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *)); 147 STATIC void pccbb_pcmcia_mem_unmap __P((pcmcia_chipset_handle_t, int)); 148 STATIC int pccbb_pcmcia_io_alloc __P((pcmcia_chipset_handle_t, bus_addr_t, 149 bus_size_t, bus_size_t, struct pcmcia_io_handle *)); 150 STATIC void pccbb_pcmcia_io_free __P((pcmcia_chipset_handle_t, 151 struct pcmcia_io_handle *)); 152 STATIC int pccbb_pcmcia_io_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 153 bus_size_t, struct pcmcia_io_handle *, int *)); 154 STATIC void pccbb_pcmcia_io_unmap __P((pcmcia_chipset_handle_t, int)); 155 STATIC void *pccbb_pcmcia_intr_establish __P((pcmcia_chipset_handle_t, 156 struct pcmcia_function *, int, int (*) (void *), void *)); 157 STATIC void pccbb_pcmcia_intr_disestablish __P((pcmcia_chipset_handle_t, void *)); 158 STATIC void pccbb_pcmcia_socket_enable __P((pcmcia_chipset_handle_t)); 159 STATIC void pccbb_pcmcia_socket_disable __P((pcmcia_chipset_handle_t)); 160 STATIC int pccbb_pcmcia_card_detect __P((pcmcia_chipset_handle_t pch)); 161 162 static void pccbb_pcmcia_do_io_map __P((struct pcic_handle *, int)); 163 static void pccbb_pcmcia_wait_ready __P((struct pcic_handle *)); 164 static void pccbb_pcmcia_do_mem_map __P((struct pcic_handle *, int)); 165 166 /* bus-space allocation and disallocation functions */ 167 #if rbus 168 169 static int pccbb_rbus_cb_space_alloc __P((cardbus_chipset_tag_t, rbus_tag_t, 170 bus_addr_t addr, bus_size_t size, 171 bus_addr_t mask, bus_size_t align, 172 int flags, bus_addr_t *addrp, 173 bus_space_handle_t *bshp)); 174 static int pccbb_rbus_cb_space_free __P((cardbus_chipset_tag_t, rbus_tag_t, 175 bus_space_handle_t, bus_size_t)); 176 177 #endif /* rbus */ 178 179 #if rbus 180 181 static int pccbb_open_win __P((struct pccbb_softc *, bus_space_tag_t, bus_addr_t, bus_size_t, bus_space_handle_t, int flags)); 182 static int pccbb_close_win __P((struct pccbb_softc *, bus_space_tag_t, bus_space_handle_t, bus_size_t)); 183 static int pccbb_winlist_insert __P((struct pccbb_win_chain **, bus_addr_t, 184 bus_size_t, bus_space_handle_t, int)); 185 static int pccbb_winlist_delete __P((struct pccbb_win_chain **, 186 bus_space_handle_t, bus_size_t)); 187 static void pccbb_winset __P((bus_addr_t align, struct pccbb_softc *, 188 bus_space_tag_t)); 189 void pccbb_winlist_show(struct pccbb_win_chain *); 190 191 #endif /* rbus */ 192 193 /* for config_defer */ 194 static void pccbb_pci_callback __P((struct device *)); 195 196 197 #if defined SHOW_REGS 198 static void cb_show_regs __P((pci_chipset_tag_t pc, pcitag_t tag, bus_space_tag_t memt, bus_space_handle_t memh)); 199 #endif 200 201 202 203 struct cfattach cbb_pci_ca = { 204 sizeof(struct pccbb_softc), pcicbbmatch, pccbbattach 205 }; 206 207 208 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 209 pccbb_pcmcia_mem_alloc, 210 pccbb_pcmcia_mem_free, 211 pccbb_pcmcia_mem_map, 212 pccbb_pcmcia_mem_unmap, 213 pccbb_pcmcia_io_alloc, 214 pccbb_pcmcia_io_free, 215 pccbb_pcmcia_io_map, 216 pccbb_pcmcia_io_unmap, 217 pccbb_pcmcia_intr_establish, 218 pccbb_pcmcia_intr_disestablish, 219 pccbb_pcmcia_socket_enable, 220 pccbb_pcmcia_socket_disable, 221 pccbb_pcmcia_card_detect 222 }; 223 224 #if rbus 225 static struct cardbus_functions pccbb_funcs = { 226 pccbb_rbus_cb_space_alloc, 227 pccbb_rbus_cb_space_free, 228 pccbb_intr_establish, 229 pccbb_intr_disestablish, 230 pccbb_ctrl, 231 pccbb_power, 232 pccbb_make_tag, 233 pccbb_free_tag, 234 pccbb_conf_read, 235 pccbb_conf_write, 236 }; 237 #else 238 static struct cardbus_functions pccbb_funcs = { 239 pccbb_ctrl, 240 pccbb_power, 241 pccbb_mem_open, 242 pccbb_mem_close, 243 pccbb_io_open, 244 pccbb_io_close, 245 pccbb_intr_establish, 246 pccbb_intr_disestablish, 247 pccbb_make_tag, 248 pccbb_conf_read, 249 pccbb_conf_write, 250 }; 251 #endif 252 253 254 255 256 int 257 pcicbbmatch(parent, match, aux) 258 struct device *parent; 259 #ifdef __BROKEN_INDIRECT_CONFIG 260 void *match; 261 #else 262 struct cfdata *match; 263 #endif 264 void *aux; 265 { 266 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 267 268 if(PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 269 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 270 PCI_INTERFACE(pa->pa_class) == 0) { 271 return 1; 272 } 273 274 return 0; 275 } 276 277 278 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 279 | ((prod) << PCI_PRODUCT_SHIFT)) 280 281 282 struct yenta_chipinfo { 283 pcireg_t yc_id; /* vendor tag | product tag */ 284 const char *yc_name; 285 int yc_chiptype; 286 int yc_flags; 287 } yc_chipsets[] = { 288 /* Texas Instruments chips */ 289 {MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), "TI1130", CB_TI113X, 290 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 291 {MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), "TI1131", CB_TI113X, 292 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 293 294 {MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), "TI1250", CB_TI12XX, 295 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 296 {MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), "TI1220", CB_TI12XX, 297 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 298 {MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), "TI1221", CB_TI12XX, 299 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 300 {MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), "TI1225", CB_TI12XX, 301 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 302 {MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), "TI1251", CB_TI12XX, 303 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 304 {MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), "TI1251B", CB_TI12XX, 305 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 306 {MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), "TI1211", CB_TI12XX, 307 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 308 {MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), "TI1420", CB_TI12XX, 309 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 310 {MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), "TI1450", CB_TI12XX, 311 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 312 313 /* Ricoh chips */ 314 {MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), "Rx5C475", 315 CB_RX5C47X, PCCBB_PCMCIA_MEM_32}, 316 {MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), "RL5C476", 317 CB_RX5C47X, PCCBB_PCMCIA_MEM_32}, 318 {MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), "Rx5C477", 319 CB_RX5C47X, PCCBB_PCMCIA_MEM_32}, 320 {MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), "Rx5C478", 321 CB_RX5C47X, PCCBB_PCMCIA_MEM_32}, 322 323 {MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), "Rx5C465", 324 CB_RX5C46X, PCCBB_PCMCIA_MEM_32}, 325 {MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), "Rx5C466", 326 CB_RX5C46X, PCCBB_PCMCIA_MEM_32}, 327 328 /* Toshiba products */ 329 {MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), "ToPIC95", 330 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 331 {MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), "ToPIC95B", 332 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 333 {MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), "ToPIC97", 334 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 335 {MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), "ToPIC100", 336 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 337 338 /* Cirrus Logic products */ 339 {MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), "CL-PD683X", 340 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 341 {MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), "CL-PD683X", 342 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 343 344 /* sentinel, or Generic chip */ 345 {0 /* null id */, "unknown", CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 346 }; 347 348 349 350 static int 351 cb_chipset(pci_id, namep, flagp) 352 u_int32_t pci_id; 353 char const **namep; 354 int *flagp; 355 { 356 int loopend = sizeof(yc_chipsets)/sizeof(yc_chipsets[0]); 357 struct yenta_chipinfo *ycp, *ycend; 358 359 ycend = yc_chipsets + loopend; 360 361 for (ycp =yc_chipsets; ycp < ycend && pci_id != ycp->yc_id; ++ycp); 362 363 if (ycp == ycend) { 364 /* not found */ 365 ycp = yc_chipsets + loopend - 1; /* to point the sentinel */ 366 } 367 368 if (namep != NULL) { 369 *namep = ycp->yc_name; 370 } 371 372 if (flagp != NULL) { 373 *flagp = ycp->yc_flags; 374 } 375 376 return ycp->yc_chiptype; 377 } 378 379 380 381 static void 382 pccbb_shutdown(void *arg) 383 { 384 struct pccbb_softc *sc = arg; 385 pcireg_t command; 386 387 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 388 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 0); 389 390 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 391 392 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 393 PCI_COMMAND_MASTER_ENABLE); 394 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 395 396 } 397 398 void 399 pccbbattach(parent, self, aux) 400 struct device *parent; 401 struct device *self; 402 void *aux; 403 { 404 struct pccbb_softc *sc = (void *)self; 405 struct pci_attach_args *pa = aux; 406 pci_chipset_tag_t pc = pa->pa_pc; 407 pcireg_t sock_base, busreg; 408 bus_addr_t sockbase; 409 char const *name; 410 int flags; 411 412 sc->sc_chipset = cb_chipset(pa->pa_id, &name, &flags); 413 printf(" (%s), chipflags %d\n", name, flags); 414 415 #if rbus 416 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 417 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 418 #endif /* rbus */ 419 420 sc->sc_base_memh = 0; 421 422 /* 423 * MAP socket registers and ExCA registers on memory-space 424 * When no valid address is set on socket base registers (on pci 425 * config space), get it not polite way. 426 */ 427 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 428 429 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 430 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 431 /* The address must be valid. */ 432 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 433 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 434 NULL)) { 435 printf("%s: can't map socket base address 0x%x\n", sc->sc_dev.dv_xname, 436 sock_base); 437 /* I think it's funny: socket base registers must be mapped on 438 memory space, but ... */ 439 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 0, 440 &sc->sc_base_memt, &sc->sc_base_memh, 441 &sockbase, NULL)) { 442 printf("%s: can't map socket base address 0x%lx: io mode\n", 443 sc->sc_dev.dv_xname, sockbase); 444 /* give up... allocate register space via rbus. */ 445 sc->sc_base_memh = 0; 446 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 447 } 448 } else { 449 DPRINTF(("%s: socket base address 0x%lx\n", 450 sc->sc_dev.dv_xname, sockbase)); 451 } 452 } 453 454 455 sc->sc_mem_start = 0; /* XXX */ 456 sc->sc_mem_end = 0xffffffff; /* XXX */ 457 458 /* 459 * When interrupt isn't routed correctly, give up probing cbb and do 460 * not kill pcic-compatible port. 461 */ 462 if ((0 == pa->pa_intrline) || (255 == pa->pa_intrline)) { 463 printf(" Do not use %s because of intr unconfig.\n", sc->sc_dev.dv_xname); 464 return; 465 } 466 467 /* 468 * When bus number isn't set correctly, give up using 32-bit CardBus 469 * mode. 470 */ 471 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 472 #if notyet 473 if (((busreg >> 8) & 0xff) == 0) { 474 printf(" CardBus on %s will not be configured, because of bus no unconfig.\n", sc->sc_dev.dv_xname); 475 flags |= PCCBB_PCMCIA_16BITONLY; 476 } 477 #endif 478 479 /* pccbb_machdep.c end */ 480 481 482 #if defined CBB_DEBUG 483 { 484 static char *intrname[5] = {"NON", "A", "B", "C", "D"}; 485 printf(" intrpin %s, intrtag %d\n", intrname[pa->pa_intrpin], 486 pa->pa_intrline); 487 } 488 #endif 489 490 491 /* setup softc */ 492 sc->sc_pc = pc; 493 sc->sc_iot = pa->pa_iot; 494 sc->sc_memt = pa->pa_memt; 495 sc->sc_dmat = pa->pa_dmat; 496 sc->sc_tag = pa->pa_tag; 497 sc->sc_function = pa->pa_function; 498 499 sc->sc_intrline = pa->pa_intrline; 500 sc->sc_intrtag = pa->pa_intrtag; 501 sc->sc_intrpin = pa->pa_intrpin; 502 503 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 504 505 /* bus bridge initialisation */ 506 pccbb_chipinit(sc); 507 508 shutdownhook_establish(pccbb_shutdown, sc); 509 510 #if __NetBSD_Version__ > 103060000 511 config_defer(self, pccbb_pci_callback); 512 #else 513 pccbb_pci_callback(self); 514 #endif 515 } 516 517 518 519 520 static void 521 pccbb_pci_callback(self) 522 struct device *self; 523 { 524 struct pccbb_softc *sc = (void *)self; 525 pci_chipset_tag_t pc = sc->sc_pc; 526 bus_space_tag_t base_memt; 527 bus_space_handle_t base_memh; 528 u_int32_t maskreg; 529 pci_intr_handle_t ih; 530 const char *intrstr = NULL; 531 bus_addr_t sockbase; 532 struct cbslot_attach_args cba; 533 struct pcmciabus_attach_args paa; 534 struct cardslot_attach_args caa; 535 struct cardslot_softc *csc; 536 537 if (0 == sc->sc_base_memh) { 538 /* The socket registers aren't mapped correctly. */ 539 #if rbus 540 if (rbus_space_alloc(sc->sc_rbus_memt, 541 0, /* address: I don't mind where it is mapped */ 542 0x1000, /* size */ 543 0x0fff, /* mask */ 544 (sc->sc_chipset == CB_RX5C47X || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, /* align */ 545 0, /* flags */ 546 &sockbase, &sc->sc_base_memh)) { 547 return; 548 } 549 sc->sc_base_memt = sc->sc_memt; 550 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 551 DPRINTF(("%s: CardBus resister address 0x%lx -> 0x%x\n", 552 sc->sc_dev.dv_xname, sockbase, pci_conf_read(pc, sc->sc_tag, PCI_SOCKBASE))); 553 #else 554 sc->sc_base_memt = sc->sc_memt; 555 #if !defined CBB_PCI_BASE 556 #define CBB_PCI_BASE 0x20000000 557 #endif 558 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 559 0x1000, /* size */ 560 0x1000, /* alignment */ 561 0, /* boundary */ 562 0, /* flags */ 563 &sockbase, &sc->sc_base_memh)) { 564 /* cannot allocate memory space */ 565 return; 566 } 567 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 568 DPRINTF(("%s: CardBus resister address 0x%x -> 0x%x\n",sc->sc_dev.dv_xname, 569 sock_base, pci_conf_read(pc, sc->sc_tag, PCI_SOCKBASE))); 570 #endif 571 } 572 573 base_memt = sc->sc_base_memt; /* socket regs memory tag */ 574 base_memh = sc->sc_base_memh; /* socket regs memory handle */ 575 576 577 /* CSC Interrupt: Card detect interrupt on */ 578 maskreg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 579 maskreg |= CB_SOCKET_MASK_CD; /* Card detect intr is turned on. */ 580 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, maskreg); 581 /* reset interrupt */ 582 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, 583 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT)); 584 585 586 /* Map and establish the interrupt. */ 587 if (pci_intr_map(pc, sc->sc_intrtag, sc->sc_intrpin, 588 sc->sc_intrline, &ih)) { 589 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 590 return; 591 } 592 intrstr = pci_intr_string(pc, ih); 593 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 594 595 if (sc->sc_ih == NULL) { 596 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 597 if (intrstr != NULL) { 598 printf(" at %s", intrstr); 599 } 600 printf("\n"); 601 return; 602 } 603 604 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 605 606 { 607 u_int32_t sockstat = bus_space_read_4(base_memt,base_memh, CB_SOCKET_STAT); 608 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { /* card exist */ 609 sc->sc_flags |= CBB_CARDEXIST; 610 } 611 } 612 613 /* 614 * attach cardbus 615 */ 616 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 617 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 618 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 619 620 /* initialise cbslot_attach */ 621 cba.cba_busname = "cardbus"; 622 cba.cba_iot = sc->sc_iot; 623 cba.cba_memt = sc->sc_memt; 624 cba.cba_dmat = sc->sc_dmat; 625 cba.cba_function = 0; 626 cba.cba_bus = (busreg >> 8) & 0x0ff; 627 cba.cba_cc = (void *)sc; 628 cba.cba_cf = &pccbb_funcs; 629 cba.cba_intrline = sc->sc_intrline; 630 631 #if rbus 632 cba.cba_rbus_iot = sc->sc_rbus_iot; 633 cba.cba_rbus_memt = sc->sc_rbus_memt; 634 #endif 635 636 cba.cba_cacheline = PCI_CACHELINE(bhlc); 637 cba.cba_lattimer = PCI_CB_LATENCY(busreg); 638 639 printf("%s: cacheline 0x%x lattimer 0x%x\n", sc->sc_dev.dv_xname, 640 cba.cba_cacheline, cba.cba_lattimer); 641 printf("%s: bhlc 0x%x lscp 0x%x\n", sc->sc_dev.dv_xname, 642 bhlc, busreg); 643 #if defined SHOW_REGS 644 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, sc->sc_base_memh); 645 #endif 646 } 647 648 pccbb_pcmcia_attach_setup(sc, &paa); 649 caa.caa_cb_attach = NULL; 650 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 651 caa.caa_cb_attach = &cba; 652 } 653 caa.caa_16_attach = &paa; 654 caa.caa_ph = &sc->sc_pcmcia_h; 655 656 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 657 DPRINTF(("pccbbattach: found cardslot\n")); 658 sc->sc_csc = csc; 659 } 660 661 return; 662 } 663 664 665 666 static void 667 pccbb_chipinit(sc) 668 struct pccbb_softc *sc; 669 { 670 pci_chipset_tag_t pc = sc->sc_pc; 671 pcitag_t tag = sc->sc_tag; 672 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory tag */ 673 bus_space_handle_t base_memh = sc->sc_base_memh; /* socket regs memory handle */ 674 pcireg_t cbctrl; 675 676 /* 677 * Set PCI command reg. 678 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 679 */ 680 { 681 pcireg_t command = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 682 683 /* I believe it is harmless. */ 684 command |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 685 PCI_COMMAND_MASTER_ENABLE); 686 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, command); 687 } 688 689 /* 690 * Set CardBus latency timer 691 */ 692 { 693 pcireg_t pci_lscp = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 694 if (PCI_CB_LATENCY(pci_lscp) < 0x20) { 695 pci_lscp &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 696 pci_lscp |= (0x20 << PCI_CB_LATENCY_SHIFT); 697 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, pci_lscp); 698 } 699 DPRINTF(("CardBus latency timer 0x%x (%x)\n", PCI_CB_LATENCY(pci_lscp), 700 pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 701 } 702 703 /* 704 * Set PCI latency timer 705 */ 706 { 707 pcireg_t pci_bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG); 708 if (PCI_LATTIMER(pci_bhlc) < 0x10) { 709 pci_bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 710 pci_bhlc |= (0x10 << PCI_LATTIMER_SHIFT); 711 pci_conf_write(pc, tag, PCI_BHLC_REG, pci_bhlc); 712 } 713 DPRINTF(("PCI latency timer 0x%x (%x)\n", PCI_LATTIMER(pci_bhlc), 714 pci_conf_read(pc, tag, PCI_BHLC_REG))); 715 } 716 717 /* disable Legacy IO */ 718 719 switch (sc->sc_chipset) { 720 case CB_RX5C46X: /* fallthrogh */ 721 #if 0 722 case CB_RX5C47X: 723 #endif 724 /* 725 * The legacy pcic io-port on Ricoh CardBus bridges cannot be 726 * disabled by substituting 0 into PCI_LEGACY register. Ricoh 727 * CardBus bridges have special bits on Bridge control reg (addr 728 * 0x3e on PCI config space). 729 */ 730 { 731 pcireg_t bcri = pci_conf_read(pc, tag, PCI_BCR_INTR); 732 bcri &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 733 pci_conf_write(pc, tag, PCI_BCR_INTR, bcri); 734 } 735 break; 736 default: 737 /* XXX: I don't know proper way to kill Legacy IO properly. */ 738 pci_conf_write(pc, tag, PCI_LEGACY, 0x0); 739 break; 740 } 741 742 743 744 /* 745 * Interrupt routing: use PCI interrupt 746 */ 747 { 748 u_int32_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 749 bcr &= ~CB_BCR_INTR_IREQ_ENABLE; /* use PCI Intr */ 750 bcr |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 751 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 752 } 753 754 if (CB_TI113X == sc->sc_chipset) { 755 cbctrl = pci_conf_read(pc, tag, PCI_CBCTRL); 756 if (0 == sc->sc_function) { 757 cbctrl |= PCI113X_CBCTRL_PCI_IRQ_ENA; 758 } 759 cbctrl |= PCI113X_CBCTRL_PCI_IRQ_ENA; /* XXX: bug in PCI113X */ 760 cbctrl |= PCI113X_CBCTRL_PCI_CSC; /* CSC intr enable */ 761 cbctrl &= ~PCI113X_CBCTRL_PCI_INTR; /* functional intr prohibit */ 762 cbctrl &= ~PCI113X_CBCTRL_INT_MASK; /* prohibit ISA routing */ 763 pci_conf_write(pc, tag, PCI_CBCTRL, cbctrl); 764 765 /* set ExCA regs: PCI113X required to be set bit 4 at Interrupt 766 and General Register, which is IRQ Enable Register, and clear 767 bit 3:0 to zero in order to route CSC interrupt to PCI 768 interrupt pin. */ 769 bus_space_write_1(base_memt, base_memh, 0x0803, 0x10); 770 /* set ExCA regs: prohibit all pcmcia-style CSC intr. */ 771 bus_space_write_1(base_memt, base_memh, 0x0805, 0x00); 772 #if 1 773 DPRINTF(("ExCA regs:")); 774 DPRINTF((" 0x803: %02x", bus_space_read_1(base_memt, base_memh, 0x803))); 775 DPRINTF((" 0x805: %02x", bus_space_read_1(base_memt, base_memh, 0x805))); 776 DPRINTF((" 0x81e: %02x\n", bus_space_read_1(base_memt,base_memh,0x81e))); 777 #endif 778 } else if (sc->sc_chipset == CB_TI12XX) { 779 cbctrl = pci_conf_read(pc, tag, PCI_CBCTRL); 780 cbctrl &= ~PCI12XX_CBCTRL_INT_MASK; /* intr routing reset */ 781 pci_conf_write(pc, tag, PCI_CBCTRL, cbctrl); 782 /* 783 * set ExCA regs: PCI12XX required to be set bit 4 at Interrupt 784 * and General Register, which is IRQ Enable Register, and clear 785 * bit 3:0 to zero in order to route CSC interrupt to PCI 786 * interrupt pin. 787 */ 788 bus_space_write_1(base_memt, base_memh, 0x0803, 0x10); 789 /* set ExCA regs: prohibit all pcmcia-style CSC intr. */ 790 bus_space_write_1(base_memt, base_memh, 0x0805, 0x00); 791 } else if (sc->sc_chipset == CB_TOPIC95B) { 792 cardbusreg_t sock_ctrl, slot_ctrl; 793 794 sock_ctrl = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 795 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, 796 sock_ctrl | TOPIC_SOCKET_CTRL_SCR_IRQSEL); 797 798 slot_ctrl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 799 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", sc->sc_dev.dv_xname, 800 slot_ctrl)); 801 slot_ctrl |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 802 TOPIC_SLOT_CTRL_ID_LOCK); 803 slot_ctrl |= TOPIC_SLOT_CTRL_CARDBUS; 804 slot_ctrl &= ~TOPIC_SLOT_CTRL_SWDETECT; 805 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slot_ctrl); 806 DPRINTF(("0x%x\n", slot_ctrl)); 807 } 808 809 /* close all memory and io windows */ 810 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 811 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 812 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 813 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 814 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 815 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 816 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 817 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 818 819 return; 820 } 821 822 823 824 /* 825 * attach pccard bus 826 */ 827 STATIC void 828 pccbb_pcmcia_attach_setup(sc, paa) 829 struct pccbb_softc *sc; 830 struct pcmciabus_attach_args *paa; 831 { 832 struct pcic_handle *ph = &sc->sc_pcmcia_h; 833 #if rbus 834 rbus_tag_t rb; 835 #endif 836 837 /* initialise pcmcia part in pccbb_softc */ 838 ph->ph_parent = (struct device *)sc; 839 ph->sock = sc->sc_function; 840 ph->flags = 0; 841 ph->shutdown = 0; 842 ph->ih_irq = sc->sc_intrline; 843 ph->ph_bus_t = sc->sc_base_memt; 844 ph->ph_bus_h = sc->sc_base_memh; 845 ph->ph_read = pccbb_pcmcia_read; 846 ph->ph_write = pccbb_pcmcia_write; 847 sc->sc_pct = &pccbb_pcmcia_funcs; 848 849 Pcic_write(ph, PCIC_CSC_INTR, 0); 850 Pcic_read(ph, PCIC_CSC); 851 852 /* initialise pcmcia bus attachment */ 853 paa->paa_busname = "pcmcia"; 854 paa->pct = sc->sc_pct; 855 paa->pch = ph; 856 paa->iobase = 0; /* I don't use them */ 857 paa->iosize = 0; 858 #if rbus 859 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 860 paa->iobase = rb->rb_start + rb->rb_offset; 861 paa->iosize = rb->rb_end - rb->rb_start; 862 #endif 863 864 return; 865 } 866 867 868 #if 0 869 STATIC void 870 pccbb_pcmcia_attach_card(ph) 871 struct pcic_handle *ph; 872 { 873 if (ph->flags & PCIC_FLAG_CARDP) { 874 panic("pccbb_pcmcia_attach_card: already attached"); 875 } 876 877 /* call the MI attach function */ 878 pcmcia_card_attach(ph->pcmcia); 879 880 ph->flags |= PCIC_FLAG_CARDP; 881 } 882 883 884 STATIC void 885 pccbb_pcmcia_detach_card(ph, flags) 886 struct pcic_handle *ph; 887 int flags; 888 { 889 if (!(ph->flags & PCIC_FLAG_CARDP)) { 890 panic("pccbb_pcmcia_detach_card: already detached"); 891 } 892 893 ph->flags &= ~PCIC_FLAG_CARDP; 894 895 /* call the MI detach function */ 896 pcmcia_card_detach(ph->pcmcia, flags); 897 } 898 #endif 899 900 901 902 903 /* 904 * int pccbbintr(arg) 905 * void *arg; 906 * This routine handles the interrupt from Yenta PCI-CardBus bridge 907 * itself. 908 */ 909 int 910 pccbbintr(arg) 911 void *arg; 912 { 913 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 914 u_int32_t sockevent; 915 bus_space_tag_t memt = sc->sc_base_memt; 916 bus_space_handle_t memh = sc->sc_base_memh; 917 u_int32_t sockstate; 918 919 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 920 if (0 == sockevent) { /* not for me */ 921 return 0; 922 } else { 923 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); /* reset bit */ 924 } 925 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 926 927 if (sockevent & CB_SOCKET_EVENT_CD) { 928 if (CB_SOCKET_STAT_CD == (sockstate & CB_SOCKET_STAT_CD)) { 929 /* A card should be removed. */ 930 if (sc->sc_flags & CBB_CARDEXIST) { 931 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 932 DPRINTF((" card removed, 0x%08x\n", sockstate)); 933 sc->sc_flags &= ~CBB_CARDEXIST; 934 if (sc->sc_csc->sc_status & CARDSLOT_STATUS_CARD_16) { 935 #if 0 936 struct pcic_handle *ph = &sc->sc_pcmcia_h; 937 938 pcmcia_card_deactivate(ph->pcmcia); 939 pccbb_pcmcia_socket_disable(ph); 940 pccbb_pcmcia_detach_card(ph, DETACH_FORCE); 941 #endif 942 cardslot_event_throw(sc->sc_csc, CARDSLOT_EVENT_REMOVAL_16); 943 } else if (sc->sc_csc->sc_status & CARDSLOT_STATUS_CARD_CB) { 944 /* Cardbus intr removed */ 945 cardslot_event_throw(sc->sc_csc, CARDSLOT_EVENT_REMOVAL_CB); 946 } 947 } 948 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD)) { 949 if (sc->sc_flags & CBB_INSERTING) { 950 untimeout(pci113x_insert, sc); 951 } 952 timeout(pci113x_insert, sc, hz/10); 953 sc->sc_flags |= CBB_INSERTING; 954 } 955 } else { 956 DPRINTF(("%s: sockevent = %b\n", 957 sc->sc_dev.dv_xname, sockevent, PCCBB_SOCKEVENT_BITS)); 958 DPRINTF(("%s: sockstate = %b\n", 959 sc->sc_dev.dv_xname, 960 sockstate, PCCBB_SOCKSTATE_BITS)); 961 } 962 963 return 1; 964 } 965 966 967 968 static void 969 pci113x_insert(arg) 970 void *arg; 971 { 972 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 973 u_int32_t sockevent, sockstate; 974 975 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 976 CB_SOCKET_EVENT); 977 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 978 CB_SOCKET_STAT); 979 980 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 981 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 982 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 983 sc->sc_flags |= CBB_CARDEXIST; 984 /* call pccard intterupt handler here */ 985 if (sockstate & CB_SOCKET_STAT_16BIT) { 986 /* 16-bit card found */ 987 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 988 cardslot_event_throw(sc->sc_csc, CARDSLOT_EVENT_INSERTION_16); 989 } else if (sockstate & CB_SOCKET_STAT_CB) { 990 /* cardbus card fuond */ 991 /* cardbus_attach_card(sc->sc_csc); */ 992 cardslot_event_throw(sc->sc_csc, CARDSLOT_EVENT_INSERTION_CB); 993 } else { 994 /* who are you? */ 995 } 996 } else { 997 timeout(pci113x_insert, sc, hz/10); 998 } 999 } 1000 1001 1002 1003 1004 #define PCCBB_PCMCIA_OFFSET 0x800 1005 static u_int8_t 1006 pccbb_pcmcia_read(ph, reg) 1007 struct pcic_handle *ph; 1008 int reg; 1009 { 1010 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg); 1011 } 1012 1013 1014 1015 static void 1016 pccbb_pcmcia_write(ph, reg, val) 1017 struct pcic_handle *ph; 1018 int reg; 1019 u_int8_t val; 1020 { 1021 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, val); 1022 } 1023 1024 1025 1026 1027 /* 1028 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1029 */ 1030 STATIC int 1031 pccbb_ctrl(ct, command) 1032 cardbus_chipset_tag_t ct; 1033 int command; 1034 { 1035 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1036 1037 switch(command) { 1038 case CARDBUS_CD: 1039 if (2 == pccbb_detect_card(sc)) { 1040 int retval = 0; 1041 int status = cb_detect_voltage(sc); 1042 if (PCCARD_VCC_5V & status) { 1043 retval |= CARDBUS_5V_CARD; 1044 } 1045 if (PCCARD_VCC_3V & status) { 1046 retval |= CARDBUS_3V_CARD; 1047 } 1048 if (PCCARD_VCC_XV & status) { 1049 retval |= CARDBUS_XV_CARD; 1050 } 1051 if (PCCARD_VCC_YV & status) { 1052 retval |= CARDBUS_YV_CARD; 1053 } 1054 return retval; 1055 } else { 1056 return 0; 1057 } 1058 break; 1059 case CARDBUS_RESET: 1060 return cb_reset(sc); 1061 break; 1062 case CARDBUS_IO_ENABLE: /* fallthrough */ 1063 case CARDBUS_IO_DISABLE: /* fallthrough */ 1064 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1065 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1066 case CARDBUS_BM_ENABLE: /* fallthrough */ 1067 case CARDBUS_BM_DISABLE: /* fallthrough */ 1068 return pccbb_cardenable(sc, command); 1069 break; 1070 } 1071 1072 return 0; 1073 } 1074 1075 1076 1077 /* 1078 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1079 * This function returns true when it succeeds and returns false when 1080 * it fails. 1081 */ 1082 STATIC int 1083 pccbb_power(ct, command) 1084 cardbus_chipset_tag_t ct; 1085 int command; 1086 { 1087 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1088 1089 u_int32_t status, sock_ctrl; 1090 bus_space_tag_t memt = sc->sc_base_memt; 1091 bus_space_handle_t memh = sc->sc_base_memh; 1092 1093 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1094 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1095 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1096 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1097 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1098 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1099 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1100 "UNKNOWN", 1101 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1102 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1103 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1104 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1105 "UNKNOWN", 1106 command)); 1107 1108 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1109 sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1110 1111 switch (command & CARDBUS_VCCMASK) { 1112 case CARDBUS_VCC_UC: 1113 break; 1114 case CARDBUS_VCC_5V: 1115 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1116 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1117 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1118 } else { 1119 printf("%s: BAD voltage request: no 5 V card\n", sc->sc_dev.dv_xname); 1120 } 1121 break; 1122 case CARDBUS_VCC_3V: 1123 if (CB_SOCKET_STAT_3VCARD & status) { 1124 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1125 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1126 } else { 1127 printf("%s: BAD voltage request: no 3.3 V card\n", sc->sc_dev.dv_xname); 1128 } 1129 break; 1130 case CARDBUS_VCC_0V: 1131 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1132 break; 1133 default: 1134 return 0; /* power NEVER changed */ 1135 break; 1136 } 1137 1138 switch (command & CARDBUS_VPPMASK) { 1139 case CARDBUS_VPP_UC: 1140 break; 1141 case CARDBUS_VPP_0V: 1142 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1143 break; 1144 case CARDBUS_VPP_VCC: 1145 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1146 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1147 break; 1148 case CARDBUS_VPP_12V: 1149 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1150 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1151 break; 1152 } 1153 1154 #if 0 1155 DPRINTF(("sock_ctrl: %x\n", sock_ctrl)); 1156 #endif 1157 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1158 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1159 1160 delay(20*1000); /* wait 20 ms: Vcc setup time */ 1161 /* XXX 1162 delay 200 ms: though the standard defines that the Vcc set-up time 1163 is 20 ms, some PC-Card bridge requires longer duration. 1164 */ 1165 delay(200*1000); 1166 1167 1168 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1169 printf("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1170 sc->sc_dev.dv_xname, sock_ctrl ,status); 1171 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1172 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1173 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V": 1174 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V": 1175 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV": 1176 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV": 1177 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V": 1178 "UNKNOWN", 1179 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC": 1180 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ?"CARDBUS_VPP_12V": 1181 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ?"CARDBUS_VPP_VCC": 1182 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1183 "UNKNOWN", 1184 command)); 1185 #if 0 1186 if (command == (CARDBUS_VCC_0V | CARDBUS_VPP_0V)) { 1187 u_int32_t force = bus_space_read_4(memt, memh, CB_SOCKET_FORCE); 1188 /* Reset Bad Vcc request */ 1189 force &= ~CB_SOCKET_FORCE_BADVCC; 1190 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, force); 1191 printf("new status 0x%x\n", bus_space_read_4(memt, memh,CB_SOCKET_STAT)); 1192 return 1; 1193 } 1194 #endif 1195 return 0; 1196 } 1197 return 1; /* power changed correctly */ 1198 } 1199 1200 1201 1202 1203 1204 1205 #if defined CB_PCMCIA_POLL 1206 struct cb_poll_str { 1207 void *arg; 1208 int (* func) __P((void *)); 1209 int level; 1210 pccard_chipset_tag_t ct; 1211 int count; 1212 }; 1213 1214 static struct cb_poll_str cb_poll[10]; 1215 static int cb_poll_n = 0; 1216 1217 static void cb_pcmcia_poll __P((void *arg)); 1218 1219 static void 1220 cb_pcmcia_poll(arg) 1221 void *arg; 1222 { 1223 struct cb_poll_str *poll = arg; 1224 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1225 struct pccbb_softc *sc = psc->cpc_parent; 1226 int s; 1227 u_int32_t spsr; /* socket present-state reg */ 1228 1229 timeout(cb_pcmcia_poll, arg, hz/10); 1230 switch (poll->level) { 1231 case IPL_NET: 1232 s = splnet(); 1233 break; 1234 case IPL_BIO: 1235 s = splbio(); 1236 break; 1237 case IPL_TTY: /* fallthrough */ 1238 default: 1239 s = spltty(); 1240 break; 1241 } 1242 1243 spsr = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_STAT); 1244 1245 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1246 if (!(spsr & 0x40)) { /* CINT low */ 1247 #else 1248 if (1) { 1249 #endif 1250 if ((*poll->func)(poll->arg) == 1) { 1251 ++poll->count; 1252 printf("intr: reported from poller, 0x%x\n", spsr); 1253 #if defined LEVEL2 1254 } else { 1255 printf("intr: miss! 0x%x\n", spsr); 1256 #endif 1257 } 1258 } 1259 splx(s); 1260 } 1261 #endif /* defined CB_PCMCIA_POLL */ 1262 1263 1264 1265 1266 /* 1267 * static int pccbb_detect_card(struct pccbb_softc *sc) 1268 * return value: 0 if no card exists. 1269 * 1 if 16-bit card exists. 1270 * 2 if cardbus card exists. 1271 */ 1272 static int 1273 pccbb_detect_card(sc) 1274 struct pccbb_softc *sc; 1275 { 1276 bus_space_handle_t base_memh = sc->sc_base_memh; 1277 bus_space_tag_t base_memt = sc->sc_base_memt; 1278 u_int32_t sockstat = bus_space_read_4(base_memt,base_memh, CB_SOCKET_STAT); 1279 int retval = 0; 1280 1281 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { /* CD1 and CD2 asserted */ 1282 /* card must be present */ 1283 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { /* NOTACARD DEASSERTED */ 1284 if (CB_SOCKET_STAT_CB & sockstat) { /* CardBus mode */ 1285 retval = 2; 1286 } else if (CB_SOCKET_STAT_16BIT & sockstat) { /* 16-bit mode */ 1287 retval = 1; 1288 } 1289 } 1290 } 1291 return retval; 1292 } 1293 1294 1295 1296 1297 /* 1298 * STATIC int cb_reset(struct pccbb_softc *sc) 1299 * This function resets CardBus card. 1300 */ 1301 STATIC int 1302 cb_reset(sc) 1303 struct pccbb_softc *sc; 1304 { 1305 /* 1306 * Reset Assert at least 20 ms 1307 * Some machines request longer duration. 1308 */ 1309 int reset_duration = (sc->sc_chipset == CB_RX5C47X ? 400*1000 : 40*1000); 1310 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1311 1312 bcr |= (0x40 << 16); /* Reset bit Assert (bit 6 at 0x3E) */ 1313 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1314 delay(reset_duration); 1315 1316 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1317 bcr &= ~(0x40 << 16); /* Reset bit Deassert (bit 6 at 0x3E) */ 1318 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1319 delay(reset_duration); 1320 } 1321 /* No card found on the slot. Keep Reset. */ 1322 return 1; 1323 } 1324 1325 1326 1327 1328 /* 1329 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1330 * This function detect card Voltage. 1331 */ 1332 STATIC int 1333 cb_detect_voltage(sc) 1334 struct pccbb_softc *sc; 1335 { 1336 u_int32_t psr; /* socket present-state reg */ 1337 bus_space_tag_t iot = sc->sc_base_memt; 1338 bus_space_handle_t ioh = sc->sc_base_memh; 1339 int vol = PCCARD_VCC_UKN; /* set 0 */ 1340 1341 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1342 1343 if (0x400u & psr) { 1344 vol |= PCCARD_VCC_5V; 1345 } 1346 if (0x800u & psr) { 1347 vol |= PCCARD_VCC_3V; 1348 } 1349 1350 return vol; 1351 } 1352 1353 1354 1355 1356 1357 1358 STATIC int 1359 cbbprint(aux, pcic) 1360 void *aux; 1361 const char *pcic; 1362 { 1363 /* 1364 struct cbslot_attach_args *cba = aux; 1365 1366 if (cba->cba_slot >= 0) { 1367 printf(" slot %d", cba->cba_slot); 1368 } 1369 */ 1370 return UNCONF; 1371 } 1372 1373 1374 1375 1376 /* 1377 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1378 * This function enables and disables the card 1379 */ 1380 STATIC int 1381 pccbb_cardenable(sc, function) 1382 struct pccbb_softc *sc; 1383 int function; 1384 { 1385 u_int32_t command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1386 1387 DPRINTF(("pccbb_cardenable:")); 1388 switch (function) { 1389 case CARDBUS_IO_ENABLE: 1390 command |= PCI_COMMAND_IO_ENABLE; 1391 break; 1392 case CARDBUS_IO_DISABLE: 1393 command &= ~PCI_COMMAND_IO_ENABLE; 1394 break; 1395 case CARDBUS_MEM_ENABLE: 1396 command |= PCI_COMMAND_MEM_ENABLE; 1397 break; 1398 case CARDBUS_MEM_DISABLE: 1399 command &= ~PCI_COMMAND_MEM_ENABLE; 1400 break; 1401 case CARDBUS_BM_ENABLE: 1402 command |= PCI_COMMAND_MASTER_ENABLE; 1403 break; 1404 case CARDBUS_BM_DISABLE: 1405 command &= ~PCI_COMMAND_MASTER_ENABLE; 1406 break; 1407 default: 1408 return 0; 1409 } 1410 1411 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1412 DPRINTF((" command reg 0x%x\n", command)); 1413 return 1; 1414 } 1415 1416 1417 1418 1419 1420 1421 #if !rbus 1422 /* 1423 * int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1424 */ 1425 static int 1426 pccbb_io_open(ct, win, start, end) 1427 cardbus_chipset_tag_t ct; 1428 int win; 1429 u_int32_t start, end; 1430 { 1431 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1432 int basereg; 1433 int limitreg; 1434 1435 if ((win < 0) || (win > 2)) { 1436 #if defined DIAGNOSTIC 1437 printf("cardbus_io_open: window out of range %d\n", win); 1438 #endif 1439 return 0; 1440 } 1441 1442 basereg = win*8 + 0x2c; 1443 limitreg = win*8 + 0x30; 1444 1445 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1446 start, basereg, end, limitreg)); 1447 1448 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1449 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1450 return 1; 1451 } 1452 1453 /* 1454 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1455 */ 1456 static int 1457 pccbb_io_close(ct, win) 1458 cardbus_chipset_tag_t ct; 1459 int win; 1460 { 1461 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1462 int basereg; 1463 int limitreg; 1464 1465 if ((win < 0) || (win > 2)) { 1466 #if defined DIAGNOSTIC 1467 printf("cardbus_io_close: window out of range %d\n", win); 1468 #endif 1469 return 0; 1470 } 1471 1472 basereg = win*8 + 0x2c; 1473 limitreg = win*8 + 0x30; 1474 1475 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1476 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1477 return 1; 1478 } 1479 1480 /* 1481 * int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1482 */ 1483 static int 1484 pccbb_mem_open(ct, win, start, end) 1485 cardbus_chipset_tag_t ct; 1486 int win; 1487 u_int32_t start, end; 1488 { 1489 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1490 int basereg; 1491 int limitreg; 1492 1493 if ((win < 0) || (win > 2)) { 1494 #if defined DIAGNOSTIC 1495 printf("cardbus_mem_open: window out of range %d\n", win); 1496 #endif 1497 return 0; 1498 } 1499 1500 basereg = win*8 + 0x1c; 1501 limitreg = win*8 + 0x20; 1502 1503 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1504 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1505 return 1; 1506 } 1507 1508 1509 /* 1510 * int pccbb_mem_close(cardbus_chipset_tag_t, int) 1511 */ 1512 static int 1513 pccbb_mem_close(ct, win) 1514 cardbus_chipset_tag_t ct; 1515 int win; 1516 { 1517 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1518 int basereg; 1519 int limitreg; 1520 1521 if ((win < 0) || (win > 2)) { 1522 #if defined DIAGNOSTIC 1523 printf("cardbus_mem_close: window out of range %d\n", win); 1524 #endif 1525 return 0; 1526 } 1527 1528 basereg = win*8 + 0x1c; 1529 limitreg = win*8 + 0x20; 1530 1531 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1532 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1533 return 1; 1534 } 1535 #endif 1536 1537 1538 1539 static void * 1540 pccbb_intr_establish(ct, irq, level, func, arg) 1541 cardbus_chipset_tag_t ct; 1542 int irq, level; 1543 int (* func) __P((void *)); 1544 void *arg; 1545 { 1546 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1547 1548 switch (sc->sc_chipset) { 1549 case CB_TI113X: 1550 { 1551 pcireg_t cbctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1552 cbctrl |= PCI113X_CBCTRL_PCI_INTR; /* functional intr enabled */ 1553 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, cbctrl); 1554 } 1555 break; 1556 default: 1557 break; 1558 } 1559 1560 return pci_intr_establish(sc->sc_pc, irq, level, func, arg); 1561 } 1562 1563 1564 1565 1566 static void 1567 pccbb_intr_disestablish(ct, ih) 1568 cardbus_chipset_tag_t ct; 1569 void *ih; 1570 { 1571 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1572 1573 switch (sc->sc_chipset) { 1574 case CB_TI113X: 1575 { 1576 pcireg_t cbctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1577 cbctrl &= ~PCI113X_CBCTRL_PCI_INTR; /* functional intr disabled */ 1578 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, cbctrl); 1579 } 1580 break; 1581 default: 1582 break; 1583 } 1584 1585 pci_intr_disestablish(sc->sc_pc, ih); 1586 } 1587 1588 1589 1590 1591 1592 #if defined SHOW_REGS 1593 static void 1594 cb_show_regs(pc, tag, memt, memh) 1595 pci_chipset_tag_t pc; 1596 pcitag_t tag; 1597 bus_space_tag_t memt; 1598 bus_space_handle_t memh; 1599 { 1600 int i; 1601 printf("PCI config regs:"); 1602 for (i = 0; i < 0x50; i += 4) { 1603 if (i % 16 == 0) { 1604 printf("\n 0x%02x:", i); 1605 } 1606 printf(" %08x", pci_conf_read(pc, tag, i)); 1607 } 1608 for (i = 0x80; i < 0xb0; i += 4) { 1609 if (i % 16 == 0) { 1610 printf("\n 0x%02x:", i); 1611 } 1612 printf(" %08x", pci_conf_read(pc, tag, i)); 1613 } 1614 1615 if (memh == 0) { 1616 printf("\n"); 1617 return; 1618 } 1619 1620 printf("\nsocket regs:"); 1621 for (i = 0; i <= 0x10; i += 0x04) { 1622 printf(" %08x", bus_space_read_4(memt, memh, i)); 1623 } 1624 printf("\nExCA regs:"); 1625 for (i = 0; i < 0x08; ++i) { 1626 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1627 } 1628 printf("\n"); 1629 return; 1630 } 1631 #endif 1632 1633 1634 1635 /* 1636 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1637 * int busno, int devno, int function) 1638 * This is the function to make a tag to access config space of 1639 * a CardBus Card. It works same as pci_conf_read. 1640 */ 1641 static cardbustag_t 1642 pccbb_make_tag(cc, busno, devno, function) 1643 cardbus_chipset_tag_t cc; 1644 int busno, devno, function; 1645 { 1646 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1647 1648 return pci_make_tag(sc->sc_pc, busno, devno, function); 1649 } 1650 1651 1652 static void 1653 pccbb_free_tag(cc, tag) 1654 cardbus_chipset_tag_t cc; 1655 cardbustag_t tag; 1656 { 1657 } 1658 1659 1660 /* 1661 * static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t cc, 1662 * cardbustag_t tag, int offset) 1663 * This is the function to read the config space of a CardBus Card. 1664 * It works same as pci_conf_read. 1665 */ 1666 static cardbusreg_t 1667 pccbb_conf_read(cc, tag, offset) 1668 cardbus_chipset_tag_t cc; 1669 cardbustag_t tag; 1670 int offset; /* register offset */ 1671 { 1672 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1673 1674 return pci_conf_read(sc->sc_pc, tag, offset); 1675 } 1676 1677 1678 1679 /* 1680 * static void pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, 1681 * int offs, cardbusreg_t val) 1682 * This is the function to write the config space of a CardBus Card. 1683 * It works same as pci_conf_write. 1684 */ 1685 static void 1686 pccbb_conf_write(cc, tag, reg, val) 1687 cardbus_chipset_tag_t cc; 1688 cardbustag_t tag; 1689 int reg; /* register offset */ 1690 cardbusreg_t val; 1691 { 1692 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1693 1694 pci_conf_write(sc->sc_pc, tag, reg, val); 1695 } 1696 1697 1698 1699 1700 1701 #if 0 1702 STATIC int 1703 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1704 bus_addr_t start, bus_size_t size, 1705 bus_size_t align, bus_addr_t mask, /* address line width */ 1706 int speed, int flags, /* bus width */ 1707 bus_space_handle_t *iohp) 1708 #endif 1709 1710 1711 /* 1712 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1713 * bus_addr_t start, bus_size_t size, 1714 * bus_size_t align, 1715 * struct pcmcia_io_handle *pcihp 1716 * 1717 * This function only allocates I/O region for pccard. This function 1718 * never maps the allcated region to pccard I/O area. 1719 * 1720 * XXX: The interface of this function is not very good, I believe. 1721 */ 1722 STATIC int 1723 pccbb_pcmcia_io_alloc(pch, start, size, align, pcihp) 1724 pcmcia_chipset_handle_t pch; 1725 bus_addr_t start; /* start address */ 1726 bus_size_t size; 1727 bus_size_t align; 1728 struct pcmcia_io_handle *pcihp; 1729 { 1730 struct pcic_handle *ph = (struct pcic_handle *)pch; 1731 bus_addr_t ioaddr; 1732 int flags = 0; 1733 bus_space_tag_t iot; 1734 bus_space_handle_t ioh; 1735 #if rbus 1736 rbus_tag_t rb; 1737 #endif 1738 if (align == 0) { 1739 align = size; /* XXX: funny??? */ 1740 } 1741 1742 1743 /* 1744 * Allocate some arbitrary I/O space. 1745 */ 1746 1747 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 1748 1749 #if rbus 1750 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 1751 if (rbus_space_alloc(rb, start, size, 0x3ff /* XXX: I assume all card decode lower 10 bits by its hardware */, 1752 align, 0, &ioaddr, &ioh)) { 1753 return 1; 1754 } 1755 #else 1756 if (start) { 1757 ioaddr = start; 1758 if (bus_space_map(iot, start, size, 0, &ioh)) { 1759 return 1; 1760 } 1761 DPRINTF(("pccbb_pcmcia_io_alloc map port %lx+%lx\n", 1762 (u_long) ioaddr, (u_long) size)); 1763 } else { 1764 flags |= PCMCIA_IO_ALLOCATED; 1765 if (bus_space_alloc(iot, 0x700/* ph->sc->sc_iobase */, 1766 0x800/* ph->sc->sc_iobase + ph->sc->sc_iosize*/, 1767 size, align, 0, 0, &ioaddr, &ioh)) { 1768 /* No room be able to be get. */ 1769 return 1; 1770 } 1771 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 1772 (u_long) ioaddr, (u_long) size)); 1773 } 1774 #endif 1775 1776 pcihp->iot = iot; 1777 pcihp->ioh = ioh; 1778 pcihp->addr = ioaddr; 1779 pcihp->size = size; 1780 pcihp->flags = flags; 1781 1782 return 0; 1783 } 1784 1785 1786 1787 1788 1789 /* 1790 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 1791 * struct pcmcia_io_handle *pcihp) 1792 * 1793 * This function only frees I/O region for pccard. 1794 * 1795 * XXX: The interface of this function is not very good, I believe. 1796 */ 1797 void 1798 pccbb_pcmcia_io_free(pch, pcihp) 1799 pcmcia_chipset_handle_t pch; 1800 struct pcmcia_io_handle *pcihp; 1801 { 1802 #if !rbus 1803 bus_space_tag_t iot = pcihp->iot; 1804 #endif 1805 bus_space_handle_t ioh = pcihp->ioh; 1806 bus_size_t size = pcihp->size; 1807 1808 #if rbus 1809 struct pccbb_softc *sc = (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 1810 rbus_tag_t rb = sc->sc_rbus_iot; 1811 1812 rbus_space_free(rb, ioh, size, NULL); 1813 #else 1814 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 1815 bus_space_free(iot, ioh, size); 1816 else 1817 bus_space_unmap(iot, ioh, size); 1818 #endif 1819 } 1820 1821 1822 1823 /* 1824 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 1825 * bus_addr_t offset, bus_size_t size, 1826 * struct pcmcia_io_handle *pcihp, 1827 * int *windowp) 1828 * 1829 * This function maps the allocated I/O region to pccard. This function 1830 * never allocates any I/O region for pccard I/O area. I don't 1831 * understand why the original authors of pcmciabus separated alloc and 1832 * map. I believe the two must be unite. 1833 * 1834 * XXX: no wait timing control? 1835 */ 1836 int 1837 pccbb_pcmcia_io_map(pch, width, offset, size, pcihp, windowp) 1838 pcmcia_chipset_handle_t pch; 1839 int width; 1840 bus_addr_t offset; 1841 bus_size_t size; 1842 struct pcmcia_io_handle *pcihp; 1843 int *windowp; 1844 { 1845 struct pcic_handle *ph = (struct pcic_handle *) pch; 1846 bus_addr_t ioaddr = pcihp->addr + offset; 1847 int i, win; 1848 #if defined CBB_DEBUG 1849 static char *width_names[] = { "dynamic", "io8", "io16" }; 1850 #endif 1851 1852 /* Sanity check I/O handle. */ 1853 1854 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 1855 panic("pccbb_pcmcia_io_map iot is bogus"); 1856 } 1857 1858 /* XXX Sanity check offset/size. */ 1859 1860 win = -1; 1861 for (i = 0; i < PCIC_IO_WINS; i++) { 1862 if ((ph->ioalloc & (1 << i)) == 0) { 1863 win = i; 1864 ph->ioalloc |= (1 << i); 1865 break; 1866 } 1867 } 1868 1869 if (win == -1) { 1870 return 1; 1871 } 1872 1873 *windowp = win; 1874 1875 /* XXX this is pretty gross */ 1876 1877 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 1878 win, width_names[width], (u_long) ioaddr, (u_long) size)); 1879 1880 /* XXX wtf is this doing here? */ 1881 1882 #if 0 1883 printf(" port 0x%lx", (u_long) ioaddr); 1884 if (size > 1) { 1885 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 1886 } 1887 #endif 1888 1889 ph->io[win].addr = ioaddr; 1890 ph->io[win].size = size; 1891 ph->io[win].width = width; 1892 1893 /* actual dirty register-value changing in the function below. */ 1894 pccbb_pcmcia_do_io_map(ph, win); 1895 1896 return 0; 1897 } 1898 1899 1900 1901 /* 1902 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 1903 * 1904 * This function changes register-value to map I/O region for pccard. 1905 */ 1906 static void 1907 pccbb_pcmcia_do_io_map(ph, win) 1908 struct pcic_handle *ph; 1909 int win; 1910 { 1911 static u_int8_t pcic_iowidth[3] = { 1912 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 1913 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | PCIC_IOCTL_IO0_DATASIZE_8BIT, 1914 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | PCIC_IOCTL_IO0_DATASIZE_16BIT, 1915 }; 1916 1917 #define PCIC_SIA_START_LOW 0 1918 #define PCIC_SIA_START_HIGH 1 1919 #define PCIC_SIA_STOP_LOW 2 1920 #define PCIC_SIA_STOP_HIGH 3 1921 1922 int regbase_win = 0x8 + win*0x04; 1923 u_int8_t ioctl, enable; 1924 1925 DPRINTF(("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx width %d\n", 1926 win, (long) ph->io[win].addr, (long) ph->io[win].size, 1927 ph->io[win].width * 8)); 1928 1929 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 1930 ph->io[win].addr & 0xff); 1931 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 1932 (ph->io[win].addr >> 8) & 0xff); 1933 1934 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 1935 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 1936 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 1937 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 1938 1939 ioctl = Pcic_read(ph, PCIC_IOCTL); 1940 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 1941 switch (win) { 1942 case 0: 1943 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 1944 PCIC_IOCTL_IO0_IOCS16SRC_MASK | PCIC_IOCTL_IO0_DATASIZE_MASK); 1945 ioctl |= pcic_iowidth[ph->io[win].width]; 1946 enable |= PCIC_ADDRWIN_ENABLE_IO0; 1947 break; 1948 case 1: 1949 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 1950 PCIC_IOCTL_IO1_IOCS16SRC_MASK | PCIC_IOCTL_IO1_DATASIZE_MASK); 1951 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 1952 enable |= PCIC_ADDRWIN_ENABLE_IO1; 1953 break; 1954 } 1955 Pcic_write(ph, PCIC_IOCTL, ioctl); 1956 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 1957 #if defined CBB_DEBUG 1958 { 1959 u_int8_t start_low = Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 1960 u_int8_t start_high = Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 1961 u_int8_t stop_low = Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 1962 u_int8_t stop_high = Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 1963 printf(" start %02x %02x, stop %02x %02x, ioctl %02x enable %02x\n", 1964 start_low, start_high, stop_low, stop_high, ioctl, enable); 1965 } 1966 #endif 1967 } 1968 1969 1970 1971 /* 1972 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 1973 * 1974 * This function unmapss I/O region. No return value. 1975 */ 1976 STATIC void 1977 pccbb_pcmcia_io_unmap(pch, win) 1978 pcmcia_chipset_handle_t pch; 1979 int win; 1980 { 1981 struct pcic_handle *ph = (struct pcic_handle *)pch; 1982 int reg; 1983 1984 if (win >= PCIC_IO_WINS || win < 0) { 1985 panic("pccbb_pcmcia_io_unmap: window out of range"); 1986 } 1987 1988 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 1989 switch (win) { 1990 case 0: 1991 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 1992 break; 1993 case 1: 1994 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 1995 break; 1996 } 1997 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 1998 1999 ph->ioalloc &= ~(1 << win); 2000 } 2001 2002 2003 2004 2005 2006 /* 2007 * static void pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 2008 * 2009 * This function enables the card. All information is stored in 2010 * the first argument, pcmcia_chipset_handle_t. 2011 */ 2012 static void 2013 pccbb_pcmcia_wait_ready(ph) 2014 struct pcic_handle *ph; 2015 { 2016 int i; 2017 2018 DPRINTF(("pccbb_pcmcia_wait_ready: status 0x%02x\n", 2019 Pcic_read(ph, PCIC_IF_STATUS))); 2020 2021 for (i = 0; i < 10000; i++) { 2022 if (Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) { 2023 return; 2024 } 2025 delay(500); 2026 #ifdef CBB_DEBUG 2027 if ((i > 5000) && (i%100 == 99)) 2028 printf("."); 2029 #endif 2030 } 2031 2032 #ifdef DIAGNOSTIC 2033 printf("pcic_wait_ready: ready never happened, status = %02x\n", 2034 Pcic_read(ph, PCIC_IF_STATUS)); 2035 #endif 2036 } 2037 2038 2039 2040 /* 2041 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2042 * 2043 * This function enables the card. All information is stored in 2044 * the first argument, pcmcia_chipset_handle_t. 2045 */ 2046 STATIC void 2047 pccbb_pcmcia_socket_enable(pch) 2048 pcmcia_chipset_handle_t pch; 2049 { 2050 struct pcic_handle *ph = (struct pcic_handle *)pch; 2051 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2052 int cardtype, win; 2053 u_int8_t power, intr; 2054 pcireg_t spsr; 2055 int voltage; 2056 #define PCIC_INTR_PCI PCIC_INTR_ENABLE 2057 2058 /* this bit is mostly stolen from pcic_attach_card */ 2059 2060 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2061 2062 /* get card Vcc info */ 2063 2064 spsr = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_STAT); 2065 if (spsr & CB_SOCKET_STAT_5VCARD) { 2066 DPRINTF(("5V card\n")); 2067 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2068 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2069 DPRINTF(("3V card\n")); 2070 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2071 } else { 2072 printf("?V card, 0x%x\n", spsr); /* XXX */ 2073 return; 2074 } 2075 2076 /* assert reset bit */ 2077 2078 intr = Pcic_read(ph, PCIC_INTR); 2079 intr &= ~PCIC_INTR_RESET; 2080 intr |= PCIC_INTR_PCI; /* XXX */ 2081 Pcic_write(ph, PCIC_INTR, intr); 2082 2083 /* disable socket i/o: negate output enable bit */ 2084 2085 power = Pcic_read(ph, PCIC_PWRCTL); 2086 power &= ~PCIC_PWRCTL_OE; 2087 Pcic_write(ph, PCIC_PWRCTL, power); 2088 2089 /* power down the socket to reset it, clear the card reset pin */ 2090 2091 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2092 2093 /* 2094 * wait 200ms until power fails (Tpf). Then, wait 100ms since 2095 * we are changing Vcc (Toff). 2096 */ 2097 /* delay(300*1000); too much */ 2098 2099 /* power up the socket */ 2100 pccbb_power(sc, voltage); 2101 2102 /* 2103 * wait 100ms until power raise (Tpr) and 20ms to become 2104 * stable (Tsu(Vcc)). 2105 * 2106 * some machines require some more time to be settled 2107 * (another 200ms is added here). 2108 */ 2109 /* delay((100 + 20 + 200)*1000); too much */ 2110 2111 power = Pcic_read(ph, PCIC_PWRCTL); 2112 Pcic_write(ph, PCIC_PWRCTL, power | PCIC_PWRCTL_OE); 2113 2114 /* 2115 * hold RESET at least 10us. 2116 */ 2117 delay(10); 2118 delay(2*1000); /* XXX: TI1130 requires it. */ 2119 delay(20*1000); /* XXX: TI1130 requires it. */ 2120 2121 /* clear the reset flag */ 2122 2123 intr = Pcic_read(ph, PCIC_INTR); 2124 Pcic_write(ph, PCIC_INTR, intr | PCIC_INTR_RESET); 2125 2126 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 2127 2128 delay(20000); 2129 2130 /* wait for the chip to finish initializing */ 2131 2132 pccbb_pcmcia_wait_ready(ph); 2133 2134 /* zero out the address windows */ 2135 2136 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2137 2138 /* set the card type */ 2139 2140 cardtype = pcmcia_card_gettype(ph->pcmcia); 2141 2142 intr = Pcic_read(ph, PCIC_INTR); 2143 intr &= ~PCIC_INTR_CARDTYPE_MASK; 2144 intr |= ((cardtype == PCMCIA_IFTYPE_IO) ? 2145 PCIC_INTR_CARDTYPE_IO : 2146 PCIC_INTR_CARDTYPE_MEM); 2147 Pcic_write(ph, PCIC_INTR, intr); 2148 2149 DPRINTF(("%s: pccbb_pcmcia_socket_enable %02x cardtype %s %02x\n", 2150 ph->ph_parent->dv_xname, ph->sock, 2151 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2152 2153 /* reinstall all the memory and io mappings */ 2154 2155 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2156 if (ph->memalloc & (1 << win)) { 2157 pccbb_pcmcia_do_mem_map(ph, win); 2158 } 2159 } 2160 2161 for (win = 0; win < PCIC_IO_WINS; ++win) { 2162 if (ph->ioalloc & (1 << win)) { 2163 pccbb_pcmcia_do_io_map(ph, win); 2164 } 2165 } 2166 } 2167 2168 2169 2170 /* 2171 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2172 * 2173 * This function disables the card. All information is stored in 2174 * the first argument, pcmcia_chipset_handle_t. 2175 */ 2176 STATIC void 2177 pccbb_pcmcia_socket_disable(pch) 2178 pcmcia_chipset_handle_t pch; 2179 { 2180 struct pcic_handle *ph = (struct pcic_handle *)pch; 2181 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2182 u_int8_t power, intr; 2183 2184 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2185 2186 /* reset signal asserting... */ 2187 2188 intr = Pcic_read(ph, PCIC_INTR); 2189 intr &= ~PCIC_INTR_RESET; 2190 Pcic_write(ph, PCIC_INTR, intr); 2191 delay(2*1000); 2192 2193 /* power down the socket */ 2194 power = Pcic_read(ph, PCIC_PWRCTL); 2195 power &= ~PCIC_PWRCTL_OE; 2196 Pcic_write(ph, PCIC_PWRCTL, power); 2197 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2198 /* 2199 * wait 300ms until power fails (Tpf). 2200 */ 2201 delay(300 * 1000); 2202 } 2203 2204 2205 2206 /* 2207 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2208 * 2209 * This function detects whether a card is in the slot or not. 2210 * If a card is inserted, return 1. Otherwise, return 0. 2211 */ 2212 STATIC int 2213 pccbb_pcmcia_card_detect(pch) 2214 pcmcia_chipset_handle_t pch; 2215 { 2216 struct pcic_handle *ph = (struct pcic_handle *)pch; 2217 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2218 2219 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2220 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2221 } 2222 2223 2224 2225 #if 0 2226 STATIC int 2227 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2228 bus_addr_t start, bus_size_t size, 2229 bus_size_t align, 2230 int speed, int flags, /* bus width */ 2231 bus_space_tag_t *memtp 2232 bus_space_handle_t *memhp) 2233 #endif 2234 2235 2236 /* 2237 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2238 * bus_size_t size, 2239 * struct pcmcia_mem_handle *pcmhp) 2240 * 2241 * This function only allocates memory region for pccard. This 2242 * function never maps the allcated region to pccard memory area. 2243 * 2244 * XXX: Why the argument of start address is not in? 2245 */ 2246 STATIC int 2247 pccbb_pcmcia_mem_alloc(pch, size, pcmhp) 2248 pcmcia_chipset_handle_t pch; 2249 bus_size_t size; 2250 struct pcmcia_mem_handle *pcmhp; 2251 { 2252 struct pcic_handle *ph = (struct pcic_handle *)pch; 2253 bus_space_handle_t memh; 2254 bus_addr_t addr; 2255 bus_size_t sizepg; 2256 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2257 #if rbus 2258 rbus_tag_t rb; 2259 #endif 2260 2261 /* out of sc->memh, allocate as many pages as necessary */ 2262 2263 /* convert size to PCIC pages */ 2264 /* 2265 This is not enough; when the requested region is on the 2266 page boundaries, this may calculate wrong result. 2267 */ 2268 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2269 #if 0 2270 if (sizepg > PCIC_MAX_MEM_PAGES) { 2271 return 1; 2272 } 2273 #endif 2274 2275 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2276 return 1; 2277 } 2278 2279 addr = 0; /* XXX gcc -Wuninitialized */ 2280 2281 #if rbus 2282 rb = sc->sc_rbus_memt; 2283 if (rbus_space_alloc(rb, 0, sizepg*PCIC_MEM_PAGESIZE, 2284 sizepg*PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 2285 0, &addr, &memh)) { 2286 return 1; 2287 } 2288 2289 #else 2290 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2291 sizepg*PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2292 0 /* boundary */, 0 /* flags */, 2293 &addr, &memh)) { 2294 return 1; 2295 } 2296 #endif 2297 2298 DPRINTF(("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, realsize 0x%lx\n", 2299 addr, size, sizepg*PCIC_MEM_PAGESIZE)); 2300 2301 pcmhp->memt = sc->sc_memt; 2302 pcmhp->memh = memh; 2303 pcmhp->addr = addr; 2304 pcmhp->size = size; 2305 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2306 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2307 pcmhp->mhandle = 0; 2308 /* No offset??? Funny. */ 2309 2310 return 0; 2311 } 2312 2313 2314 2315 2316 /* 2317 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2318 * struct pcmcia_mem_handle *pcmhp) 2319 * 2320 * This function release the memory space allocated by the fuction 2321 * pccbb_pcmcia_mem_alloc(). 2322 */ 2323 STATIC void 2324 pccbb_pcmcia_mem_free(pch, pcmhp) 2325 pcmcia_chipset_handle_t pch; 2326 struct pcmcia_mem_handle *pcmhp; 2327 { 2328 #if rbus 2329 struct pcic_handle *ph = (struct pcic_handle *)pch; 2330 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2331 2332 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2333 #else 2334 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2335 #endif 2336 } 2337 2338 2339 2340 2341 /* 2342 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2343 * 2344 * This function release the memory space allocated by the fuction 2345 * pccbb_pcmcia_mem_alloc(). 2346 */ 2347 STATIC void 2348 pccbb_pcmcia_do_mem_map(ph, win) 2349 struct pcic_handle *ph; 2350 int win; 2351 { 2352 int regbase_win; 2353 bus_addr_t phys_addr; 2354 bus_addr_t phys_end; 2355 2356 #define PCIC_SMM_START_LOW 0 2357 #define PCIC_SMM_START_HIGH 1 2358 #define PCIC_SMM_STOP_LOW 2 2359 #define PCIC_SMM_STOP_HIGH 3 2360 #define PCIC_CMA_LOW 4 2361 #define PCIC_CMA_HIGH 5 2362 2363 u_int8_t start_low, start_high = 0; 2364 u_int8_t stop_low, stop_high; 2365 u_int8_t off_low, off_high; 2366 u_int8_t mem_window; 2367 int reg; 2368 2369 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2370 int mem8 = (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8; 2371 2372 regbase_win = 0x10 + win*0x08; 2373 2374 phys_addr = ph->mem[win].addr; 2375 phys_end = phys_addr + ph->mem[win].size; 2376 2377 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2378 phys_addr, phys_end, ph->mem[win].offset)); 2379 2380 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2381 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2382 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2383 2384 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; /* bit 19:12 */ 2385 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) /* bit 23:20 */ 2386 | (mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); /* bit 7 on */ 2387 /* bit 31:24, for 32-bit address */ 2388 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; /* bit 31:24 */ 2389 2390 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2391 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2392 2393 if (((struct pccbb_softc *)ph->ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2394 Pcic_write(ph, 0x40 + win, mem_window); 2395 } 2396 2397 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2398 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2399 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2400 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2401 2402 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2403 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2404 2405 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2406 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2407 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2408 | ((kind == PCMCIA_MEM_ATTR) ? 2409 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2410 2411 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2412 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2413 2414 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2415 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2416 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2417 2418 #if defined CBB_DEBUG 2419 { 2420 int r1, r2, r3, r4, r5, r6, r7 = 0; 2421 2422 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2423 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2424 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2425 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2426 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2427 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2428 if (((struct pccbb_softc *)(ph->ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2429 r7 = Pcic_read(ph, 0x40 + win); 2430 } 2431 2432 DPRINTF(("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2433 "%02x%02x", win, r1, r2, r3, r4, r5, r6)); 2434 if (((struct pccbb_softc *)(ph->ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2435 DPRINTF((" %02x",r7)); 2436 } 2437 DPRINTF(("\n")); 2438 } 2439 #endif 2440 } 2441 2442 2443 2444 2445 /* 2446 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2447 * bus_addr_t card_addr, bus_size_t size, 2448 * struct pcmcia_mem_handle *pcmhp, 2449 * bus_addr_t *offsetp, int *windowp) 2450 * 2451 * This function maps memory space allocated by the fuction 2452 * pccbb_pcmcia_mem_alloc(). 2453 */ 2454 STATIC int 2455 pccbb_pcmcia_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 2456 pcmcia_chipset_handle_t pch; 2457 int kind; 2458 bus_addr_t card_addr; 2459 bus_size_t size; 2460 struct pcmcia_mem_handle *pcmhp; 2461 bus_addr_t *offsetp; 2462 int *windowp; 2463 { 2464 struct pcic_handle *ph = (struct pcic_handle *)pch; 2465 bus_addr_t busaddr; 2466 long card_offset; 2467 int win; 2468 2469 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2470 if ((ph->memalloc & (1 << win)) == 0) { 2471 ph->memalloc |= (1 << win); 2472 break; 2473 } 2474 } 2475 2476 if (win == PCIC_MEM_WINS) { 2477 return 1; 2478 } 2479 2480 *windowp = win; 2481 2482 /* XXX this is pretty gross */ 2483 2484 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2485 panic("pccbb_pcmcia_mem_map memt is bogus"); 2486 } 2487 2488 busaddr = pcmhp->addr; 2489 2490 /* 2491 * compute the address offset to the pcmcia address space for the 2492 * pcic. this is intentionally signed. The masks and shifts below 2493 * will cause TRT to happen in the pcic registers. Deal with making 2494 * sure the address is aligned, and return the alignment offset. 2495 */ 2496 2497 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2498 card_addr -= *offsetp; 2499 2500 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2501 "%lx\n", win, (u_long)busaddr, (u_long)*offsetp, (u_long)size, 2502 (u_long)card_addr)); 2503 2504 /* 2505 * include the offset in the size, and decrement size by one, since 2506 * the hw wants start/stop 2507 */ 2508 size += *offsetp - 1; 2509 2510 card_offset = (((long) card_addr) - ((long) busaddr)); 2511 2512 ph->mem[win].addr = busaddr; 2513 ph->mem[win].size = size; 2514 ph->mem[win].offset = card_offset; 2515 ph->mem[win].kind = kind; 2516 2517 pccbb_pcmcia_do_mem_map(ph, win); 2518 2519 return 0; 2520 } 2521 2522 2523 2524 /* 2525 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2526 * int window) 2527 * 2528 * This function unmaps memory space which mapped by the fuction 2529 * pccbb_pcmcia_mem_map(). 2530 */ 2531 STATIC void 2532 pccbb_pcmcia_mem_unmap(pch, window) 2533 pcmcia_chipset_handle_t pch; 2534 int window; 2535 { 2536 struct pcic_handle *ph = (struct pcic_handle *)pch; 2537 int reg; 2538 2539 if (window >= PCIC_MEM_WINS) { 2540 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2541 } 2542 2543 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2544 reg &= ~(1 << window); 2545 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2546 2547 ph->memalloc &= ~(1 << window); 2548 } 2549 2550 2551 2552 #if defined PCCBB_PCMCIA_POLL 2553 struct pccbb_poll_str { 2554 void *arg; 2555 int (* func) __P((void *)); 2556 int level; 2557 struct pcic_handle *ph; 2558 int count; 2559 int num; 2560 }; 2561 2562 static struct pccbb_poll_str pccbb_poll[10]; 2563 static int pccbb_poll_n = 0; 2564 2565 static void pccbb_pcmcia_poll __P((void *arg)); 2566 2567 static void 2568 pccbb_pcmcia_poll(arg) 2569 void *arg; 2570 { 2571 struct pccbb_poll_str *poll = arg; 2572 struct pcic_handle *ph = poll->ph; 2573 struct pccbb_softc *sc = ph->sc; 2574 int s; 2575 u_int32_t spsr; /* socket present-state reg */ 2576 2577 timeout(pccbb_pcmcia_poll, arg, hz*2); 2578 switch (poll->level) { 2579 case IPL_NET: 2580 s = splnet(); 2581 break; 2582 case IPL_BIO: 2583 s = splbio(); 2584 break; 2585 case IPL_TTY: /* fallthrough */ 2586 default: 2587 s = spltty(); 2588 break; 2589 } 2590 2591 spsr = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_STAT); 2592 2593 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2594 if (!(spsr & 0x40)) /* CINT low */ 2595 #else 2596 if (1) 2597 #endif 2598 { 2599 if ((*poll->func)(poll->arg) > 0) { 2600 ++poll->count; 2601 // printf("intr: reported from poller, 0x%x\n", spsr); 2602 #if defined LEVEL2 2603 } else { 2604 printf("intr: miss! 0x%x\n", spsr); 2605 #endif 2606 } 2607 } 2608 splx(s); 2609 } 2610 #endif /* defined CB_PCMCIA_POLL */ 2611 2612 2613 2614 /* 2615 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2616 * struct pcmcia_function *pf, 2617 * int ipl, 2618 * int (*func)(void *), 2619 * void *arg); 2620 * 2621 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2622 */ 2623 STATIC void * 2624 pccbb_pcmcia_intr_establish(pch, pf, ipl, func, arg) 2625 pcmcia_chipset_handle_t pch; 2626 struct pcmcia_function *pf; 2627 int ipl; 2628 int (*func) __P((void *)); 2629 void *arg; 2630 { 2631 struct pcic_handle *ph = (struct pcic_handle *)pch; 2632 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2633 pci_intr_handle_t handle; 2634 void *ih; 2635 2636 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2637 /* what should I do? */ 2638 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2639 DPRINTF(("%s does not provide edge nor pulse interrupt\n", 2640 sc->sc_dev.dv_xname)); 2641 return NULL; 2642 } 2643 /* 2644 * XXX Noooooo! The interrupt flag must set properly!! 2645 * dumb pcmcia driver!! 2646 */ 2647 } 2648 2649 if (pci_intr_map(sc->sc_pc, sc->sc_intrtag, sc->sc_intrpin, 2650 sc->sc_intrline, &handle)) { 2651 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 2652 return NULL; 2653 } 2654 DPRINTF(("pccbb_pcmcia_intr_establish: line %d, handle %d\n", 2655 sc->sc_intrline, handle)); 2656 2657 if (NULL != (ih = pci_intr_establish(sc->sc_pc, handle, ipl, func, arg))) 2658 { 2659 u_int32_t cbctrl; 2660 2661 if ((CB_TI113X == sc->sc_chipset)) { 2662 cbctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 2663 cbctrl |= PCI113X_CBCTRL_PCI_INTR; /* PCI functional intr req */ 2664 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, cbctrl); 2665 } 2666 } 2667 #if defined PCCBB_PCMCIA_POLL 2668 if (pccbb_poll_n < 10) { 2669 pccbb_poll[pccbb_poll_n].arg = arg; 2670 pccbb_poll[pccbb_poll_n].func = func; 2671 pccbb_poll[pccbb_poll_n].level = ipl; 2672 pccbb_poll[pccbb_poll_n].count = 0; 2673 pccbb_poll[pccbb_poll_n].num = pccbb_poll_n; 2674 pccbb_poll[pccbb_poll_n].ph = ph; 2675 timeout(pccbb_pcmcia_poll, &pccbb_poll[pccbb_poll_n++], hz*2); 2676 printf("polling set\n"); 2677 } 2678 #endif 2679 #if defined SHOW_REGS 2680 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, sc->sc_base_memh); 2681 #endif 2682 2683 return ih; 2684 } 2685 2686 2687 2688 2689 /* 2690 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2691 * void *ih) 2692 * 2693 * This function disables PC-Card interrupt. 2694 */ 2695 STATIC void 2696 pccbb_pcmcia_intr_disestablish(pch, ih) 2697 pcmcia_chipset_handle_t pch; 2698 void *ih; 2699 { 2700 struct pcic_handle *ph = (struct pcic_handle *)pch; 2701 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2702 2703 pci_intr_disestablish(sc->sc_pc, ih); 2704 } 2705 2706 2707 2708 2709 #if rbus 2710 /* 2711 * static int 2712 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2713 * bus_addr_t addr, bus_size_t size, 2714 * bus_addr_t mask, bus_size_t align, 2715 * int flags, bus_addr_t *addrp; 2716 * bus_space_handle_t *bshp) 2717 * 2718 * This function allocates a portion of memory or io space for 2719 * clients. This function is called from CardBus card drivers. 2720 */ 2721 static int 2722 pccbb_rbus_cb_space_alloc(ct, rb, addr, size, mask, align, flags, addrp, bshp) 2723 cardbus_chipset_tag_t ct; 2724 rbus_tag_t rb; 2725 bus_addr_t addr; 2726 bus_size_t size; 2727 bus_addr_t mask; 2728 bus_size_t align; 2729 int flags; 2730 bus_addr_t *addrp; 2731 bus_space_handle_t *bshp; 2732 { 2733 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2734 2735 DPRINTF(("pccbb_rbus_cb_space_alloc: adr %lx, size %lx, mask %lx, align %lx\n", addr, size, mask, align)); 2736 2737 if (align == 0) { 2738 align = size; 2739 } 2740 2741 if (rb->rb_bt == sc->sc_memt) { 2742 if (align < 16) { 2743 return 1; 2744 } 2745 } else if (rb->rb_bt == sc->sc_iot) { 2746 if (align < 4) { 2747 return 1; 2748 } 2749 } else { 2750 DPRINTF(("pccbb_rbus_cb_space_alloc: Bus space tag %x is NOT used.\n", 2751 rb->rb_bt)); 2752 return 1; 2753 /* XXX: panic here? */ 2754 } 2755 2756 /* XXX: hack for avoiding ISA image */ 2757 if (mask < 0x3ff) { 2758 mask = 0x3ff; 2759 addr = 0x300; 2760 } 2761 2762 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 2763 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 2764 return 1; 2765 } 2766 2767 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 2768 2769 return 0; 2770 } 2771 2772 2773 2774 2775 2776 /* 2777 * static int 2778 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 2779 * bus_space_handle_t *bshp, bus_size_t size); 2780 * 2781 * This function is called from CardBus card drivers. 2782 */ 2783 static int 2784 pccbb_rbus_cb_space_free(ct, rb, bsh, size) 2785 cardbus_chipset_tag_t ct; 2786 rbus_tag_t rb; 2787 bus_space_handle_t bsh; 2788 bus_size_t size; 2789 { 2790 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2791 bus_space_tag_t bt = rb->rb_bt; 2792 2793 pccbb_close_win(sc, bt, bsh, size); 2794 2795 if (bt == sc->sc_memt) { 2796 } else if (bt == sc->sc_iot) { 2797 } else { 2798 return 1; 2799 /* XXX: panic here? */ 2800 } 2801 2802 return rbus_space_free(rb, bsh, size, NULL); 2803 } 2804 #endif /* rbus */ 2805 2806 2807 #if rbus 2808 2809 static int 2810 pccbb_open_win(sc, bst, addr, size, bsh, flags) 2811 struct pccbb_softc *sc; 2812 bus_space_tag_t bst; 2813 bus_addr_t addr; 2814 bus_size_t size; 2815 bus_space_handle_t bsh; 2816 int flags; 2817 { 2818 struct pccbb_win_chain **top; 2819 bus_addr_t align; 2820 2821 top = &sc->sc_iowindow; 2822 align = 0x04; 2823 if (sc->sc_memt == bst) { 2824 top = &sc->sc_memwindow; 2825 align = 0x1000; 2826 DPRINTF(("using memory window, %x %x %x\n\n", 2827 sc->sc_iot, sc->sc_memt, bst)); 2828 } 2829 2830 if (pccbb_winlist_insert(top, addr, size, bsh, flags)) { 2831 printf("winlist insert fails:\n"); 2832 } 2833 pccbb_winset(align, sc, bst); 2834 2835 return 0; 2836 } 2837 2838 2839 2840 static int 2841 pccbb_close_win(sc, bst, bsh, size) 2842 struct pccbb_softc *sc; 2843 bus_space_tag_t bst; 2844 bus_space_handle_t bsh; 2845 bus_size_t size; 2846 { 2847 struct pccbb_win_chain **top; 2848 bus_addr_t align; 2849 2850 top = &sc->sc_iowindow; 2851 align = 0x04; 2852 if (sc->sc_memt == bst) { 2853 top = &sc->sc_memwindow; 2854 align = 0x1000; 2855 } 2856 2857 if (pccbb_winlist_delete(top, bsh, size)) { 2858 printf("winlist delete fails:\n"); 2859 } 2860 pccbb_winset(align, sc, bst); 2861 2862 return 0; 2863 } 2864 2865 2866 static int 2867 pccbb_winlist_insert(top, start, size, bsh, flags) 2868 struct pccbb_win_chain **top; 2869 bus_addr_t start; 2870 bus_size_t size; 2871 bus_space_handle_t bsh; 2872 int flags; 2873 { 2874 struct pccbb_win_chain *chainp = *top; 2875 struct pccbb_win_chain *before = *top; 2876 struct pccbb_win_chain *elem; 2877 2878 if (*top == NULL) { 2879 if (NULL == (elem = (struct pccbb_win_chain *)malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, M_NOWAIT))) { 2880 return 1; /* fail */ 2881 } 2882 2883 elem->wc_start = start; 2884 elem->wc_end = start + size - 1; 2885 elem->wc_handle = bsh; 2886 elem->wc_flags = flags; 2887 2888 *top = elem; 2889 elem->wc_next = NULL; 2890 return 0; 2891 } 2892 2893 for(; chainp && chainp->wc_start <= start; chainp = chainp->wc_next) { 2894 before = chainp; 2895 } 2896 2897 if (chainp != NULL) { 2898 if (chainp->wc_start < start + size) { 2899 printf("fatal! 0x%lx 0x%lx\n", chainp->wc_start, start+size); 2900 return 1; 2901 } 2902 } 2903 if ((before != *top) && (before->wc_end >= start)) { 2904 printf("fatal!! 0x%lx 0x%lx\n", before->wc_end, start); 2905 return 1; 2906 } 2907 2908 if (NULL == (elem = (struct pccbb_win_chain *)malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, M_NOWAIT))) { 2909 return 1; /* fail */ 2910 } 2911 2912 elem->wc_start = start; 2913 elem->wc_end = start + size - 1; 2914 elem->wc_handle = bsh; 2915 elem->wc_flags = flags; 2916 2917 elem->wc_next = chainp; 2918 if (chainp == *top) { 2919 *top = elem; 2920 } else { 2921 before->wc_next = elem; 2922 } 2923 return 0; 2924 } 2925 2926 2927 2928 2929 static int 2930 pccbb_winlist_delete(top, bsh, size) 2931 struct pccbb_win_chain **top; 2932 bus_space_handle_t bsh; 2933 bus_size_t size; 2934 { 2935 struct pccbb_win_chain *chainp = *top; 2936 struct pccbb_win_chain **before = top; 2937 2938 for (; chainp && chainp->wc_handle != bsh; chainp = chainp->wc_next) { 2939 before = &chainp->wc_next; 2940 } 2941 2942 if (chainp == NULL) { 2943 return 1; /* fail: no candidate to remove */ 2944 } 2945 2946 if (chainp->wc_end - chainp->wc_start != size - 1) { 2947 printf("fatal!!! 0x%lx\n", chainp->wc_start); 2948 return 1; /* fail: no candidate to remove */ 2949 } 2950 2951 *before = chainp->wc_next; 2952 free(chainp, M_DEVBUF); 2953 2954 return 0; 2955 } 2956 2957 2958 2959 static void 2960 pccbb_winset(align, sc, bst) 2961 bus_addr_t align; 2962 struct pccbb_softc *sc; 2963 bus_space_tag_t bst; 2964 { 2965 pci_chipset_tag_t pc; 2966 pcitag_t tag; 2967 bus_addr_t mask = ~(align - 1); 2968 struct { 2969 cardbusreg_t win_start; 2970 cardbusreg_t win_limit; 2971 int win_flags; 2972 } win[2]; 2973 struct pccbb_win_chain *chainp; 2974 int offs; 2975 2976 win[0].win_start = 0xffffffff; 2977 win[0].win_limit = 0; 2978 win[1].win_start = 0xffffffff; 2979 win[1].win_limit = 0; 2980 2981 chainp = sc->sc_iowindow; 2982 offs = 0x2c; 2983 if (sc->sc_memt == bst) { 2984 chainp = sc->sc_memwindow; 2985 offs = 0x1c; 2986 } 2987 2988 if (chainp) { 2989 win[0].win_start = chainp->wc_start & mask; 2990 win[0].win_limit = chainp->wc_end & mask; 2991 win[0].win_flags = chainp->wc_flags; 2992 chainp = chainp->wc_next; 2993 } 2994 2995 for(; chainp; chainp = chainp->wc_next) { 2996 if (win[1].win_start == 0xffffffff) { 2997 /* window 1 is not used */ 2998 if ((win[0].win_flags == chainp->wc_flags) && 2999 (win[0].win_limit + align >= (chainp->wc_start & mask))) { 3000 /* concatinate */ 3001 win[0].win_limit = chainp->wc_end & mask; 3002 } else { 3003 /* make new window */ 3004 win[1].win_start = chainp->wc_start & mask; 3005 win[1].win_limit = chainp->wc_end & mask; 3006 win[1].win_flags = chainp->wc_flags; 3007 } 3008 continue; 3009 } 3010 3011 /* Both windows are engagad. */ 3012 if (win[0].win_flags == win[1].win_flags) { 3013 /* same flags */ 3014 if (win[0].win_flags == chainp->wc_flags) { 3015 if (win[1].win_start - (win[0].win_limit + align) 3016 < (chainp->wc_start & mask) - ((chainp->wc_end & mask) + align)) { 3017 /* merge window 0 and 1, and set win1 to chainp */ 3018 win[0].win_limit = win[1].win_limit; 3019 win[1].win_start = chainp->wc_start & mask; 3020 win[1].win_limit = chainp->wc_end & mask; 3021 } else { 3022 win[1].win_limit = chainp->wc_end & mask; 3023 } 3024 } else { 3025 /* different flags */ 3026 3027 /* concatinate win0 and win1 */ 3028 win[0].win_limit = win[1].win_limit; 3029 /* allocate win[1] to new space */ 3030 win[1].win_start = chainp->wc_start & mask; 3031 win[1].win_limit = chainp->wc_end & mask; 3032 win[1].win_flags = chainp->wc_flags; 3033 } 3034 } else { 3035 /* the flags of win[0] and win[1] is different */ 3036 if (win[0].win_flags == chainp->wc_flags) { 3037 win[0].win_limit = chainp->wc_end & mask; 3038 /* XXX this creates overlapping windows, so what should the 3039 poor bridge do if one is cachable, and the other is not? */ 3040 printf("%s: overlapping windows\n", sc->sc_dev.dv_xname); 3041 } else { 3042 win[1].win_limit = chainp->wc_end & mask; 3043 } 3044 } 3045 } 3046 3047 pc = sc->sc_pc; 3048 tag = sc->sc_tag; 3049 pci_conf_write(pc, tag, offs, win[0].win_start); 3050 pci_conf_write(pc, tag, offs+4, win[0].win_limit); 3051 pci_conf_write(pc, tag, offs+8, win[1].win_start); 3052 pci_conf_write(pc, tag, offs+12, win[1].win_limit); 3053 DPRINTF(("--pccbb_winset: win0 [%x, %lx), win1 [%x, %lx)\n", 3054 pci_conf_read(pc, tag, offs), 3055 pci_conf_read(pc, tag, offs+4) + align, 3056 pci_conf_read(pc, tag, offs+8), 3057 pci_conf_read(pc, tag, offs+12) + align)); 3058 3059 if (bst == sc->sc_memt) { 3060 if (win[0].win_flags & PCCBB_MEM_CACHABLE) { 3061 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3062 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3063 pci_conf_write(pc,tag, PCI_BCR_INTR, bcr); 3064 } 3065 if (win[1].win_flags & PCCBB_MEM_CACHABLE) { 3066 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3067 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3068 pci_conf_write(pc,tag, PCI_BCR_INTR, bcr); 3069 } 3070 } 3071 } 3072 3073 #endif /* rbus */ 3074
Indexes created Tue Oct 14 21:09:58 GMT 2025