pccbb.c revision 1.172
1 /* $NetBSD: pccbb.c,v 1.172 2008/06/25 11:42:32 drochner Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: pccbb.c,v 1.172 2008/06/25 11:42:32 drochner Exp $"); 35 36 /* 37 #define CBB_DEBUG 38 #define SHOW_REGS 39 */ 40 41 /* 42 * BROKEN! 43 #define PCCBB_PCMCIA_POLL 44 #define CB_PCMCIA_POLL 45 #define CB_PCMCIA_POLL_ONLY 46 #define LEVEL2 47 */ 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/kernel.h> 52 #include <sys/errno.h> 53 #include <sys/ioctl.h> 54 #include <sys/reboot.h> /* for bootverbose */ 55 #include <sys/syslog.h> 56 #include <sys/device.h> 57 #include <sys/malloc.h> 58 #include <sys/proc.h> 59 60 #include <sys/intr.h> 61 #include <sys/bus.h> 62 63 #include <dev/pci/pcivar.h> 64 #include <dev/pci/pcireg.h> 65 #include <dev/pci/pcidevs.h> 66 67 #include <dev/pci/pccbbreg.h> 68 69 #include <dev/cardbus/cardslotvar.h> 70 71 #include <dev/cardbus/cardbusvar.h> 72 73 #include <dev/pcmcia/pcmciareg.h> 74 #include <dev/pcmcia/pcmciavar.h> 75 76 #include <dev/ic/i82365reg.h> 77 #include <dev/ic/i82365var.h> 78 #include <dev/pci/pccbbvar.h> 79 80 #ifndef __NetBSD_Version__ 81 struct cfdriver cbb_cd = { 82 NULL, "cbb", DV_DULL 83 }; 84 #endif 85 86 #ifdef CBB_DEBUG 87 #define DPRINTF(x) printf x 88 #define STATIC 89 #else 90 #define DPRINTF(x) 91 #define STATIC static 92 #endif 93 94 int pccbb_burstup = 1; 95 96 /* 97 * delay_ms() is wait in milliseconds. It should be used instead 98 * of delay() if you want to wait more than 1 ms. 99 */ 100 static inline void 101 delay_ms(int millis, void *param) 102 { 103 if (cold) 104 delay(millis * 1000); 105 else 106 tsleep(param, PWAIT, "pccbb", MAX(2, hz * millis / 1000)); 107 } 108 109 int pcicbbmatch(device_t, struct cfdata *, void *); 110 void pccbbattach(device_t, device_t, void *); 111 int pccbbdetach(device_t, int); 112 int pccbbintr(void *); 113 static void pci113x_insert(void *); 114 static int pccbbintr_function(struct pccbb_softc *); 115 116 static int pccbb_detect_card(struct pccbb_softc *); 117 118 static void pccbb_pcmcia_write(struct pcic_handle *, int, u_int8_t); 119 static u_int8_t pccbb_pcmcia_read(struct pcic_handle *, int); 120 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 121 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 122 123 STATIC int cb_reset(struct pccbb_softc *); 124 STATIC int cb_detect_voltage(struct pccbb_softc *); 125 STATIC int cbbprint(void *, const char *); 126 127 static int cb_chipset(u_int32_t, int *); 128 STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *, 129 struct pcmciabus_attach_args *); 130 #if 0 131 STATIC void pccbb_pcmcia_attach_card(struct pcic_handle *); 132 STATIC void pccbb_pcmcia_detach_card(struct pcic_handle *, int); 133 STATIC void pccbb_pcmcia_deactivate_card(struct pcic_handle *); 134 #endif 135 136 STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int); 137 STATIC int pccbb_power(struct pccbb_softc *sc, int); 138 STATIC int pccbb_power_ct(cardbus_chipset_tag_t, int); 139 STATIC int pccbb_cardenable(struct pccbb_softc * sc, int function); 140 #if !rbus 141 static int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 142 static int pccbb_io_close(cardbus_chipset_tag_t, int); 143 static int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 144 static int pccbb_mem_close(cardbus_chipset_tag_t, int); 145 #endif /* !rbus */ 146 static void *pccbb_intr_establish(struct pccbb_softc *, 147 cardbus_intr_line_t irq, int level, int (*ih) (void *), void *sc); 148 static void pccbb_intr_disestablish(struct pccbb_softc *, void *ih); 149 150 static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t, 151 cardbus_intr_line_t irq, int level, int (*ih) (void *), void *sc); 152 static void pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih); 153 154 static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t, int, int); 155 static void pccbb_free_tag(cardbus_chipset_tag_t, cardbustag_t); 156 static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t, cardbustag_t, int); 157 static void pccbb_conf_write(cardbus_chipset_tag_t, cardbustag_t, int, 158 cardbusreg_t); 159 static void pccbb_chipinit(struct pccbb_softc *); 160 static void pccbb_intrinit(struct pccbb_softc *); 161 162 STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 163 struct pcmcia_mem_handle *); 164 STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t, 165 struct pcmcia_mem_handle *); 166 STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 167 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *); 168 STATIC void pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t, int); 169 STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 170 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 171 STATIC void pccbb_pcmcia_io_free(pcmcia_chipset_handle_t, 172 struct pcmcia_io_handle *); 173 STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 174 bus_size_t, struct pcmcia_io_handle *, int *); 175 STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t, int); 176 STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t, 177 struct pcmcia_function *, int, int (*)(void *), void *); 178 STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t, void *); 179 STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t); 180 STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t); 181 STATIC void pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t, int); 182 STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch); 183 184 static int pccbb_pcmcia_wait_ready(struct pcic_handle *); 185 static void pccbb_pcmcia_delay(struct pcic_handle *, int, const char *); 186 187 static void pccbb_pcmcia_do_io_map(struct pcic_handle *, int); 188 static void pccbb_pcmcia_do_mem_map(struct pcic_handle *, int); 189 190 /* bus-space allocation and deallocation functions */ 191 #if rbus 192 193 static int pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t, rbus_tag_t, 194 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 195 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp); 196 static int pccbb_rbus_cb_space_free(cardbus_chipset_tag_t, rbus_tag_t, 197 bus_space_handle_t, bus_size_t); 198 199 #endif /* rbus */ 200 201 #if rbus 202 203 static int pccbb_open_win(struct pccbb_softc *, bus_space_tag_t, 204 bus_addr_t, bus_size_t, bus_space_handle_t, int flags); 205 static int pccbb_close_win(struct pccbb_softc *, bus_space_tag_t, 206 bus_space_handle_t, bus_size_t); 207 static int pccbb_winlist_insert(struct pccbb_win_chain_head *, bus_addr_t, 208 bus_size_t, bus_space_handle_t, int); 209 static int pccbb_winlist_delete(struct pccbb_win_chain_head *, 210 bus_space_handle_t, bus_size_t); 211 static void pccbb_winset(bus_addr_t align, struct pccbb_softc *, 212 bus_space_tag_t); 213 void pccbb_winlist_show(struct pccbb_win_chain *); 214 215 #endif /* rbus */ 216 217 /* for config_defer */ 218 static void pccbb_pci_callback(device_t); 219 220 static bool pccbb_suspend(device_t PMF_FN_PROTO); 221 static bool pccbb_resume(device_t PMF_FN_PROTO); 222 223 #if defined SHOW_REGS 224 static void cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, 225 bus_space_tag_t memt, bus_space_handle_t memh); 226 #endif 227 228 CFATTACH_DECL_NEW(cbb_pci, sizeof(struct pccbb_softc), 229 pcicbbmatch, pccbbattach, pccbbdetach, NULL); 230 231 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 232 pccbb_pcmcia_mem_alloc, 233 pccbb_pcmcia_mem_free, 234 pccbb_pcmcia_mem_map, 235 pccbb_pcmcia_mem_unmap, 236 pccbb_pcmcia_io_alloc, 237 pccbb_pcmcia_io_free, 238 pccbb_pcmcia_io_map, 239 pccbb_pcmcia_io_unmap, 240 pccbb_pcmcia_intr_establish, 241 pccbb_pcmcia_intr_disestablish, 242 pccbb_pcmcia_socket_enable, 243 pccbb_pcmcia_socket_disable, 244 pccbb_pcmcia_socket_settype, 245 pccbb_pcmcia_card_detect 246 }; 247 248 #if rbus 249 static struct cardbus_functions pccbb_funcs = { 250 pccbb_rbus_cb_space_alloc, 251 pccbb_rbus_cb_space_free, 252 pccbb_cb_intr_establish, 253 pccbb_cb_intr_disestablish, 254 pccbb_ctrl, 255 pccbb_power_ct, 256 pccbb_make_tag, 257 pccbb_free_tag, 258 pccbb_conf_read, 259 pccbb_conf_write, 260 }; 261 #else 262 static struct cardbus_functions pccbb_funcs = { 263 pccbb_ctrl, 264 pccbb_power_ct, 265 pccbb_mem_open, 266 pccbb_mem_close, 267 pccbb_io_open, 268 pccbb_io_close, 269 pccbb_cb_intr_establish, 270 pccbb_cb_intr_disestablish, 271 pccbb_make_tag, 272 pccbb_conf_read, 273 pccbb_conf_write, 274 }; 275 #endif 276 277 int 278 pcicbbmatch(device_t parent, struct cfdata *match, void *aux) 279 { 280 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 281 282 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 283 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 284 PCI_INTERFACE(pa->pa_class) == 0) { 285 return 1; 286 } 287 288 return 0; 289 } 290 291 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 292 | ((prod) << PCI_PRODUCT_SHIFT)) 293 294 const struct yenta_chipinfo { 295 pcireg_t yc_id; /* vendor tag | product tag */ 296 int yc_chiptype; 297 int yc_flags; 298 } yc_chipsets[] = { 299 /* Texas Instruments chips */ 300 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 301 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 302 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 303 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 304 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI125X, 305 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 306 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 307 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 308 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 309 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 310 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 311 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 312 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI125X, 313 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 314 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI125X, 315 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 316 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 317 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 318 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 319 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 320 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI1420, 321 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 322 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI125X, 323 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 324 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 325 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 326 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1520), CB_TI12XX, 327 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 328 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4410YENTA), CB_TI12XX, 329 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 330 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4520YENTA), CB_TI12XX, 331 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 332 333 /* Ricoh chips */ 334 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 335 PCCBB_PCMCIA_MEM_32}, 336 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 337 PCCBB_PCMCIA_MEM_32}, 338 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 339 PCCBB_PCMCIA_MEM_32}, 340 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 341 PCCBB_PCMCIA_MEM_32}, 342 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 343 PCCBB_PCMCIA_MEM_32}, 344 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 345 PCCBB_PCMCIA_MEM_32}, 346 347 /* Toshiba products */ 348 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 349 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 350 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 351 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 352 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 353 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 354 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 355 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 356 357 /* Cirrus Logic products */ 358 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 359 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 360 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 361 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 362 363 /* O2 Micro products */ 364 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6729), 365 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 366 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6730), 367 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 368 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6832), 369 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 370 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6836), 371 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 372 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6872), 373 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 374 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6922), 375 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 376 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6933), 377 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 378 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6972), 379 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 380 381 /* sentinel, or Generic chip */ 382 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 383 }; 384 385 static int 386 cb_chipset(u_int32_t pci_id, int *flagp) 387 { 388 const struct yenta_chipinfo *yc; 389 390 /* Loop over except the last default entry. */ 391 for (yc = yc_chipsets; yc < yc_chipsets + 392 __arraycount(yc_chipsets) - 1; yc++) 393 if (pci_id == yc->yc_id) 394 break; 395 396 if (flagp != NULL) 397 *flagp = yc->yc_flags; 398 399 return (yc->yc_chiptype); 400 } 401 402 void 403 pccbbattach(device_t parent, device_t self, void *aux) 404 { 405 struct pccbb_softc *sc = device_private(self); 406 struct pci_attach_args *pa = aux; 407 pci_chipset_tag_t pc = pa->pa_pc; 408 pcireg_t busreg, reg, sock_base; 409 bus_addr_t sockbase; 410 char devinfo[256]; 411 int flags; 412 413 #ifdef __HAVE_PCCBB_ATTACH_HOOK 414 pccbb_attach_hook(parent, self, pa); 415 #endif 416 417 sc->sc_dev = self; 418 419 callout_init(&sc->sc_insert_ch, 0); 420 callout_setfunc(&sc->sc_insert_ch, pci113x_insert, sc); 421 422 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 423 424 aprint_naive("\n"); 425 426 pci_devinfo(pa->pa_id, 0, 0, devinfo, sizeof(devinfo)); 427 aprint_normal(": %s (rev. 0x%02x)", devinfo, 428 PCI_REVISION(pa->pa_class)); 429 DPRINTF((" (chipflags %x)", flags)); 430 aprint_normal("\n"); 431 432 TAILQ_INIT(&sc->sc_memwindow); 433 TAILQ_INIT(&sc->sc_iowindow); 434 435 #if rbus 436 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 437 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 438 439 #if 0 440 printf("pa->pa_memt: %08x vs rbus_mem->rb_bt: %08x\n", 441 pa->pa_memt, sc->sc_rbus_memt->rb_bt); 442 #endif 443 #endif /* rbus */ 444 445 sc->sc_flags &= ~CBB_MEMHMAPPED; 446 447 /* 448 * MAP socket registers and ExCA registers on memory-space 449 * When no valid address is set on socket base registers (on pci 450 * config space), get it not polite way. 451 */ 452 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 453 454 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 455 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 456 /* The address must be valid. */ 457 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 458 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, &sc->sc_base_size)) { 459 aprint_error_dev(self, 460 "can't map socket base address 0x%lx\n", 461 (unsigned long)sock_base); 462 /* 463 * I think it's funny: socket base registers must be 464 * mapped on memory space, but ... 465 */ 466 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 467 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 468 &sc->sc_base_size)) { 469 aprint_error_dev(self, 470 "can't map socket base address" 471 " 0x%lx: io mode\n", 472 (unsigned long)sockbase); 473 /* give up... allocate reg space via rbus. */ 474 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 475 } else 476 sc->sc_flags |= CBB_MEMHMAPPED; 477 } else { 478 DPRINTF(("%s: socket base address 0x%lx\n", 479 device_xname(self), 480 (unsigned long)sockbase)); 481 sc->sc_flags |= CBB_MEMHMAPPED; 482 } 483 } 484 485 sc->sc_mem_start = 0; /* XXX */ 486 sc->sc_mem_end = 0xffffffff; /* XXX */ 487 488 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 489 490 /* pccbb_machdep.c end */ 491 492 #if defined CBB_DEBUG 493 { 494 static const char *intrname[] = { "NON", "A", "B", "C", "D" }; 495 aprint_debug_dev(self, "intrpin %s, intrtag %d\n", 496 intrname[pa->pa_intrpin], pa->pa_intrline); 497 } 498 #endif 499 500 /* setup softc */ 501 sc->sc_pc = pc; 502 sc->sc_iot = pa->pa_iot; 503 sc->sc_memt = pa->pa_memt; 504 sc->sc_dmat = pa->pa_dmat; 505 sc->sc_tag = pa->pa_tag; 506 sc->sc_function = pa->pa_function; 507 508 memcpy(&sc->sc_pa, pa, sizeof(*pa)); 509 510 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 511 512 /* Disable legacy register mapping. */ 513 switch (sc->sc_chipset) { 514 case CB_RX5C46X: /* fallthrough */ 515 #if 0 516 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 517 case CB_RX5C47X: 518 #endif 519 /* 520 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 521 * cannot be disabled by substituting 0 into PCI_LEGACY 522 * register. Ricoh CardBus bridges have special bits on Bridge 523 * control reg (addr 0x3e on PCI config space). 524 */ 525 reg = pci_conf_read(pc, pa->pa_tag, PCI_BRIDGE_CONTROL_REG); 526 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 527 pci_conf_write(pc, pa->pa_tag, PCI_BRIDGE_CONTROL_REG, reg); 528 break; 529 530 default: 531 /* XXX I don't know proper way to kill legacy I/O. */ 532 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 533 break; 534 } 535 536 if (!pmf_device_register(self, pccbb_suspend, pccbb_resume)) 537 aprint_error_dev(self, "couldn't establish power handler\n"); 538 539 config_defer(self, pccbb_pci_callback); 540 } 541 542 int 543 pccbbdetach(device_t self, int flags) 544 { 545 struct pccbb_softc *sc = device_private(self); 546 pci_chipset_tag_t pc = sc->sc_pa.pa_pc; 547 bus_space_tag_t bmt = sc->sc_base_memt; 548 bus_space_handle_t bmh = sc->sc_base_memh; 549 uint32_t sockmask; 550 int rc; 551 552 if ((rc = config_detach_children(self, flags)) != 0) 553 return rc; 554 555 if (!LIST_EMPTY(&sc->sc_pil)) { 556 panic("%s: interrupt handlers still registered", 557 device_xname(self)); 558 return EBUSY; 559 } 560 561 if (sc->sc_ih != NULL) { 562 pci_intr_disestablish(pc, sc->sc_ih); 563 sc->sc_ih = NULL; 564 } 565 566 /* CSC Interrupt: turn off card detect and power cycle interrupts */ 567 sockmask = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 568 sockmask &= ~(CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | 569 CB_SOCKET_MASK_POWER); 570 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, sockmask); 571 /* reset interrupt */ 572 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 573 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 574 575 switch (sc->sc_flags & (CBB_MEMHMAPPED|CBB_SPECMAPPED)) { 576 case CBB_MEMHMAPPED: 577 bus_space_unmap(bmt, bmh, sc->sc_base_size); 578 break; 579 case CBB_MEMHMAPPED|CBB_SPECMAPPED: 580 #if rbus 581 { 582 pcireg_t sockbase; 583 584 sockbase = pci_conf_read(pc, sc->sc_tag, PCI_SOCKBASE); 585 rbus_space_free(sc->sc_rbus_memt, bmh, 0x1000, 586 NULL); 587 } 588 #else 589 bus_space_free(bmt, bmh, 0x1000); 590 #endif 591 } 592 sc->sc_flags &= ~(CBB_MEMHMAPPED|CBB_SPECMAPPED); 593 594 if (!TAILQ_EMPTY(&sc->sc_iowindow)) 595 aprint_error_dev(self, "i/o windows not empty"); 596 if (!TAILQ_EMPTY(&sc->sc_memwindow)) 597 aprint_error_dev(self, "memory windows not empty"); 598 599 callout_stop(&sc->sc_insert_ch); 600 callout_destroy(&sc->sc_insert_ch); 601 return 0; 602 } 603 604 /* 605 * static void pccbb_pci_callback(device_t self) 606 * 607 * The actual attach routine: get memory space for YENTA register 608 * space, setup YENTA register and route interrupt. 609 * 610 * This function should be deferred because this device may obtain 611 * memory space dynamically. This function must avoid obtaining 612 * memory area which has already kept for another device. 613 */ 614 static void 615 pccbb_pci_callback(device_t self) 616 { 617 struct pccbb_softc *sc = device_private(self); 618 pci_chipset_tag_t pc = sc->sc_pc; 619 bus_addr_t sockbase; 620 struct cbslot_attach_args cba; 621 struct pcmciabus_attach_args paa; 622 struct cardslot_attach_args caa; 623 device_t csc; 624 625 if (!(sc->sc_flags & CBB_MEMHMAPPED)) { 626 /* The socket registers aren't mapped correctly. */ 627 #if rbus 628 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 629 (sc->sc_chipset == CB_RX5C47X 630 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 631 0, &sockbase, &sc->sc_base_memh)) { 632 return; 633 } 634 sc->sc_base_memt = sc->sc_memt; 635 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 636 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 637 device_xname(self), (unsigned long)sockbase, 638 (unsigned long)pci_conf_read(pc, sc->sc_tag, 639 PCI_SOCKBASE))); 640 #else 641 sc->sc_base_memt = sc->sc_memt; 642 #if !defined CBB_PCI_BASE 643 #define CBB_PCI_BASE 0x20000000 644 #endif 645 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 646 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 647 /* cannot allocate memory space */ 648 return; 649 } 650 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 651 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 652 device_xname(self), (unsigned long)sock_base, 653 (unsigned long)pci_conf_read(pc, 654 sc->sc_tag, PCI_SOCKBASE))); 655 #endif 656 sc->sc_flags |= CBB_MEMHMAPPED; 657 } 658 659 /* clear data structure for child device interrupt handlers */ 660 LIST_INIT(&sc->sc_pil); 661 662 /* bus bridge initialization */ 663 pccbb_chipinit(sc); 664 665 sc->sc_pil_intr_enable = 1; 666 667 { 668 u_int32_t sockstat; 669 670 sockstat = bus_space_read_4(sc->sc_base_memt, 671 sc->sc_base_memh, CB_SOCKET_STAT); 672 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 673 sc->sc_flags |= CBB_CARDEXIST; 674 } 675 } 676 677 /* 678 * attach cardbus 679 */ 680 { 681 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 682 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 683 684 /* initialize cbslot_attach */ 685 cba.cba_iot = sc->sc_iot; 686 cba.cba_memt = sc->sc_memt; 687 cba.cba_dmat = sc->sc_dmat; 688 cba.cba_bus = (busreg >> 8) & 0x0ff; 689 cba.cba_cc = (void *)sc; 690 cba.cba_cf = &pccbb_funcs; 691 cba.cba_intrline = 0; /* XXX dummy */ 692 693 #if rbus 694 cba.cba_rbus_iot = sc->sc_rbus_iot; 695 cba.cba_rbus_memt = sc->sc_rbus_memt; 696 #endif 697 698 cba.cba_cacheline = PCI_CACHELINE(bhlc); 699 cba.cba_max_lattimer = PCI_LATTIMER(bhlc); 700 701 aprint_verbose_dev(self, 702 "cacheline 0x%x lattimer 0x%x\n", 703 cba.cba_cacheline, 704 cba.cba_max_lattimer); 705 aprint_verbose_dev(self, "bhlc 0x%x\n", bhlc); 706 #if defined SHOW_REGS 707 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 708 sc->sc_base_memh); 709 #endif 710 } 711 712 pccbb_pcmcia_attach_setup(sc, &paa); 713 caa.caa_cb_attach = NULL; 714 if (cba.cba_bus == 0) 715 aprint_error_dev(self, 716 "secondary bus number uninitialized; try PCI_BUS_FIXUP\n"); 717 else 718 caa.caa_cb_attach = &cba; 719 caa.caa_16_attach = &paa; 720 caa.caa_ph = &sc->sc_pcmcia_h; 721 722 pccbb_intrinit(sc); 723 724 if (NULL != (csc = config_found_ia(self, "pcmciaslot", &caa, 725 cbbprint))) { 726 DPRINTF(("%s: found cardslot\n", __func__)); 727 sc->sc_csc = device_private(csc); 728 } 729 730 return; 731 } 732 733 734 735 736 737 /* 738 * static void pccbb_chipinit(struct pccbb_softc *sc) 739 * 740 * This function initialize YENTA chip registers listed below: 741 * 1) PCI command reg, 742 * 2) PCI and CardBus latency timer, 743 * 3) route PCI interrupt, 744 * 4) close all memory and io windows. 745 * 5) turn off bus power. 746 * 6) card detect and power cycle interrupts on. 747 * 7) clear interrupt 748 */ 749 static void 750 pccbb_chipinit(struct pccbb_softc *sc) 751 { 752 pci_chipset_tag_t pc = sc->sc_pc; 753 pcitag_t tag = sc->sc_tag; 754 bus_space_tag_t bmt = sc->sc_base_memt; 755 bus_space_handle_t bmh = sc->sc_base_memh; 756 pcireg_t bcr, bhlc, cbctl, csr, lscp, mfunc, mrburst, slotctl, sockctl, 757 sysctrl; 758 759 /* 760 * Set PCI command reg. 761 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 762 */ 763 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 764 /* I believe it is harmless. */ 765 csr |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 766 PCI_COMMAND_MASTER_ENABLE); 767 768 /* All O2 Micro chips have broken parity-error reporting 769 * until proven otherwise. The OZ6933 PCI-CardBus Bridge 770 * is known to have the defect---see PR kern/38698. 771 */ 772 if (sc->sc_chipset != CB_O2MICRO) 773 csr |= PCI_COMMAND_PARITY_ENABLE; 774 775 csr |= PCI_COMMAND_SERR_ENABLE; 776 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 777 778 /* 779 * Set CardBus latency timer. 780 */ 781 lscp = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 782 if (PCI_CB_LATENCY(lscp) < 0x20) { 783 lscp &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 784 lscp |= (0x20 << PCI_CB_LATENCY_SHIFT); 785 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, lscp); 786 } 787 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 788 PCI_CB_LATENCY(lscp), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 789 790 /* 791 * Set PCI latency timer. 792 */ 793 bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG); 794 if (PCI_LATTIMER(bhlc) < 0x10) { 795 bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 796 bhlc |= (0x10 << PCI_LATTIMER_SHIFT); 797 pci_conf_write(pc, tag, PCI_BHLC_REG, bhlc); 798 } 799 DPRINTF(("PCI latency timer 0x%x (%x)\n", 800 PCI_LATTIMER(bhlc), pci_conf_read(pc, tag, PCI_BHLC_REG))); 801 802 803 /* Route functional interrupts to PCI. */ 804 bcr = pci_conf_read(pc, tag, PCI_BRIDGE_CONTROL_REG); 805 bcr |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 806 bcr |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 807 /* assert reset */ 808 bcr |= PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT; 809 /* Set master abort mode to 1, forward SERR# from secondary 810 * to primary, and detect parity errors on secondary. 811 */ 812 bcr |= PCI_BRIDGE_CONTROL_MABRT << PCI_BRIDGE_CONTROL_SHIFT; 813 bcr |= PCI_BRIDGE_CONTROL_SERR << PCI_BRIDGE_CONTROL_SHIFT; 814 bcr |= PCI_BRIDGE_CONTROL_PERE << PCI_BRIDGE_CONTROL_SHIFT; 815 pci_conf_write(pc, tag, PCI_BRIDGE_CONTROL_REG, bcr); 816 817 switch (sc->sc_chipset) { 818 case CB_TI113X: 819 cbctl = pci_conf_read(pc, tag, PCI_CBCTRL); 820 /* This bit is shared, but may read as 0 on some chips, so set 821 it explicitly on both functions. */ 822 cbctl |= PCI113X_CBCTRL_PCI_IRQ_ENA; 823 /* CSC intr enable */ 824 cbctl |= PCI113X_CBCTRL_PCI_CSC; 825 /* functional intr prohibit | prohibit ISA routing */ 826 cbctl &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 827 pci_conf_write(pc, tag, PCI_CBCTRL, cbctl); 828 break; 829 830 case CB_TI1420: 831 sysctrl = pci_conf_read(pc, tag, PCI_SYSCTRL); 832 mrburst = pccbb_burstup 833 ? PCI1420_SYSCTRL_MRBURST : PCI1420_SYSCTRL_MRBURSTDN; 834 if ((sysctrl & PCI1420_SYSCTRL_MRBURST) == mrburst) { 835 printf("%s: %swrite bursts enabled\n", 836 device_xname(sc->sc_dev), 837 pccbb_burstup ? "read/" : ""); 838 } else if (pccbb_burstup) { 839 printf("%s: enabling read/write bursts\n", 840 device_xname(sc->sc_dev)); 841 sysctrl |= PCI1420_SYSCTRL_MRBURST; 842 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 843 } else { 844 printf("%s: disabling read bursts, " 845 "enabling write bursts\n", 846 device_xname(sc->sc_dev)); 847 sysctrl |= PCI1420_SYSCTRL_MRBURSTDN; 848 sysctrl &= ~PCI1420_SYSCTRL_MRBURSTUP; 849 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 850 } 851 /*FALLTHROUGH*/ 852 case CB_TI12XX: 853 /* 854 * Some TI 12xx (and [14][45]xx) based pci cards 855 * sometimes have issues with the MFUNC register not 856 * being initialized due to a bad EEPROM on board. 857 * Laptops that this matters on have this register 858 * properly initialized. 859 * 860 * The TI125X parts have a different register. 861 */ 862 mfunc = pci_conf_read(pc, tag, PCI12XX_MFUNC); 863 if (mfunc == 0) { 864 mfunc &= ~PCI12XX_MFUNC_PIN0; 865 mfunc |= PCI12XX_MFUNC_PIN0_INTA; 866 if ((pci_conf_read(pc, tag, PCI_SYSCTRL) & 867 PCI12XX_SYSCTRL_INTRTIE) == 0) { 868 mfunc &= ~PCI12XX_MFUNC_PIN1; 869 mfunc |= PCI12XX_MFUNC_PIN1_INTB; 870 } 871 pci_conf_write(pc, tag, PCI12XX_MFUNC, mfunc); 872 } 873 /* fallthrough */ 874 875 case CB_TI125X: 876 /* 877 * Disable zoom video. Some machines initialize this 878 * improperly and experience has shown that this helps 879 * prevent strange behavior. 880 */ 881 pci_conf_write(pc, tag, PCI12XX_MMCTRL, 0); 882 883 sysctrl = pci_conf_read(pc, tag, PCI_SYSCTRL); 884 sysctrl |= PCI12XX_SYSCTRL_VCCPROT; 885 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 886 cbctl = pci_conf_read(pc, tag, PCI_CBCTRL); 887 cbctl |= PCI12XX_CBCTRL_CSC; 888 pci_conf_write(pc, tag, PCI_CBCTRL, cbctl); 889 break; 890 891 case CB_TOPIC95B: 892 sockctl = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 893 sockctl |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 894 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, sockctl); 895 slotctl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 896 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 897 device_xname(sc->sc_dev), slotctl)); 898 slotctl |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 899 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 900 slotctl &= ~TOPIC_SLOT_CTRL_SWDETECT; 901 DPRINTF(("0x%x\n", slotctl)); 902 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slotctl); 903 break; 904 905 case CB_TOPIC97: 906 slotctl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 907 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 908 device_xname(sc->sc_dev), slotctl)); 909 slotctl |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 910 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 911 slotctl &= ~TOPIC_SLOT_CTRL_SWDETECT; 912 slotctl |= TOPIC97_SLOT_CTRL_PCIINT; 913 slotctl &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 914 DPRINTF(("0x%x\n", slotctl)); 915 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slotctl); 916 /* make sure to assert LV card support bits */ 917 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 918 0x800 + 0x3e, 919 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 920 0x800 + 0x3e) | 0x03); 921 break; 922 } 923 924 /* Close all memory and I/O windows. */ 925 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 926 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 927 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 928 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 929 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 930 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 931 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 932 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 933 934 /* reset 16-bit pcmcia bus */ 935 bus_space_write_1(bmt, bmh, 0x800 + PCIC_INTR, 936 bus_space_read_1(bmt, bmh, 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 937 938 /* turn off power */ 939 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 940 } 941 942 static void 943 pccbb_intrinit(struct pccbb_softc *sc) 944 { 945 pcireg_t sockmask; 946 const char *intrstr = NULL; 947 pci_intr_handle_t ih; 948 pci_chipset_tag_t pc = sc->sc_pc; 949 bus_space_tag_t bmt = sc->sc_base_memt; 950 bus_space_handle_t bmh = sc->sc_base_memh; 951 952 /* Map and establish the interrupt. */ 953 if (pci_intr_map(&sc->sc_pa, &ih)) { 954 aprint_error_dev(sc->sc_dev, "couldn't map interrupt\n"); 955 return; 956 } 957 intrstr = pci_intr_string(pc, ih); 958 959 /* 960 * XXX pccbbintr should be called under the priority lower 961 * than any other hard interupts. 962 */ 963 KASSERT(sc->sc_ih == NULL); 964 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 965 966 if (sc->sc_ih == NULL) { 967 aprint_error_dev(sc->sc_dev, "couldn't establish interrupt"); 968 if (intrstr != NULL) 969 aprint_error(" at %s\n", intrstr); 970 else 971 aprint_error("\n"); 972 return; 973 } 974 975 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 976 977 /* CSC Interrupt: Card detect and power cycle interrupts on */ 978 sockmask = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 979 sockmask |= CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | 980 CB_SOCKET_MASK_POWER; 981 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, sockmask); 982 /* reset interrupt */ 983 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 984 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 985 } 986 987 /* 988 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 989 * struct pcmciabus_attach_args *paa) 990 * 991 * This function attaches 16-bit PCcard bus. 992 */ 993 STATIC void 994 pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 995 struct pcmciabus_attach_args *paa) 996 { 997 struct pcic_handle *ph = &sc->sc_pcmcia_h; 998 #if rbus 999 rbus_tag_t rb; 1000 #endif 1001 1002 /* initialize pcmcia part in pccbb_softc */ 1003 ph->ph_parent = sc; 1004 ph->sock = sc->sc_function; 1005 ph->flags = 0; 1006 ph->shutdown = 0; 1007 ph->ih_irq = sc->sc_pa.pa_intrline; 1008 ph->ph_bus_t = sc->sc_base_memt; 1009 ph->ph_bus_h = sc->sc_base_memh; 1010 ph->ph_read = pccbb_pcmcia_read; 1011 ph->ph_write = pccbb_pcmcia_write; 1012 sc->sc_pct = &pccbb_pcmcia_funcs; 1013 1014 /* 1015 * We need to do a few things here: 1016 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 1017 * setting the IRQ numbers to 0. 1018 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 1019 * routing of CSC interrupts (e.g. card removal) to PCI while in 1020 * PCMCIA mode. We just leave this set all the time. 1021 * 3) Enable card insertion/removal interrupts in case the chip also 1022 * needs that while in PCMCIA mode. 1023 * 4) Clear any pending CSC interrupt. 1024 */ 1025 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE); 1026 if (sc->sc_chipset == CB_TI113X) { 1027 Pcic_write(ph, PCIC_CSC_INTR, 0); 1028 } else { 1029 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 1030 Pcic_read(ph, PCIC_CSC); 1031 } 1032 1033 /* initialize pcmcia bus attachment */ 1034 paa->paa_busname = "pcmcia"; 1035 paa->pct = sc->sc_pct; 1036 paa->pch = ph; 1037 paa->iobase = 0; /* I don't use them */ 1038 paa->iosize = 0; 1039 #if rbus 1040 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 1041 paa->iobase = rb->rb_start + rb->rb_offset; 1042 paa->iosize = rb->rb_end - rb->rb_start; 1043 #endif 1044 1045 return; 1046 } 1047 1048 #if 0 1049 STATIC void 1050 pccbb_pcmcia_attach_card(struct pcic_handle *ph) 1051 { 1052 if (ph->flags & PCIC_FLAG_CARDP) { 1053 panic("pccbb_pcmcia_attach_card: already attached"); 1054 } 1055 1056 /* call the MI attach function */ 1057 pcmcia_card_attach(ph->pcmcia); 1058 1059 ph->flags |= PCIC_FLAG_CARDP; 1060 } 1061 1062 STATIC void 1063 pccbb_pcmcia_detach_card(struct pcic_handle *ph, int flags) 1064 { 1065 if (!(ph->flags & PCIC_FLAG_CARDP)) { 1066 panic("pccbb_pcmcia_detach_card: already detached"); 1067 } 1068 1069 ph->flags &= ~PCIC_FLAG_CARDP; 1070 1071 /* call the MI detach function */ 1072 pcmcia_card_detach(ph->pcmcia, flags); 1073 } 1074 #endif 1075 1076 /* 1077 * int pccbbintr(arg) 1078 * void *arg; 1079 * This routine handles the interrupt from Yenta PCI-CardBus bridge 1080 * itself. 1081 */ 1082 int 1083 pccbbintr(void *arg) 1084 { 1085 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1086 u_int32_t sockevent, sockstate; 1087 bus_space_tag_t memt = sc->sc_base_memt; 1088 bus_space_handle_t memh = sc->sc_base_memh; 1089 struct pcic_handle *ph = &sc->sc_pcmcia_h; 1090 1091 if (!device_has_power(sc->sc_dev)) 1092 return 0; 1093 1094 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 1095 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 1096 Pcic_read(ph, PCIC_CSC); 1097 1098 if (sockevent != 0) { 1099 aprint_debug("%s: enter sockevent %" PRIx32 "\n", __func__, 1100 sockevent); 1101 } 1102 1103 /* Sometimes a change of CSTSCHG# accompanies the first 1104 * interrupt from an Atheros WLAN. That generates a 1105 * CB_SOCKET_EVENT_CSTS event on the bridge. The event 1106 * isn't interesting to pccbb(4), so we used to ignore the 1107 * interrupt. Now, let the child devices try to handle 1108 * the interrupt, instead. The Atheros NIC produces 1109 * interrupts more reliably, now: used to be that it would 1110 * only interrupt if the driver avoided powering down the 1111 * NIC's cardslot, and then the NIC would only work after 1112 * it was reset a second time. 1113 */ 1114 if (sockevent == 0 || 1115 (sockevent & ~(CB_SOCKET_EVENT_POWER|CB_SOCKET_EVENT_CD)) != 0) { 1116 /* This intr is not for me: it may be for my child devices. */ 1117 if (sc->sc_pil_intr_enable) { 1118 return pccbbintr_function(sc); 1119 } else { 1120 return 0; 1121 } 1122 } 1123 1124 if (sockevent & CB_SOCKET_EVENT_CD) { 1125 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1126 if (0x00 != (sockstate & CB_SOCKET_STAT_CD)) { 1127 /* A card should be removed. */ 1128 if (sc->sc_flags & CBB_CARDEXIST) { 1129 DPRINTF(("%s: 0x%08x", 1130 device_xname(sc->sc_dev), sockevent)); 1131 DPRINTF((" card removed, 0x%08x\n", sockstate)); 1132 sc->sc_flags &= ~CBB_CARDEXIST; 1133 if (sc->sc_csc->sc_status & 1134 CARDSLOT_STATUS_CARD_16) { 1135 #if 0 1136 struct pcic_handle *ph = 1137 &sc->sc_pcmcia_h; 1138 1139 pcmcia_card_deactivate(ph->pcmcia); 1140 pccbb_pcmcia_socket_disable(ph); 1141 pccbb_pcmcia_detach_card(ph, 1142 DETACH_FORCE); 1143 #endif 1144 cardslot_event_throw(sc->sc_csc, 1145 CARDSLOT_EVENT_REMOVAL_16); 1146 } else if (sc->sc_csc->sc_status & 1147 CARDSLOT_STATUS_CARD_CB) { 1148 /* Cardbus intr removed */ 1149 cardslot_event_throw(sc->sc_csc, 1150 CARDSLOT_EVENT_REMOVAL_CB); 1151 } 1152 } else if (sc->sc_flags & CBB_INSERTING) { 1153 sc->sc_flags &= ~CBB_INSERTING; 1154 callout_stop(&sc->sc_insert_ch); 1155 } 1156 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 1157 /* 1158 * The pccbbintr may called from powerdown hook when 1159 * the system resumed, to detect the card 1160 * insertion/removal during suspension. 1161 */ 1162 (sc->sc_flags & CBB_CARDEXIST) == 0) { 1163 if (sc->sc_flags & CBB_INSERTING) { 1164 callout_stop(&sc->sc_insert_ch); 1165 } 1166 callout_schedule(&sc->sc_insert_ch, hz / 5); 1167 sc->sc_flags |= CBB_INSERTING; 1168 } 1169 } 1170 1171 /* XXX sockevent == 9 does occur in the wild. handle it. */ 1172 if (sockevent & CB_SOCKET_EVENT_POWER) { 1173 DPRINTF(("Powercycling because of socket event\n")); 1174 /* XXX: Does not happen when attaching a 16-bit card */ 1175 sc->sc_pwrcycle++; 1176 wakeup(&sc->sc_pwrcycle); 1177 } 1178 1179 return (1); 1180 } 1181 1182 /* 1183 * static int pccbbintr_function(struct pccbb_softc *sc) 1184 * 1185 * This function calls each interrupt handler registered at the 1186 * bridge. The interrupt handlers are called in registered order. 1187 */ 1188 static int 1189 pccbbintr_function(struct pccbb_softc *sc) 1190 { 1191 int retval = 0, val; 1192 struct pccbb_intrhand_list *pil; 1193 int s; 1194 1195 LIST_FOREACH(pil, &sc->sc_pil, pil_next) { 1196 s = splraiseipl(pil->pil_icookie); 1197 val = (*pil->pil_func)(pil->pil_arg); 1198 splx(s); 1199 1200 retval = retval == 1 ? 1 : 1201 retval == 0 ? val : val != 0 ? val : retval; 1202 } 1203 1204 return retval; 1205 } 1206 1207 static void 1208 pci113x_insert(void *arg) 1209 { 1210 struct pccbb_softc *sc = arg; 1211 u_int32_t sockevent, sockstate; 1212 1213 if (!(sc->sc_flags & CBB_INSERTING)) { 1214 /* We add a card only under inserting state. */ 1215 return; 1216 } 1217 sc->sc_flags &= ~CBB_INSERTING; 1218 1219 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1220 CB_SOCKET_EVENT); 1221 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1222 CB_SOCKET_STAT); 1223 1224 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1225 DPRINTF(("%s: 0x%08x", device_xname(sc->sc_dev), sockevent)); 1226 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1227 sc->sc_flags |= CBB_CARDEXIST; 1228 /* call pccard interrupt handler here */ 1229 if (sockstate & CB_SOCKET_STAT_16BIT) { 1230 /* 16-bit card found */ 1231 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1232 cardslot_event_throw(sc->sc_csc, 1233 CARDSLOT_EVENT_INSERTION_16); 1234 } else if (sockstate & CB_SOCKET_STAT_CB) { 1235 /* cardbus card found */ 1236 /* cardbus_attach_card(sc->sc_csc); */ 1237 cardslot_event_throw(sc->sc_csc, 1238 CARDSLOT_EVENT_INSERTION_CB); 1239 } else { 1240 /* who are you? */ 1241 } 1242 } else { 1243 callout_schedule(&sc->sc_insert_ch, hz / 10); 1244 } 1245 } 1246 1247 #define PCCBB_PCMCIA_OFFSET 0x800 1248 static u_int8_t 1249 pccbb_pcmcia_read(struct pcic_handle *ph, int reg) 1250 { 1251 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1252 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1253 1254 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1255 PCCBB_PCMCIA_OFFSET + reg); 1256 } 1257 1258 static void 1259 pccbb_pcmcia_write(struct pcic_handle *ph, int reg, u_int8_t val) 1260 { 1261 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1262 val); 1263 1264 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1265 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1266 } 1267 1268 /* 1269 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1270 */ 1271 STATIC int 1272 pccbb_ctrl(cardbus_chipset_tag_t ct, int command) 1273 { 1274 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1275 1276 switch (command) { 1277 case CARDBUS_CD: 1278 if (2 == pccbb_detect_card(sc)) { 1279 int retval = 0; 1280 int status = cb_detect_voltage(sc); 1281 if (PCCARD_VCC_5V & status) { 1282 retval |= CARDBUS_5V_CARD; 1283 } 1284 if (PCCARD_VCC_3V & status) { 1285 retval |= CARDBUS_3V_CARD; 1286 } 1287 if (PCCARD_VCC_XV & status) { 1288 retval |= CARDBUS_XV_CARD; 1289 } 1290 if (PCCARD_VCC_YV & status) { 1291 retval |= CARDBUS_YV_CARD; 1292 } 1293 return retval; 1294 } else { 1295 return 0; 1296 } 1297 case CARDBUS_RESET: 1298 return cb_reset(sc); 1299 case CARDBUS_IO_ENABLE: /* fallthrough */ 1300 case CARDBUS_IO_DISABLE: /* fallthrough */ 1301 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1302 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1303 case CARDBUS_BM_ENABLE: /* fallthrough */ 1304 case CARDBUS_BM_DISABLE: /* fallthrough */ 1305 /* XXX: I think we don't need to call this function below. */ 1306 return pccbb_cardenable(sc, command); 1307 } 1308 1309 return 0; 1310 } 1311 1312 STATIC int 1313 pccbb_power_ct(cardbus_chipset_tag_t ct, int command) 1314 { 1315 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1316 1317 return pccbb_power(sc, command); 1318 } 1319 1320 /* 1321 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1322 * This function returns true when it succeeds and returns false when 1323 * it fails. 1324 */ 1325 STATIC int 1326 pccbb_power(struct pccbb_softc *sc, int command) 1327 { 1328 u_int32_t status, osock_ctrl, sock_ctrl, reg_ctrl; 1329 bus_space_tag_t memt = sc->sc_base_memt; 1330 bus_space_handle_t memh = sc->sc_base_memh; 1331 int on = 0, pwrcycle, s, times; 1332 struct timeval before, after, diff; 1333 1334 DPRINTF(("pccbb_power: %s and %s [0x%x]\n", 1335 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1336 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1337 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1338 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1339 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1340 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1341 "UNKNOWN", 1342 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1343 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1344 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1345 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1346 "UNKNOWN", command)); 1347 1348 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1349 osock_ctrl = sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1350 1351 switch (command & CARDBUS_VCCMASK) { 1352 case CARDBUS_VCC_UC: 1353 break; 1354 case CARDBUS_VCC_5V: 1355 on++; 1356 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1357 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1358 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1359 } else { 1360 aprint_error_dev(sc->sc_dev, 1361 "BAD voltage request: no 5 V card\n"); 1362 return 0; 1363 } 1364 break; 1365 case CARDBUS_VCC_3V: 1366 on++; 1367 if (CB_SOCKET_STAT_3VCARD & status) { 1368 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1369 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1370 } else { 1371 aprint_error_dev(sc->sc_dev, 1372 "BAD voltage request: no 3.3 V card\n"); 1373 return 0; 1374 } 1375 break; 1376 case CARDBUS_VCC_0V: 1377 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1378 break; 1379 default: 1380 return 0; /* power NEVER changed */ 1381 } 1382 1383 switch (command & CARDBUS_VPPMASK) { 1384 case CARDBUS_VPP_UC: 1385 break; 1386 case CARDBUS_VPP_0V: 1387 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1388 break; 1389 case CARDBUS_VPP_VCC: 1390 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1391 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1392 break; 1393 case CARDBUS_VPP_12V: 1394 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1395 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1396 break; 1397 } 1398 1399 pwrcycle = sc->sc_pwrcycle; 1400 aprint_debug_dev(sc->sc_dev, "osock_ctrl %#" PRIx32 1401 " sock_ctrl %#" PRIx32 "\n", osock_ctrl, sock_ctrl); 1402 1403 microtime(&before); 1404 s = splbio(); 1405 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1406 1407 /* 1408 * Wait as long as 200ms for a power-cycle interrupt. If 1409 * interrupts are enabled, but the socket has already 1410 * changed to the desired status, keep waiting for the 1411 * interrupt. "Consuming" the interrupt in this way keeps 1412 * the interrupt from prematurely waking some subsequent 1413 * pccbb_power call. 1414 * 1415 * XXX Not every bridge interrupts on the ->OFF transition. 1416 * XXX That's ok, we will time-out after 200ms. 1417 * 1418 * XXX The power cycle event will never happen when attaching 1419 * XXX a 16-bit card. That's ok, we will time-out after 1420 * XXX 200ms. 1421 */ 1422 for (times = 5; --times >= 0; ) { 1423 if (cold) 1424 DELAY(40 * 1000); 1425 else { 1426 (void)tsleep(&sc->sc_pwrcycle, PWAIT, "pccpwr", 1427 hz / 25); 1428 if (pwrcycle == sc->sc_pwrcycle) 1429 continue; 1430 } 1431 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1432 if ((status & CB_SOCKET_STAT_PWRCYCLE) != 0 && on) 1433 break; 1434 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0 && !on) 1435 break; 1436 } 1437 splx(s); 1438 microtime(&after); 1439 timersub(&after, &before, &diff); 1440 aprint_debug_dev(sc->sc_dev, "wait took%s %ld.%06lds\n", 1441 (on && times < 0) ? " too long" : "", diff.tv_sec, diff.tv_usec); 1442 1443 /* 1444 * Ok, wait a bit longer for things to settle. 1445 */ 1446 if (on && sc->sc_chipset == CB_TOPIC95B) 1447 delay_ms(100, sc); 1448 1449 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1450 1451 if (on && sc->sc_chipset != CB_TOPIC95B) { 1452 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0) 1453 aprint_error_dev(sc->sc_dev, "power on failed?\n"); 1454 } 1455 1456 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1457 aprint_error_dev(sc->sc_dev, 1458 "bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1459 sock_ctrl, status); 1460 aprint_error_dev(sc->sc_dev, "disabling socket\n"); 1461 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1462 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1463 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1464 status &= ~CB_SOCKET_STAT_BADVCC; 1465 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, status); 1466 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1467 CB_SOCKET_STAT)); 1468 return 0; 1469 } 1470 1471 if (sc->sc_chipset == CB_TOPIC97) { 1472 reg_ctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL); 1473 reg_ctrl &= ~TOPIC97_REG_CTRL_TESTMODE; 1474 if ((command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V) 1475 reg_ctrl &= ~TOPIC97_REG_CTRL_CLKRUN_ENA; 1476 else 1477 reg_ctrl |= TOPIC97_REG_CTRL_CLKRUN_ENA; 1478 pci_conf_write(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL, reg_ctrl); 1479 } 1480 1481 return 1; /* power changed correctly */ 1482 } 1483 1484 #if defined CB_PCMCIA_POLL 1485 struct cb_poll_str { 1486 void *arg; 1487 int (*func)(void *); 1488 int level; 1489 pccard_chipset_tag_t ct; 1490 int count; 1491 struct callout poll_ch; 1492 }; 1493 1494 static struct cb_poll_str cb_poll[10]; 1495 static int cb_poll_n = 0; 1496 1497 static void cb_pcmcia_poll(void *arg); 1498 1499 static void 1500 cb_pcmcia_poll(void *arg) 1501 { 1502 struct cb_poll_str *poll = arg; 1503 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1504 struct pccbb_softc *sc = psc->cpc_parent; 1505 int s; 1506 u_int32_t spsr; /* socket present-state reg */ 1507 1508 callout_reset(&poll->poll_ch, hz / 10, cb_pcmcia_poll, poll); 1509 switch (poll->level) { 1510 case IPL_NET: 1511 s = splnet(); 1512 break; 1513 case IPL_BIO: 1514 s = splbio(); 1515 break; 1516 case IPL_TTY: /* fallthrough */ 1517 default: 1518 s = spltty(); 1519 break; 1520 } 1521 1522 spsr = 1523 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1524 CB_SOCKET_STAT); 1525 1526 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1527 if (!(spsr & 0x40)) { /* CINT low */ 1528 #else 1529 if (1) { 1530 #endif 1531 if ((*poll->func) (poll->arg) == 1) { 1532 ++poll->count; 1533 printf("intr: reported from poller, 0x%x\n", spsr); 1534 #if defined LEVEL2 1535 } else { 1536 printf("intr: miss! 0x%x\n", spsr); 1537 #endif 1538 } 1539 } 1540 splx(s); 1541 } 1542 #endif /* defined CB_PCMCIA_POLL */ 1543 1544 /* 1545 * static int pccbb_detect_card(struct pccbb_softc *sc) 1546 * return value: 0 if no card exists. 1547 * 1 if 16-bit card exists. 1548 * 2 if cardbus card exists. 1549 */ 1550 static int 1551 pccbb_detect_card(struct pccbb_softc *sc) 1552 { 1553 bus_space_handle_t base_memh = sc->sc_base_memh; 1554 bus_space_tag_t base_memt = sc->sc_base_memt; 1555 u_int32_t sockstat = 1556 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1557 int retval = 0; 1558 1559 /* CD1 and CD2 asserted */ 1560 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1561 /* card must be present */ 1562 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1563 /* NOTACARD DEASSERTED */ 1564 if (CB_SOCKET_STAT_CB & sockstat) { 1565 /* CardBus mode */ 1566 retval = 2; 1567 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1568 /* 16-bit mode */ 1569 retval = 1; 1570 } 1571 } 1572 } 1573 return retval; 1574 } 1575 1576 /* 1577 * STATIC int cb_reset(struct pccbb_softc *sc) 1578 * This function resets CardBus card. 1579 */ 1580 STATIC int 1581 cb_reset(struct pccbb_softc *sc) 1582 { 1583 /* 1584 * Reset Assert at least 20 ms 1585 * Some machines request longer duration. 1586 */ 1587 int reset_duration = 1588 (sc->sc_chipset == CB_RX5C47X ? 400 : 50); 1589 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1590 aprint_debug("%s: enter bcr %" PRIx32 "\n", __func__, bcr); 1591 1592 /* Reset bit Assert (bit 6 at 0x3E) */ 1593 bcr |= PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT; 1594 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr); 1595 aprint_debug("%s: wrote bcr %" PRIx32 "\n", __func__, bcr); 1596 delay_ms(reset_duration, sc); 1597 1598 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1599 /* Reset bit Deassert (bit 6 at 0x3E) */ 1600 bcr &= ~(PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT); 1601 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, 1602 bcr); 1603 aprint_debug("%s: wrote bcr %" PRIx32 "\n", __func__, bcr); 1604 delay_ms(reset_duration, sc); 1605 aprint_debug("%s: end of delay\n", __func__); 1606 } 1607 /* No card found on the slot. Keep Reset. */ 1608 return 1; 1609 } 1610 1611 /* 1612 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1613 * This function detect card Voltage. 1614 */ 1615 STATIC int 1616 cb_detect_voltage(struct pccbb_softc *sc) 1617 { 1618 u_int32_t psr; /* socket present-state reg */ 1619 bus_space_tag_t iot = sc->sc_base_memt; 1620 bus_space_handle_t ioh = sc->sc_base_memh; 1621 int vol = PCCARD_VCC_UKN; /* set 0 */ 1622 1623 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1624 1625 if (0x400u & psr) { 1626 vol |= PCCARD_VCC_5V; 1627 } 1628 if (0x800u & psr) { 1629 vol |= PCCARD_VCC_3V; 1630 } 1631 1632 return vol; 1633 } 1634 1635 STATIC int 1636 cbbprint(void *aux, const char *pcic) 1637 { 1638 #if 0 1639 struct cbslot_attach_args *cba = aux; 1640 1641 if (cba->cba_slot >= 0) { 1642 aprint_normal(" slot %d", cba->cba_slot); 1643 } 1644 #endif 1645 return UNCONF; 1646 } 1647 1648 /* 1649 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1650 * This function enables and disables the card 1651 */ 1652 STATIC int 1653 pccbb_cardenable(struct pccbb_softc *sc, int function) 1654 { 1655 u_int32_t command = 1656 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1657 1658 DPRINTF(("pccbb_cardenable:")); 1659 switch (function) { 1660 case CARDBUS_IO_ENABLE: 1661 command |= PCI_COMMAND_IO_ENABLE; 1662 break; 1663 case CARDBUS_IO_DISABLE: 1664 command &= ~PCI_COMMAND_IO_ENABLE; 1665 break; 1666 case CARDBUS_MEM_ENABLE: 1667 command |= PCI_COMMAND_MEM_ENABLE; 1668 break; 1669 case CARDBUS_MEM_DISABLE: 1670 command &= ~PCI_COMMAND_MEM_ENABLE; 1671 break; 1672 case CARDBUS_BM_ENABLE: 1673 command |= PCI_COMMAND_MASTER_ENABLE; 1674 break; 1675 case CARDBUS_BM_DISABLE: 1676 command &= ~PCI_COMMAND_MASTER_ENABLE; 1677 break; 1678 default: 1679 return 0; 1680 } 1681 1682 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1683 DPRINTF((" command reg 0x%x\n", command)); 1684 return 1; 1685 } 1686 1687 #if !rbus 1688 static int 1689 pccbb_io_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 1690 { 1691 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1692 int basereg; 1693 int limitreg; 1694 1695 if ((win < 0) || (win > 2)) { 1696 #if defined DIAGNOSTIC 1697 printf("cardbus_io_open: window out of range %d\n", win); 1698 #endif 1699 return 0; 1700 } 1701 1702 basereg = win * 8 + PCI_CB_IOBASE0; 1703 limitreg = win * 8 + PCI_CB_IOLIMIT0; 1704 1705 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1706 start, basereg, end, limitreg)); 1707 1708 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1709 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1710 return 1; 1711 } 1712 1713 /* 1714 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1715 */ 1716 static int 1717 pccbb_io_close(cardbus_chipset_tag_t ct, int win) 1718 { 1719 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1720 int basereg; 1721 int limitreg; 1722 1723 if ((win < 0) || (win > 2)) { 1724 #if defined DIAGNOSTIC 1725 printf("cardbus_io_close: window out of range %d\n", win); 1726 #endif 1727 return 0; 1728 } 1729 1730 basereg = win * 8 + PCI_CB_IOBASE0; 1731 limitreg = win * 8 + PCI_CB_IOLIMIT0; 1732 1733 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1734 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1735 return 1; 1736 } 1737 1738 static int 1739 pccbb_mem_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 1740 { 1741 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1742 int basereg; 1743 int limitreg; 1744 1745 if ((win < 0) || (win > 2)) { 1746 #if defined DIAGNOSTIC 1747 printf("cardbus_mem_open: window out of range %d\n", win); 1748 #endif 1749 return 0; 1750 } 1751 1752 basereg = win * 8 + PCI_CB_MEMBASE0; 1753 limitreg = win * 8 + PCI_CB_MEMLIMIT0; 1754 1755 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1756 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1757 return 1; 1758 } 1759 1760 static int 1761 pccbb_mem_close(cardbus_chipset_tag_t ct, int win) 1762 { 1763 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1764 int basereg; 1765 int limitreg; 1766 1767 if ((win < 0) || (win > 2)) { 1768 #if defined DIAGNOSTIC 1769 printf("cardbus_mem_close: window out of range %d\n", win); 1770 #endif 1771 return 0; 1772 } 1773 1774 basereg = win * 8 + PCI_CB_MEMBASE0; 1775 limitreg = win * 8 + PCI_CB_MEMLIMIT0; 1776 1777 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1778 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1779 return 1; 1780 } 1781 #endif 1782 1783 /* 1784 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1785 * int irq, 1786 * int level, 1787 * int (* func)(void *), 1788 * void *arg) 1789 * 1790 * This function registers an interrupt handler at the bridge, in 1791 * order not to call the interrupt handlers of child devices when 1792 * a card-deletion interrupt occurs. 1793 * 1794 * The arguments irq and level are not used. 1795 */ 1796 static void * 1797 pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, cardbus_intr_line_t irq, 1798 int level, int (*func)(void *), void *arg) 1799 { 1800 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1801 1802 return pccbb_intr_establish(sc, irq, level, func, arg); 1803 } 1804 1805 1806 /* 1807 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1808 * void *ih) 1809 * 1810 * This function removes an interrupt handler pointed by ih. 1811 */ 1812 static void 1813 pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih) 1814 { 1815 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1816 1817 pccbb_intr_disestablish(sc, ih); 1818 } 1819 1820 1821 void 1822 pccbb_intr_route(struct pccbb_softc *sc) 1823 { 1824 pcireg_t bcr, cbctrl; 1825 1826 /* initialize bridge intr routing */ 1827 bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1828 bcr &= ~CB_BCR_INTR_IREQ_ENABLE; 1829 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr); 1830 1831 switch (sc->sc_chipset) { 1832 case CB_TI113X: 1833 cbctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1834 /* functional intr enabled */ 1835 cbctrl |= PCI113X_CBCTRL_PCI_INTR; 1836 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, cbctrl); 1837 break; 1838 default: 1839 break; 1840 } 1841 } 1842 1843 /* 1844 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1845 * int irq, 1846 * int level, 1847 * int (* func)(void *), 1848 * void *arg) 1849 * 1850 * This function registers an interrupt handler at the bridge, in 1851 * order not to call the interrupt handlers of child devices when 1852 * a card-deletion interrupt occurs. 1853 * 1854 * The arguments irq is not used because pccbb selects intr vector. 1855 */ 1856 static void * 1857 pccbb_intr_establish(struct pccbb_softc *sc, cardbus_intr_line_t irq, 1858 int level, int (*func)(void *), void *arg) 1859 { 1860 struct pccbb_intrhand_list *pil, *newpil; 1861 1862 DPRINTF(("pccbb_intr_establish start. %p\n", LIST_FIRST(&sc->sc_pil))); 1863 1864 if (LIST_EMPTY(&sc->sc_pil)) { 1865 pccbb_intr_route(sc); 1866 } 1867 1868 /* 1869 * Allocate a room for interrupt handler structure. 1870 */ 1871 if (NULL == (newpil = 1872 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1873 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1874 return NULL; 1875 } 1876 1877 newpil->pil_func = func; 1878 newpil->pil_arg = arg; 1879 newpil->pil_icookie = makeiplcookie(level); 1880 1881 if (LIST_EMPTY(&sc->sc_pil)) { 1882 LIST_INSERT_HEAD(&sc->sc_pil, newpil, pil_next); 1883 } else { 1884 for (pil = LIST_FIRST(&sc->sc_pil); 1885 LIST_NEXT(pil, pil_next) != NULL; 1886 pil = LIST_NEXT(pil, pil_next)); 1887 LIST_INSERT_AFTER(pil, newpil, pil_next); 1888 } 1889 1890 DPRINTF(("pccbb_intr_establish add pil. %p\n", 1891 LIST_FIRST(&sc->sc_pil))); 1892 1893 return newpil; 1894 } 1895 1896 /* 1897 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1898 * void *ih) 1899 * 1900 * This function removes an interrupt handler pointed by ih. ih 1901 * should be the value returned by cardbus_intr_establish() or 1902 * NULL. 1903 * 1904 * When ih is NULL, this function will do nothing. 1905 */ 1906 static void 1907 pccbb_intr_disestablish(struct pccbb_softc *sc, void *ih) 1908 { 1909 struct pccbb_intrhand_list *pil; 1910 pcireg_t reg; 1911 1912 DPRINTF(("pccbb_intr_disestablish start. %p\n", 1913 LIST_FIRST(&sc->sc_pil))); 1914 1915 if (ih == NULL) { 1916 /* intr handler is not set */ 1917 DPRINTF(("pccbb_intr_disestablish: no ih\n")); 1918 return; 1919 } 1920 1921 #ifdef DIAGNOSTIC 1922 LIST_FOREACH(pil, &sc->sc_pil, pil_next) { 1923 DPRINTF(("pccbb_intr_disestablish: pil %p\n", pil)); 1924 if (pil == ih) { 1925 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1926 break; 1927 } 1928 } 1929 if (pil == NULL) { 1930 panic("pccbb_intr_disestablish: %s cannot find pil %p", 1931 device_xname(sc->sc_dev), ih); 1932 } 1933 #endif 1934 1935 pil = (struct pccbb_intrhand_list *)ih; 1936 LIST_REMOVE(pil, pil_next); 1937 free(pil, M_DEVBUF); 1938 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1939 1940 if (LIST_EMPTY(&sc->sc_pil)) { 1941 /* No interrupt handlers */ 1942 1943 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1944 1945 /* stop routing PCI intr */ 1946 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1947 reg |= CB_BCR_INTR_IREQ_ENABLE; 1948 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, reg); 1949 1950 switch (sc->sc_chipset) { 1951 case CB_TI113X: 1952 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1953 /* functional intr disabled */ 1954 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1955 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1956 break; 1957 default: 1958 break; 1959 } 1960 } 1961 } 1962 1963 #if defined SHOW_REGS 1964 static void 1965 cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, bus_space_tag_t memt, 1966 bus_space_handle_t memh) 1967 { 1968 int i; 1969 printf("PCI config regs:"); 1970 for (i = 0; i < 0x50; i += 4) { 1971 if (i % 16 == 0) 1972 printf("\n 0x%02x:", i); 1973 printf(" %08x", pci_conf_read(pc, tag, i)); 1974 } 1975 for (i = 0x80; i < 0xb0; i += 4) { 1976 if (i % 16 == 0) 1977 printf("\n 0x%02x:", i); 1978 printf(" %08x", pci_conf_read(pc, tag, i)); 1979 } 1980 1981 if (memh == 0) { 1982 printf("\n"); 1983 return; 1984 } 1985 1986 printf("\nsocket regs:"); 1987 for (i = 0; i <= 0x10; i += 0x04) 1988 printf(" %08x", bus_space_read_4(memt, memh, i)); 1989 printf("\nExCA regs:"); 1990 for (i = 0; i < 0x08; ++i) 1991 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1992 printf("\n"); 1993 return; 1994 } 1995 #endif 1996 1997 /* 1998 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1999 * int busno, int function) 2000 * This is the function to make a tag to access config space of 2001 * a CardBus Card. It works same as pci_conf_read. 2002 */ 2003 static cardbustag_t 2004 pccbb_make_tag(cardbus_chipset_tag_t cc, int busno, int function) 2005 { 2006 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 2007 2008 return pci_make_tag(sc->sc_pc, busno, 0, function); 2009 } 2010 2011 static void 2012 pccbb_free_tag(cardbus_chipset_tag_t cc, cardbustag_t tag) 2013 { 2014 } 2015 2016 /* 2017 * pccbb_conf_read 2018 * 2019 * This is the function to read the config space of a CardBus card. 2020 * It works the same as pci_conf_read(9). 2021 */ 2022 static cardbusreg_t 2023 pccbb_conf_read(cardbus_chipset_tag_t cc, cardbustag_t tag, int offset) 2024 { 2025 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 2026 2027 return pci_conf_read(sc->sc_pc, tag, offset); 2028 } 2029 2030 /* 2031 * pccbb_conf_write 2032 * 2033 * This is the function to write the config space of a CardBus 2034 * card. It works the same as pci_conf_write(9). 2035 */ 2036 static void 2037 pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, int reg, 2038 cardbusreg_t val) 2039 { 2040 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 2041 2042 pci_conf_write(sc->sc_pc, tag, reg, val); 2043 } 2044 2045 #if 0 2046 STATIC int 2047 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 2048 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 2049 int speed, int flags, 2050 bus_space_handle_t * iohp) 2051 #endif 2052 /* 2053 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 2054 * bus_addr_t start, bus_size_t size, 2055 * bus_size_t align, 2056 * struct pcmcia_io_handle *pcihp 2057 * 2058 * This function only allocates I/O region for pccard. This function 2059 * never maps the allocated region to pccard I/O area. 2060 * 2061 * XXX: The interface of this function is not very good, I believe. 2062 */ 2063 STATIC int 2064 pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, 2065 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 2066 { 2067 struct pcic_handle *ph = (struct pcic_handle *)pch; 2068 bus_addr_t ioaddr; 2069 int flags = 0; 2070 bus_space_tag_t iot; 2071 bus_space_handle_t ioh; 2072 bus_addr_t mask; 2073 #if rbus 2074 rbus_tag_t rb; 2075 #endif 2076 if (align == 0) { 2077 align = size; /* XXX: funny??? */ 2078 } 2079 2080 if (start != 0) { 2081 /* XXX: assume all card decode lower 10 bits by its hardware */ 2082 mask = 0x3ff; 2083 /* enforce to use only masked address */ 2084 start &= mask; 2085 } else { 2086 /* 2087 * calculate mask: 2088 * 1. get the most significant bit of size (call it msb). 2089 * 2. compare msb with the value of size. 2090 * 3. if size is larger, shift msb left once. 2091 * 4. obtain mask value to decrement msb. 2092 */ 2093 bus_size_t size_tmp = size; 2094 int shifts = 0; 2095 2096 mask = 1; 2097 while (size_tmp) { 2098 ++shifts; 2099 size_tmp >>= 1; 2100 } 2101 mask = (1 << shifts); 2102 if (mask < size) { 2103 mask <<= 1; 2104 } 2105 --mask; 2106 } 2107 2108 /* 2109 * Allocate some arbitrary I/O space. 2110 */ 2111 2112 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 2113 2114 #if rbus 2115 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 2116 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 2117 return 1; 2118 } 2119 DPRINTF(("pccbb_pcmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2120 (u_long) ioaddr, (u_long) size)); 2121 #else 2122 if (start) { 2123 ioaddr = start; 2124 if (bus_space_map(iot, start, size, 0, &ioh)) { 2125 return 1; 2126 } 2127 DPRINTF(("pccbb_pcmcia_io_alloc map port 0x%lx+0x%lx\n", 2128 (u_long) ioaddr, (u_long) size)); 2129 } else { 2130 flags |= PCMCIA_IO_ALLOCATED; 2131 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 2132 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 2133 size, align, 0, 0, &ioaddr, &ioh)) { 2134 /* No room be able to be get. */ 2135 return 1; 2136 } 2137 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2138 (u_long) ioaddr, (u_long) size)); 2139 } 2140 #endif 2141 2142 pcihp->iot = iot; 2143 pcihp->ioh = ioh; 2144 pcihp->addr = ioaddr; 2145 pcihp->size = size; 2146 pcihp->flags = flags; 2147 2148 return 0; 2149 } 2150 2151 /* 2152 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2153 * struct pcmcia_io_handle *pcihp) 2154 * 2155 * This function only frees I/O region for pccard. 2156 * 2157 * XXX: The interface of this function is not very good, I believe. 2158 */ 2159 void 2160 pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2161 struct pcmcia_io_handle *pcihp) 2162 { 2163 #if !rbus 2164 bus_space_tag_t iot = pcihp->iot; 2165 #endif 2166 bus_space_handle_t ioh = pcihp->ioh; 2167 bus_size_t size = pcihp->size; 2168 2169 #if rbus 2170 struct pccbb_softc *sc = 2171 ((struct pcic_handle *)pch)->ph_parent; 2172 rbus_tag_t rb = sc->sc_rbus_iot; 2173 2174 rbus_space_free(rb, ioh, size, NULL); 2175 #else 2176 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 2177 bus_space_free(iot, ioh, size); 2178 else 2179 bus_space_unmap(iot, ioh, size); 2180 #endif 2181 } 2182 2183 /* 2184 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 2185 * bus_addr_t offset, bus_size_t size, 2186 * struct pcmcia_io_handle *pcihp, 2187 * int *windowp) 2188 * 2189 * This function maps the allocated I/O region to pccard. This function 2190 * never allocates any I/O region for pccard I/O area. I don't 2191 * understand why the original authors of pcmciabus separated alloc and 2192 * map. I believe the two must be unite. 2193 * 2194 * XXX: no wait timing control? 2195 */ 2196 int 2197 pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, bus_addr_t offset, 2198 bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp) 2199 { 2200 struct pcic_handle *ph = (struct pcic_handle *)pch; 2201 bus_addr_t ioaddr = pcihp->addr + offset; 2202 int i, win; 2203 #if defined CBB_DEBUG 2204 static const char *width_names[] = { "dynamic", "io8", "io16" }; 2205 #endif 2206 2207 /* Sanity check I/O handle. */ 2208 2209 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 2210 panic("pccbb_pcmcia_io_map iot is bogus"); 2211 } 2212 2213 /* XXX Sanity check offset/size. */ 2214 2215 win = -1; 2216 for (i = 0; i < PCIC_IO_WINS; i++) { 2217 if ((ph->ioalloc & (1 << i)) == 0) { 2218 win = i; 2219 ph->ioalloc |= (1 << i); 2220 break; 2221 } 2222 } 2223 2224 if (win == -1) { 2225 return 1; 2226 } 2227 2228 *windowp = win; 2229 2230 /* XXX this is pretty gross */ 2231 2232 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2233 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2234 2235 /* XXX wtf is this doing here? */ 2236 2237 #if 0 2238 printf(" port 0x%lx", (u_long) ioaddr); 2239 if (size > 1) { 2240 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2241 } 2242 #endif 2243 2244 ph->io[win].addr = ioaddr; 2245 ph->io[win].size = size; 2246 ph->io[win].width = width; 2247 2248 /* actual dirty register-value changing in the function below. */ 2249 pccbb_pcmcia_do_io_map(ph, win); 2250 2251 return 0; 2252 } 2253 2254 /* 2255 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2256 * 2257 * This function changes register-value to map I/O region for pccard. 2258 */ 2259 static void 2260 pccbb_pcmcia_do_io_map(struct pcic_handle *ph, int win) 2261 { 2262 static u_int8_t pcic_iowidth[3] = { 2263 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2264 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2265 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2266 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2267 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2268 }; 2269 2270 #define PCIC_SIA_START_LOW 0 2271 #define PCIC_SIA_START_HIGH 1 2272 #define PCIC_SIA_STOP_LOW 2 2273 #define PCIC_SIA_STOP_HIGH 3 2274 2275 int regbase_win = 0x8 + win * 0x04; 2276 u_int8_t ioctl, enable; 2277 2278 DPRINTF(("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx " 2279 "width %d\n", win, (unsigned long)ph->io[win].addr, 2280 (unsigned long)ph->io[win].size, ph->io[win].width * 8)); 2281 2282 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2283 ph->io[win].addr & 0xff); 2284 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2285 (ph->io[win].addr >> 8) & 0xff); 2286 2287 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2288 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2289 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2290 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2291 2292 ioctl = Pcic_read(ph, PCIC_IOCTL); 2293 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2294 switch (win) { 2295 case 0: 2296 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2297 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2298 PCIC_IOCTL_IO0_DATASIZE_MASK); 2299 ioctl |= pcic_iowidth[ph->io[win].width]; 2300 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2301 break; 2302 case 1: 2303 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2304 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2305 PCIC_IOCTL_IO1_DATASIZE_MASK); 2306 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2307 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2308 break; 2309 } 2310 Pcic_write(ph, PCIC_IOCTL, ioctl); 2311 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2312 #if defined(CBB_DEBUG) 2313 { 2314 u_int8_t start_low = 2315 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2316 u_int8_t start_high = 2317 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2318 u_int8_t stop_low = 2319 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2320 u_int8_t stop_high = 2321 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2322 printf("pccbb_pcmcia_do_io_map start %02x %02x, " 2323 "stop %02x %02x, ioctl %02x enable %02x\n", 2324 start_low, start_high, stop_low, stop_high, ioctl, enable); 2325 } 2326 #endif 2327 } 2328 2329 /* 2330 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2331 * 2332 * This function unmaps I/O region. No return value. 2333 */ 2334 STATIC void 2335 pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t pch, int win) 2336 { 2337 struct pcic_handle *ph = (struct pcic_handle *)pch; 2338 int reg; 2339 2340 if (win >= PCIC_IO_WINS || win < 0) { 2341 panic("pccbb_pcmcia_io_unmap: window out of range"); 2342 } 2343 2344 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2345 switch (win) { 2346 case 0: 2347 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2348 break; 2349 case 1: 2350 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2351 break; 2352 } 2353 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2354 2355 ph->ioalloc &= ~(1 << win); 2356 } 2357 2358 static int 2359 pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 2360 { 2361 u_int8_t stat; 2362 int i; 2363 2364 /* wait an initial 10ms for quick cards */ 2365 stat = Pcic_read(ph, PCIC_IF_STATUS); 2366 if (stat & PCIC_IF_STATUS_READY) 2367 return (0); 2368 pccbb_pcmcia_delay(ph, 10, "pccwr0"); 2369 for (i = 0; i < 50; i++) { 2370 stat = Pcic_read(ph, PCIC_IF_STATUS); 2371 if (stat & PCIC_IF_STATUS_READY) 2372 return (0); 2373 if ((stat & PCIC_IF_STATUS_CARDDETECT_MASK) != 2374 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2375 return (ENXIO); 2376 /* wait .1s (100ms) each iteration now */ 2377 pccbb_pcmcia_delay(ph, 100, "pccwr1"); 2378 } 2379 2380 printf("pccbb_pcmcia_wait_ready: ready never happened, status=%02x\n", stat); 2381 return (EWOULDBLOCK); 2382 } 2383 2384 /* 2385 * Perform long (msec order) delay. timo is in milliseconds. 2386 */ 2387 static void 2388 pccbb_pcmcia_delay(struct pcic_handle *ph, int timo, const char *wmesg) 2389 { 2390 #ifdef DIAGNOSTIC 2391 if (timo <= 0) 2392 panic("pccbb_pcmcia_delay: called with timeout %d", timo); 2393 if (!curlwp) 2394 panic("pccbb_pcmcia_delay: called in interrupt context"); 2395 #if 0 2396 if (!ph->event_thread) 2397 panic("pccbb_pcmcia_delay: no event thread"); 2398 #endif 2399 #endif 2400 DPRINTF(("pccbb_pcmcia_delay: \"%s\" %p, sleep %d ms\n", 2401 wmesg, ph->event_thread, timo)); 2402 tsleep(pccbb_pcmcia_delay, PWAIT, wmesg, roundup(timo * hz, 1000) / 1000); 2403 } 2404 2405 /* 2406 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2407 * 2408 * This function enables the card. All information is stored in 2409 * the first argument, pcmcia_chipset_handle_t. 2410 */ 2411 STATIC void 2412 pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2413 { 2414 struct pcic_handle *ph = (struct pcic_handle *)pch; 2415 struct pccbb_softc *sc = ph->ph_parent; 2416 pcireg_t spsr; 2417 int voltage; 2418 int win; 2419 u_int8_t power, intr; 2420 #ifdef DIAGNOSTIC 2421 int reg; 2422 #endif 2423 2424 /* this bit is mostly stolen from pcic_attach_card */ 2425 2426 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2427 2428 /* get card Vcc info */ 2429 spsr = 2430 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2431 CB_SOCKET_STAT); 2432 if (spsr & CB_SOCKET_STAT_5VCARD) { 2433 DPRINTF(("5V card\n")); 2434 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2435 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2436 DPRINTF(("3V card\n")); 2437 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2438 } else { 2439 DPRINTF(("?V card, 0x%x\n", spsr)); /* XXX */ 2440 return; 2441 } 2442 2443 /* disable interrupts; assert RESET */ 2444 intr = Pcic_read(ph, PCIC_INTR); 2445 intr &= PCIC_INTR_ENABLE; 2446 Pcic_write(ph, PCIC_INTR, intr); 2447 2448 /* zero out the address windows */ 2449 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2450 2451 /* power down the socket to reset it, clear the card reset pin */ 2452 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2453 2454 /* power off; assert output enable bit */ 2455 power = PCIC_PWRCTL_OE; 2456 Pcic_write(ph, PCIC_PWRCTL, power); 2457 2458 /* power up the socket */ 2459 if (pccbb_power(sc, voltage) == 0) 2460 return; 2461 2462 /* 2463 * Table 4-18 and figure 4-6 of the PC Card specifiction say: 2464 * Vcc Rising Time (Tpr) = 100ms (handled in pccbb_power() above) 2465 * RESET Width (Th (Hi-z RESET)) = 1ms 2466 * RESET Width (Tw (RESET)) = 10us 2467 * 2468 * some machines require some more time to be settled 2469 * for example old toshiba topic bridges! 2470 * (100ms is added here). 2471 */ 2472 pccbb_pcmcia_delay(ph, 200 + 1, "pccen1"); 2473 2474 /* negate RESET */ 2475 intr |= PCIC_INTR_RESET; 2476 Pcic_write(ph, PCIC_INTR, intr); 2477 2478 /* 2479 * RESET Setup Time (Tsu (RESET)) = 20ms 2480 */ 2481 pccbb_pcmcia_delay(ph, 20, "pccen2"); 2482 2483 #ifdef DIAGNOSTIC 2484 reg = Pcic_read(ph, PCIC_IF_STATUS); 2485 if ((reg & PCIC_IF_STATUS_POWERACTIVE) == 0) 2486 printf("pccbb_pcmcia_socket_enable: no power, status=%x\n", reg); 2487 #endif 2488 2489 /* wait for the chip to finish initializing */ 2490 if (pccbb_pcmcia_wait_ready(ph)) { 2491 #ifdef DIAGNOSTIC 2492 printf("pccbb_pcmcia_socket_enable: never became ready\n"); 2493 #endif 2494 /* XXX return a failure status?? */ 2495 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2496 Pcic_write(ph, PCIC_PWRCTL, 0); 2497 return; 2498 } 2499 2500 /* reinstall all the memory and io mappings */ 2501 for (win = 0; win < PCIC_MEM_WINS; ++win) 2502 if (ph->memalloc & (1 << win)) 2503 pccbb_pcmcia_do_mem_map(ph, win); 2504 for (win = 0; win < PCIC_IO_WINS; ++win) 2505 if (ph->ioalloc & (1 << win)) 2506 pccbb_pcmcia_do_io_map(ph, win); 2507 } 2508 2509 /* 2510 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2511 * 2512 * This function disables the card. All information is stored in 2513 * the first argument, pcmcia_chipset_handle_t. 2514 */ 2515 STATIC void 2516 pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t pch) 2517 { 2518 struct pcic_handle *ph = (struct pcic_handle *)pch; 2519 struct pccbb_softc *sc = ph->ph_parent; 2520 u_int8_t intr; 2521 2522 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2523 2524 /* disable interrupts; assert RESET */ 2525 intr = Pcic_read(ph, PCIC_INTR); 2526 intr &= PCIC_INTR_ENABLE; 2527 Pcic_write(ph, PCIC_INTR, intr); 2528 2529 /* zero out the address windows */ 2530 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2531 2532 /* power down the socket to reset it, clear the card reset pin */ 2533 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2534 2535 /* disable socket: negate output enable bit and power off */ 2536 Pcic_write(ph, PCIC_PWRCTL, 0); 2537 2538 /* 2539 * Vcc Falling Time (Tpf) = 300ms 2540 */ 2541 pccbb_pcmcia_delay(ph, 300, "pccwr1"); 2542 } 2543 2544 STATIC void 2545 pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t pch, int type) 2546 { 2547 struct pcic_handle *ph = (struct pcic_handle *)pch; 2548 u_int8_t intr; 2549 2550 /* set the card type */ 2551 2552 intr = Pcic_read(ph, PCIC_INTR); 2553 intr &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_CARDTYPE_MASK); 2554 if (type == PCMCIA_IFTYPE_IO) 2555 intr |= PCIC_INTR_CARDTYPE_IO; 2556 else 2557 intr |= PCIC_INTR_CARDTYPE_MEM; 2558 Pcic_write(ph, PCIC_INTR, intr); 2559 2560 DPRINTF(("%s: pccbb_pcmcia_socket_settype %02x type %s %02x\n", 2561 device_xname(((struct pccbb_softc *)ph->ph_parent)->sc_dev), 2562 ph->sock, ((type == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2563 } 2564 2565 /* 2566 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2567 * 2568 * This function detects whether a card is in the slot or not. 2569 * If a card is inserted, return 1. Otherwise, return 0. 2570 */ 2571 STATIC int 2572 pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch) 2573 { 2574 struct pcic_handle *ph = (struct pcic_handle *)pch; 2575 struct pccbb_softc *sc = ph->ph_parent; 2576 2577 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2578 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2579 } 2580 2581 #if 0 2582 STATIC int 2583 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2584 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2585 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2586 #endif 2587 /* 2588 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2589 * bus_size_t size, 2590 * struct pcmcia_mem_handle *pcmhp) 2591 * 2592 * This function only allocates memory region for pccard. This 2593 * function never maps the allocated region to pccard memory area. 2594 * 2595 * XXX: Why the argument of start address is not in? 2596 */ 2597 STATIC int 2598 pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 2599 struct pcmcia_mem_handle *pcmhp) 2600 { 2601 struct pcic_handle *ph = (struct pcic_handle *)pch; 2602 bus_space_handle_t memh; 2603 bus_addr_t addr; 2604 bus_size_t sizepg; 2605 struct pccbb_softc *sc = ph->ph_parent; 2606 #if rbus 2607 rbus_tag_t rb; 2608 #endif 2609 2610 /* Check that the card is still there. */ 2611 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2612 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2613 return 1; 2614 2615 /* out of sc->memh, allocate as many pages as necessary */ 2616 2617 /* convert size to PCIC pages */ 2618 /* 2619 * This is not enough; when the requested region is on the page 2620 * boundaries, this may calculate wrong result. 2621 */ 2622 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2623 #if 0 2624 if (sizepg > PCIC_MAX_MEM_PAGES) { 2625 return 1; 2626 } 2627 #endif 2628 2629 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2630 return 1; 2631 } 2632 2633 addr = 0; /* XXX gcc -Wuninitialized */ 2634 2635 #if rbus 2636 rb = sc->sc_rbus_memt; 2637 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2638 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2639 &addr, &memh)) { 2640 return 1; 2641 } 2642 #else 2643 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2644 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2645 0, /* boundary */ 2646 0, /* flags */ 2647 &addr, &memh)) { 2648 return 1; 2649 } 2650 #endif 2651 2652 DPRINTF(("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, " 2653 "realsize 0x%lx\n", (unsigned long)addr, (unsigned long)size, 2654 (unsigned long)sizepg * PCIC_MEM_PAGESIZE)); 2655 2656 pcmhp->memt = sc->sc_memt; 2657 pcmhp->memh = memh; 2658 pcmhp->addr = addr; 2659 pcmhp->size = size; 2660 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2661 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2662 pcmhp->mhandle = 0; 2663 /* No offset??? Funny. */ 2664 2665 return 0; 2666 } 2667 2668 /* 2669 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2670 * struct pcmcia_mem_handle *pcmhp) 2671 * 2672 * This function release the memory space allocated by the function 2673 * pccbb_pcmcia_mem_alloc(). 2674 */ 2675 STATIC void 2676 pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2677 struct pcmcia_mem_handle *pcmhp) 2678 { 2679 #if rbus 2680 struct pcic_handle *ph = (struct pcic_handle *)pch; 2681 struct pccbb_softc *sc = ph->ph_parent; 2682 2683 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2684 #else 2685 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2686 #endif 2687 } 2688 2689 /* 2690 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2691 * 2692 * This function release the memory space allocated by the function 2693 * pccbb_pcmcia_mem_alloc(). 2694 */ 2695 STATIC void 2696 pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2697 { 2698 int regbase_win; 2699 bus_addr_t phys_addr; 2700 bus_addr_t phys_end; 2701 2702 #define PCIC_SMM_START_LOW 0 2703 #define PCIC_SMM_START_HIGH 1 2704 #define PCIC_SMM_STOP_LOW 2 2705 #define PCIC_SMM_STOP_HIGH 3 2706 #define PCIC_CMA_LOW 4 2707 #define PCIC_CMA_HIGH 5 2708 2709 u_int8_t start_low, start_high = 0; 2710 u_int8_t stop_low, stop_high; 2711 u_int8_t off_low, off_high; 2712 u_int8_t mem_window; 2713 int reg; 2714 2715 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2716 int mem8 = 2717 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2718 || (kind == PCMCIA_MEM_ATTR); 2719 2720 regbase_win = 0x10 + win * 0x08; 2721 2722 phys_addr = ph->mem[win].addr; 2723 phys_end = phys_addr + ph->mem[win].size; 2724 2725 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2726 (unsigned long)phys_addr, (unsigned long)phys_end, 2727 (unsigned long)ph->mem[win].offset)); 2728 2729 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2730 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2731 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2732 2733 /* bit 19:12 */ 2734 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2735 /* bit 23:20 and bit 7 on */ 2736 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2737 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2738 /* bit 31:24, for 32-bit address */ 2739 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2740 2741 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2742 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2743 2744 if (((struct pccbb_softc *)ph-> 2745 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2746 Pcic_write(ph, 0x40 + win, mem_window); 2747 } 2748 2749 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2750 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2751 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2752 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2753 2754 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2755 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2756 2757 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2758 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2759 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2760 | ((kind == PCMCIA_MEM_ATTR) ? 2761 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2762 2763 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2764 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2765 2766 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2767 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2768 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2769 2770 #if defined(CBB_DEBUG) 2771 { 2772 int r1, r2, r3, r4, r5, r6, r7 = 0; 2773 2774 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2775 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2776 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2777 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2778 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2779 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2780 if (((struct pccbb_softc *)(ph-> 2781 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2782 r7 = Pcic_read(ph, 0x40 + win); 2783 } 2784 2785 printf("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2786 "%02x%02x", win, r1, r2, r3, r4, r5, r6); 2787 if (((struct pccbb_softc *)(ph-> 2788 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2789 printf(" %02x", r7); 2790 } 2791 printf("\n"); 2792 } 2793 #endif 2794 } 2795 2796 /* 2797 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2798 * bus_addr_t card_addr, bus_size_t size, 2799 * struct pcmcia_mem_handle *pcmhp, 2800 * bus_addr_t *offsetp, int *windowp) 2801 * 2802 * This function maps memory space allocated by the function 2803 * pccbb_pcmcia_mem_alloc(). 2804 */ 2805 STATIC int 2806 pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2807 bus_addr_t card_addr, bus_size_t size, struct pcmcia_mem_handle *pcmhp, 2808 bus_addr_t *offsetp, int *windowp) 2809 { 2810 struct pcic_handle *ph = (struct pcic_handle *)pch; 2811 bus_addr_t busaddr; 2812 long card_offset; 2813 int win; 2814 2815 /* Check that the card is still there. */ 2816 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2817 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2818 return 1; 2819 2820 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2821 if ((ph->memalloc & (1 << win)) == 0) { 2822 ph->memalloc |= (1 << win); 2823 break; 2824 } 2825 } 2826 2827 if (win == PCIC_MEM_WINS) { 2828 return 1; 2829 } 2830 2831 *windowp = win; 2832 2833 /* XXX this is pretty gross */ 2834 2835 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2836 panic("pccbb_pcmcia_mem_map memt is bogus"); 2837 } 2838 2839 busaddr = pcmhp->addr; 2840 2841 /* 2842 * compute the address offset to the pcmcia address space for the 2843 * pcic. this is intentionally signed. The masks and shifts below 2844 * will cause TRT to happen in the pcic registers. Deal with making 2845 * sure the address is aligned, and return the alignment offset. 2846 */ 2847 2848 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2849 card_addr -= *offsetp; 2850 2851 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2852 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2853 (u_long) card_addr)); 2854 2855 /* 2856 * include the offset in the size, and decrement size by one, since 2857 * the hw wants start/stop 2858 */ 2859 size += *offsetp - 1; 2860 2861 card_offset = (((long)card_addr) - ((long)busaddr)); 2862 2863 ph->mem[win].addr = busaddr; 2864 ph->mem[win].size = size; 2865 ph->mem[win].offset = card_offset; 2866 ph->mem[win].kind = kind; 2867 2868 pccbb_pcmcia_do_mem_map(ph, win); 2869 2870 return 0; 2871 } 2872 2873 /* 2874 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2875 * int window) 2876 * 2877 * This function unmaps memory space which mapped by the function 2878 * pccbb_pcmcia_mem_map(). 2879 */ 2880 STATIC void 2881 pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, int window) 2882 { 2883 struct pcic_handle *ph = (struct pcic_handle *)pch; 2884 int reg; 2885 2886 if (window >= PCIC_MEM_WINS) { 2887 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2888 } 2889 2890 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2891 reg &= ~(1 << window); 2892 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2893 2894 ph->memalloc &= ~(1 << window); 2895 } 2896 2897 #if defined PCCBB_PCMCIA_POLL 2898 struct pccbb_poll_str { 2899 void *arg; 2900 int (*func)(void *); 2901 int level; 2902 struct pcic_handle *ph; 2903 int count; 2904 int num; 2905 struct callout poll_ch; 2906 }; 2907 2908 static struct pccbb_poll_str pccbb_poll[10]; 2909 static int pccbb_poll_n = 0; 2910 2911 static void pccbb_pcmcia_poll(void *arg); 2912 2913 static void 2914 pccbb_pcmcia_poll(void *arg) 2915 { 2916 struct pccbb_poll_str *poll = arg; 2917 struct pcic_handle *ph = poll->ph; 2918 struct pccbb_softc *sc = ph->sc; 2919 int s; 2920 u_int32_t spsr; /* socket present-state reg */ 2921 2922 callout_reset(&poll->poll_ch, hz * 2, pccbb_pcmcia_poll, arg); 2923 switch (poll->level) { 2924 case IPL_NET: 2925 s = splnet(); 2926 break; 2927 case IPL_BIO: 2928 s = splbio(); 2929 break; 2930 case IPL_TTY: /* fallthrough */ 2931 default: 2932 s = spltty(); 2933 break; 2934 } 2935 2936 spsr = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2937 CB_SOCKET_STAT); 2938 2939 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2940 if (!(spsr & 0x40)) /* CINT low */ 2941 #else 2942 if (1) 2943 #endif 2944 { 2945 if ((*poll->func) (poll->arg) > 0) { 2946 ++poll->count; 2947 /* printf("intr: reported from poller, 0x%x\n", spsr); */ 2948 #if defined LEVEL2 2949 } else { 2950 printf("intr: miss! 0x%x\n", spsr); 2951 #endif 2952 } 2953 } 2954 splx(s); 2955 } 2956 #endif /* defined CB_PCMCIA_POLL */ 2957 2958 /* 2959 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2960 * struct pcmcia_function *pf, 2961 * int ipl, 2962 * int (*func)(void *), 2963 * void *arg); 2964 * 2965 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2966 */ 2967 STATIC void * 2968 pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2969 struct pcmcia_function *pf, int ipl, int (*func)(void *), void *arg) 2970 { 2971 struct pcic_handle *ph = (struct pcic_handle *)pch; 2972 struct pccbb_softc *sc = ph->ph_parent; 2973 2974 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2975 /* what should I do? */ 2976 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2977 DPRINTF(("%s does not provide edge nor pulse " 2978 "interrupt\n", device_xname(sc->sc_dev))); 2979 return NULL; 2980 } 2981 /* 2982 * XXX Noooooo! The interrupt flag must set properly!! 2983 * dumb pcmcia driver!! 2984 */ 2985 } 2986 2987 return pccbb_intr_establish(sc, 0, ipl, func, arg); 2988 } 2989 2990 /* 2991 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2992 * void *ih) 2993 * 2994 * This function disables PC-Card interrupt. 2995 */ 2996 STATIC void 2997 pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 2998 { 2999 struct pcic_handle *ph = (struct pcic_handle *)pch; 3000 struct pccbb_softc *sc = ph->ph_parent; 3001 3002 pccbb_intr_disestablish(sc, ih); 3003 } 3004 3005 #if rbus 3006 /* 3007 * static int 3008 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 3009 * bus_addr_t addr, bus_size_t size, 3010 * bus_addr_t mask, bus_size_t align, 3011 * int flags, bus_addr_t *addrp; 3012 * bus_space_handle_t *bshp) 3013 * 3014 * This function allocates a portion of memory or io space for 3015 * clients. This function is called from CardBus card drivers. 3016 */ 3017 static int 3018 pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 3019 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 3020 int flags, bus_addr_t *addrp, bus_space_handle_t *bshp) 3021 { 3022 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 3023 3024 DPRINTF(("pccbb_rbus_cb_space_alloc: addr 0x%lx, size 0x%lx, " 3025 "mask 0x%lx, align 0x%lx\n", (unsigned long)addr, 3026 (unsigned long)size, (unsigned long)mask, (unsigned long)align)); 3027 3028 if (align == 0) { 3029 align = size; 3030 } 3031 3032 if (rb->rb_bt == sc->sc_memt) { 3033 if (align < 16) { 3034 return 1; 3035 } 3036 /* 3037 * XXX: align more than 0x1000 to avoid overwrapping 3038 * memory windows for two or more devices. 0x1000 3039 * means memory window's granularity. 3040 * 3041 * Two or more devices should be able to share same 3042 * memory window region. However, overrapping memory 3043 * window is not good because some devices, such as 3044 * 3Com 3C575[BC], have a broken address decoder and 3045 * intrude other's memory region. 3046 */ 3047 if (align < 0x1000) { 3048 align = 0x1000; 3049 } 3050 } else if (rb->rb_bt == sc->sc_iot) { 3051 if (align < 4) { 3052 return 1; 3053 } 3054 /* XXX: hack for avoiding ISA image */ 3055 if (mask < 0x0100) { 3056 mask = 0x3ff; 3057 addr = 0x300; 3058 } 3059 3060 } else { 3061 DPRINTF(("pccbb_rbus_cb_space_alloc: Bus space tag 0x%lx is " 3062 "NOT used. io: 0x%lx, mem: 0x%lx\n", 3063 (unsigned long)rb->rb_bt, (unsigned long)sc->sc_iot, 3064 (unsigned long)sc->sc_memt)); 3065 return 1; 3066 /* XXX: panic here? */ 3067 } 3068 3069 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 3070 aprint_normal_dev(sc->sc_dev, "<rbus> no bus space\n"); 3071 return 1; 3072 } 3073 3074 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 3075 3076 return 0; 3077 } 3078 3079 /* 3080 * static int 3081 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 3082 * bus_space_handle_t *bshp, bus_size_t size); 3083 * 3084 * This function is called from CardBus card drivers. 3085 */ 3086 static int 3087 pccbb_rbus_cb_space_free(cardbus_chipset_tag_t ct, rbus_tag_t rb, 3088 bus_space_handle_t bsh, bus_size_t size) 3089 { 3090 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 3091 bus_space_tag_t bt = rb->rb_bt; 3092 3093 pccbb_close_win(sc, bt, bsh, size); 3094 3095 if (bt == sc->sc_memt) { 3096 } else if (bt == sc->sc_iot) { 3097 } else { 3098 return 1; 3099 /* XXX: panic here? */ 3100 } 3101 3102 return rbus_space_free(rb, bsh, size, NULL); 3103 } 3104 #endif /* rbus */ 3105 3106 #if rbus 3107 3108 static int 3109 pccbb_open_win(struct pccbb_softc *sc, bus_space_tag_t bst, bus_addr_t addr, 3110 bus_size_t size, bus_space_handle_t bsh, int flags) 3111 { 3112 struct pccbb_win_chain_head *head; 3113 bus_addr_t align; 3114 3115 head = &sc->sc_iowindow; 3116 align = 0x04; 3117 if (sc->sc_memt == bst) { 3118 head = &sc->sc_memwindow; 3119 align = 0x1000; 3120 DPRINTF(("using memory window, 0x%lx 0x%lx 0x%lx\n\n", 3121 (unsigned long)sc->sc_iot, (unsigned long)sc->sc_memt, 3122 (unsigned long)bst)); 3123 } 3124 3125 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 3126 aprint_error_dev(sc->sc_dev, 3127 "pccbb_open_win: %s winlist insert failed\n", 3128 (head == &sc->sc_memwindow) ? "mem" : "io"); 3129 } 3130 pccbb_winset(align, sc, bst); 3131 3132 return 0; 3133 } 3134 3135 static int 3136 pccbb_close_win(struct pccbb_softc *sc, bus_space_tag_t bst, 3137 bus_space_handle_t bsh, bus_size_t size) 3138 { 3139 struct pccbb_win_chain_head *head; 3140 bus_addr_t align; 3141 3142 head = &sc->sc_iowindow; 3143 align = 0x04; 3144 if (sc->sc_memt == bst) { 3145 head = &sc->sc_memwindow; 3146 align = 0x1000; 3147 } 3148 3149 if (pccbb_winlist_delete(head, bsh, size)) { 3150 aprint_error_dev(sc->sc_dev, 3151 "pccbb_close_win: %s winlist delete failed\n", 3152 (head == &sc->sc_memwindow) ? "mem" : "io"); 3153 } 3154 pccbb_winset(align, sc, bst); 3155 3156 return 0; 3157 } 3158 3159 static int 3160 pccbb_winlist_insert(struct pccbb_win_chain_head *head, bus_addr_t start, 3161 bus_size_t size, bus_space_handle_t bsh, int flags) 3162 { 3163 struct pccbb_win_chain *chainp, *elem; 3164 3165 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 3166 M_NOWAIT)) == NULL) 3167 return (1); /* fail */ 3168 3169 elem->wc_start = start; 3170 elem->wc_end = start + (size - 1); 3171 elem->wc_handle = bsh; 3172 elem->wc_flags = flags; 3173 3174 TAILQ_FOREACH(chainp, head, wc_list) { 3175 if (chainp->wc_end >= start) 3176 break; 3177 } 3178 if (chainp != NULL) 3179 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 3180 else 3181 TAILQ_INSERT_TAIL(head, elem, wc_list); 3182 return (0); 3183 } 3184 3185 static int 3186 pccbb_winlist_delete(struct pccbb_win_chain_head *head, bus_space_handle_t bsh, 3187 bus_size_t size) 3188 { 3189 struct pccbb_win_chain *chainp; 3190 3191 TAILQ_FOREACH(chainp, head, wc_list) { 3192 if (memcmp(&chainp->wc_handle, &bsh, sizeof(bsh)) == 0) 3193 break; 3194 } 3195 if (chainp == NULL) 3196 return 1; /* fail: no candidate to remove */ 3197 3198 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 3199 printf("pccbb_winlist_delete: window 0x%lx size " 3200 "inconsistent: 0x%lx, 0x%lx\n", 3201 (unsigned long)chainp->wc_start, 3202 (unsigned long)(chainp->wc_end - chainp->wc_start), 3203 (unsigned long)(size - 1)); 3204 return 1; 3205 } 3206 3207 TAILQ_REMOVE(head, chainp, wc_list); 3208 free(chainp, M_DEVBUF); 3209 3210 return 0; 3211 } 3212 3213 static void 3214 pccbb_winset(bus_addr_t align, struct pccbb_softc *sc, bus_space_tag_t bst) 3215 { 3216 pci_chipset_tag_t pc; 3217 pcitag_t tag; 3218 bus_addr_t mask = ~(align - 1); 3219 struct { 3220 cardbusreg_t win_start; 3221 cardbusreg_t win_limit; 3222 int win_flags; 3223 } win[2]; 3224 struct pccbb_win_chain *chainp; 3225 int offs; 3226 3227 win[0].win_start = win[1].win_start = 0xffffffff; 3228 win[0].win_limit = win[1].win_limit = 0; 3229 win[0].win_flags = win[1].win_flags = 0; 3230 3231 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3232 offs = PCI_CB_IOBASE0; 3233 if (sc->sc_memt == bst) { 3234 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3235 offs = PCI_CB_MEMBASE0; 3236 } 3237 3238 if (chainp != NULL) { 3239 win[0].win_start = chainp->wc_start & mask; 3240 win[0].win_limit = chainp->wc_end & mask; 3241 win[0].win_flags = chainp->wc_flags; 3242 chainp = TAILQ_NEXT(chainp, wc_list); 3243 } 3244 3245 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3246 if (win[1].win_start == 0xffffffff) { 3247 /* window 1 is not used */ 3248 if ((win[0].win_flags == chainp->wc_flags) && 3249 (win[0].win_limit + align >= 3250 (chainp->wc_start & mask))) { 3251 /* concatenate */ 3252 win[0].win_limit = chainp->wc_end & mask; 3253 } else { 3254 /* make new window */ 3255 win[1].win_start = chainp->wc_start & mask; 3256 win[1].win_limit = chainp->wc_end & mask; 3257 win[1].win_flags = chainp->wc_flags; 3258 } 3259 continue; 3260 } 3261 3262 /* Both windows are engaged. */ 3263 if (win[0].win_flags == win[1].win_flags) { 3264 /* same flags */ 3265 if (win[0].win_flags == chainp->wc_flags) { 3266 if (win[1].win_start - (win[0].win_limit + 3267 align) < 3268 (chainp->wc_start & mask) - 3269 ((chainp->wc_end & mask) + align)) { 3270 /* 3271 * merge window 0 and 1, and set win1 3272 * to chainp 3273 */ 3274 win[0].win_limit = win[1].win_limit; 3275 win[1].win_start = 3276 chainp->wc_start & mask; 3277 win[1].win_limit = 3278 chainp->wc_end & mask; 3279 } else { 3280 win[1].win_limit = 3281 chainp->wc_end & mask; 3282 } 3283 } else { 3284 /* different flags */ 3285 3286 /* concatenate win0 and win1 */ 3287 win[0].win_limit = win[1].win_limit; 3288 /* allocate win[1] to new space */ 3289 win[1].win_start = chainp->wc_start & mask; 3290 win[1].win_limit = chainp->wc_end & mask; 3291 win[1].win_flags = chainp->wc_flags; 3292 } 3293 } else { 3294 /* the flags of win[0] and win[1] is different */ 3295 if (win[0].win_flags == chainp->wc_flags) { 3296 win[0].win_limit = chainp->wc_end & mask; 3297 /* 3298 * XXX this creates overlapping windows, so 3299 * what should the poor bridge do if one is 3300 * cachable, and the other is not? 3301 */ 3302 aprint_error_dev(sc->sc_dev, 3303 "overlapping windows\n"); 3304 } else { 3305 win[1].win_limit = chainp->wc_end & mask; 3306 } 3307 } 3308 } 3309 3310 pc = sc->sc_pc; 3311 tag = sc->sc_tag; 3312 pci_conf_write(pc, tag, offs, win[0].win_start); 3313 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3314 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3315 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3316 DPRINTF(("--pccbb_winset: win0 [0x%lx, 0x%lx), win1 [0x%lx, 0x%lx)\n", 3317 (unsigned long)pci_conf_read(pc, tag, offs), 3318 (unsigned long)pci_conf_read(pc, tag, offs + 4) + align, 3319 (unsigned long)pci_conf_read(pc, tag, offs + 8), 3320 (unsigned long)pci_conf_read(pc, tag, offs + 12) + align)); 3321 3322 if (bst == sc->sc_memt) { 3323 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BRIDGE_CONTROL_REG); 3324 3325 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 3326 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 3327 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3328 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 3329 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3330 pci_conf_write(pc, tag, PCI_BRIDGE_CONTROL_REG, bcr); 3331 } 3332 } 3333 3334 #endif /* rbus */ 3335 3336 static bool 3337 pccbb_suspend(device_t dv PMF_FN_ARGS) 3338 { 3339 struct pccbb_softc *sc = device_private(dv); 3340 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3341 bus_space_handle_t base_memh = sc->sc_base_memh; 3342 pcireg_t reg; 3343 3344 if (sc->sc_pil_intr_enable) 3345 (void)pccbbintr_function(sc); 3346 sc->sc_pil_intr_enable = 0; 3347 3348 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3349 /* Disable interrupts. */ 3350 reg &= ~(CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER); 3351 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3352 /* XXX joerg Disable power to the socket? */ 3353 3354 /* XXX flush PCI write */ 3355 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3356 3357 /* reset interrupt */ 3358 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, 3359 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT)); 3360 /* XXX flush PCI write */ 3361 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3362 3363 if (sc->sc_ih != NULL) { 3364 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 3365 sc->sc_ih = NULL; 3366 } 3367 3368 return true; 3369 } 3370 3371 static bool 3372 pccbb_resume(device_t dv PMF_FN_ARGS) 3373 { 3374 struct pccbb_softc *sc = device_private(dv); 3375 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3376 bus_space_handle_t base_memh = sc->sc_base_memh; 3377 pcireg_t reg; 3378 3379 pccbb_chipinit(sc); 3380 pccbb_intrinit(sc); 3381 /* setup memory and io space window for CB */ 3382 pccbb_winset(0x1000, sc, sc->sc_memt); 3383 pccbb_winset(0x04, sc, sc->sc_iot); 3384 3385 /* CSC Interrupt: Card detect interrupt on */ 3386 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3387 /* Card detect intr is turned on. */ 3388 reg |= CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; 3389 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3390 /* reset interrupt */ 3391 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3392 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3393 3394 /* 3395 * check for card insertion or removal during suspend period. 3396 * XXX: the code can't cope with card swap (remove then 3397 * insert). how can we detect such situation? 3398 */ 3399 (void)pccbbintr(sc); 3400 3401 sc->sc_pil_intr_enable = 1; 3402 3403 return true; 3404 } 3405
Indexes created Fri Sep 26 08:10:20 GMT 2025