pccbb.c revision 1.175
1 /* $NetBSD: pccbb.c,v 1.175 2008/06/26 17:22:23 drochner Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: pccbb.c,v 1.175 2008/06/26 17:22:23 drochner Exp $"); 35 36 /* 37 #define CBB_DEBUG 38 #define SHOW_REGS 39 */ 40 41 /* 42 * BROKEN! 43 #define PCCBB_PCMCIA_POLL 44 #define CB_PCMCIA_POLL 45 #define CB_PCMCIA_POLL_ONLY 46 #define LEVEL2 47 */ 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/kernel.h> 52 #include <sys/errno.h> 53 #include <sys/ioctl.h> 54 #include <sys/reboot.h> /* for bootverbose */ 55 #include <sys/syslog.h> 56 #include <sys/device.h> 57 #include <sys/malloc.h> 58 #include <sys/proc.h> 59 60 #include <sys/intr.h> 61 #include <sys/bus.h> 62 63 #include <dev/pci/pcivar.h> 64 #include <dev/pci/pcireg.h> 65 #include <dev/pci/pcidevs.h> 66 67 #include <dev/pci/pccbbreg.h> 68 69 #include <dev/cardbus/cardslotvar.h> 70 71 #include <dev/cardbus/cardbusvar.h> 72 73 #include <dev/pcmcia/pcmciareg.h> 74 #include <dev/pcmcia/pcmciavar.h> 75 76 #include <dev/ic/i82365reg.h> 77 #include <dev/pci/pccbbvar.h> 78 79 #ifndef __NetBSD_Version__ 80 struct cfdriver cbb_cd = { 81 NULL, "cbb", DV_DULL 82 }; 83 #endif 84 85 #ifdef CBB_DEBUG 86 #define DPRINTF(x) printf x 87 #define STATIC 88 #else 89 #define DPRINTF(x) 90 #define STATIC static 91 #endif 92 93 int pccbb_burstup = 1; 94 95 /* 96 * delay_ms() is wait in milliseconds. It should be used instead 97 * of delay() if you want to wait more than 1 ms. 98 */ 99 static inline void 100 delay_ms(int millis, void *param) 101 { 102 if (cold) 103 delay(millis * 1000); 104 else 105 tsleep(param, PWAIT, "pccbb", MAX(2, hz * millis / 1000)); 106 } 107 108 int pcicbbmatch(device_t, struct cfdata *, void *); 109 void pccbbattach(device_t, device_t, void *); 110 int pccbbdetach(device_t, int); 111 int pccbbintr(void *); 112 static void pci113x_insert(void *); 113 static int pccbbintr_function(struct pccbb_softc *); 114 115 static int pccbb_detect_card(struct pccbb_softc *); 116 117 static void pccbb_pcmcia_write(struct pccbb_softc *, int, u_int8_t); 118 static u_int8_t pccbb_pcmcia_read(struct pccbb_softc *, int); 119 #define Pcic_read(ph, reg) pccbb_pcmcia_read((ph)->ph_parent, (reg)) 120 #define Pcic_write(ph, reg, val) pccbb_pcmcia_write((ph)->ph_parent, \ 121 (reg), (val)) 122 123 STATIC int cb_reset(struct pccbb_softc *); 124 STATIC int cb_detect_voltage(struct pccbb_softc *); 125 STATIC int cbbprint(void *, const char *); 126 127 static int cb_chipset(u_int32_t, int *); 128 STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *, 129 struct pcmciabus_attach_args *); 130 #if 0 131 STATIC void pccbb_pcmcia_attach_card(struct pcic_handle *); 132 STATIC void pccbb_pcmcia_detach_card(struct pcic_handle *, int); 133 STATIC void pccbb_pcmcia_deactivate_card(struct pcic_handle *); 134 #endif 135 136 STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int); 137 STATIC int pccbb_power(struct pccbb_softc *sc, int); 138 STATIC int pccbb_power_ct(cardbus_chipset_tag_t, int); 139 STATIC int pccbb_cardenable(struct pccbb_softc * sc, int function); 140 #if !rbus 141 static int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 142 static int pccbb_io_close(cardbus_chipset_tag_t, int); 143 static int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 144 static int pccbb_mem_close(cardbus_chipset_tag_t, int); 145 #endif /* !rbus */ 146 static void *pccbb_intr_establish(struct pccbb_softc *, 147 cardbus_intr_line_t irq, int level, int (*ih) (void *), void *sc); 148 static void pccbb_intr_disestablish(struct pccbb_softc *, void *ih); 149 150 static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t, 151 cardbus_intr_line_t irq, int level, int (*ih) (void *), void *sc); 152 static void pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih); 153 154 static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t, int, int); 155 static void pccbb_free_tag(cardbus_chipset_tag_t, cardbustag_t); 156 static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t, cardbustag_t, int); 157 static void pccbb_conf_write(cardbus_chipset_tag_t, cardbustag_t, int, 158 cardbusreg_t); 159 static void pccbb_chipinit(struct pccbb_softc *); 160 static void pccbb_intrinit(struct pccbb_softc *); 161 162 STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 163 struct pcmcia_mem_handle *); 164 STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t, 165 struct pcmcia_mem_handle *); 166 STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 167 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *); 168 STATIC void pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t, int); 169 STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 170 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 171 STATIC void pccbb_pcmcia_io_free(pcmcia_chipset_handle_t, 172 struct pcmcia_io_handle *); 173 STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 174 bus_size_t, struct pcmcia_io_handle *, int *); 175 STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t, int); 176 STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t, 177 struct pcmcia_function *, int, int (*)(void *), void *); 178 STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t, void *); 179 STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t); 180 STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t); 181 STATIC void pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t, int); 182 STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch); 183 184 static int pccbb_pcmcia_wait_ready(struct pcic_handle *); 185 static void pccbb_pcmcia_delay(struct pcic_handle *, int, const char *); 186 187 static void pccbb_pcmcia_do_io_map(struct pcic_handle *, int); 188 static void pccbb_pcmcia_do_mem_map(struct pcic_handle *, int); 189 190 /* bus-space allocation and deallocation functions */ 191 #if rbus 192 193 static int pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t, rbus_tag_t, 194 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 195 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp); 196 static int pccbb_rbus_cb_space_free(cardbus_chipset_tag_t, rbus_tag_t, 197 bus_space_handle_t, bus_size_t); 198 199 #endif /* rbus */ 200 201 #if rbus 202 203 static int pccbb_open_win(struct pccbb_softc *, bus_space_tag_t, 204 bus_addr_t, bus_size_t, bus_space_handle_t, int flags); 205 static int pccbb_close_win(struct pccbb_softc *, bus_space_tag_t, 206 bus_space_handle_t, bus_size_t); 207 static int pccbb_winlist_insert(struct pccbb_win_chain_head *, bus_addr_t, 208 bus_size_t, bus_space_handle_t, int); 209 static int pccbb_winlist_delete(struct pccbb_win_chain_head *, 210 bus_space_handle_t, bus_size_t); 211 static void pccbb_winset(bus_addr_t align, struct pccbb_softc *, 212 bus_space_tag_t); 213 void pccbb_winlist_show(struct pccbb_win_chain *); 214 215 #endif /* rbus */ 216 217 /* for config_defer */ 218 static void pccbb_pci_callback(device_t); 219 220 static bool pccbb_suspend(device_t PMF_FN_PROTO); 221 static bool pccbb_resume(device_t PMF_FN_PROTO); 222 223 #if defined SHOW_REGS 224 static void cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, 225 bus_space_tag_t memt, bus_space_handle_t memh); 226 #endif 227 228 CFATTACH_DECL_NEW(cbb_pci, sizeof(struct pccbb_softc), 229 pcicbbmatch, pccbbattach, pccbbdetach, NULL); 230 231 static const struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 232 pccbb_pcmcia_mem_alloc, 233 pccbb_pcmcia_mem_free, 234 pccbb_pcmcia_mem_map, 235 pccbb_pcmcia_mem_unmap, 236 pccbb_pcmcia_io_alloc, 237 pccbb_pcmcia_io_free, 238 pccbb_pcmcia_io_map, 239 pccbb_pcmcia_io_unmap, 240 pccbb_pcmcia_intr_establish, 241 pccbb_pcmcia_intr_disestablish, 242 pccbb_pcmcia_socket_enable, 243 pccbb_pcmcia_socket_disable, 244 pccbb_pcmcia_socket_settype, 245 pccbb_pcmcia_card_detect 246 }; 247 248 #if rbus 249 static const struct cardbus_functions pccbb_funcs = { 250 pccbb_rbus_cb_space_alloc, 251 pccbb_rbus_cb_space_free, 252 pccbb_cb_intr_establish, 253 pccbb_cb_intr_disestablish, 254 pccbb_ctrl, 255 pccbb_power_ct, 256 pccbb_make_tag, 257 pccbb_free_tag, 258 pccbb_conf_read, 259 pccbb_conf_write, 260 }; 261 #else 262 static const struct cardbus_functions pccbb_funcs = { 263 pccbb_ctrl, 264 pccbb_power_ct, 265 pccbb_mem_open, 266 pccbb_mem_close, 267 pccbb_io_open, 268 pccbb_io_close, 269 pccbb_cb_intr_establish, 270 pccbb_cb_intr_disestablish, 271 pccbb_make_tag, 272 pccbb_conf_read, 273 pccbb_conf_write, 274 }; 275 #endif 276 277 int 278 pcicbbmatch(device_t parent, struct cfdata *match, void *aux) 279 { 280 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 281 282 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 283 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 284 PCI_INTERFACE(pa->pa_class) == 0) { 285 return 1; 286 } 287 288 return 0; 289 } 290 291 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 292 | ((prod) << PCI_PRODUCT_SHIFT)) 293 294 const struct yenta_chipinfo { 295 pcireg_t yc_id; /* vendor tag | product tag */ 296 int yc_chiptype; 297 int yc_flags; 298 } yc_chipsets[] = { 299 /* Texas Instruments chips */ 300 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 301 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 302 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 303 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 304 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI125X, 305 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 306 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 307 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 308 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 309 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 310 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 311 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 312 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI125X, 313 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 314 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI125X, 315 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 316 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 317 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 318 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 319 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 320 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI1420, 321 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 322 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI125X, 323 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 324 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 325 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 326 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1520), CB_TI12XX, 327 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 328 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4410YENTA), CB_TI12XX, 329 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 330 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4520YENTA), CB_TI12XX, 331 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 332 333 /* Ricoh chips */ 334 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 335 PCCBB_PCMCIA_MEM_32}, 336 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 337 PCCBB_PCMCIA_MEM_32}, 338 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 339 PCCBB_PCMCIA_MEM_32}, 340 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 341 PCCBB_PCMCIA_MEM_32}, 342 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 343 PCCBB_PCMCIA_MEM_32}, 344 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 345 PCCBB_PCMCIA_MEM_32}, 346 347 /* Toshiba products */ 348 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 349 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 350 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 351 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 352 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 353 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 354 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 355 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 356 357 /* Cirrus Logic products */ 358 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 359 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 360 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 361 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 362 363 /* O2 Micro products */ 364 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6729), 365 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 366 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6730), 367 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 368 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6832), 369 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 370 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6836), 371 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 372 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6872), 373 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 374 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6922), 375 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 376 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6933), 377 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 378 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6972), 379 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 380 381 /* sentinel, or Generic chip */ 382 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 383 }; 384 385 static int 386 cb_chipset(u_int32_t pci_id, int *flagp) 387 { 388 const struct yenta_chipinfo *yc; 389 390 /* Loop over except the last default entry. */ 391 for (yc = yc_chipsets; yc < yc_chipsets + 392 __arraycount(yc_chipsets) - 1; yc++) 393 if (pci_id == yc->yc_id) 394 break; 395 396 if (flagp != NULL) 397 *flagp = yc->yc_flags; 398 399 return (yc->yc_chiptype); 400 } 401 402 void 403 pccbbattach(device_t parent, device_t self, void *aux) 404 { 405 struct pccbb_softc *sc = device_private(self); 406 struct pci_attach_args *pa = aux; 407 pci_chipset_tag_t pc = pa->pa_pc; 408 pcireg_t busreg, reg, sock_base; 409 bus_addr_t sockbase; 410 char devinfo[256]; 411 int flags; 412 413 #ifdef __HAVE_PCCBB_ATTACH_HOOK 414 pccbb_attach_hook(parent, self, pa); 415 #endif 416 417 sc->sc_dev = self; 418 419 callout_init(&sc->sc_insert_ch, 0); 420 callout_setfunc(&sc->sc_insert_ch, pci113x_insert, sc); 421 422 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 423 424 aprint_naive("\n"); 425 426 pci_devinfo(pa->pa_id, 0, 0, devinfo, sizeof(devinfo)); 427 aprint_normal(": %s (rev. 0x%02x)", devinfo, 428 PCI_REVISION(pa->pa_class)); 429 DPRINTF((" (chipflags %x)", flags)); 430 aprint_normal("\n"); 431 432 TAILQ_INIT(&sc->sc_memwindow); 433 TAILQ_INIT(&sc->sc_iowindow); 434 435 #if rbus 436 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 437 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 438 439 #if 0 440 printf("pa->pa_memt: %08x vs rbus_mem->rb_bt: %08x\n", 441 pa->pa_memt, sc->sc_rbus_memt->rb_bt); 442 #endif 443 #endif /* rbus */ 444 445 sc->sc_flags &= ~CBB_MEMHMAPPED; 446 447 /* 448 * MAP socket registers and ExCA registers on memory-space 449 * When no valid address is set on socket base registers (on pci 450 * config space), get it not polite way. 451 */ 452 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 453 454 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 455 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 456 /* The address must be valid. */ 457 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 458 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, &sc->sc_base_size)) { 459 aprint_error_dev(self, 460 "can't map socket base address 0x%lx\n", 461 (unsigned long)sock_base); 462 /* 463 * I think it's funny: socket base registers must be 464 * mapped on memory space, but ... 465 */ 466 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 467 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 468 &sc->sc_base_size)) { 469 aprint_error_dev(self, 470 "can't map socket base address" 471 " 0x%lx: io mode\n", 472 (unsigned long)sockbase); 473 /* give up... allocate reg space via rbus. */ 474 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 475 } else 476 sc->sc_flags |= CBB_MEMHMAPPED; 477 } else { 478 DPRINTF(("%s: socket base address 0x%lx\n", 479 device_xname(self), 480 (unsigned long)sockbase)); 481 sc->sc_flags |= CBB_MEMHMAPPED; 482 } 483 } 484 485 sc->sc_mem_start = 0; /* XXX */ 486 sc->sc_mem_end = 0xffffffff; /* XXX */ 487 488 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 489 490 /* pccbb_machdep.c end */ 491 492 #if defined CBB_DEBUG 493 { 494 static const char *intrname[] = { "NON", "A", "B", "C", "D" }; 495 aprint_debug_dev(self, "intrpin %s, intrtag %d\n", 496 intrname[pa->pa_intrpin], pa->pa_intrline); 497 } 498 #endif 499 500 /* setup softc */ 501 sc->sc_pc = pc; 502 sc->sc_iot = pa->pa_iot; 503 sc->sc_memt = pa->pa_memt; 504 sc->sc_dmat = pa->pa_dmat; 505 sc->sc_tag = pa->pa_tag; 506 sc->sc_function = pa->pa_function; 507 508 memcpy(&sc->sc_pa, pa, sizeof(*pa)); 509 510 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 511 512 /* Disable legacy register mapping. */ 513 switch (sc->sc_chipset) { 514 case CB_RX5C46X: /* fallthrough */ 515 #if 0 516 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 517 case CB_RX5C47X: 518 #endif 519 /* 520 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 521 * cannot be disabled by substituting 0 into PCI_LEGACY 522 * register. Ricoh CardBus bridges have special bits on Bridge 523 * control reg (addr 0x3e on PCI config space). 524 */ 525 reg = pci_conf_read(pc, pa->pa_tag, PCI_BRIDGE_CONTROL_REG); 526 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 527 pci_conf_write(pc, pa->pa_tag, PCI_BRIDGE_CONTROL_REG, reg); 528 break; 529 530 default: 531 /* XXX I don't know proper way to kill legacy I/O. */ 532 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 533 break; 534 } 535 536 if (!pmf_device_register(self, pccbb_suspend, pccbb_resume)) 537 aprint_error_dev(self, "couldn't establish power handler\n"); 538 539 config_defer(self, pccbb_pci_callback); 540 } 541 542 int 543 pccbbdetach(device_t self, int flags) 544 { 545 struct pccbb_softc *sc = device_private(self); 546 pci_chipset_tag_t pc = sc->sc_pa.pa_pc; 547 bus_space_tag_t bmt = sc->sc_base_memt; 548 bus_space_handle_t bmh = sc->sc_base_memh; 549 uint32_t sockmask; 550 int rc; 551 552 if ((rc = config_detach_children(self, flags)) != 0) 553 return rc; 554 555 if (!LIST_EMPTY(&sc->sc_pil)) { 556 panic("%s: interrupt handlers still registered", 557 device_xname(self)); 558 return EBUSY; 559 } 560 561 if (sc->sc_ih != NULL) { 562 pci_intr_disestablish(pc, sc->sc_ih); 563 sc->sc_ih = NULL; 564 } 565 566 /* CSC Interrupt: turn off card detect and power cycle interrupts */ 567 sockmask = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 568 sockmask &= ~(CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | 569 CB_SOCKET_MASK_POWER); 570 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, sockmask); 571 /* reset interrupt */ 572 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 573 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 574 575 switch (sc->sc_flags & (CBB_MEMHMAPPED|CBB_SPECMAPPED)) { 576 case CBB_MEMHMAPPED: 577 bus_space_unmap(bmt, bmh, sc->sc_base_size); 578 break; 579 case CBB_MEMHMAPPED|CBB_SPECMAPPED: 580 #if rbus 581 { 582 pcireg_t sockbase; 583 584 sockbase = pci_conf_read(pc, sc->sc_tag, PCI_SOCKBASE); 585 rbus_space_free(sc->sc_rbus_memt, bmh, 0x1000, 586 NULL); 587 } 588 #else 589 bus_space_free(bmt, bmh, 0x1000); 590 #endif 591 } 592 sc->sc_flags &= ~(CBB_MEMHMAPPED|CBB_SPECMAPPED); 593 594 if (!TAILQ_EMPTY(&sc->sc_iowindow)) 595 aprint_error_dev(self, "i/o windows not empty"); 596 if (!TAILQ_EMPTY(&sc->sc_memwindow)) 597 aprint_error_dev(self, "memory windows not empty"); 598 599 callout_stop(&sc->sc_insert_ch); 600 callout_destroy(&sc->sc_insert_ch); 601 return 0; 602 } 603 604 /* 605 * static void pccbb_pci_callback(device_t self) 606 * 607 * The actual attach routine: get memory space for YENTA register 608 * space, setup YENTA register and route interrupt. 609 * 610 * This function should be deferred because this device may obtain 611 * memory space dynamically. This function must avoid obtaining 612 * memory area which has already kept for another device. 613 */ 614 static void 615 pccbb_pci_callback(device_t self) 616 { 617 struct pccbb_softc *sc = device_private(self); 618 pci_chipset_tag_t pc = sc->sc_pc; 619 bus_addr_t sockbase; 620 struct cbslot_attach_args cba; 621 struct pcmciabus_attach_args paa; 622 struct cardslot_attach_args caa; 623 device_t csc; 624 625 if (!(sc->sc_flags & CBB_MEMHMAPPED)) { 626 /* The socket registers aren't mapped correctly. */ 627 #if rbus 628 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 629 (sc->sc_chipset == CB_RX5C47X 630 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 631 0, &sockbase, &sc->sc_base_memh)) { 632 return; 633 } 634 sc->sc_base_memt = sc->sc_memt; 635 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 636 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 637 device_xname(self), (unsigned long)sockbase, 638 (unsigned long)pci_conf_read(pc, sc->sc_tag, 639 PCI_SOCKBASE))); 640 #else 641 sc->sc_base_memt = sc->sc_memt; 642 #if !defined CBB_PCI_BASE 643 #define CBB_PCI_BASE 0x20000000 644 #endif 645 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 646 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 647 /* cannot allocate memory space */ 648 return; 649 } 650 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 651 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 652 device_xname(self), (unsigned long)sock_base, 653 (unsigned long)pci_conf_read(pc, 654 sc->sc_tag, PCI_SOCKBASE))); 655 #endif 656 sc->sc_flags |= CBB_MEMHMAPPED; 657 } 658 659 /* clear data structure for child device interrupt handlers */ 660 LIST_INIT(&sc->sc_pil); 661 662 /* bus bridge initialization */ 663 pccbb_chipinit(sc); 664 665 sc->sc_pil_intr_enable = 1; 666 667 { 668 u_int32_t sockstat; 669 670 sockstat = bus_space_read_4(sc->sc_base_memt, 671 sc->sc_base_memh, CB_SOCKET_STAT); 672 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 673 sc->sc_flags |= CBB_CARDEXIST; 674 } 675 } 676 677 /* 678 * attach cardbus 679 */ 680 { 681 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 682 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 683 684 /* initialize cbslot_attach */ 685 cba.cba_iot = sc->sc_iot; 686 cba.cba_memt = sc->sc_memt; 687 cba.cba_dmat = sc->sc_dmat; 688 cba.cba_bus = (busreg >> 8) & 0x0ff; 689 cba.cba_cc = (void *)sc; 690 cba.cba_cf = &pccbb_funcs; 691 cba.cba_intrline = 0; /* XXX dummy */ 692 693 #if rbus 694 cba.cba_rbus_iot = sc->sc_rbus_iot; 695 cba.cba_rbus_memt = sc->sc_rbus_memt; 696 #endif 697 698 cba.cba_cacheline = PCI_CACHELINE(bhlc); 699 cba.cba_max_lattimer = PCI_LATTIMER(bhlc); 700 701 aprint_verbose_dev(self, 702 "cacheline 0x%x lattimer 0x%x\n", 703 cba.cba_cacheline, 704 cba.cba_max_lattimer); 705 aprint_verbose_dev(self, "bhlc 0x%x\n", bhlc); 706 #if defined SHOW_REGS 707 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 708 sc->sc_base_memh); 709 #endif 710 } 711 712 pccbb_pcmcia_attach_setup(sc, &paa); 713 caa.caa_cb_attach = NULL; 714 if (cba.cba_bus == 0) 715 aprint_error_dev(self, 716 "secondary bus number uninitialized; try PCI_BUS_FIXUP\n"); 717 else 718 caa.caa_cb_attach = &cba; 719 caa.caa_16_attach = &paa; 720 721 pccbb_intrinit(sc); 722 723 if (NULL != (csc = config_found_ia(self, "pcmciaslot", &caa, 724 cbbprint))) { 725 DPRINTF(("%s: found cardslot\n", __func__)); 726 sc->sc_csc = device_private(csc); 727 } 728 729 return; 730 } 731 732 733 734 735 736 /* 737 * static void pccbb_chipinit(struct pccbb_softc *sc) 738 * 739 * This function initialize YENTA chip registers listed below: 740 * 1) PCI command reg, 741 * 2) PCI and CardBus latency timer, 742 * 3) route PCI interrupt, 743 * 4) close all memory and io windows. 744 * 5) turn off bus power. 745 * 6) card detect and power cycle interrupts on. 746 * 7) clear interrupt 747 */ 748 static void 749 pccbb_chipinit(struct pccbb_softc *sc) 750 { 751 pci_chipset_tag_t pc = sc->sc_pc; 752 pcitag_t tag = sc->sc_tag; 753 bus_space_tag_t bmt = sc->sc_base_memt; 754 bus_space_handle_t bmh = sc->sc_base_memh; 755 pcireg_t bcr, bhlc, cbctl, csr, lscp, mfunc, mrburst, slotctl, sockctl, 756 sysctrl; 757 758 /* 759 * Set PCI command reg. 760 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 761 */ 762 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 763 /* I believe it is harmless. */ 764 csr |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 765 PCI_COMMAND_MASTER_ENABLE); 766 767 /* All O2 Micro chips have broken parity-error reporting 768 * until proven otherwise. The OZ6933 PCI-CardBus Bridge 769 * is known to have the defect---see PR kern/38698. 770 */ 771 if (sc->sc_chipset != CB_O2MICRO) 772 csr |= PCI_COMMAND_PARITY_ENABLE; 773 774 csr |= PCI_COMMAND_SERR_ENABLE; 775 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 776 777 /* 778 * Set CardBus latency timer. 779 */ 780 lscp = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 781 if (PCI_CB_LATENCY(lscp) < 0x20) { 782 lscp &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 783 lscp |= (0x20 << PCI_CB_LATENCY_SHIFT); 784 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, lscp); 785 } 786 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 787 PCI_CB_LATENCY(lscp), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 788 789 /* 790 * Set PCI latency timer. 791 */ 792 bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG); 793 if (PCI_LATTIMER(bhlc) < 0x10) { 794 bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 795 bhlc |= (0x10 << PCI_LATTIMER_SHIFT); 796 pci_conf_write(pc, tag, PCI_BHLC_REG, bhlc); 797 } 798 DPRINTF(("PCI latency timer 0x%x (%x)\n", 799 PCI_LATTIMER(bhlc), pci_conf_read(pc, tag, PCI_BHLC_REG))); 800 801 802 /* Route functional interrupts to PCI. */ 803 bcr = pci_conf_read(pc, tag, PCI_BRIDGE_CONTROL_REG); 804 bcr |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 805 bcr |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 806 /* assert reset */ 807 bcr |= PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT; 808 /* Set master abort mode to 1, forward SERR# from secondary 809 * to primary, and detect parity errors on secondary. 810 */ 811 bcr |= PCI_BRIDGE_CONTROL_MABRT << PCI_BRIDGE_CONTROL_SHIFT; 812 bcr |= PCI_BRIDGE_CONTROL_SERR << PCI_BRIDGE_CONTROL_SHIFT; 813 bcr |= PCI_BRIDGE_CONTROL_PERE << PCI_BRIDGE_CONTROL_SHIFT; 814 pci_conf_write(pc, tag, PCI_BRIDGE_CONTROL_REG, bcr); 815 816 switch (sc->sc_chipset) { 817 case CB_TI113X: 818 cbctl = pci_conf_read(pc, tag, PCI_CBCTRL); 819 /* This bit is shared, but may read as 0 on some chips, so set 820 it explicitly on both functions. */ 821 cbctl |= PCI113X_CBCTRL_PCI_IRQ_ENA; 822 /* CSC intr enable */ 823 cbctl |= PCI113X_CBCTRL_PCI_CSC; 824 /* functional intr prohibit | prohibit ISA routing */ 825 cbctl &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 826 pci_conf_write(pc, tag, PCI_CBCTRL, cbctl); 827 break; 828 829 case CB_TI1420: 830 sysctrl = pci_conf_read(pc, tag, PCI_SYSCTRL); 831 mrburst = pccbb_burstup 832 ? PCI1420_SYSCTRL_MRBURST : PCI1420_SYSCTRL_MRBURSTDN; 833 if ((sysctrl & PCI1420_SYSCTRL_MRBURST) == mrburst) { 834 printf("%s: %swrite bursts enabled\n", 835 device_xname(sc->sc_dev), 836 pccbb_burstup ? "read/" : ""); 837 } else if (pccbb_burstup) { 838 printf("%s: enabling read/write bursts\n", 839 device_xname(sc->sc_dev)); 840 sysctrl |= PCI1420_SYSCTRL_MRBURST; 841 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 842 } else { 843 printf("%s: disabling read bursts, " 844 "enabling write bursts\n", 845 device_xname(sc->sc_dev)); 846 sysctrl |= PCI1420_SYSCTRL_MRBURSTDN; 847 sysctrl &= ~PCI1420_SYSCTRL_MRBURSTUP; 848 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 849 } 850 /*FALLTHROUGH*/ 851 case CB_TI12XX: 852 /* 853 * Some TI 12xx (and [14][45]xx) based pci cards 854 * sometimes have issues with the MFUNC register not 855 * being initialized due to a bad EEPROM on board. 856 * Laptops that this matters on have this register 857 * properly initialized. 858 * 859 * The TI125X parts have a different register. 860 */ 861 mfunc = pci_conf_read(pc, tag, PCI12XX_MFUNC); 862 if (mfunc == 0) { 863 mfunc &= ~PCI12XX_MFUNC_PIN0; 864 mfunc |= PCI12XX_MFUNC_PIN0_INTA; 865 if ((pci_conf_read(pc, tag, PCI_SYSCTRL) & 866 PCI12XX_SYSCTRL_INTRTIE) == 0) { 867 mfunc &= ~PCI12XX_MFUNC_PIN1; 868 mfunc |= PCI12XX_MFUNC_PIN1_INTB; 869 } 870 pci_conf_write(pc, tag, PCI12XX_MFUNC, mfunc); 871 } 872 /* fallthrough */ 873 874 case CB_TI125X: 875 /* 876 * Disable zoom video. Some machines initialize this 877 * improperly and experience has shown that this helps 878 * prevent strange behavior. 879 */ 880 pci_conf_write(pc, tag, PCI12XX_MMCTRL, 0); 881 882 sysctrl = pci_conf_read(pc, tag, PCI_SYSCTRL); 883 sysctrl |= PCI12XX_SYSCTRL_VCCPROT; 884 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 885 cbctl = pci_conf_read(pc, tag, PCI_CBCTRL); 886 cbctl |= PCI12XX_CBCTRL_CSC; 887 pci_conf_write(pc, tag, PCI_CBCTRL, cbctl); 888 break; 889 890 case CB_TOPIC95B: 891 sockctl = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 892 sockctl |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 893 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, sockctl); 894 slotctl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 895 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 896 device_xname(sc->sc_dev), slotctl)); 897 slotctl |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 898 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 899 slotctl &= ~TOPIC_SLOT_CTRL_SWDETECT; 900 DPRINTF(("0x%x\n", slotctl)); 901 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slotctl); 902 break; 903 904 case CB_TOPIC97: 905 slotctl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 906 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 907 device_xname(sc->sc_dev), slotctl)); 908 slotctl |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 909 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 910 slotctl &= ~TOPIC_SLOT_CTRL_SWDETECT; 911 slotctl |= TOPIC97_SLOT_CTRL_PCIINT; 912 slotctl &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 913 DPRINTF(("0x%x\n", slotctl)); 914 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slotctl); 915 /* make sure to assert LV card support bits */ 916 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 917 0x800 + 0x3e, 918 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 919 0x800 + 0x3e) | 0x03); 920 break; 921 } 922 923 /* Close all memory and I/O windows. */ 924 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 925 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 926 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 927 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 928 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 929 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 930 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 931 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 932 933 /* reset 16-bit pcmcia bus */ 934 bus_space_write_1(bmt, bmh, 0x800 + PCIC_INTR, 935 bus_space_read_1(bmt, bmh, 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 936 937 /* turn off power */ 938 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 939 } 940 941 static void 942 pccbb_intrinit(struct pccbb_softc *sc) 943 { 944 pcireg_t sockmask; 945 const char *intrstr = NULL; 946 pci_intr_handle_t ih; 947 pci_chipset_tag_t pc = sc->sc_pc; 948 bus_space_tag_t bmt = sc->sc_base_memt; 949 bus_space_handle_t bmh = sc->sc_base_memh; 950 951 /* Map and establish the interrupt. */ 952 if (pci_intr_map(&sc->sc_pa, &ih)) { 953 aprint_error_dev(sc->sc_dev, "couldn't map interrupt\n"); 954 return; 955 } 956 intrstr = pci_intr_string(pc, ih); 957 958 /* 959 * XXX pccbbintr should be called under the priority lower 960 * than any other hard interupts. 961 */ 962 KASSERT(sc->sc_ih == NULL); 963 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 964 965 if (sc->sc_ih == NULL) { 966 aprint_error_dev(sc->sc_dev, "couldn't establish interrupt"); 967 if (intrstr != NULL) 968 aprint_error(" at %s\n", intrstr); 969 else 970 aprint_error("\n"); 971 return; 972 } 973 974 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 975 976 /* CSC Interrupt: Card detect and power cycle interrupts on */ 977 sockmask = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 978 sockmask |= CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | 979 CB_SOCKET_MASK_POWER; 980 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, sockmask); 981 /* reset interrupt */ 982 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 983 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 984 } 985 986 /* 987 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 988 * struct pcmciabus_attach_args *paa) 989 * 990 * This function attaches 16-bit PCcard bus. 991 */ 992 STATIC void 993 pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 994 struct pcmciabus_attach_args *paa) 995 { 996 struct pcic_handle *ph = &sc->sc_pcmcia_h; 997 #if rbus 998 rbus_tag_t rb; 999 #endif 1000 1001 /* initialize pcmcia part in pccbb_softc */ 1002 ph->ph_parent = sc; 1003 /* rest of ph is zero-initialized */ 1004 sc->sc_pct = &pccbb_pcmcia_funcs; 1005 1006 /* 1007 * We need to do a few things here: 1008 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 1009 * setting the IRQ numbers to 0. 1010 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 1011 * routing of CSC interrupts (e.g. card removal) to PCI while in 1012 * PCMCIA mode. We just leave this set all the time. 1013 * 3) Enable card insertion/removal interrupts in case the chip also 1014 * needs that while in PCMCIA mode. 1015 * 4) Clear any pending CSC interrupt. 1016 */ 1017 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE); 1018 if (sc->sc_chipset == CB_TI113X) { 1019 Pcic_write(ph, PCIC_CSC_INTR, 0); 1020 } else { 1021 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 1022 Pcic_read(ph, PCIC_CSC); 1023 } 1024 1025 /* initialize pcmcia bus attachment */ 1026 paa->paa_busname = "pcmcia"; 1027 paa->pct = sc->sc_pct; 1028 paa->pch = ph; 1029 paa->iobase = 0; /* I don't use them */ 1030 paa->iosize = 0; 1031 #if rbus 1032 rb = sc->sc_rbus_iot; 1033 paa->iobase = rb->rb_start + rb->rb_offset; 1034 paa->iosize = rb->rb_end - rb->rb_start; 1035 #endif 1036 1037 return; 1038 } 1039 1040 #if 0 1041 STATIC void 1042 pccbb_pcmcia_attach_card(struct pcic_handle *ph) 1043 { 1044 if (ph->flags & PCIC_FLAG_CARDP) { 1045 panic("pccbb_pcmcia_attach_card: already attached"); 1046 } 1047 1048 /* call the MI attach function */ 1049 pcmcia_card_attach(ph->pcmcia); 1050 1051 ph->flags |= PCIC_FLAG_CARDP; 1052 } 1053 1054 STATIC void 1055 pccbb_pcmcia_detach_card(struct pcic_handle *ph, int flags) 1056 { 1057 if (!(ph->flags & PCIC_FLAG_CARDP)) { 1058 panic("pccbb_pcmcia_detach_card: already detached"); 1059 } 1060 1061 ph->flags &= ~PCIC_FLAG_CARDP; 1062 1063 /* call the MI detach function */ 1064 pcmcia_card_detach(ph->pcmcia, flags); 1065 } 1066 #endif 1067 1068 /* 1069 * int pccbbintr(arg) 1070 * void *arg; 1071 * This routine handles the interrupt from Yenta PCI-CardBus bridge 1072 * itself. 1073 */ 1074 int 1075 pccbbintr(void *arg) 1076 { 1077 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1078 u_int32_t sockevent, sockstate; 1079 bus_space_tag_t memt = sc->sc_base_memt; 1080 bus_space_handle_t memh = sc->sc_base_memh; 1081 struct pcic_handle *ph = &sc->sc_pcmcia_h; 1082 1083 if (!device_has_power(sc->sc_dev)) 1084 return 0; 1085 1086 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 1087 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 1088 Pcic_read(ph, PCIC_CSC); 1089 1090 if (sockevent != 0) { 1091 aprint_debug("%s: enter sockevent %" PRIx32 "\n", __func__, 1092 sockevent); 1093 } 1094 1095 /* Sometimes a change of CSTSCHG# accompanies the first 1096 * interrupt from an Atheros WLAN. That generates a 1097 * CB_SOCKET_EVENT_CSTS event on the bridge. The event 1098 * isn't interesting to pccbb(4), so we used to ignore the 1099 * interrupt. Now, let the child devices try to handle 1100 * the interrupt, instead. The Atheros NIC produces 1101 * interrupts more reliably, now: used to be that it would 1102 * only interrupt if the driver avoided powering down the 1103 * NIC's cardslot, and then the NIC would only work after 1104 * it was reset a second time. 1105 */ 1106 if (sockevent == 0 || 1107 (sockevent & ~(CB_SOCKET_EVENT_POWER|CB_SOCKET_EVENT_CD)) != 0) { 1108 /* This intr is not for me: it may be for my child devices. */ 1109 if (sc->sc_pil_intr_enable) { 1110 return pccbbintr_function(sc); 1111 } else { 1112 return 0; 1113 } 1114 } 1115 1116 if (sockevent & CB_SOCKET_EVENT_CD) { 1117 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1118 if (0x00 != (sockstate & CB_SOCKET_STAT_CD)) { 1119 /* A card should be removed. */ 1120 if (sc->sc_flags & CBB_CARDEXIST) { 1121 DPRINTF(("%s: 0x%08x", 1122 device_xname(sc->sc_dev), sockevent)); 1123 DPRINTF((" card removed, 0x%08x\n", sockstate)); 1124 sc->sc_flags &= ~CBB_CARDEXIST; 1125 if (sc->sc_csc->sc_status & 1126 CARDSLOT_STATUS_CARD_16) { 1127 #if 0 1128 struct pcic_handle *ph = 1129 &sc->sc_pcmcia_h; 1130 1131 pcmcia_card_deactivate(ph->pcmcia); 1132 pccbb_pcmcia_socket_disable(ph); 1133 pccbb_pcmcia_detach_card(ph, 1134 DETACH_FORCE); 1135 #endif 1136 cardslot_event_throw(sc->sc_csc, 1137 CARDSLOT_EVENT_REMOVAL_16); 1138 } else if (sc->sc_csc->sc_status & 1139 CARDSLOT_STATUS_CARD_CB) { 1140 /* Cardbus intr removed */ 1141 cardslot_event_throw(sc->sc_csc, 1142 CARDSLOT_EVENT_REMOVAL_CB); 1143 } 1144 } else if (sc->sc_flags & CBB_INSERTING) { 1145 sc->sc_flags &= ~CBB_INSERTING; 1146 callout_stop(&sc->sc_insert_ch); 1147 } 1148 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 1149 /* 1150 * The pccbbintr may called from powerdown hook when 1151 * the system resumed, to detect the card 1152 * insertion/removal during suspension. 1153 */ 1154 (sc->sc_flags & CBB_CARDEXIST) == 0) { 1155 if (sc->sc_flags & CBB_INSERTING) { 1156 callout_stop(&sc->sc_insert_ch); 1157 } 1158 callout_schedule(&sc->sc_insert_ch, hz / 5); 1159 sc->sc_flags |= CBB_INSERTING; 1160 } 1161 } 1162 1163 /* XXX sockevent == 9 does occur in the wild. handle it. */ 1164 if (sockevent & CB_SOCKET_EVENT_POWER) { 1165 DPRINTF(("Powercycling because of socket event\n")); 1166 /* XXX: Does not happen when attaching a 16-bit card */ 1167 sc->sc_pwrcycle++; 1168 wakeup(&sc->sc_pwrcycle); 1169 } 1170 1171 return (1); 1172 } 1173 1174 /* 1175 * static int pccbbintr_function(struct pccbb_softc *sc) 1176 * 1177 * This function calls each interrupt handler registered at the 1178 * bridge. The interrupt handlers are called in registered order. 1179 */ 1180 static int 1181 pccbbintr_function(struct pccbb_softc *sc) 1182 { 1183 int retval = 0, val; 1184 struct pccbb_intrhand_list *pil; 1185 int s; 1186 1187 LIST_FOREACH(pil, &sc->sc_pil, pil_next) { 1188 s = splraiseipl(pil->pil_icookie); 1189 val = (*pil->pil_func)(pil->pil_arg); 1190 splx(s); 1191 1192 retval = retval == 1 ? 1 : 1193 retval == 0 ? val : val != 0 ? val : retval; 1194 } 1195 1196 return retval; 1197 } 1198 1199 static void 1200 pci113x_insert(void *arg) 1201 { 1202 struct pccbb_softc *sc = arg; 1203 u_int32_t sockevent, sockstate; 1204 1205 if (!(sc->sc_flags & CBB_INSERTING)) { 1206 /* We add a card only under inserting state. */ 1207 return; 1208 } 1209 sc->sc_flags &= ~CBB_INSERTING; 1210 1211 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1212 CB_SOCKET_EVENT); 1213 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1214 CB_SOCKET_STAT); 1215 1216 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1217 DPRINTF(("%s: 0x%08x", device_xname(sc->sc_dev), sockevent)); 1218 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1219 sc->sc_flags |= CBB_CARDEXIST; 1220 /* call pccard interrupt handler here */ 1221 if (sockstate & CB_SOCKET_STAT_16BIT) { 1222 /* 16-bit card found */ 1223 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1224 cardslot_event_throw(sc->sc_csc, 1225 CARDSLOT_EVENT_INSERTION_16); 1226 } else if (sockstate & CB_SOCKET_STAT_CB) { 1227 /* cardbus card found */ 1228 /* cardbus_attach_card(sc->sc_csc); */ 1229 cardslot_event_throw(sc->sc_csc, 1230 CARDSLOT_EVENT_INSERTION_CB); 1231 } else { 1232 /* who are you? */ 1233 } 1234 } else { 1235 callout_schedule(&sc->sc_insert_ch, hz / 10); 1236 } 1237 } 1238 1239 #define PCCBB_PCMCIA_OFFSET 0x800 1240 static u_int8_t 1241 pccbb_pcmcia_read(struct pccbb_softc *sc, int reg) 1242 { 1243 bus_space_barrier(sc->sc_base_memt, sc->sc_base_memh, 1244 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1245 1246 return bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 1247 PCCBB_PCMCIA_OFFSET + reg); 1248 } 1249 1250 static void 1251 pccbb_pcmcia_write(struct pccbb_softc *sc, int reg, u_int8_t val) 1252 { 1253 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 1254 PCCBB_PCMCIA_OFFSET + reg, val); 1255 1256 bus_space_barrier(sc->sc_base_memt, sc->sc_base_memh, 1257 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1258 } 1259 1260 /* 1261 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1262 */ 1263 STATIC int 1264 pccbb_ctrl(cardbus_chipset_tag_t ct, int command) 1265 { 1266 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1267 1268 switch (command) { 1269 case CARDBUS_CD: 1270 if (2 == pccbb_detect_card(sc)) { 1271 int retval = 0; 1272 int status = cb_detect_voltage(sc); 1273 if (PCCARD_VCC_5V & status) { 1274 retval |= CARDBUS_5V_CARD; 1275 } 1276 if (PCCARD_VCC_3V & status) { 1277 retval |= CARDBUS_3V_CARD; 1278 } 1279 if (PCCARD_VCC_XV & status) { 1280 retval |= CARDBUS_XV_CARD; 1281 } 1282 if (PCCARD_VCC_YV & status) { 1283 retval |= CARDBUS_YV_CARD; 1284 } 1285 return retval; 1286 } else { 1287 return 0; 1288 } 1289 case CARDBUS_RESET: 1290 return cb_reset(sc); 1291 case CARDBUS_IO_ENABLE: /* fallthrough */ 1292 case CARDBUS_IO_DISABLE: /* fallthrough */ 1293 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1294 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1295 case CARDBUS_BM_ENABLE: /* fallthrough */ 1296 case CARDBUS_BM_DISABLE: /* fallthrough */ 1297 /* XXX: I think we don't need to call this function below. */ 1298 return pccbb_cardenable(sc, command); 1299 } 1300 1301 return 0; 1302 } 1303 1304 STATIC int 1305 pccbb_power_ct(cardbus_chipset_tag_t ct, int command) 1306 { 1307 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1308 1309 return pccbb_power(sc, command); 1310 } 1311 1312 /* 1313 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1314 * This function returns true when it succeeds and returns false when 1315 * it fails. 1316 */ 1317 STATIC int 1318 pccbb_power(struct pccbb_softc *sc, int command) 1319 { 1320 u_int32_t status, osock_ctrl, sock_ctrl, reg_ctrl; 1321 bus_space_tag_t memt = sc->sc_base_memt; 1322 bus_space_handle_t memh = sc->sc_base_memh; 1323 int on = 0, pwrcycle, s, times; 1324 struct timeval before, after, diff; 1325 1326 DPRINTF(("pccbb_power: %s and %s [0x%x]\n", 1327 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1328 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1329 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1330 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1331 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1332 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1333 "UNKNOWN", 1334 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1335 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1336 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1337 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1338 "UNKNOWN", command)); 1339 1340 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1341 osock_ctrl = sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1342 1343 switch (command & CARDBUS_VCCMASK) { 1344 case CARDBUS_VCC_UC: 1345 break; 1346 case CARDBUS_VCC_5V: 1347 on++; 1348 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1349 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1350 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1351 } else { 1352 aprint_error_dev(sc->sc_dev, 1353 "BAD voltage request: no 5 V card\n"); 1354 return 0; 1355 } 1356 break; 1357 case CARDBUS_VCC_3V: 1358 on++; 1359 if (CB_SOCKET_STAT_3VCARD & status) { 1360 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1361 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1362 } else { 1363 aprint_error_dev(sc->sc_dev, 1364 "BAD voltage request: no 3.3 V card\n"); 1365 return 0; 1366 } 1367 break; 1368 case CARDBUS_VCC_0V: 1369 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1370 break; 1371 default: 1372 return 0; /* power NEVER changed */ 1373 } 1374 1375 switch (command & CARDBUS_VPPMASK) { 1376 case CARDBUS_VPP_UC: 1377 break; 1378 case CARDBUS_VPP_0V: 1379 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1380 break; 1381 case CARDBUS_VPP_VCC: 1382 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1383 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1384 break; 1385 case CARDBUS_VPP_12V: 1386 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1387 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1388 break; 1389 } 1390 1391 pwrcycle = sc->sc_pwrcycle; 1392 aprint_debug_dev(sc->sc_dev, "osock_ctrl %#" PRIx32 1393 " sock_ctrl %#" PRIx32 "\n", osock_ctrl, sock_ctrl); 1394 1395 microtime(&before); 1396 s = splbio(); 1397 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1398 1399 /* 1400 * Wait as long as 200ms for a power-cycle interrupt. If 1401 * interrupts are enabled, but the socket has already 1402 * changed to the desired status, keep waiting for the 1403 * interrupt. "Consuming" the interrupt in this way keeps 1404 * the interrupt from prematurely waking some subsequent 1405 * pccbb_power call. 1406 * 1407 * XXX Not every bridge interrupts on the ->OFF transition. 1408 * XXX That's ok, we will time-out after 200ms. 1409 * 1410 * XXX The power cycle event will never happen when attaching 1411 * XXX a 16-bit card. That's ok, we will time-out after 1412 * XXX 200ms. 1413 */ 1414 for (times = 5; --times >= 0; ) { 1415 if (cold) 1416 DELAY(40 * 1000); 1417 else { 1418 (void)tsleep(&sc->sc_pwrcycle, PWAIT, "pccpwr", 1419 hz / 25); 1420 if (pwrcycle == sc->sc_pwrcycle) 1421 continue; 1422 } 1423 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1424 if ((status & CB_SOCKET_STAT_PWRCYCLE) != 0 && on) 1425 break; 1426 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0 && !on) 1427 break; 1428 } 1429 splx(s); 1430 microtime(&after); 1431 timersub(&after, &before, &diff); 1432 aprint_debug_dev(sc->sc_dev, "wait took%s %ld.%06lds\n", 1433 (on && times < 0) ? " too long" : "", diff.tv_sec, diff.tv_usec); 1434 1435 /* 1436 * Ok, wait a bit longer for things to settle. 1437 */ 1438 if (on && sc->sc_chipset == CB_TOPIC95B) 1439 delay_ms(100, sc); 1440 1441 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1442 1443 if (on && sc->sc_chipset != CB_TOPIC95B) { 1444 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0) 1445 aprint_error_dev(sc->sc_dev, "power on failed?\n"); 1446 } 1447 1448 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1449 aprint_error_dev(sc->sc_dev, 1450 "bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1451 sock_ctrl, status); 1452 aprint_error_dev(sc->sc_dev, "disabling socket\n"); 1453 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1454 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1455 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1456 status &= ~CB_SOCKET_STAT_BADVCC; 1457 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, status); 1458 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1459 CB_SOCKET_STAT)); 1460 return 0; 1461 } 1462 1463 if (sc->sc_chipset == CB_TOPIC97) { 1464 reg_ctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL); 1465 reg_ctrl &= ~TOPIC97_REG_CTRL_TESTMODE; 1466 if ((command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V) 1467 reg_ctrl &= ~TOPIC97_REG_CTRL_CLKRUN_ENA; 1468 else 1469 reg_ctrl |= TOPIC97_REG_CTRL_CLKRUN_ENA; 1470 pci_conf_write(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL, reg_ctrl); 1471 } 1472 1473 return 1; /* power changed correctly */ 1474 } 1475 1476 #if defined CB_PCMCIA_POLL 1477 struct cb_poll_str { 1478 void *arg; 1479 int (*func)(void *); 1480 int level; 1481 pccard_chipset_tag_t ct; 1482 int count; 1483 struct callout poll_ch; 1484 }; 1485 1486 static struct cb_poll_str cb_poll[10]; 1487 static int cb_poll_n = 0; 1488 1489 static void cb_pcmcia_poll(void *arg); 1490 1491 static void 1492 cb_pcmcia_poll(void *arg) 1493 { 1494 struct cb_poll_str *poll = arg; 1495 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1496 struct pccbb_softc *sc = psc->cpc_parent; 1497 int s; 1498 u_int32_t spsr; /* socket present-state reg */ 1499 1500 callout_reset(&poll->poll_ch, hz / 10, cb_pcmcia_poll, poll); 1501 switch (poll->level) { 1502 case IPL_NET: 1503 s = splnet(); 1504 break; 1505 case IPL_BIO: 1506 s = splbio(); 1507 break; 1508 case IPL_TTY: /* fallthrough */ 1509 default: 1510 s = spltty(); 1511 break; 1512 } 1513 1514 spsr = 1515 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1516 CB_SOCKET_STAT); 1517 1518 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1519 if (!(spsr & 0x40)) { /* CINT low */ 1520 #else 1521 if (1) { 1522 #endif 1523 if ((*poll->func) (poll->arg) == 1) { 1524 ++poll->count; 1525 printf("intr: reported from poller, 0x%x\n", spsr); 1526 #if defined LEVEL2 1527 } else { 1528 printf("intr: miss! 0x%x\n", spsr); 1529 #endif 1530 } 1531 } 1532 splx(s); 1533 } 1534 #endif /* defined CB_PCMCIA_POLL */ 1535 1536 /* 1537 * static int pccbb_detect_card(struct pccbb_softc *sc) 1538 * return value: 0 if no card exists. 1539 * 1 if 16-bit card exists. 1540 * 2 if cardbus card exists. 1541 */ 1542 static int 1543 pccbb_detect_card(struct pccbb_softc *sc) 1544 { 1545 bus_space_handle_t base_memh = sc->sc_base_memh; 1546 bus_space_tag_t base_memt = sc->sc_base_memt; 1547 u_int32_t sockstat = 1548 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1549 int retval = 0; 1550 1551 /* CD1 and CD2 asserted */ 1552 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1553 /* card must be present */ 1554 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1555 /* NOTACARD DEASSERTED */ 1556 if (CB_SOCKET_STAT_CB & sockstat) { 1557 /* CardBus mode */ 1558 retval = 2; 1559 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1560 /* 16-bit mode */ 1561 retval = 1; 1562 } 1563 } 1564 } 1565 return retval; 1566 } 1567 1568 /* 1569 * STATIC int cb_reset(struct pccbb_softc *sc) 1570 * This function resets CardBus card. 1571 */ 1572 STATIC int 1573 cb_reset(struct pccbb_softc *sc) 1574 { 1575 /* 1576 * Reset Assert at least 20 ms 1577 * Some machines request longer duration. 1578 */ 1579 int reset_duration = 1580 (sc->sc_chipset == CB_RX5C47X ? 400 : 50); 1581 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1582 aprint_debug("%s: enter bcr %" PRIx32 "\n", __func__, bcr); 1583 1584 /* Reset bit Assert (bit 6 at 0x3E) */ 1585 bcr |= PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT; 1586 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr); 1587 aprint_debug("%s: wrote bcr %" PRIx32 "\n", __func__, bcr); 1588 delay_ms(reset_duration, sc); 1589 1590 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1591 /* Reset bit Deassert (bit 6 at 0x3E) */ 1592 bcr &= ~(PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT); 1593 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, 1594 bcr); 1595 aprint_debug("%s: wrote bcr %" PRIx32 "\n", __func__, bcr); 1596 delay_ms(reset_duration, sc); 1597 aprint_debug("%s: end of delay\n", __func__); 1598 } 1599 /* No card found on the slot. Keep Reset. */ 1600 return 1; 1601 } 1602 1603 /* 1604 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1605 * This function detect card Voltage. 1606 */ 1607 STATIC int 1608 cb_detect_voltage(struct pccbb_softc *sc) 1609 { 1610 u_int32_t psr; /* socket present-state reg */ 1611 bus_space_tag_t iot = sc->sc_base_memt; 1612 bus_space_handle_t ioh = sc->sc_base_memh; 1613 int vol = PCCARD_VCC_UKN; /* set 0 */ 1614 1615 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1616 1617 if (0x400u & psr) { 1618 vol |= PCCARD_VCC_5V; 1619 } 1620 if (0x800u & psr) { 1621 vol |= PCCARD_VCC_3V; 1622 } 1623 1624 return vol; 1625 } 1626 1627 STATIC int 1628 cbbprint(void *aux, const char *pcic) 1629 { 1630 #if 0 1631 struct cbslot_attach_args *cba = aux; 1632 1633 if (cba->cba_slot >= 0) { 1634 aprint_normal(" slot %d", cba->cba_slot); 1635 } 1636 #endif 1637 return UNCONF; 1638 } 1639 1640 /* 1641 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1642 * This function enables and disables the card 1643 */ 1644 STATIC int 1645 pccbb_cardenable(struct pccbb_softc *sc, int function) 1646 { 1647 u_int32_t command = 1648 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1649 1650 DPRINTF(("pccbb_cardenable:")); 1651 switch (function) { 1652 case CARDBUS_IO_ENABLE: 1653 command |= PCI_COMMAND_IO_ENABLE; 1654 break; 1655 case CARDBUS_IO_DISABLE: 1656 command &= ~PCI_COMMAND_IO_ENABLE; 1657 break; 1658 case CARDBUS_MEM_ENABLE: 1659 command |= PCI_COMMAND_MEM_ENABLE; 1660 break; 1661 case CARDBUS_MEM_DISABLE: 1662 command &= ~PCI_COMMAND_MEM_ENABLE; 1663 break; 1664 case CARDBUS_BM_ENABLE: 1665 command |= PCI_COMMAND_MASTER_ENABLE; 1666 break; 1667 case CARDBUS_BM_DISABLE: 1668 command &= ~PCI_COMMAND_MASTER_ENABLE; 1669 break; 1670 default: 1671 return 0; 1672 } 1673 1674 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1675 DPRINTF((" command reg 0x%x\n", command)); 1676 return 1; 1677 } 1678 1679 #if !rbus 1680 static int 1681 pccbb_io_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 1682 { 1683 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1684 int basereg; 1685 int limitreg; 1686 1687 if ((win < 0) || (win > 2)) { 1688 #if defined DIAGNOSTIC 1689 printf("cardbus_io_open: window out of range %d\n", win); 1690 #endif 1691 return 0; 1692 } 1693 1694 basereg = win * 8 + PCI_CB_IOBASE0; 1695 limitreg = win * 8 + PCI_CB_IOLIMIT0; 1696 1697 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1698 start, basereg, end, limitreg)); 1699 1700 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1701 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1702 return 1; 1703 } 1704 1705 /* 1706 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1707 */ 1708 static int 1709 pccbb_io_close(cardbus_chipset_tag_t ct, int win) 1710 { 1711 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1712 int basereg; 1713 int limitreg; 1714 1715 if ((win < 0) || (win > 2)) { 1716 #if defined DIAGNOSTIC 1717 printf("cardbus_io_close: window out of range %d\n", win); 1718 #endif 1719 return 0; 1720 } 1721 1722 basereg = win * 8 + PCI_CB_IOBASE0; 1723 limitreg = win * 8 + PCI_CB_IOLIMIT0; 1724 1725 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1726 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1727 return 1; 1728 } 1729 1730 static int 1731 pccbb_mem_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 1732 { 1733 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1734 int basereg; 1735 int limitreg; 1736 1737 if ((win < 0) || (win > 2)) { 1738 #if defined DIAGNOSTIC 1739 printf("cardbus_mem_open: window out of range %d\n", win); 1740 #endif 1741 return 0; 1742 } 1743 1744 basereg = win * 8 + PCI_CB_MEMBASE0; 1745 limitreg = win * 8 + PCI_CB_MEMLIMIT0; 1746 1747 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1748 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1749 return 1; 1750 } 1751 1752 static int 1753 pccbb_mem_close(cardbus_chipset_tag_t ct, int win) 1754 { 1755 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1756 int basereg; 1757 int limitreg; 1758 1759 if ((win < 0) || (win > 2)) { 1760 #if defined DIAGNOSTIC 1761 printf("cardbus_mem_close: window out of range %d\n", win); 1762 #endif 1763 return 0; 1764 } 1765 1766 basereg = win * 8 + PCI_CB_MEMBASE0; 1767 limitreg = win * 8 + PCI_CB_MEMLIMIT0; 1768 1769 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1770 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1771 return 1; 1772 } 1773 #endif 1774 1775 /* 1776 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1777 * int irq, 1778 * int level, 1779 * int (* func)(void *), 1780 * void *arg) 1781 * 1782 * This function registers an interrupt handler at the bridge, in 1783 * order not to call the interrupt handlers of child devices when 1784 * a card-deletion interrupt occurs. 1785 * 1786 * The arguments irq and level are not used. 1787 */ 1788 static void * 1789 pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, cardbus_intr_line_t irq, 1790 int level, int (*func)(void *), void *arg) 1791 { 1792 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1793 1794 return pccbb_intr_establish(sc, irq, level, func, arg); 1795 } 1796 1797 1798 /* 1799 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1800 * void *ih) 1801 * 1802 * This function removes an interrupt handler pointed by ih. 1803 */ 1804 static void 1805 pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih) 1806 { 1807 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1808 1809 pccbb_intr_disestablish(sc, ih); 1810 } 1811 1812 1813 void 1814 pccbb_intr_route(struct pccbb_softc *sc) 1815 { 1816 pcireg_t bcr, cbctrl; 1817 1818 /* initialize bridge intr routing */ 1819 bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1820 bcr &= ~CB_BCR_INTR_IREQ_ENABLE; 1821 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr); 1822 1823 switch (sc->sc_chipset) { 1824 case CB_TI113X: 1825 cbctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1826 /* functional intr enabled */ 1827 cbctrl |= PCI113X_CBCTRL_PCI_INTR; 1828 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, cbctrl); 1829 break; 1830 default: 1831 break; 1832 } 1833 } 1834 1835 /* 1836 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1837 * int irq, 1838 * int level, 1839 * int (* func)(void *), 1840 * void *arg) 1841 * 1842 * This function registers an interrupt handler at the bridge, in 1843 * order not to call the interrupt handlers of child devices when 1844 * a card-deletion interrupt occurs. 1845 * 1846 * The arguments irq is not used because pccbb selects intr vector. 1847 */ 1848 static void * 1849 pccbb_intr_establish(struct pccbb_softc *sc, cardbus_intr_line_t irq, 1850 int level, int (*func)(void *), void *arg) 1851 { 1852 struct pccbb_intrhand_list *pil, *newpil; 1853 1854 DPRINTF(("pccbb_intr_establish start. %p\n", LIST_FIRST(&sc->sc_pil))); 1855 1856 if (LIST_EMPTY(&sc->sc_pil)) { 1857 pccbb_intr_route(sc); 1858 } 1859 1860 /* 1861 * Allocate a room for interrupt handler structure. 1862 */ 1863 if (NULL == (newpil = 1864 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1865 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1866 return NULL; 1867 } 1868 1869 newpil->pil_func = func; 1870 newpil->pil_arg = arg; 1871 newpil->pil_icookie = makeiplcookie(level); 1872 1873 if (LIST_EMPTY(&sc->sc_pil)) { 1874 LIST_INSERT_HEAD(&sc->sc_pil, newpil, pil_next); 1875 } else { 1876 for (pil = LIST_FIRST(&sc->sc_pil); 1877 LIST_NEXT(pil, pil_next) != NULL; 1878 pil = LIST_NEXT(pil, pil_next)); 1879 LIST_INSERT_AFTER(pil, newpil, pil_next); 1880 } 1881 1882 DPRINTF(("pccbb_intr_establish add pil. %p\n", 1883 LIST_FIRST(&sc->sc_pil))); 1884 1885 return newpil; 1886 } 1887 1888 /* 1889 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1890 * void *ih) 1891 * 1892 * This function removes an interrupt handler pointed by ih. ih 1893 * should be the value returned by cardbus_intr_establish() or 1894 * NULL. 1895 * 1896 * When ih is NULL, this function will do nothing. 1897 */ 1898 static void 1899 pccbb_intr_disestablish(struct pccbb_softc *sc, void *ih) 1900 { 1901 struct pccbb_intrhand_list *pil; 1902 pcireg_t reg; 1903 1904 DPRINTF(("pccbb_intr_disestablish start. %p\n", 1905 LIST_FIRST(&sc->sc_pil))); 1906 1907 if (ih == NULL) { 1908 /* intr handler is not set */ 1909 DPRINTF(("pccbb_intr_disestablish: no ih\n")); 1910 return; 1911 } 1912 1913 #ifdef DIAGNOSTIC 1914 LIST_FOREACH(pil, &sc->sc_pil, pil_next) { 1915 DPRINTF(("pccbb_intr_disestablish: pil %p\n", pil)); 1916 if (pil == ih) { 1917 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1918 break; 1919 } 1920 } 1921 if (pil == NULL) { 1922 panic("pccbb_intr_disestablish: %s cannot find pil %p", 1923 device_xname(sc->sc_dev), ih); 1924 } 1925 #endif 1926 1927 pil = (struct pccbb_intrhand_list *)ih; 1928 LIST_REMOVE(pil, pil_next); 1929 free(pil, M_DEVBUF); 1930 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1931 1932 if (LIST_EMPTY(&sc->sc_pil)) { 1933 /* No interrupt handlers */ 1934 1935 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1936 1937 /* stop routing PCI intr */ 1938 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1939 reg |= CB_BCR_INTR_IREQ_ENABLE; 1940 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, reg); 1941 1942 switch (sc->sc_chipset) { 1943 case CB_TI113X: 1944 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1945 /* functional intr disabled */ 1946 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1947 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1948 break; 1949 default: 1950 break; 1951 } 1952 } 1953 } 1954 1955 #if defined SHOW_REGS 1956 static void 1957 cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, bus_space_tag_t memt, 1958 bus_space_handle_t memh) 1959 { 1960 int i; 1961 printf("PCI config regs:"); 1962 for (i = 0; i < 0x50; i += 4) { 1963 if (i % 16 == 0) 1964 printf("\n 0x%02x:", i); 1965 printf(" %08x", pci_conf_read(pc, tag, i)); 1966 } 1967 for (i = 0x80; i < 0xb0; i += 4) { 1968 if (i % 16 == 0) 1969 printf("\n 0x%02x:", i); 1970 printf(" %08x", pci_conf_read(pc, tag, i)); 1971 } 1972 1973 if (memh == 0) { 1974 printf("\n"); 1975 return; 1976 } 1977 1978 printf("\nsocket regs:"); 1979 for (i = 0; i <= 0x10; i += 0x04) 1980 printf(" %08x", bus_space_read_4(memt, memh, i)); 1981 printf("\nExCA regs:"); 1982 for (i = 0; i < 0x08; ++i) 1983 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1984 printf("\n"); 1985 return; 1986 } 1987 #endif 1988 1989 /* 1990 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1991 * int busno, int function) 1992 * This is the function to make a tag to access config space of 1993 * a CardBus Card. It works same as pci_conf_read. 1994 */ 1995 static cardbustag_t 1996 pccbb_make_tag(cardbus_chipset_tag_t cc, int busno, int function) 1997 { 1998 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1999 2000 return pci_make_tag(sc->sc_pc, busno, 0, function); 2001 } 2002 2003 static void 2004 pccbb_free_tag(cardbus_chipset_tag_t cc, cardbustag_t tag) 2005 { 2006 } 2007 2008 /* 2009 * pccbb_conf_read 2010 * 2011 * This is the function to read the config space of a CardBus card. 2012 * It works the same as pci_conf_read(9). 2013 */ 2014 static cardbusreg_t 2015 pccbb_conf_read(cardbus_chipset_tag_t cc, cardbustag_t tag, int offset) 2016 { 2017 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 2018 2019 return pci_conf_read(sc->sc_pc, tag, offset); 2020 } 2021 2022 /* 2023 * pccbb_conf_write 2024 * 2025 * This is the function to write the config space of a CardBus 2026 * card. It works the same as pci_conf_write(9). 2027 */ 2028 static void 2029 pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, int reg, 2030 cardbusreg_t val) 2031 { 2032 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 2033 2034 pci_conf_write(sc->sc_pc, tag, reg, val); 2035 } 2036 2037 #if 0 2038 STATIC int 2039 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 2040 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 2041 int speed, int flags, 2042 bus_space_handle_t * iohp) 2043 #endif 2044 /* 2045 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 2046 * bus_addr_t start, bus_size_t size, 2047 * bus_size_t align, 2048 * struct pcmcia_io_handle *pcihp 2049 * 2050 * This function only allocates I/O region for pccard. This function 2051 * never maps the allocated region to pccard I/O area. 2052 * 2053 * XXX: The interface of this function is not very good, I believe. 2054 */ 2055 STATIC int 2056 pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, 2057 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 2058 { 2059 struct pcic_handle *ph = (struct pcic_handle *)pch; 2060 bus_addr_t ioaddr; 2061 int flags = 0; 2062 bus_space_tag_t iot; 2063 bus_space_handle_t ioh; 2064 bus_addr_t mask; 2065 #if rbus 2066 rbus_tag_t rb; 2067 #endif 2068 if (align == 0) { 2069 align = size; /* XXX: funny??? */ 2070 } 2071 2072 if (start != 0) { 2073 /* XXX: assume all card decode lower 10 bits by its hardware */ 2074 mask = 0x3ff; 2075 /* enforce to use only masked address */ 2076 start &= mask; 2077 } else { 2078 /* 2079 * calculate mask: 2080 * 1. get the most significant bit of size (call it msb). 2081 * 2. compare msb with the value of size. 2082 * 3. if size is larger, shift msb left once. 2083 * 4. obtain mask value to decrement msb. 2084 */ 2085 bus_size_t size_tmp = size; 2086 int shifts = 0; 2087 2088 mask = 1; 2089 while (size_tmp) { 2090 ++shifts; 2091 size_tmp >>= 1; 2092 } 2093 mask = (1 << shifts); 2094 if (mask < size) { 2095 mask <<= 1; 2096 } 2097 --mask; 2098 } 2099 2100 /* 2101 * Allocate some arbitrary I/O space. 2102 */ 2103 2104 iot = ph->ph_parent->sc_iot; 2105 2106 #if rbus 2107 rb = ph->ph_parent->sc_rbus_iot; 2108 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 2109 return 1; 2110 } 2111 DPRINTF(("pccbb_pcmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2112 (u_long) ioaddr, (u_long) size)); 2113 #else 2114 if (start) { 2115 ioaddr = start; 2116 if (bus_space_map(iot, start, size, 0, &ioh)) { 2117 return 1; 2118 } 2119 DPRINTF(("pccbb_pcmcia_io_alloc map port 0x%lx+0x%lx\n", 2120 (u_long) ioaddr, (u_long) size)); 2121 } else { 2122 flags |= PCMCIA_IO_ALLOCATED; 2123 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 2124 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 2125 size, align, 0, 0, &ioaddr, &ioh)) { 2126 /* No room be able to be get. */ 2127 return 1; 2128 } 2129 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2130 (u_long) ioaddr, (u_long) size)); 2131 } 2132 #endif 2133 2134 pcihp->iot = iot; 2135 pcihp->ioh = ioh; 2136 pcihp->addr = ioaddr; 2137 pcihp->size = size; 2138 pcihp->flags = flags; 2139 2140 return 0; 2141 } 2142 2143 /* 2144 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2145 * struct pcmcia_io_handle *pcihp) 2146 * 2147 * This function only frees I/O region for pccard. 2148 * 2149 * XXX: The interface of this function is not very good, I believe. 2150 */ 2151 void 2152 pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2153 struct pcmcia_io_handle *pcihp) 2154 { 2155 #if !rbus 2156 bus_space_tag_t iot = pcihp->iot; 2157 #endif 2158 bus_space_handle_t ioh = pcihp->ioh; 2159 bus_size_t size = pcihp->size; 2160 2161 #if rbus 2162 struct pccbb_softc *sc = 2163 ((struct pcic_handle *)pch)->ph_parent; 2164 rbus_tag_t rb = sc->sc_rbus_iot; 2165 2166 rbus_space_free(rb, ioh, size, NULL); 2167 #else 2168 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 2169 bus_space_free(iot, ioh, size); 2170 else 2171 bus_space_unmap(iot, ioh, size); 2172 #endif 2173 } 2174 2175 /* 2176 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 2177 * bus_addr_t offset, bus_size_t size, 2178 * struct pcmcia_io_handle *pcihp, 2179 * int *windowp) 2180 * 2181 * This function maps the allocated I/O region to pccard. This function 2182 * never allocates any I/O region for pccard I/O area. I don't 2183 * understand why the original authors of pcmciabus separated alloc and 2184 * map. I believe the two must be unite. 2185 * 2186 * XXX: no wait timing control? 2187 */ 2188 int 2189 pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, bus_addr_t offset, 2190 bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp) 2191 { 2192 struct pcic_handle *ph = (struct pcic_handle *)pch; 2193 bus_addr_t ioaddr = pcihp->addr + offset; 2194 int i, win; 2195 #if defined CBB_DEBUG 2196 static const char *width_names[] = { "dynamic", "io8", "io16" }; 2197 #endif 2198 2199 /* Sanity check I/O handle. */ 2200 2201 if (ph->ph_parent->sc_iot != pcihp->iot) { 2202 panic("pccbb_pcmcia_io_map iot is bogus"); 2203 } 2204 2205 /* XXX Sanity check offset/size. */ 2206 2207 win = -1; 2208 for (i = 0; i < PCIC_IO_WINS; i++) { 2209 if ((ph->ioalloc & (1 << i)) == 0) { 2210 win = i; 2211 ph->ioalloc |= (1 << i); 2212 break; 2213 } 2214 } 2215 2216 if (win == -1) { 2217 return 1; 2218 } 2219 2220 *windowp = win; 2221 2222 /* XXX this is pretty gross */ 2223 2224 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2225 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2226 2227 /* XXX wtf is this doing here? */ 2228 2229 #if 0 2230 printf(" port 0x%lx", (u_long) ioaddr); 2231 if (size > 1) { 2232 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2233 } 2234 #endif 2235 2236 ph->io[win].addr = ioaddr; 2237 ph->io[win].size = size; 2238 ph->io[win].width = width; 2239 2240 /* actual dirty register-value changing in the function below. */ 2241 pccbb_pcmcia_do_io_map(ph, win); 2242 2243 return 0; 2244 } 2245 2246 /* 2247 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2248 * 2249 * This function changes register-value to map I/O region for pccard. 2250 */ 2251 static void 2252 pccbb_pcmcia_do_io_map(struct pcic_handle *ph, int win) 2253 { 2254 static u_int8_t pcic_iowidth[3] = { 2255 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2256 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2257 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2258 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2259 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2260 }; 2261 2262 #define PCIC_SIA_START_LOW 0 2263 #define PCIC_SIA_START_HIGH 1 2264 #define PCIC_SIA_STOP_LOW 2 2265 #define PCIC_SIA_STOP_HIGH 3 2266 2267 int regbase_win = 0x8 + win * 0x04; 2268 u_int8_t ioctl, enable; 2269 2270 DPRINTF(("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx " 2271 "width %d\n", win, (unsigned long)ph->io[win].addr, 2272 (unsigned long)ph->io[win].size, ph->io[win].width * 8)); 2273 2274 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2275 ph->io[win].addr & 0xff); 2276 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2277 (ph->io[win].addr >> 8) & 0xff); 2278 2279 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2280 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2281 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2282 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2283 2284 ioctl = Pcic_read(ph, PCIC_IOCTL); 2285 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2286 switch (win) { 2287 case 0: 2288 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2289 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2290 PCIC_IOCTL_IO0_DATASIZE_MASK); 2291 ioctl |= pcic_iowidth[ph->io[win].width]; 2292 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2293 break; 2294 case 1: 2295 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2296 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2297 PCIC_IOCTL_IO1_DATASIZE_MASK); 2298 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2299 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2300 break; 2301 } 2302 Pcic_write(ph, PCIC_IOCTL, ioctl); 2303 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2304 #if defined(CBB_DEBUG) 2305 { 2306 u_int8_t start_low = 2307 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2308 u_int8_t start_high = 2309 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2310 u_int8_t stop_low = 2311 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2312 u_int8_t stop_high = 2313 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2314 printf("pccbb_pcmcia_do_io_map start %02x %02x, " 2315 "stop %02x %02x, ioctl %02x enable %02x\n", 2316 start_low, start_high, stop_low, stop_high, ioctl, enable); 2317 } 2318 #endif 2319 } 2320 2321 /* 2322 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2323 * 2324 * This function unmaps I/O region. No return value. 2325 */ 2326 STATIC void 2327 pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t pch, int win) 2328 { 2329 struct pcic_handle *ph = (struct pcic_handle *)pch; 2330 int reg; 2331 2332 if (win >= PCIC_IO_WINS || win < 0) { 2333 panic("pccbb_pcmcia_io_unmap: window out of range"); 2334 } 2335 2336 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2337 switch (win) { 2338 case 0: 2339 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2340 break; 2341 case 1: 2342 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2343 break; 2344 } 2345 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2346 2347 ph->ioalloc &= ~(1 << win); 2348 } 2349 2350 static int 2351 pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 2352 { 2353 u_int8_t stat; 2354 int i; 2355 2356 /* wait an initial 10ms for quick cards */ 2357 stat = Pcic_read(ph, PCIC_IF_STATUS); 2358 if (stat & PCIC_IF_STATUS_READY) 2359 return (0); 2360 pccbb_pcmcia_delay(ph, 10, "pccwr0"); 2361 for (i = 0; i < 50; i++) { 2362 stat = Pcic_read(ph, PCIC_IF_STATUS); 2363 if (stat & PCIC_IF_STATUS_READY) 2364 return (0); 2365 if ((stat & PCIC_IF_STATUS_CARDDETECT_MASK) != 2366 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2367 return (ENXIO); 2368 /* wait .1s (100ms) each iteration now */ 2369 pccbb_pcmcia_delay(ph, 100, "pccwr1"); 2370 } 2371 2372 printf("pccbb_pcmcia_wait_ready: ready never happened, status=%02x\n", stat); 2373 return (EWOULDBLOCK); 2374 } 2375 2376 /* 2377 * Perform long (msec order) delay. timo is in milliseconds. 2378 */ 2379 static void 2380 pccbb_pcmcia_delay(struct pcic_handle *ph, int timo, const char *wmesg) 2381 { 2382 #ifdef DIAGNOSTIC 2383 if (timo <= 0) 2384 panic("pccbb_pcmcia_delay: called with timeout %d", timo); 2385 if (!curlwp) 2386 panic("pccbb_pcmcia_delay: called in interrupt context"); 2387 #endif 2388 DPRINTF(("pccbb_pcmcia_delay: \"%s\", sleep %d ms\n", wmesg, timo)); 2389 tsleep(pccbb_pcmcia_delay, PWAIT, wmesg, roundup(timo * hz, 1000) / 1000); 2390 } 2391 2392 /* 2393 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2394 * 2395 * This function enables the card. All information is stored in 2396 * the first argument, pcmcia_chipset_handle_t. 2397 */ 2398 STATIC void 2399 pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2400 { 2401 struct pcic_handle *ph = (struct pcic_handle *)pch; 2402 struct pccbb_softc *sc = ph->ph_parent; 2403 pcireg_t spsr; 2404 int voltage; 2405 int win; 2406 u_int8_t power, intr; 2407 #ifdef DIAGNOSTIC 2408 int reg; 2409 #endif 2410 2411 /* this bit is mostly stolen from pcic_attach_card */ 2412 2413 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2414 2415 /* get card Vcc info */ 2416 spsr = 2417 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2418 CB_SOCKET_STAT); 2419 if (spsr & CB_SOCKET_STAT_5VCARD) { 2420 DPRINTF(("5V card\n")); 2421 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2422 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2423 DPRINTF(("3V card\n")); 2424 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2425 } else { 2426 DPRINTF(("?V card, 0x%x\n", spsr)); /* XXX */ 2427 return; 2428 } 2429 2430 /* disable interrupts; assert RESET */ 2431 intr = Pcic_read(ph, PCIC_INTR); 2432 intr &= PCIC_INTR_ENABLE; 2433 Pcic_write(ph, PCIC_INTR, intr); 2434 2435 /* zero out the address windows */ 2436 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2437 2438 /* power down the socket to reset it, clear the card reset pin */ 2439 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2440 2441 /* power off; assert output enable bit */ 2442 power = PCIC_PWRCTL_OE; 2443 Pcic_write(ph, PCIC_PWRCTL, power); 2444 2445 /* power up the socket */ 2446 if (pccbb_power(sc, voltage) == 0) 2447 return; 2448 2449 /* 2450 * Table 4-18 and figure 4-6 of the PC Card specifiction say: 2451 * Vcc Rising Time (Tpr) = 100ms (handled in pccbb_power() above) 2452 * RESET Width (Th (Hi-z RESET)) = 1ms 2453 * RESET Width (Tw (RESET)) = 10us 2454 * 2455 * some machines require some more time to be settled 2456 * for example old toshiba topic bridges! 2457 * (100ms is added here). 2458 */ 2459 pccbb_pcmcia_delay(ph, 200 + 1, "pccen1"); 2460 2461 /* negate RESET */ 2462 intr |= PCIC_INTR_RESET; 2463 Pcic_write(ph, PCIC_INTR, intr); 2464 2465 /* 2466 * RESET Setup Time (Tsu (RESET)) = 20ms 2467 */ 2468 pccbb_pcmcia_delay(ph, 20, "pccen2"); 2469 2470 #ifdef DIAGNOSTIC 2471 reg = Pcic_read(ph, PCIC_IF_STATUS); 2472 if ((reg & PCIC_IF_STATUS_POWERACTIVE) == 0) 2473 printf("pccbb_pcmcia_socket_enable: no power, status=%x\n", reg); 2474 #endif 2475 2476 /* wait for the chip to finish initializing */ 2477 if (pccbb_pcmcia_wait_ready(ph)) { 2478 #ifdef DIAGNOSTIC 2479 printf("pccbb_pcmcia_socket_enable: never became ready\n"); 2480 #endif 2481 /* XXX return a failure status?? */ 2482 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2483 Pcic_write(ph, PCIC_PWRCTL, 0); 2484 return; 2485 } 2486 2487 /* reinstall all the memory and io mappings */ 2488 for (win = 0; win < PCIC_MEM_WINS; ++win) 2489 if (ph->memalloc & (1 << win)) 2490 pccbb_pcmcia_do_mem_map(ph, win); 2491 for (win = 0; win < PCIC_IO_WINS; ++win) 2492 if (ph->ioalloc & (1 << win)) 2493 pccbb_pcmcia_do_io_map(ph, win); 2494 } 2495 2496 /* 2497 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2498 * 2499 * This function disables the card. All information is stored in 2500 * the first argument, pcmcia_chipset_handle_t. 2501 */ 2502 STATIC void 2503 pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t pch) 2504 { 2505 struct pcic_handle *ph = (struct pcic_handle *)pch; 2506 struct pccbb_softc *sc = ph->ph_parent; 2507 u_int8_t intr; 2508 2509 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2510 2511 /* disable interrupts; assert RESET */ 2512 intr = Pcic_read(ph, PCIC_INTR); 2513 intr &= PCIC_INTR_ENABLE; 2514 Pcic_write(ph, PCIC_INTR, intr); 2515 2516 /* zero out the address windows */ 2517 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2518 2519 /* power down the socket to reset it, clear the card reset pin */ 2520 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2521 2522 /* disable socket: negate output enable bit and power off */ 2523 Pcic_write(ph, PCIC_PWRCTL, 0); 2524 2525 /* 2526 * Vcc Falling Time (Tpf) = 300ms 2527 */ 2528 pccbb_pcmcia_delay(ph, 300, "pccwr1"); 2529 } 2530 2531 STATIC void 2532 pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t pch, int type) 2533 { 2534 struct pcic_handle *ph = (struct pcic_handle *)pch; 2535 u_int8_t intr; 2536 2537 /* set the card type */ 2538 2539 intr = Pcic_read(ph, PCIC_INTR); 2540 intr &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_CARDTYPE_MASK); 2541 if (type == PCMCIA_IFTYPE_IO) 2542 intr |= PCIC_INTR_CARDTYPE_IO; 2543 else 2544 intr |= PCIC_INTR_CARDTYPE_MEM; 2545 Pcic_write(ph, PCIC_INTR, intr); 2546 2547 DPRINTF(("%s: pccbb_pcmcia_socket_settype type %s %02x\n", 2548 device_xname(ph->ph_parent->sc_dev), 2549 ((type == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2550 } 2551 2552 /* 2553 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2554 * 2555 * This function detects whether a card is in the slot or not. 2556 * If a card is inserted, return 1. Otherwise, return 0. 2557 */ 2558 STATIC int 2559 pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch) 2560 { 2561 struct pcic_handle *ph = (struct pcic_handle *)pch; 2562 struct pccbb_softc *sc = ph->ph_parent; 2563 2564 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2565 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2566 } 2567 2568 #if 0 2569 STATIC int 2570 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2571 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2572 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2573 #endif 2574 /* 2575 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2576 * bus_size_t size, 2577 * struct pcmcia_mem_handle *pcmhp) 2578 * 2579 * This function only allocates memory region for pccard. This 2580 * function never maps the allocated region to pccard memory area. 2581 * 2582 * XXX: Why the argument of start address is not in? 2583 */ 2584 STATIC int 2585 pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 2586 struct pcmcia_mem_handle *pcmhp) 2587 { 2588 struct pcic_handle *ph = (struct pcic_handle *)pch; 2589 bus_space_handle_t memh; 2590 bus_addr_t addr; 2591 bus_size_t sizepg; 2592 struct pccbb_softc *sc = ph->ph_parent; 2593 #if rbus 2594 rbus_tag_t rb; 2595 #endif 2596 2597 /* Check that the card is still there. */ 2598 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2599 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2600 return 1; 2601 2602 /* out of sc->memh, allocate as many pages as necessary */ 2603 2604 /* convert size to PCIC pages */ 2605 /* 2606 * This is not enough; when the requested region is on the page 2607 * boundaries, this may calculate wrong result. 2608 */ 2609 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2610 #if 0 2611 if (sizepg > PCIC_MAX_MEM_PAGES) { 2612 return 1; 2613 } 2614 #endif 2615 2616 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2617 return 1; 2618 } 2619 2620 addr = 0; /* XXX gcc -Wuninitialized */ 2621 2622 #if rbus 2623 rb = sc->sc_rbus_memt; 2624 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2625 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2626 &addr, &memh)) { 2627 return 1; 2628 } 2629 #else 2630 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2631 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2632 0, /* boundary */ 2633 0, /* flags */ 2634 &addr, &memh)) { 2635 return 1; 2636 } 2637 #endif 2638 2639 DPRINTF(("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, " 2640 "realsize 0x%lx\n", (unsigned long)addr, (unsigned long)size, 2641 (unsigned long)sizepg * PCIC_MEM_PAGESIZE)); 2642 2643 pcmhp->memt = sc->sc_memt; 2644 pcmhp->memh = memh; 2645 pcmhp->addr = addr; 2646 pcmhp->size = size; 2647 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2648 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2649 pcmhp->mhandle = 0; 2650 /* No offset??? Funny. */ 2651 2652 return 0; 2653 } 2654 2655 /* 2656 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2657 * struct pcmcia_mem_handle *pcmhp) 2658 * 2659 * This function release the memory space allocated by the function 2660 * pccbb_pcmcia_mem_alloc(). 2661 */ 2662 STATIC void 2663 pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2664 struct pcmcia_mem_handle *pcmhp) 2665 { 2666 #if rbus 2667 struct pcic_handle *ph = (struct pcic_handle *)pch; 2668 struct pccbb_softc *sc = ph->ph_parent; 2669 2670 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2671 #else 2672 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2673 #endif 2674 } 2675 2676 /* 2677 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2678 * 2679 * This function release the memory space allocated by the function 2680 * pccbb_pcmcia_mem_alloc(). 2681 */ 2682 STATIC void 2683 pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2684 { 2685 int regbase_win; 2686 bus_addr_t phys_addr; 2687 bus_addr_t phys_end; 2688 2689 #define PCIC_SMM_START_LOW 0 2690 #define PCIC_SMM_START_HIGH 1 2691 #define PCIC_SMM_STOP_LOW 2 2692 #define PCIC_SMM_STOP_HIGH 3 2693 #define PCIC_CMA_LOW 4 2694 #define PCIC_CMA_HIGH 5 2695 2696 u_int8_t start_low, start_high = 0; 2697 u_int8_t stop_low, stop_high; 2698 u_int8_t off_low, off_high; 2699 u_int8_t mem_window; 2700 int reg; 2701 2702 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2703 int mem8 = 2704 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2705 || (kind == PCMCIA_MEM_ATTR); 2706 2707 regbase_win = 0x10 + win * 0x08; 2708 2709 phys_addr = ph->mem[win].addr; 2710 phys_end = phys_addr + ph->mem[win].size; 2711 2712 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2713 (unsigned long)phys_addr, (unsigned long)phys_end, 2714 (unsigned long)ph->mem[win].offset)); 2715 2716 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2717 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2718 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2719 2720 /* bit 19:12 */ 2721 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2722 /* bit 23:20 and bit 7 on */ 2723 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2724 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2725 /* bit 31:24, for 32-bit address */ 2726 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2727 2728 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2729 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2730 2731 if (ph->ph_parent->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2732 Pcic_write(ph, 0x40 + win, mem_window); 2733 } 2734 2735 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2736 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2737 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2738 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2739 2740 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2741 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2742 2743 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2744 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2745 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2746 | ((kind == PCMCIA_MEM_ATTR) ? 2747 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2748 2749 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2750 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2751 2752 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2753 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2754 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2755 2756 #if defined(CBB_DEBUG) 2757 { 2758 int r1, r2, r3, r4, r5, r6, r7 = 0; 2759 2760 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2761 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2762 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2763 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2764 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2765 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2766 if (ph->ph_parent->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2767 r7 = Pcic_read(ph, 0x40 + win); 2768 } 2769 2770 printf("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2771 "%02x%02x", win, r1, r2, r3, r4, r5, r6); 2772 if (ph->ph_parent->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2773 printf(" %02x", r7); 2774 } 2775 printf("\n"); 2776 } 2777 #endif 2778 } 2779 2780 /* 2781 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2782 * bus_addr_t card_addr, bus_size_t size, 2783 * struct pcmcia_mem_handle *pcmhp, 2784 * bus_addr_t *offsetp, int *windowp) 2785 * 2786 * This function maps memory space allocated by the function 2787 * pccbb_pcmcia_mem_alloc(). 2788 */ 2789 STATIC int 2790 pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2791 bus_addr_t card_addr, bus_size_t size, struct pcmcia_mem_handle *pcmhp, 2792 bus_addr_t *offsetp, int *windowp) 2793 { 2794 struct pcic_handle *ph = (struct pcic_handle *)pch; 2795 bus_addr_t busaddr; 2796 long card_offset; 2797 int win; 2798 2799 /* Check that the card is still there. */ 2800 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2801 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2802 return 1; 2803 2804 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2805 if ((ph->memalloc & (1 << win)) == 0) { 2806 ph->memalloc |= (1 << win); 2807 break; 2808 } 2809 } 2810 2811 if (win == PCIC_MEM_WINS) { 2812 return 1; 2813 } 2814 2815 *windowp = win; 2816 2817 /* XXX this is pretty gross */ 2818 2819 if (ph->ph_parent->sc_memt != pcmhp->memt) { 2820 panic("pccbb_pcmcia_mem_map memt is bogus"); 2821 } 2822 2823 busaddr = pcmhp->addr; 2824 2825 /* 2826 * compute the address offset to the pcmcia address space for the 2827 * pcic. this is intentionally signed. The masks and shifts below 2828 * will cause TRT to happen in the pcic registers. Deal with making 2829 * sure the address is aligned, and return the alignment offset. 2830 */ 2831 2832 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2833 card_addr -= *offsetp; 2834 2835 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2836 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2837 (u_long) card_addr)); 2838 2839 /* 2840 * include the offset in the size, and decrement size by one, since 2841 * the hw wants start/stop 2842 */ 2843 size += *offsetp - 1; 2844 2845 card_offset = (((long)card_addr) - ((long)busaddr)); 2846 2847 ph->mem[win].addr = busaddr; 2848 ph->mem[win].size = size; 2849 ph->mem[win].offset = card_offset; 2850 ph->mem[win].kind = kind; 2851 2852 pccbb_pcmcia_do_mem_map(ph, win); 2853 2854 return 0; 2855 } 2856 2857 /* 2858 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2859 * int window) 2860 * 2861 * This function unmaps memory space which mapped by the function 2862 * pccbb_pcmcia_mem_map(). 2863 */ 2864 STATIC void 2865 pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, int window) 2866 { 2867 struct pcic_handle *ph = (struct pcic_handle *)pch; 2868 int reg; 2869 2870 if (window >= PCIC_MEM_WINS) { 2871 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2872 } 2873 2874 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2875 reg &= ~(1 << window); 2876 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2877 2878 ph->memalloc &= ~(1 << window); 2879 } 2880 2881 #if defined PCCBB_PCMCIA_POLL 2882 struct pccbb_poll_str { 2883 void *arg; 2884 int (*func)(void *); 2885 int level; 2886 struct pcic_handle *ph; 2887 int count; 2888 int num; 2889 struct callout poll_ch; 2890 }; 2891 2892 static struct pccbb_poll_str pccbb_poll[10]; 2893 static int pccbb_poll_n = 0; 2894 2895 static void pccbb_pcmcia_poll(void *arg); 2896 2897 static void 2898 pccbb_pcmcia_poll(void *arg) 2899 { 2900 struct pccbb_poll_str *poll = arg; 2901 struct pcic_handle *ph = poll->ph; 2902 struct pccbb_softc *sc = ph->sc; 2903 int s; 2904 u_int32_t spsr; /* socket present-state reg */ 2905 2906 callout_reset(&poll->poll_ch, hz * 2, pccbb_pcmcia_poll, arg); 2907 switch (poll->level) { 2908 case IPL_NET: 2909 s = splnet(); 2910 break; 2911 case IPL_BIO: 2912 s = splbio(); 2913 break; 2914 case IPL_TTY: /* fallthrough */ 2915 default: 2916 s = spltty(); 2917 break; 2918 } 2919 2920 spsr = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2921 CB_SOCKET_STAT); 2922 2923 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2924 if (!(spsr & 0x40)) /* CINT low */ 2925 #else 2926 if (1) 2927 #endif 2928 { 2929 if ((*poll->func) (poll->arg) > 0) { 2930 ++poll->count; 2931 /* printf("intr: reported from poller, 0x%x\n", spsr); */ 2932 #if defined LEVEL2 2933 } else { 2934 printf("intr: miss! 0x%x\n", spsr); 2935 #endif 2936 } 2937 } 2938 splx(s); 2939 } 2940 #endif /* defined CB_PCMCIA_POLL */ 2941 2942 /* 2943 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2944 * struct pcmcia_function *pf, 2945 * int ipl, 2946 * int (*func)(void *), 2947 * void *arg); 2948 * 2949 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2950 */ 2951 STATIC void * 2952 pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2953 struct pcmcia_function *pf, int ipl, int (*func)(void *), void *arg) 2954 { 2955 struct pcic_handle *ph = (struct pcic_handle *)pch; 2956 struct pccbb_softc *sc = ph->ph_parent; 2957 2958 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2959 /* what should I do? */ 2960 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2961 DPRINTF(("%s does not provide edge nor pulse " 2962 "interrupt\n", device_xname(sc->sc_dev))); 2963 return NULL; 2964 } 2965 /* 2966 * XXX Noooooo! The interrupt flag must set properly!! 2967 * dumb pcmcia driver!! 2968 */ 2969 } 2970 2971 return pccbb_intr_establish(sc, 0, ipl, func, arg); 2972 } 2973 2974 /* 2975 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2976 * void *ih) 2977 * 2978 * This function disables PC-Card interrupt. 2979 */ 2980 STATIC void 2981 pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 2982 { 2983 struct pcic_handle *ph = (struct pcic_handle *)pch; 2984 struct pccbb_softc *sc = ph->ph_parent; 2985 2986 pccbb_intr_disestablish(sc, ih); 2987 } 2988 2989 #if rbus 2990 /* 2991 * static int 2992 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2993 * bus_addr_t addr, bus_size_t size, 2994 * bus_addr_t mask, bus_size_t align, 2995 * int flags, bus_addr_t *addrp; 2996 * bus_space_handle_t *bshp) 2997 * 2998 * This function allocates a portion of memory or io space for 2999 * clients. This function is called from CardBus card drivers. 3000 */ 3001 static int 3002 pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 3003 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 3004 int flags, bus_addr_t *addrp, bus_space_handle_t *bshp) 3005 { 3006 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 3007 3008 DPRINTF(("pccbb_rbus_cb_space_alloc: addr 0x%lx, size 0x%lx, " 3009 "mask 0x%lx, align 0x%lx\n", (unsigned long)addr, 3010 (unsigned long)size, (unsigned long)mask, (unsigned long)align)); 3011 3012 if (align == 0) { 3013 align = size; 3014 } 3015 3016 if (rb->rb_bt == sc->sc_memt) { 3017 if (align < 16) { 3018 return 1; 3019 } 3020 /* 3021 * XXX: align more than 0x1000 to avoid overwrapping 3022 * memory windows for two or more devices. 0x1000 3023 * means memory window's granularity. 3024 * 3025 * Two or more devices should be able to share same 3026 * memory window region. However, overrapping memory 3027 * window is not good because some devices, such as 3028 * 3Com 3C575[BC], have a broken address decoder and 3029 * intrude other's memory region. 3030 */ 3031 if (align < 0x1000) { 3032 align = 0x1000; 3033 } 3034 } else if (rb->rb_bt == sc->sc_iot) { 3035 if (align < 4) { 3036 return 1; 3037 } 3038 /* XXX: hack for avoiding ISA image */ 3039 if (mask < 0x0100) { 3040 mask = 0x3ff; 3041 addr = 0x300; 3042 } 3043 3044 } else { 3045 DPRINTF(("pccbb_rbus_cb_space_alloc: Bus space tag 0x%lx is " 3046 "NOT used. io: 0x%lx, mem: 0x%lx\n", 3047 (unsigned long)rb->rb_bt, (unsigned long)sc->sc_iot, 3048 (unsigned long)sc->sc_memt)); 3049 return 1; 3050 /* XXX: panic here? */ 3051 } 3052 3053 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 3054 aprint_normal_dev(sc->sc_dev, "<rbus> no bus space\n"); 3055 return 1; 3056 } 3057 3058 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 3059 3060 return 0; 3061 } 3062 3063 /* 3064 * static int 3065 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 3066 * bus_space_handle_t *bshp, bus_size_t size); 3067 * 3068 * This function is called from CardBus card drivers. 3069 */ 3070 static int 3071 pccbb_rbus_cb_space_free(cardbus_chipset_tag_t ct, rbus_tag_t rb, 3072 bus_space_handle_t bsh, bus_size_t size) 3073 { 3074 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 3075 bus_space_tag_t bt = rb->rb_bt; 3076 3077 pccbb_close_win(sc, bt, bsh, size); 3078 3079 if (bt == sc->sc_memt) { 3080 } else if (bt == sc->sc_iot) { 3081 } else { 3082 return 1; 3083 /* XXX: panic here? */ 3084 } 3085 3086 return rbus_space_free(rb, bsh, size, NULL); 3087 } 3088 #endif /* rbus */ 3089 3090 #if rbus 3091 3092 static int 3093 pccbb_open_win(struct pccbb_softc *sc, bus_space_tag_t bst, bus_addr_t addr, 3094 bus_size_t size, bus_space_handle_t bsh, int flags) 3095 { 3096 struct pccbb_win_chain_head *head; 3097 bus_addr_t align; 3098 3099 head = &sc->sc_iowindow; 3100 align = 0x04; 3101 if (sc->sc_memt == bst) { 3102 head = &sc->sc_memwindow; 3103 align = 0x1000; 3104 DPRINTF(("using memory window, 0x%lx 0x%lx 0x%lx\n\n", 3105 (unsigned long)sc->sc_iot, (unsigned long)sc->sc_memt, 3106 (unsigned long)bst)); 3107 } 3108 3109 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 3110 aprint_error_dev(sc->sc_dev, 3111 "pccbb_open_win: %s winlist insert failed\n", 3112 (head == &sc->sc_memwindow) ? "mem" : "io"); 3113 } 3114 pccbb_winset(align, sc, bst); 3115 3116 return 0; 3117 } 3118 3119 static int 3120 pccbb_close_win(struct pccbb_softc *sc, bus_space_tag_t bst, 3121 bus_space_handle_t bsh, bus_size_t size) 3122 { 3123 struct pccbb_win_chain_head *head; 3124 bus_addr_t align; 3125 3126 head = &sc->sc_iowindow; 3127 align = 0x04; 3128 if (sc->sc_memt == bst) { 3129 head = &sc->sc_memwindow; 3130 align = 0x1000; 3131 } 3132 3133 if (pccbb_winlist_delete(head, bsh, size)) { 3134 aprint_error_dev(sc->sc_dev, 3135 "pccbb_close_win: %s winlist delete failed\n", 3136 (head == &sc->sc_memwindow) ? "mem" : "io"); 3137 } 3138 pccbb_winset(align, sc, bst); 3139 3140 return 0; 3141 } 3142 3143 static int 3144 pccbb_winlist_insert(struct pccbb_win_chain_head *head, bus_addr_t start, 3145 bus_size_t size, bus_space_handle_t bsh, int flags) 3146 { 3147 struct pccbb_win_chain *chainp, *elem; 3148 3149 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 3150 M_NOWAIT)) == NULL) 3151 return (1); /* fail */ 3152 3153 elem->wc_start = start; 3154 elem->wc_end = start + (size - 1); 3155 elem->wc_handle = bsh; 3156 elem->wc_flags = flags; 3157 3158 TAILQ_FOREACH(chainp, head, wc_list) { 3159 if (chainp->wc_end >= start) 3160 break; 3161 } 3162 if (chainp != NULL) 3163 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 3164 else 3165 TAILQ_INSERT_TAIL(head, elem, wc_list); 3166 return (0); 3167 } 3168 3169 static int 3170 pccbb_winlist_delete(struct pccbb_win_chain_head *head, bus_space_handle_t bsh, 3171 bus_size_t size) 3172 { 3173 struct pccbb_win_chain *chainp; 3174 3175 TAILQ_FOREACH(chainp, head, wc_list) { 3176 if (memcmp(&chainp->wc_handle, &bsh, sizeof(bsh)) == 0) 3177 break; 3178 } 3179 if (chainp == NULL) 3180 return 1; /* fail: no candidate to remove */ 3181 3182 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 3183 printf("pccbb_winlist_delete: window 0x%lx size " 3184 "inconsistent: 0x%lx, 0x%lx\n", 3185 (unsigned long)chainp->wc_start, 3186 (unsigned long)(chainp->wc_end - chainp->wc_start), 3187 (unsigned long)(size - 1)); 3188 return 1; 3189 } 3190 3191 TAILQ_REMOVE(head, chainp, wc_list); 3192 free(chainp, M_DEVBUF); 3193 3194 return 0; 3195 } 3196 3197 static void 3198 pccbb_winset(bus_addr_t align, struct pccbb_softc *sc, bus_space_tag_t bst) 3199 { 3200 pci_chipset_tag_t pc; 3201 pcitag_t tag; 3202 bus_addr_t mask = ~(align - 1); 3203 struct { 3204 cardbusreg_t win_start; 3205 cardbusreg_t win_limit; 3206 int win_flags; 3207 } win[2]; 3208 struct pccbb_win_chain *chainp; 3209 int offs; 3210 3211 win[0].win_start = win[1].win_start = 0xffffffff; 3212 win[0].win_limit = win[1].win_limit = 0; 3213 win[0].win_flags = win[1].win_flags = 0; 3214 3215 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3216 offs = PCI_CB_IOBASE0; 3217 if (sc->sc_memt == bst) { 3218 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3219 offs = PCI_CB_MEMBASE0; 3220 } 3221 3222 if (chainp != NULL) { 3223 win[0].win_start = chainp->wc_start & mask; 3224 win[0].win_limit = chainp->wc_end & mask; 3225 win[0].win_flags = chainp->wc_flags; 3226 chainp = TAILQ_NEXT(chainp, wc_list); 3227 } 3228 3229 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3230 if (win[1].win_start == 0xffffffff) { 3231 /* window 1 is not used */ 3232 if ((win[0].win_flags == chainp->wc_flags) && 3233 (win[0].win_limit + align >= 3234 (chainp->wc_start & mask))) { 3235 /* concatenate */ 3236 win[0].win_limit = chainp->wc_end & mask; 3237 } else { 3238 /* make new window */ 3239 win[1].win_start = chainp->wc_start & mask; 3240 win[1].win_limit = chainp->wc_end & mask; 3241 win[1].win_flags = chainp->wc_flags; 3242 } 3243 continue; 3244 } 3245 3246 /* Both windows are engaged. */ 3247 if (win[0].win_flags == win[1].win_flags) { 3248 /* same flags */ 3249 if (win[0].win_flags == chainp->wc_flags) { 3250 if (win[1].win_start - (win[0].win_limit + 3251 align) < 3252 (chainp->wc_start & mask) - 3253 ((chainp->wc_end & mask) + align)) { 3254 /* 3255 * merge window 0 and 1, and set win1 3256 * to chainp 3257 */ 3258 win[0].win_limit = win[1].win_limit; 3259 win[1].win_start = 3260 chainp->wc_start & mask; 3261 win[1].win_limit = 3262 chainp->wc_end & mask; 3263 } else { 3264 win[1].win_limit = 3265 chainp->wc_end & mask; 3266 } 3267 } else { 3268 /* different flags */ 3269 3270 /* concatenate win0 and win1 */ 3271 win[0].win_limit = win[1].win_limit; 3272 /* allocate win[1] to new space */ 3273 win[1].win_start = chainp->wc_start & mask; 3274 win[1].win_limit = chainp->wc_end & mask; 3275 win[1].win_flags = chainp->wc_flags; 3276 } 3277 } else { 3278 /* the flags of win[0] and win[1] is different */ 3279 if (win[0].win_flags == chainp->wc_flags) { 3280 win[0].win_limit = chainp->wc_end & mask; 3281 /* 3282 * XXX this creates overlapping windows, so 3283 * what should the poor bridge do if one is 3284 * cachable, and the other is not? 3285 */ 3286 aprint_error_dev(sc->sc_dev, 3287 "overlapping windows\n"); 3288 } else { 3289 win[1].win_limit = chainp->wc_end & mask; 3290 } 3291 } 3292 } 3293 3294 pc = sc->sc_pc; 3295 tag = sc->sc_tag; 3296 pci_conf_write(pc, tag, offs, win[0].win_start); 3297 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3298 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3299 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3300 DPRINTF(("--pccbb_winset: win0 [0x%lx, 0x%lx), win1 [0x%lx, 0x%lx)\n", 3301 (unsigned long)pci_conf_read(pc, tag, offs), 3302 (unsigned long)pci_conf_read(pc, tag, offs + 4) + align, 3303 (unsigned long)pci_conf_read(pc, tag, offs + 8), 3304 (unsigned long)pci_conf_read(pc, tag, offs + 12) + align)); 3305 3306 if (bst == sc->sc_memt) { 3307 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BRIDGE_CONTROL_REG); 3308 3309 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 3310 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 3311 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3312 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 3313 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3314 pci_conf_write(pc, tag, PCI_BRIDGE_CONTROL_REG, bcr); 3315 } 3316 } 3317 3318 #endif /* rbus */ 3319 3320 static bool 3321 pccbb_suspend(device_t dv PMF_FN_ARGS) 3322 { 3323 struct pccbb_softc *sc = device_private(dv); 3324 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3325 bus_space_handle_t base_memh = sc->sc_base_memh; 3326 pcireg_t reg; 3327 3328 if (sc->sc_pil_intr_enable) 3329 (void)pccbbintr_function(sc); 3330 sc->sc_pil_intr_enable = 0; 3331 3332 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3333 /* Disable interrupts. */ 3334 reg &= ~(CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER); 3335 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3336 /* XXX joerg Disable power to the socket? */ 3337 3338 /* XXX flush PCI write */ 3339 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3340 3341 /* reset interrupt */ 3342 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, 3343 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT)); 3344 /* XXX flush PCI write */ 3345 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3346 3347 if (sc->sc_ih != NULL) { 3348 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 3349 sc->sc_ih = NULL; 3350 } 3351 3352 return true; 3353 } 3354 3355 static bool 3356 pccbb_resume(device_t dv PMF_FN_ARGS) 3357 { 3358 struct pccbb_softc *sc = device_private(dv); 3359 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3360 bus_space_handle_t base_memh = sc->sc_base_memh; 3361 pcireg_t reg; 3362 3363 pccbb_chipinit(sc); 3364 pccbb_intrinit(sc); 3365 /* setup memory and io space window for CB */ 3366 pccbb_winset(0x1000, sc, sc->sc_memt); 3367 pccbb_winset(0x04, sc, sc->sc_iot); 3368 3369 /* CSC Interrupt: Card detect interrupt on */ 3370 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3371 /* Card detect intr is turned on. */ 3372 reg |= CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; 3373 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3374 /* reset interrupt */ 3375 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3376 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3377 3378 /* 3379 * check for card insertion or removal during suspend period. 3380 * XXX: the code can't cope with card swap (remove then 3381 * insert). how can we detect such situation? 3382 */ 3383 (void)pccbbintr(sc); 3384 3385 sc->sc_pil_intr_enable = 1; 3386 3387 return true; 3388 } 3389
Indexes created Mon Sep 29 03:10:08 GMT 2025