pccbb.c revision 1.176
1 /* $NetBSD: pccbb.c,v 1.176 2008/06/26 18:05:48 drochner Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: pccbb.c,v 1.176 2008/06/26 18:05:48 drochner Exp $"); 35 36 /* 37 #define CBB_DEBUG 38 #define SHOW_REGS 39 */ 40 41 /* 42 * BROKEN! 43 #define PCCBB_PCMCIA_POLL 44 #define CB_PCMCIA_POLL 45 #define CB_PCMCIA_POLL_ONLY 46 #define LEVEL2 47 */ 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/kernel.h> 52 #include <sys/errno.h> 53 #include <sys/ioctl.h> 54 #include <sys/reboot.h> /* for bootverbose */ 55 #include <sys/syslog.h> 56 #include <sys/device.h> 57 #include <sys/malloc.h> 58 #include <sys/proc.h> 59 60 #include <sys/intr.h> 61 #include <sys/bus.h> 62 63 #include <dev/pci/pcivar.h> 64 #include <dev/pci/pcireg.h> 65 #include <dev/pci/pcidevs.h> 66 67 #include <dev/pci/pccbbreg.h> 68 69 #include <dev/cardbus/cardslotvar.h> 70 71 #include <dev/cardbus/cardbusvar.h> 72 73 #include <dev/pcmcia/pcmciareg.h> 74 #include <dev/pcmcia/pcmciavar.h> 75 76 #include <dev/ic/i82365reg.h> 77 #include <dev/pci/pccbbvar.h> 78 79 #ifndef __NetBSD_Version__ 80 struct cfdriver cbb_cd = { 81 NULL, "cbb", DV_DULL 82 }; 83 #endif 84 85 #ifdef CBB_DEBUG 86 #define DPRINTF(x) printf x 87 #define STATIC 88 #else 89 #define DPRINTF(x) 90 #define STATIC static 91 #endif 92 93 int pccbb_burstup = 1; 94 95 /* 96 * delay_ms() is wait in milliseconds. It should be used instead 97 * of delay() if you want to wait more than 1 ms. 98 */ 99 static inline void 100 delay_ms(int millis, void *param) 101 { 102 if (cold) 103 delay(millis * 1000); 104 else 105 tsleep(param, PWAIT, "pccbb", MAX(2, hz * millis / 1000)); 106 } 107 108 int pcicbbmatch(device_t, struct cfdata *, void *); 109 void pccbbattach(device_t, device_t, void *); 110 int pccbbdetach(device_t, int); 111 int pccbbintr(void *); 112 static void pci113x_insert(void *); 113 static int pccbbintr_function(struct pccbb_softc *); 114 115 static int pccbb_detect_card(struct pccbb_softc *); 116 117 static void pccbb_pcmcia_write(struct pccbb_softc *, int, u_int8_t); 118 static u_int8_t pccbb_pcmcia_read(struct pccbb_softc *, int); 119 #define Pcic_read(ph, reg) pccbb_pcmcia_read((ph)->ph_parent, (reg)) 120 #define Pcic_write(ph, reg, val) pccbb_pcmcia_write((ph)->ph_parent, \ 121 (reg), (val)) 122 123 STATIC int cb_reset(struct pccbb_softc *); 124 STATIC int cb_detect_voltage(struct pccbb_softc *); 125 STATIC int cbbprint(void *, const char *); 126 127 static int cb_chipset(u_int32_t, int *); 128 STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *, 129 struct pcmciabus_attach_args *); 130 131 STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int); 132 STATIC int pccbb_power(struct pccbb_softc *sc, int); 133 STATIC int pccbb_power_ct(cardbus_chipset_tag_t, int); 134 STATIC int pccbb_cardenable(struct pccbb_softc * sc, int function); 135 #if !rbus 136 static int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 137 static int pccbb_io_close(cardbus_chipset_tag_t, int); 138 static int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 139 static int pccbb_mem_close(cardbus_chipset_tag_t, int); 140 #endif /* !rbus */ 141 static void *pccbb_intr_establish(struct pccbb_softc *, 142 cardbus_intr_line_t irq, int level, int (*ih) (void *), void *sc); 143 static void pccbb_intr_disestablish(struct pccbb_softc *, void *ih); 144 145 static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t, 146 cardbus_intr_line_t irq, int level, int (*ih) (void *), void *sc); 147 static void pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih); 148 149 static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t, int, int); 150 static void pccbb_free_tag(cardbus_chipset_tag_t, cardbustag_t); 151 static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t, cardbustag_t, int); 152 static void pccbb_conf_write(cardbus_chipset_tag_t, cardbustag_t, int, 153 cardbusreg_t); 154 static void pccbb_chipinit(struct pccbb_softc *); 155 static void pccbb_intrinit(struct pccbb_softc *); 156 157 STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 158 struct pcmcia_mem_handle *); 159 STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t, 160 struct pcmcia_mem_handle *); 161 STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 162 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *); 163 STATIC void pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t, int); 164 STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 165 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 166 STATIC void pccbb_pcmcia_io_free(pcmcia_chipset_handle_t, 167 struct pcmcia_io_handle *); 168 STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 169 bus_size_t, struct pcmcia_io_handle *, int *); 170 STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t, int); 171 STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t, 172 struct pcmcia_function *, int, int (*)(void *), void *); 173 STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t, void *); 174 STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t); 175 STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t); 176 STATIC void pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t, int); 177 STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch); 178 179 static int pccbb_pcmcia_wait_ready(struct pccbb_softc *); 180 static void pccbb_pcmcia_delay(struct pccbb_softc *, int, const char *); 181 182 static void pccbb_pcmcia_do_io_map(struct pccbb_softc *, int); 183 static void pccbb_pcmcia_do_mem_map(struct pccbb_softc *, int); 184 185 /* bus-space allocation and deallocation functions */ 186 #if rbus 187 188 static int pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t, rbus_tag_t, 189 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 190 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp); 191 static int pccbb_rbus_cb_space_free(cardbus_chipset_tag_t, rbus_tag_t, 192 bus_space_handle_t, bus_size_t); 193 194 #endif /* rbus */ 195 196 #if rbus 197 198 static int pccbb_open_win(struct pccbb_softc *, bus_space_tag_t, 199 bus_addr_t, bus_size_t, bus_space_handle_t, int flags); 200 static int pccbb_close_win(struct pccbb_softc *, bus_space_tag_t, 201 bus_space_handle_t, bus_size_t); 202 static int pccbb_winlist_insert(struct pccbb_win_chain_head *, bus_addr_t, 203 bus_size_t, bus_space_handle_t, int); 204 static int pccbb_winlist_delete(struct pccbb_win_chain_head *, 205 bus_space_handle_t, bus_size_t); 206 static void pccbb_winset(bus_addr_t align, struct pccbb_softc *, 207 bus_space_tag_t); 208 void pccbb_winlist_show(struct pccbb_win_chain *); 209 210 #endif /* rbus */ 211 212 /* for config_defer */ 213 static void pccbb_pci_callback(device_t); 214 215 static bool pccbb_suspend(device_t PMF_FN_PROTO); 216 static bool pccbb_resume(device_t PMF_FN_PROTO); 217 218 #if defined SHOW_REGS 219 static void cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, 220 bus_space_tag_t memt, bus_space_handle_t memh); 221 #endif 222 223 CFATTACH_DECL_NEW(cbb_pci, sizeof(struct pccbb_softc), 224 pcicbbmatch, pccbbattach, pccbbdetach, NULL); 225 226 static const struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 227 pccbb_pcmcia_mem_alloc, 228 pccbb_pcmcia_mem_free, 229 pccbb_pcmcia_mem_map, 230 pccbb_pcmcia_mem_unmap, 231 pccbb_pcmcia_io_alloc, 232 pccbb_pcmcia_io_free, 233 pccbb_pcmcia_io_map, 234 pccbb_pcmcia_io_unmap, 235 pccbb_pcmcia_intr_establish, 236 pccbb_pcmcia_intr_disestablish, 237 pccbb_pcmcia_socket_enable, 238 pccbb_pcmcia_socket_disable, 239 pccbb_pcmcia_socket_settype, 240 pccbb_pcmcia_card_detect 241 }; 242 243 #if rbus 244 static const struct cardbus_functions pccbb_funcs = { 245 pccbb_rbus_cb_space_alloc, 246 pccbb_rbus_cb_space_free, 247 pccbb_cb_intr_establish, 248 pccbb_cb_intr_disestablish, 249 pccbb_ctrl, 250 pccbb_power_ct, 251 pccbb_make_tag, 252 pccbb_free_tag, 253 pccbb_conf_read, 254 pccbb_conf_write, 255 }; 256 #else 257 static const struct cardbus_functions pccbb_funcs = { 258 pccbb_ctrl, 259 pccbb_power_ct, 260 pccbb_mem_open, 261 pccbb_mem_close, 262 pccbb_io_open, 263 pccbb_io_close, 264 pccbb_cb_intr_establish, 265 pccbb_cb_intr_disestablish, 266 pccbb_make_tag, 267 pccbb_conf_read, 268 pccbb_conf_write, 269 }; 270 #endif 271 272 int 273 pcicbbmatch(device_t parent, struct cfdata *match, void *aux) 274 { 275 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 276 277 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 278 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 279 PCI_INTERFACE(pa->pa_class) == 0) { 280 return 1; 281 } 282 283 return 0; 284 } 285 286 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 287 | ((prod) << PCI_PRODUCT_SHIFT)) 288 289 const struct yenta_chipinfo { 290 pcireg_t yc_id; /* vendor tag | product tag */ 291 int yc_chiptype; 292 int yc_flags; 293 } yc_chipsets[] = { 294 /* Texas Instruments chips */ 295 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 296 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 297 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 298 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 299 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI125X, 300 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 301 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 302 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 303 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 304 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 305 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 306 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 307 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI125X, 308 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 309 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI125X, 310 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 311 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 312 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 313 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 314 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 315 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI1420, 316 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 317 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI125X, 318 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 319 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 320 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 321 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1520), CB_TI12XX, 322 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 323 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4410YENTA), CB_TI12XX, 324 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 325 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4520YENTA), CB_TI12XX, 326 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 327 328 /* Ricoh chips */ 329 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 330 PCCBB_PCMCIA_MEM_32}, 331 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 332 PCCBB_PCMCIA_MEM_32}, 333 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 334 PCCBB_PCMCIA_MEM_32}, 335 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 336 PCCBB_PCMCIA_MEM_32}, 337 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 338 PCCBB_PCMCIA_MEM_32}, 339 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 340 PCCBB_PCMCIA_MEM_32}, 341 342 /* Toshiba products */ 343 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 344 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 345 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 346 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 347 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 348 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 349 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 350 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 351 352 /* Cirrus Logic products */ 353 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 354 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 355 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 356 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 357 358 /* O2 Micro products */ 359 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6729), 360 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 361 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6730), 362 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 363 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6832), 364 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 365 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6836), 366 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 367 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6872), 368 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 369 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6922), 370 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 371 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6933), 372 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 373 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6972), 374 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 375 376 /* sentinel, or Generic chip */ 377 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 378 }; 379 380 static int 381 cb_chipset(u_int32_t pci_id, int *flagp) 382 { 383 const struct yenta_chipinfo *yc; 384 385 /* Loop over except the last default entry. */ 386 for (yc = yc_chipsets; yc < yc_chipsets + 387 __arraycount(yc_chipsets) - 1; yc++) 388 if (pci_id == yc->yc_id) 389 break; 390 391 if (flagp != NULL) 392 *flagp = yc->yc_flags; 393 394 return (yc->yc_chiptype); 395 } 396 397 void 398 pccbbattach(device_t parent, device_t self, void *aux) 399 { 400 struct pccbb_softc *sc = device_private(self); 401 struct pci_attach_args *pa = aux; 402 pci_chipset_tag_t pc = pa->pa_pc; 403 pcireg_t busreg, reg, sock_base; 404 bus_addr_t sockbase; 405 char devinfo[256]; 406 int flags; 407 408 #ifdef __HAVE_PCCBB_ATTACH_HOOK 409 pccbb_attach_hook(parent, self, pa); 410 #endif 411 412 sc->sc_dev = self; 413 414 callout_init(&sc->sc_insert_ch, 0); 415 callout_setfunc(&sc->sc_insert_ch, pci113x_insert, sc); 416 417 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 418 419 aprint_naive("\n"); 420 421 pci_devinfo(pa->pa_id, 0, 0, devinfo, sizeof(devinfo)); 422 aprint_normal(": %s (rev. 0x%02x)", devinfo, 423 PCI_REVISION(pa->pa_class)); 424 DPRINTF((" (chipflags %x)", flags)); 425 aprint_normal("\n"); 426 427 TAILQ_INIT(&sc->sc_memwindow); 428 TAILQ_INIT(&sc->sc_iowindow); 429 430 #if rbus 431 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 432 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 433 434 #if 0 435 printf("pa->pa_memt: %08x vs rbus_mem->rb_bt: %08x\n", 436 pa->pa_memt, sc->sc_rbus_memt->rb_bt); 437 #endif 438 #endif /* rbus */ 439 440 sc->sc_flags &= ~CBB_MEMHMAPPED; 441 442 /* 443 * MAP socket registers and ExCA registers on memory-space 444 * When no valid address is set on socket base registers (on pci 445 * config space), get it not polite way. 446 */ 447 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 448 449 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 450 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 451 /* The address must be valid. */ 452 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 453 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, &sc->sc_base_size)) { 454 aprint_error_dev(self, 455 "can't map socket base address 0x%lx\n", 456 (unsigned long)sock_base); 457 /* 458 * I think it's funny: socket base registers must be 459 * mapped on memory space, but ... 460 */ 461 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 462 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 463 &sc->sc_base_size)) { 464 aprint_error_dev(self, 465 "can't map socket base address" 466 " 0x%lx: io mode\n", 467 (unsigned long)sockbase); 468 /* give up... allocate reg space via rbus. */ 469 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 470 } else 471 sc->sc_flags |= CBB_MEMHMAPPED; 472 } else { 473 DPRINTF(("%s: socket base address 0x%lx\n", 474 device_xname(self), 475 (unsigned long)sockbase)); 476 sc->sc_flags |= CBB_MEMHMAPPED; 477 } 478 } 479 480 sc->sc_mem_start = 0; /* XXX */ 481 sc->sc_mem_end = 0xffffffff; /* XXX */ 482 483 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 484 485 /* pccbb_machdep.c end */ 486 487 #if defined CBB_DEBUG 488 { 489 static const char *intrname[] = { "NON", "A", "B", "C", "D" }; 490 aprint_debug_dev(self, "intrpin %s, intrtag %d\n", 491 intrname[pa->pa_intrpin], pa->pa_intrline); 492 } 493 #endif 494 495 /* setup softc */ 496 sc->sc_pc = pc; 497 sc->sc_iot = pa->pa_iot; 498 sc->sc_memt = pa->pa_memt; 499 sc->sc_dmat = pa->pa_dmat; 500 sc->sc_tag = pa->pa_tag; 501 sc->sc_function = pa->pa_function; 502 503 memcpy(&sc->sc_pa, pa, sizeof(*pa)); 504 505 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 506 507 /* Disable legacy register mapping. */ 508 switch (sc->sc_chipset) { 509 case CB_RX5C46X: /* fallthrough */ 510 #if 0 511 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 512 case CB_RX5C47X: 513 #endif 514 /* 515 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 516 * cannot be disabled by substituting 0 into PCI_LEGACY 517 * register. Ricoh CardBus bridges have special bits on Bridge 518 * control reg (addr 0x3e on PCI config space). 519 */ 520 reg = pci_conf_read(pc, pa->pa_tag, PCI_BRIDGE_CONTROL_REG); 521 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 522 pci_conf_write(pc, pa->pa_tag, PCI_BRIDGE_CONTROL_REG, reg); 523 break; 524 525 default: 526 /* XXX I don't know proper way to kill legacy I/O. */ 527 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 528 break; 529 } 530 531 if (!pmf_device_register(self, pccbb_suspend, pccbb_resume)) 532 aprint_error_dev(self, "couldn't establish power handler\n"); 533 534 config_defer(self, pccbb_pci_callback); 535 } 536 537 int 538 pccbbdetach(device_t self, int flags) 539 { 540 struct pccbb_softc *sc = device_private(self); 541 pci_chipset_tag_t pc = sc->sc_pa.pa_pc; 542 bus_space_tag_t bmt = sc->sc_base_memt; 543 bus_space_handle_t bmh = sc->sc_base_memh; 544 uint32_t sockmask; 545 int rc; 546 547 if ((rc = config_detach_children(self, flags)) != 0) 548 return rc; 549 550 if (!LIST_EMPTY(&sc->sc_pil)) { 551 panic("%s: interrupt handlers still registered", 552 device_xname(self)); 553 return EBUSY; 554 } 555 556 if (sc->sc_ih != NULL) { 557 pci_intr_disestablish(pc, sc->sc_ih); 558 sc->sc_ih = NULL; 559 } 560 561 /* CSC Interrupt: turn off card detect and power cycle interrupts */ 562 sockmask = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 563 sockmask &= ~(CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | 564 CB_SOCKET_MASK_POWER); 565 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, sockmask); 566 /* reset interrupt */ 567 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 568 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 569 570 switch (sc->sc_flags & (CBB_MEMHMAPPED|CBB_SPECMAPPED)) { 571 case CBB_MEMHMAPPED: 572 bus_space_unmap(bmt, bmh, sc->sc_base_size); 573 break; 574 case CBB_MEMHMAPPED|CBB_SPECMAPPED: 575 #if rbus 576 { 577 pcireg_t sockbase; 578 579 sockbase = pci_conf_read(pc, sc->sc_tag, PCI_SOCKBASE); 580 rbus_space_free(sc->sc_rbus_memt, bmh, 0x1000, 581 NULL); 582 } 583 #else 584 bus_space_free(bmt, bmh, 0x1000); 585 #endif 586 } 587 sc->sc_flags &= ~(CBB_MEMHMAPPED|CBB_SPECMAPPED); 588 589 if (!TAILQ_EMPTY(&sc->sc_iowindow)) 590 aprint_error_dev(self, "i/o windows not empty"); 591 if (!TAILQ_EMPTY(&sc->sc_memwindow)) 592 aprint_error_dev(self, "memory windows not empty"); 593 594 callout_stop(&sc->sc_insert_ch); 595 callout_destroy(&sc->sc_insert_ch); 596 return 0; 597 } 598 599 /* 600 * static void pccbb_pci_callback(device_t self) 601 * 602 * The actual attach routine: get memory space for YENTA register 603 * space, setup YENTA register and route interrupt. 604 * 605 * This function should be deferred because this device may obtain 606 * memory space dynamically. This function must avoid obtaining 607 * memory area which has already kept for another device. 608 */ 609 static void 610 pccbb_pci_callback(device_t self) 611 { 612 struct pccbb_softc *sc = device_private(self); 613 pci_chipset_tag_t pc = sc->sc_pc; 614 bus_addr_t sockbase; 615 struct cbslot_attach_args cba; 616 struct pcmciabus_attach_args paa; 617 struct cardslot_attach_args caa; 618 device_t csc; 619 620 if (!(sc->sc_flags & CBB_MEMHMAPPED)) { 621 /* The socket registers aren't mapped correctly. */ 622 #if rbus 623 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 624 (sc->sc_chipset == CB_RX5C47X 625 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 626 0, &sockbase, &sc->sc_base_memh)) { 627 return; 628 } 629 sc->sc_base_memt = sc->sc_memt; 630 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 631 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 632 device_xname(self), (unsigned long)sockbase, 633 (unsigned long)pci_conf_read(pc, sc->sc_tag, 634 PCI_SOCKBASE))); 635 #else 636 sc->sc_base_memt = sc->sc_memt; 637 #if !defined CBB_PCI_BASE 638 #define CBB_PCI_BASE 0x20000000 639 #endif 640 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 641 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 642 /* cannot allocate memory space */ 643 return; 644 } 645 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 646 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 647 device_xname(self), (unsigned long)sock_base, 648 (unsigned long)pci_conf_read(pc, 649 sc->sc_tag, PCI_SOCKBASE))); 650 #endif 651 sc->sc_flags |= CBB_MEMHMAPPED; 652 } 653 654 /* clear data structure for child device interrupt handlers */ 655 LIST_INIT(&sc->sc_pil); 656 657 /* bus bridge initialization */ 658 pccbb_chipinit(sc); 659 660 sc->sc_pil_intr_enable = 1; 661 662 { 663 u_int32_t sockstat; 664 665 sockstat = bus_space_read_4(sc->sc_base_memt, 666 sc->sc_base_memh, CB_SOCKET_STAT); 667 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 668 sc->sc_flags |= CBB_CARDEXIST; 669 } 670 } 671 672 /* 673 * attach cardbus 674 */ 675 { 676 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 677 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 678 679 /* initialize cbslot_attach */ 680 cba.cba_iot = sc->sc_iot; 681 cba.cba_memt = sc->sc_memt; 682 cba.cba_dmat = sc->sc_dmat; 683 cba.cba_bus = (busreg >> 8) & 0x0ff; 684 cba.cba_cc = (void *)sc; 685 cba.cba_cf = &pccbb_funcs; 686 cba.cba_intrline = 0; /* XXX dummy */ 687 688 #if rbus 689 cba.cba_rbus_iot = sc->sc_rbus_iot; 690 cba.cba_rbus_memt = sc->sc_rbus_memt; 691 #endif 692 693 cba.cba_cacheline = PCI_CACHELINE(bhlc); 694 cba.cba_max_lattimer = PCI_LATTIMER(bhlc); 695 696 aprint_verbose_dev(self, 697 "cacheline 0x%x lattimer 0x%x\n", 698 cba.cba_cacheline, 699 cba.cba_max_lattimer); 700 aprint_verbose_dev(self, "bhlc 0x%x\n", bhlc); 701 #if defined SHOW_REGS 702 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 703 sc->sc_base_memh); 704 #endif 705 } 706 707 pccbb_pcmcia_attach_setup(sc, &paa); 708 caa.caa_cb_attach = NULL; 709 if (cba.cba_bus == 0) 710 aprint_error_dev(self, 711 "secondary bus number uninitialized; try PCI_BUS_FIXUP\n"); 712 else 713 caa.caa_cb_attach = &cba; 714 caa.caa_16_attach = &paa; 715 716 pccbb_intrinit(sc); 717 718 if (NULL != (csc = config_found_ia(self, "pcmciaslot", &caa, 719 cbbprint))) { 720 DPRINTF(("%s: found cardslot\n", __func__)); 721 sc->sc_csc = device_private(csc); 722 } 723 724 return; 725 } 726 727 728 729 730 731 /* 732 * static void pccbb_chipinit(struct pccbb_softc *sc) 733 * 734 * This function initialize YENTA chip registers listed below: 735 * 1) PCI command reg, 736 * 2) PCI and CardBus latency timer, 737 * 3) route PCI interrupt, 738 * 4) close all memory and io windows. 739 * 5) turn off bus power. 740 * 6) card detect and power cycle interrupts on. 741 * 7) clear interrupt 742 */ 743 static void 744 pccbb_chipinit(struct pccbb_softc *sc) 745 { 746 pci_chipset_tag_t pc = sc->sc_pc; 747 pcitag_t tag = sc->sc_tag; 748 bus_space_tag_t bmt = sc->sc_base_memt; 749 bus_space_handle_t bmh = sc->sc_base_memh; 750 pcireg_t bcr, bhlc, cbctl, csr, lscp, mfunc, mrburst, slotctl, sockctl, 751 sysctrl; 752 753 /* 754 * Set PCI command reg. 755 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 756 */ 757 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 758 /* I believe it is harmless. */ 759 csr |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 760 PCI_COMMAND_MASTER_ENABLE); 761 762 /* All O2 Micro chips have broken parity-error reporting 763 * until proven otherwise. The OZ6933 PCI-CardBus Bridge 764 * is known to have the defect---see PR kern/38698. 765 */ 766 if (sc->sc_chipset != CB_O2MICRO) 767 csr |= PCI_COMMAND_PARITY_ENABLE; 768 769 csr |= PCI_COMMAND_SERR_ENABLE; 770 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 771 772 /* 773 * Set CardBus latency timer. 774 */ 775 lscp = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 776 if (PCI_CB_LATENCY(lscp) < 0x20) { 777 lscp &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 778 lscp |= (0x20 << PCI_CB_LATENCY_SHIFT); 779 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, lscp); 780 } 781 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 782 PCI_CB_LATENCY(lscp), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 783 784 /* 785 * Set PCI latency timer. 786 */ 787 bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG); 788 if (PCI_LATTIMER(bhlc) < 0x10) { 789 bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 790 bhlc |= (0x10 << PCI_LATTIMER_SHIFT); 791 pci_conf_write(pc, tag, PCI_BHLC_REG, bhlc); 792 } 793 DPRINTF(("PCI latency timer 0x%x (%x)\n", 794 PCI_LATTIMER(bhlc), pci_conf_read(pc, tag, PCI_BHLC_REG))); 795 796 797 /* Route functional interrupts to PCI. */ 798 bcr = pci_conf_read(pc, tag, PCI_BRIDGE_CONTROL_REG); 799 bcr |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 800 bcr |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 801 /* assert reset */ 802 bcr |= PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT; 803 /* Set master abort mode to 1, forward SERR# from secondary 804 * to primary, and detect parity errors on secondary. 805 */ 806 bcr |= PCI_BRIDGE_CONTROL_MABRT << PCI_BRIDGE_CONTROL_SHIFT; 807 bcr |= PCI_BRIDGE_CONTROL_SERR << PCI_BRIDGE_CONTROL_SHIFT; 808 bcr |= PCI_BRIDGE_CONTROL_PERE << PCI_BRIDGE_CONTROL_SHIFT; 809 pci_conf_write(pc, tag, PCI_BRIDGE_CONTROL_REG, bcr); 810 811 switch (sc->sc_chipset) { 812 case CB_TI113X: 813 cbctl = pci_conf_read(pc, tag, PCI_CBCTRL); 814 /* This bit is shared, but may read as 0 on some chips, so set 815 it explicitly on both functions. */ 816 cbctl |= PCI113X_CBCTRL_PCI_IRQ_ENA; 817 /* CSC intr enable */ 818 cbctl |= PCI113X_CBCTRL_PCI_CSC; 819 /* functional intr prohibit | prohibit ISA routing */ 820 cbctl &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 821 pci_conf_write(pc, tag, PCI_CBCTRL, cbctl); 822 break; 823 824 case CB_TI1420: 825 sysctrl = pci_conf_read(pc, tag, PCI_SYSCTRL); 826 mrburst = pccbb_burstup 827 ? PCI1420_SYSCTRL_MRBURST : PCI1420_SYSCTRL_MRBURSTDN; 828 if ((sysctrl & PCI1420_SYSCTRL_MRBURST) == mrburst) { 829 printf("%s: %swrite bursts enabled\n", 830 device_xname(sc->sc_dev), 831 pccbb_burstup ? "read/" : ""); 832 } else if (pccbb_burstup) { 833 printf("%s: enabling read/write bursts\n", 834 device_xname(sc->sc_dev)); 835 sysctrl |= PCI1420_SYSCTRL_MRBURST; 836 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 837 } else { 838 printf("%s: disabling read bursts, " 839 "enabling write bursts\n", 840 device_xname(sc->sc_dev)); 841 sysctrl |= PCI1420_SYSCTRL_MRBURSTDN; 842 sysctrl &= ~PCI1420_SYSCTRL_MRBURSTUP; 843 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 844 } 845 /*FALLTHROUGH*/ 846 case CB_TI12XX: 847 /* 848 * Some TI 12xx (and [14][45]xx) based pci cards 849 * sometimes have issues with the MFUNC register not 850 * being initialized due to a bad EEPROM on board. 851 * Laptops that this matters on have this register 852 * properly initialized. 853 * 854 * The TI125X parts have a different register. 855 */ 856 mfunc = pci_conf_read(pc, tag, PCI12XX_MFUNC); 857 if (mfunc == 0) { 858 mfunc &= ~PCI12XX_MFUNC_PIN0; 859 mfunc |= PCI12XX_MFUNC_PIN0_INTA; 860 if ((pci_conf_read(pc, tag, PCI_SYSCTRL) & 861 PCI12XX_SYSCTRL_INTRTIE) == 0) { 862 mfunc &= ~PCI12XX_MFUNC_PIN1; 863 mfunc |= PCI12XX_MFUNC_PIN1_INTB; 864 } 865 pci_conf_write(pc, tag, PCI12XX_MFUNC, mfunc); 866 } 867 /* fallthrough */ 868 869 case CB_TI125X: 870 /* 871 * Disable zoom video. Some machines initialize this 872 * improperly and experience has shown that this helps 873 * prevent strange behavior. 874 */ 875 pci_conf_write(pc, tag, PCI12XX_MMCTRL, 0); 876 877 sysctrl = pci_conf_read(pc, tag, PCI_SYSCTRL); 878 sysctrl |= PCI12XX_SYSCTRL_VCCPROT; 879 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 880 cbctl = pci_conf_read(pc, tag, PCI_CBCTRL); 881 cbctl |= PCI12XX_CBCTRL_CSC; 882 pci_conf_write(pc, tag, PCI_CBCTRL, cbctl); 883 break; 884 885 case CB_TOPIC95B: 886 sockctl = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 887 sockctl |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 888 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, sockctl); 889 slotctl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 890 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 891 device_xname(sc->sc_dev), slotctl)); 892 slotctl |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 893 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 894 slotctl &= ~TOPIC_SLOT_CTRL_SWDETECT; 895 DPRINTF(("0x%x\n", slotctl)); 896 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slotctl); 897 break; 898 899 case CB_TOPIC97: 900 slotctl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 901 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 902 device_xname(sc->sc_dev), slotctl)); 903 slotctl |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 904 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 905 slotctl &= ~TOPIC_SLOT_CTRL_SWDETECT; 906 slotctl |= TOPIC97_SLOT_CTRL_PCIINT; 907 slotctl &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 908 DPRINTF(("0x%x\n", slotctl)); 909 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slotctl); 910 /* make sure to assert LV card support bits */ 911 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 912 0x800 + 0x3e, 913 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 914 0x800 + 0x3e) | 0x03); 915 break; 916 } 917 918 /* Close all memory and I/O windows. */ 919 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 920 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 921 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 922 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 923 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 924 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 925 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 926 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 927 928 /* reset 16-bit pcmcia bus */ 929 bus_space_write_1(bmt, bmh, 0x800 + PCIC_INTR, 930 bus_space_read_1(bmt, bmh, 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 931 932 /* turn off power */ 933 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 934 } 935 936 static void 937 pccbb_intrinit(struct pccbb_softc *sc) 938 { 939 pcireg_t sockmask; 940 const char *intrstr = NULL; 941 pci_intr_handle_t ih; 942 pci_chipset_tag_t pc = sc->sc_pc; 943 bus_space_tag_t bmt = sc->sc_base_memt; 944 bus_space_handle_t bmh = sc->sc_base_memh; 945 946 /* Map and establish the interrupt. */ 947 if (pci_intr_map(&sc->sc_pa, &ih)) { 948 aprint_error_dev(sc->sc_dev, "couldn't map interrupt\n"); 949 return; 950 } 951 intrstr = pci_intr_string(pc, ih); 952 953 /* 954 * XXX pccbbintr should be called under the priority lower 955 * than any other hard interupts. 956 */ 957 KASSERT(sc->sc_ih == NULL); 958 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 959 960 if (sc->sc_ih == NULL) { 961 aprint_error_dev(sc->sc_dev, "couldn't establish interrupt"); 962 if (intrstr != NULL) 963 aprint_error(" at %s\n", intrstr); 964 else 965 aprint_error("\n"); 966 return; 967 } 968 969 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 970 971 /* CSC Interrupt: Card detect and power cycle interrupts on */ 972 sockmask = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 973 sockmask |= CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | 974 CB_SOCKET_MASK_POWER; 975 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, sockmask); 976 /* reset interrupt */ 977 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 978 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 979 } 980 981 /* 982 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 983 * struct pcmciabus_attach_args *paa) 984 * 985 * This function attaches 16-bit PCcard bus. 986 */ 987 STATIC void 988 pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 989 struct pcmciabus_attach_args *paa) 990 { 991 struct pcic_handle *ph = &sc->sc_pcmcia_h; 992 #if rbus 993 rbus_tag_t rb; 994 #endif 995 996 /* initialize pcmcia part in pccbb_softc */ 997 ph->ph_parent = sc; 998 /* rest of ph is zero-initialized */ 999 sc->sc_pct = &pccbb_pcmcia_funcs; 1000 1001 /* 1002 * We need to do a few things here: 1003 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 1004 * setting the IRQ numbers to 0. 1005 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 1006 * routing of CSC interrupts (e.g. card removal) to PCI while in 1007 * PCMCIA mode. We just leave this set all the time. 1008 * 3) Enable card insertion/removal interrupts in case the chip also 1009 * needs that while in PCMCIA mode. 1010 * 4) Clear any pending CSC interrupt. 1011 */ 1012 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE); 1013 if (sc->sc_chipset == CB_TI113X) { 1014 Pcic_write(ph, PCIC_CSC_INTR, 0); 1015 } else { 1016 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 1017 Pcic_read(ph, PCIC_CSC); 1018 } 1019 1020 /* initialize pcmcia bus attachment */ 1021 paa->paa_busname = "pcmcia"; 1022 paa->pct = sc->sc_pct; 1023 paa->pch = ph; 1024 paa->iobase = 0; /* I don't use them */ 1025 paa->iosize = 0; 1026 #if rbus 1027 rb = sc->sc_rbus_iot; 1028 paa->iobase = rb->rb_start + rb->rb_offset; 1029 paa->iosize = rb->rb_end - rb->rb_start; 1030 #endif 1031 1032 return; 1033 } 1034 1035 /* 1036 * int pccbbintr(arg) 1037 * void *arg; 1038 * This routine handles the interrupt from Yenta PCI-CardBus bridge 1039 * itself. 1040 */ 1041 int 1042 pccbbintr(void *arg) 1043 { 1044 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1045 u_int32_t sockevent, sockstate; 1046 bus_space_tag_t memt = sc->sc_base_memt; 1047 bus_space_handle_t memh = sc->sc_base_memh; 1048 struct pcic_handle *ph = &sc->sc_pcmcia_h; 1049 1050 if (!device_has_power(sc->sc_dev)) 1051 return 0; 1052 1053 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 1054 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 1055 Pcic_read(ph, PCIC_CSC); 1056 1057 if (sockevent != 0) { 1058 aprint_debug("%s: enter sockevent %" PRIx32 "\n", __func__, 1059 sockevent); 1060 } 1061 1062 /* Sometimes a change of CSTSCHG# accompanies the first 1063 * interrupt from an Atheros WLAN. That generates a 1064 * CB_SOCKET_EVENT_CSTS event on the bridge. The event 1065 * isn't interesting to pccbb(4), so we used to ignore the 1066 * interrupt. Now, let the child devices try to handle 1067 * the interrupt, instead. The Atheros NIC produces 1068 * interrupts more reliably, now: used to be that it would 1069 * only interrupt if the driver avoided powering down the 1070 * NIC's cardslot, and then the NIC would only work after 1071 * it was reset a second time. 1072 */ 1073 if (sockevent == 0 || 1074 (sockevent & ~(CB_SOCKET_EVENT_POWER|CB_SOCKET_EVENT_CD)) != 0) { 1075 /* This intr is not for me: it may be for my child devices. */ 1076 if (sc->sc_pil_intr_enable) { 1077 return pccbbintr_function(sc); 1078 } else { 1079 return 0; 1080 } 1081 } 1082 1083 if (sockevent & CB_SOCKET_EVENT_CD) { 1084 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1085 if (0x00 != (sockstate & CB_SOCKET_STAT_CD)) { 1086 /* A card should be removed. */ 1087 if (sc->sc_flags & CBB_CARDEXIST) { 1088 DPRINTF(("%s: 0x%08x", 1089 device_xname(sc->sc_dev), sockevent)); 1090 DPRINTF((" card removed, 0x%08x\n", sockstate)); 1091 sc->sc_flags &= ~CBB_CARDEXIST; 1092 if (sc->sc_csc->sc_status & 1093 CARDSLOT_STATUS_CARD_16) { 1094 cardslot_event_throw(sc->sc_csc, 1095 CARDSLOT_EVENT_REMOVAL_16); 1096 } else if (sc->sc_csc->sc_status & 1097 CARDSLOT_STATUS_CARD_CB) { 1098 /* Cardbus intr removed */ 1099 cardslot_event_throw(sc->sc_csc, 1100 CARDSLOT_EVENT_REMOVAL_CB); 1101 } 1102 } else if (sc->sc_flags & CBB_INSERTING) { 1103 sc->sc_flags &= ~CBB_INSERTING; 1104 callout_stop(&sc->sc_insert_ch); 1105 } 1106 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 1107 /* 1108 * The pccbbintr may called from powerdown hook when 1109 * the system resumed, to detect the card 1110 * insertion/removal during suspension. 1111 */ 1112 (sc->sc_flags & CBB_CARDEXIST) == 0) { 1113 if (sc->sc_flags & CBB_INSERTING) { 1114 callout_stop(&sc->sc_insert_ch); 1115 } 1116 callout_schedule(&sc->sc_insert_ch, hz / 5); 1117 sc->sc_flags |= CBB_INSERTING; 1118 } 1119 } 1120 1121 /* XXX sockevent == 9 does occur in the wild. handle it. */ 1122 if (sockevent & CB_SOCKET_EVENT_POWER) { 1123 DPRINTF(("Powercycling because of socket event\n")); 1124 /* XXX: Does not happen when attaching a 16-bit card */ 1125 sc->sc_pwrcycle++; 1126 wakeup(&sc->sc_pwrcycle); 1127 } 1128 1129 return (1); 1130 } 1131 1132 /* 1133 * static int pccbbintr_function(struct pccbb_softc *sc) 1134 * 1135 * This function calls each interrupt handler registered at the 1136 * bridge. The interrupt handlers are called in registered order. 1137 */ 1138 static int 1139 pccbbintr_function(struct pccbb_softc *sc) 1140 { 1141 int retval = 0, val; 1142 struct pccbb_intrhand_list *pil; 1143 int s; 1144 1145 LIST_FOREACH(pil, &sc->sc_pil, pil_next) { 1146 s = splraiseipl(pil->pil_icookie); 1147 val = (*pil->pil_func)(pil->pil_arg); 1148 splx(s); 1149 1150 retval = retval == 1 ? 1 : 1151 retval == 0 ? val : val != 0 ? val : retval; 1152 } 1153 1154 return retval; 1155 } 1156 1157 static void 1158 pci113x_insert(void *arg) 1159 { 1160 struct pccbb_softc *sc = arg; 1161 u_int32_t sockevent, sockstate; 1162 1163 if (!(sc->sc_flags & CBB_INSERTING)) { 1164 /* We add a card only under inserting state. */ 1165 return; 1166 } 1167 sc->sc_flags &= ~CBB_INSERTING; 1168 1169 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1170 CB_SOCKET_EVENT); 1171 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1172 CB_SOCKET_STAT); 1173 1174 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1175 DPRINTF(("%s: 0x%08x", device_xname(sc->sc_dev), sockevent)); 1176 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1177 sc->sc_flags |= CBB_CARDEXIST; 1178 /* call pccard interrupt handler here */ 1179 if (sockstate & CB_SOCKET_STAT_16BIT) { 1180 /* 16-bit card found */ 1181 cardslot_event_throw(sc->sc_csc, 1182 CARDSLOT_EVENT_INSERTION_16); 1183 } else if (sockstate & CB_SOCKET_STAT_CB) { 1184 /* cardbus card found */ 1185 cardslot_event_throw(sc->sc_csc, 1186 CARDSLOT_EVENT_INSERTION_CB); 1187 } else { 1188 /* who are you? */ 1189 } 1190 } else { 1191 callout_schedule(&sc->sc_insert_ch, hz / 10); 1192 } 1193 } 1194 1195 #define PCCBB_PCMCIA_OFFSET 0x800 1196 static u_int8_t 1197 pccbb_pcmcia_read(struct pccbb_softc *sc, int reg) 1198 { 1199 bus_space_barrier(sc->sc_base_memt, sc->sc_base_memh, 1200 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1201 1202 return bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 1203 PCCBB_PCMCIA_OFFSET + reg); 1204 } 1205 1206 static void 1207 pccbb_pcmcia_write(struct pccbb_softc *sc, int reg, u_int8_t val) 1208 { 1209 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 1210 PCCBB_PCMCIA_OFFSET + reg, val); 1211 1212 bus_space_barrier(sc->sc_base_memt, sc->sc_base_memh, 1213 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1214 } 1215 1216 /* 1217 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1218 */ 1219 STATIC int 1220 pccbb_ctrl(cardbus_chipset_tag_t ct, int command) 1221 { 1222 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1223 1224 switch (command) { 1225 case CARDBUS_CD: 1226 if (2 == pccbb_detect_card(sc)) { 1227 int retval = 0; 1228 int status = cb_detect_voltage(sc); 1229 if (PCCARD_VCC_5V & status) { 1230 retval |= CARDBUS_5V_CARD; 1231 } 1232 if (PCCARD_VCC_3V & status) { 1233 retval |= CARDBUS_3V_CARD; 1234 } 1235 if (PCCARD_VCC_XV & status) { 1236 retval |= CARDBUS_XV_CARD; 1237 } 1238 if (PCCARD_VCC_YV & status) { 1239 retval |= CARDBUS_YV_CARD; 1240 } 1241 return retval; 1242 } else { 1243 return 0; 1244 } 1245 case CARDBUS_RESET: 1246 return cb_reset(sc); 1247 case CARDBUS_IO_ENABLE: /* fallthrough */ 1248 case CARDBUS_IO_DISABLE: /* fallthrough */ 1249 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1250 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1251 case CARDBUS_BM_ENABLE: /* fallthrough */ 1252 case CARDBUS_BM_DISABLE: /* fallthrough */ 1253 /* XXX: I think we don't need to call this function below. */ 1254 return pccbb_cardenable(sc, command); 1255 } 1256 1257 return 0; 1258 } 1259 1260 STATIC int 1261 pccbb_power_ct(cardbus_chipset_tag_t ct, int command) 1262 { 1263 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1264 1265 return pccbb_power(sc, command); 1266 } 1267 1268 /* 1269 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1270 * This function returns true when it succeeds and returns false when 1271 * it fails. 1272 */ 1273 STATIC int 1274 pccbb_power(struct pccbb_softc *sc, int command) 1275 { 1276 u_int32_t status, osock_ctrl, sock_ctrl, reg_ctrl; 1277 bus_space_tag_t memt = sc->sc_base_memt; 1278 bus_space_handle_t memh = sc->sc_base_memh; 1279 int on = 0, pwrcycle, s, times; 1280 struct timeval before, after, diff; 1281 1282 DPRINTF(("pccbb_power: %s and %s [0x%x]\n", 1283 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1284 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1285 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1286 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1287 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1288 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1289 "UNKNOWN", 1290 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1291 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1292 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1293 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1294 "UNKNOWN", command)); 1295 1296 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1297 osock_ctrl = sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1298 1299 switch (command & CARDBUS_VCCMASK) { 1300 case CARDBUS_VCC_UC: 1301 break; 1302 case CARDBUS_VCC_5V: 1303 on++; 1304 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1305 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1306 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1307 } else { 1308 aprint_error_dev(sc->sc_dev, 1309 "BAD voltage request: no 5 V card\n"); 1310 return 0; 1311 } 1312 break; 1313 case CARDBUS_VCC_3V: 1314 on++; 1315 if (CB_SOCKET_STAT_3VCARD & status) { 1316 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1317 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1318 } else { 1319 aprint_error_dev(sc->sc_dev, 1320 "BAD voltage request: no 3.3 V card\n"); 1321 return 0; 1322 } 1323 break; 1324 case CARDBUS_VCC_0V: 1325 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1326 break; 1327 default: 1328 return 0; /* power NEVER changed */ 1329 } 1330 1331 switch (command & CARDBUS_VPPMASK) { 1332 case CARDBUS_VPP_UC: 1333 break; 1334 case CARDBUS_VPP_0V: 1335 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1336 break; 1337 case CARDBUS_VPP_VCC: 1338 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1339 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1340 break; 1341 case CARDBUS_VPP_12V: 1342 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1343 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1344 break; 1345 } 1346 1347 pwrcycle = sc->sc_pwrcycle; 1348 aprint_debug_dev(sc->sc_dev, "osock_ctrl %#" PRIx32 1349 " sock_ctrl %#" PRIx32 "\n", osock_ctrl, sock_ctrl); 1350 1351 microtime(&before); 1352 s = splbio(); 1353 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1354 1355 /* 1356 * Wait as long as 200ms for a power-cycle interrupt. If 1357 * interrupts are enabled, but the socket has already 1358 * changed to the desired status, keep waiting for the 1359 * interrupt. "Consuming" the interrupt in this way keeps 1360 * the interrupt from prematurely waking some subsequent 1361 * pccbb_power call. 1362 * 1363 * XXX Not every bridge interrupts on the ->OFF transition. 1364 * XXX That's ok, we will time-out after 200ms. 1365 * 1366 * XXX The power cycle event will never happen when attaching 1367 * XXX a 16-bit card. That's ok, we will time-out after 1368 * XXX 200ms. 1369 */ 1370 for (times = 5; --times >= 0; ) { 1371 if (cold) 1372 DELAY(40 * 1000); 1373 else { 1374 (void)tsleep(&sc->sc_pwrcycle, PWAIT, "pccpwr", 1375 hz / 25); 1376 if (pwrcycle == sc->sc_pwrcycle) 1377 continue; 1378 } 1379 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1380 if ((status & CB_SOCKET_STAT_PWRCYCLE) != 0 && on) 1381 break; 1382 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0 && !on) 1383 break; 1384 } 1385 splx(s); 1386 microtime(&after); 1387 timersub(&after, &before, &diff); 1388 aprint_debug_dev(sc->sc_dev, "wait took%s %ld.%06lds\n", 1389 (on && times < 0) ? " too long" : "", diff.tv_sec, diff.tv_usec); 1390 1391 /* 1392 * Ok, wait a bit longer for things to settle. 1393 */ 1394 if (on && sc->sc_chipset == CB_TOPIC95B) 1395 delay_ms(100, sc); 1396 1397 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1398 1399 if (on && sc->sc_chipset != CB_TOPIC95B) { 1400 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0) 1401 aprint_error_dev(sc->sc_dev, "power on failed?\n"); 1402 } 1403 1404 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1405 aprint_error_dev(sc->sc_dev, 1406 "bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1407 sock_ctrl, status); 1408 aprint_error_dev(sc->sc_dev, "disabling socket\n"); 1409 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1410 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1411 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1412 status &= ~CB_SOCKET_STAT_BADVCC; 1413 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, status); 1414 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1415 CB_SOCKET_STAT)); 1416 return 0; 1417 } 1418 1419 if (sc->sc_chipset == CB_TOPIC97) { 1420 reg_ctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL); 1421 reg_ctrl &= ~TOPIC97_REG_CTRL_TESTMODE; 1422 if ((command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V) 1423 reg_ctrl &= ~TOPIC97_REG_CTRL_CLKRUN_ENA; 1424 else 1425 reg_ctrl |= TOPIC97_REG_CTRL_CLKRUN_ENA; 1426 pci_conf_write(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL, reg_ctrl); 1427 } 1428 1429 return 1; /* power changed correctly */ 1430 } 1431 1432 #if defined CB_PCMCIA_POLL 1433 struct cb_poll_str { 1434 void *arg; 1435 int (*func)(void *); 1436 int level; 1437 pccard_chipset_tag_t ct; 1438 int count; 1439 struct callout poll_ch; 1440 }; 1441 1442 static struct cb_poll_str cb_poll[10]; 1443 static int cb_poll_n = 0; 1444 1445 static void cb_pcmcia_poll(void *arg); 1446 1447 static void 1448 cb_pcmcia_poll(void *arg) 1449 { 1450 struct cb_poll_str *poll = arg; 1451 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1452 struct pccbb_softc *sc = psc->cpc_parent; 1453 int s; 1454 u_int32_t spsr; /* socket present-state reg */ 1455 1456 callout_reset(&poll->poll_ch, hz / 10, cb_pcmcia_poll, poll); 1457 switch (poll->level) { 1458 case IPL_NET: 1459 s = splnet(); 1460 break; 1461 case IPL_BIO: 1462 s = splbio(); 1463 break; 1464 case IPL_TTY: /* fallthrough */ 1465 default: 1466 s = spltty(); 1467 break; 1468 } 1469 1470 spsr = 1471 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1472 CB_SOCKET_STAT); 1473 1474 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1475 if (!(spsr & 0x40)) { /* CINT low */ 1476 #else 1477 if (1) { 1478 #endif 1479 if ((*poll->func) (poll->arg) == 1) { 1480 ++poll->count; 1481 printf("intr: reported from poller, 0x%x\n", spsr); 1482 #if defined LEVEL2 1483 } else { 1484 printf("intr: miss! 0x%x\n", spsr); 1485 #endif 1486 } 1487 } 1488 splx(s); 1489 } 1490 #endif /* defined CB_PCMCIA_POLL */ 1491 1492 /* 1493 * static int pccbb_detect_card(struct pccbb_softc *sc) 1494 * return value: 0 if no card exists. 1495 * 1 if 16-bit card exists. 1496 * 2 if cardbus card exists. 1497 */ 1498 static int 1499 pccbb_detect_card(struct pccbb_softc *sc) 1500 { 1501 bus_space_handle_t base_memh = sc->sc_base_memh; 1502 bus_space_tag_t base_memt = sc->sc_base_memt; 1503 u_int32_t sockstat = 1504 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1505 int retval = 0; 1506 1507 /* CD1 and CD2 asserted */ 1508 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1509 /* card must be present */ 1510 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1511 /* NOTACARD DEASSERTED */ 1512 if (CB_SOCKET_STAT_CB & sockstat) { 1513 /* CardBus mode */ 1514 retval = 2; 1515 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1516 /* 16-bit mode */ 1517 retval = 1; 1518 } 1519 } 1520 } 1521 return retval; 1522 } 1523 1524 /* 1525 * STATIC int cb_reset(struct pccbb_softc *sc) 1526 * This function resets CardBus card. 1527 */ 1528 STATIC int 1529 cb_reset(struct pccbb_softc *sc) 1530 { 1531 /* 1532 * Reset Assert at least 20 ms 1533 * Some machines request longer duration. 1534 */ 1535 int reset_duration = 1536 (sc->sc_chipset == CB_RX5C47X ? 400 : 50); 1537 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1538 aprint_debug("%s: enter bcr %" PRIx32 "\n", __func__, bcr); 1539 1540 /* Reset bit Assert (bit 6 at 0x3E) */ 1541 bcr |= PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT; 1542 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr); 1543 aprint_debug("%s: wrote bcr %" PRIx32 "\n", __func__, bcr); 1544 delay_ms(reset_duration, sc); 1545 1546 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1547 /* Reset bit Deassert (bit 6 at 0x3E) */ 1548 bcr &= ~(PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT); 1549 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, 1550 bcr); 1551 aprint_debug("%s: wrote bcr %" PRIx32 "\n", __func__, bcr); 1552 delay_ms(reset_duration, sc); 1553 aprint_debug("%s: end of delay\n", __func__); 1554 } 1555 /* No card found on the slot. Keep Reset. */ 1556 return 1; 1557 } 1558 1559 /* 1560 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1561 * This function detect card Voltage. 1562 */ 1563 STATIC int 1564 cb_detect_voltage(struct pccbb_softc *sc) 1565 { 1566 u_int32_t psr; /* socket present-state reg */ 1567 bus_space_tag_t iot = sc->sc_base_memt; 1568 bus_space_handle_t ioh = sc->sc_base_memh; 1569 int vol = PCCARD_VCC_UKN; /* set 0 */ 1570 1571 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1572 1573 if (0x400u & psr) { 1574 vol |= PCCARD_VCC_5V; 1575 } 1576 if (0x800u & psr) { 1577 vol |= PCCARD_VCC_3V; 1578 } 1579 1580 return vol; 1581 } 1582 1583 STATIC int 1584 cbbprint(void *aux, const char *pcic) 1585 { 1586 #if 0 1587 struct cbslot_attach_args *cba = aux; 1588 1589 if (cba->cba_slot >= 0) { 1590 aprint_normal(" slot %d", cba->cba_slot); 1591 } 1592 #endif 1593 return UNCONF; 1594 } 1595 1596 /* 1597 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1598 * This function enables and disables the card 1599 */ 1600 STATIC int 1601 pccbb_cardenable(struct pccbb_softc *sc, int function) 1602 { 1603 u_int32_t command = 1604 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1605 1606 DPRINTF(("pccbb_cardenable:")); 1607 switch (function) { 1608 case CARDBUS_IO_ENABLE: 1609 command |= PCI_COMMAND_IO_ENABLE; 1610 break; 1611 case CARDBUS_IO_DISABLE: 1612 command &= ~PCI_COMMAND_IO_ENABLE; 1613 break; 1614 case CARDBUS_MEM_ENABLE: 1615 command |= PCI_COMMAND_MEM_ENABLE; 1616 break; 1617 case CARDBUS_MEM_DISABLE: 1618 command &= ~PCI_COMMAND_MEM_ENABLE; 1619 break; 1620 case CARDBUS_BM_ENABLE: 1621 command |= PCI_COMMAND_MASTER_ENABLE; 1622 break; 1623 case CARDBUS_BM_DISABLE: 1624 command &= ~PCI_COMMAND_MASTER_ENABLE; 1625 break; 1626 default: 1627 return 0; 1628 } 1629 1630 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1631 DPRINTF((" command reg 0x%x\n", command)); 1632 return 1; 1633 } 1634 1635 #if !rbus 1636 static int 1637 pccbb_io_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 1638 { 1639 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1640 int basereg; 1641 int limitreg; 1642 1643 if ((win < 0) || (win > 2)) { 1644 #if defined DIAGNOSTIC 1645 printf("cardbus_io_open: window out of range %d\n", win); 1646 #endif 1647 return 0; 1648 } 1649 1650 basereg = win * 8 + PCI_CB_IOBASE0; 1651 limitreg = win * 8 + PCI_CB_IOLIMIT0; 1652 1653 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1654 start, basereg, end, limitreg)); 1655 1656 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1657 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1658 return 1; 1659 } 1660 1661 /* 1662 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1663 */ 1664 static int 1665 pccbb_io_close(cardbus_chipset_tag_t ct, int win) 1666 { 1667 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1668 int basereg; 1669 int limitreg; 1670 1671 if ((win < 0) || (win > 2)) { 1672 #if defined DIAGNOSTIC 1673 printf("cardbus_io_close: window out of range %d\n", win); 1674 #endif 1675 return 0; 1676 } 1677 1678 basereg = win * 8 + PCI_CB_IOBASE0; 1679 limitreg = win * 8 + PCI_CB_IOLIMIT0; 1680 1681 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1682 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1683 return 1; 1684 } 1685 1686 static int 1687 pccbb_mem_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 1688 { 1689 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1690 int basereg; 1691 int limitreg; 1692 1693 if ((win < 0) || (win > 2)) { 1694 #if defined DIAGNOSTIC 1695 printf("cardbus_mem_open: window out of range %d\n", win); 1696 #endif 1697 return 0; 1698 } 1699 1700 basereg = win * 8 + PCI_CB_MEMBASE0; 1701 limitreg = win * 8 + PCI_CB_MEMLIMIT0; 1702 1703 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1704 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1705 return 1; 1706 } 1707 1708 static int 1709 pccbb_mem_close(cardbus_chipset_tag_t ct, int win) 1710 { 1711 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1712 int basereg; 1713 int limitreg; 1714 1715 if ((win < 0) || (win > 2)) { 1716 #if defined DIAGNOSTIC 1717 printf("cardbus_mem_close: window out of range %d\n", win); 1718 #endif 1719 return 0; 1720 } 1721 1722 basereg = win * 8 + PCI_CB_MEMBASE0; 1723 limitreg = win * 8 + PCI_CB_MEMLIMIT0; 1724 1725 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1726 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1727 return 1; 1728 } 1729 #endif 1730 1731 /* 1732 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1733 * int irq, 1734 * int level, 1735 * int (* func)(void *), 1736 * void *arg) 1737 * 1738 * This function registers an interrupt handler at the bridge, in 1739 * order not to call the interrupt handlers of child devices when 1740 * a card-deletion interrupt occurs. 1741 * 1742 * The arguments irq and level are not used. 1743 */ 1744 static void * 1745 pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, cardbus_intr_line_t irq, 1746 int level, int (*func)(void *), void *arg) 1747 { 1748 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1749 1750 return pccbb_intr_establish(sc, irq, level, func, arg); 1751 } 1752 1753 1754 /* 1755 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1756 * void *ih) 1757 * 1758 * This function removes an interrupt handler pointed by ih. 1759 */ 1760 static void 1761 pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih) 1762 { 1763 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1764 1765 pccbb_intr_disestablish(sc, ih); 1766 } 1767 1768 1769 void 1770 pccbb_intr_route(struct pccbb_softc *sc) 1771 { 1772 pcireg_t bcr, cbctrl; 1773 1774 /* initialize bridge intr routing */ 1775 bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1776 bcr &= ~CB_BCR_INTR_IREQ_ENABLE; 1777 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr); 1778 1779 switch (sc->sc_chipset) { 1780 case CB_TI113X: 1781 cbctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1782 /* functional intr enabled */ 1783 cbctrl |= PCI113X_CBCTRL_PCI_INTR; 1784 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, cbctrl); 1785 break; 1786 default: 1787 break; 1788 } 1789 } 1790 1791 /* 1792 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1793 * int irq, 1794 * int level, 1795 * int (* func)(void *), 1796 * void *arg) 1797 * 1798 * This function registers an interrupt handler at the bridge, in 1799 * order not to call the interrupt handlers of child devices when 1800 * a card-deletion interrupt occurs. 1801 * 1802 * The arguments irq is not used because pccbb selects intr vector. 1803 */ 1804 static void * 1805 pccbb_intr_establish(struct pccbb_softc *sc, cardbus_intr_line_t irq, 1806 int level, int (*func)(void *), void *arg) 1807 { 1808 struct pccbb_intrhand_list *pil, *newpil; 1809 1810 DPRINTF(("pccbb_intr_establish start. %p\n", LIST_FIRST(&sc->sc_pil))); 1811 1812 if (LIST_EMPTY(&sc->sc_pil)) { 1813 pccbb_intr_route(sc); 1814 } 1815 1816 /* 1817 * Allocate a room for interrupt handler structure. 1818 */ 1819 if (NULL == (newpil = 1820 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1821 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1822 return NULL; 1823 } 1824 1825 newpil->pil_func = func; 1826 newpil->pil_arg = arg; 1827 newpil->pil_icookie = makeiplcookie(level); 1828 1829 if (LIST_EMPTY(&sc->sc_pil)) { 1830 LIST_INSERT_HEAD(&sc->sc_pil, newpil, pil_next); 1831 } else { 1832 for (pil = LIST_FIRST(&sc->sc_pil); 1833 LIST_NEXT(pil, pil_next) != NULL; 1834 pil = LIST_NEXT(pil, pil_next)); 1835 LIST_INSERT_AFTER(pil, newpil, pil_next); 1836 } 1837 1838 DPRINTF(("pccbb_intr_establish add pil. %p\n", 1839 LIST_FIRST(&sc->sc_pil))); 1840 1841 return newpil; 1842 } 1843 1844 /* 1845 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1846 * void *ih) 1847 * 1848 * This function removes an interrupt handler pointed by ih. ih 1849 * should be the value returned by cardbus_intr_establish() or 1850 * NULL. 1851 * 1852 * When ih is NULL, this function will do nothing. 1853 */ 1854 static void 1855 pccbb_intr_disestablish(struct pccbb_softc *sc, void *ih) 1856 { 1857 struct pccbb_intrhand_list *pil; 1858 pcireg_t reg; 1859 1860 DPRINTF(("pccbb_intr_disestablish start. %p\n", 1861 LIST_FIRST(&sc->sc_pil))); 1862 1863 if (ih == NULL) { 1864 /* intr handler is not set */ 1865 DPRINTF(("pccbb_intr_disestablish: no ih\n")); 1866 return; 1867 } 1868 1869 #ifdef DIAGNOSTIC 1870 LIST_FOREACH(pil, &sc->sc_pil, pil_next) { 1871 DPRINTF(("pccbb_intr_disestablish: pil %p\n", pil)); 1872 if (pil == ih) { 1873 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1874 break; 1875 } 1876 } 1877 if (pil == NULL) { 1878 panic("pccbb_intr_disestablish: %s cannot find pil %p", 1879 device_xname(sc->sc_dev), ih); 1880 } 1881 #endif 1882 1883 pil = (struct pccbb_intrhand_list *)ih; 1884 LIST_REMOVE(pil, pil_next); 1885 free(pil, M_DEVBUF); 1886 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1887 1888 if (LIST_EMPTY(&sc->sc_pil)) { 1889 /* No interrupt handlers */ 1890 1891 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1892 1893 /* stop routing PCI intr */ 1894 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1895 reg |= CB_BCR_INTR_IREQ_ENABLE; 1896 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, reg); 1897 1898 switch (sc->sc_chipset) { 1899 case CB_TI113X: 1900 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1901 /* functional intr disabled */ 1902 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1903 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1904 break; 1905 default: 1906 break; 1907 } 1908 } 1909 } 1910 1911 #if defined SHOW_REGS 1912 static void 1913 cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, bus_space_tag_t memt, 1914 bus_space_handle_t memh) 1915 { 1916 int i; 1917 printf("PCI config regs:"); 1918 for (i = 0; i < 0x50; i += 4) { 1919 if (i % 16 == 0) 1920 printf("\n 0x%02x:", i); 1921 printf(" %08x", pci_conf_read(pc, tag, i)); 1922 } 1923 for (i = 0x80; i < 0xb0; i += 4) { 1924 if (i % 16 == 0) 1925 printf("\n 0x%02x:", i); 1926 printf(" %08x", pci_conf_read(pc, tag, i)); 1927 } 1928 1929 if (memh == 0) { 1930 printf("\n"); 1931 return; 1932 } 1933 1934 printf("\nsocket regs:"); 1935 for (i = 0; i <= 0x10; i += 0x04) 1936 printf(" %08x", bus_space_read_4(memt, memh, i)); 1937 printf("\nExCA regs:"); 1938 for (i = 0; i < 0x08; ++i) 1939 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1940 printf("\n"); 1941 return; 1942 } 1943 #endif 1944 1945 /* 1946 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1947 * int busno, int function) 1948 * This is the function to make a tag to access config space of 1949 * a CardBus Card. It works same as pci_conf_read. 1950 */ 1951 static cardbustag_t 1952 pccbb_make_tag(cardbus_chipset_tag_t cc, int busno, int function) 1953 { 1954 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1955 1956 return pci_make_tag(sc->sc_pc, busno, 0, function); 1957 } 1958 1959 static void 1960 pccbb_free_tag(cardbus_chipset_tag_t cc, cardbustag_t tag) 1961 { 1962 } 1963 1964 /* 1965 * pccbb_conf_read 1966 * 1967 * This is the function to read the config space of a CardBus card. 1968 * It works the same as pci_conf_read(9). 1969 */ 1970 static cardbusreg_t 1971 pccbb_conf_read(cardbus_chipset_tag_t cc, cardbustag_t tag, int offset) 1972 { 1973 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1974 1975 return pci_conf_read(sc->sc_pc, tag, offset); 1976 } 1977 1978 /* 1979 * pccbb_conf_write 1980 * 1981 * This is the function to write the config space of a CardBus 1982 * card. It works the same as pci_conf_write(9). 1983 */ 1984 static void 1985 pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, int reg, 1986 cardbusreg_t val) 1987 { 1988 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1989 1990 pci_conf_write(sc->sc_pc, tag, reg, val); 1991 } 1992 1993 #if 0 1994 STATIC int 1995 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1996 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 1997 int speed, int flags, 1998 bus_space_handle_t * iohp) 1999 #endif 2000 /* 2001 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 2002 * bus_addr_t start, bus_size_t size, 2003 * bus_size_t align, 2004 * struct pcmcia_io_handle *pcihp 2005 * 2006 * This function only allocates I/O region for pccard. This function 2007 * never maps the allocated region to pccard I/O area. 2008 * 2009 * XXX: The interface of this function is not very good, I believe. 2010 */ 2011 STATIC int 2012 pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, 2013 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 2014 { 2015 struct pcic_handle *ph = (struct pcic_handle *)pch; 2016 bus_addr_t ioaddr; 2017 int flags = 0; 2018 bus_space_tag_t iot; 2019 bus_space_handle_t ioh; 2020 bus_addr_t mask; 2021 #if rbus 2022 rbus_tag_t rb; 2023 #endif 2024 if (align == 0) { 2025 align = size; /* XXX: funny??? */ 2026 } 2027 2028 if (start != 0) { 2029 /* XXX: assume all card decode lower 10 bits by its hardware */ 2030 mask = 0x3ff; 2031 /* enforce to use only masked address */ 2032 start &= mask; 2033 } else { 2034 /* 2035 * calculate mask: 2036 * 1. get the most significant bit of size (call it msb). 2037 * 2. compare msb with the value of size. 2038 * 3. if size is larger, shift msb left once. 2039 * 4. obtain mask value to decrement msb. 2040 */ 2041 bus_size_t size_tmp = size; 2042 int shifts = 0; 2043 2044 mask = 1; 2045 while (size_tmp) { 2046 ++shifts; 2047 size_tmp >>= 1; 2048 } 2049 mask = (1 << shifts); 2050 if (mask < size) { 2051 mask <<= 1; 2052 } 2053 --mask; 2054 } 2055 2056 /* 2057 * Allocate some arbitrary I/O space. 2058 */ 2059 2060 iot = ph->ph_parent->sc_iot; 2061 2062 #if rbus 2063 rb = ph->ph_parent->sc_rbus_iot; 2064 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 2065 return 1; 2066 } 2067 DPRINTF(("pccbb_pcmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2068 (u_long) ioaddr, (u_long) size)); 2069 #else 2070 if (start) { 2071 ioaddr = start; 2072 if (bus_space_map(iot, start, size, 0, &ioh)) { 2073 return 1; 2074 } 2075 DPRINTF(("pccbb_pcmcia_io_alloc map port 0x%lx+0x%lx\n", 2076 (u_long) ioaddr, (u_long) size)); 2077 } else { 2078 flags |= PCMCIA_IO_ALLOCATED; 2079 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 2080 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 2081 size, align, 0, 0, &ioaddr, &ioh)) { 2082 /* No room be able to be get. */ 2083 return 1; 2084 } 2085 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2086 (u_long) ioaddr, (u_long) size)); 2087 } 2088 #endif 2089 2090 pcihp->iot = iot; 2091 pcihp->ioh = ioh; 2092 pcihp->addr = ioaddr; 2093 pcihp->size = size; 2094 pcihp->flags = flags; 2095 2096 return 0; 2097 } 2098 2099 /* 2100 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2101 * struct pcmcia_io_handle *pcihp) 2102 * 2103 * This function only frees I/O region for pccard. 2104 * 2105 * XXX: The interface of this function is not very good, I believe. 2106 */ 2107 void 2108 pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2109 struct pcmcia_io_handle *pcihp) 2110 { 2111 #if !rbus 2112 bus_space_tag_t iot = pcihp->iot; 2113 #endif 2114 bus_space_handle_t ioh = pcihp->ioh; 2115 bus_size_t size = pcihp->size; 2116 2117 #if rbus 2118 struct pccbb_softc *sc = 2119 ((struct pcic_handle *)pch)->ph_parent; 2120 rbus_tag_t rb = sc->sc_rbus_iot; 2121 2122 rbus_space_free(rb, ioh, size, NULL); 2123 #else 2124 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 2125 bus_space_free(iot, ioh, size); 2126 else 2127 bus_space_unmap(iot, ioh, size); 2128 #endif 2129 } 2130 2131 /* 2132 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 2133 * bus_addr_t offset, bus_size_t size, 2134 * struct pcmcia_io_handle *pcihp, 2135 * int *windowp) 2136 * 2137 * This function maps the allocated I/O region to pccard. This function 2138 * never allocates any I/O region for pccard I/O area. I don't 2139 * understand why the original authors of pcmciabus separated alloc and 2140 * map. I believe the two must be unite. 2141 * 2142 * XXX: no wait timing control? 2143 */ 2144 int 2145 pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, bus_addr_t offset, 2146 bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp) 2147 { 2148 struct pcic_handle *ph = (struct pcic_handle *)pch; 2149 struct pccbb_softc *sc = ph->ph_parent; 2150 bus_addr_t ioaddr = pcihp->addr + offset; 2151 int i, win; 2152 #if defined CBB_DEBUG 2153 static const char *width_names[] = { "dynamic", "io8", "io16" }; 2154 #endif 2155 2156 /* Sanity check I/O handle. */ 2157 2158 if (ph->ph_parent->sc_iot != pcihp->iot) { 2159 panic("pccbb_pcmcia_io_map iot is bogus"); 2160 } 2161 2162 /* XXX Sanity check offset/size. */ 2163 2164 win = -1; 2165 for (i = 0; i < PCIC_IO_WINS; i++) { 2166 if ((ph->ioalloc & (1 << i)) == 0) { 2167 win = i; 2168 ph->ioalloc |= (1 << i); 2169 break; 2170 } 2171 } 2172 2173 if (win == -1) { 2174 return 1; 2175 } 2176 2177 *windowp = win; 2178 2179 /* XXX this is pretty gross */ 2180 2181 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2182 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2183 2184 /* XXX wtf is this doing here? */ 2185 2186 #if 0 2187 printf(" port 0x%lx", (u_long) ioaddr); 2188 if (size > 1) { 2189 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2190 } 2191 #endif 2192 2193 ph->io[win].addr = ioaddr; 2194 ph->io[win].size = size; 2195 ph->io[win].width = width; 2196 2197 /* actual dirty register-value changing in the function below. */ 2198 pccbb_pcmcia_do_io_map(sc, win); 2199 2200 return 0; 2201 } 2202 2203 /* 2204 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2205 * 2206 * This function changes register-value to map I/O region for pccard. 2207 */ 2208 static void 2209 pccbb_pcmcia_do_io_map(struct pccbb_softc *sc, int win) 2210 { 2211 static u_int8_t pcic_iowidth[3] = { 2212 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2213 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2214 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2215 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2216 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2217 }; 2218 2219 #define PCIC_SIA_START_LOW 0 2220 #define PCIC_SIA_START_HIGH 1 2221 #define PCIC_SIA_STOP_LOW 2 2222 #define PCIC_SIA_STOP_HIGH 3 2223 2224 int regbase_win = 0x8 + win * 0x04; 2225 u_int8_t ioctl, enable; 2226 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2227 2228 DPRINTF(("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx " 2229 "width %d\n", win, (unsigned long)ph->io[win].addr, 2230 (unsigned long)ph->io[win].size, ph->io[win].width * 8)); 2231 2232 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2233 ph->io[win].addr & 0xff); 2234 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2235 (ph->io[win].addr >> 8) & 0xff); 2236 2237 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2238 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2239 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2240 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2241 2242 ioctl = Pcic_read(ph, PCIC_IOCTL); 2243 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2244 switch (win) { 2245 case 0: 2246 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2247 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2248 PCIC_IOCTL_IO0_DATASIZE_MASK); 2249 ioctl |= pcic_iowidth[ph->io[win].width]; 2250 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2251 break; 2252 case 1: 2253 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2254 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2255 PCIC_IOCTL_IO1_DATASIZE_MASK); 2256 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2257 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2258 break; 2259 } 2260 Pcic_write(ph, PCIC_IOCTL, ioctl); 2261 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2262 #if defined(CBB_DEBUG) 2263 { 2264 u_int8_t start_low = 2265 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2266 u_int8_t start_high = 2267 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2268 u_int8_t stop_low = 2269 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2270 u_int8_t stop_high = 2271 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2272 printf("pccbb_pcmcia_do_io_map start %02x %02x, " 2273 "stop %02x %02x, ioctl %02x enable %02x\n", 2274 start_low, start_high, stop_low, stop_high, ioctl, enable); 2275 } 2276 #endif 2277 } 2278 2279 /* 2280 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2281 * 2282 * This function unmaps I/O region. No return value. 2283 */ 2284 STATIC void 2285 pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t pch, int win) 2286 { 2287 struct pcic_handle *ph = (struct pcic_handle *)pch; 2288 int reg; 2289 2290 if (win >= PCIC_IO_WINS || win < 0) { 2291 panic("pccbb_pcmcia_io_unmap: window out of range"); 2292 } 2293 2294 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2295 switch (win) { 2296 case 0: 2297 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2298 break; 2299 case 1: 2300 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2301 break; 2302 } 2303 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2304 2305 ph->ioalloc &= ~(1 << win); 2306 } 2307 2308 static int 2309 pccbb_pcmcia_wait_ready(struct pccbb_softc *sc) 2310 { 2311 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2312 u_int8_t stat; 2313 int i; 2314 2315 /* wait an initial 10ms for quick cards */ 2316 stat = Pcic_read(ph, PCIC_IF_STATUS); 2317 if (stat & PCIC_IF_STATUS_READY) 2318 return (0); 2319 pccbb_pcmcia_delay(sc, 10, "pccwr0"); 2320 for (i = 0; i < 50; i++) { 2321 stat = Pcic_read(ph, PCIC_IF_STATUS); 2322 if (stat & PCIC_IF_STATUS_READY) 2323 return (0); 2324 if ((stat & PCIC_IF_STATUS_CARDDETECT_MASK) != 2325 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2326 return (ENXIO); 2327 /* wait .1s (100ms) each iteration now */ 2328 pccbb_pcmcia_delay(sc, 100, "pccwr1"); 2329 } 2330 2331 printf("pccbb_pcmcia_wait_ready: ready never happened, status=%02x\n", stat); 2332 return (EWOULDBLOCK); 2333 } 2334 2335 /* 2336 * Perform long (msec order) delay. timo is in milliseconds. 2337 */ 2338 static void 2339 pccbb_pcmcia_delay(struct pccbb_softc *sc, int timo, const char *wmesg) 2340 { 2341 #ifdef DIAGNOSTIC 2342 if (timo <= 0) 2343 panic("pccbb_pcmcia_delay: called with timeout %d", timo); 2344 if (!curlwp) 2345 panic("pccbb_pcmcia_delay: called in interrupt context"); 2346 #endif 2347 DPRINTF(("pccbb_pcmcia_delay: \"%s\", sleep %d ms\n", wmesg, timo)); 2348 tsleep(pccbb_pcmcia_delay, PWAIT, wmesg, roundup(timo * hz, 1000) / 1000); 2349 } 2350 2351 /* 2352 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2353 * 2354 * This function enables the card. All information is stored in 2355 * the first argument, pcmcia_chipset_handle_t. 2356 */ 2357 STATIC void 2358 pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2359 { 2360 struct pcic_handle *ph = (struct pcic_handle *)pch; 2361 struct pccbb_softc *sc = ph->ph_parent; 2362 pcireg_t spsr; 2363 int voltage; 2364 int win; 2365 u_int8_t power, intr; 2366 #ifdef DIAGNOSTIC 2367 int reg; 2368 #endif 2369 2370 /* this bit is mostly stolen from pcic_attach_card */ 2371 2372 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2373 2374 /* get card Vcc info */ 2375 spsr = 2376 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2377 CB_SOCKET_STAT); 2378 if (spsr & CB_SOCKET_STAT_5VCARD) { 2379 DPRINTF(("5V card\n")); 2380 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2381 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2382 DPRINTF(("3V card\n")); 2383 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2384 } else { 2385 DPRINTF(("?V card, 0x%x\n", spsr)); /* XXX */ 2386 return; 2387 } 2388 2389 /* disable interrupts; assert RESET */ 2390 intr = Pcic_read(ph, PCIC_INTR); 2391 intr &= PCIC_INTR_ENABLE; 2392 Pcic_write(ph, PCIC_INTR, intr); 2393 2394 /* zero out the address windows */ 2395 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2396 2397 /* power down the socket to reset it, clear the card reset pin */ 2398 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2399 2400 /* power off; assert output enable bit */ 2401 power = PCIC_PWRCTL_OE; 2402 Pcic_write(ph, PCIC_PWRCTL, power); 2403 2404 /* power up the socket */ 2405 if (pccbb_power(sc, voltage) == 0) 2406 return; 2407 2408 /* 2409 * Table 4-18 and figure 4-6 of the PC Card specifiction say: 2410 * Vcc Rising Time (Tpr) = 100ms (handled in pccbb_power() above) 2411 * RESET Width (Th (Hi-z RESET)) = 1ms 2412 * RESET Width (Tw (RESET)) = 10us 2413 * 2414 * some machines require some more time to be settled 2415 * for example old toshiba topic bridges! 2416 * (100ms is added here). 2417 */ 2418 pccbb_pcmcia_delay(sc, 200 + 1, "pccen1"); 2419 2420 /* negate RESET */ 2421 intr |= PCIC_INTR_RESET; 2422 Pcic_write(ph, PCIC_INTR, intr); 2423 2424 /* 2425 * RESET Setup Time (Tsu (RESET)) = 20ms 2426 */ 2427 pccbb_pcmcia_delay(sc, 20, "pccen2"); 2428 2429 #ifdef DIAGNOSTIC 2430 reg = Pcic_read(ph, PCIC_IF_STATUS); 2431 if ((reg & PCIC_IF_STATUS_POWERACTIVE) == 0) 2432 printf("pccbb_pcmcia_socket_enable: no power, status=%x\n", reg); 2433 #endif 2434 2435 /* wait for the chip to finish initializing */ 2436 if (pccbb_pcmcia_wait_ready(sc)) { 2437 #ifdef DIAGNOSTIC 2438 printf("pccbb_pcmcia_socket_enable: never became ready\n"); 2439 #endif 2440 /* XXX return a failure status?? */ 2441 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2442 Pcic_write(ph, PCIC_PWRCTL, 0); 2443 return; 2444 } 2445 2446 /* reinstall all the memory and io mappings */ 2447 for (win = 0; win < PCIC_MEM_WINS; ++win) 2448 if (ph->memalloc & (1 << win)) 2449 pccbb_pcmcia_do_mem_map(sc, win); 2450 for (win = 0; win < PCIC_IO_WINS; ++win) 2451 if (ph->ioalloc & (1 << win)) 2452 pccbb_pcmcia_do_io_map(sc, win); 2453 } 2454 2455 /* 2456 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2457 * 2458 * This function disables the card. All information is stored in 2459 * the first argument, pcmcia_chipset_handle_t. 2460 */ 2461 STATIC void 2462 pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t pch) 2463 { 2464 struct pcic_handle *ph = (struct pcic_handle *)pch; 2465 struct pccbb_softc *sc = ph->ph_parent; 2466 u_int8_t intr; 2467 2468 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2469 2470 /* disable interrupts; assert RESET */ 2471 intr = Pcic_read(ph, PCIC_INTR); 2472 intr &= PCIC_INTR_ENABLE; 2473 Pcic_write(ph, PCIC_INTR, intr); 2474 2475 /* zero out the address windows */ 2476 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2477 2478 /* power down the socket to reset it, clear the card reset pin */ 2479 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2480 2481 /* disable socket: negate output enable bit and power off */ 2482 Pcic_write(ph, PCIC_PWRCTL, 0); 2483 2484 /* 2485 * Vcc Falling Time (Tpf) = 300ms 2486 */ 2487 pccbb_pcmcia_delay(sc, 300, "pccwr1"); 2488 } 2489 2490 STATIC void 2491 pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t pch, int type) 2492 { 2493 struct pcic_handle *ph = (struct pcic_handle *)pch; 2494 u_int8_t intr; 2495 2496 /* set the card type */ 2497 2498 intr = Pcic_read(ph, PCIC_INTR); 2499 intr &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_CARDTYPE_MASK); 2500 if (type == PCMCIA_IFTYPE_IO) 2501 intr |= PCIC_INTR_CARDTYPE_IO; 2502 else 2503 intr |= PCIC_INTR_CARDTYPE_MEM; 2504 Pcic_write(ph, PCIC_INTR, intr); 2505 2506 DPRINTF(("%s: pccbb_pcmcia_socket_settype type %s %02x\n", 2507 device_xname(ph->ph_parent->sc_dev), 2508 ((type == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2509 } 2510 2511 /* 2512 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2513 * 2514 * This function detects whether a card is in the slot or not. 2515 * If a card is inserted, return 1. Otherwise, return 0. 2516 */ 2517 STATIC int 2518 pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch) 2519 { 2520 struct pcic_handle *ph = (struct pcic_handle *)pch; 2521 struct pccbb_softc *sc = ph->ph_parent; 2522 2523 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2524 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2525 } 2526 2527 #if 0 2528 STATIC int 2529 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2530 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2531 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2532 #endif 2533 /* 2534 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2535 * bus_size_t size, 2536 * struct pcmcia_mem_handle *pcmhp) 2537 * 2538 * This function only allocates memory region for pccard. This 2539 * function never maps the allocated region to pccard memory area. 2540 * 2541 * XXX: Why the argument of start address is not in? 2542 */ 2543 STATIC int 2544 pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 2545 struct pcmcia_mem_handle *pcmhp) 2546 { 2547 struct pcic_handle *ph = (struct pcic_handle *)pch; 2548 bus_space_handle_t memh; 2549 bus_addr_t addr; 2550 bus_size_t sizepg; 2551 struct pccbb_softc *sc = ph->ph_parent; 2552 #if rbus 2553 rbus_tag_t rb; 2554 #endif 2555 2556 /* Check that the card is still there. */ 2557 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2558 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2559 return 1; 2560 2561 /* out of sc->memh, allocate as many pages as necessary */ 2562 2563 /* convert size to PCIC pages */ 2564 /* 2565 * This is not enough; when the requested region is on the page 2566 * boundaries, this may calculate wrong result. 2567 */ 2568 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2569 #if 0 2570 if (sizepg > PCIC_MAX_MEM_PAGES) { 2571 return 1; 2572 } 2573 #endif 2574 2575 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2576 return 1; 2577 } 2578 2579 addr = 0; /* XXX gcc -Wuninitialized */ 2580 2581 #if rbus 2582 rb = sc->sc_rbus_memt; 2583 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2584 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2585 &addr, &memh)) { 2586 return 1; 2587 } 2588 #else 2589 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2590 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2591 0, /* boundary */ 2592 0, /* flags */ 2593 &addr, &memh)) { 2594 return 1; 2595 } 2596 #endif 2597 2598 DPRINTF(("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, " 2599 "realsize 0x%lx\n", (unsigned long)addr, (unsigned long)size, 2600 (unsigned long)sizepg * PCIC_MEM_PAGESIZE)); 2601 2602 pcmhp->memt = sc->sc_memt; 2603 pcmhp->memh = memh; 2604 pcmhp->addr = addr; 2605 pcmhp->size = size; 2606 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2607 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2608 pcmhp->mhandle = 0; 2609 /* No offset??? Funny. */ 2610 2611 return 0; 2612 } 2613 2614 /* 2615 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2616 * struct pcmcia_mem_handle *pcmhp) 2617 * 2618 * This function release the memory space allocated by the function 2619 * pccbb_pcmcia_mem_alloc(). 2620 */ 2621 STATIC void 2622 pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2623 struct pcmcia_mem_handle *pcmhp) 2624 { 2625 #if rbus 2626 struct pcic_handle *ph = (struct pcic_handle *)pch; 2627 struct pccbb_softc *sc = ph->ph_parent; 2628 2629 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2630 #else 2631 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2632 #endif 2633 } 2634 2635 /* 2636 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2637 * 2638 * This function release the memory space allocated by the function 2639 * pccbb_pcmcia_mem_alloc(). 2640 */ 2641 STATIC void 2642 pccbb_pcmcia_do_mem_map(struct pccbb_softc *sc, int win) 2643 { 2644 int regbase_win; 2645 bus_addr_t phys_addr; 2646 bus_addr_t phys_end; 2647 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2648 2649 #define PCIC_SMM_START_LOW 0 2650 #define PCIC_SMM_START_HIGH 1 2651 #define PCIC_SMM_STOP_LOW 2 2652 #define PCIC_SMM_STOP_HIGH 3 2653 #define PCIC_CMA_LOW 4 2654 #define PCIC_CMA_HIGH 5 2655 2656 u_int8_t start_low, start_high = 0; 2657 u_int8_t stop_low, stop_high; 2658 u_int8_t off_low, off_high; 2659 u_int8_t mem_window; 2660 int reg; 2661 2662 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2663 int mem8 = 2664 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2665 || (kind == PCMCIA_MEM_ATTR); 2666 2667 regbase_win = 0x10 + win * 0x08; 2668 2669 phys_addr = ph->mem[win].addr; 2670 phys_end = phys_addr + ph->mem[win].size; 2671 2672 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2673 (unsigned long)phys_addr, (unsigned long)phys_end, 2674 (unsigned long)ph->mem[win].offset)); 2675 2676 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2677 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2678 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2679 2680 /* bit 19:12 */ 2681 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2682 /* bit 23:20 and bit 7 on */ 2683 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2684 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2685 /* bit 31:24, for 32-bit address */ 2686 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2687 2688 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2689 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2690 2691 if (ph->ph_parent->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2692 Pcic_write(ph, 0x40 + win, mem_window); 2693 } 2694 2695 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2696 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2697 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2698 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2699 2700 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2701 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2702 2703 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2704 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2705 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2706 | ((kind == PCMCIA_MEM_ATTR) ? 2707 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2708 2709 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2710 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2711 2712 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2713 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2714 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2715 2716 #if defined(CBB_DEBUG) 2717 { 2718 int r1, r2, r3, r4, r5, r6, r7 = 0; 2719 2720 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2721 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2722 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2723 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2724 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2725 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2726 if (ph->ph_parent->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2727 r7 = Pcic_read(ph, 0x40 + win); 2728 } 2729 2730 printf("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2731 "%02x%02x", win, r1, r2, r3, r4, r5, r6); 2732 if (ph->ph_parent->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2733 printf(" %02x", r7); 2734 } 2735 printf("\n"); 2736 } 2737 #endif 2738 } 2739 2740 /* 2741 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2742 * bus_addr_t card_addr, bus_size_t size, 2743 * struct pcmcia_mem_handle *pcmhp, 2744 * bus_addr_t *offsetp, int *windowp) 2745 * 2746 * This function maps memory space allocated by the function 2747 * pccbb_pcmcia_mem_alloc(). 2748 */ 2749 STATIC int 2750 pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2751 bus_addr_t card_addr, bus_size_t size, struct pcmcia_mem_handle *pcmhp, 2752 bus_addr_t *offsetp, int *windowp) 2753 { 2754 struct pcic_handle *ph = (struct pcic_handle *)pch; 2755 struct pccbb_softc *sc = ph->ph_parent; 2756 bus_addr_t busaddr; 2757 long card_offset; 2758 int win; 2759 2760 /* Check that the card is still there. */ 2761 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2762 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2763 return 1; 2764 2765 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2766 if ((ph->memalloc & (1 << win)) == 0) { 2767 ph->memalloc |= (1 << win); 2768 break; 2769 } 2770 } 2771 2772 if (win == PCIC_MEM_WINS) { 2773 return 1; 2774 } 2775 2776 *windowp = win; 2777 2778 /* XXX this is pretty gross */ 2779 2780 if (ph->ph_parent->sc_memt != pcmhp->memt) { 2781 panic("pccbb_pcmcia_mem_map memt is bogus"); 2782 } 2783 2784 busaddr = pcmhp->addr; 2785 2786 /* 2787 * compute the address offset to the pcmcia address space for the 2788 * pcic. this is intentionally signed. The masks and shifts below 2789 * will cause TRT to happen in the pcic registers. Deal with making 2790 * sure the address is aligned, and return the alignment offset. 2791 */ 2792 2793 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2794 card_addr -= *offsetp; 2795 2796 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2797 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2798 (u_long) card_addr)); 2799 2800 /* 2801 * include the offset in the size, and decrement size by one, since 2802 * the hw wants start/stop 2803 */ 2804 size += *offsetp - 1; 2805 2806 card_offset = (((long)card_addr) - ((long)busaddr)); 2807 2808 ph->mem[win].addr = busaddr; 2809 ph->mem[win].size = size; 2810 ph->mem[win].offset = card_offset; 2811 ph->mem[win].kind = kind; 2812 2813 pccbb_pcmcia_do_mem_map(sc, win); 2814 2815 return 0; 2816 } 2817 2818 /* 2819 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2820 * int window) 2821 * 2822 * This function unmaps memory space which mapped by the function 2823 * pccbb_pcmcia_mem_map(). 2824 */ 2825 STATIC void 2826 pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, int window) 2827 { 2828 struct pcic_handle *ph = (struct pcic_handle *)pch; 2829 int reg; 2830 2831 if (window >= PCIC_MEM_WINS) { 2832 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2833 } 2834 2835 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2836 reg &= ~(1 << window); 2837 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2838 2839 ph->memalloc &= ~(1 << window); 2840 } 2841 2842 #if defined PCCBB_PCMCIA_POLL 2843 struct pccbb_poll_str { 2844 void *arg; 2845 int (*func)(void *); 2846 int level; 2847 struct pcic_handle *ph; 2848 int count; 2849 int num; 2850 struct callout poll_ch; 2851 }; 2852 2853 static struct pccbb_poll_str pccbb_poll[10]; 2854 static int pccbb_poll_n = 0; 2855 2856 static void pccbb_pcmcia_poll(void *arg); 2857 2858 static void 2859 pccbb_pcmcia_poll(void *arg) 2860 { 2861 struct pccbb_poll_str *poll = arg; 2862 struct pcic_handle *ph = poll->ph; 2863 struct pccbb_softc *sc = ph->sc; 2864 int s; 2865 u_int32_t spsr; /* socket present-state reg */ 2866 2867 callout_reset(&poll->poll_ch, hz * 2, pccbb_pcmcia_poll, arg); 2868 switch (poll->level) { 2869 case IPL_NET: 2870 s = splnet(); 2871 break; 2872 case IPL_BIO: 2873 s = splbio(); 2874 break; 2875 case IPL_TTY: /* fallthrough */ 2876 default: 2877 s = spltty(); 2878 break; 2879 } 2880 2881 spsr = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2882 CB_SOCKET_STAT); 2883 2884 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2885 if (!(spsr & 0x40)) /* CINT low */ 2886 #else 2887 if (1) 2888 #endif 2889 { 2890 if ((*poll->func) (poll->arg) > 0) { 2891 ++poll->count; 2892 /* printf("intr: reported from poller, 0x%x\n", spsr); */ 2893 #if defined LEVEL2 2894 } else { 2895 printf("intr: miss! 0x%x\n", spsr); 2896 #endif 2897 } 2898 } 2899 splx(s); 2900 } 2901 #endif /* defined CB_PCMCIA_POLL */ 2902 2903 /* 2904 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2905 * struct pcmcia_function *pf, 2906 * int ipl, 2907 * int (*func)(void *), 2908 * void *arg); 2909 * 2910 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2911 */ 2912 STATIC void * 2913 pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2914 struct pcmcia_function *pf, int ipl, int (*func)(void *), void *arg) 2915 { 2916 struct pcic_handle *ph = (struct pcic_handle *)pch; 2917 struct pccbb_softc *sc = ph->ph_parent; 2918 2919 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2920 /* what should I do? */ 2921 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2922 DPRINTF(("%s does not provide edge nor pulse " 2923 "interrupt\n", device_xname(sc->sc_dev))); 2924 return NULL; 2925 } 2926 /* 2927 * XXX Noooooo! The interrupt flag must set properly!! 2928 * dumb pcmcia driver!! 2929 */ 2930 } 2931 2932 return pccbb_intr_establish(sc, 0, ipl, func, arg); 2933 } 2934 2935 /* 2936 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2937 * void *ih) 2938 * 2939 * This function disables PC-Card interrupt. 2940 */ 2941 STATIC void 2942 pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 2943 { 2944 struct pcic_handle *ph = (struct pcic_handle *)pch; 2945 struct pccbb_softc *sc = ph->ph_parent; 2946 2947 pccbb_intr_disestablish(sc, ih); 2948 } 2949 2950 #if rbus 2951 /* 2952 * static int 2953 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2954 * bus_addr_t addr, bus_size_t size, 2955 * bus_addr_t mask, bus_size_t align, 2956 * int flags, bus_addr_t *addrp; 2957 * bus_space_handle_t *bshp) 2958 * 2959 * This function allocates a portion of memory or io space for 2960 * clients. This function is called from CardBus card drivers. 2961 */ 2962 static int 2963 pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2964 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 2965 int flags, bus_addr_t *addrp, bus_space_handle_t *bshp) 2966 { 2967 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2968 2969 DPRINTF(("pccbb_rbus_cb_space_alloc: addr 0x%lx, size 0x%lx, " 2970 "mask 0x%lx, align 0x%lx\n", (unsigned long)addr, 2971 (unsigned long)size, (unsigned long)mask, (unsigned long)align)); 2972 2973 if (align == 0) { 2974 align = size; 2975 } 2976 2977 if (rb->rb_bt == sc->sc_memt) { 2978 if (align < 16) { 2979 return 1; 2980 } 2981 /* 2982 * XXX: align more than 0x1000 to avoid overwrapping 2983 * memory windows for two or more devices. 0x1000 2984 * means memory window's granularity. 2985 * 2986 * Two or more devices should be able to share same 2987 * memory window region. However, overrapping memory 2988 * window is not good because some devices, such as 2989 * 3Com 3C575[BC], have a broken address decoder and 2990 * intrude other's memory region. 2991 */ 2992 if (align < 0x1000) { 2993 align = 0x1000; 2994 } 2995 } else if (rb->rb_bt == sc->sc_iot) { 2996 if (align < 4) { 2997 return 1; 2998 } 2999 /* XXX: hack for avoiding ISA image */ 3000 if (mask < 0x0100) { 3001 mask = 0x3ff; 3002 addr = 0x300; 3003 } 3004 3005 } else { 3006 DPRINTF(("pccbb_rbus_cb_space_alloc: Bus space tag 0x%lx is " 3007 "NOT used. io: 0x%lx, mem: 0x%lx\n", 3008 (unsigned long)rb->rb_bt, (unsigned long)sc->sc_iot, 3009 (unsigned long)sc->sc_memt)); 3010 return 1; 3011 /* XXX: panic here? */ 3012 } 3013 3014 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 3015 aprint_normal_dev(sc->sc_dev, "<rbus> no bus space\n"); 3016 return 1; 3017 } 3018 3019 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 3020 3021 return 0; 3022 } 3023 3024 /* 3025 * static int 3026 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 3027 * bus_space_handle_t *bshp, bus_size_t size); 3028 * 3029 * This function is called from CardBus card drivers. 3030 */ 3031 static int 3032 pccbb_rbus_cb_space_free(cardbus_chipset_tag_t ct, rbus_tag_t rb, 3033 bus_space_handle_t bsh, bus_size_t size) 3034 { 3035 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 3036 bus_space_tag_t bt = rb->rb_bt; 3037 3038 pccbb_close_win(sc, bt, bsh, size); 3039 3040 if (bt == sc->sc_memt) { 3041 } else if (bt == sc->sc_iot) { 3042 } else { 3043 return 1; 3044 /* XXX: panic here? */ 3045 } 3046 3047 return rbus_space_free(rb, bsh, size, NULL); 3048 } 3049 #endif /* rbus */ 3050 3051 #if rbus 3052 3053 static int 3054 pccbb_open_win(struct pccbb_softc *sc, bus_space_tag_t bst, bus_addr_t addr, 3055 bus_size_t size, bus_space_handle_t bsh, int flags) 3056 { 3057 struct pccbb_win_chain_head *head; 3058 bus_addr_t align; 3059 3060 head = &sc->sc_iowindow; 3061 align = 0x04; 3062 if (sc->sc_memt == bst) { 3063 head = &sc->sc_memwindow; 3064 align = 0x1000; 3065 DPRINTF(("using memory window, 0x%lx 0x%lx 0x%lx\n\n", 3066 (unsigned long)sc->sc_iot, (unsigned long)sc->sc_memt, 3067 (unsigned long)bst)); 3068 } 3069 3070 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 3071 aprint_error_dev(sc->sc_dev, 3072 "pccbb_open_win: %s winlist insert failed\n", 3073 (head == &sc->sc_memwindow) ? "mem" : "io"); 3074 } 3075 pccbb_winset(align, sc, bst); 3076 3077 return 0; 3078 } 3079 3080 static int 3081 pccbb_close_win(struct pccbb_softc *sc, bus_space_tag_t bst, 3082 bus_space_handle_t bsh, bus_size_t size) 3083 { 3084 struct pccbb_win_chain_head *head; 3085 bus_addr_t align; 3086 3087 head = &sc->sc_iowindow; 3088 align = 0x04; 3089 if (sc->sc_memt == bst) { 3090 head = &sc->sc_memwindow; 3091 align = 0x1000; 3092 } 3093 3094 if (pccbb_winlist_delete(head, bsh, size)) { 3095 aprint_error_dev(sc->sc_dev, 3096 "pccbb_close_win: %s winlist delete failed\n", 3097 (head == &sc->sc_memwindow) ? "mem" : "io"); 3098 } 3099 pccbb_winset(align, sc, bst); 3100 3101 return 0; 3102 } 3103 3104 static int 3105 pccbb_winlist_insert(struct pccbb_win_chain_head *head, bus_addr_t start, 3106 bus_size_t size, bus_space_handle_t bsh, int flags) 3107 { 3108 struct pccbb_win_chain *chainp, *elem; 3109 3110 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 3111 M_NOWAIT)) == NULL) 3112 return (1); /* fail */ 3113 3114 elem->wc_start = start; 3115 elem->wc_end = start + (size - 1); 3116 elem->wc_handle = bsh; 3117 elem->wc_flags = flags; 3118 3119 TAILQ_FOREACH(chainp, head, wc_list) { 3120 if (chainp->wc_end >= start) 3121 break; 3122 } 3123 if (chainp != NULL) 3124 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 3125 else 3126 TAILQ_INSERT_TAIL(head, elem, wc_list); 3127 return (0); 3128 } 3129 3130 static int 3131 pccbb_winlist_delete(struct pccbb_win_chain_head *head, bus_space_handle_t bsh, 3132 bus_size_t size) 3133 { 3134 struct pccbb_win_chain *chainp; 3135 3136 TAILQ_FOREACH(chainp, head, wc_list) { 3137 if (memcmp(&chainp->wc_handle, &bsh, sizeof(bsh)) == 0) 3138 break; 3139 } 3140 if (chainp == NULL) 3141 return 1; /* fail: no candidate to remove */ 3142 3143 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 3144 printf("pccbb_winlist_delete: window 0x%lx size " 3145 "inconsistent: 0x%lx, 0x%lx\n", 3146 (unsigned long)chainp->wc_start, 3147 (unsigned long)(chainp->wc_end - chainp->wc_start), 3148 (unsigned long)(size - 1)); 3149 return 1; 3150 } 3151 3152 TAILQ_REMOVE(head, chainp, wc_list); 3153 free(chainp, M_DEVBUF); 3154 3155 return 0; 3156 } 3157 3158 static void 3159 pccbb_winset(bus_addr_t align, struct pccbb_softc *sc, bus_space_tag_t bst) 3160 { 3161 pci_chipset_tag_t pc; 3162 pcitag_t tag; 3163 bus_addr_t mask = ~(align - 1); 3164 struct { 3165 cardbusreg_t win_start; 3166 cardbusreg_t win_limit; 3167 int win_flags; 3168 } win[2]; 3169 struct pccbb_win_chain *chainp; 3170 int offs; 3171 3172 win[0].win_start = win[1].win_start = 0xffffffff; 3173 win[0].win_limit = win[1].win_limit = 0; 3174 win[0].win_flags = win[1].win_flags = 0; 3175 3176 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3177 offs = PCI_CB_IOBASE0; 3178 if (sc->sc_memt == bst) { 3179 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3180 offs = PCI_CB_MEMBASE0; 3181 } 3182 3183 if (chainp != NULL) { 3184 win[0].win_start = chainp->wc_start & mask; 3185 win[0].win_limit = chainp->wc_end & mask; 3186 win[0].win_flags = chainp->wc_flags; 3187 chainp = TAILQ_NEXT(chainp, wc_list); 3188 } 3189 3190 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3191 if (win[1].win_start == 0xffffffff) { 3192 /* window 1 is not used */ 3193 if ((win[0].win_flags == chainp->wc_flags) && 3194 (win[0].win_limit + align >= 3195 (chainp->wc_start & mask))) { 3196 /* concatenate */ 3197 win[0].win_limit = chainp->wc_end & mask; 3198 } else { 3199 /* make new window */ 3200 win[1].win_start = chainp->wc_start & mask; 3201 win[1].win_limit = chainp->wc_end & mask; 3202 win[1].win_flags = chainp->wc_flags; 3203 } 3204 continue; 3205 } 3206 3207 /* Both windows are engaged. */ 3208 if (win[0].win_flags == win[1].win_flags) { 3209 /* same flags */ 3210 if (win[0].win_flags == chainp->wc_flags) { 3211 if (win[1].win_start - (win[0].win_limit + 3212 align) < 3213 (chainp->wc_start & mask) - 3214 ((chainp->wc_end & mask) + align)) { 3215 /* 3216 * merge window 0 and 1, and set win1 3217 * to chainp 3218 */ 3219 win[0].win_limit = win[1].win_limit; 3220 win[1].win_start = 3221 chainp->wc_start & mask; 3222 win[1].win_limit = 3223 chainp->wc_end & mask; 3224 } else { 3225 win[1].win_limit = 3226 chainp->wc_end & mask; 3227 } 3228 } else { 3229 /* different flags */ 3230 3231 /* concatenate win0 and win1 */ 3232 win[0].win_limit = win[1].win_limit; 3233 /* allocate win[1] to new space */ 3234 win[1].win_start = chainp->wc_start & mask; 3235 win[1].win_limit = chainp->wc_end & mask; 3236 win[1].win_flags = chainp->wc_flags; 3237 } 3238 } else { 3239 /* the flags of win[0] and win[1] is different */ 3240 if (win[0].win_flags == chainp->wc_flags) { 3241 win[0].win_limit = chainp->wc_end & mask; 3242 /* 3243 * XXX this creates overlapping windows, so 3244 * what should the poor bridge do if one is 3245 * cachable, and the other is not? 3246 */ 3247 aprint_error_dev(sc->sc_dev, 3248 "overlapping windows\n"); 3249 } else { 3250 win[1].win_limit = chainp->wc_end & mask; 3251 } 3252 } 3253 } 3254 3255 pc = sc->sc_pc; 3256 tag = sc->sc_tag; 3257 pci_conf_write(pc, tag, offs, win[0].win_start); 3258 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3259 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3260 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3261 DPRINTF(("--pccbb_winset: win0 [0x%lx, 0x%lx), win1 [0x%lx, 0x%lx)\n", 3262 (unsigned long)pci_conf_read(pc, tag, offs), 3263 (unsigned long)pci_conf_read(pc, tag, offs + 4) + align, 3264 (unsigned long)pci_conf_read(pc, tag, offs + 8), 3265 (unsigned long)pci_conf_read(pc, tag, offs + 12) + align)); 3266 3267 if (bst == sc->sc_memt) { 3268 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BRIDGE_CONTROL_REG); 3269 3270 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 3271 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 3272 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3273 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 3274 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3275 pci_conf_write(pc, tag, PCI_BRIDGE_CONTROL_REG, bcr); 3276 } 3277 } 3278 3279 #endif /* rbus */ 3280 3281 static bool 3282 pccbb_suspend(device_t dv PMF_FN_ARGS) 3283 { 3284 struct pccbb_softc *sc = device_private(dv); 3285 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3286 bus_space_handle_t base_memh = sc->sc_base_memh; 3287 pcireg_t reg; 3288 3289 if (sc->sc_pil_intr_enable) 3290 (void)pccbbintr_function(sc); 3291 sc->sc_pil_intr_enable = 0; 3292 3293 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3294 /* Disable interrupts. */ 3295 reg &= ~(CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER); 3296 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3297 /* XXX joerg Disable power to the socket? */ 3298 3299 /* XXX flush PCI write */ 3300 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3301 3302 /* reset interrupt */ 3303 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, 3304 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT)); 3305 /* XXX flush PCI write */ 3306 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3307 3308 if (sc->sc_ih != NULL) { 3309 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 3310 sc->sc_ih = NULL; 3311 } 3312 3313 return true; 3314 } 3315 3316 static bool 3317 pccbb_resume(device_t dv PMF_FN_ARGS) 3318 { 3319 struct pccbb_softc *sc = device_private(dv); 3320 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3321 bus_space_handle_t base_memh = sc->sc_base_memh; 3322 pcireg_t reg; 3323 3324 pccbb_chipinit(sc); 3325 pccbb_intrinit(sc); 3326 /* setup memory and io space window for CB */ 3327 pccbb_winset(0x1000, sc, sc->sc_memt); 3328 pccbb_winset(0x04, sc, sc->sc_iot); 3329 3330 /* CSC Interrupt: Card detect interrupt on */ 3331 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3332 /* Card detect intr is turned on. */ 3333 reg |= CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; 3334 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3335 /* reset interrupt */ 3336 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3337 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3338 3339 /* 3340 * check for card insertion or removal during suspend period. 3341 * XXX: the code can't cope with card swap (remove then 3342 * insert). how can we detect such situation? 3343 */ 3344 (void)pccbbintr(sc); 3345 3346 sc->sc_pil_intr_enable = 1; 3347 3348 return true; 3349 } 3350
Indexes created Fri Sep 26 08:10:20 GMT 2025