pccbb.c revision 1.177
1 /* $NetBSD: pccbb.c,v 1.177 2008/06/26 20:57:10 drochner Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: pccbb.c,v 1.177 2008/06/26 20:57:10 drochner Exp $"); 35 36 /* 37 #define CBB_DEBUG 38 #define SHOW_REGS 39 */ 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/kernel.h> 44 #include <sys/errno.h> 45 #include <sys/ioctl.h> 46 #include <sys/reboot.h> /* for bootverbose */ 47 #include <sys/syslog.h> 48 #include <sys/device.h> 49 #include <sys/malloc.h> 50 #include <sys/proc.h> 51 52 #include <sys/intr.h> 53 #include <sys/bus.h> 54 55 #include <dev/pci/pcivar.h> 56 #include <dev/pci/pcireg.h> 57 #include <dev/pci/pcidevs.h> 58 59 #include <dev/pci/pccbbreg.h> 60 61 #include <dev/cardbus/cardslotvar.h> 62 63 #include <dev/cardbus/cardbusvar.h> 64 65 #include <dev/pcmcia/pcmciareg.h> 66 #include <dev/pcmcia/pcmciavar.h> 67 68 #include <dev/ic/i82365reg.h> 69 #include <dev/pci/pccbbvar.h> 70 71 #ifndef __NetBSD_Version__ 72 struct cfdriver cbb_cd = { 73 NULL, "cbb", DV_DULL 74 }; 75 #endif 76 77 #ifdef CBB_DEBUG 78 #define DPRINTF(x) printf x 79 #define STATIC 80 #else 81 #define DPRINTF(x) 82 #define STATIC static 83 #endif 84 85 int pccbb_burstup = 1; 86 87 /* 88 * delay_ms() is wait in milliseconds. It should be used instead 89 * of delay() if you want to wait more than 1 ms. 90 */ 91 static inline void 92 delay_ms(int millis, void *param) 93 { 94 if (cold) 95 delay(millis * 1000); 96 else 97 tsleep(param, PWAIT, "pccbb", MAX(2, hz * millis / 1000)); 98 } 99 100 int pcicbbmatch(device_t, struct cfdata *, void *); 101 void pccbbattach(device_t, device_t, void *); 102 int pccbbdetach(device_t, int); 103 int pccbbintr(void *); 104 static void pci113x_insert(void *); 105 static int pccbbintr_function(struct pccbb_softc *); 106 107 static int pccbb_detect_card(struct pccbb_softc *); 108 109 static void pccbb_pcmcia_write(struct pccbb_softc *, int, u_int8_t); 110 static u_int8_t pccbb_pcmcia_read(struct pccbb_softc *, int); 111 #define Pcic_read(sc, reg) pccbb_pcmcia_read((sc), (reg)) 112 #define Pcic_write(sc, reg, val) pccbb_pcmcia_write((sc), (reg), (val)) 113 114 STATIC int cb_reset(struct pccbb_softc *); 115 STATIC int cb_detect_voltage(struct pccbb_softc *); 116 STATIC int cbbprint(void *, const char *); 117 118 static int cb_chipset(u_int32_t, int *); 119 STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *, 120 struct pcmciabus_attach_args *); 121 122 STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int); 123 STATIC int pccbb_power(struct pccbb_softc *sc, int); 124 STATIC int pccbb_power_ct(cardbus_chipset_tag_t, int); 125 STATIC int pccbb_cardenable(struct pccbb_softc * sc, int function); 126 #if !rbus 127 static int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 128 static int pccbb_io_close(cardbus_chipset_tag_t, int); 129 static int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 130 static int pccbb_mem_close(cardbus_chipset_tag_t, int); 131 #endif /* !rbus */ 132 static void *pccbb_intr_establish(struct pccbb_softc *, 133 cardbus_intr_line_t irq, int level, int (*ih) (void *), void *sc); 134 static void pccbb_intr_disestablish(struct pccbb_softc *, void *ih); 135 136 static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t, 137 cardbus_intr_line_t irq, int level, int (*ih) (void *), void *sc); 138 static void pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih); 139 140 static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t, int, int); 141 static void pccbb_free_tag(cardbus_chipset_tag_t, cardbustag_t); 142 static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t, cardbustag_t, int); 143 static void pccbb_conf_write(cardbus_chipset_tag_t, cardbustag_t, int, 144 cardbusreg_t); 145 static void pccbb_chipinit(struct pccbb_softc *); 146 static void pccbb_intrinit(struct pccbb_softc *); 147 148 STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 149 struct pcmcia_mem_handle *); 150 STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t, 151 struct pcmcia_mem_handle *); 152 STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 153 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *); 154 STATIC void pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t, int); 155 STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 156 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 157 STATIC void pccbb_pcmcia_io_free(pcmcia_chipset_handle_t, 158 struct pcmcia_io_handle *); 159 STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 160 bus_size_t, struct pcmcia_io_handle *, int *); 161 STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t, int); 162 STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t, 163 struct pcmcia_function *, int, int (*)(void *), void *); 164 STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t, void *); 165 STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t); 166 STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t); 167 STATIC void pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t, int); 168 STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch); 169 170 static int pccbb_pcmcia_wait_ready(struct pccbb_softc *); 171 static void pccbb_pcmcia_delay(struct pccbb_softc *, int, const char *); 172 173 static void pccbb_pcmcia_do_io_map(struct pccbb_softc *, int); 174 static void pccbb_pcmcia_do_mem_map(struct pccbb_softc *, int); 175 176 /* bus-space allocation and deallocation functions */ 177 #if rbus 178 179 static int pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t, rbus_tag_t, 180 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 181 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp); 182 static int pccbb_rbus_cb_space_free(cardbus_chipset_tag_t, rbus_tag_t, 183 bus_space_handle_t, bus_size_t); 184 185 #endif /* rbus */ 186 187 #if rbus 188 189 static int pccbb_open_win(struct pccbb_softc *, bus_space_tag_t, 190 bus_addr_t, bus_size_t, bus_space_handle_t, int flags); 191 static int pccbb_close_win(struct pccbb_softc *, bus_space_tag_t, 192 bus_space_handle_t, bus_size_t); 193 static int pccbb_winlist_insert(struct pccbb_win_chain_head *, bus_addr_t, 194 bus_size_t, bus_space_handle_t, int); 195 static int pccbb_winlist_delete(struct pccbb_win_chain_head *, 196 bus_space_handle_t, bus_size_t); 197 static void pccbb_winset(bus_addr_t align, struct pccbb_softc *, 198 bus_space_tag_t); 199 void pccbb_winlist_show(struct pccbb_win_chain *); 200 201 #endif /* rbus */ 202 203 /* for config_defer */ 204 static void pccbb_pci_callback(device_t); 205 206 static bool pccbb_suspend(device_t PMF_FN_PROTO); 207 static bool pccbb_resume(device_t PMF_FN_PROTO); 208 209 #if defined SHOW_REGS 210 static void cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, 211 bus_space_tag_t memt, bus_space_handle_t memh); 212 #endif 213 214 CFATTACH_DECL_NEW(cbb_pci, sizeof(struct pccbb_softc), 215 pcicbbmatch, pccbbattach, pccbbdetach, NULL); 216 217 static const struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 218 pccbb_pcmcia_mem_alloc, 219 pccbb_pcmcia_mem_free, 220 pccbb_pcmcia_mem_map, 221 pccbb_pcmcia_mem_unmap, 222 pccbb_pcmcia_io_alloc, 223 pccbb_pcmcia_io_free, 224 pccbb_pcmcia_io_map, 225 pccbb_pcmcia_io_unmap, 226 pccbb_pcmcia_intr_establish, 227 pccbb_pcmcia_intr_disestablish, 228 pccbb_pcmcia_socket_enable, 229 pccbb_pcmcia_socket_disable, 230 pccbb_pcmcia_socket_settype, 231 pccbb_pcmcia_card_detect 232 }; 233 234 #if rbus 235 static const struct cardbus_functions pccbb_funcs = { 236 pccbb_rbus_cb_space_alloc, 237 pccbb_rbus_cb_space_free, 238 pccbb_cb_intr_establish, 239 pccbb_cb_intr_disestablish, 240 pccbb_ctrl, 241 pccbb_power_ct, 242 pccbb_make_tag, 243 pccbb_free_tag, 244 pccbb_conf_read, 245 pccbb_conf_write, 246 }; 247 #else 248 static const struct cardbus_functions pccbb_funcs = { 249 pccbb_ctrl, 250 pccbb_power_ct, 251 pccbb_mem_open, 252 pccbb_mem_close, 253 pccbb_io_open, 254 pccbb_io_close, 255 pccbb_cb_intr_establish, 256 pccbb_cb_intr_disestablish, 257 pccbb_make_tag, 258 pccbb_conf_read, 259 pccbb_conf_write, 260 }; 261 #endif 262 263 int 264 pcicbbmatch(device_t parent, struct cfdata *match, void *aux) 265 { 266 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 267 268 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 269 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 270 PCI_INTERFACE(pa->pa_class) == 0) { 271 return 1; 272 } 273 274 return 0; 275 } 276 277 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 278 | ((prod) << PCI_PRODUCT_SHIFT)) 279 280 const struct yenta_chipinfo { 281 pcireg_t yc_id; /* vendor tag | product tag */ 282 int yc_chiptype; 283 int yc_flags; 284 } yc_chipsets[] = { 285 /* Texas Instruments chips */ 286 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 287 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 288 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 289 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 290 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI125X, 291 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 292 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 293 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 294 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 295 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 296 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 297 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 298 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI125X, 299 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 300 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI125X, 301 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 302 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 303 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 304 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 305 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 306 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI1420, 307 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 308 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI125X, 309 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 310 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 311 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 312 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1520), CB_TI12XX, 313 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 314 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4410YENTA), CB_TI12XX, 315 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 316 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4520YENTA), CB_TI12XX, 317 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 318 319 /* Ricoh chips */ 320 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 321 PCCBB_PCMCIA_MEM_32}, 322 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 323 PCCBB_PCMCIA_MEM_32}, 324 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 325 PCCBB_PCMCIA_MEM_32}, 326 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 327 PCCBB_PCMCIA_MEM_32}, 328 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 329 PCCBB_PCMCIA_MEM_32}, 330 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 331 PCCBB_PCMCIA_MEM_32}, 332 333 /* Toshiba products */ 334 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 335 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 336 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 337 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 338 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 339 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 340 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 341 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 342 343 /* Cirrus Logic products */ 344 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 345 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 346 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 347 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 348 349 /* O2 Micro products */ 350 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6729), 351 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 352 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6730), 353 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 354 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6832), 355 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 356 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6836), 357 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 358 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6872), 359 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 360 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6922), 361 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 362 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6933), 363 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 364 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6972), 365 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 366 367 /* sentinel, or Generic chip */ 368 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 369 }; 370 371 static int 372 cb_chipset(u_int32_t pci_id, int *flagp) 373 { 374 const struct yenta_chipinfo *yc; 375 376 /* Loop over except the last default entry. */ 377 for (yc = yc_chipsets; yc < yc_chipsets + 378 __arraycount(yc_chipsets) - 1; yc++) 379 if (pci_id == yc->yc_id) 380 break; 381 382 if (flagp != NULL) 383 *flagp = yc->yc_flags; 384 385 return (yc->yc_chiptype); 386 } 387 388 void 389 pccbbattach(device_t parent, device_t self, void *aux) 390 { 391 struct pccbb_softc *sc = device_private(self); 392 struct pci_attach_args *pa = aux; 393 pci_chipset_tag_t pc = pa->pa_pc; 394 pcireg_t busreg, reg, sock_base; 395 bus_addr_t sockbase; 396 char devinfo[256]; 397 int flags; 398 399 #ifdef __HAVE_PCCBB_ATTACH_HOOK 400 pccbb_attach_hook(parent, self, pa); 401 #endif 402 403 sc->sc_dev = self; 404 405 callout_init(&sc->sc_insert_ch, 0); 406 callout_setfunc(&sc->sc_insert_ch, pci113x_insert, sc); 407 408 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 409 410 aprint_naive("\n"); 411 412 pci_devinfo(pa->pa_id, 0, 0, devinfo, sizeof(devinfo)); 413 aprint_normal(": %s (rev. 0x%02x)", devinfo, 414 PCI_REVISION(pa->pa_class)); 415 DPRINTF((" (chipflags %x)", flags)); 416 aprint_normal("\n"); 417 418 TAILQ_INIT(&sc->sc_memwindow); 419 TAILQ_INIT(&sc->sc_iowindow); 420 421 #if rbus 422 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 423 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 424 425 #if 0 426 printf("pa->pa_memt: %08x vs rbus_mem->rb_bt: %08x\n", 427 pa->pa_memt, sc->sc_rbus_memt->rb_bt); 428 #endif 429 #endif /* rbus */ 430 431 sc->sc_flags &= ~CBB_MEMHMAPPED; 432 433 /* 434 * MAP socket registers and ExCA registers on memory-space 435 * When no valid address is set on socket base registers (on pci 436 * config space), get it not polite way. 437 */ 438 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 439 440 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 441 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 442 /* The address must be valid. */ 443 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 444 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, &sc->sc_base_size)) { 445 aprint_error_dev(self, 446 "can't map socket base address 0x%lx\n", 447 (unsigned long)sock_base); 448 /* 449 * I think it's funny: socket base registers must be 450 * mapped on memory space, but ... 451 */ 452 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 453 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 454 &sc->sc_base_size)) { 455 aprint_error_dev(self, 456 "can't map socket base address" 457 " 0x%lx: io mode\n", 458 (unsigned long)sockbase); 459 /* give up... allocate reg space via rbus. */ 460 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 461 } else 462 sc->sc_flags |= CBB_MEMHMAPPED; 463 } else { 464 DPRINTF(("%s: socket base address 0x%lx\n", 465 device_xname(self), 466 (unsigned long)sockbase)); 467 sc->sc_flags |= CBB_MEMHMAPPED; 468 } 469 } 470 471 sc->sc_mem_start = 0; /* XXX */ 472 sc->sc_mem_end = 0xffffffff; /* XXX */ 473 474 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 475 476 /* pccbb_machdep.c end */ 477 478 #if defined CBB_DEBUG 479 { 480 static const char *intrname[] = { "NON", "A", "B", "C", "D" }; 481 aprint_debug_dev(self, "intrpin %s, intrtag %d\n", 482 intrname[pa->pa_intrpin], pa->pa_intrline); 483 } 484 #endif 485 486 /* setup softc */ 487 sc->sc_pc = pc; 488 sc->sc_iot = pa->pa_iot; 489 sc->sc_memt = pa->pa_memt; 490 sc->sc_dmat = pa->pa_dmat; 491 sc->sc_tag = pa->pa_tag; 492 493 memcpy(&sc->sc_pa, pa, sizeof(*pa)); 494 495 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 496 497 /* Disable legacy register mapping. */ 498 switch (sc->sc_chipset) { 499 case CB_RX5C46X: /* fallthrough */ 500 #if 0 501 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 502 case CB_RX5C47X: 503 #endif 504 /* 505 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 506 * cannot be disabled by substituting 0 into PCI_LEGACY 507 * register. Ricoh CardBus bridges have special bits on Bridge 508 * control reg (addr 0x3e on PCI config space). 509 */ 510 reg = pci_conf_read(pc, pa->pa_tag, PCI_BRIDGE_CONTROL_REG); 511 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 512 pci_conf_write(pc, pa->pa_tag, PCI_BRIDGE_CONTROL_REG, reg); 513 break; 514 515 default: 516 /* XXX I don't know proper way to kill legacy I/O. */ 517 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 518 break; 519 } 520 521 if (!pmf_device_register(self, pccbb_suspend, pccbb_resume)) 522 aprint_error_dev(self, "couldn't establish power handler\n"); 523 524 config_defer(self, pccbb_pci_callback); 525 } 526 527 int 528 pccbbdetach(device_t self, int flags) 529 { 530 struct pccbb_softc *sc = device_private(self); 531 pci_chipset_tag_t pc = sc->sc_pa.pa_pc; 532 bus_space_tag_t bmt = sc->sc_base_memt; 533 bus_space_handle_t bmh = sc->sc_base_memh; 534 uint32_t sockmask; 535 int rc; 536 537 if ((rc = config_detach_children(self, flags)) != 0) 538 return rc; 539 540 if (!LIST_EMPTY(&sc->sc_pil)) { 541 panic("%s: interrupt handlers still registered", 542 device_xname(self)); 543 return EBUSY; 544 } 545 546 if (sc->sc_ih != NULL) { 547 pci_intr_disestablish(pc, sc->sc_ih); 548 sc->sc_ih = NULL; 549 } 550 551 /* CSC Interrupt: turn off card detect and power cycle interrupts */ 552 sockmask = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 553 sockmask &= ~(CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | 554 CB_SOCKET_MASK_POWER); 555 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, sockmask); 556 /* reset interrupt */ 557 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 558 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 559 560 switch (sc->sc_flags & (CBB_MEMHMAPPED|CBB_SPECMAPPED)) { 561 case CBB_MEMHMAPPED: 562 bus_space_unmap(bmt, bmh, sc->sc_base_size); 563 break; 564 case CBB_MEMHMAPPED|CBB_SPECMAPPED: 565 #if rbus 566 { 567 pcireg_t sockbase; 568 569 sockbase = pci_conf_read(pc, sc->sc_tag, PCI_SOCKBASE); 570 rbus_space_free(sc->sc_rbus_memt, bmh, 0x1000, 571 NULL); 572 } 573 #else 574 bus_space_free(bmt, bmh, 0x1000); 575 #endif 576 } 577 sc->sc_flags &= ~(CBB_MEMHMAPPED|CBB_SPECMAPPED); 578 579 if (!TAILQ_EMPTY(&sc->sc_iowindow)) 580 aprint_error_dev(self, "i/o windows not empty"); 581 if (!TAILQ_EMPTY(&sc->sc_memwindow)) 582 aprint_error_dev(self, "memory windows not empty"); 583 584 callout_stop(&sc->sc_insert_ch); 585 callout_destroy(&sc->sc_insert_ch); 586 return 0; 587 } 588 589 /* 590 * static void pccbb_pci_callback(device_t self) 591 * 592 * The actual attach routine: get memory space for YENTA register 593 * space, setup YENTA register and route interrupt. 594 * 595 * This function should be deferred because this device may obtain 596 * memory space dynamically. This function must avoid obtaining 597 * memory area which has already kept for another device. 598 */ 599 static void 600 pccbb_pci_callback(device_t self) 601 { 602 struct pccbb_softc *sc = device_private(self); 603 pci_chipset_tag_t pc = sc->sc_pc; 604 bus_addr_t sockbase; 605 struct cbslot_attach_args cba; 606 struct pcmciabus_attach_args paa; 607 struct cardslot_attach_args caa; 608 device_t csc; 609 610 if (!(sc->sc_flags & CBB_MEMHMAPPED)) { 611 /* The socket registers aren't mapped correctly. */ 612 #if rbus 613 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 614 (sc->sc_chipset == CB_RX5C47X 615 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 616 0, &sockbase, &sc->sc_base_memh)) { 617 return; 618 } 619 sc->sc_base_memt = sc->sc_memt; 620 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 621 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 622 device_xname(self), (unsigned long)sockbase, 623 (unsigned long)pci_conf_read(pc, sc->sc_tag, 624 PCI_SOCKBASE))); 625 #else 626 sc->sc_base_memt = sc->sc_memt; 627 #if !defined CBB_PCI_BASE 628 #define CBB_PCI_BASE 0x20000000 629 #endif 630 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 631 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 632 /* cannot allocate memory space */ 633 return; 634 } 635 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 636 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 637 device_xname(self), (unsigned long)sock_base, 638 (unsigned long)pci_conf_read(pc, 639 sc->sc_tag, PCI_SOCKBASE))); 640 #endif 641 sc->sc_flags |= CBB_MEMHMAPPED; 642 } 643 644 /* clear data structure for child device interrupt handlers */ 645 LIST_INIT(&sc->sc_pil); 646 647 /* bus bridge initialization */ 648 pccbb_chipinit(sc); 649 650 sc->sc_pil_intr_enable = 1; 651 652 { 653 u_int32_t sockstat; 654 655 sockstat = bus_space_read_4(sc->sc_base_memt, 656 sc->sc_base_memh, CB_SOCKET_STAT); 657 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 658 sc->sc_flags |= CBB_CARDEXIST; 659 } 660 } 661 662 /* 663 * attach cardbus 664 */ 665 { 666 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 667 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 668 669 /* initialize cbslot_attach */ 670 cba.cba_iot = sc->sc_iot; 671 cba.cba_memt = sc->sc_memt; 672 cba.cba_dmat = sc->sc_dmat; 673 cba.cba_bus = (busreg >> 8) & 0x0ff; 674 cba.cba_cc = (void *)sc; 675 cba.cba_cf = &pccbb_funcs; 676 cba.cba_intrline = 0; /* XXX dummy */ 677 678 #if rbus 679 cba.cba_rbus_iot = sc->sc_rbus_iot; 680 cba.cba_rbus_memt = sc->sc_rbus_memt; 681 #endif 682 683 cba.cba_cacheline = PCI_CACHELINE(bhlc); 684 cba.cba_max_lattimer = PCI_LATTIMER(bhlc); 685 686 aprint_verbose_dev(self, 687 "cacheline 0x%x lattimer 0x%x\n", 688 cba.cba_cacheline, 689 cba.cba_max_lattimer); 690 aprint_verbose_dev(self, "bhlc 0x%x\n", bhlc); 691 #if defined SHOW_REGS 692 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 693 sc->sc_base_memh); 694 #endif 695 } 696 697 pccbb_pcmcia_attach_setup(sc, &paa); 698 caa.caa_cb_attach = NULL; 699 if (cba.cba_bus == 0) 700 aprint_error_dev(self, 701 "secondary bus number uninitialized; try PCI_BUS_FIXUP\n"); 702 else 703 caa.caa_cb_attach = &cba; 704 caa.caa_16_attach = &paa; 705 706 pccbb_intrinit(sc); 707 708 if (NULL != (csc = config_found_ia(self, "pcmciaslot", &caa, 709 cbbprint))) { 710 DPRINTF(("%s: found cardslot\n", __func__)); 711 sc->sc_csc = device_private(csc); 712 } 713 714 return; 715 } 716 717 718 719 720 721 /* 722 * static void pccbb_chipinit(struct pccbb_softc *sc) 723 * 724 * This function initialize YENTA chip registers listed below: 725 * 1) PCI command reg, 726 * 2) PCI and CardBus latency timer, 727 * 3) route PCI interrupt, 728 * 4) close all memory and io windows. 729 * 5) turn off bus power. 730 * 6) card detect and power cycle interrupts on. 731 * 7) clear interrupt 732 */ 733 static void 734 pccbb_chipinit(struct pccbb_softc *sc) 735 { 736 pci_chipset_tag_t pc = sc->sc_pc; 737 pcitag_t tag = sc->sc_tag; 738 bus_space_tag_t bmt = sc->sc_base_memt; 739 bus_space_handle_t bmh = sc->sc_base_memh; 740 pcireg_t bcr, bhlc, cbctl, csr, lscp, mfunc, mrburst, slotctl, sockctl, 741 sysctrl; 742 743 /* 744 * Set PCI command reg. 745 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 746 */ 747 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 748 /* I believe it is harmless. */ 749 csr |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 750 PCI_COMMAND_MASTER_ENABLE); 751 752 /* All O2 Micro chips have broken parity-error reporting 753 * until proven otherwise. The OZ6933 PCI-CardBus Bridge 754 * is known to have the defect---see PR kern/38698. 755 */ 756 if (sc->sc_chipset != CB_O2MICRO) 757 csr |= PCI_COMMAND_PARITY_ENABLE; 758 759 csr |= PCI_COMMAND_SERR_ENABLE; 760 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 761 762 /* 763 * Set CardBus latency timer. 764 */ 765 lscp = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 766 if (PCI_CB_LATENCY(lscp) < 0x20) { 767 lscp &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 768 lscp |= (0x20 << PCI_CB_LATENCY_SHIFT); 769 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, lscp); 770 } 771 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 772 PCI_CB_LATENCY(lscp), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 773 774 /* 775 * Set PCI latency timer. 776 */ 777 bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG); 778 if (PCI_LATTIMER(bhlc) < 0x10) { 779 bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 780 bhlc |= (0x10 << PCI_LATTIMER_SHIFT); 781 pci_conf_write(pc, tag, PCI_BHLC_REG, bhlc); 782 } 783 DPRINTF(("PCI latency timer 0x%x (%x)\n", 784 PCI_LATTIMER(bhlc), pci_conf_read(pc, tag, PCI_BHLC_REG))); 785 786 787 /* Route functional interrupts to PCI. */ 788 bcr = pci_conf_read(pc, tag, PCI_BRIDGE_CONTROL_REG); 789 bcr |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 790 bcr |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 791 /* assert reset */ 792 bcr |= PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT; 793 /* Set master abort mode to 1, forward SERR# from secondary 794 * to primary, and detect parity errors on secondary. 795 */ 796 bcr |= PCI_BRIDGE_CONTROL_MABRT << PCI_BRIDGE_CONTROL_SHIFT; 797 bcr |= PCI_BRIDGE_CONTROL_SERR << PCI_BRIDGE_CONTROL_SHIFT; 798 bcr |= PCI_BRIDGE_CONTROL_PERE << PCI_BRIDGE_CONTROL_SHIFT; 799 pci_conf_write(pc, tag, PCI_BRIDGE_CONTROL_REG, bcr); 800 801 switch (sc->sc_chipset) { 802 case CB_TI113X: 803 cbctl = pci_conf_read(pc, tag, PCI_CBCTRL); 804 /* This bit is shared, but may read as 0 on some chips, so set 805 it explicitly on both functions. */ 806 cbctl |= PCI113X_CBCTRL_PCI_IRQ_ENA; 807 /* CSC intr enable */ 808 cbctl |= PCI113X_CBCTRL_PCI_CSC; 809 /* functional intr prohibit | prohibit ISA routing */ 810 cbctl &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 811 pci_conf_write(pc, tag, PCI_CBCTRL, cbctl); 812 break; 813 814 case CB_TI1420: 815 sysctrl = pci_conf_read(pc, tag, PCI_SYSCTRL); 816 mrburst = pccbb_burstup 817 ? PCI1420_SYSCTRL_MRBURST : PCI1420_SYSCTRL_MRBURSTDN; 818 if ((sysctrl & PCI1420_SYSCTRL_MRBURST) == mrburst) { 819 printf("%s: %swrite bursts enabled\n", 820 device_xname(sc->sc_dev), 821 pccbb_burstup ? "read/" : ""); 822 } else if (pccbb_burstup) { 823 printf("%s: enabling read/write bursts\n", 824 device_xname(sc->sc_dev)); 825 sysctrl |= PCI1420_SYSCTRL_MRBURST; 826 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 827 } else { 828 printf("%s: disabling read bursts, " 829 "enabling write bursts\n", 830 device_xname(sc->sc_dev)); 831 sysctrl |= PCI1420_SYSCTRL_MRBURSTDN; 832 sysctrl &= ~PCI1420_SYSCTRL_MRBURSTUP; 833 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 834 } 835 /*FALLTHROUGH*/ 836 case CB_TI12XX: 837 /* 838 * Some TI 12xx (and [14][45]xx) based pci cards 839 * sometimes have issues with the MFUNC register not 840 * being initialized due to a bad EEPROM on board. 841 * Laptops that this matters on have this register 842 * properly initialized. 843 * 844 * The TI125X parts have a different register. 845 */ 846 mfunc = pci_conf_read(pc, tag, PCI12XX_MFUNC); 847 if (mfunc == 0) { 848 mfunc &= ~PCI12XX_MFUNC_PIN0; 849 mfunc |= PCI12XX_MFUNC_PIN0_INTA; 850 if ((pci_conf_read(pc, tag, PCI_SYSCTRL) & 851 PCI12XX_SYSCTRL_INTRTIE) == 0) { 852 mfunc &= ~PCI12XX_MFUNC_PIN1; 853 mfunc |= PCI12XX_MFUNC_PIN1_INTB; 854 } 855 pci_conf_write(pc, tag, PCI12XX_MFUNC, mfunc); 856 } 857 /* fallthrough */ 858 859 case CB_TI125X: 860 /* 861 * Disable zoom video. Some machines initialize this 862 * improperly and experience has shown that this helps 863 * prevent strange behavior. 864 */ 865 pci_conf_write(pc, tag, PCI12XX_MMCTRL, 0); 866 867 sysctrl = pci_conf_read(pc, tag, PCI_SYSCTRL); 868 sysctrl |= PCI12XX_SYSCTRL_VCCPROT; 869 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 870 cbctl = pci_conf_read(pc, tag, PCI_CBCTRL); 871 cbctl |= PCI12XX_CBCTRL_CSC; 872 pci_conf_write(pc, tag, PCI_CBCTRL, cbctl); 873 break; 874 875 case CB_TOPIC95B: 876 sockctl = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 877 sockctl |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 878 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, sockctl); 879 slotctl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 880 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 881 device_xname(sc->sc_dev), slotctl)); 882 slotctl |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 883 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 884 slotctl &= ~TOPIC_SLOT_CTRL_SWDETECT; 885 DPRINTF(("0x%x\n", slotctl)); 886 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slotctl); 887 break; 888 889 case CB_TOPIC97: 890 slotctl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 891 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 892 device_xname(sc->sc_dev), slotctl)); 893 slotctl |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 894 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 895 slotctl &= ~TOPIC_SLOT_CTRL_SWDETECT; 896 slotctl |= TOPIC97_SLOT_CTRL_PCIINT; 897 slotctl &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 898 DPRINTF(("0x%x\n", slotctl)); 899 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slotctl); 900 /* make sure to assert LV card support bits */ 901 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 902 0x800 + 0x3e, 903 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 904 0x800 + 0x3e) | 0x03); 905 break; 906 } 907 908 /* Close all memory and I/O windows. */ 909 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 910 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 911 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 912 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 913 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 914 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 915 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 916 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 917 918 /* reset 16-bit pcmcia bus */ 919 bus_space_write_1(bmt, bmh, 0x800 + PCIC_INTR, 920 bus_space_read_1(bmt, bmh, 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 921 922 /* turn off power */ 923 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 924 } 925 926 static void 927 pccbb_intrinit(struct pccbb_softc *sc) 928 { 929 pcireg_t sockmask; 930 const char *intrstr = NULL; 931 pci_intr_handle_t ih; 932 pci_chipset_tag_t pc = sc->sc_pc; 933 bus_space_tag_t bmt = sc->sc_base_memt; 934 bus_space_handle_t bmh = sc->sc_base_memh; 935 936 /* Map and establish the interrupt. */ 937 if (pci_intr_map(&sc->sc_pa, &ih)) { 938 aprint_error_dev(sc->sc_dev, "couldn't map interrupt\n"); 939 return; 940 } 941 intrstr = pci_intr_string(pc, ih); 942 943 /* 944 * XXX pccbbintr should be called under the priority lower 945 * than any other hard interupts. 946 */ 947 KASSERT(sc->sc_ih == NULL); 948 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 949 950 if (sc->sc_ih == NULL) { 951 aprint_error_dev(sc->sc_dev, "couldn't establish interrupt"); 952 if (intrstr != NULL) 953 aprint_error(" at %s\n", intrstr); 954 else 955 aprint_error("\n"); 956 return; 957 } 958 959 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 960 961 /* CSC Interrupt: Card detect and power cycle interrupts on */ 962 sockmask = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 963 sockmask |= CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | 964 CB_SOCKET_MASK_POWER; 965 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, sockmask); 966 /* reset interrupt */ 967 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 968 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 969 } 970 971 /* 972 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 973 * struct pcmciabus_attach_args *paa) 974 * 975 * This function attaches 16-bit PCcard bus. 976 */ 977 STATIC void 978 pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 979 struct pcmciabus_attach_args *paa) 980 { 981 #if rbus 982 rbus_tag_t rb; 983 #endif 984 /* 985 * We need to do a few things here: 986 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 987 * setting the IRQ numbers to 0. 988 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 989 * routing of CSC interrupts (e.g. card removal) to PCI while in 990 * PCMCIA mode. We just leave this set all the time. 991 * 3) Enable card insertion/removal interrupts in case the chip also 992 * needs that while in PCMCIA mode. 993 * 4) Clear any pending CSC interrupt. 994 */ 995 Pcic_write(sc, PCIC_INTR, PCIC_INTR_ENABLE); 996 if (sc->sc_chipset == CB_TI113X) { 997 Pcic_write(sc, PCIC_CSC_INTR, 0); 998 } else { 999 Pcic_write(sc, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 1000 Pcic_read(sc, PCIC_CSC); 1001 } 1002 1003 /* initialize pcmcia bus attachment */ 1004 paa->paa_busname = "pcmcia"; 1005 paa->pct = &pccbb_pcmcia_funcs; 1006 paa->pch = sc; 1007 paa->iobase = 0; /* I don't use them */ 1008 paa->iosize = 0; 1009 #if rbus 1010 rb = sc->sc_rbus_iot; 1011 paa->iobase = rb->rb_start + rb->rb_offset; 1012 paa->iosize = rb->rb_end - rb->rb_start; 1013 #endif 1014 1015 return; 1016 } 1017 1018 /* 1019 * int pccbbintr(arg) 1020 * void *arg; 1021 * This routine handles the interrupt from Yenta PCI-CardBus bridge 1022 * itself. 1023 */ 1024 int 1025 pccbbintr(void *arg) 1026 { 1027 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1028 u_int32_t sockevent, sockstate; 1029 bus_space_tag_t memt = sc->sc_base_memt; 1030 bus_space_handle_t memh = sc->sc_base_memh; 1031 1032 if (!device_has_power(sc->sc_dev)) 1033 return 0; 1034 1035 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 1036 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 1037 Pcic_read(sc, PCIC_CSC); 1038 1039 if (sockevent != 0) { 1040 aprint_debug("%s: enter sockevent %" PRIx32 "\n", __func__, 1041 sockevent); 1042 } 1043 1044 /* Sometimes a change of CSTSCHG# accompanies the first 1045 * interrupt from an Atheros WLAN. That generates a 1046 * CB_SOCKET_EVENT_CSTS event on the bridge. The event 1047 * isn't interesting to pccbb(4), so we used to ignore the 1048 * interrupt. Now, let the child devices try to handle 1049 * the interrupt, instead. The Atheros NIC produces 1050 * interrupts more reliably, now: used to be that it would 1051 * only interrupt if the driver avoided powering down the 1052 * NIC's cardslot, and then the NIC would only work after 1053 * it was reset a second time. 1054 */ 1055 if (sockevent == 0 || 1056 (sockevent & ~(CB_SOCKET_EVENT_POWER|CB_SOCKET_EVENT_CD)) != 0) { 1057 /* This intr is not for me: it may be for my child devices. */ 1058 if (sc->sc_pil_intr_enable) { 1059 return pccbbintr_function(sc); 1060 } else { 1061 return 0; 1062 } 1063 } 1064 1065 if (sockevent & CB_SOCKET_EVENT_CD) { 1066 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1067 if (0x00 != (sockstate & CB_SOCKET_STAT_CD)) { 1068 /* A card should be removed. */ 1069 if (sc->sc_flags & CBB_CARDEXIST) { 1070 DPRINTF(("%s: 0x%08x", 1071 device_xname(sc->sc_dev), sockevent)); 1072 DPRINTF((" card removed, 0x%08x\n", sockstate)); 1073 sc->sc_flags &= ~CBB_CARDEXIST; 1074 if (sc->sc_csc->sc_status & 1075 CARDSLOT_STATUS_CARD_16) { 1076 cardslot_event_throw(sc->sc_csc, 1077 CARDSLOT_EVENT_REMOVAL_16); 1078 } else if (sc->sc_csc->sc_status & 1079 CARDSLOT_STATUS_CARD_CB) { 1080 /* Cardbus intr removed */ 1081 cardslot_event_throw(sc->sc_csc, 1082 CARDSLOT_EVENT_REMOVAL_CB); 1083 } 1084 } else if (sc->sc_flags & CBB_INSERTING) { 1085 sc->sc_flags &= ~CBB_INSERTING; 1086 callout_stop(&sc->sc_insert_ch); 1087 } 1088 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 1089 /* 1090 * The pccbbintr may called from powerdown hook when 1091 * the system resumed, to detect the card 1092 * insertion/removal during suspension. 1093 */ 1094 (sc->sc_flags & CBB_CARDEXIST) == 0) { 1095 if (sc->sc_flags & CBB_INSERTING) { 1096 callout_stop(&sc->sc_insert_ch); 1097 } 1098 callout_schedule(&sc->sc_insert_ch, hz / 5); 1099 sc->sc_flags |= CBB_INSERTING; 1100 } 1101 } 1102 1103 /* XXX sockevent == 9 does occur in the wild. handle it. */ 1104 if (sockevent & CB_SOCKET_EVENT_POWER) { 1105 DPRINTF(("Powercycling because of socket event\n")); 1106 /* XXX: Does not happen when attaching a 16-bit card */ 1107 sc->sc_pwrcycle++; 1108 wakeup(&sc->sc_pwrcycle); 1109 } 1110 1111 return (1); 1112 } 1113 1114 /* 1115 * static int pccbbintr_function(struct pccbb_softc *sc) 1116 * 1117 * This function calls each interrupt handler registered at the 1118 * bridge. The interrupt handlers are called in registered order. 1119 */ 1120 static int 1121 pccbbintr_function(struct pccbb_softc *sc) 1122 { 1123 int retval = 0, val; 1124 struct pccbb_intrhand_list *pil; 1125 int s; 1126 1127 LIST_FOREACH(pil, &sc->sc_pil, pil_next) { 1128 s = splraiseipl(pil->pil_icookie); 1129 val = (*pil->pil_func)(pil->pil_arg); 1130 splx(s); 1131 1132 retval = retval == 1 ? 1 : 1133 retval == 0 ? val : val != 0 ? val : retval; 1134 } 1135 1136 return retval; 1137 } 1138 1139 static void 1140 pci113x_insert(void *arg) 1141 { 1142 struct pccbb_softc *sc = arg; 1143 u_int32_t sockevent, sockstate; 1144 1145 if (!(sc->sc_flags & CBB_INSERTING)) { 1146 /* We add a card only under inserting state. */ 1147 return; 1148 } 1149 sc->sc_flags &= ~CBB_INSERTING; 1150 1151 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1152 CB_SOCKET_EVENT); 1153 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1154 CB_SOCKET_STAT); 1155 1156 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1157 DPRINTF(("%s: 0x%08x", device_xname(sc->sc_dev), sockevent)); 1158 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1159 sc->sc_flags |= CBB_CARDEXIST; 1160 /* call pccard interrupt handler here */ 1161 if (sockstate & CB_SOCKET_STAT_16BIT) { 1162 /* 16-bit card found */ 1163 cardslot_event_throw(sc->sc_csc, 1164 CARDSLOT_EVENT_INSERTION_16); 1165 } else if (sockstate & CB_SOCKET_STAT_CB) { 1166 /* cardbus card found */ 1167 cardslot_event_throw(sc->sc_csc, 1168 CARDSLOT_EVENT_INSERTION_CB); 1169 } else { 1170 /* who are you? */ 1171 } 1172 } else { 1173 callout_schedule(&sc->sc_insert_ch, hz / 10); 1174 } 1175 } 1176 1177 #define PCCBB_PCMCIA_OFFSET 0x800 1178 static u_int8_t 1179 pccbb_pcmcia_read(struct pccbb_softc *sc, int reg) 1180 { 1181 bus_space_barrier(sc->sc_base_memt, sc->sc_base_memh, 1182 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1183 1184 return bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 1185 PCCBB_PCMCIA_OFFSET + reg); 1186 } 1187 1188 static void 1189 pccbb_pcmcia_write(struct pccbb_softc *sc, int reg, u_int8_t val) 1190 { 1191 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 1192 PCCBB_PCMCIA_OFFSET + reg, val); 1193 1194 bus_space_barrier(sc->sc_base_memt, sc->sc_base_memh, 1195 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1196 } 1197 1198 /* 1199 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1200 */ 1201 STATIC int 1202 pccbb_ctrl(cardbus_chipset_tag_t ct, int command) 1203 { 1204 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1205 1206 switch (command) { 1207 case CARDBUS_CD: 1208 if (2 == pccbb_detect_card(sc)) { 1209 int retval = 0; 1210 int status = cb_detect_voltage(sc); 1211 if (PCCARD_VCC_5V & status) { 1212 retval |= CARDBUS_5V_CARD; 1213 } 1214 if (PCCARD_VCC_3V & status) { 1215 retval |= CARDBUS_3V_CARD; 1216 } 1217 if (PCCARD_VCC_XV & status) { 1218 retval |= CARDBUS_XV_CARD; 1219 } 1220 if (PCCARD_VCC_YV & status) { 1221 retval |= CARDBUS_YV_CARD; 1222 } 1223 return retval; 1224 } else { 1225 return 0; 1226 } 1227 case CARDBUS_RESET: 1228 return cb_reset(sc); 1229 case CARDBUS_IO_ENABLE: /* fallthrough */ 1230 case CARDBUS_IO_DISABLE: /* fallthrough */ 1231 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1232 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1233 case CARDBUS_BM_ENABLE: /* fallthrough */ 1234 case CARDBUS_BM_DISABLE: /* fallthrough */ 1235 /* XXX: I think we don't need to call this function below. */ 1236 return pccbb_cardenable(sc, command); 1237 } 1238 1239 return 0; 1240 } 1241 1242 STATIC int 1243 pccbb_power_ct(cardbus_chipset_tag_t ct, int command) 1244 { 1245 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1246 1247 return pccbb_power(sc, command); 1248 } 1249 1250 /* 1251 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1252 * This function returns true when it succeeds and returns false when 1253 * it fails. 1254 */ 1255 STATIC int 1256 pccbb_power(struct pccbb_softc *sc, int command) 1257 { 1258 u_int32_t status, osock_ctrl, sock_ctrl, reg_ctrl; 1259 bus_space_tag_t memt = sc->sc_base_memt; 1260 bus_space_handle_t memh = sc->sc_base_memh; 1261 int on = 0, pwrcycle, s, times; 1262 struct timeval before, after, diff; 1263 1264 DPRINTF(("pccbb_power: %s and %s [0x%x]\n", 1265 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1266 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1267 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1268 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1269 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1270 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1271 "UNKNOWN", 1272 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1273 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1274 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1275 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1276 "UNKNOWN", command)); 1277 1278 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1279 osock_ctrl = sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1280 1281 switch (command & CARDBUS_VCCMASK) { 1282 case CARDBUS_VCC_UC: 1283 break; 1284 case CARDBUS_VCC_5V: 1285 on++; 1286 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1287 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1288 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1289 } else { 1290 aprint_error_dev(sc->sc_dev, 1291 "BAD voltage request: no 5 V card\n"); 1292 return 0; 1293 } 1294 break; 1295 case CARDBUS_VCC_3V: 1296 on++; 1297 if (CB_SOCKET_STAT_3VCARD & status) { 1298 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1299 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1300 } else { 1301 aprint_error_dev(sc->sc_dev, 1302 "BAD voltage request: no 3.3 V card\n"); 1303 return 0; 1304 } 1305 break; 1306 case CARDBUS_VCC_0V: 1307 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1308 break; 1309 default: 1310 return 0; /* power NEVER changed */ 1311 } 1312 1313 switch (command & CARDBUS_VPPMASK) { 1314 case CARDBUS_VPP_UC: 1315 break; 1316 case CARDBUS_VPP_0V: 1317 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1318 break; 1319 case CARDBUS_VPP_VCC: 1320 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1321 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1322 break; 1323 case CARDBUS_VPP_12V: 1324 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1325 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1326 break; 1327 } 1328 1329 pwrcycle = sc->sc_pwrcycle; 1330 aprint_debug_dev(sc->sc_dev, "osock_ctrl %#" PRIx32 1331 " sock_ctrl %#" PRIx32 "\n", osock_ctrl, sock_ctrl); 1332 1333 microtime(&before); 1334 s = splbio(); 1335 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1336 1337 /* 1338 * Wait as long as 200ms for a power-cycle interrupt. If 1339 * interrupts are enabled, but the socket has already 1340 * changed to the desired status, keep waiting for the 1341 * interrupt. "Consuming" the interrupt in this way keeps 1342 * the interrupt from prematurely waking some subsequent 1343 * pccbb_power call. 1344 * 1345 * XXX Not every bridge interrupts on the ->OFF transition. 1346 * XXX That's ok, we will time-out after 200ms. 1347 * 1348 * XXX The power cycle event will never happen when attaching 1349 * XXX a 16-bit card. That's ok, we will time-out after 1350 * XXX 200ms. 1351 */ 1352 for (times = 5; --times >= 0; ) { 1353 if (cold) 1354 DELAY(40 * 1000); 1355 else { 1356 (void)tsleep(&sc->sc_pwrcycle, PWAIT, "pccpwr", 1357 hz / 25); 1358 if (pwrcycle == sc->sc_pwrcycle) 1359 continue; 1360 } 1361 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1362 if ((status & CB_SOCKET_STAT_PWRCYCLE) != 0 && on) 1363 break; 1364 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0 && !on) 1365 break; 1366 } 1367 splx(s); 1368 microtime(&after); 1369 timersub(&after, &before, &diff); 1370 aprint_debug_dev(sc->sc_dev, "wait took%s %ld.%06lds\n", 1371 (on && times < 0) ? " too long" : "", diff.tv_sec, diff.tv_usec); 1372 1373 /* 1374 * Ok, wait a bit longer for things to settle. 1375 */ 1376 if (on && sc->sc_chipset == CB_TOPIC95B) 1377 delay_ms(100, sc); 1378 1379 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1380 1381 if (on && sc->sc_chipset != CB_TOPIC95B) { 1382 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0) 1383 aprint_error_dev(sc->sc_dev, "power on failed?\n"); 1384 } 1385 1386 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1387 aprint_error_dev(sc->sc_dev, 1388 "bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1389 sock_ctrl, status); 1390 aprint_error_dev(sc->sc_dev, "disabling socket\n"); 1391 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1392 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1393 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1394 status &= ~CB_SOCKET_STAT_BADVCC; 1395 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, status); 1396 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1397 CB_SOCKET_STAT)); 1398 return 0; 1399 } 1400 1401 if (sc->sc_chipset == CB_TOPIC97) { 1402 reg_ctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL); 1403 reg_ctrl &= ~TOPIC97_REG_CTRL_TESTMODE; 1404 if ((command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V) 1405 reg_ctrl &= ~TOPIC97_REG_CTRL_CLKRUN_ENA; 1406 else 1407 reg_ctrl |= TOPIC97_REG_CTRL_CLKRUN_ENA; 1408 pci_conf_write(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL, reg_ctrl); 1409 } 1410 1411 return 1; /* power changed correctly */ 1412 } 1413 1414 /* 1415 * static int pccbb_detect_card(struct pccbb_softc *sc) 1416 * return value: 0 if no card exists. 1417 * 1 if 16-bit card exists. 1418 * 2 if cardbus card exists. 1419 */ 1420 static int 1421 pccbb_detect_card(struct pccbb_softc *sc) 1422 { 1423 bus_space_handle_t base_memh = sc->sc_base_memh; 1424 bus_space_tag_t base_memt = sc->sc_base_memt; 1425 u_int32_t sockstat = 1426 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1427 int retval = 0; 1428 1429 /* CD1 and CD2 asserted */ 1430 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1431 /* card must be present */ 1432 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1433 /* NOTACARD DEASSERTED */ 1434 if (CB_SOCKET_STAT_CB & sockstat) { 1435 /* CardBus mode */ 1436 retval = 2; 1437 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1438 /* 16-bit mode */ 1439 retval = 1; 1440 } 1441 } 1442 } 1443 return retval; 1444 } 1445 1446 /* 1447 * STATIC int cb_reset(struct pccbb_softc *sc) 1448 * This function resets CardBus card. 1449 */ 1450 STATIC int 1451 cb_reset(struct pccbb_softc *sc) 1452 { 1453 /* 1454 * Reset Assert at least 20 ms 1455 * Some machines request longer duration. 1456 */ 1457 int reset_duration = 1458 (sc->sc_chipset == CB_RX5C47X ? 400 : 50); 1459 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1460 aprint_debug("%s: enter bcr %" PRIx32 "\n", __func__, bcr); 1461 1462 /* Reset bit Assert (bit 6 at 0x3E) */ 1463 bcr |= PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT; 1464 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr); 1465 aprint_debug("%s: wrote bcr %" PRIx32 "\n", __func__, bcr); 1466 delay_ms(reset_duration, sc); 1467 1468 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1469 /* Reset bit Deassert (bit 6 at 0x3E) */ 1470 bcr &= ~(PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT); 1471 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, 1472 bcr); 1473 aprint_debug("%s: wrote bcr %" PRIx32 "\n", __func__, bcr); 1474 delay_ms(reset_duration, sc); 1475 aprint_debug("%s: end of delay\n", __func__); 1476 } 1477 /* No card found on the slot. Keep Reset. */ 1478 return 1; 1479 } 1480 1481 /* 1482 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1483 * This function detect card Voltage. 1484 */ 1485 STATIC int 1486 cb_detect_voltage(struct pccbb_softc *sc) 1487 { 1488 u_int32_t psr; /* socket present-state reg */ 1489 bus_space_tag_t iot = sc->sc_base_memt; 1490 bus_space_handle_t ioh = sc->sc_base_memh; 1491 int vol = PCCARD_VCC_UKN; /* set 0 */ 1492 1493 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1494 1495 if (0x400u & psr) { 1496 vol |= PCCARD_VCC_5V; 1497 } 1498 if (0x800u & psr) { 1499 vol |= PCCARD_VCC_3V; 1500 } 1501 1502 return vol; 1503 } 1504 1505 STATIC int 1506 cbbprint(void *aux, const char *pcic) 1507 { 1508 #if 0 1509 struct cbslot_attach_args *cba = aux; 1510 1511 if (cba->cba_slot >= 0) { 1512 aprint_normal(" slot %d", cba->cba_slot); 1513 } 1514 #endif 1515 return UNCONF; 1516 } 1517 1518 /* 1519 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1520 * This function enables and disables the card 1521 */ 1522 STATIC int 1523 pccbb_cardenable(struct pccbb_softc *sc, int function) 1524 { 1525 u_int32_t command = 1526 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1527 1528 DPRINTF(("pccbb_cardenable:")); 1529 switch (function) { 1530 case CARDBUS_IO_ENABLE: 1531 command |= PCI_COMMAND_IO_ENABLE; 1532 break; 1533 case CARDBUS_IO_DISABLE: 1534 command &= ~PCI_COMMAND_IO_ENABLE; 1535 break; 1536 case CARDBUS_MEM_ENABLE: 1537 command |= PCI_COMMAND_MEM_ENABLE; 1538 break; 1539 case CARDBUS_MEM_DISABLE: 1540 command &= ~PCI_COMMAND_MEM_ENABLE; 1541 break; 1542 case CARDBUS_BM_ENABLE: 1543 command |= PCI_COMMAND_MASTER_ENABLE; 1544 break; 1545 case CARDBUS_BM_DISABLE: 1546 command &= ~PCI_COMMAND_MASTER_ENABLE; 1547 break; 1548 default: 1549 return 0; 1550 } 1551 1552 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1553 DPRINTF((" command reg 0x%x\n", command)); 1554 return 1; 1555 } 1556 1557 #if !rbus 1558 static int 1559 pccbb_io_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 1560 { 1561 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1562 int basereg; 1563 int limitreg; 1564 1565 if ((win < 0) || (win > 2)) { 1566 #if defined DIAGNOSTIC 1567 printf("cardbus_io_open: window out of range %d\n", win); 1568 #endif 1569 return 0; 1570 } 1571 1572 basereg = win * 8 + PCI_CB_IOBASE0; 1573 limitreg = win * 8 + PCI_CB_IOLIMIT0; 1574 1575 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1576 start, basereg, end, limitreg)); 1577 1578 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1579 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1580 return 1; 1581 } 1582 1583 /* 1584 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1585 */ 1586 static int 1587 pccbb_io_close(cardbus_chipset_tag_t ct, int win) 1588 { 1589 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1590 int basereg; 1591 int limitreg; 1592 1593 if ((win < 0) || (win > 2)) { 1594 #if defined DIAGNOSTIC 1595 printf("cardbus_io_close: window out of range %d\n", win); 1596 #endif 1597 return 0; 1598 } 1599 1600 basereg = win * 8 + PCI_CB_IOBASE0; 1601 limitreg = win * 8 + PCI_CB_IOLIMIT0; 1602 1603 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1604 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1605 return 1; 1606 } 1607 1608 static int 1609 pccbb_mem_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 1610 { 1611 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1612 int basereg; 1613 int limitreg; 1614 1615 if ((win < 0) || (win > 2)) { 1616 #if defined DIAGNOSTIC 1617 printf("cardbus_mem_open: window out of range %d\n", win); 1618 #endif 1619 return 0; 1620 } 1621 1622 basereg = win * 8 + PCI_CB_MEMBASE0; 1623 limitreg = win * 8 + PCI_CB_MEMLIMIT0; 1624 1625 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1626 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1627 return 1; 1628 } 1629 1630 static int 1631 pccbb_mem_close(cardbus_chipset_tag_t ct, int win) 1632 { 1633 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1634 int basereg; 1635 int limitreg; 1636 1637 if ((win < 0) || (win > 2)) { 1638 #if defined DIAGNOSTIC 1639 printf("cardbus_mem_close: window out of range %d\n", win); 1640 #endif 1641 return 0; 1642 } 1643 1644 basereg = win * 8 + PCI_CB_MEMBASE0; 1645 limitreg = win * 8 + PCI_CB_MEMLIMIT0; 1646 1647 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1648 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1649 return 1; 1650 } 1651 #endif 1652 1653 /* 1654 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1655 * int irq, 1656 * int level, 1657 * int (* func)(void *), 1658 * void *arg) 1659 * 1660 * This function registers an interrupt handler at the bridge, in 1661 * order not to call the interrupt handlers of child devices when 1662 * a card-deletion interrupt occurs. 1663 * 1664 * The arguments irq and level are not used. 1665 */ 1666 static void * 1667 pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, cardbus_intr_line_t irq, 1668 int level, int (*func)(void *), void *arg) 1669 { 1670 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1671 1672 return pccbb_intr_establish(sc, irq, level, func, arg); 1673 } 1674 1675 1676 /* 1677 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1678 * void *ih) 1679 * 1680 * This function removes an interrupt handler pointed by ih. 1681 */ 1682 static void 1683 pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih) 1684 { 1685 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1686 1687 pccbb_intr_disestablish(sc, ih); 1688 } 1689 1690 1691 void 1692 pccbb_intr_route(struct pccbb_softc *sc) 1693 { 1694 pcireg_t bcr, cbctrl; 1695 1696 /* initialize bridge intr routing */ 1697 bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1698 bcr &= ~CB_BCR_INTR_IREQ_ENABLE; 1699 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr); 1700 1701 switch (sc->sc_chipset) { 1702 case CB_TI113X: 1703 cbctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1704 /* functional intr enabled */ 1705 cbctrl |= PCI113X_CBCTRL_PCI_INTR; 1706 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, cbctrl); 1707 break; 1708 default: 1709 break; 1710 } 1711 } 1712 1713 /* 1714 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1715 * int irq, 1716 * int level, 1717 * int (* func)(void *), 1718 * void *arg) 1719 * 1720 * This function registers an interrupt handler at the bridge, in 1721 * order not to call the interrupt handlers of child devices when 1722 * a card-deletion interrupt occurs. 1723 * 1724 * The arguments irq is not used because pccbb selects intr vector. 1725 */ 1726 static void * 1727 pccbb_intr_establish(struct pccbb_softc *sc, cardbus_intr_line_t irq, 1728 int level, int (*func)(void *), void *arg) 1729 { 1730 struct pccbb_intrhand_list *pil, *newpil; 1731 1732 DPRINTF(("pccbb_intr_establish start. %p\n", LIST_FIRST(&sc->sc_pil))); 1733 1734 if (LIST_EMPTY(&sc->sc_pil)) { 1735 pccbb_intr_route(sc); 1736 } 1737 1738 /* 1739 * Allocate a room for interrupt handler structure. 1740 */ 1741 if (NULL == (newpil = 1742 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1743 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1744 return NULL; 1745 } 1746 1747 newpil->pil_func = func; 1748 newpil->pil_arg = arg; 1749 newpil->pil_icookie = makeiplcookie(level); 1750 1751 if (LIST_EMPTY(&sc->sc_pil)) { 1752 LIST_INSERT_HEAD(&sc->sc_pil, newpil, pil_next); 1753 } else { 1754 for (pil = LIST_FIRST(&sc->sc_pil); 1755 LIST_NEXT(pil, pil_next) != NULL; 1756 pil = LIST_NEXT(pil, pil_next)); 1757 LIST_INSERT_AFTER(pil, newpil, pil_next); 1758 } 1759 1760 DPRINTF(("pccbb_intr_establish add pil. %p\n", 1761 LIST_FIRST(&sc->sc_pil))); 1762 1763 return newpil; 1764 } 1765 1766 /* 1767 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1768 * void *ih) 1769 * 1770 * This function removes an interrupt handler pointed by ih. ih 1771 * should be the value returned by cardbus_intr_establish() or 1772 * NULL. 1773 * 1774 * When ih is NULL, this function will do nothing. 1775 */ 1776 static void 1777 pccbb_intr_disestablish(struct pccbb_softc *sc, void *ih) 1778 { 1779 struct pccbb_intrhand_list *pil; 1780 pcireg_t reg; 1781 1782 DPRINTF(("pccbb_intr_disestablish start. %p\n", 1783 LIST_FIRST(&sc->sc_pil))); 1784 1785 if (ih == NULL) { 1786 /* intr handler is not set */ 1787 DPRINTF(("pccbb_intr_disestablish: no ih\n")); 1788 return; 1789 } 1790 1791 #ifdef DIAGNOSTIC 1792 LIST_FOREACH(pil, &sc->sc_pil, pil_next) { 1793 DPRINTF(("pccbb_intr_disestablish: pil %p\n", pil)); 1794 if (pil == ih) { 1795 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1796 break; 1797 } 1798 } 1799 if (pil == NULL) { 1800 panic("pccbb_intr_disestablish: %s cannot find pil %p", 1801 device_xname(sc->sc_dev), ih); 1802 } 1803 #endif 1804 1805 pil = (struct pccbb_intrhand_list *)ih; 1806 LIST_REMOVE(pil, pil_next); 1807 free(pil, M_DEVBUF); 1808 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1809 1810 if (LIST_EMPTY(&sc->sc_pil)) { 1811 /* No interrupt handlers */ 1812 1813 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1814 1815 /* stop routing PCI intr */ 1816 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1817 reg |= CB_BCR_INTR_IREQ_ENABLE; 1818 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, reg); 1819 1820 switch (sc->sc_chipset) { 1821 case CB_TI113X: 1822 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1823 /* functional intr disabled */ 1824 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1825 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1826 break; 1827 default: 1828 break; 1829 } 1830 } 1831 } 1832 1833 #if defined SHOW_REGS 1834 static void 1835 cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, bus_space_tag_t memt, 1836 bus_space_handle_t memh) 1837 { 1838 int i; 1839 printf("PCI config regs:"); 1840 for (i = 0; i < 0x50; i += 4) { 1841 if (i % 16 == 0) 1842 printf("\n 0x%02x:", i); 1843 printf(" %08x", pci_conf_read(pc, tag, i)); 1844 } 1845 for (i = 0x80; i < 0xb0; i += 4) { 1846 if (i % 16 == 0) 1847 printf("\n 0x%02x:", i); 1848 printf(" %08x", pci_conf_read(pc, tag, i)); 1849 } 1850 1851 if (memh == 0) { 1852 printf("\n"); 1853 return; 1854 } 1855 1856 printf("\nsocket regs:"); 1857 for (i = 0; i <= 0x10; i += 0x04) 1858 printf(" %08x", bus_space_read_4(memt, memh, i)); 1859 printf("\nExCA regs:"); 1860 for (i = 0; i < 0x08; ++i) 1861 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1862 printf("\n"); 1863 return; 1864 } 1865 #endif 1866 1867 /* 1868 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1869 * int busno, int function) 1870 * This is the function to make a tag to access config space of 1871 * a CardBus Card. It works same as pci_conf_read. 1872 */ 1873 static cardbustag_t 1874 pccbb_make_tag(cardbus_chipset_tag_t cc, int busno, int function) 1875 { 1876 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1877 1878 return pci_make_tag(sc->sc_pc, busno, 0, function); 1879 } 1880 1881 static void 1882 pccbb_free_tag(cardbus_chipset_tag_t cc, cardbustag_t tag) 1883 { 1884 } 1885 1886 /* 1887 * pccbb_conf_read 1888 * 1889 * This is the function to read the config space of a CardBus card. 1890 * It works the same as pci_conf_read(9). 1891 */ 1892 static cardbusreg_t 1893 pccbb_conf_read(cardbus_chipset_tag_t cc, cardbustag_t tag, int offset) 1894 { 1895 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1896 1897 return pci_conf_read(sc->sc_pc, tag, offset); 1898 } 1899 1900 /* 1901 * pccbb_conf_write 1902 * 1903 * This is the function to write the config space of a CardBus 1904 * card. It works the same as pci_conf_write(9). 1905 */ 1906 static void 1907 pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, int reg, 1908 cardbusreg_t val) 1909 { 1910 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1911 1912 pci_conf_write(sc->sc_pc, tag, reg, val); 1913 } 1914 1915 #if 0 1916 STATIC int 1917 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1918 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 1919 int speed, int flags, 1920 bus_space_handle_t * iohp) 1921 #endif 1922 /* 1923 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1924 * bus_addr_t start, bus_size_t size, 1925 * bus_size_t align, 1926 * struct pcmcia_io_handle *pcihp 1927 * 1928 * This function only allocates I/O region for pccard. This function 1929 * never maps the allocated region to pccard I/O area. 1930 * 1931 * XXX: The interface of this function is not very good, I believe. 1932 */ 1933 STATIC int 1934 pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, 1935 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 1936 { 1937 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 1938 bus_addr_t ioaddr; 1939 int flags = 0; 1940 bus_space_tag_t iot; 1941 bus_space_handle_t ioh; 1942 bus_addr_t mask; 1943 #if rbus 1944 rbus_tag_t rb; 1945 #endif 1946 if (align == 0) { 1947 align = size; /* XXX: funny??? */ 1948 } 1949 1950 if (start != 0) { 1951 /* XXX: assume all card decode lower 10 bits by its hardware */ 1952 mask = 0x3ff; 1953 /* enforce to use only masked address */ 1954 start &= mask; 1955 } else { 1956 /* 1957 * calculate mask: 1958 * 1. get the most significant bit of size (call it msb). 1959 * 2. compare msb with the value of size. 1960 * 3. if size is larger, shift msb left once. 1961 * 4. obtain mask value to decrement msb. 1962 */ 1963 bus_size_t size_tmp = size; 1964 int shifts = 0; 1965 1966 mask = 1; 1967 while (size_tmp) { 1968 ++shifts; 1969 size_tmp >>= 1; 1970 } 1971 mask = (1 << shifts); 1972 if (mask < size) { 1973 mask <<= 1; 1974 } 1975 --mask; 1976 } 1977 1978 /* 1979 * Allocate some arbitrary I/O space. 1980 */ 1981 1982 iot = sc->sc_iot; 1983 1984 #if rbus 1985 rb = sc->sc_rbus_iot; 1986 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 1987 return 1; 1988 } 1989 DPRINTF(("pccbb_pcmcia_io_alloc alloc port 0x%lx+0x%lx\n", 1990 (u_long) ioaddr, (u_long) size)); 1991 #else 1992 if (start) { 1993 ioaddr = start; 1994 if (bus_space_map(iot, start, size, 0, &ioh)) { 1995 return 1; 1996 } 1997 DPRINTF(("pccbb_pcmcia_io_alloc map port 0x%lx+0x%lx\n", 1998 (u_long) ioaddr, (u_long) size)); 1999 } else { 2000 flags |= PCMCIA_IO_ALLOCATED; 2001 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 2002 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 2003 size, align, 0, 0, &ioaddr, &ioh)) { 2004 /* No room be able to be get. */ 2005 return 1; 2006 } 2007 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2008 (u_long) ioaddr, (u_long) size)); 2009 } 2010 #endif 2011 2012 pcihp->iot = iot; 2013 pcihp->ioh = ioh; 2014 pcihp->addr = ioaddr; 2015 pcihp->size = size; 2016 pcihp->flags = flags; 2017 2018 return 0; 2019 } 2020 2021 /* 2022 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2023 * struct pcmcia_io_handle *pcihp) 2024 * 2025 * This function only frees I/O region for pccard. 2026 * 2027 * XXX: The interface of this function is not very good, I believe. 2028 */ 2029 void 2030 pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2031 struct pcmcia_io_handle *pcihp) 2032 { 2033 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2034 #if !rbus 2035 bus_space_tag_t iot = pcihp->iot; 2036 #endif 2037 bus_space_handle_t ioh = pcihp->ioh; 2038 bus_size_t size = pcihp->size; 2039 2040 #if rbus 2041 rbus_tag_t rb = sc->sc_rbus_iot; 2042 2043 rbus_space_free(rb, ioh, size, NULL); 2044 #else 2045 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 2046 bus_space_free(iot, ioh, size); 2047 else 2048 bus_space_unmap(iot, ioh, size); 2049 #endif 2050 } 2051 2052 /* 2053 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 2054 * bus_addr_t offset, bus_size_t size, 2055 * struct pcmcia_io_handle *pcihp, 2056 * int *windowp) 2057 * 2058 * This function maps the allocated I/O region to pccard. This function 2059 * never allocates any I/O region for pccard I/O area. I don't 2060 * understand why the original authors of pcmciabus separated alloc and 2061 * map. I believe the two must be unite. 2062 * 2063 * XXX: no wait timing control? 2064 */ 2065 int 2066 pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, bus_addr_t offset, 2067 bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp) 2068 { 2069 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2070 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2071 bus_addr_t ioaddr = pcihp->addr + offset; 2072 int i, win; 2073 #if defined CBB_DEBUG 2074 static const char *width_names[] = { "dynamic", "io8", "io16" }; 2075 #endif 2076 2077 /* Sanity check I/O handle. */ 2078 2079 if (sc->sc_iot != pcihp->iot) { 2080 panic("pccbb_pcmcia_io_map iot is bogus"); 2081 } 2082 2083 /* XXX Sanity check offset/size. */ 2084 2085 win = -1; 2086 for (i = 0; i < PCIC_IO_WINS; i++) { 2087 if ((ph->ioalloc & (1 << i)) == 0) { 2088 win = i; 2089 ph->ioalloc |= (1 << i); 2090 break; 2091 } 2092 } 2093 2094 if (win == -1) { 2095 return 1; 2096 } 2097 2098 *windowp = win; 2099 2100 /* XXX this is pretty gross */ 2101 2102 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2103 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2104 2105 /* XXX wtf is this doing here? */ 2106 2107 #if 0 2108 printf(" port 0x%lx", (u_long) ioaddr); 2109 if (size > 1) { 2110 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2111 } 2112 #endif 2113 2114 ph->io[win].addr = ioaddr; 2115 ph->io[win].size = size; 2116 ph->io[win].width = width; 2117 2118 /* actual dirty register-value changing in the function below. */ 2119 pccbb_pcmcia_do_io_map(sc, win); 2120 2121 return 0; 2122 } 2123 2124 /* 2125 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2126 * 2127 * This function changes register-value to map I/O region for pccard. 2128 */ 2129 static void 2130 pccbb_pcmcia_do_io_map(struct pccbb_softc *sc, int win) 2131 { 2132 static u_int8_t pcic_iowidth[3] = { 2133 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2134 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2135 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2136 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2137 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2138 }; 2139 2140 #define PCIC_SIA_START_LOW 0 2141 #define PCIC_SIA_START_HIGH 1 2142 #define PCIC_SIA_STOP_LOW 2 2143 #define PCIC_SIA_STOP_HIGH 3 2144 2145 int regbase_win = 0x8 + win * 0x04; 2146 u_int8_t ioctl, enable; 2147 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2148 2149 DPRINTF(("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx " 2150 "width %d\n", win, (unsigned long)ph->io[win].addr, 2151 (unsigned long)ph->io[win].size, ph->io[win].width * 8)); 2152 2153 Pcic_write(sc, regbase_win + PCIC_SIA_START_LOW, 2154 ph->io[win].addr & 0xff); 2155 Pcic_write(sc, regbase_win + PCIC_SIA_START_HIGH, 2156 (ph->io[win].addr >> 8) & 0xff); 2157 2158 Pcic_write(sc, regbase_win + PCIC_SIA_STOP_LOW, 2159 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2160 Pcic_write(sc, regbase_win + PCIC_SIA_STOP_HIGH, 2161 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2162 2163 ioctl = Pcic_read(sc, PCIC_IOCTL); 2164 enable = Pcic_read(sc, PCIC_ADDRWIN_ENABLE); 2165 switch (win) { 2166 case 0: 2167 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2168 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2169 PCIC_IOCTL_IO0_DATASIZE_MASK); 2170 ioctl |= pcic_iowidth[ph->io[win].width]; 2171 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2172 break; 2173 case 1: 2174 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2175 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2176 PCIC_IOCTL_IO1_DATASIZE_MASK); 2177 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2178 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2179 break; 2180 } 2181 Pcic_write(sc, PCIC_IOCTL, ioctl); 2182 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, enable); 2183 #if defined(CBB_DEBUG) 2184 { 2185 u_int8_t start_low = 2186 Pcic_read(sc, regbase_win + PCIC_SIA_START_LOW); 2187 u_int8_t start_high = 2188 Pcic_read(sc, regbase_win + PCIC_SIA_START_HIGH); 2189 u_int8_t stop_low = 2190 Pcic_read(sc, regbase_win + PCIC_SIA_STOP_LOW); 2191 u_int8_t stop_high = 2192 Pcic_read(sc, regbase_win + PCIC_SIA_STOP_HIGH); 2193 printf("pccbb_pcmcia_do_io_map start %02x %02x, " 2194 "stop %02x %02x, ioctl %02x enable %02x\n", 2195 start_low, start_high, stop_low, stop_high, ioctl, enable); 2196 } 2197 #endif 2198 } 2199 2200 /* 2201 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2202 * 2203 * This function unmaps I/O region. No return value. 2204 */ 2205 STATIC void 2206 pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t pch, int win) 2207 { 2208 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2209 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2210 int reg; 2211 2212 if (win >= PCIC_IO_WINS || win < 0) { 2213 panic("pccbb_pcmcia_io_unmap: window out of range"); 2214 } 2215 2216 reg = Pcic_read(sc, PCIC_ADDRWIN_ENABLE); 2217 switch (win) { 2218 case 0: 2219 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2220 break; 2221 case 1: 2222 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2223 break; 2224 } 2225 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, reg); 2226 2227 ph->ioalloc &= ~(1 << win); 2228 } 2229 2230 static int 2231 pccbb_pcmcia_wait_ready(struct pccbb_softc *sc) 2232 { 2233 u_int8_t stat; 2234 int i; 2235 2236 /* wait an initial 10ms for quick cards */ 2237 stat = Pcic_read(sc, PCIC_IF_STATUS); 2238 if (stat & PCIC_IF_STATUS_READY) 2239 return (0); 2240 pccbb_pcmcia_delay(sc, 10, "pccwr0"); 2241 for (i = 0; i < 50; i++) { 2242 stat = Pcic_read(sc, PCIC_IF_STATUS); 2243 if (stat & PCIC_IF_STATUS_READY) 2244 return (0); 2245 if ((stat & PCIC_IF_STATUS_CARDDETECT_MASK) != 2246 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2247 return (ENXIO); 2248 /* wait .1s (100ms) each iteration now */ 2249 pccbb_pcmcia_delay(sc, 100, "pccwr1"); 2250 } 2251 2252 printf("pccbb_pcmcia_wait_ready: ready never happened, status=%02x\n", stat); 2253 return (EWOULDBLOCK); 2254 } 2255 2256 /* 2257 * Perform long (msec order) delay. timo is in milliseconds. 2258 */ 2259 static void 2260 pccbb_pcmcia_delay(struct pccbb_softc *sc, int timo, const char *wmesg) 2261 { 2262 #ifdef DIAGNOSTIC 2263 if (timo <= 0) 2264 panic("pccbb_pcmcia_delay: called with timeout %d", timo); 2265 if (!curlwp) 2266 panic("pccbb_pcmcia_delay: called in interrupt context"); 2267 #endif 2268 DPRINTF(("pccbb_pcmcia_delay: \"%s\", sleep %d ms\n", wmesg, timo)); 2269 tsleep(pccbb_pcmcia_delay, PWAIT, wmesg, roundup(timo * hz, 1000) / 1000); 2270 } 2271 2272 /* 2273 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2274 * 2275 * This function enables the card. All information is stored in 2276 * the first argument, pcmcia_chipset_handle_t. 2277 */ 2278 STATIC void 2279 pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2280 { 2281 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2282 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2283 pcireg_t spsr; 2284 int voltage; 2285 int win; 2286 u_int8_t power, intr; 2287 #ifdef DIAGNOSTIC 2288 int reg; 2289 #endif 2290 2291 /* this bit is mostly stolen from pcic_attach_card */ 2292 2293 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2294 2295 /* get card Vcc info */ 2296 spsr = 2297 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2298 CB_SOCKET_STAT); 2299 if (spsr & CB_SOCKET_STAT_5VCARD) { 2300 DPRINTF(("5V card\n")); 2301 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2302 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2303 DPRINTF(("3V card\n")); 2304 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2305 } else { 2306 DPRINTF(("?V card, 0x%x\n", spsr)); /* XXX */ 2307 return; 2308 } 2309 2310 /* disable interrupts; assert RESET */ 2311 intr = Pcic_read(sc, PCIC_INTR); 2312 intr &= PCIC_INTR_ENABLE; 2313 Pcic_write(sc, PCIC_INTR, intr); 2314 2315 /* zero out the address windows */ 2316 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, 0); 2317 2318 /* power down the socket to reset it, clear the card reset pin */ 2319 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2320 2321 /* power off; assert output enable bit */ 2322 power = PCIC_PWRCTL_OE; 2323 Pcic_write(sc, PCIC_PWRCTL, power); 2324 2325 /* power up the socket */ 2326 if (pccbb_power(sc, voltage) == 0) 2327 return; 2328 2329 /* 2330 * Table 4-18 and figure 4-6 of the PC Card specifiction say: 2331 * Vcc Rising Time (Tpr) = 100ms (handled in pccbb_power() above) 2332 * RESET Width (Th (Hi-z RESET)) = 1ms 2333 * RESET Width (Tw (RESET)) = 10us 2334 * 2335 * some machines require some more time to be settled 2336 * for example old toshiba topic bridges! 2337 * (100ms is added here). 2338 */ 2339 pccbb_pcmcia_delay(sc, 200 + 1, "pccen1"); 2340 2341 /* negate RESET */ 2342 intr |= PCIC_INTR_RESET; 2343 Pcic_write(sc, PCIC_INTR, intr); 2344 2345 /* 2346 * RESET Setup Time (Tsu (RESET)) = 20ms 2347 */ 2348 pccbb_pcmcia_delay(sc, 20, "pccen2"); 2349 2350 #ifdef DIAGNOSTIC 2351 reg = Pcic_read(sc, PCIC_IF_STATUS); 2352 if ((reg & PCIC_IF_STATUS_POWERACTIVE) == 0) 2353 printf("pccbb_pcmcia_socket_enable: no power, status=%x\n", reg); 2354 #endif 2355 2356 /* wait for the chip to finish initializing */ 2357 if (pccbb_pcmcia_wait_ready(sc)) { 2358 #ifdef DIAGNOSTIC 2359 printf("pccbb_pcmcia_socket_enable: never became ready\n"); 2360 #endif 2361 /* XXX return a failure status?? */ 2362 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2363 Pcic_write(sc, PCIC_PWRCTL, 0); 2364 return; 2365 } 2366 2367 /* reinstall all the memory and io mappings */ 2368 for (win = 0; win < PCIC_MEM_WINS; ++win) 2369 if (ph->memalloc & (1 << win)) 2370 pccbb_pcmcia_do_mem_map(sc, win); 2371 for (win = 0; win < PCIC_IO_WINS; ++win) 2372 if (ph->ioalloc & (1 << win)) 2373 pccbb_pcmcia_do_io_map(sc, win); 2374 } 2375 2376 /* 2377 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2378 * 2379 * This function disables the card. All information is stored in 2380 * the first argument, pcmcia_chipset_handle_t. 2381 */ 2382 STATIC void 2383 pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t pch) 2384 { 2385 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2386 u_int8_t intr; 2387 2388 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2389 2390 /* disable interrupts; assert RESET */ 2391 intr = Pcic_read(sc, PCIC_INTR); 2392 intr &= PCIC_INTR_ENABLE; 2393 Pcic_write(sc, PCIC_INTR, intr); 2394 2395 /* zero out the address windows */ 2396 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, 0); 2397 2398 /* power down the socket to reset it, clear the card reset pin */ 2399 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2400 2401 /* disable socket: negate output enable bit and power off */ 2402 Pcic_write(sc, PCIC_PWRCTL, 0); 2403 2404 /* 2405 * Vcc Falling Time (Tpf) = 300ms 2406 */ 2407 pccbb_pcmcia_delay(sc, 300, "pccwr1"); 2408 } 2409 2410 STATIC void 2411 pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t pch, int type) 2412 { 2413 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2414 u_int8_t intr; 2415 2416 /* set the card type */ 2417 2418 intr = Pcic_read(sc, PCIC_INTR); 2419 intr &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_CARDTYPE_MASK); 2420 if (type == PCMCIA_IFTYPE_IO) 2421 intr |= PCIC_INTR_CARDTYPE_IO; 2422 else 2423 intr |= PCIC_INTR_CARDTYPE_MEM; 2424 Pcic_write(sc, PCIC_INTR, intr); 2425 2426 DPRINTF(("%s: pccbb_pcmcia_socket_settype type %s %02x\n", 2427 device_xname(sc->sc_dev), 2428 ((type == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2429 } 2430 2431 /* 2432 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2433 * 2434 * This function detects whether a card is in the slot or not. 2435 * If a card is inserted, return 1. Otherwise, return 0. 2436 */ 2437 STATIC int 2438 pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch) 2439 { 2440 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2441 2442 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2443 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2444 } 2445 2446 #if 0 2447 STATIC int 2448 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2449 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2450 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2451 #endif 2452 /* 2453 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2454 * bus_size_t size, 2455 * struct pcmcia_mem_handle *pcmhp) 2456 * 2457 * This function only allocates memory region for pccard. This 2458 * function never maps the allocated region to pccard memory area. 2459 * 2460 * XXX: Why the argument of start address is not in? 2461 */ 2462 STATIC int 2463 pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 2464 struct pcmcia_mem_handle *pcmhp) 2465 { 2466 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2467 bus_space_handle_t memh; 2468 bus_addr_t addr; 2469 bus_size_t sizepg; 2470 #if rbus 2471 rbus_tag_t rb; 2472 #endif 2473 2474 /* Check that the card is still there. */ 2475 if ((Pcic_read(sc, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2476 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2477 return 1; 2478 2479 /* out of sc->memh, allocate as many pages as necessary */ 2480 2481 /* convert size to PCIC pages */ 2482 /* 2483 * This is not enough; when the requested region is on the page 2484 * boundaries, this may calculate wrong result. 2485 */ 2486 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2487 #if 0 2488 if (sizepg > PCIC_MAX_MEM_PAGES) { 2489 return 1; 2490 } 2491 #endif 2492 2493 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2494 return 1; 2495 } 2496 2497 addr = 0; /* XXX gcc -Wuninitialized */ 2498 2499 #if rbus 2500 rb = sc->sc_rbus_memt; 2501 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2502 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2503 &addr, &memh)) { 2504 return 1; 2505 } 2506 #else 2507 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2508 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2509 0, /* boundary */ 2510 0, /* flags */ 2511 &addr, &memh)) { 2512 return 1; 2513 } 2514 #endif 2515 2516 DPRINTF(("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, " 2517 "realsize 0x%lx\n", (unsigned long)addr, (unsigned long)size, 2518 (unsigned long)sizepg * PCIC_MEM_PAGESIZE)); 2519 2520 pcmhp->memt = sc->sc_memt; 2521 pcmhp->memh = memh; 2522 pcmhp->addr = addr; 2523 pcmhp->size = size; 2524 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2525 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2526 pcmhp->mhandle = 0; 2527 /* No offset??? Funny. */ 2528 2529 return 0; 2530 } 2531 2532 /* 2533 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2534 * struct pcmcia_mem_handle *pcmhp) 2535 * 2536 * This function release the memory space allocated by the function 2537 * pccbb_pcmcia_mem_alloc(). 2538 */ 2539 STATIC void 2540 pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2541 struct pcmcia_mem_handle *pcmhp) 2542 { 2543 #if rbus 2544 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2545 2546 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2547 #else 2548 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2549 #endif 2550 } 2551 2552 /* 2553 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2554 * 2555 * This function release the memory space allocated by the function 2556 * pccbb_pcmcia_mem_alloc(). 2557 */ 2558 STATIC void 2559 pccbb_pcmcia_do_mem_map(struct pccbb_softc *sc, int win) 2560 { 2561 int regbase_win; 2562 bus_addr_t phys_addr; 2563 bus_addr_t phys_end; 2564 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2565 2566 #define PCIC_SMM_START_LOW 0 2567 #define PCIC_SMM_START_HIGH 1 2568 #define PCIC_SMM_STOP_LOW 2 2569 #define PCIC_SMM_STOP_HIGH 3 2570 #define PCIC_CMA_LOW 4 2571 #define PCIC_CMA_HIGH 5 2572 2573 u_int8_t start_low, start_high = 0; 2574 u_int8_t stop_low, stop_high; 2575 u_int8_t off_low, off_high; 2576 u_int8_t mem_window; 2577 int reg; 2578 2579 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2580 int mem8 = 2581 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2582 || (kind == PCMCIA_MEM_ATTR); 2583 2584 regbase_win = 0x10 + win * 0x08; 2585 2586 phys_addr = ph->mem[win].addr; 2587 phys_end = phys_addr + ph->mem[win].size; 2588 2589 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2590 (unsigned long)phys_addr, (unsigned long)phys_end, 2591 (unsigned long)ph->mem[win].offset)); 2592 2593 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2594 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2595 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2596 2597 /* bit 19:12 */ 2598 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2599 /* bit 23:20 and bit 7 on */ 2600 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2601 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2602 /* bit 31:24, for 32-bit address */ 2603 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2604 2605 Pcic_write(sc, regbase_win + PCIC_SMM_START_LOW, start_low); 2606 Pcic_write(sc, regbase_win + PCIC_SMM_START_HIGH, start_high); 2607 2608 if (sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2609 Pcic_write(sc, 0x40 + win, mem_window); 2610 } 2611 2612 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2613 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2614 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2615 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2616 2617 Pcic_write(sc, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2618 Pcic_write(sc, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2619 2620 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2621 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2622 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2623 | ((kind == PCMCIA_MEM_ATTR) ? 2624 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2625 2626 Pcic_write(sc, regbase_win + PCIC_CMA_LOW, off_low); 2627 Pcic_write(sc, regbase_win + PCIC_CMA_HIGH, off_high); 2628 2629 reg = Pcic_read(sc, PCIC_ADDRWIN_ENABLE); 2630 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2631 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, reg); 2632 2633 #if defined(CBB_DEBUG) 2634 { 2635 int r1, r2, r3, r4, r5, r6, r7 = 0; 2636 2637 r1 = Pcic_read(sc, regbase_win + PCIC_SMM_START_LOW); 2638 r2 = Pcic_read(sc, regbase_win + PCIC_SMM_START_HIGH); 2639 r3 = Pcic_read(sc, regbase_win + PCIC_SMM_STOP_LOW); 2640 r4 = Pcic_read(sc, regbase_win + PCIC_SMM_STOP_HIGH); 2641 r5 = Pcic_read(sc, regbase_win + PCIC_CMA_LOW); 2642 r6 = Pcic_read(sc, regbase_win + PCIC_CMA_HIGH); 2643 if (sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2644 r7 = Pcic_read(sc, 0x40 + win); 2645 } 2646 2647 printf("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2648 "%02x%02x", win, r1, r2, r3, r4, r5, r6); 2649 if (sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2650 printf(" %02x", r7); 2651 } 2652 printf("\n"); 2653 } 2654 #endif 2655 } 2656 2657 /* 2658 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2659 * bus_addr_t card_addr, bus_size_t size, 2660 * struct pcmcia_mem_handle *pcmhp, 2661 * bus_addr_t *offsetp, int *windowp) 2662 * 2663 * This function maps memory space allocated by the function 2664 * pccbb_pcmcia_mem_alloc(). 2665 */ 2666 STATIC int 2667 pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2668 bus_addr_t card_addr, bus_size_t size, struct pcmcia_mem_handle *pcmhp, 2669 bus_addr_t *offsetp, int *windowp) 2670 { 2671 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2672 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2673 bus_addr_t busaddr; 2674 long card_offset; 2675 int win; 2676 2677 /* Check that the card is still there. */ 2678 if ((Pcic_read(sc, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2679 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2680 return 1; 2681 2682 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2683 if ((ph->memalloc & (1 << win)) == 0) { 2684 ph->memalloc |= (1 << win); 2685 break; 2686 } 2687 } 2688 2689 if (win == PCIC_MEM_WINS) { 2690 return 1; 2691 } 2692 2693 *windowp = win; 2694 2695 /* XXX this is pretty gross */ 2696 2697 if (sc->sc_memt != pcmhp->memt) { 2698 panic("pccbb_pcmcia_mem_map memt is bogus"); 2699 } 2700 2701 busaddr = pcmhp->addr; 2702 2703 /* 2704 * compute the address offset to the pcmcia address space for the 2705 * pcic. this is intentionally signed. The masks and shifts below 2706 * will cause TRT to happen in the pcic registers. Deal with making 2707 * sure the address is aligned, and return the alignment offset. 2708 */ 2709 2710 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2711 card_addr -= *offsetp; 2712 2713 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2714 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2715 (u_long) card_addr)); 2716 2717 /* 2718 * include the offset in the size, and decrement size by one, since 2719 * the hw wants start/stop 2720 */ 2721 size += *offsetp - 1; 2722 2723 card_offset = (((long)card_addr) - ((long)busaddr)); 2724 2725 ph->mem[win].addr = busaddr; 2726 ph->mem[win].size = size; 2727 ph->mem[win].offset = card_offset; 2728 ph->mem[win].kind = kind; 2729 2730 pccbb_pcmcia_do_mem_map(sc, win); 2731 2732 return 0; 2733 } 2734 2735 /* 2736 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2737 * int window) 2738 * 2739 * This function unmaps memory space which mapped by the function 2740 * pccbb_pcmcia_mem_map(). 2741 */ 2742 STATIC void 2743 pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, int window) 2744 { 2745 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2746 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2747 int reg; 2748 2749 if (window >= PCIC_MEM_WINS) { 2750 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2751 } 2752 2753 reg = Pcic_read(sc, PCIC_ADDRWIN_ENABLE); 2754 reg &= ~(1 << window); 2755 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, reg); 2756 2757 ph->memalloc &= ~(1 << window); 2758 } 2759 2760 /* 2761 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2762 * struct pcmcia_function *pf, 2763 * int ipl, 2764 * int (*func)(void *), 2765 * void *arg); 2766 * 2767 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2768 */ 2769 STATIC void * 2770 pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2771 struct pcmcia_function *pf, int ipl, int (*func)(void *), void *arg) 2772 { 2773 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2774 2775 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2776 /* what should I do? */ 2777 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2778 DPRINTF(("%s does not provide edge nor pulse " 2779 "interrupt\n", device_xname(sc->sc_dev))); 2780 return NULL; 2781 } 2782 /* 2783 * XXX Noooooo! The interrupt flag must set properly!! 2784 * dumb pcmcia driver!! 2785 */ 2786 } 2787 2788 return pccbb_intr_establish(sc, 0, ipl, func, arg); 2789 } 2790 2791 /* 2792 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2793 * void *ih) 2794 * 2795 * This function disables PC-Card interrupt. 2796 */ 2797 STATIC void 2798 pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 2799 { 2800 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2801 2802 pccbb_intr_disestablish(sc, ih); 2803 } 2804 2805 #if rbus 2806 /* 2807 * static int 2808 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2809 * bus_addr_t addr, bus_size_t size, 2810 * bus_addr_t mask, bus_size_t align, 2811 * int flags, bus_addr_t *addrp; 2812 * bus_space_handle_t *bshp) 2813 * 2814 * This function allocates a portion of memory or io space for 2815 * clients. This function is called from CardBus card drivers. 2816 */ 2817 static int 2818 pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2819 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 2820 int flags, bus_addr_t *addrp, bus_space_handle_t *bshp) 2821 { 2822 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2823 2824 DPRINTF(("pccbb_rbus_cb_space_alloc: addr 0x%lx, size 0x%lx, " 2825 "mask 0x%lx, align 0x%lx\n", (unsigned long)addr, 2826 (unsigned long)size, (unsigned long)mask, (unsigned long)align)); 2827 2828 if (align == 0) { 2829 align = size; 2830 } 2831 2832 if (rb->rb_bt == sc->sc_memt) { 2833 if (align < 16) { 2834 return 1; 2835 } 2836 /* 2837 * XXX: align more than 0x1000 to avoid overwrapping 2838 * memory windows for two or more devices. 0x1000 2839 * means memory window's granularity. 2840 * 2841 * Two or more devices should be able to share same 2842 * memory window region. However, overrapping memory 2843 * window is not good because some devices, such as 2844 * 3Com 3C575[BC], have a broken address decoder and 2845 * intrude other's memory region. 2846 */ 2847 if (align < 0x1000) { 2848 align = 0x1000; 2849 } 2850 } else if (rb->rb_bt == sc->sc_iot) { 2851 if (align < 4) { 2852 return 1; 2853 } 2854 /* XXX: hack for avoiding ISA image */ 2855 if (mask < 0x0100) { 2856 mask = 0x3ff; 2857 addr = 0x300; 2858 } 2859 2860 } else { 2861 DPRINTF(("pccbb_rbus_cb_space_alloc: Bus space tag 0x%lx is " 2862 "NOT used. io: 0x%lx, mem: 0x%lx\n", 2863 (unsigned long)rb->rb_bt, (unsigned long)sc->sc_iot, 2864 (unsigned long)sc->sc_memt)); 2865 return 1; 2866 /* XXX: panic here? */ 2867 } 2868 2869 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 2870 aprint_normal_dev(sc->sc_dev, "<rbus> no bus space\n"); 2871 return 1; 2872 } 2873 2874 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 2875 2876 return 0; 2877 } 2878 2879 /* 2880 * static int 2881 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 2882 * bus_space_handle_t *bshp, bus_size_t size); 2883 * 2884 * This function is called from CardBus card drivers. 2885 */ 2886 static int 2887 pccbb_rbus_cb_space_free(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2888 bus_space_handle_t bsh, bus_size_t size) 2889 { 2890 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2891 bus_space_tag_t bt = rb->rb_bt; 2892 2893 pccbb_close_win(sc, bt, bsh, size); 2894 2895 if (bt == sc->sc_memt) { 2896 } else if (bt == sc->sc_iot) { 2897 } else { 2898 return 1; 2899 /* XXX: panic here? */ 2900 } 2901 2902 return rbus_space_free(rb, bsh, size, NULL); 2903 } 2904 #endif /* rbus */ 2905 2906 #if rbus 2907 2908 static int 2909 pccbb_open_win(struct pccbb_softc *sc, bus_space_tag_t bst, bus_addr_t addr, 2910 bus_size_t size, bus_space_handle_t bsh, int flags) 2911 { 2912 struct pccbb_win_chain_head *head; 2913 bus_addr_t align; 2914 2915 head = &sc->sc_iowindow; 2916 align = 0x04; 2917 if (sc->sc_memt == bst) { 2918 head = &sc->sc_memwindow; 2919 align = 0x1000; 2920 DPRINTF(("using memory window, 0x%lx 0x%lx 0x%lx\n\n", 2921 (unsigned long)sc->sc_iot, (unsigned long)sc->sc_memt, 2922 (unsigned long)bst)); 2923 } 2924 2925 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 2926 aprint_error_dev(sc->sc_dev, 2927 "pccbb_open_win: %s winlist insert failed\n", 2928 (head == &sc->sc_memwindow) ? "mem" : "io"); 2929 } 2930 pccbb_winset(align, sc, bst); 2931 2932 return 0; 2933 } 2934 2935 static int 2936 pccbb_close_win(struct pccbb_softc *sc, bus_space_tag_t bst, 2937 bus_space_handle_t bsh, bus_size_t size) 2938 { 2939 struct pccbb_win_chain_head *head; 2940 bus_addr_t align; 2941 2942 head = &sc->sc_iowindow; 2943 align = 0x04; 2944 if (sc->sc_memt == bst) { 2945 head = &sc->sc_memwindow; 2946 align = 0x1000; 2947 } 2948 2949 if (pccbb_winlist_delete(head, bsh, size)) { 2950 aprint_error_dev(sc->sc_dev, 2951 "pccbb_close_win: %s winlist delete failed\n", 2952 (head == &sc->sc_memwindow) ? "mem" : "io"); 2953 } 2954 pccbb_winset(align, sc, bst); 2955 2956 return 0; 2957 } 2958 2959 static int 2960 pccbb_winlist_insert(struct pccbb_win_chain_head *head, bus_addr_t start, 2961 bus_size_t size, bus_space_handle_t bsh, int flags) 2962 { 2963 struct pccbb_win_chain *chainp, *elem; 2964 2965 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 2966 M_NOWAIT)) == NULL) 2967 return (1); /* fail */ 2968 2969 elem->wc_start = start; 2970 elem->wc_end = start + (size - 1); 2971 elem->wc_handle = bsh; 2972 elem->wc_flags = flags; 2973 2974 TAILQ_FOREACH(chainp, head, wc_list) { 2975 if (chainp->wc_end >= start) 2976 break; 2977 } 2978 if (chainp != NULL) 2979 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 2980 else 2981 TAILQ_INSERT_TAIL(head, elem, wc_list); 2982 return (0); 2983 } 2984 2985 static int 2986 pccbb_winlist_delete(struct pccbb_win_chain_head *head, bus_space_handle_t bsh, 2987 bus_size_t size) 2988 { 2989 struct pccbb_win_chain *chainp; 2990 2991 TAILQ_FOREACH(chainp, head, wc_list) { 2992 if (memcmp(&chainp->wc_handle, &bsh, sizeof(bsh)) == 0) 2993 break; 2994 } 2995 if (chainp == NULL) 2996 return 1; /* fail: no candidate to remove */ 2997 2998 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 2999 printf("pccbb_winlist_delete: window 0x%lx size " 3000 "inconsistent: 0x%lx, 0x%lx\n", 3001 (unsigned long)chainp->wc_start, 3002 (unsigned long)(chainp->wc_end - chainp->wc_start), 3003 (unsigned long)(size - 1)); 3004 return 1; 3005 } 3006 3007 TAILQ_REMOVE(head, chainp, wc_list); 3008 free(chainp, M_DEVBUF); 3009 3010 return 0; 3011 } 3012 3013 static void 3014 pccbb_winset(bus_addr_t align, struct pccbb_softc *sc, bus_space_tag_t bst) 3015 { 3016 pci_chipset_tag_t pc; 3017 pcitag_t tag; 3018 bus_addr_t mask = ~(align - 1); 3019 struct { 3020 cardbusreg_t win_start; 3021 cardbusreg_t win_limit; 3022 int win_flags; 3023 } win[2]; 3024 struct pccbb_win_chain *chainp; 3025 int offs; 3026 3027 win[0].win_start = win[1].win_start = 0xffffffff; 3028 win[0].win_limit = win[1].win_limit = 0; 3029 win[0].win_flags = win[1].win_flags = 0; 3030 3031 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3032 offs = PCI_CB_IOBASE0; 3033 if (sc->sc_memt == bst) { 3034 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3035 offs = PCI_CB_MEMBASE0; 3036 } 3037 3038 if (chainp != NULL) { 3039 win[0].win_start = chainp->wc_start & mask; 3040 win[0].win_limit = chainp->wc_end & mask; 3041 win[0].win_flags = chainp->wc_flags; 3042 chainp = TAILQ_NEXT(chainp, wc_list); 3043 } 3044 3045 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3046 if (win[1].win_start == 0xffffffff) { 3047 /* window 1 is not used */ 3048 if ((win[0].win_flags == chainp->wc_flags) && 3049 (win[0].win_limit + align >= 3050 (chainp->wc_start & mask))) { 3051 /* concatenate */ 3052 win[0].win_limit = chainp->wc_end & mask; 3053 } else { 3054 /* make new window */ 3055 win[1].win_start = chainp->wc_start & mask; 3056 win[1].win_limit = chainp->wc_end & mask; 3057 win[1].win_flags = chainp->wc_flags; 3058 } 3059 continue; 3060 } 3061 3062 /* Both windows are engaged. */ 3063 if (win[0].win_flags == win[1].win_flags) { 3064 /* same flags */ 3065 if (win[0].win_flags == chainp->wc_flags) { 3066 if (win[1].win_start - (win[0].win_limit + 3067 align) < 3068 (chainp->wc_start & mask) - 3069 ((chainp->wc_end & mask) + align)) { 3070 /* 3071 * merge window 0 and 1, and set win1 3072 * to chainp 3073 */ 3074 win[0].win_limit = win[1].win_limit; 3075 win[1].win_start = 3076 chainp->wc_start & mask; 3077 win[1].win_limit = 3078 chainp->wc_end & mask; 3079 } else { 3080 win[1].win_limit = 3081 chainp->wc_end & mask; 3082 } 3083 } else { 3084 /* different flags */ 3085 3086 /* concatenate win0 and win1 */ 3087 win[0].win_limit = win[1].win_limit; 3088 /* allocate win[1] to new space */ 3089 win[1].win_start = chainp->wc_start & mask; 3090 win[1].win_limit = chainp->wc_end & mask; 3091 win[1].win_flags = chainp->wc_flags; 3092 } 3093 } else { 3094 /* the flags of win[0] and win[1] is different */ 3095 if (win[0].win_flags == chainp->wc_flags) { 3096 win[0].win_limit = chainp->wc_end & mask; 3097 /* 3098 * XXX this creates overlapping windows, so 3099 * what should the poor bridge do if one is 3100 * cachable, and the other is not? 3101 */ 3102 aprint_error_dev(sc->sc_dev, 3103 "overlapping windows\n"); 3104 } else { 3105 win[1].win_limit = chainp->wc_end & mask; 3106 } 3107 } 3108 } 3109 3110 pc = sc->sc_pc; 3111 tag = sc->sc_tag; 3112 pci_conf_write(pc, tag, offs, win[0].win_start); 3113 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3114 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3115 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3116 DPRINTF(("--pccbb_winset: win0 [0x%lx, 0x%lx), win1 [0x%lx, 0x%lx)\n", 3117 (unsigned long)pci_conf_read(pc, tag, offs), 3118 (unsigned long)pci_conf_read(pc, tag, offs + 4) + align, 3119 (unsigned long)pci_conf_read(pc, tag, offs + 8), 3120 (unsigned long)pci_conf_read(pc, tag, offs + 12) + align)); 3121 3122 if (bst == sc->sc_memt) { 3123 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BRIDGE_CONTROL_REG); 3124 3125 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 3126 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 3127 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3128 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 3129 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3130 pci_conf_write(pc, tag, PCI_BRIDGE_CONTROL_REG, bcr); 3131 } 3132 } 3133 3134 #endif /* rbus */ 3135 3136 static bool 3137 pccbb_suspend(device_t dv PMF_FN_ARGS) 3138 { 3139 struct pccbb_softc *sc = device_private(dv); 3140 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3141 bus_space_handle_t base_memh = sc->sc_base_memh; 3142 pcireg_t reg; 3143 3144 if (sc->sc_pil_intr_enable) 3145 (void)pccbbintr_function(sc); 3146 sc->sc_pil_intr_enable = 0; 3147 3148 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3149 /* Disable interrupts. */ 3150 reg &= ~(CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER); 3151 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3152 /* XXX joerg Disable power to the socket? */ 3153 3154 /* XXX flush PCI write */ 3155 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3156 3157 /* reset interrupt */ 3158 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, 3159 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT)); 3160 /* XXX flush PCI write */ 3161 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3162 3163 if (sc->sc_ih != NULL) { 3164 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 3165 sc->sc_ih = NULL; 3166 } 3167 3168 return true; 3169 } 3170 3171 static bool 3172 pccbb_resume(device_t dv PMF_FN_ARGS) 3173 { 3174 struct pccbb_softc *sc = device_private(dv); 3175 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3176 bus_space_handle_t base_memh = sc->sc_base_memh; 3177 pcireg_t reg; 3178 3179 pccbb_chipinit(sc); 3180 pccbb_intrinit(sc); 3181 /* setup memory and io space window for CB */ 3182 pccbb_winset(0x1000, sc, sc->sc_memt); 3183 pccbb_winset(0x04, sc, sc->sc_iot); 3184 3185 /* CSC Interrupt: Card detect interrupt on */ 3186 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3187 /* Card detect intr is turned on. */ 3188 reg |= CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; 3189 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3190 /* reset interrupt */ 3191 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3192 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3193 3194 /* 3195 * check for card insertion or removal during suspend period. 3196 * XXX: the code can't cope with card swap (remove then 3197 * insert). how can we detect such situation? 3198 */ 3199 (void)pccbbintr(sc); 3200 3201 sc->sc_pil_intr_enable = 1; 3202 3203 return true; 3204 } 3205
Indexes created Sun Sep 28 07:09:56 GMT 2025