pccbb.c revision 1.179
1 /* $NetBSD: pccbb.c,v 1.179 2008/08/06 15:50:46 dyoung Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: pccbb.c,v 1.179 2008/08/06 15:50:46 dyoung Exp $"); 35 36 /* 37 #define CBB_DEBUG 38 #define SHOW_REGS 39 */ 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/kernel.h> 44 #include <sys/errno.h> 45 #include <sys/ioctl.h> 46 #include <sys/reboot.h> /* for bootverbose */ 47 #include <sys/syslog.h> 48 #include <sys/device.h> 49 #include <sys/malloc.h> 50 #include <sys/proc.h> 51 52 #include <sys/intr.h> 53 #include <sys/bus.h> 54 55 #include <dev/pci/pcivar.h> 56 #include <dev/pci/pcireg.h> 57 #include <dev/pci/pcidevs.h> 58 59 #include <dev/pci/pccbbreg.h> 60 61 #include <dev/cardbus/cardslotvar.h> 62 63 #include <dev/cardbus/cardbusvar.h> 64 65 #include <dev/pcmcia/pcmciareg.h> 66 #include <dev/pcmcia/pcmciavar.h> 67 68 #include <dev/ic/i82365reg.h> 69 #include <dev/pci/pccbbvar.h> 70 71 #ifndef __NetBSD_Version__ 72 struct cfdriver cbb_cd = { 73 NULL, "cbb", DV_DULL 74 }; 75 #endif 76 77 #ifdef CBB_DEBUG 78 #define DPRINTF(x) printf x 79 #define STATIC 80 #else 81 #define DPRINTF(x) 82 #define STATIC static 83 #endif 84 85 int pccbb_burstup = 1; 86 87 /* 88 * delay_ms() is wait in milliseconds. It should be used instead 89 * of delay() if you want to wait more than 1 ms. 90 */ 91 static inline void 92 delay_ms(int millis, void *param) 93 { 94 if (cold) 95 delay(millis * 1000); 96 else 97 tsleep(param, PWAIT, "pccbb", MAX(2, hz * millis / 1000)); 98 } 99 100 int pcicbbmatch(device_t, struct cfdata *, void *); 101 void pccbbattach(device_t, device_t, void *); 102 int pccbbdetach(device_t, int); 103 int pccbbintr(void *); 104 static void pci113x_insert(void *); 105 static int pccbbintr_function(struct pccbb_softc *); 106 107 static int pccbb_detect_card(struct pccbb_softc *); 108 109 static void pccbb_pcmcia_write(struct pccbb_softc *, int, u_int8_t); 110 static u_int8_t pccbb_pcmcia_read(struct pccbb_softc *, int); 111 #define Pcic_read(sc, reg) pccbb_pcmcia_read((sc), (reg)) 112 #define Pcic_write(sc, reg, val) pccbb_pcmcia_write((sc), (reg), (val)) 113 114 STATIC int cb_reset(struct pccbb_softc *); 115 STATIC int cb_detect_voltage(struct pccbb_softc *); 116 STATIC int cbbprint(void *, const char *); 117 118 static int cb_chipset(u_int32_t, int *); 119 STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *, 120 struct pcmciabus_attach_args *); 121 122 STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int); 123 STATIC int pccbb_power(struct pccbb_softc *sc, int); 124 STATIC int pccbb_power_ct(cardbus_chipset_tag_t, int); 125 STATIC int pccbb_cardenable(struct pccbb_softc * sc, int function); 126 #if !rbus 127 static int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 128 static int pccbb_io_close(cardbus_chipset_tag_t, int); 129 static int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 130 static int pccbb_mem_close(cardbus_chipset_tag_t, int); 131 #endif /* !rbus */ 132 static void *pccbb_intr_establish(struct pccbb_softc *, 133 cardbus_intr_line_t irq, int level, int (*ih) (void *), void *sc); 134 static void pccbb_intr_disestablish(struct pccbb_softc *, void *ih); 135 136 static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t, 137 cardbus_intr_line_t irq, int level, int (*ih) (void *), void *sc); 138 static void pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih); 139 140 static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t, int, int); 141 static void pccbb_free_tag(cardbus_chipset_tag_t, cardbustag_t); 142 static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t, cardbustag_t, int); 143 static void pccbb_conf_write(cardbus_chipset_tag_t, cardbustag_t, int, 144 cardbusreg_t); 145 static void pccbb_chipinit(struct pccbb_softc *); 146 static void pccbb_intrinit(struct pccbb_softc *); 147 148 STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 149 struct pcmcia_mem_handle *); 150 STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t, 151 struct pcmcia_mem_handle *); 152 STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 153 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *); 154 STATIC void pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t, int); 155 STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 156 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 157 STATIC void pccbb_pcmcia_io_free(pcmcia_chipset_handle_t, 158 struct pcmcia_io_handle *); 159 STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 160 bus_size_t, struct pcmcia_io_handle *, int *); 161 STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t, int); 162 STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t, 163 struct pcmcia_function *, int, int (*)(void *), void *); 164 STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t, void *); 165 STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t); 166 STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t); 167 STATIC void pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t, int); 168 STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch); 169 170 static int pccbb_pcmcia_wait_ready(struct pccbb_softc *); 171 static void pccbb_pcmcia_delay(struct pccbb_softc *, int, const char *); 172 173 static void pccbb_pcmcia_do_io_map(struct pccbb_softc *, int); 174 static void pccbb_pcmcia_do_mem_map(struct pccbb_softc *, int); 175 176 /* bus-space allocation and deallocation functions */ 177 #if rbus 178 179 static int pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t, rbus_tag_t, 180 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 181 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp); 182 static int pccbb_rbus_cb_space_free(cardbus_chipset_tag_t, rbus_tag_t, 183 bus_space_handle_t, bus_size_t); 184 185 #endif /* rbus */ 186 187 #if rbus 188 189 static int pccbb_open_win(struct pccbb_softc *, bus_space_tag_t, 190 bus_addr_t, bus_size_t, bus_space_handle_t, int flags); 191 static int pccbb_close_win(struct pccbb_softc *, bus_space_tag_t, 192 bus_space_handle_t, bus_size_t); 193 static int pccbb_winlist_insert(struct pccbb_win_chain_head *, bus_addr_t, 194 bus_size_t, bus_space_handle_t, int); 195 static int pccbb_winlist_delete(struct pccbb_win_chain_head *, 196 bus_space_handle_t, bus_size_t); 197 static void pccbb_winset(bus_addr_t align, struct pccbb_softc *, 198 bus_space_tag_t); 199 void pccbb_winlist_show(struct pccbb_win_chain *); 200 201 #endif /* rbus */ 202 203 /* for config_defer */ 204 static void pccbb_pci_callback(device_t); 205 206 static bool pccbb_suspend(device_t PMF_FN_PROTO); 207 static bool pccbb_resume(device_t PMF_FN_PROTO); 208 209 #if defined SHOW_REGS 210 static void cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, 211 bus_space_tag_t memt, bus_space_handle_t memh); 212 #endif 213 214 CFATTACH_DECL_NEW(cbb_pci, sizeof(struct pccbb_softc), 215 pcicbbmatch, pccbbattach, pccbbdetach, NULL); 216 217 static const struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 218 pccbb_pcmcia_mem_alloc, 219 pccbb_pcmcia_mem_free, 220 pccbb_pcmcia_mem_map, 221 pccbb_pcmcia_mem_unmap, 222 pccbb_pcmcia_io_alloc, 223 pccbb_pcmcia_io_free, 224 pccbb_pcmcia_io_map, 225 pccbb_pcmcia_io_unmap, 226 pccbb_pcmcia_intr_establish, 227 pccbb_pcmcia_intr_disestablish, 228 pccbb_pcmcia_socket_enable, 229 pccbb_pcmcia_socket_disable, 230 pccbb_pcmcia_socket_settype, 231 pccbb_pcmcia_card_detect 232 }; 233 234 #if rbus 235 static const struct cardbus_functions pccbb_funcs = { 236 pccbb_rbus_cb_space_alloc, 237 pccbb_rbus_cb_space_free, 238 pccbb_cb_intr_establish, 239 pccbb_cb_intr_disestablish, 240 pccbb_ctrl, 241 pccbb_power_ct, 242 pccbb_make_tag, 243 pccbb_free_tag, 244 pccbb_conf_read, 245 pccbb_conf_write, 246 }; 247 #else 248 static const struct cardbus_functions pccbb_funcs = { 249 pccbb_ctrl, 250 pccbb_power_ct, 251 pccbb_mem_open, 252 pccbb_mem_close, 253 pccbb_io_open, 254 pccbb_io_close, 255 pccbb_cb_intr_establish, 256 pccbb_cb_intr_disestablish, 257 pccbb_make_tag, 258 pccbb_conf_read, 259 pccbb_conf_write, 260 }; 261 #endif 262 263 int 264 pcicbbmatch(device_t parent, struct cfdata *match, void *aux) 265 { 266 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 267 268 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 269 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 270 PCI_INTERFACE(pa->pa_class) == 0) { 271 return 1; 272 } 273 274 return 0; 275 } 276 277 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 278 | ((prod) << PCI_PRODUCT_SHIFT)) 279 280 const struct yenta_chipinfo { 281 pcireg_t yc_id; /* vendor tag | product tag */ 282 int yc_chiptype; 283 int yc_flags; 284 } yc_chipsets[] = { 285 /* Texas Instruments chips */ 286 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 287 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 288 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 289 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 290 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI125X, 291 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 292 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 293 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 294 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 295 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 296 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 297 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 298 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI125X, 299 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 300 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI125X, 301 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 302 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 303 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 304 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 305 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 306 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI1420, 307 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 308 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI125X, 309 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 310 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 311 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 312 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1520), CB_TI12XX, 313 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 314 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4410YENTA), CB_TI12XX, 315 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 316 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4520YENTA), CB_TI12XX, 317 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 318 319 /* Ricoh chips */ 320 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 321 PCCBB_PCMCIA_MEM_32}, 322 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 323 PCCBB_PCMCIA_MEM_32}, 324 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 325 PCCBB_PCMCIA_MEM_32}, 326 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 327 PCCBB_PCMCIA_MEM_32}, 328 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 329 PCCBB_PCMCIA_MEM_32}, 330 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 331 PCCBB_PCMCIA_MEM_32}, 332 333 /* Toshiba products */ 334 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 335 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 336 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 337 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 338 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 339 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 340 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 341 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 342 343 /* Cirrus Logic products */ 344 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 345 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 346 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 347 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 348 349 /* O2 Micro products */ 350 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6729), 351 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 352 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6730), 353 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 354 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6832), 355 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 356 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6836), 357 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 358 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6872), 359 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 360 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6922), 361 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 362 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6933), 363 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 364 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6972), 365 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 366 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_7223), 367 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 368 369 /* sentinel, or Generic chip */ 370 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 371 }; 372 373 static int 374 cb_chipset(u_int32_t pci_id, int *flagp) 375 { 376 const struct yenta_chipinfo *yc; 377 378 /* Loop over except the last default entry. */ 379 for (yc = yc_chipsets; yc < yc_chipsets + 380 __arraycount(yc_chipsets) - 1; yc++) 381 if (pci_id == yc->yc_id) 382 break; 383 384 if (flagp != NULL) 385 *flagp = yc->yc_flags; 386 387 return (yc->yc_chiptype); 388 } 389 390 void 391 pccbbattach(device_t parent, device_t self, void *aux) 392 { 393 struct pccbb_softc *sc = device_private(self); 394 struct pci_attach_args *pa = aux; 395 pci_chipset_tag_t pc = pa->pa_pc; 396 pcireg_t busreg, reg, sock_base; 397 bus_addr_t sockbase; 398 char devinfo[256]; 399 int flags; 400 401 #ifdef __HAVE_PCCBB_ATTACH_HOOK 402 pccbb_attach_hook(parent, self, pa); 403 #endif 404 405 sc->sc_dev = self; 406 407 callout_init(&sc->sc_insert_ch, 0); 408 callout_setfunc(&sc->sc_insert_ch, pci113x_insert, sc); 409 410 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 411 412 aprint_naive("\n"); 413 414 pci_devinfo(pa->pa_id, 0, 0, devinfo, sizeof(devinfo)); 415 aprint_normal(": %s (rev. 0x%02x)", devinfo, 416 PCI_REVISION(pa->pa_class)); 417 DPRINTF((" (chipflags %x)", flags)); 418 aprint_normal("\n"); 419 420 TAILQ_INIT(&sc->sc_memwindow); 421 TAILQ_INIT(&sc->sc_iowindow); 422 423 #if rbus 424 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 425 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 426 427 #if 0 428 printf("pa->pa_memt: %08x vs rbus_mem->rb_bt: %08x\n", 429 pa->pa_memt, sc->sc_rbus_memt->rb_bt); 430 #endif 431 #endif /* rbus */ 432 433 sc->sc_flags &= ~CBB_MEMHMAPPED; 434 435 /* 436 * MAP socket registers and ExCA registers on memory-space 437 * When no valid address is set on socket base registers (on pci 438 * config space), get it not polite way. 439 */ 440 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 441 442 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 443 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 444 /* The address must be valid. */ 445 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 446 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, &sc->sc_base_size)) { 447 aprint_error_dev(self, 448 "can't map socket base address 0x%lx\n", 449 (unsigned long)sock_base); 450 /* 451 * I think it's funny: socket base registers must be 452 * mapped on memory space, but ... 453 */ 454 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 455 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 456 &sc->sc_base_size)) { 457 aprint_error_dev(self, 458 "can't map socket base address" 459 " 0x%lx: io mode\n", 460 (unsigned long)sockbase); 461 /* give up... allocate reg space via rbus. */ 462 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 463 } else 464 sc->sc_flags |= CBB_MEMHMAPPED; 465 } else { 466 DPRINTF(("%s: socket base address 0x%lx\n", 467 device_xname(self), 468 (unsigned long)sockbase)); 469 sc->sc_flags |= CBB_MEMHMAPPED; 470 } 471 } 472 473 sc->sc_mem_start = 0; /* XXX */ 474 sc->sc_mem_end = 0xffffffff; /* XXX */ 475 476 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 477 478 /* pccbb_machdep.c end */ 479 480 #if defined CBB_DEBUG 481 { 482 static const char *intrname[] = { "NON", "A", "B", "C", "D" }; 483 aprint_debug_dev(self, "intrpin %s, intrtag %d\n", 484 intrname[pa->pa_intrpin], pa->pa_intrline); 485 } 486 #endif 487 488 /* setup softc */ 489 sc->sc_pc = pc; 490 sc->sc_iot = pa->pa_iot; 491 sc->sc_memt = pa->pa_memt; 492 sc->sc_dmat = pa->pa_dmat; 493 sc->sc_tag = pa->pa_tag; 494 495 memcpy(&sc->sc_pa, pa, sizeof(*pa)); 496 497 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 498 499 /* Disable legacy register mapping. */ 500 switch (sc->sc_chipset) { 501 case CB_RX5C46X: /* fallthrough */ 502 #if 0 503 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 504 case CB_RX5C47X: 505 #endif 506 /* 507 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 508 * cannot be disabled by substituting 0 into PCI_LEGACY 509 * register. Ricoh CardBus bridges have special bits on Bridge 510 * control reg (addr 0x3e on PCI config space). 511 */ 512 reg = pci_conf_read(pc, pa->pa_tag, PCI_BRIDGE_CONTROL_REG); 513 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 514 pci_conf_write(pc, pa->pa_tag, PCI_BRIDGE_CONTROL_REG, reg); 515 break; 516 517 default: 518 /* XXX I don't know proper way to kill legacy I/O. */ 519 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 520 break; 521 } 522 523 if (!pmf_device_register(self, pccbb_suspend, pccbb_resume)) 524 aprint_error_dev(self, "couldn't establish power handler\n"); 525 526 config_defer(self, pccbb_pci_callback); 527 } 528 529 int 530 pccbbdetach(device_t self, int flags) 531 { 532 struct pccbb_softc *sc = device_private(self); 533 pci_chipset_tag_t pc = sc->sc_pa.pa_pc; 534 bus_space_tag_t bmt = sc->sc_base_memt; 535 bus_space_handle_t bmh = sc->sc_base_memh; 536 uint32_t sockmask; 537 int rc; 538 539 if ((rc = config_detach_children(self, flags)) != 0) 540 return rc; 541 542 if (!LIST_EMPTY(&sc->sc_pil)) { 543 panic("%s: interrupt handlers still registered", 544 device_xname(self)); 545 return EBUSY; 546 } 547 548 if (sc->sc_ih != NULL) { 549 pci_intr_disestablish(pc, sc->sc_ih); 550 sc->sc_ih = NULL; 551 } 552 553 /* CSC Interrupt: turn off card detect and power cycle interrupts */ 554 sockmask = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 555 sockmask &= ~(CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | 556 CB_SOCKET_MASK_POWER); 557 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, sockmask); 558 /* reset interrupt */ 559 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 560 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 561 562 switch (sc->sc_flags & (CBB_MEMHMAPPED|CBB_SPECMAPPED)) { 563 case CBB_MEMHMAPPED: 564 bus_space_unmap(bmt, bmh, sc->sc_base_size); 565 break; 566 case CBB_MEMHMAPPED|CBB_SPECMAPPED: 567 #if rbus 568 { 569 pcireg_t sockbase; 570 571 sockbase = pci_conf_read(pc, sc->sc_tag, PCI_SOCKBASE); 572 rbus_space_free(sc->sc_rbus_memt, bmh, 0x1000, 573 NULL); 574 } 575 #else 576 bus_space_free(bmt, bmh, 0x1000); 577 #endif 578 } 579 sc->sc_flags &= ~(CBB_MEMHMAPPED|CBB_SPECMAPPED); 580 581 if (!TAILQ_EMPTY(&sc->sc_iowindow)) 582 aprint_error_dev(self, "i/o windows not empty"); 583 if (!TAILQ_EMPTY(&sc->sc_memwindow)) 584 aprint_error_dev(self, "memory windows not empty"); 585 586 callout_stop(&sc->sc_insert_ch); 587 callout_destroy(&sc->sc_insert_ch); 588 return 0; 589 } 590 591 /* 592 * static void pccbb_pci_callback(device_t self) 593 * 594 * The actual attach routine: get memory space for YENTA register 595 * space, setup YENTA register and route interrupt. 596 * 597 * This function should be deferred because this device may obtain 598 * memory space dynamically. This function must avoid obtaining 599 * memory area which has already kept for another device. 600 */ 601 static void 602 pccbb_pci_callback(device_t self) 603 { 604 struct pccbb_softc *sc = device_private(self); 605 pci_chipset_tag_t pc = sc->sc_pc; 606 bus_addr_t sockbase; 607 struct cbslot_attach_args cba; 608 struct pcmciabus_attach_args paa; 609 struct cardslot_attach_args caa; 610 device_t csc; 611 612 if (!(sc->sc_flags & CBB_MEMHMAPPED)) { 613 /* The socket registers aren't mapped correctly. */ 614 #if rbus 615 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 616 (sc->sc_chipset == CB_RX5C47X 617 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 618 0, &sockbase, &sc->sc_base_memh)) { 619 return; 620 } 621 sc->sc_base_memt = sc->sc_memt; 622 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 623 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 624 device_xname(self), (unsigned long)sockbase, 625 (unsigned long)pci_conf_read(pc, sc->sc_tag, 626 PCI_SOCKBASE))); 627 #else 628 sc->sc_base_memt = sc->sc_memt; 629 #if !defined CBB_PCI_BASE 630 #define CBB_PCI_BASE 0x20000000 631 #endif 632 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 633 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 634 /* cannot allocate memory space */ 635 return; 636 } 637 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 638 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 639 device_xname(self), (unsigned long)sock_base, 640 (unsigned long)pci_conf_read(pc, 641 sc->sc_tag, PCI_SOCKBASE))); 642 #endif 643 sc->sc_flags |= CBB_MEMHMAPPED; 644 } 645 646 /* clear data structure for child device interrupt handlers */ 647 LIST_INIT(&sc->sc_pil); 648 649 /* bus bridge initialization */ 650 pccbb_chipinit(sc); 651 652 sc->sc_pil_intr_enable = 1; 653 654 { 655 u_int32_t sockstat; 656 657 sockstat = bus_space_read_4(sc->sc_base_memt, 658 sc->sc_base_memh, CB_SOCKET_STAT); 659 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 660 sc->sc_flags |= CBB_CARDEXIST; 661 } 662 } 663 664 /* 665 * attach cardbus 666 */ 667 { 668 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 669 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 670 671 /* initialize cbslot_attach */ 672 cba.cba_iot = sc->sc_iot; 673 cba.cba_memt = sc->sc_memt; 674 cba.cba_dmat = sc->sc_dmat; 675 cba.cba_bus = (busreg >> 8) & 0x0ff; 676 cba.cba_cc = (void *)sc; 677 cba.cba_cf = &pccbb_funcs; 678 cba.cba_intrline = 0; /* XXX dummy */ 679 680 #if rbus 681 cba.cba_rbus_iot = sc->sc_rbus_iot; 682 cba.cba_rbus_memt = sc->sc_rbus_memt; 683 #endif 684 685 cba.cba_cacheline = PCI_CACHELINE(bhlc); 686 cba.cba_max_lattimer = PCI_LATTIMER(bhlc); 687 688 aprint_verbose_dev(self, 689 "cacheline 0x%x lattimer 0x%x\n", 690 cba.cba_cacheline, 691 cba.cba_max_lattimer); 692 aprint_verbose_dev(self, "bhlc 0x%x\n", bhlc); 693 #if defined SHOW_REGS 694 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 695 sc->sc_base_memh); 696 #endif 697 } 698 699 pccbb_pcmcia_attach_setup(sc, &paa); 700 caa.caa_cb_attach = NULL; 701 if (cba.cba_bus == 0) 702 aprint_error_dev(self, 703 "secondary bus number uninitialized; try PCI_BUS_FIXUP\n"); 704 else 705 caa.caa_cb_attach = &cba; 706 caa.caa_16_attach = &paa; 707 708 pccbb_intrinit(sc); 709 710 if (NULL != (csc = config_found_ia(self, "pcmciaslot", &caa, 711 cbbprint))) { 712 DPRINTF(("%s: found cardslot\n", __func__)); 713 sc->sc_csc = device_private(csc); 714 } 715 716 return; 717 } 718 719 720 721 722 723 /* 724 * static void pccbb_chipinit(struct pccbb_softc *sc) 725 * 726 * This function initialize YENTA chip registers listed below: 727 * 1) PCI command reg, 728 * 2) PCI and CardBus latency timer, 729 * 3) route PCI interrupt, 730 * 4) close all memory and io windows. 731 * 5) turn off bus power. 732 * 6) card detect and power cycle interrupts on. 733 * 7) clear interrupt 734 */ 735 static void 736 pccbb_chipinit(struct pccbb_softc *sc) 737 { 738 pci_chipset_tag_t pc = sc->sc_pc; 739 pcitag_t tag = sc->sc_tag; 740 bus_space_tag_t bmt = sc->sc_base_memt; 741 bus_space_handle_t bmh = sc->sc_base_memh; 742 pcireg_t bcr, bhlc, cbctl, csr, lscp, mfunc, mrburst, slotctl, sockctl, 743 sysctrl; 744 745 /* 746 * Set PCI command reg. 747 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 748 */ 749 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 750 /* I believe it is harmless. */ 751 csr |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 752 PCI_COMMAND_MASTER_ENABLE); 753 754 /* All O2 Micro chips have broken parity-error reporting 755 * until proven otherwise. The OZ6933 PCI-CardBus Bridge 756 * is known to have the defect---see PR kern/38698. 757 */ 758 if (sc->sc_chipset != CB_O2MICRO) 759 csr |= PCI_COMMAND_PARITY_ENABLE; 760 761 csr |= PCI_COMMAND_SERR_ENABLE; 762 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 763 764 /* 765 * Set CardBus latency timer. 766 */ 767 lscp = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 768 if (PCI_CB_LATENCY(lscp) < 0x20) { 769 lscp &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 770 lscp |= (0x20 << PCI_CB_LATENCY_SHIFT); 771 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, lscp); 772 } 773 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 774 PCI_CB_LATENCY(lscp), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 775 776 /* 777 * Set PCI latency timer. 778 */ 779 bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG); 780 if (PCI_LATTIMER(bhlc) < 0x10) { 781 bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 782 bhlc |= (0x10 << PCI_LATTIMER_SHIFT); 783 pci_conf_write(pc, tag, PCI_BHLC_REG, bhlc); 784 } 785 DPRINTF(("PCI latency timer 0x%x (%x)\n", 786 PCI_LATTIMER(bhlc), pci_conf_read(pc, tag, PCI_BHLC_REG))); 787 788 789 /* Route functional interrupts to PCI. */ 790 bcr = pci_conf_read(pc, tag, PCI_BRIDGE_CONTROL_REG); 791 bcr |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 792 bcr |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 793 /* assert reset */ 794 bcr |= PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT; 795 /* Set master abort mode to 1, forward SERR# from secondary 796 * to primary, and detect parity errors on secondary. 797 */ 798 bcr |= PCI_BRIDGE_CONTROL_MABRT << PCI_BRIDGE_CONTROL_SHIFT; 799 bcr |= PCI_BRIDGE_CONTROL_SERR << PCI_BRIDGE_CONTROL_SHIFT; 800 bcr |= PCI_BRIDGE_CONTROL_PERE << PCI_BRIDGE_CONTROL_SHIFT; 801 pci_conf_write(pc, tag, PCI_BRIDGE_CONTROL_REG, bcr); 802 803 switch (sc->sc_chipset) { 804 case CB_TI113X: 805 cbctl = pci_conf_read(pc, tag, PCI_CBCTRL); 806 /* This bit is shared, but may read as 0 on some chips, so set 807 it explicitly on both functions. */ 808 cbctl |= PCI113X_CBCTRL_PCI_IRQ_ENA; 809 /* CSC intr enable */ 810 cbctl |= PCI113X_CBCTRL_PCI_CSC; 811 /* functional intr prohibit | prohibit ISA routing */ 812 cbctl &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 813 pci_conf_write(pc, tag, PCI_CBCTRL, cbctl); 814 break; 815 816 case CB_TI1420: 817 sysctrl = pci_conf_read(pc, tag, PCI_SYSCTRL); 818 mrburst = pccbb_burstup 819 ? PCI1420_SYSCTRL_MRBURST : PCI1420_SYSCTRL_MRBURSTDN; 820 if ((sysctrl & PCI1420_SYSCTRL_MRBURST) == mrburst) { 821 printf("%s: %swrite bursts enabled\n", 822 device_xname(sc->sc_dev), 823 pccbb_burstup ? "read/" : ""); 824 } else if (pccbb_burstup) { 825 printf("%s: enabling read/write bursts\n", 826 device_xname(sc->sc_dev)); 827 sysctrl |= PCI1420_SYSCTRL_MRBURST; 828 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 829 } else { 830 printf("%s: disabling read bursts, " 831 "enabling write bursts\n", 832 device_xname(sc->sc_dev)); 833 sysctrl |= PCI1420_SYSCTRL_MRBURSTDN; 834 sysctrl &= ~PCI1420_SYSCTRL_MRBURSTUP; 835 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 836 } 837 /*FALLTHROUGH*/ 838 case CB_TI12XX: 839 /* 840 * Some TI 12xx (and [14][45]xx) based pci cards 841 * sometimes have issues with the MFUNC register not 842 * being initialized due to a bad EEPROM on board. 843 * Laptops that this matters on have this register 844 * properly initialized. 845 * 846 * The TI125X parts have a different register. 847 */ 848 mfunc = pci_conf_read(pc, tag, PCI12XX_MFUNC); 849 if (mfunc == 0) { 850 mfunc &= ~PCI12XX_MFUNC_PIN0; 851 mfunc |= PCI12XX_MFUNC_PIN0_INTA; 852 if ((pci_conf_read(pc, tag, PCI_SYSCTRL) & 853 PCI12XX_SYSCTRL_INTRTIE) == 0) { 854 mfunc &= ~PCI12XX_MFUNC_PIN1; 855 mfunc |= PCI12XX_MFUNC_PIN1_INTB; 856 } 857 pci_conf_write(pc, tag, PCI12XX_MFUNC, mfunc); 858 } 859 /* fallthrough */ 860 861 case CB_TI125X: 862 /* 863 * Disable zoom video. Some machines initialize this 864 * improperly and experience has shown that this helps 865 * prevent strange behavior. 866 */ 867 pci_conf_write(pc, tag, PCI12XX_MMCTRL, 0); 868 869 sysctrl = pci_conf_read(pc, tag, PCI_SYSCTRL); 870 sysctrl |= PCI12XX_SYSCTRL_VCCPROT; 871 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 872 cbctl = pci_conf_read(pc, tag, PCI_CBCTRL); 873 cbctl |= PCI12XX_CBCTRL_CSC; 874 pci_conf_write(pc, tag, PCI_CBCTRL, cbctl); 875 break; 876 877 case CB_TOPIC95B: 878 sockctl = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 879 sockctl |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 880 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, sockctl); 881 slotctl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 882 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 883 device_xname(sc->sc_dev), slotctl)); 884 slotctl |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 885 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 886 slotctl &= ~TOPIC_SLOT_CTRL_SWDETECT; 887 DPRINTF(("0x%x\n", slotctl)); 888 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slotctl); 889 break; 890 891 case CB_TOPIC97: 892 slotctl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 893 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 894 device_xname(sc->sc_dev), slotctl)); 895 slotctl |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 896 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 897 slotctl &= ~TOPIC_SLOT_CTRL_SWDETECT; 898 slotctl |= TOPIC97_SLOT_CTRL_PCIINT; 899 slotctl &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 900 DPRINTF(("0x%x\n", slotctl)); 901 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slotctl); 902 /* make sure to assert LV card support bits */ 903 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 904 0x800 + 0x3e, 905 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 906 0x800 + 0x3e) | 0x03); 907 break; 908 } 909 910 /* Close all memory and I/O windows. */ 911 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 912 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 913 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 914 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 915 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 916 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 917 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 918 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 919 920 /* reset 16-bit pcmcia bus */ 921 bus_space_write_1(bmt, bmh, 0x800 + PCIC_INTR, 922 bus_space_read_1(bmt, bmh, 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 923 924 /* turn off power */ 925 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 926 } 927 928 static void 929 pccbb_intrinit(struct pccbb_softc *sc) 930 { 931 pcireg_t sockmask; 932 const char *intrstr = NULL; 933 pci_intr_handle_t ih; 934 pci_chipset_tag_t pc = sc->sc_pc; 935 bus_space_tag_t bmt = sc->sc_base_memt; 936 bus_space_handle_t bmh = sc->sc_base_memh; 937 938 /* Map and establish the interrupt. */ 939 if (pci_intr_map(&sc->sc_pa, &ih)) { 940 aprint_error_dev(sc->sc_dev, "couldn't map interrupt\n"); 941 return; 942 } 943 intrstr = pci_intr_string(pc, ih); 944 945 /* 946 * XXX pccbbintr should be called under the priority lower 947 * than any other hard interupts. 948 */ 949 KASSERT(sc->sc_ih == NULL); 950 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 951 952 if (sc->sc_ih == NULL) { 953 aprint_error_dev(sc->sc_dev, "couldn't establish interrupt"); 954 if (intrstr != NULL) 955 aprint_error(" at %s\n", intrstr); 956 else 957 aprint_error("\n"); 958 return; 959 } 960 961 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 962 963 /* CSC Interrupt: Card detect and power cycle interrupts on */ 964 sockmask = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 965 sockmask |= CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | 966 CB_SOCKET_MASK_POWER; 967 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, sockmask); 968 /* reset interrupt */ 969 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 970 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 971 } 972 973 /* 974 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 975 * struct pcmciabus_attach_args *paa) 976 * 977 * This function attaches 16-bit PCcard bus. 978 */ 979 STATIC void 980 pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 981 struct pcmciabus_attach_args *paa) 982 { 983 #if rbus 984 rbus_tag_t rb; 985 #endif 986 /* 987 * We need to do a few things here: 988 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 989 * setting the IRQ numbers to 0. 990 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 991 * routing of CSC interrupts (e.g. card removal) to PCI while in 992 * PCMCIA mode. We just leave this set all the time. 993 * 3) Enable card insertion/removal interrupts in case the chip also 994 * needs that while in PCMCIA mode. 995 * 4) Clear any pending CSC interrupt. 996 */ 997 Pcic_write(sc, PCIC_INTR, PCIC_INTR_ENABLE); 998 if (sc->sc_chipset == CB_TI113X) { 999 Pcic_write(sc, PCIC_CSC_INTR, 0); 1000 } else { 1001 Pcic_write(sc, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 1002 Pcic_read(sc, PCIC_CSC); 1003 } 1004 1005 /* initialize pcmcia bus attachment */ 1006 paa->paa_busname = "pcmcia"; 1007 paa->pct = &pccbb_pcmcia_funcs; 1008 paa->pch = sc; 1009 paa->iobase = 0; /* I don't use them */ 1010 paa->iosize = 0; 1011 #if rbus 1012 rb = sc->sc_rbus_iot; 1013 paa->iobase = rb->rb_start + rb->rb_offset; 1014 paa->iosize = rb->rb_end - rb->rb_start; 1015 #endif 1016 1017 return; 1018 } 1019 1020 /* 1021 * int pccbbintr(arg) 1022 * void *arg; 1023 * This routine handles the interrupt from Yenta PCI-CardBus bridge 1024 * itself. 1025 */ 1026 int 1027 pccbbintr(void *arg) 1028 { 1029 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1030 u_int32_t sockevent, sockstate; 1031 bus_space_tag_t memt = sc->sc_base_memt; 1032 bus_space_handle_t memh = sc->sc_base_memh; 1033 1034 if (!device_has_power(sc->sc_dev)) 1035 return 0; 1036 1037 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 1038 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 1039 Pcic_read(sc, PCIC_CSC); 1040 1041 if (sockevent != 0) { 1042 aprint_debug("%s: enter sockevent %" PRIx32 "\n", __func__, 1043 sockevent); 1044 } 1045 1046 /* Sometimes a change of CSTSCHG# accompanies the first 1047 * interrupt from an Atheros WLAN. That generates a 1048 * CB_SOCKET_EVENT_CSTS event on the bridge. The event 1049 * isn't interesting to pccbb(4), so we used to ignore the 1050 * interrupt. Now, let the child devices try to handle 1051 * the interrupt, instead. The Atheros NIC produces 1052 * interrupts more reliably, now: used to be that it would 1053 * only interrupt if the driver avoided powering down the 1054 * NIC's cardslot, and then the NIC would only work after 1055 * it was reset a second time. 1056 */ 1057 if (sockevent == 0 || 1058 (sockevent & ~(CB_SOCKET_EVENT_POWER|CB_SOCKET_EVENT_CD)) != 0) { 1059 /* This intr is not for me: it may be for my child devices. */ 1060 if (sc->sc_pil_intr_enable) { 1061 return pccbbintr_function(sc); 1062 } else { 1063 return 0; 1064 } 1065 } 1066 1067 if (sockevent & CB_SOCKET_EVENT_CD) { 1068 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1069 if (0x00 != (sockstate & CB_SOCKET_STAT_CD)) { 1070 /* A card should be removed. */ 1071 if (sc->sc_flags & CBB_CARDEXIST) { 1072 DPRINTF(("%s: 0x%08x", 1073 device_xname(sc->sc_dev), sockevent)); 1074 DPRINTF((" card removed, 0x%08x\n", sockstate)); 1075 sc->sc_flags &= ~CBB_CARDEXIST; 1076 if (sc->sc_csc->sc_status & 1077 CARDSLOT_STATUS_CARD_16) { 1078 cardslot_event_throw(sc->sc_csc, 1079 CARDSLOT_EVENT_REMOVAL_16); 1080 } else if (sc->sc_csc->sc_status & 1081 CARDSLOT_STATUS_CARD_CB) { 1082 /* Cardbus intr removed */ 1083 cardslot_event_throw(sc->sc_csc, 1084 CARDSLOT_EVENT_REMOVAL_CB); 1085 } 1086 } else if (sc->sc_flags & CBB_INSERTING) { 1087 sc->sc_flags &= ~CBB_INSERTING; 1088 callout_stop(&sc->sc_insert_ch); 1089 } 1090 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 1091 /* 1092 * The pccbbintr may called from powerdown hook when 1093 * the system resumed, to detect the card 1094 * insertion/removal during suspension. 1095 */ 1096 (sc->sc_flags & CBB_CARDEXIST) == 0) { 1097 if (sc->sc_flags & CBB_INSERTING) { 1098 callout_stop(&sc->sc_insert_ch); 1099 } 1100 callout_schedule(&sc->sc_insert_ch, hz / 5); 1101 sc->sc_flags |= CBB_INSERTING; 1102 } 1103 } 1104 1105 /* XXX sockevent == 9 does occur in the wild. handle it. */ 1106 if (sockevent & CB_SOCKET_EVENT_POWER) { 1107 DPRINTF(("Powercycling because of socket event\n")); 1108 /* XXX: Does not happen when attaching a 16-bit card */ 1109 sc->sc_pwrcycle++; 1110 wakeup(&sc->sc_pwrcycle); 1111 } 1112 1113 return (1); 1114 } 1115 1116 /* 1117 * static int pccbbintr_function(struct pccbb_softc *sc) 1118 * 1119 * This function calls each interrupt handler registered at the 1120 * bridge. The interrupt handlers are called in registered order. 1121 */ 1122 static int 1123 pccbbintr_function(struct pccbb_softc *sc) 1124 { 1125 int retval = 0, val; 1126 struct pccbb_intrhand_list *pil; 1127 int s; 1128 1129 LIST_FOREACH(pil, &sc->sc_pil, pil_next) { 1130 s = splraiseipl(pil->pil_icookie); 1131 val = (*pil->pil_func)(pil->pil_arg); 1132 splx(s); 1133 1134 retval = retval == 1 ? 1 : 1135 retval == 0 ? val : val != 0 ? val : retval; 1136 } 1137 1138 return retval; 1139 } 1140 1141 static void 1142 pci113x_insert(void *arg) 1143 { 1144 struct pccbb_softc *sc = arg; 1145 u_int32_t sockevent, sockstate; 1146 1147 if (!(sc->sc_flags & CBB_INSERTING)) { 1148 /* We add a card only under inserting state. */ 1149 return; 1150 } 1151 sc->sc_flags &= ~CBB_INSERTING; 1152 1153 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1154 CB_SOCKET_EVENT); 1155 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1156 CB_SOCKET_STAT); 1157 1158 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1159 DPRINTF(("%s: 0x%08x", device_xname(sc->sc_dev), sockevent)); 1160 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1161 sc->sc_flags |= CBB_CARDEXIST; 1162 /* call pccard interrupt handler here */ 1163 if (sockstate & CB_SOCKET_STAT_16BIT) { 1164 /* 16-bit card found */ 1165 cardslot_event_throw(sc->sc_csc, 1166 CARDSLOT_EVENT_INSERTION_16); 1167 } else if (sockstate & CB_SOCKET_STAT_CB) { 1168 /* cardbus card found */ 1169 cardslot_event_throw(sc->sc_csc, 1170 CARDSLOT_EVENT_INSERTION_CB); 1171 } else { 1172 /* who are you? */ 1173 } 1174 } else { 1175 callout_schedule(&sc->sc_insert_ch, hz / 10); 1176 } 1177 } 1178 1179 #define PCCBB_PCMCIA_OFFSET 0x800 1180 static u_int8_t 1181 pccbb_pcmcia_read(struct pccbb_softc *sc, int reg) 1182 { 1183 bus_space_barrier(sc->sc_base_memt, sc->sc_base_memh, 1184 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1185 1186 return bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 1187 PCCBB_PCMCIA_OFFSET + reg); 1188 } 1189 1190 static void 1191 pccbb_pcmcia_write(struct pccbb_softc *sc, int reg, u_int8_t val) 1192 { 1193 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 1194 PCCBB_PCMCIA_OFFSET + reg, val); 1195 1196 bus_space_barrier(sc->sc_base_memt, sc->sc_base_memh, 1197 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1198 } 1199 1200 /* 1201 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1202 */ 1203 STATIC int 1204 pccbb_ctrl(cardbus_chipset_tag_t ct, int command) 1205 { 1206 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1207 1208 switch (command) { 1209 case CARDBUS_CD: 1210 if (2 == pccbb_detect_card(sc)) { 1211 int retval = 0; 1212 int status = cb_detect_voltage(sc); 1213 if (PCCARD_VCC_5V & status) { 1214 retval |= CARDBUS_5V_CARD; 1215 } 1216 if (PCCARD_VCC_3V & status) { 1217 retval |= CARDBUS_3V_CARD; 1218 } 1219 if (PCCARD_VCC_XV & status) { 1220 retval |= CARDBUS_XV_CARD; 1221 } 1222 if (PCCARD_VCC_YV & status) { 1223 retval |= CARDBUS_YV_CARD; 1224 } 1225 return retval; 1226 } else { 1227 return 0; 1228 } 1229 case CARDBUS_RESET: 1230 return cb_reset(sc); 1231 case CARDBUS_IO_ENABLE: /* fallthrough */ 1232 case CARDBUS_IO_DISABLE: /* fallthrough */ 1233 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1234 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1235 case CARDBUS_BM_ENABLE: /* fallthrough */ 1236 case CARDBUS_BM_DISABLE: /* fallthrough */ 1237 /* XXX: I think we don't need to call this function below. */ 1238 return pccbb_cardenable(sc, command); 1239 } 1240 1241 return 0; 1242 } 1243 1244 STATIC int 1245 pccbb_power_ct(cardbus_chipset_tag_t ct, int command) 1246 { 1247 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1248 1249 return pccbb_power(sc, command); 1250 } 1251 1252 /* 1253 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1254 * This function returns true when it succeeds and returns false when 1255 * it fails. 1256 */ 1257 STATIC int 1258 pccbb_power(struct pccbb_softc *sc, int command) 1259 { 1260 u_int32_t status, osock_ctrl, sock_ctrl, reg_ctrl; 1261 bus_space_tag_t memt = sc->sc_base_memt; 1262 bus_space_handle_t memh = sc->sc_base_memh; 1263 int on = 0, pwrcycle, s, times; 1264 struct timeval before, after, diff; 1265 1266 DPRINTF(("pccbb_power: %s and %s [0x%x]\n", 1267 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1268 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1269 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1270 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1271 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1272 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1273 "UNKNOWN", 1274 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1275 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1276 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1277 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1278 "UNKNOWN", command)); 1279 1280 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1281 osock_ctrl = sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1282 1283 switch (command & CARDBUS_VCCMASK) { 1284 case CARDBUS_VCC_UC: 1285 break; 1286 case CARDBUS_VCC_5V: 1287 on++; 1288 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1289 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1290 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1291 } else { 1292 aprint_error_dev(sc->sc_dev, 1293 "BAD voltage request: no 5 V card\n"); 1294 return 0; 1295 } 1296 break; 1297 case CARDBUS_VCC_3V: 1298 on++; 1299 if (CB_SOCKET_STAT_3VCARD & status) { 1300 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1301 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1302 } else { 1303 aprint_error_dev(sc->sc_dev, 1304 "BAD voltage request: no 3.3 V card\n"); 1305 return 0; 1306 } 1307 break; 1308 case CARDBUS_VCC_0V: 1309 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1310 break; 1311 default: 1312 return 0; /* power NEVER changed */ 1313 } 1314 1315 switch (command & CARDBUS_VPPMASK) { 1316 case CARDBUS_VPP_UC: 1317 break; 1318 case CARDBUS_VPP_0V: 1319 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1320 break; 1321 case CARDBUS_VPP_VCC: 1322 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1323 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1324 break; 1325 case CARDBUS_VPP_12V: 1326 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1327 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1328 break; 1329 } 1330 1331 pwrcycle = sc->sc_pwrcycle; 1332 aprint_debug_dev(sc->sc_dev, "osock_ctrl %#" PRIx32 1333 " sock_ctrl %#" PRIx32 "\n", osock_ctrl, sock_ctrl); 1334 1335 microtime(&before); 1336 s = splbio(); 1337 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1338 1339 /* 1340 * Wait as long as 200ms for a power-cycle interrupt. If 1341 * interrupts are enabled, but the socket has already 1342 * changed to the desired status, keep waiting for the 1343 * interrupt. "Consuming" the interrupt in this way keeps 1344 * the interrupt from prematurely waking some subsequent 1345 * pccbb_power call. 1346 * 1347 * XXX Not every bridge interrupts on the ->OFF transition. 1348 * XXX That's ok, we will time-out after 200ms. 1349 * 1350 * XXX The power cycle event will never happen when attaching 1351 * XXX a 16-bit card. That's ok, we will time-out after 1352 * XXX 200ms. 1353 */ 1354 for (times = 5; --times >= 0; ) { 1355 if (cold) 1356 DELAY(40 * 1000); 1357 else { 1358 (void)tsleep(&sc->sc_pwrcycle, PWAIT, "pccpwr", 1359 hz / 25); 1360 if (pwrcycle == sc->sc_pwrcycle) 1361 continue; 1362 } 1363 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1364 if ((status & CB_SOCKET_STAT_PWRCYCLE) != 0 && on) 1365 break; 1366 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0 && !on) 1367 break; 1368 } 1369 splx(s); 1370 microtime(&after); 1371 timersub(&after, &before, &diff); 1372 aprint_debug_dev(sc->sc_dev, "wait took%s %ld.%06lds\n", 1373 (on && times < 0) ? " too long" : "", diff.tv_sec, diff.tv_usec); 1374 1375 /* 1376 * Ok, wait a bit longer for things to settle. 1377 */ 1378 if (on && sc->sc_chipset == CB_TOPIC95B) 1379 delay_ms(100, sc); 1380 1381 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1382 1383 if (on && sc->sc_chipset != CB_TOPIC95B) { 1384 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0) 1385 aprint_error_dev(sc->sc_dev, "power on failed?\n"); 1386 } 1387 1388 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1389 aprint_error_dev(sc->sc_dev, 1390 "bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1391 sock_ctrl, status); 1392 aprint_error_dev(sc->sc_dev, "disabling socket\n"); 1393 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1394 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1395 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1396 status &= ~CB_SOCKET_STAT_BADVCC; 1397 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, status); 1398 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1399 CB_SOCKET_STAT)); 1400 return 0; 1401 } 1402 1403 if (sc->sc_chipset == CB_TOPIC97) { 1404 reg_ctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL); 1405 reg_ctrl &= ~TOPIC97_REG_CTRL_TESTMODE; 1406 if ((command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V) 1407 reg_ctrl &= ~TOPIC97_REG_CTRL_CLKRUN_ENA; 1408 else 1409 reg_ctrl |= TOPIC97_REG_CTRL_CLKRUN_ENA; 1410 pci_conf_write(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL, reg_ctrl); 1411 } 1412 1413 return 1; /* power changed correctly */ 1414 } 1415 1416 /* 1417 * static int pccbb_detect_card(struct pccbb_softc *sc) 1418 * return value: 0 if no card exists. 1419 * 1 if 16-bit card exists. 1420 * 2 if cardbus card exists. 1421 */ 1422 static int 1423 pccbb_detect_card(struct pccbb_softc *sc) 1424 { 1425 bus_space_handle_t base_memh = sc->sc_base_memh; 1426 bus_space_tag_t base_memt = sc->sc_base_memt; 1427 u_int32_t sockstat = 1428 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1429 int retval = 0; 1430 1431 /* CD1 and CD2 asserted */ 1432 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1433 /* card must be present */ 1434 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1435 /* NOTACARD DEASSERTED */ 1436 if (CB_SOCKET_STAT_CB & sockstat) { 1437 /* CardBus mode */ 1438 retval = 2; 1439 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1440 /* 16-bit mode */ 1441 retval = 1; 1442 } 1443 } 1444 } 1445 return retval; 1446 } 1447 1448 /* 1449 * STATIC int cb_reset(struct pccbb_softc *sc) 1450 * This function resets CardBus card. 1451 */ 1452 STATIC int 1453 cb_reset(struct pccbb_softc *sc) 1454 { 1455 /* 1456 * Reset Assert at least 20 ms 1457 * Some machines request longer duration. 1458 */ 1459 int reset_duration = 1460 (sc->sc_chipset == CB_RX5C47X ? 400 : 50); 1461 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1462 aprint_debug("%s: enter bcr %" PRIx32 "\n", __func__, bcr); 1463 1464 /* Reset bit Assert (bit 6 at 0x3E) */ 1465 bcr |= PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT; 1466 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr); 1467 aprint_debug("%s: wrote bcr %" PRIx32 "\n", __func__, bcr); 1468 delay_ms(reset_duration, sc); 1469 1470 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1471 /* Reset bit Deassert (bit 6 at 0x3E) */ 1472 bcr &= ~(PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT); 1473 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, 1474 bcr); 1475 aprint_debug("%s: wrote bcr %" PRIx32 "\n", __func__, bcr); 1476 delay_ms(reset_duration, sc); 1477 aprint_debug("%s: end of delay\n", __func__); 1478 } 1479 /* No card found on the slot. Keep Reset. */ 1480 return 1; 1481 } 1482 1483 /* 1484 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1485 * This function detect card Voltage. 1486 */ 1487 STATIC int 1488 cb_detect_voltage(struct pccbb_softc *sc) 1489 { 1490 u_int32_t psr; /* socket present-state reg */ 1491 bus_space_tag_t iot = sc->sc_base_memt; 1492 bus_space_handle_t ioh = sc->sc_base_memh; 1493 int vol = PCCARD_VCC_UKN; /* set 0 */ 1494 1495 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1496 1497 if (0x400u & psr) { 1498 vol |= PCCARD_VCC_5V; 1499 } 1500 if (0x800u & psr) { 1501 vol |= PCCARD_VCC_3V; 1502 } 1503 1504 return vol; 1505 } 1506 1507 STATIC int 1508 cbbprint(void *aux, const char *pcic) 1509 { 1510 #if 0 1511 struct cbslot_attach_args *cba = aux; 1512 1513 if (cba->cba_slot >= 0) { 1514 aprint_normal(" slot %d", cba->cba_slot); 1515 } 1516 #endif 1517 return UNCONF; 1518 } 1519 1520 /* 1521 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1522 * This function enables and disables the card 1523 */ 1524 STATIC int 1525 pccbb_cardenable(struct pccbb_softc *sc, int function) 1526 { 1527 u_int32_t command = 1528 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1529 1530 DPRINTF(("pccbb_cardenable:")); 1531 switch (function) { 1532 case CARDBUS_IO_ENABLE: 1533 command |= PCI_COMMAND_IO_ENABLE; 1534 break; 1535 case CARDBUS_IO_DISABLE: 1536 command &= ~PCI_COMMAND_IO_ENABLE; 1537 break; 1538 case CARDBUS_MEM_ENABLE: 1539 command |= PCI_COMMAND_MEM_ENABLE; 1540 break; 1541 case CARDBUS_MEM_DISABLE: 1542 command &= ~PCI_COMMAND_MEM_ENABLE; 1543 break; 1544 case CARDBUS_BM_ENABLE: 1545 command |= PCI_COMMAND_MASTER_ENABLE; 1546 break; 1547 case CARDBUS_BM_DISABLE: 1548 command &= ~PCI_COMMAND_MASTER_ENABLE; 1549 break; 1550 default: 1551 return 0; 1552 } 1553 1554 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1555 DPRINTF((" command reg 0x%x\n", command)); 1556 return 1; 1557 } 1558 1559 #if !rbus 1560 static int 1561 pccbb_io_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 1562 { 1563 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1564 int basereg; 1565 int limitreg; 1566 1567 if ((win < 0) || (win > 2)) { 1568 #if defined DIAGNOSTIC 1569 printf("cardbus_io_open: window out of range %d\n", win); 1570 #endif 1571 return 0; 1572 } 1573 1574 basereg = win * 8 + PCI_CB_IOBASE0; 1575 limitreg = win * 8 + PCI_CB_IOLIMIT0; 1576 1577 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1578 start, basereg, end, limitreg)); 1579 1580 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1581 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1582 return 1; 1583 } 1584 1585 /* 1586 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1587 */ 1588 static int 1589 pccbb_io_close(cardbus_chipset_tag_t ct, int win) 1590 { 1591 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1592 int basereg; 1593 int limitreg; 1594 1595 if ((win < 0) || (win > 2)) { 1596 #if defined DIAGNOSTIC 1597 printf("cardbus_io_close: window out of range %d\n", win); 1598 #endif 1599 return 0; 1600 } 1601 1602 basereg = win * 8 + PCI_CB_IOBASE0; 1603 limitreg = win * 8 + PCI_CB_IOLIMIT0; 1604 1605 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1606 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1607 return 1; 1608 } 1609 1610 static int 1611 pccbb_mem_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 1612 { 1613 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1614 int basereg; 1615 int limitreg; 1616 1617 if ((win < 0) || (win > 2)) { 1618 #if defined DIAGNOSTIC 1619 printf("cardbus_mem_open: window out of range %d\n", win); 1620 #endif 1621 return 0; 1622 } 1623 1624 basereg = win * 8 + PCI_CB_MEMBASE0; 1625 limitreg = win * 8 + PCI_CB_MEMLIMIT0; 1626 1627 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1628 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1629 return 1; 1630 } 1631 1632 static int 1633 pccbb_mem_close(cardbus_chipset_tag_t ct, int win) 1634 { 1635 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1636 int basereg; 1637 int limitreg; 1638 1639 if ((win < 0) || (win > 2)) { 1640 #if defined DIAGNOSTIC 1641 printf("cardbus_mem_close: window out of range %d\n", win); 1642 #endif 1643 return 0; 1644 } 1645 1646 basereg = win * 8 + PCI_CB_MEMBASE0; 1647 limitreg = win * 8 + PCI_CB_MEMLIMIT0; 1648 1649 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1650 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1651 return 1; 1652 } 1653 #endif 1654 1655 /* 1656 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1657 * int irq, 1658 * int level, 1659 * int (* func)(void *), 1660 * void *arg) 1661 * 1662 * This function registers an interrupt handler at the bridge, in 1663 * order not to call the interrupt handlers of child devices when 1664 * a card-deletion interrupt occurs. 1665 * 1666 * The arguments irq and level are not used. 1667 */ 1668 static void * 1669 pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, cardbus_intr_line_t irq, 1670 int level, int (*func)(void *), void *arg) 1671 { 1672 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1673 1674 return pccbb_intr_establish(sc, irq, level, func, arg); 1675 } 1676 1677 1678 /* 1679 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1680 * void *ih) 1681 * 1682 * This function removes an interrupt handler pointed by ih. 1683 */ 1684 static void 1685 pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih) 1686 { 1687 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1688 1689 pccbb_intr_disestablish(sc, ih); 1690 } 1691 1692 1693 void 1694 pccbb_intr_route(struct pccbb_softc *sc) 1695 { 1696 pcireg_t bcr, cbctrl; 1697 1698 /* initialize bridge intr routing */ 1699 bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1700 bcr &= ~CB_BCR_INTR_IREQ_ENABLE; 1701 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr); 1702 1703 switch (sc->sc_chipset) { 1704 case CB_TI113X: 1705 cbctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1706 /* functional intr enabled */ 1707 cbctrl |= PCI113X_CBCTRL_PCI_INTR; 1708 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, cbctrl); 1709 break; 1710 default: 1711 break; 1712 } 1713 } 1714 1715 /* 1716 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1717 * int irq, 1718 * int level, 1719 * int (* func)(void *), 1720 * void *arg) 1721 * 1722 * This function registers an interrupt handler at the bridge, in 1723 * order not to call the interrupt handlers of child devices when 1724 * a card-deletion interrupt occurs. 1725 * 1726 * The arguments irq is not used because pccbb selects intr vector. 1727 */ 1728 static void * 1729 pccbb_intr_establish(struct pccbb_softc *sc, cardbus_intr_line_t irq, 1730 int level, int (*func)(void *), void *arg) 1731 { 1732 struct pccbb_intrhand_list *pil, *newpil; 1733 1734 DPRINTF(("pccbb_intr_establish start. %p\n", LIST_FIRST(&sc->sc_pil))); 1735 1736 if (LIST_EMPTY(&sc->sc_pil)) { 1737 pccbb_intr_route(sc); 1738 } 1739 1740 /* 1741 * Allocate a room for interrupt handler structure. 1742 */ 1743 if (NULL == (newpil = 1744 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1745 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1746 return NULL; 1747 } 1748 1749 newpil->pil_func = func; 1750 newpil->pil_arg = arg; 1751 newpil->pil_icookie = makeiplcookie(level); 1752 1753 if (LIST_EMPTY(&sc->sc_pil)) { 1754 LIST_INSERT_HEAD(&sc->sc_pil, newpil, pil_next); 1755 } else { 1756 for (pil = LIST_FIRST(&sc->sc_pil); 1757 LIST_NEXT(pil, pil_next) != NULL; 1758 pil = LIST_NEXT(pil, pil_next)); 1759 LIST_INSERT_AFTER(pil, newpil, pil_next); 1760 } 1761 1762 DPRINTF(("pccbb_intr_establish add pil. %p\n", 1763 LIST_FIRST(&sc->sc_pil))); 1764 1765 return newpil; 1766 } 1767 1768 /* 1769 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1770 * void *ih) 1771 * 1772 * This function removes an interrupt handler pointed by ih. ih 1773 * should be the value returned by cardbus_intr_establish() or 1774 * NULL. 1775 * 1776 * When ih is NULL, this function will do nothing. 1777 */ 1778 static void 1779 pccbb_intr_disestablish(struct pccbb_softc *sc, void *ih) 1780 { 1781 struct pccbb_intrhand_list *pil; 1782 pcireg_t reg; 1783 1784 DPRINTF(("pccbb_intr_disestablish start. %p\n", 1785 LIST_FIRST(&sc->sc_pil))); 1786 1787 if (ih == NULL) { 1788 /* intr handler is not set */ 1789 DPRINTF(("pccbb_intr_disestablish: no ih\n")); 1790 return; 1791 } 1792 1793 #ifdef DIAGNOSTIC 1794 LIST_FOREACH(pil, &sc->sc_pil, pil_next) { 1795 DPRINTF(("pccbb_intr_disestablish: pil %p\n", pil)); 1796 if (pil == ih) { 1797 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1798 break; 1799 } 1800 } 1801 if (pil == NULL) { 1802 panic("pccbb_intr_disestablish: %s cannot find pil %p", 1803 device_xname(sc->sc_dev), ih); 1804 } 1805 #endif 1806 1807 pil = (struct pccbb_intrhand_list *)ih; 1808 LIST_REMOVE(pil, pil_next); 1809 free(pil, M_DEVBUF); 1810 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1811 1812 if (LIST_EMPTY(&sc->sc_pil)) { 1813 /* No interrupt handlers */ 1814 1815 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1816 1817 /* stop routing PCI intr */ 1818 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1819 reg |= CB_BCR_INTR_IREQ_ENABLE; 1820 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, reg); 1821 1822 switch (sc->sc_chipset) { 1823 case CB_TI113X: 1824 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1825 /* functional intr disabled */ 1826 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1827 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1828 break; 1829 default: 1830 break; 1831 } 1832 } 1833 } 1834 1835 #if defined SHOW_REGS 1836 static void 1837 cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, bus_space_tag_t memt, 1838 bus_space_handle_t memh) 1839 { 1840 int i; 1841 printf("PCI config regs:"); 1842 for (i = 0; i < 0x50; i += 4) { 1843 if (i % 16 == 0) 1844 printf("\n 0x%02x:", i); 1845 printf(" %08x", pci_conf_read(pc, tag, i)); 1846 } 1847 for (i = 0x80; i < 0xb0; i += 4) { 1848 if (i % 16 == 0) 1849 printf("\n 0x%02x:", i); 1850 printf(" %08x", pci_conf_read(pc, tag, i)); 1851 } 1852 1853 if (memh == 0) { 1854 printf("\n"); 1855 return; 1856 } 1857 1858 printf("\nsocket regs:"); 1859 for (i = 0; i <= 0x10; i += 0x04) 1860 printf(" %08x", bus_space_read_4(memt, memh, i)); 1861 printf("\nExCA regs:"); 1862 for (i = 0; i < 0x08; ++i) 1863 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1864 printf("\n"); 1865 return; 1866 } 1867 #endif 1868 1869 /* 1870 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1871 * int busno, int function) 1872 * This is the function to make a tag to access config space of 1873 * a CardBus Card. It works same as pci_conf_read. 1874 */ 1875 static cardbustag_t 1876 pccbb_make_tag(cardbus_chipset_tag_t cc, int busno, int function) 1877 { 1878 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1879 1880 return pci_make_tag(sc->sc_pc, busno, 0, function); 1881 } 1882 1883 static void 1884 pccbb_free_tag(cardbus_chipset_tag_t cc, cardbustag_t tag) 1885 { 1886 } 1887 1888 /* 1889 * pccbb_conf_read 1890 * 1891 * This is the function to read the config space of a CardBus card. 1892 * It works the same as pci_conf_read(9). 1893 */ 1894 static cardbusreg_t 1895 pccbb_conf_read(cardbus_chipset_tag_t cc, cardbustag_t tag, int offset) 1896 { 1897 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1898 pcitag_t brtag = sc->sc_tag; 1899 cardbusreg_t reg; 1900 1901 /* 1902 * clear cardbus master abort status; it is OK to write without 1903 * reading before because all bits are r/o or w1tc 1904 */ 1905 pci_conf_write(sc->sc_pc, brtag, PCI_CBB_SECSTATUS, 1906 CBB_SECSTATUS_CBMABORT); 1907 reg = pci_conf_read(sc->sc_pc, tag, offset); 1908 /* check cardbus master abort status */ 1909 if (pci_conf_read(sc->sc_pc, brtag, PCI_CBB_SECSTATUS) 1910 & CBB_SECSTATUS_CBMABORT) 1911 return (0xffffffff); 1912 return reg; 1913 } 1914 1915 /* 1916 * pccbb_conf_write 1917 * 1918 * This is the function to write the config space of a CardBus 1919 * card. It works the same as pci_conf_write(9). 1920 */ 1921 static void 1922 pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, int reg, 1923 cardbusreg_t val) 1924 { 1925 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1926 1927 pci_conf_write(sc->sc_pc, tag, reg, val); 1928 } 1929 1930 #if 0 1931 STATIC int 1932 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1933 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 1934 int speed, int flags, 1935 bus_space_handle_t * iohp) 1936 #endif 1937 /* 1938 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1939 * bus_addr_t start, bus_size_t size, 1940 * bus_size_t align, 1941 * struct pcmcia_io_handle *pcihp 1942 * 1943 * This function only allocates I/O region for pccard. This function 1944 * never maps the allocated region to pccard I/O area. 1945 * 1946 * XXX: The interface of this function is not very good, I believe. 1947 */ 1948 STATIC int 1949 pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, 1950 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 1951 { 1952 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 1953 bus_addr_t ioaddr; 1954 int flags = 0; 1955 bus_space_tag_t iot; 1956 bus_space_handle_t ioh; 1957 bus_addr_t mask; 1958 #if rbus 1959 rbus_tag_t rb; 1960 #endif 1961 if (align == 0) { 1962 align = size; /* XXX: funny??? */ 1963 } 1964 1965 if (start != 0) { 1966 /* XXX: assume all card decode lower 10 bits by its hardware */ 1967 mask = 0x3ff; 1968 /* enforce to use only masked address */ 1969 start &= mask; 1970 } else { 1971 /* 1972 * calculate mask: 1973 * 1. get the most significant bit of size (call it msb). 1974 * 2. compare msb with the value of size. 1975 * 3. if size is larger, shift msb left once. 1976 * 4. obtain mask value to decrement msb. 1977 */ 1978 bus_size_t size_tmp = size; 1979 int shifts = 0; 1980 1981 mask = 1; 1982 while (size_tmp) { 1983 ++shifts; 1984 size_tmp >>= 1; 1985 } 1986 mask = (1 << shifts); 1987 if (mask < size) { 1988 mask <<= 1; 1989 } 1990 --mask; 1991 } 1992 1993 /* 1994 * Allocate some arbitrary I/O space. 1995 */ 1996 1997 iot = sc->sc_iot; 1998 1999 #if rbus 2000 rb = sc->sc_rbus_iot; 2001 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 2002 return 1; 2003 } 2004 DPRINTF(("pccbb_pcmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2005 (u_long) ioaddr, (u_long) size)); 2006 #else 2007 if (start) { 2008 ioaddr = start; 2009 if (bus_space_map(iot, start, size, 0, &ioh)) { 2010 return 1; 2011 } 2012 DPRINTF(("pccbb_pcmcia_io_alloc map port 0x%lx+0x%lx\n", 2013 (u_long) ioaddr, (u_long) size)); 2014 } else { 2015 flags |= PCMCIA_IO_ALLOCATED; 2016 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 2017 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 2018 size, align, 0, 0, &ioaddr, &ioh)) { 2019 /* No room be able to be get. */ 2020 return 1; 2021 } 2022 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2023 (u_long) ioaddr, (u_long) size)); 2024 } 2025 #endif 2026 2027 pcihp->iot = iot; 2028 pcihp->ioh = ioh; 2029 pcihp->addr = ioaddr; 2030 pcihp->size = size; 2031 pcihp->flags = flags; 2032 2033 return 0; 2034 } 2035 2036 /* 2037 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2038 * struct pcmcia_io_handle *pcihp) 2039 * 2040 * This function only frees I/O region for pccard. 2041 * 2042 * XXX: The interface of this function is not very good, I believe. 2043 */ 2044 void 2045 pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2046 struct pcmcia_io_handle *pcihp) 2047 { 2048 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2049 #if !rbus 2050 bus_space_tag_t iot = pcihp->iot; 2051 #endif 2052 bus_space_handle_t ioh = pcihp->ioh; 2053 bus_size_t size = pcihp->size; 2054 2055 #if rbus 2056 rbus_tag_t rb = sc->sc_rbus_iot; 2057 2058 rbus_space_free(rb, ioh, size, NULL); 2059 #else 2060 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 2061 bus_space_free(iot, ioh, size); 2062 else 2063 bus_space_unmap(iot, ioh, size); 2064 #endif 2065 } 2066 2067 /* 2068 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 2069 * bus_addr_t offset, bus_size_t size, 2070 * struct pcmcia_io_handle *pcihp, 2071 * int *windowp) 2072 * 2073 * This function maps the allocated I/O region to pccard. This function 2074 * never allocates any I/O region for pccard I/O area. I don't 2075 * understand why the original authors of pcmciabus separated alloc and 2076 * map. I believe the two must be unite. 2077 * 2078 * XXX: no wait timing control? 2079 */ 2080 int 2081 pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, bus_addr_t offset, 2082 bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp) 2083 { 2084 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2085 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2086 bus_addr_t ioaddr = pcihp->addr + offset; 2087 int i, win; 2088 #if defined CBB_DEBUG 2089 static const char *width_names[] = { "dynamic", "io8", "io16" }; 2090 #endif 2091 2092 /* Sanity check I/O handle. */ 2093 2094 if (sc->sc_iot != pcihp->iot) { 2095 panic("pccbb_pcmcia_io_map iot is bogus"); 2096 } 2097 2098 /* XXX Sanity check offset/size. */ 2099 2100 win = -1; 2101 for (i = 0; i < PCIC_IO_WINS; i++) { 2102 if ((ph->ioalloc & (1 << i)) == 0) { 2103 win = i; 2104 ph->ioalloc |= (1 << i); 2105 break; 2106 } 2107 } 2108 2109 if (win == -1) { 2110 return 1; 2111 } 2112 2113 *windowp = win; 2114 2115 /* XXX this is pretty gross */ 2116 2117 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2118 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2119 2120 /* XXX wtf is this doing here? */ 2121 2122 #if 0 2123 printf(" port 0x%lx", (u_long) ioaddr); 2124 if (size > 1) { 2125 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2126 } 2127 #endif 2128 2129 ph->io[win].addr = ioaddr; 2130 ph->io[win].size = size; 2131 ph->io[win].width = width; 2132 2133 /* actual dirty register-value changing in the function below. */ 2134 pccbb_pcmcia_do_io_map(sc, win); 2135 2136 return 0; 2137 } 2138 2139 /* 2140 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2141 * 2142 * This function changes register-value to map I/O region for pccard. 2143 */ 2144 static void 2145 pccbb_pcmcia_do_io_map(struct pccbb_softc *sc, int win) 2146 { 2147 static u_int8_t pcic_iowidth[3] = { 2148 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2149 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2150 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2151 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2152 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2153 }; 2154 2155 #define PCIC_SIA_START_LOW 0 2156 #define PCIC_SIA_START_HIGH 1 2157 #define PCIC_SIA_STOP_LOW 2 2158 #define PCIC_SIA_STOP_HIGH 3 2159 2160 int regbase_win = 0x8 + win * 0x04; 2161 u_int8_t ioctl, enable; 2162 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2163 2164 DPRINTF(("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx " 2165 "width %d\n", win, (unsigned long)ph->io[win].addr, 2166 (unsigned long)ph->io[win].size, ph->io[win].width * 8)); 2167 2168 Pcic_write(sc, regbase_win + PCIC_SIA_START_LOW, 2169 ph->io[win].addr & 0xff); 2170 Pcic_write(sc, regbase_win + PCIC_SIA_START_HIGH, 2171 (ph->io[win].addr >> 8) & 0xff); 2172 2173 Pcic_write(sc, regbase_win + PCIC_SIA_STOP_LOW, 2174 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2175 Pcic_write(sc, regbase_win + PCIC_SIA_STOP_HIGH, 2176 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2177 2178 ioctl = Pcic_read(sc, PCIC_IOCTL); 2179 enable = Pcic_read(sc, PCIC_ADDRWIN_ENABLE); 2180 switch (win) { 2181 case 0: 2182 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2183 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2184 PCIC_IOCTL_IO0_DATASIZE_MASK); 2185 ioctl |= pcic_iowidth[ph->io[win].width]; 2186 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2187 break; 2188 case 1: 2189 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2190 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2191 PCIC_IOCTL_IO1_DATASIZE_MASK); 2192 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2193 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2194 break; 2195 } 2196 Pcic_write(sc, PCIC_IOCTL, ioctl); 2197 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, enable); 2198 #if defined(CBB_DEBUG) 2199 { 2200 u_int8_t start_low = 2201 Pcic_read(sc, regbase_win + PCIC_SIA_START_LOW); 2202 u_int8_t start_high = 2203 Pcic_read(sc, regbase_win + PCIC_SIA_START_HIGH); 2204 u_int8_t stop_low = 2205 Pcic_read(sc, regbase_win + PCIC_SIA_STOP_LOW); 2206 u_int8_t stop_high = 2207 Pcic_read(sc, regbase_win + PCIC_SIA_STOP_HIGH); 2208 printf("pccbb_pcmcia_do_io_map start %02x %02x, " 2209 "stop %02x %02x, ioctl %02x enable %02x\n", 2210 start_low, start_high, stop_low, stop_high, ioctl, enable); 2211 } 2212 #endif 2213 } 2214 2215 /* 2216 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2217 * 2218 * This function unmaps I/O region. No return value. 2219 */ 2220 STATIC void 2221 pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t pch, int win) 2222 { 2223 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2224 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2225 int reg; 2226 2227 if (win >= PCIC_IO_WINS || win < 0) { 2228 panic("pccbb_pcmcia_io_unmap: window out of range"); 2229 } 2230 2231 reg = Pcic_read(sc, PCIC_ADDRWIN_ENABLE); 2232 switch (win) { 2233 case 0: 2234 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2235 break; 2236 case 1: 2237 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2238 break; 2239 } 2240 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, reg); 2241 2242 ph->ioalloc &= ~(1 << win); 2243 } 2244 2245 static int 2246 pccbb_pcmcia_wait_ready(struct pccbb_softc *sc) 2247 { 2248 u_int8_t stat; 2249 int i; 2250 2251 /* wait an initial 10ms for quick cards */ 2252 stat = Pcic_read(sc, PCIC_IF_STATUS); 2253 if (stat & PCIC_IF_STATUS_READY) 2254 return (0); 2255 pccbb_pcmcia_delay(sc, 10, "pccwr0"); 2256 for (i = 0; i < 50; i++) { 2257 stat = Pcic_read(sc, PCIC_IF_STATUS); 2258 if (stat & PCIC_IF_STATUS_READY) 2259 return (0); 2260 if ((stat & PCIC_IF_STATUS_CARDDETECT_MASK) != 2261 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2262 return (ENXIO); 2263 /* wait .1s (100ms) each iteration now */ 2264 pccbb_pcmcia_delay(sc, 100, "pccwr1"); 2265 } 2266 2267 printf("pccbb_pcmcia_wait_ready: ready never happened, status=%02x\n", stat); 2268 return (EWOULDBLOCK); 2269 } 2270 2271 /* 2272 * Perform long (msec order) delay. timo is in milliseconds. 2273 */ 2274 static void 2275 pccbb_pcmcia_delay(struct pccbb_softc *sc, int timo, const char *wmesg) 2276 { 2277 #ifdef DIAGNOSTIC 2278 if (timo <= 0) 2279 panic("pccbb_pcmcia_delay: called with timeout %d", timo); 2280 if (!curlwp) 2281 panic("pccbb_pcmcia_delay: called in interrupt context"); 2282 #endif 2283 DPRINTF(("pccbb_pcmcia_delay: \"%s\", sleep %d ms\n", wmesg, timo)); 2284 tsleep(pccbb_pcmcia_delay, PWAIT, wmesg, roundup(timo * hz, 1000) / 1000); 2285 } 2286 2287 /* 2288 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2289 * 2290 * This function enables the card. All information is stored in 2291 * the first argument, pcmcia_chipset_handle_t. 2292 */ 2293 STATIC void 2294 pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2295 { 2296 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2297 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2298 pcireg_t spsr; 2299 int voltage; 2300 int win; 2301 u_int8_t power, intr; 2302 #ifdef DIAGNOSTIC 2303 int reg; 2304 #endif 2305 2306 /* this bit is mostly stolen from pcic_attach_card */ 2307 2308 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2309 2310 /* get card Vcc info */ 2311 spsr = 2312 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2313 CB_SOCKET_STAT); 2314 if (spsr & CB_SOCKET_STAT_5VCARD) { 2315 DPRINTF(("5V card\n")); 2316 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2317 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2318 DPRINTF(("3V card\n")); 2319 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2320 } else { 2321 DPRINTF(("?V card, 0x%x\n", spsr)); /* XXX */ 2322 return; 2323 } 2324 2325 /* disable interrupts; assert RESET */ 2326 intr = Pcic_read(sc, PCIC_INTR); 2327 intr &= PCIC_INTR_ENABLE; 2328 Pcic_write(sc, PCIC_INTR, intr); 2329 2330 /* zero out the address windows */ 2331 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, 0); 2332 2333 /* power down the socket to reset it, clear the card reset pin */ 2334 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2335 2336 /* power off; assert output enable bit */ 2337 power = PCIC_PWRCTL_OE; 2338 Pcic_write(sc, PCIC_PWRCTL, power); 2339 2340 /* power up the socket */ 2341 if (pccbb_power(sc, voltage) == 0) 2342 return; 2343 2344 /* 2345 * Table 4-18 and figure 4-6 of the PC Card specifiction say: 2346 * Vcc Rising Time (Tpr) = 100ms (handled in pccbb_power() above) 2347 * RESET Width (Th (Hi-z RESET)) = 1ms 2348 * RESET Width (Tw (RESET)) = 10us 2349 * 2350 * some machines require some more time to be settled 2351 * for example old toshiba topic bridges! 2352 * (100ms is added here). 2353 */ 2354 pccbb_pcmcia_delay(sc, 200 + 1, "pccen1"); 2355 2356 /* negate RESET */ 2357 intr |= PCIC_INTR_RESET; 2358 Pcic_write(sc, PCIC_INTR, intr); 2359 2360 /* 2361 * RESET Setup Time (Tsu (RESET)) = 20ms 2362 */ 2363 pccbb_pcmcia_delay(sc, 20, "pccen2"); 2364 2365 #ifdef DIAGNOSTIC 2366 reg = Pcic_read(sc, PCIC_IF_STATUS); 2367 if ((reg & PCIC_IF_STATUS_POWERACTIVE) == 0) 2368 printf("pccbb_pcmcia_socket_enable: no power, status=%x\n", reg); 2369 #endif 2370 2371 /* wait for the chip to finish initializing */ 2372 if (pccbb_pcmcia_wait_ready(sc)) { 2373 #ifdef DIAGNOSTIC 2374 printf("pccbb_pcmcia_socket_enable: never became ready\n"); 2375 #endif 2376 /* XXX return a failure status?? */ 2377 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2378 Pcic_write(sc, PCIC_PWRCTL, 0); 2379 return; 2380 } 2381 2382 /* reinstall all the memory and io mappings */ 2383 for (win = 0; win < PCIC_MEM_WINS; ++win) 2384 if (ph->memalloc & (1 << win)) 2385 pccbb_pcmcia_do_mem_map(sc, win); 2386 for (win = 0; win < PCIC_IO_WINS; ++win) 2387 if (ph->ioalloc & (1 << win)) 2388 pccbb_pcmcia_do_io_map(sc, win); 2389 } 2390 2391 /* 2392 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2393 * 2394 * This function disables the card. All information is stored in 2395 * the first argument, pcmcia_chipset_handle_t. 2396 */ 2397 STATIC void 2398 pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t pch) 2399 { 2400 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2401 u_int8_t intr; 2402 2403 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2404 2405 /* disable interrupts; assert RESET */ 2406 intr = Pcic_read(sc, PCIC_INTR); 2407 intr &= PCIC_INTR_ENABLE; 2408 Pcic_write(sc, PCIC_INTR, intr); 2409 2410 /* zero out the address windows */ 2411 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, 0); 2412 2413 /* power down the socket to reset it, clear the card reset pin */ 2414 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2415 2416 /* disable socket: negate output enable bit and power off */ 2417 Pcic_write(sc, PCIC_PWRCTL, 0); 2418 2419 /* 2420 * Vcc Falling Time (Tpf) = 300ms 2421 */ 2422 pccbb_pcmcia_delay(sc, 300, "pccwr1"); 2423 } 2424 2425 STATIC void 2426 pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t pch, int type) 2427 { 2428 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2429 u_int8_t intr; 2430 2431 /* set the card type */ 2432 2433 intr = Pcic_read(sc, PCIC_INTR); 2434 intr &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_CARDTYPE_MASK); 2435 if (type == PCMCIA_IFTYPE_IO) 2436 intr |= PCIC_INTR_CARDTYPE_IO; 2437 else 2438 intr |= PCIC_INTR_CARDTYPE_MEM; 2439 Pcic_write(sc, PCIC_INTR, intr); 2440 2441 DPRINTF(("%s: pccbb_pcmcia_socket_settype type %s %02x\n", 2442 device_xname(sc->sc_dev), 2443 ((type == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2444 } 2445 2446 /* 2447 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2448 * 2449 * This function detects whether a card is in the slot or not. 2450 * If a card is inserted, return 1. Otherwise, return 0. 2451 */ 2452 STATIC int 2453 pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch) 2454 { 2455 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2456 2457 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2458 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2459 } 2460 2461 #if 0 2462 STATIC int 2463 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2464 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2465 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2466 #endif 2467 /* 2468 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2469 * bus_size_t size, 2470 * struct pcmcia_mem_handle *pcmhp) 2471 * 2472 * This function only allocates memory region for pccard. This 2473 * function never maps the allocated region to pccard memory area. 2474 * 2475 * XXX: Why the argument of start address is not in? 2476 */ 2477 STATIC int 2478 pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 2479 struct pcmcia_mem_handle *pcmhp) 2480 { 2481 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2482 bus_space_handle_t memh; 2483 bus_addr_t addr; 2484 bus_size_t sizepg; 2485 #if rbus 2486 rbus_tag_t rb; 2487 #endif 2488 2489 /* Check that the card is still there. */ 2490 if ((Pcic_read(sc, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2491 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2492 return 1; 2493 2494 /* out of sc->memh, allocate as many pages as necessary */ 2495 2496 /* convert size to PCIC pages */ 2497 /* 2498 * This is not enough; when the requested region is on the page 2499 * boundaries, this may calculate wrong result. 2500 */ 2501 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2502 #if 0 2503 if (sizepg > PCIC_MAX_MEM_PAGES) { 2504 return 1; 2505 } 2506 #endif 2507 2508 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2509 return 1; 2510 } 2511 2512 addr = 0; /* XXX gcc -Wuninitialized */ 2513 2514 #if rbus 2515 rb = sc->sc_rbus_memt; 2516 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2517 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2518 &addr, &memh)) { 2519 return 1; 2520 } 2521 #else 2522 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2523 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2524 0, /* boundary */ 2525 0, /* flags */ 2526 &addr, &memh)) { 2527 return 1; 2528 } 2529 #endif 2530 2531 DPRINTF(("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, " 2532 "realsize 0x%lx\n", (unsigned long)addr, (unsigned long)size, 2533 (unsigned long)sizepg * PCIC_MEM_PAGESIZE)); 2534 2535 pcmhp->memt = sc->sc_memt; 2536 pcmhp->memh = memh; 2537 pcmhp->addr = addr; 2538 pcmhp->size = size; 2539 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2540 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2541 pcmhp->mhandle = 0; 2542 /* No offset??? Funny. */ 2543 2544 return 0; 2545 } 2546 2547 /* 2548 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2549 * struct pcmcia_mem_handle *pcmhp) 2550 * 2551 * This function release the memory space allocated by the function 2552 * pccbb_pcmcia_mem_alloc(). 2553 */ 2554 STATIC void 2555 pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2556 struct pcmcia_mem_handle *pcmhp) 2557 { 2558 #if rbus 2559 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2560 2561 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2562 #else 2563 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2564 #endif 2565 } 2566 2567 /* 2568 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2569 * 2570 * This function release the memory space allocated by the function 2571 * pccbb_pcmcia_mem_alloc(). 2572 */ 2573 STATIC void 2574 pccbb_pcmcia_do_mem_map(struct pccbb_softc *sc, int win) 2575 { 2576 int regbase_win; 2577 bus_addr_t phys_addr; 2578 bus_addr_t phys_end; 2579 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2580 2581 #define PCIC_SMM_START_LOW 0 2582 #define PCIC_SMM_START_HIGH 1 2583 #define PCIC_SMM_STOP_LOW 2 2584 #define PCIC_SMM_STOP_HIGH 3 2585 #define PCIC_CMA_LOW 4 2586 #define PCIC_CMA_HIGH 5 2587 2588 u_int8_t start_low, start_high = 0; 2589 u_int8_t stop_low, stop_high; 2590 u_int8_t off_low, off_high; 2591 u_int8_t mem_window; 2592 int reg; 2593 2594 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2595 int mem8 = 2596 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2597 || (kind == PCMCIA_MEM_ATTR); 2598 2599 regbase_win = 0x10 + win * 0x08; 2600 2601 phys_addr = ph->mem[win].addr; 2602 phys_end = phys_addr + ph->mem[win].size; 2603 2604 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2605 (unsigned long)phys_addr, (unsigned long)phys_end, 2606 (unsigned long)ph->mem[win].offset)); 2607 2608 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2609 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2610 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2611 2612 /* bit 19:12 */ 2613 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2614 /* bit 23:20 and bit 7 on */ 2615 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2616 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2617 /* bit 31:24, for 32-bit address */ 2618 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2619 2620 Pcic_write(sc, regbase_win + PCIC_SMM_START_LOW, start_low); 2621 Pcic_write(sc, regbase_win + PCIC_SMM_START_HIGH, start_high); 2622 2623 if (sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2624 Pcic_write(sc, 0x40 + win, mem_window); 2625 } 2626 2627 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2628 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2629 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2630 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2631 2632 Pcic_write(sc, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2633 Pcic_write(sc, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2634 2635 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2636 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2637 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2638 | ((kind == PCMCIA_MEM_ATTR) ? 2639 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2640 2641 Pcic_write(sc, regbase_win + PCIC_CMA_LOW, off_low); 2642 Pcic_write(sc, regbase_win + PCIC_CMA_HIGH, off_high); 2643 2644 reg = Pcic_read(sc, PCIC_ADDRWIN_ENABLE); 2645 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2646 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, reg); 2647 2648 #if defined(CBB_DEBUG) 2649 { 2650 int r1, r2, r3, r4, r5, r6, r7 = 0; 2651 2652 r1 = Pcic_read(sc, regbase_win + PCIC_SMM_START_LOW); 2653 r2 = Pcic_read(sc, regbase_win + PCIC_SMM_START_HIGH); 2654 r3 = Pcic_read(sc, regbase_win + PCIC_SMM_STOP_LOW); 2655 r4 = Pcic_read(sc, regbase_win + PCIC_SMM_STOP_HIGH); 2656 r5 = Pcic_read(sc, regbase_win + PCIC_CMA_LOW); 2657 r6 = Pcic_read(sc, regbase_win + PCIC_CMA_HIGH); 2658 if (sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2659 r7 = Pcic_read(sc, 0x40 + win); 2660 } 2661 2662 printf("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2663 "%02x%02x", win, r1, r2, r3, r4, r5, r6); 2664 if (sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2665 printf(" %02x", r7); 2666 } 2667 printf("\n"); 2668 } 2669 #endif 2670 } 2671 2672 /* 2673 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2674 * bus_addr_t card_addr, bus_size_t size, 2675 * struct pcmcia_mem_handle *pcmhp, 2676 * bus_addr_t *offsetp, int *windowp) 2677 * 2678 * This function maps memory space allocated by the function 2679 * pccbb_pcmcia_mem_alloc(). 2680 */ 2681 STATIC int 2682 pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2683 bus_addr_t card_addr, bus_size_t size, struct pcmcia_mem_handle *pcmhp, 2684 bus_addr_t *offsetp, int *windowp) 2685 { 2686 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2687 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2688 bus_addr_t busaddr; 2689 long card_offset; 2690 int win; 2691 2692 /* Check that the card is still there. */ 2693 if ((Pcic_read(sc, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2694 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2695 return 1; 2696 2697 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2698 if ((ph->memalloc & (1 << win)) == 0) { 2699 ph->memalloc |= (1 << win); 2700 break; 2701 } 2702 } 2703 2704 if (win == PCIC_MEM_WINS) { 2705 return 1; 2706 } 2707 2708 *windowp = win; 2709 2710 /* XXX this is pretty gross */ 2711 2712 if (sc->sc_memt != pcmhp->memt) { 2713 panic("pccbb_pcmcia_mem_map memt is bogus"); 2714 } 2715 2716 busaddr = pcmhp->addr; 2717 2718 /* 2719 * compute the address offset to the pcmcia address space for the 2720 * pcic. this is intentionally signed. The masks and shifts below 2721 * will cause TRT to happen in the pcic registers. Deal with making 2722 * sure the address is aligned, and return the alignment offset. 2723 */ 2724 2725 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2726 card_addr -= *offsetp; 2727 2728 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2729 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2730 (u_long) card_addr)); 2731 2732 /* 2733 * include the offset in the size, and decrement size by one, since 2734 * the hw wants start/stop 2735 */ 2736 size += *offsetp - 1; 2737 2738 card_offset = (((long)card_addr) - ((long)busaddr)); 2739 2740 ph->mem[win].addr = busaddr; 2741 ph->mem[win].size = size; 2742 ph->mem[win].offset = card_offset; 2743 ph->mem[win].kind = kind; 2744 2745 pccbb_pcmcia_do_mem_map(sc, win); 2746 2747 return 0; 2748 } 2749 2750 /* 2751 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2752 * int window) 2753 * 2754 * This function unmaps memory space which mapped by the function 2755 * pccbb_pcmcia_mem_map(). 2756 */ 2757 STATIC void 2758 pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, int window) 2759 { 2760 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2761 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2762 int reg; 2763 2764 if (window >= PCIC_MEM_WINS) { 2765 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2766 } 2767 2768 reg = Pcic_read(sc, PCIC_ADDRWIN_ENABLE); 2769 reg &= ~(1 << window); 2770 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, reg); 2771 2772 ph->memalloc &= ~(1 << window); 2773 } 2774 2775 /* 2776 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2777 * struct pcmcia_function *pf, 2778 * int ipl, 2779 * int (*func)(void *), 2780 * void *arg); 2781 * 2782 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2783 */ 2784 STATIC void * 2785 pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2786 struct pcmcia_function *pf, int ipl, int (*func)(void *), void *arg) 2787 { 2788 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2789 2790 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2791 /* what should I do? */ 2792 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2793 DPRINTF(("%s does not provide edge nor pulse " 2794 "interrupt\n", device_xname(sc->sc_dev))); 2795 return NULL; 2796 } 2797 /* 2798 * XXX Noooooo! The interrupt flag must set properly!! 2799 * dumb pcmcia driver!! 2800 */ 2801 } 2802 2803 return pccbb_intr_establish(sc, 0, ipl, func, arg); 2804 } 2805 2806 /* 2807 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2808 * void *ih) 2809 * 2810 * This function disables PC-Card interrupt. 2811 */ 2812 STATIC void 2813 pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 2814 { 2815 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2816 2817 pccbb_intr_disestablish(sc, ih); 2818 } 2819 2820 #if rbus 2821 /* 2822 * static int 2823 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2824 * bus_addr_t addr, bus_size_t size, 2825 * bus_addr_t mask, bus_size_t align, 2826 * int flags, bus_addr_t *addrp; 2827 * bus_space_handle_t *bshp) 2828 * 2829 * This function allocates a portion of memory or io space for 2830 * clients. This function is called from CardBus card drivers. 2831 */ 2832 static int 2833 pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2834 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 2835 int flags, bus_addr_t *addrp, bus_space_handle_t *bshp) 2836 { 2837 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2838 2839 DPRINTF(("pccbb_rbus_cb_space_alloc: addr 0x%lx, size 0x%lx, " 2840 "mask 0x%lx, align 0x%lx\n", (unsigned long)addr, 2841 (unsigned long)size, (unsigned long)mask, (unsigned long)align)); 2842 2843 if (align == 0) { 2844 align = size; 2845 } 2846 2847 if (rb->rb_bt == sc->sc_memt) { 2848 if (align < 16) { 2849 return 1; 2850 } 2851 /* 2852 * XXX: align more than 0x1000 to avoid overwrapping 2853 * memory windows for two or more devices. 0x1000 2854 * means memory window's granularity. 2855 * 2856 * Two or more devices should be able to share same 2857 * memory window region. However, overrapping memory 2858 * window is not good because some devices, such as 2859 * 3Com 3C575[BC], have a broken address decoder and 2860 * intrude other's memory region. 2861 */ 2862 if (align < 0x1000) { 2863 align = 0x1000; 2864 } 2865 } else if (rb->rb_bt == sc->sc_iot) { 2866 if (align < 4) { 2867 return 1; 2868 } 2869 /* XXX: hack for avoiding ISA image */ 2870 if (mask < 0x0100) { 2871 mask = 0x3ff; 2872 addr = 0x300; 2873 } 2874 2875 } else { 2876 DPRINTF(("pccbb_rbus_cb_space_alloc: Bus space tag 0x%lx is " 2877 "NOT used. io: 0x%lx, mem: 0x%lx\n", 2878 (unsigned long)rb->rb_bt, (unsigned long)sc->sc_iot, 2879 (unsigned long)sc->sc_memt)); 2880 return 1; 2881 /* XXX: panic here? */ 2882 } 2883 2884 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 2885 aprint_normal_dev(sc->sc_dev, "<rbus> no bus space\n"); 2886 return 1; 2887 } 2888 2889 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 2890 2891 return 0; 2892 } 2893 2894 /* 2895 * static int 2896 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 2897 * bus_space_handle_t *bshp, bus_size_t size); 2898 * 2899 * This function is called from CardBus card drivers. 2900 */ 2901 static int 2902 pccbb_rbus_cb_space_free(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2903 bus_space_handle_t bsh, bus_size_t size) 2904 { 2905 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2906 bus_space_tag_t bt = rb->rb_bt; 2907 2908 pccbb_close_win(sc, bt, bsh, size); 2909 2910 if (bt == sc->sc_memt) { 2911 } else if (bt == sc->sc_iot) { 2912 } else { 2913 return 1; 2914 /* XXX: panic here? */ 2915 } 2916 2917 return rbus_space_free(rb, bsh, size, NULL); 2918 } 2919 #endif /* rbus */ 2920 2921 #if rbus 2922 2923 static int 2924 pccbb_open_win(struct pccbb_softc *sc, bus_space_tag_t bst, bus_addr_t addr, 2925 bus_size_t size, bus_space_handle_t bsh, int flags) 2926 { 2927 struct pccbb_win_chain_head *head; 2928 bus_addr_t align; 2929 2930 head = &sc->sc_iowindow; 2931 align = 0x04; 2932 if (sc->sc_memt == bst) { 2933 head = &sc->sc_memwindow; 2934 align = 0x1000; 2935 DPRINTF(("using memory window, 0x%lx 0x%lx 0x%lx\n\n", 2936 (unsigned long)sc->sc_iot, (unsigned long)sc->sc_memt, 2937 (unsigned long)bst)); 2938 } 2939 2940 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 2941 aprint_error_dev(sc->sc_dev, 2942 "pccbb_open_win: %s winlist insert failed\n", 2943 (head == &sc->sc_memwindow) ? "mem" : "io"); 2944 } 2945 pccbb_winset(align, sc, bst); 2946 2947 return 0; 2948 } 2949 2950 static int 2951 pccbb_close_win(struct pccbb_softc *sc, bus_space_tag_t bst, 2952 bus_space_handle_t bsh, bus_size_t size) 2953 { 2954 struct pccbb_win_chain_head *head; 2955 bus_addr_t align; 2956 2957 head = &sc->sc_iowindow; 2958 align = 0x04; 2959 if (sc->sc_memt == bst) { 2960 head = &sc->sc_memwindow; 2961 align = 0x1000; 2962 } 2963 2964 if (pccbb_winlist_delete(head, bsh, size)) { 2965 aprint_error_dev(sc->sc_dev, 2966 "pccbb_close_win: %s winlist delete failed\n", 2967 (head == &sc->sc_memwindow) ? "mem" : "io"); 2968 } 2969 pccbb_winset(align, sc, bst); 2970 2971 return 0; 2972 } 2973 2974 static int 2975 pccbb_winlist_insert(struct pccbb_win_chain_head *head, bus_addr_t start, 2976 bus_size_t size, bus_space_handle_t bsh, int flags) 2977 { 2978 struct pccbb_win_chain *chainp, *elem; 2979 2980 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 2981 M_NOWAIT)) == NULL) 2982 return (1); /* fail */ 2983 2984 elem->wc_start = start; 2985 elem->wc_end = start + (size - 1); 2986 elem->wc_handle = bsh; 2987 elem->wc_flags = flags; 2988 2989 TAILQ_FOREACH(chainp, head, wc_list) { 2990 if (chainp->wc_end >= start) 2991 break; 2992 } 2993 if (chainp != NULL) 2994 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 2995 else 2996 TAILQ_INSERT_TAIL(head, elem, wc_list); 2997 return (0); 2998 } 2999 3000 static int 3001 pccbb_winlist_delete(struct pccbb_win_chain_head *head, bus_space_handle_t bsh, 3002 bus_size_t size) 3003 { 3004 struct pccbb_win_chain *chainp; 3005 3006 TAILQ_FOREACH(chainp, head, wc_list) { 3007 if (memcmp(&chainp->wc_handle, &bsh, sizeof(bsh)) == 0) 3008 break; 3009 } 3010 if (chainp == NULL) 3011 return 1; /* fail: no candidate to remove */ 3012 3013 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 3014 printf("pccbb_winlist_delete: window 0x%lx size " 3015 "inconsistent: 0x%lx, 0x%lx\n", 3016 (unsigned long)chainp->wc_start, 3017 (unsigned long)(chainp->wc_end - chainp->wc_start), 3018 (unsigned long)(size - 1)); 3019 return 1; 3020 } 3021 3022 TAILQ_REMOVE(head, chainp, wc_list); 3023 free(chainp, M_DEVBUF); 3024 3025 return 0; 3026 } 3027 3028 static void 3029 pccbb_winset(bus_addr_t align, struct pccbb_softc *sc, bus_space_tag_t bst) 3030 { 3031 pci_chipset_tag_t pc; 3032 pcitag_t tag; 3033 bus_addr_t mask = ~(align - 1); 3034 struct { 3035 cardbusreg_t win_start; 3036 cardbusreg_t win_limit; 3037 int win_flags; 3038 } win[2]; 3039 struct pccbb_win_chain *chainp; 3040 int offs; 3041 3042 win[0].win_start = win[1].win_start = 0xffffffff; 3043 win[0].win_limit = win[1].win_limit = 0; 3044 win[0].win_flags = win[1].win_flags = 0; 3045 3046 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3047 offs = PCI_CB_IOBASE0; 3048 if (sc->sc_memt == bst) { 3049 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3050 offs = PCI_CB_MEMBASE0; 3051 } 3052 3053 if (chainp != NULL) { 3054 win[0].win_start = chainp->wc_start & mask; 3055 win[0].win_limit = chainp->wc_end & mask; 3056 win[0].win_flags = chainp->wc_flags; 3057 chainp = TAILQ_NEXT(chainp, wc_list); 3058 } 3059 3060 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3061 if (win[1].win_start == 0xffffffff) { 3062 /* window 1 is not used */ 3063 if ((win[0].win_flags == chainp->wc_flags) && 3064 (win[0].win_limit + align >= 3065 (chainp->wc_start & mask))) { 3066 /* concatenate */ 3067 win[0].win_limit = chainp->wc_end & mask; 3068 } else { 3069 /* make new window */ 3070 win[1].win_start = chainp->wc_start & mask; 3071 win[1].win_limit = chainp->wc_end & mask; 3072 win[1].win_flags = chainp->wc_flags; 3073 } 3074 continue; 3075 } 3076 3077 /* Both windows are engaged. */ 3078 if (win[0].win_flags == win[1].win_flags) { 3079 /* same flags */ 3080 if (win[0].win_flags == chainp->wc_flags) { 3081 if (win[1].win_start - (win[0].win_limit + 3082 align) < 3083 (chainp->wc_start & mask) - 3084 ((chainp->wc_end & mask) + align)) { 3085 /* 3086 * merge window 0 and 1, and set win1 3087 * to chainp 3088 */ 3089 win[0].win_limit = win[1].win_limit; 3090 win[1].win_start = 3091 chainp->wc_start & mask; 3092 win[1].win_limit = 3093 chainp->wc_end & mask; 3094 } else { 3095 win[1].win_limit = 3096 chainp->wc_end & mask; 3097 } 3098 } else { 3099 /* different flags */ 3100 3101 /* concatenate win0 and win1 */ 3102 win[0].win_limit = win[1].win_limit; 3103 /* allocate win[1] to new space */ 3104 win[1].win_start = chainp->wc_start & mask; 3105 win[1].win_limit = chainp->wc_end & mask; 3106 win[1].win_flags = chainp->wc_flags; 3107 } 3108 } else { 3109 /* the flags of win[0] and win[1] is different */ 3110 if (win[0].win_flags == chainp->wc_flags) { 3111 win[0].win_limit = chainp->wc_end & mask; 3112 /* 3113 * XXX this creates overlapping windows, so 3114 * what should the poor bridge do if one is 3115 * cachable, and the other is not? 3116 */ 3117 aprint_error_dev(sc->sc_dev, 3118 "overlapping windows\n"); 3119 } else { 3120 win[1].win_limit = chainp->wc_end & mask; 3121 } 3122 } 3123 } 3124 3125 pc = sc->sc_pc; 3126 tag = sc->sc_tag; 3127 pci_conf_write(pc, tag, offs, win[0].win_start); 3128 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3129 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3130 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3131 DPRINTF(("--pccbb_winset: win0 [0x%lx, 0x%lx), win1 [0x%lx, 0x%lx)\n", 3132 (unsigned long)pci_conf_read(pc, tag, offs), 3133 (unsigned long)pci_conf_read(pc, tag, offs + 4) + align, 3134 (unsigned long)pci_conf_read(pc, tag, offs + 8), 3135 (unsigned long)pci_conf_read(pc, tag, offs + 12) + align)); 3136 3137 if (bst == sc->sc_memt) { 3138 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BRIDGE_CONTROL_REG); 3139 3140 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 3141 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 3142 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3143 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 3144 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3145 pci_conf_write(pc, tag, PCI_BRIDGE_CONTROL_REG, bcr); 3146 } 3147 } 3148 3149 #endif /* rbus */ 3150 3151 static bool 3152 pccbb_suspend(device_t dv PMF_FN_ARGS) 3153 { 3154 struct pccbb_softc *sc = device_private(dv); 3155 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3156 bus_space_handle_t base_memh = sc->sc_base_memh; 3157 pcireg_t reg; 3158 3159 if (sc->sc_pil_intr_enable) 3160 (void)pccbbintr_function(sc); 3161 sc->sc_pil_intr_enable = 0; 3162 3163 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3164 /* Disable interrupts. */ 3165 reg &= ~(CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER); 3166 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3167 /* XXX joerg Disable power to the socket? */ 3168 3169 /* XXX flush PCI write */ 3170 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3171 3172 /* reset interrupt */ 3173 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, 3174 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT)); 3175 /* XXX flush PCI write */ 3176 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3177 3178 if (sc->sc_ih != NULL) { 3179 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 3180 sc->sc_ih = NULL; 3181 } 3182 3183 return true; 3184 } 3185 3186 static bool 3187 pccbb_resume(device_t dv PMF_FN_ARGS) 3188 { 3189 struct pccbb_softc *sc = device_private(dv); 3190 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3191 bus_space_handle_t base_memh = sc->sc_base_memh; 3192 pcireg_t reg; 3193 3194 pccbb_chipinit(sc); 3195 pccbb_intrinit(sc); 3196 /* setup memory and io space window for CB */ 3197 pccbb_winset(0x1000, sc, sc->sc_memt); 3198 pccbb_winset(0x04, sc, sc->sc_iot); 3199 3200 /* CSC Interrupt: Card detect interrupt on */ 3201 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3202 /* Card detect intr is turned on. */ 3203 reg |= CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; 3204 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3205 /* reset interrupt */ 3206 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3207 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3208 3209 /* 3210 * check for card insertion or removal during suspend period. 3211 * XXX: the code can't cope with card swap (remove then 3212 * insert). how can we detect such situation? 3213 */ 3214 (void)pccbbintr(sc); 3215 3216 sc->sc_pil_intr_enable = 1; 3217 3218 return true; 3219 } 3220
Indexes created Fri Sep 26 20:09:58 GMT 2025