pccbb.c revision 1.184
1 /* $NetBSD: pccbb.c,v 1.184 2009/03/05 01:38:12 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: pccbb.c,v 1.184 2009/03/05 01:38:12 msaitoh Exp $"); 35 36 /* 37 #define CBB_DEBUG 38 #define SHOW_REGS 39 */ 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/kernel.h> 44 #include <sys/errno.h> 45 #include <sys/ioctl.h> 46 #include <sys/reboot.h> /* for bootverbose */ 47 #include <sys/syslog.h> 48 #include <sys/device.h> 49 #include <sys/malloc.h> 50 #include <sys/proc.h> 51 52 #include <sys/intr.h> 53 #include <sys/bus.h> 54 55 #include <dev/pci/pcivar.h> 56 #include <dev/pci/pcireg.h> 57 #include <dev/pci/pcidevs.h> 58 59 #include <dev/pci/pccbbreg.h> 60 61 #include <dev/cardbus/cardslotvar.h> 62 63 #include <dev/cardbus/cardbusvar.h> 64 65 #include <dev/pcmcia/pcmciareg.h> 66 #include <dev/pcmcia/pcmciavar.h> 67 68 #include <dev/ic/i82365reg.h> 69 #include <dev/pci/pccbbvar.h> 70 71 #ifndef __NetBSD_Version__ 72 struct cfdriver cbb_cd = { 73 NULL, "cbb", DV_DULL 74 }; 75 #endif 76 77 #ifdef CBB_DEBUG 78 #define DPRINTF(x) printf x 79 #define STATIC 80 #else 81 #define DPRINTF(x) 82 #define STATIC static 83 #endif 84 85 int pccbb_burstup = 1; 86 87 /* 88 * delay_ms() is wait in milliseconds. It should be used instead 89 * of delay() if you want to wait more than 1 ms. 90 */ 91 static inline void 92 delay_ms(int millis, void *param) 93 { 94 if (cold) 95 delay(millis * 1000); 96 else 97 tsleep(param, PWAIT, "pccbb", MAX(2, hz * millis / 1000)); 98 } 99 100 int pcicbbmatch(device_t, struct cfdata *, void *); 101 void pccbbattach(device_t, device_t, void *); 102 int pccbbdetach(device_t, int); 103 int pccbbintr(void *); 104 static void pci113x_insert(void *); 105 static int pccbbintr_function(struct pccbb_softc *); 106 107 static int pccbb_detect_card(struct pccbb_softc *); 108 109 static void pccbb_pcmcia_write(struct pccbb_softc *, int, u_int8_t); 110 static u_int8_t pccbb_pcmcia_read(struct pccbb_softc *, int); 111 #define Pcic_read(sc, reg) pccbb_pcmcia_read((sc), (reg)) 112 #define Pcic_write(sc, reg, val) pccbb_pcmcia_write((sc), (reg), (val)) 113 114 STATIC int cb_reset(struct pccbb_softc *); 115 STATIC int cb_detect_voltage(struct pccbb_softc *); 116 STATIC int cbbprint(void *, const char *); 117 118 static int cb_chipset(u_int32_t, int *); 119 STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *, 120 struct pcmciabus_attach_args *); 121 122 STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int); 123 STATIC int pccbb_power(struct pccbb_softc *sc, int); 124 STATIC int pccbb_power_ct(cardbus_chipset_tag_t, int); 125 STATIC int pccbb_cardenable(struct pccbb_softc * sc, int function); 126 #if !rbus 127 static int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 128 static int pccbb_io_close(cardbus_chipset_tag_t, int); 129 static int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 130 static int pccbb_mem_close(cardbus_chipset_tag_t, int); 131 #endif /* !rbus */ 132 static void *pccbb_intr_establish(struct pccbb_softc *, 133 cardbus_intr_line_t irq, int level, int (*ih) (void *), void *sc); 134 static void pccbb_intr_disestablish(struct pccbb_softc *, void *ih); 135 136 static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t, 137 cardbus_intr_line_t irq, int level, int (*ih) (void *), void *sc); 138 static void pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih); 139 140 static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t, int, int); 141 static void pccbb_free_tag(cardbus_chipset_tag_t, cardbustag_t); 142 static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t, cardbustag_t, int); 143 static void pccbb_conf_write(cardbus_chipset_tag_t, cardbustag_t, int, 144 cardbusreg_t); 145 static void pccbb_chipinit(struct pccbb_softc *); 146 static void pccbb_intrinit(struct pccbb_softc *); 147 148 STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 149 struct pcmcia_mem_handle *); 150 STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t, 151 struct pcmcia_mem_handle *); 152 STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 153 bus_size_t, struct pcmcia_mem_handle *, bus_size_t *, int *); 154 STATIC void pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t, int); 155 STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 156 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 157 STATIC void pccbb_pcmcia_io_free(pcmcia_chipset_handle_t, 158 struct pcmcia_io_handle *); 159 STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 160 bus_size_t, struct pcmcia_io_handle *, int *); 161 STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t, int); 162 STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t, 163 struct pcmcia_function *, int, int (*)(void *), void *); 164 STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t, void *); 165 STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t); 166 STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t); 167 STATIC void pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t, int); 168 STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch); 169 170 static int pccbb_pcmcia_wait_ready(struct pccbb_softc *); 171 static void pccbb_pcmcia_delay(struct pccbb_softc *, int, const char *); 172 173 static void pccbb_pcmcia_do_io_map(struct pccbb_softc *, int); 174 static void pccbb_pcmcia_do_mem_map(struct pccbb_softc *, int); 175 176 /* bus-space allocation and deallocation functions */ 177 #if rbus 178 179 static int pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t, rbus_tag_t, 180 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 181 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp); 182 static int pccbb_rbus_cb_space_free(cardbus_chipset_tag_t, rbus_tag_t, 183 bus_space_handle_t, bus_size_t); 184 185 #endif /* rbus */ 186 187 #if rbus 188 189 static int pccbb_open_win(struct pccbb_softc *, bus_space_tag_t, 190 bus_addr_t, bus_size_t, bus_space_handle_t, int flags); 191 static int pccbb_close_win(struct pccbb_softc *, bus_space_tag_t, 192 bus_space_handle_t, bus_size_t); 193 static int pccbb_winlist_insert(struct pccbb_win_chain_head *, bus_addr_t, 194 bus_size_t, bus_space_handle_t, int); 195 static int pccbb_winlist_delete(struct pccbb_win_chain_head *, 196 bus_space_handle_t, bus_size_t); 197 static void pccbb_winset(bus_addr_t align, struct pccbb_softc *, 198 bus_space_tag_t); 199 void pccbb_winlist_show(struct pccbb_win_chain *); 200 201 #endif /* rbus */ 202 203 /* for config_defer */ 204 static void pccbb_pci_callback(device_t); 205 206 static bool pccbb_suspend(device_t PMF_FN_PROTO); 207 static bool pccbb_resume(device_t PMF_FN_PROTO); 208 209 #if defined SHOW_REGS 210 static void cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, 211 bus_space_tag_t memt, bus_space_handle_t memh); 212 #endif 213 214 CFATTACH_DECL_NEW(cbb_pci, sizeof(struct pccbb_softc), 215 pcicbbmatch, pccbbattach, pccbbdetach, NULL); 216 217 static const struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 218 pccbb_pcmcia_mem_alloc, 219 pccbb_pcmcia_mem_free, 220 pccbb_pcmcia_mem_map, 221 pccbb_pcmcia_mem_unmap, 222 pccbb_pcmcia_io_alloc, 223 pccbb_pcmcia_io_free, 224 pccbb_pcmcia_io_map, 225 pccbb_pcmcia_io_unmap, 226 pccbb_pcmcia_intr_establish, 227 pccbb_pcmcia_intr_disestablish, 228 pccbb_pcmcia_socket_enable, 229 pccbb_pcmcia_socket_disable, 230 pccbb_pcmcia_socket_settype, 231 pccbb_pcmcia_card_detect 232 }; 233 234 #if rbus 235 static const struct cardbus_functions pccbb_funcs = { 236 pccbb_rbus_cb_space_alloc, 237 pccbb_rbus_cb_space_free, 238 pccbb_cb_intr_establish, 239 pccbb_cb_intr_disestablish, 240 pccbb_ctrl, 241 pccbb_power_ct, 242 pccbb_make_tag, 243 pccbb_free_tag, 244 pccbb_conf_read, 245 pccbb_conf_write, 246 }; 247 #else 248 static const struct cardbus_functions pccbb_funcs = { 249 pccbb_ctrl, 250 pccbb_power_ct, 251 pccbb_mem_open, 252 pccbb_mem_close, 253 pccbb_io_open, 254 pccbb_io_close, 255 pccbb_cb_intr_establish, 256 pccbb_cb_intr_disestablish, 257 pccbb_make_tag, 258 pccbb_conf_read, 259 pccbb_conf_write, 260 }; 261 #endif 262 263 int 264 pcicbbmatch(device_t parent, struct cfdata *match, void *aux) 265 { 266 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 267 268 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 269 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 270 PCI_INTERFACE(pa->pa_class) == 0) { 271 return 1; 272 } 273 274 return 0; 275 } 276 277 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 278 | ((prod) << PCI_PRODUCT_SHIFT)) 279 280 const struct yenta_chipinfo { 281 pcireg_t yc_id; /* vendor tag | product tag */ 282 int yc_chiptype; 283 int yc_flags; 284 } yc_chipsets[] = { 285 /* Texas Instruments chips */ 286 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 287 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 288 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 289 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 290 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI125X, 291 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 292 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 293 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 294 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 295 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 296 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 297 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 298 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI125X, 299 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 300 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI125X, 301 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 302 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 303 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 304 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 305 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 306 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI1420, 307 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 308 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI125X, 309 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 310 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 311 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 312 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1520), CB_TI12XX, 313 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 314 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4410YENTA), CB_TI12XX, 315 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 316 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4520YENTA), CB_TI12XX, 317 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 318 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI7420YENTA), CB_TI12XX, 319 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 320 321 /* Ricoh chips */ 322 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 323 PCCBB_PCMCIA_MEM_32}, 324 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 325 PCCBB_PCMCIA_MEM_32}, 326 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 327 PCCBB_PCMCIA_MEM_32}, 328 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 329 PCCBB_PCMCIA_MEM_32}, 330 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 331 PCCBB_PCMCIA_MEM_32}, 332 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 333 PCCBB_PCMCIA_MEM_32}, 334 335 /* Toshiba products */ 336 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 337 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 338 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 339 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 340 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 341 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 342 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 343 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 344 345 /* Cirrus Logic products */ 346 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 347 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 348 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 349 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 350 351 /* O2 Micro products */ 352 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6729), 353 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 354 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6730), 355 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 356 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6832), 357 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 358 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6836), 359 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 360 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6872), 361 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 362 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6922), 363 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 364 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6933), 365 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 366 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6972), 367 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 368 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_7223), 369 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 370 371 /* sentinel, or Generic chip */ 372 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 373 }; 374 375 static int 376 cb_chipset(u_int32_t pci_id, int *flagp) 377 { 378 const struct yenta_chipinfo *yc; 379 380 /* Loop over except the last default entry. */ 381 for (yc = yc_chipsets; yc < yc_chipsets + 382 __arraycount(yc_chipsets) - 1; yc++) 383 if (pci_id == yc->yc_id) 384 break; 385 386 if (flagp != NULL) 387 *flagp = yc->yc_flags; 388 389 return (yc->yc_chiptype); 390 } 391 392 void 393 pccbbattach(device_t parent, device_t self, void *aux) 394 { 395 struct pccbb_softc *sc = device_private(self); 396 struct pci_attach_args *pa = aux; 397 pci_chipset_tag_t pc = pa->pa_pc; 398 pcireg_t busreg, reg, sock_base; 399 bus_addr_t sockbase; 400 char devinfo[256]; 401 int flags; 402 403 #ifdef __HAVE_PCCBB_ATTACH_HOOK 404 pccbb_attach_hook(parent, self, pa); 405 #endif 406 407 sc->sc_dev = self; 408 409 callout_init(&sc->sc_insert_ch, 0); 410 callout_setfunc(&sc->sc_insert_ch, pci113x_insert, sc); 411 412 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 413 414 aprint_naive("\n"); 415 416 pci_devinfo(pa->pa_id, 0, 0, devinfo, sizeof(devinfo)); 417 aprint_normal(": %s (rev. 0x%02x)", devinfo, 418 PCI_REVISION(pa->pa_class)); 419 DPRINTF((" (chipflags %x)", flags)); 420 aprint_normal("\n"); 421 422 TAILQ_INIT(&sc->sc_memwindow); 423 TAILQ_INIT(&sc->sc_iowindow); 424 425 #if rbus 426 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 427 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 428 429 #if 0 430 printf("pa->pa_memt: %08x vs rbus_mem->rb_bt: %08x\n", 431 pa->pa_memt, sc->sc_rbus_memt->rb_bt); 432 #endif 433 #endif /* rbus */ 434 435 sc->sc_flags &= ~CBB_MEMHMAPPED; 436 437 /* 438 * MAP socket registers and ExCA registers on memory-space 439 * When no valid address is set on socket base registers (on pci 440 * config space), get it not polite way. 441 */ 442 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 443 444 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 445 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 446 /* The address must be valid. */ 447 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 448 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, &sc->sc_base_size)) { 449 aprint_error_dev(self, 450 "can't map socket base address 0x%lx\n", 451 (unsigned long)sock_base); 452 /* 453 * I think it's funny: socket base registers must be 454 * mapped on memory space, but ... 455 */ 456 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 457 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 458 &sc->sc_base_size)) { 459 aprint_error_dev(self, 460 "can't map socket base address" 461 " 0x%lx: io mode\n", 462 (unsigned long)sockbase); 463 /* give up... allocate reg space via rbus. */ 464 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 465 } else 466 sc->sc_flags |= CBB_MEMHMAPPED; 467 } else { 468 DPRINTF(("%s: socket base address 0x%lx\n", 469 device_xname(self), 470 (unsigned long)sockbase)); 471 sc->sc_flags |= CBB_MEMHMAPPED; 472 } 473 } 474 475 sc->sc_mem_start = 0; /* XXX */ 476 sc->sc_mem_end = 0xffffffff; /* XXX */ 477 478 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 479 480 /* pccbb_machdep.c end */ 481 482 #if defined CBB_DEBUG 483 { 484 static const char *intrname[] = { "NON", "A", "B", "C", "D" }; 485 aprint_debug_dev(self, "intrpin %s, intrtag %d\n", 486 intrname[pa->pa_intrpin], pa->pa_intrline); 487 } 488 #endif 489 490 /* setup softc */ 491 sc->sc_pc = pc; 492 sc->sc_iot = pa->pa_iot; 493 sc->sc_memt = pa->pa_memt; 494 sc->sc_dmat = pa->pa_dmat; 495 sc->sc_tag = pa->pa_tag; 496 497 memcpy(&sc->sc_pa, pa, sizeof(*pa)); 498 499 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 500 501 /* Disable legacy register mapping. */ 502 switch (sc->sc_chipset) { 503 case CB_RX5C46X: /* fallthrough */ 504 #if 0 505 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 506 case CB_RX5C47X: 507 #endif 508 /* 509 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 510 * cannot be disabled by substituting 0 into PCI_LEGACY 511 * register. Ricoh CardBus bridges have special bits on Bridge 512 * control reg (addr 0x3e on PCI config space). 513 */ 514 reg = pci_conf_read(pc, pa->pa_tag, PCI_BRIDGE_CONTROL_REG); 515 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 516 pci_conf_write(pc, pa->pa_tag, PCI_BRIDGE_CONTROL_REG, reg); 517 break; 518 519 default: 520 /* XXX I don't know proper way to kill legacy I/O. */ 521 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 522 break; 523 } 524 525 if (!pmf_device_register(self, pccbb_suspend, pccbb_resume)) 526 aprint_error_dev(self, "couldn't establish power handler\n"); 527 528 config_defer(self, pccbb_pci_callback); 529 } 530 531 int 532 pccbbdetach(device_t self, int flags) 533 { 534 struct pccbb_softc *sc = device_private(self); 535 pci_chipset_tag_t pc = sc->sc_pa.pa_pc; 536 bus_space_tag_t bmt = sc->sc_base_memt; 537 bus_space_handle_t bmh = sc->sc_base_memh; 538 uint32_t sockmask; 539 int rc; 540 541 if ((rc = config_detach_children(self, flags)) != 0) 542 return rc; 543 544 if (!LIST_EMPTY(&sc->sc_pil)) { 545 panic("%s: interrupt handlers still registered", 546 device_xname(self)); 547 return EBUSY; 548 } 549 550 if (sc->sc_ih != NULL) { 551 pci_intr_disestablish(pc, sc->sc_ih); 552 sc->sc_ih = NULL; 553 } 554 555 /* CSC Interrupt: turn off card detect and power cycle interrupts */ 556 sockmask = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 557 sockmask &= ~(CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | 558 CB_SOCKET_MASK_POWER); 559 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, sockmask); 560 /* reset interrupt */ 561 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 562 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 563 564 switch (sc->sc_flags & (CBB_MEMHMAPPED|CBB_SPECMAPPED)) { 565 case CBB_MEMHMAPPED: 566 bus_space_unmap(bmt, bmh, sc->sc_base_size); 567 break; 568 case CBB_MEMHMAPPED|CBB_SPECMAPPED: 569 #if rbus 570 { 571 pcireg_t sockbase; 572 573 sockbase = pci_conf_read(pc, sc->sc_tag, PCI_SOCKBASE); 574 rbus_space_free(sc->sc_rbus_memt, bmh, 0x1000, 575 NULL); 576 } 577 #else 578 bus_space_free(bmt, bmh, 0x1000); 579 #endif 580 } 581 sc->sc_flags &= ~(CBB_MEMHMAPPED|CBB_SPECMAPPED); 582 583 if (!TAILQ_EMPTY(&sc->sc_iowindow)) 584 aprint_error_dev(self, "i/o windows not empty"); 585 if (!TAILQ_EMPTY(&sc->sc_memwindow)) 586 aprint_error_dev(self, "memory windows not empty"); 587 588 callout_stop(&sc->sc_insert_ch); 589 callout_destroy(&sc->sc_insert_ch); 590 return 0; 591 } 592 593 /* 594 * static void pccbb_pci_callback(device_t self) 595 * 596 * The actual attach routine: get memory space for YENTA register 597 * space, setup YENTA register and route interrupt. 598 * 599 * This function should be deferred because this device may obtain 600 * memory space dynamically. This function must avoid obtaining 601 * memory area which has already kept for another device. 602 */ 603 static void 604 pccbb_pci_callback(device_t self) 605 { 606 struct pccbb_softc *sc = device_private(self); 607 pci_chipset_tag_t pc = sc->sc_pc; 608 bus_addr_t sockbase; 609 struct cbslot_attach_args cba; 610 struct pcmciabus_attach_args paa; 611 struct cardslot_attach_args caa; 612 device_t csc; 613 614 if (!(sc->sc_flags & CBB_MEMHMAPPED)) { 615 /* The socket registers aren't mapped correctly. */ 616 #if rbus 617 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 618 (sc->sc_chipset == CB_RX5C47X 619 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 620 0, &sockbase, &sc->sc_base_memh)) { 621 return; 622 } 623 sc->sc_base_memt = sc->sc_memt; 624 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 625 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 626 device_xname(self), (unsigned long)sockbase, 627 (unsigned long)pci_conf_read(pc, sc->sc_tag, 628 PCI_SOCKBASE))); 629 #else 630 sc->sc_base_memt = sc->sc_memt; 631 #if !defined CBB_PCI_BASE 632 #define CBB_PCI_BASE 0x20000000 633 #endif 634 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 635 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 636 /* cannot allocate memory space */ 637 return; 638 } 639 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 640 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 641 device_xname(self), (unsigned long)sock_base, 642 (unsigned long)pci_conf_read(pc, 643 sc->sc_tag, PCI_SOCKBASE))); 644 #endif 645 sc->sc_flags |= CBB_MEMHMAPPED; 646 } 647 648 /* clear data structure for child device interrupt handlers */ 649 LIST_INIT(&sc->sc_pil); 650 651 /* bus bridge initialization */ 652 pccbb_chipinit(sc); 653 654 sc->sc_pil_intr_enable = 1; 655 656 { 657 u_int32_t sockstat; 658 659 sockstat = bus_space_read_4(sc->sc_base_memt, 660 sc->sc_base_memh, CB_SOCKET_STAT); 661 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 662 sc->sc_flags |= CBB_CARDEXIST; 663 } 664 } 665 666 /* 667 * attach cardbus 668 */ 669 { 670 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 671 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 672 673 /* initialize cbslot_attach */ 674 cba.cba_iot = sc->sc_iot; 675 cba.cba_memt = sc->sc_memt; 676 cba.cba_dmat = sc->sc_dmat; 677 cba.cba_bus = (busreg >> 8) & 0x0ff; 678 cba.cba_cc = (void *)sc; 679 cba.cba_cf = &pccbb_funcs; 680 cba.cba_intrline = 0; /* XXX dummy */ 681 682 #if rbus 683 cba.cba_rbus_iot = sc->sc_rbus_iot; 684 cba.cba_rbus_memt = sc->sc_rbus_memt; 685 #endif 686 687 cba.cba_cacheline = PCI_CACHELINE(bhlc); 688 cba.cba_max_lattimer = PCI_LATTIMER(bhlc); 689 690 aprint_verbose_dev(self, 691 "cacheline 0x%x lattimer 0x%x\n", 692 cba.cba_cacheline, 693 cba.cba_max_lattimer); 694 aprint_verbose_dev(self, "bhlc 0x%x\n", bhlc); 695 #if defined SHOW_REGS 696 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 697 sc->sc_base_memh); 698 #endif 699 } 700 701 pccbb_pcmcia_attach_setup(sc, &paa); 702 caa.caa_cb_attach = NULL; 703 if (cba.cba_bus == 0) 704 aprint_error_dev(self, 705 "secondary bus number uninitialized; try PCI_BUS_FIXUP\n"); 706 else 707 caa.caa_cb_attach = &cba; 708 caa.caa_16_attach = &paa; 709 710 pccbb_intrinit(sc); 711 712 if (NULL != (csc = config_found_ia(self, "pcmciaslot", &caa, 713 cbbprint))) { 714 DPRINTF(("%s: found cardslot\n", __func__)); 715 sc->sc_csc = device_private(csc); 716 } 717 718 return; 719 } 720 721 722 723 724 725 /* 726 * static void pccbb_chipinit(struct pccbb_softc *sc) 727 * 728 * This function initialize YENTA chip registers listed below: 729 * 1) PCI command reg, 730 * 2) PCI and CardBus latency timer, 731 * 3) route PCI interrupt, 732 * 4) close all memory and io windows. 733 * 5) turn off bus power. 734 * 6) card detect and power cycle interrupts on. 735 * 7) clear interrupt 736 */ 737 static void 738 pccbb_chipinit(struct pccbb_softc *sc) 739 { 740 pci_chipset_tag_t pc = sc->sc_pc; 741 pcitag_t tag = sc->sc_tag; 742 bus_space_tag_t bmt = sc->sc_base_memt; 743 bus_space_handle_t bmh = sc->sc_base_memh; 744 pcireg_t bcr, bhlc, cbctl, csr, lscp, mfunc, mrburst, slotctl, sockctl, 745 sysctrl; 746 747 /* 748 * Set PCI command reg. 749 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 750 */ 751 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 752 /* I believe it is harmless. */ 753 csr |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 754 PCI_COMMAND_MASTER_ENABLE); 755 756 /* All O2 Micro chips have broken parity-error reporting 757 * until proven otherwise. The OZ6933 PCI-CardBus Bridge 758 * is known to have the defect---see PR kern/38698. 759 */ 760 if (sc->sc_chipset != CB_O2MICRO) 761 csr |= PCI_COMMAND_PARITY_ENABLE; 762 763 csr |= PCI_COMMAND_SERR_ENABLE; 764 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 765 766 /* 767 * Set CardBus latency timer. 768 */ 769 lscp = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 770 if (PCI_CB_LATENCY(lscp) < 0x20) { 771 lscp &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 772 lscp |= (0x20 << PCI_CB_LATENCY_SHIFT); 773 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, lscp); 774 } 775 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 776 PCI_CB_LATENCY(lscp), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 777 778 /* 779 * Set PCI latency timer. 780 */ 781 bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG); 782 if (PCI_LATTIMER(bhlc) < 0x10) { 783 bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 784 bhlc |= (0x10 << PCI_LATTIMER_SHIFT); 785 pci_conf_write(pc, tag, PCI_BHLC_REG, bhlc); 786 } 787 DPRINTF(("PCI latency timer 0x%x (%x)\n", 788 PCI_LATTIMER(bhlc), pci_conf_read(pc, tag, PCI_BHLC_REG))); 789 790 791 /* Route functional interrupts to PCI. */ 792 bcr = pci_conf_read(pc, tag, PCI_BRIDGE_CONTROL_REG); 793 bcr |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 794 bcr |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 795 /* assert reset */ 796 bcr |= PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT; 797 /* Set master abort mode to 1, forward SERR# from secondary 798 * to primary, and detect parity errors on secondary. 799 */ 800 bcr |= PCI_BRIDGE_CONTROL_MABRT << PCI_BRIDGE_CONTROL_SHIFT; 801 bcr |= PCI_BRIDGE_CONTROL_SERR << PCI_BRIDGE_CONTROL_SHIFT; 802 bcr |= PCI_BRIDGE_CONTROL_PERE << PCI_BRIDGE_CONTROL_SHIFT; 803 pci_conf_write(pc, tag, PCI_BRIDGE_CONTROL_REG, bcr); 804 805 switch (sc->sc_chipset) { 806 case CB_TI113X: 807 cbctl = pci_conf_read(pc, tag, PCI_CBCTRL); 808 /* This bit is shared, but may read as 0 on some chips, so set 809 it explicitly on both functions. */ 810 cbctl |= PCI113X_CBCTRL_PCI_IRQ_ENA; 811 /* CSC intr enable */ 812 cbctl |= PCI113X_CBCTRL_PCI_CSC; 813 /* functional intr prohibit | prohibit ISA routing */ 814 cbctl &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 815 pci_conf_write(pc, tag, PCI_CBCTRL, cbctl); 816 break; 817 818 case CB_TI1420: 819 sysctrl = pci_conf_read(pc, tag, PCI_SYSCTRL); 820 mrburst = pccbb_burstup 821 ? PCI1420_SYSCTRL_MRBURST : PCI1420_SYSCTRL_MRBURSTDN; 822 if ((sysctrl & PCI1420_SYSCTRL_MRBURST) == mrburst) { 823 printf("%s: %swrite bursts enabled\n", 824 device_xname(sc->sc_dev), 825 pccbb_burstup ? "read/" : ""); 826 } else if (pccbb_burstup) { 827 printf("%s: enabling read/write bursts\n", 828 device_xname(sc->sc_dev)); 829 sysctrl |= PCI1420_SYSCTRL_MRBURST; 830 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 831 } else { 832 printf("%s: disabling read bursts, " 833 "enabling write bursts\n", 834 device_xname(sc->sc_dev)); 835 sysctrl |= PCI1420_SYSCTRL_MRBURSTDN; 836 sysctrl &= ~PCI1420_SYSCTRL_MRBURSTUP; 837 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 838 } 839 /*FALLTHROUGH*/ 840 case CB_TI12XX: 841 /* 842 * Some TI 12xx (and [14][45]xx) based pci cards 843 * sometimes have issues with the MFUNC register not 844 * being initialized due to a bad EEPROM on board. 845 * Laptops that this matters on have this register 846 * properly initialized. 847 * 848 * The TI125X parts have a different register. 849 */ 850 mfunc = pci_conf_read(pc, tag, PCI12XX_MFUNC); 851 if (mfunc == 0) { 852 mfunc &= ~PCI12XX_MFUNC_PIN0; 853 mfunc |= PCI12XX_MFUNC_PIN0_INTA; 854 if ((pci_conf_read(pc, tag, PCI_SYSCTRL) & 855 PCI12XX_SYSCTRL_INTRTIE) == 0) { 856 mfunc &= ~PCI12XX_MFUNC_PIN1; 857 mfunc |= PCI12XX_MFUNC_PIN1_INTB; 858 } 859 pci_conf_write(pc, tag, PCI12XX_MFUNC, mfunc); 860 } 861 /* fallthrough */ 862 863 case CB_TI125X: 864 /* 865 * Disable zoom video. Some machines initialize this 866 * improperly and experience has shown that this helps 867 * prevent strange behavior. 868 */ 869 pci_conf_write(pc, tag, PCI12XX_MMCTRL, 0); 870 871 sysctrl = pci_conf_read(pc, tag, PCI_SYSCTRL); 872 sysctrl |= PCI12XX_SYSCTRL_VCCPROT; 873 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 874 cbctl = pci_conf_read(pc, tag, PCI_CBCTRL); 875 cbctl |= PCI12XX_CBCTRL_CSC; 876 pci_conf_write(pc, tag, PCI_CBCTRL, cbctl); 877 break; 878 879 case CB_TOPIC95B: 880 sockctl = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 881 sockctl |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 882 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, sockctl); 883 slotctl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 884 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 885 device_xname(sc->sc_dev), slotctl)); 886 slotctl |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 887 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 888 slotctl &= ~TOPIC_SLOT_CTRL_SWDETECT; 889 DPRINTF(("0x%x\n", slotctl)); 890 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slotctl); 891 break; 892 893 case CB_TOPIC97: 894 slotctl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 895 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 896 device_xname(sc->sc_dev), slotctl)); 897 slotctl |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 898 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 899 slotctl &= ~TOPIC_SLOT_CTRL_SWDETECT; 900 slotctl |= TOPIC97_SLOT_CTRL_PCIINT; 901 slotctl &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 902 DPRINTF(("0x%x\n", slotctl)); 903 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slotctl); 904 /* make sure to assert LV card support bits */ 905 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 906 0x800 + 0x3e, 907 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 908 0x800 + 0x3e) | 0x03); 909 break; 910 } 911 912 /* Close all memory and I/O windows. */ 913 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 914 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 915 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 916 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 917 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 918 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 919 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 920 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 921 922 /* reset 16-bit pcmcia bus */ 923 bus_space_write_1(bmt, bmh, 0x800 + PCIC_INTR, 924 bus_space_read_1(bmt, bmh, 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 925 926 /* turn off power */ 927 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 928 } 929 930 static void 931 pccbb_intrinit(struct pccbb_softc *sc) 932 { 933 pcireg_t sockmask; 934 const char *intrstr = NULL; 935 pci_intr_handle_t ih; 936 pci_chipset_tag_t pc = sc->sc_pc; 937 bus_space_tag_t bmt = sc->sc_base_memt; 938 bus_space_handle_t bmh = sc->sc_base_memh; 939 940 /* Map and establish the interrupt. */ 941 if (pci_intr_map(&sc->sc_pa, &ih)) { 942 aprint_error_dev(sc->sc_dev, "couldn't map interrupt\n"); 943 return; 944 } 945 intrstr = pci_intr_string(pc, ih); 946 947 /* 948 * XXX pccbbintr should be called under the priority lower 949 * than any other hard interrupts. 950 */ 951 KASSERT(sc->sc_ih == NULL); 952 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 953 954 if (sc->sc_ih == NULL) { 955 aprint_error_dev(sc->sc_dev, "couldn't establish interrupt"); 956 if (intrstr != NULL) 957 aprint_error(" at %s\n", intrstr); 958 else 959 aprint_error("\n"); 960 return; 961 } 962 963 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 964 965 /* CSC Interrupt: Card detect and power cycle interrupts on */ 966 sockmask = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 967 sockmask |= CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | 968 CB_SOCKET_MASK_POWER; 969 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, sockmask); 970 /* reset interrupt */ 971 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 972 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 973 } 974 975 /* 976 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 977 * struct pcmciabus_attach_args *paa) 978 * 979 * This function attaches 16-bit PCcard bus. 980 */ 981 STATIC void 982 pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 983 struct pcmciabus_attach_args *paa) 984 { 985 #if rbus 986 rbus_tag_t rb; 987 #endif 988 /* 989 * We need to do a few things here: 990 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 991 * setting the IRQ numbers to 0. 992 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 993 * routing of CSC interrupts (e.g. card removal) to PCI while in 994 * PCMCIA mode. We just leave this set all the time. 995 * 3) Enable card insertion/removal interrupts in case the chip also 996 * needs that while in PCMCIA mode. 997 * 4) Clear any pending CSC interrupt. 998 */ 999 Pcic_write(sc, PCIC_INTR, PCIC_INTR_ENABLE); 1000 if (sc->sc_chipset == CB_TI113X) { 1001 Pcic_write(sc, PCIC_CSC_INTR, 0); 1002 } else { 1003 Pcic_write(sc, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 1004 Pcic_read(sc, PCIC_CSC); 1005 } 1006 1007 /* initialize pcmcia bus attachment */ 1008 paa->paa_busname = "pcmcia"; 1009 paa->pct = &pccbb_pcmcia_funcs; 1010 paa->pch = sc; 1011 paa->iobase = 0; /* I don't use them */ 1012 paa->iosize = 0; 1013 #if rbus 1014 rb = sc->sc_rbus_iot; 1015 paa->iobase = rb->rb_start + rb->rb_offset; 1016 paa->iosize = rb->rb_end - rb->rb_start; 1017 #endif 1018 1019 return; 1020 } 1021 1022 /* 1023 * int pccbbintr(arg) 1024 * void *arg; 1025 * This routine handles the interrupt from Yenta PCI-CardBus bridge 1026 * itself. 1027 */ 1028 int 1029 pccbbintr(void *arg) 1030 { 1031 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1032 u_int32_t sockevent, sockstate; 1033 bus_space_tag_t memt = sc->sc_base_memt; 1034 bus_space_handle_t memh = sc->sc_base_memh; 1035 1036 if (!device_has_power(sc->sc_dev)) 1037 return 0; 1038 1039 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 1040 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 1041 Pcic_read(sc, PCIC_CSC); 1042 1043 if (sockevent != 0) { 1044 aprint_debug("%s: enter sockevent %" PRIx32 "\n", __func__, 1045 sockevent); 1046 } 1047 1048 /* XXX sockevent == CB_SOCKET_EVENT_CSTS|CB_SOCKET_EVENT_POWER 1049 * does occur in the wild. Check for a _POWER event before 1050 * possibly exiting because of an _CSTS event. 1051 */ 1052 if (sockevent & CB_SOCKET_EVENT_POWER) { 1053 DPRINTF(("Powercycling because of socket event\n")); 1054 /* XXX: Does not happen when attaching a 16-bit card */ 1055 sc->sc_pwrcycle++; 1056 wakeup(&sc->sc_pwrcycle); 1057 } 1058 1059 /* Sometimes a change of CSTSCHG# accompanies the first 1060 * interrupt from an Atheros WLAN. That generates a 1061 * CB_SOCKET_EVENT_CSTS event on the bridge. The event 1062 * isn't interesting to pccbb(4), so we used to ignore the 1063 * interrupt. Now, let the child devices try to handle 1064 * the interrupt, instead. The Atheros NIC produces 1065 * interrupts more reliably, now: used to be that it would 1066 * only interrupt if the driver avoided powering down the 1067 * NIC's cardslot, and then the NIC would only work after 1068 * it was reset a second time. 1069 */ 1070 if (sockevent == 0 || 1071 (sockevent & ~(CB_SOCKET_EVENT_POWER|CB_SOCKET_EVENT_CD)) != 0) { 1072 /* This intr is not for me: it may be for my child devices. */ 1073 if (sc->sc_pil_intr_enable) { 1074 return pccbbintr_function(sc); 1075 } else { 1076 return 0; 1077 } 1078 } 1079 1080 if (sockevent & CB_SOCKET_EVENT_CD) { 1081 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1082 if (0x00 != (sockstate & CB_SOCKET_STAT_CD)) { 1083 /* A card should be removed. */ 1084 if (sc->sc_flags & CBB_CARDEXIST) { 1085 DPRINTF(("%s: 0x%08x", 1086 device_xname(sc->sc_dev), sockevent)); 1087 DPRINTF((" card removed, 0x%08x\n", sockstate)); 1088 sc->sc_flags &= ~CBB_CARDEXIST; 1089 if (sc->sc_csc->sc_status & 1090 CARDSLOT_STATUS_CARD_16) { 1091 cardslot_event_throw(sc->sc_csc, 1092 CARDSLOT_EVENT_REMOVAL_16); 1093 } else if (sc->sc_csc->sc_status & 1094 CARDSLOT_STATUS_CARD_CB) { 1095 /* Cardbus intr removed */ 1096 cardslot_event_throw(sc->sc_csc, 1097 CARDSLOT_EVENT_REMOVAL_CB); 1098 } 1099 } else if (sc->sc_flags & CBB_INSERTING) { 1100 sc->sc_flags &= ~CBB_INSERTING; 1101 callout_stop(&sc->sc_insert_ch); 1102 } 1103 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 1104 /* 1105 * The pccbbintr may called from powerdown hook when 1106 * the system resumed, to detect the card 1107 * insertion/removal during suspension. 1108 */ 1109 (sc->sc_flags & CBB_CARDEXIST) == 0) { 1110 if (sc->sc_flags & CBB_INSERTING) { 1111 callout_stop(&sc->sc_insert_ch); 1112 } 1113 callout_schedule(&sc->sc_insert_ch, hz / 5); 1114 sc->sc_flags |= CBB_INSERTING; 1115 } 1116 } 1117 1118 return (1); 1119 } 1120 1121 /* 1122 * static int pccbbintr_function(struct pccbb_softc *sc) 1123 * 1124 * This function calls each interrupt handler registered at the 1125 * bridge. The interrupt handlers are called in registered order. 1126 */ 1127 static int 1128 pccbbintr_function(struct pccbb_softc *sc) 1129 { 1130 int retval = 0, val; 1131 struct pccbb_intrhand_list *pil; 1132 int s; 1133 1134 LIST_FOREACH(pil, &sc->sc_pil, pil_next) { 1135 s = splraiseipl(pil->pil_icookie); 1136 val = (*pil->pil_func)(pil->pil_arg); 1137 splx(s); 1138 1139 retval = retval == 1 ? 1 : 1140 retval == 0 ? val : val != 0 ? val : retval; 1141 } 1142 1143 return retval; 1144 } 1145 1146 static void 1147 pci113x_insert(void *arg) 1148 { 1149 struct pccbb_softc *sc = arg; 1150 u_int32_t sockevent, sockstate; 1151 1152 if (!(sc->sc_flags & CBB_INSERTING)) { 1153 /* We add a card only under inserting state. */ 1154 return; 1155 } 1156 sc->sc_flags &= ~CBB_INSERTING; 1157 1158 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1159 CB_SOCKET_EVENT); 1160 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1161 CB_SOCKET_STAT); 1162 1163 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1164 DPRINTF(("%s: 0x%08x", device_xname(sc->sc_dev), sockevent)); 1165 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1166 sc->sc_flags |= CBB_CARDEXIST; 1167 /* call pccard interrupt handler here */ 1168 if (sockstate & CB_SOCKET_STAT_16BIT) { 1169 /* 16-bit card found */ 1170 cardslot_event_throw(sc->sc_csc, 1171 CARDSLOT_EVENT_INSERTION_16); 1172 } else if (sockstate & CB_SOCKET_STAT_CB) { 1173 /* cardbus card found */ 1174 cardslot_event_throw(sc->sc_csc, 1175 CARDSLOT_EVENT_INSERTION_CB); 1176 } else { 1177 /* who are you? */ 1178 } 1179 } else { 1180 callout_schedule(&sc->sc_insert_ch, hz / 10); 1181 } 1182 } 1183 1184 #define PCCBB_PCMCIA_OFFSET 0x800 1185 static u_int8_t 1186 pccbb_pcmcia_read(struct pccbb_softc *sc, int reg) 1187 { 1188 bus_space_barrier(sc->sc_base_memt, sc->sc_base_memh, 1189 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1190 1191 return bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 1192 PCCBB_PCMCIA_OFFSET + reg); 1193 } 1194 1195 static void 1196 pccbb_pcmcia_write(struct pccbb_softc *sc, int reg, u_int8_t val) 1197 { 1198 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 1199 PCCBB_PCMCIA_OFFSET + reg, val); 1200 1201 bus_space_barrier(sc->sc_base_memt, sc->sc_base_memh, 1202 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1203 } 1204 1205 /* 1206 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1207 */ 1208 STATIC int 1209 pccbb_ctrl(cardbus_chipset_tag_t ct, int command) 1210 { 1211 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1212 1213 switch (command) { 1214 case CARDBUS_CD: 1215 if (2 == pccbb_detect_card(sc)) { 1216 int retval = 0; 1217 int status = cb_detect_voltage(sc); 1218 if (PCCARD_VCC_5V & status) { 1219 retval |= CARDBUS_5V_CARD; 1220 } 1221 if (PCCARD_VCC_3V & status) { 1222 retval |= CARDBUS_3V_CARD; 1223 } 1224 if (PCCARD_VCC_XV & status) { 1225 retval |= CARDBUS_XV_CARD; 1226 } 1227 if (PCCARD_VCC_YV & status) { 1228 retval |= CARDBUS_YV_CARD; 1229 } 1230 return retval; 1231 } else { 1232 return 0; 1233 } 1234 case CARDBUS_RESET: 1235 return cb_reset(sc); 1236 case CARDBUS_IO_ENABLE: /* fallthrough */ 1237 case CARDBUS_IO_DISABLE: /* fallthrough */ 1238 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1239 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1240 case CARDBUS_BM_ENABLE: /* fallthrough */ 1241 case CARDBUS_BM_DISABLE: /* fallthrough */ 1242 /* XXX: I think we don't need to call this function below. */ 1243 return pccbb_cardenable(sc, command); 1244 } 1245 1246 return 0; 1247 } 1248 1249 STATIC int 1250 pccbb_power_ct(cardbus_chipset_tag_t ct, int command) 1251 { 1252 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1253 1254 return pccbb_power(sc, command); 1255 } 1256 1257 /* 1258 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1259 * This function returns true when it succeeds and returns false when 1260 * it fails. 1261 */ 1262 STATIC int 1263 pccbb_power(struct pccbb_softc *sc, int command) 1264 { 1265 u_int32_t status, osock_ctrl, sock_ctrl, reg_ctrl; 1266 bus_space_tag_t memt = sc->sc_base_memt; 1267 bus_space_handle_t memh = sc->sc_base_memh; 1268 int on = 0, pwrcycle, s, times; 1269 struct timeval before, after, diff; 1270 1271 DPRINTF(("pccbb_power: %s and %s [0x%x]\n", 1272 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1273 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1274 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1275 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1276 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1277 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1278 "UNKNOWN", 1279 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1280 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1281 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1282 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1283 "UNKNOWN", command)); 1284 1285 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1286 osock_ctrl = sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1287 1288 switch (command & CARDBUS_VCCMASK) { 1289 case CARDBUS_VCC_UC: 1290 break; 1291 case CARDBUS_VCC_5V: 1292 on++; 1293 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1294 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1295 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1296 } else { 1297 aprint_error_dev(sc->sc_dev, 1298 "BAD voltage request: no 5 V card\n"); 1299 return 0; 1300 } 1301 break; 1302 case CARDBUS_VCC_3V: 1303 on++; 1304 if (CB_SOCKET_STAT_3VCARD & status) { 1305 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1306 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1307 } else { 1308 aprint_error_dev(sc->sc_dev, 1309 "BAD voltage request: no 3.3 V card\n"); 1310 return 0; 1311 } 1312 break; 1313 case CARDBUS_VCC_0V: 1314 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1315 break; 1316 default: 1317 return 0; /* power NEVER changed */ 1318 } 1319 1320 switch (command & CARDBUS_VPPMASK) { 1321 case CARDBUS_VPP_UC: 1322 break; 1323 case CARDBUS_VPP_0V: 1324 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1325 break; 1326 case CARDBUS_VPP_VCC: 1327 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1328 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1329 break; 1330 case CARDBUS_VPP_12V: 1331 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1332 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1333 break; 1334 } 1335 1336 pwrcycle = sc->sc_pwrcycle; 1337 aprint_debug_dev(sc->sc_dev, "osock_ctrl %#" PRIx32 1338 " sock_ctrl %#" PRIx32 "\n", osock_ctrl, sock_ctrl); 1339 1340 microtime(&before); 1341 s = splbio(); 1342 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1343 1344 /* 1345 * Wait as long as 200ms for a power-cycle interrupt. If 1346 * interrupts are enabled, but the socket has already 1347 * changed to the desired status, keep waiting for the 1348 * interrupt. "Consuming" the interrupt in this way keeps 1349 * the interrupt from prematurely waking some subsequent 1350 * pccbb_power call. 1351 * 1352 * XXX Not every bridge interrupts on the ->OFF transition. 1353 * XXX That's ok, we will time-out after 200ms. 1354 * 1355 * XXX The power cycle event will never happen when attaching 1356 * XXX a 16-bit card. That's ok, we will time-out after 1357 * XXX 200ms. 1358 */ 1359 for (times = 5; --times >= 0; ) { 1360 if (cold) 1361 DELAY(40 * 1000); 1362 else { 1363 (void)tsleep(&sc->sc_pwrcycle, PWAIT, "pccpwr", 1364 hz / 25); 1365 if (pwrcycle == sc->sc_pwrcycle) 1366 continue; 1367 } 1368 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1369 if ((status & CB_SOCKET_STAT_PWRCYCLE) != 0 && on) 1370 break; 1371 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0 && !on) 1372 break; 1373 } 1374 splx(s); 1375 microtime(&after); 1376 timersub(&after, &before, &diff); 1377 aprint_debug_dev(sc->sc_dev, "wait took%s %lld.%06lds\n", 1378 (on && times < 0) ? " too long" : "", (long long)diff.tv_sec, 1379 (long)diff.tv_usec); 1380 1381 /* 1382 * Ok, wait a bit longer for things to settle. 1383 */ 1384 if (on && sc->sc_chipset == CB_TOPIC95B) 1385 delay_ms(100, sc); 1386 1387 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1388 1389 if (on && sc->sc_chipset != CB_TOPIC95B) { 1390 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0) 1391 aprint_error_dev(sc->sc_dev, "power on failed?\n"); 1392 } 1393 1394 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1395 aprint_error_dev(sc->sc_dev, 1396 "bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1397 sock_ctrl, status); 1398 aprint_error_dev(sc->sc_dev, "disabling socket\n"); 1399 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1400 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1401 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1402 status &= ~CB_SOCKET_STAT_BADVCC; 1403 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, status); 1404 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1405 CB_SOCKET_STAT)); 1406 return 0; 1407 } 1408 1409 if (sc->sc_chipset == CB_TOPIC97) { 1410 reg_ctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL); 1411 reg_ctrl &= ~TOPIC97_REG_CTRL_TESTMODE; 1412 if ((command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V) 1413 reg_ctrl &= ~TOPIC97_REG_CTRL_CLKRUN_ENA; 1414 else 1415 reg_ctrl |= TOPIC97_REG_CTRL_CLKRUN_ENA; 1416 pci_conf_write(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL, reg_ctrl); 1417 } 1418 1419 return 1; /* power changed correctly */ 1420 } 1421 1422 /* 1423 * static int pccbb_detect_card(struct pccbb_softc *sc) 1424 * return value: 0 if no card exists. 1425 * 1 if 16-bit card exists. 1426 * 2 if cardbus card exists. 1427 */ 1428 static int 1429 pccbb_detect_card(struct pccbb_softc *sc) 1430 { 1431 bus_space_handle_t base_memh = sc->sc_base_memh; 1432 bus_space_tag_t base_memt = sc->sc_base_memt; 1433 u_int32_t sockstat = 1434 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1435 int retval = 0; 1436 1437 /* CD1 and CD2 asserted */ 1438 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1439 /* card must be present */ 1440 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1441 /* NOTACARD DEASSERTED */ 1442 if (CB_SOCKET_STAT_CB & sockstat) { 1443 /* CardBus mode */ 1444 retval = 2; 1445 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1446 /* 16-bit mode */ 1447 retval = 1; 1448 } 1449 } 1450 } 1451 return retval; 1452 } 1453 1454 /* 1455 * STATIC int cb_reset(struct pccbb_softc *sc) 1456 * This function resets CardBus card. 1457 */ 1458 STATIC int 1459 cb_reset(struct pccbb_softc *sc) 1460 { 1461 /* 1462 * Reset Assert at least 20 ms 1463 * Some machines request longer duration. 1464 */ 1465 int reset_duration = 1466 (sc->sc_chipset == CB_RX5C47X ? 400 : 50); 1467 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1468 aprint_debug("%s: enter bcr %" PRIx32 "\n", __func__, bcr); 1469 1470 /* Reset bit Assert (bit 6 at 0x3E) */ 1471 bcr |= PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT; 1472 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr); 1473 aprint_debug("%s: wrote bcr %" PRIx32 "\n", __func__, bcr); 1474 delay_ms(reset_duration, sc); 1475 1476 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1477 /* Reset bit Deassert (bit 6 at 0x3E) */ 1478 bcr &= ~(PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT); 1479 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, 1480 bcr); 1481 aprint_debug("%s: wrote bcr %" PRIx32 "\n", __func__, bcr); 1482 delay_ms(reset_duration, sc); 1483 aprint_debug("%s: end of delay\n", __func__); 1484 } 1485 /* No card found on the slot. Keep Reset. */ 1486 return 1; 1487 } 1488 1489 /* 1490 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1491 * This function detect card Voltage. 1492 */ 1493 STATIC int 1494 cb_detect_voltage(struct pccbb_softc *sc) 1495 { 1496 u_int32_t psr; /* socket present-state reg */ 1497 bus_space_tag_t iot = sc->sc_base_memt; 1498 bus_space_handle_t ioh = sc->sc_base_memh; 1499 int vol = PCCARD_VCC_UKN; /* set 0 */ 1500 1501 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1502 1503 if (0x400u & psr) { 1504 vol |= PCCARD_VCC_5V; 1505 } 1506 if (0x800u & psr) { 1507 vol |= PCCARD_VCC_3V; 1508 } 1509 1510 return vol; 1511 } 1512 1513 STATIC int 1514 cbbprint(void *aux, const char *pcic) 1515 { 1516 #if 0 1517 struct cbslot_attach_args *cba = aux; 1518 1519 if (cba->cba_slot >= 0) { 1520 aprint_normal(" slot %d", cba->cba_slot); 1521 } 1522 #endif 1523 return UNCONF; 1524 } 1525 1526 /* 1527 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1528 * This function enables and disables the card 1529 */ 1530 STATIC int 1531 pccbb_cardenable(struct pccbb_softc *sc, int function) 1532 { 1533 u_int32_t command = 1534 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1535 1536 DPRINTF(("pccbb_cardenable:")); 1537 switch (function) { 1538 case CARDBUS_IO_ENABLE: 1539 command |= PCI_COMMAND_IO_ENABLE; 1540 break; 1541 case CARDBUS_IO_DISABLE: 1542 command &= ~PCI_COMMAND_IO_ENABLE; 1543 break; 1544 case CARDBUS_MEM_ENABLE: 1545 command |= PCI_COMMAND_MEM_ENABLE; 1546 break; 1547 case CARDBUS_MEM_DISABLE: 1548 command &= ~PCI_COMMAND_MEM_ENABLE; 1549 break; 1550 case CARDBUS_BM_ENABLE: 1551 command |= PCI_COMMAND_MASTER_ENABLE; 1552 break; 1553 case CARDBUS_BM_DISABLE: 1554 command &= ~PCI_COMMAND_MASTER_ENABLE; 1555 break; 1556 default: 1557 return 0; 1558 } 1559 1560 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1561 DPRINTF((" command reg 0x%x\n", command)); 1562 return 1; 1563 } 1564 1565 #if !rbus 1566 static int 1567 pccbb_io_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 1568 { 1569 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1570 int basereg; 1571 int limitreg; 1572 1573 if ((win < 0) || (win > 2)) { 1574 #if defined DIAGNOSTIC 1575 printf("cardbus_io_open: window out of range %d\n", win); 1576 #endif 1577 return 0; 1578 } 1579 1580 basereg = win * 8 + PCI_CB_IOBASE0; 1581 limitreg = win * 8 + PCI_CB_IOLIMIT0; 1582 1583 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1584 start, basereg, end, limitreg)); 1585 1586 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1587 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1588 return 1; 1589 } 1590 1591 /* 1592 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1593 */ 1594 static int 1595 pccbb_io_close(cardbus_chipset_tag_t ct, int win) 1596 { 1597 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1598 int basereg; 1599 int limitreg; 1600 1601 if ((win < 0) || (win > 2)) { 1602 #if defined DIAGNOSTIC 1603 printf("cardbus_io_close: window out of range %d\n", win); 1604 #endif 1605 return 0; 1606 } 1607 1608 basereg = win * 8 + PCI_CB_IOBASE0; 1609 limitreg = win * 8 + PCI_CB_IOLIMIT0; 1610 1611 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1612 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1613 return 1; 1614 } 1615 1616 static int 1617 pccbb_mem_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 1618 { 1619 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1620 int basereg; 1621 int limitreg; 1622 1623 if ((win < 0) || (win > 2)) { 1624 #if defined DIAGNOSTIC 1625 printf("cardbus_mem_open: window out of range %d\n", win); 1626 #endif 1627 return 0; 1628 } 1629 1630 basereg = win * 8 + PCI_CB_MEMBASE0; 1631 limitreg = win * 8 + PCI_CB_MEMLIMIT0; 1632 1633 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1634 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1635 return 1; 1636 } 1637 1638 static int 1639 pccbb_mem_close(cardbus_chipset_tag_t ct, int win) 1640 { 1641 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1642 int basereg; 1643 int limitreg; 1644 1645 if ((win < 0) || (win > 2)) { 1646 #if defined DIAGNOSTIC 1647 printf("cardbus_mem_close: window out of range %d\n", win); 1648 #endif 1649 return 0; 1650 } 1651 1652 basereg = win * 8 + PCI_CB_MEMBASE0; 1653 limitreg = win * 8 + PCI_CB_MEMLIMIT0; 1654 1655 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1656 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1657 return 1; 1658 } 1659 #endif 1660 1661 /* 1662 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1663 * int irq, 1664 * int level, 1665 * int (* func)(void *), 1666 * void *arg) 1667 * 1668 * This function registers an interrupt handler at the bridge, in 1669 * order not to call the interrupt handlers of child devices when 1670 * a card-deletion interrupt occurs. 1671 * 1672 * The arguments irq and level are not used. 1673 */ 1674 static void * 1675 pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, cardbus_intr_line_t irq, 1676 int level, int (*func)(void *), void *arg) 1677 { 1678 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1679 1680 return pccbb_intr_establish(sc, irq, level, func, arg); 1681 } 1682 1683 1684 /* 1685 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1686 * void *ih) 1687 * 1688 * This function removes an interrupt handler pointed by ih. 1689 */ 1690 static void 1691 pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih) 1692 { 1693 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1694 1695 pccbb_intr_disestablish(sc, ih); 1696 } 1697 1698 1699 void 1700 pccbb_intr_route(struct pccbb_softc *sc) 1701 { 1702 pcireg_t bcr, cbctrl; 1703 1704 /* initialize bridge intr routing */ 1705 bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1706 bcr &= ~CB_BCR_INTR_IREQ_ENABLE; 1707 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr); 1708 1709 switch (sc->sc_chipset) { 1710 case CB_TI113X: 1711 cbctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1712 /* functional intr enabled */ 1713 cbctrl |= PCI113X_CBCTRL_PCI_INTR; 1714 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, cbctrl); 1715 break; 1716 default: 1717 break; 1718 } 1719 } 1720 1721 /* 1722 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1723 * int irq, 1724 * int level, 1725 * int (* func)(void *), 1726 * void *arg) 1727 * 1728 * This function registers an interrupt handler at the bridge, in 1729 * order not to call the interrupt handlers of child devices when 1730 * a card-deletion interrupt occurs. 1731 * 1732 * The arguments irq is not used because pccbb selects intr vector. 1733 */ 1734 static void * 1735 pccbb_intr_establish(struct pccbb_softc *sc, cardbus_intr_line_t irq, 1736 int level, int (*func)(void *), void *arg) 1737 { 1738 struct pccbb_intrhand_list *pil, *newpil; 1739 1740 DPRINTF(("pccbb_intr_establish start. %p\n", LIST_FIRST(&sc->sc_pil))); 1741 1742 if (LIST_EMPTY(&sc->sc_pil)) { 1743 pccbb_intr_route(sc); 1744 } 1745 1746 /* 1747 * Allocate a room for interrupt handler structure. 1748 */ 1749 if (NULL == (newpil = 1750 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1751 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1752 return NULL; 1753 } 1754 1755 newpil->pil_func = func; 1756 newpil->pil_arg = arg; 1757 newpil->pil_icookie = makeiplcookie(level); 1758 1759 if (LIST_EMPTY(&sc->sc_pil)) { 1760 LIST_INSERT_HEAD(&sc->sc_pil, newpil, pil_next); 1761 } else { 1762 for (pil = LIST_FIRST(&sc->sc_pil); 1763 LIST_NEXT(pil, pil_next) != NULL; 1764 pil = LIST_NEXT(pil, pil_next)); 1765 LIST_INSERT_AFTER(pil, newpil, pil_next); 1766 } 1767 1768 DPRINTF(("pccbb_intr_establish add pil. %p\n", 1769 LIST_FIRST(&sc->sc_pil))); 1770 1771 return newpil; 1772 } 1773 1774 /* 1775 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1776 * void *ih) 1777 * 1778 * This function removes an interrupt handler pointed by ih. ih 1779 * should be the value returned by cardbus_intr_establish() or 1780 * NULL. 1781 * 1782 * When ih is NULL, this function will do nothing. 1783 */ 1784 static void 1785 pccbb_intr_disestablish(struct pccbb_softc *sc, void *ih) 1786 { 1787 struct pccbb_intrhand_list *pil; 1788 pcireg_t reg; 1789 1790 DPRINTF(("pccbb_intr_disestablish start. %p\n", 1791 LIST_FIRST(&sc->sc_pil))); 1792 1793 if (ih == NULL) { 1794 /* intr handler is not set */ 1795 DPRINTF(("pccbb_intr_disestablish: no ih\n")); 1796 return; 1797 } 1798 1799 #ifdef DIAGNOSTIC 1800 LIST_FOREACH(pil, &sc->sc_pil, pil_next) { 1801 DPRINTF(("pccbb_intr_disestablish: pil %p\n", pil)); 1802 if (pil == ih) { 1803 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1804 break; 1805 } 1806 } 1807 if (pil == NULL) { 1808 panic("pccbb_intr_disestablish: %s cannot find pil %p", 1809 device_xname(sc->sc_dev), ih); 1810 } 1811 #endif 1812 1813 pil = (struct pccbb_intrhand_list *)ih; 1814 LIST_REMOVE(pil, pil_next); 1815 free(pil, M_DEVBUF); 1816 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1817 1818 if (LIST_EMPTY(&sc->sc_pil)) { 1819 /* No interrupt handlers */ 1820 1821 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1822 1823 /* stop routing PCI intr */ 1824 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1825 reg |= CB_BCR_INTR_IREQ_ENABLE; 1826 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, reg); 1827 1828 switch (sc->sc_chipset) { 1829 case CB_TI113X: 1830 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1831 /* functional intr disabled */ 1832 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1833 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1834 break; 1835 default: 1836 break; 1837 } 1838 } 1839 } 1840 1841 #if defined SHOW_REGS 1842 static void 1843 cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, bus_space_tag_t memt, 1844 bus_space_handle_t memh) 1845 { 1846 int i; 1847 printf("PCI config regs:"); 1848 for (i = 0; i < 0x50; i += 4) { 1849 if (i % 16 == 0) 1850 printf("\n 0x%02x:", i); 1851 printf(" %08x", pci_conf_read(pc, tag, i)); 1852 } 1853 for (i = 0x80; i < 0xb0; i += 4) { 1854 if (i % 16 == 0) 1855 printf("\n 0x%02x:", i); 1856 printf(" %08x", pci_conf_read(pc, tag, i)); 1857 } 1858 1859 if (memh == 0) { 1860 printf("\n"); 1861 return; 1862 } 1863 1864 printf("\nsocket regs:"); 1865 for (i = 0; i <= 0x10; i += 0x04) 1866 printf(" %08x", bus_space_read_4(memt, memh, i)); 1867 printf("\nExCA regs:"); 1868 for (i = 0; i < 0x08; ++i) 1869 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1870 printf("\n"); 1871 return; 1872 } 1873 #endif 1874 1875 /* 1876 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1877 * int busno, int function) 1878 * This is the function to make a tag to access config space of 1879 * a CardBus Card. It works same as pci_conf_read. 1880 */ 1881 static cardbustag_t 1882 pccbb_make_tag(cardbus_chipset_tag_t cc, int busno, int function) 1883 { 1884 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1885 1886 return pci_make_tag(sc->sc_pc, busno, 0, function); 1887 } 1888 1889 static void 1890 pccbb_free_tag(cardbus_chipset_tag_t cc, cardbustag_t tag) 1891 { 1892 } 1893 1894 /* 1895 * pccbb_conf_read 1896 * 1897 * This is the function to read the config space of a CardBus card. 1898 * It works the same as pci_conf_read(9). 1899 */ 1900 static cardbusreg_t 1901 pccbb_conf_read(cardbus_chipset_tag_t cc, cardbustag_t tag, int offset) 1902 { 1903 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1904 pcitag_t brtag = sc->sc_tag; 1905 cardbusreg_t reg; 1906 1907 /* 1908 * clear cardbus master abort status; it is OK to write without 1909 * reading before because all bits are r/o or w1tc 1910 */ 1911 pci_conf_write(sc->sc_pc, brtag, PCI_CBB_SECSTATUS, 1912 CBB_SECSTATUS_CBMABORT); 1913 reg = pci_conf_read(sc->sc_pc, tag, offset); 1914 /* check cardbus master abort status */ 1915 if (pci_conf_read(sc->sc_pc, brtag, PCI_CBB_SECSTATUS) 1916 & CBB_SECSTATUS_CBMABORT) 1917 return (0xffffffff); 1918 return reg; 1919 } 1920 1921 /* 1922 * pccbb_conf_write 1923 * 1924 * This is the function to write the config space of a CardBus 1925 * card. It works the same as pci_conf_write(9). 1926 */ 1927 static void 1928 pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, int reg, 1929 cardbusreg_t val) 1930 { 1931 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1932 1933 pci_conf_write(sc->sc_pc, tag, reg, val); 1934 } 1935 1936 #if 0 1937 STATIC int 1938 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1939 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 1940 int speed, int flags, 1941 bus_space_handle_t * iohp) 1942 #endif 1943 /* 1944 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1945 * bus_addr_t start, bus_size_t size, 1946 * bus_size_t align, 1947 * struct pcmcia_io_handle *pcihp 1948 * 1949 * This function only allocates I/O region for pccard. This function 1950 * never maps the allocated region to pccard I/O area. 1951 * 1952 * XXX: The interface of this function is not very good, I believe. 1953 */ 1954 STATIC int 1955 pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, 1956 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 1957 { 1958 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 1959 bus_addr_t ioaddr; 1960 int flags = 0; 1961 bus_space_tag_t iot; 1962 bus_space_handle_t ioh; 1963 bus_addr_t mask; 1964 #if rbus 1965 rbus_tag_t rb; 1966 #endif 1967 if (align == 0) { 1968 align = size; /* XXX: funny??? */ 1969 } 1970 1971 if (start != 0) { 1972 /* XXX: assume all card decode lower 10 bits by its hardware */ 1973 mask = 0x3ff; 1974 /* enforce to use only masked address */ 1975 start &= mask; 1976 } else { 1977 /* 1978 * calculate mask: 1979 * 1. get the most significant bit of size (call it msb). 1980 * 2. compare msb with the value of size. 1981 * 3. if size is larger, shift msb left once. 1982 * 4. obtain mask value to decrement msb. 1983 */ 1984 bus_size_t size_tmp = size; 1985 int shifts = 0; 1986 1987 mask = 1; 1988 while (size_tmp) { 1989 ++shifts; 1990 size_tmp >>= 1; 1991 } 1992 mask = (1 << shifts); 1993 if (mask < size) { 1994 mask <<= 1; 1995 } 1996 --mask; 1997 } 1998 1999 /* 2000 * Allocate some arbitrary I/O space. 2001 */ 2002 2003 iot = sc->sc_iot; 2004 2005 #if rbus 2006 rb = sc->sc_rbus_iot; 2007 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 2008 return 1; 2009 } 2010 DPRINTF(("pccbb_pcmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2011 (u_long) ioaddr, (u_long) size)); 2012 #else 2013 if (start) { 2014 ioaddr = start; 2015 if (bus_space_map(iot, start, size, 0, &ioh)) { 2016 return 1; 2017 } 2018 DPRINTF(("pccbb_pcmcia_io_alloc map port 0x%lx+0x%lx\n", 2019 (u_long) ioaddr, (u_long) size)); 2020 } else { 2021 flags |= PCMCIA_IO_ALLOCATED; 2022 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 2023 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 2024 size, align, 0, 0, &ioaddr, &ioh)) { 2025 /* No room be able to be get. */ 2026 return 1; 2027 } 2028 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2029 (u_long) ioaddr, (u_long) size)); 2030 } 2031 #endif 2032 2033 pcihp->iot = iot; 2034 pcihp->ioh = ioh; 2035 pcihp->addr = ioaddr; 2036 pcihp->size = size; 2037 pcihp->flags = flags; 2038 2039 return 0; 2040 } 2041 2042 /* 2043 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2044 * struct pcmcia_io_handle *pcihp) 2045 * 2046 * This function only frees I/O region for pccard. 2047 * 2048 * XXX: The interface of this function is not very good, I believe. 2049 */ 2050 void 2051 pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2052 struct pcmcia_io_handle *pcihp) 2053 { 2054 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2055 #if !rbus 2056 bus_space_tag_t iot = pcihp->iot; 2057 #endif 2058 bus_space_handle_t ioh = pcihp->ioh; 2059 bus_size_t size = pcihp->size; 2060 2061 #if rbus 2062 rbus_tag_t rb = sc->sc_rbus_iot; 2063 2064 rbus_space_free(rb, ioh, size, NULL); 2065 #else 2066 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 2067 bus_space_free(iot, ioh, size); 2068 else 2069 bus_space_unmap(iot, ioh, size); 2070 #endif 2071 } 2072 2073 /* 2074 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 2075 * bus_addr_t offset, bus_size_t size, 2076 * struct pcmcia_io_handle *pcihp, 2077 * int *windowp) 2078 * 2079 * This function maps the allocated I/O region to pccard. This function 2080 * never allocates any I/O region for pccard I/O area. I don't 2081 * understand why the original authors of pcmciabus separated alloc and 2082 * map. I believe the two must be unite. 2083 * 2084 * XXX: no wait timing control? 2085 */ 2086 int 2087 pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, bus_addr_t offset, 2088 bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp) 2089 { 2090 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2091 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2092 bus_addr_t ioaddr = pcihp->addr + offset; 2093 int i, win; 2094 #if defined CBB_DEBUG 2095 static const char *width_names[] = { "dynamic", "io8", "io16" }; 2096 #endif 2097 2098 /* Sanity check I/O handle. */ 2099 2100 if (sc->sc_iot != pcihp->iot) { 2101 panic("pccbb_pcmcia_io_map iot is bogus"); 2102 } 2103 2104 /* XXX Sanity check offset/size. */ 2105 2106 win = -1; 2107 for (i = 0; i < PCIC_IO_WINS; i++) { 2108 if ((ph->ioalloc & (1 << i)) == 0) { 2109 win = i; 2110 ph->ioalloc |= (1 << i); 2111 break; 2112 } 2113 } 2114 2115 if (win == -1) { 2116 return 1; 2117 } 2118 2119 *windowp = win; 2120 2121 /* XXX this is pretty gross */ 2122 2123 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2124 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2125 2126 /* XXX wtf is this doing here? */ 2127 2128 #if 0 2129 printf(" port 0x%lx", (u_long) ioaddr); 2130 if (size > 1) { 2131 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2132 } 2133 #endif 2134 2135 ph->io[win].addr = ioaddr; 2136 ph->io[win].size = size; 2137 ph->io[win].width = width; 2138 2139 /* actual dirty register-value changing in the function below. */ 2140 pccbb_pcmcia_do_io_map(sc, win); 2141 2142 return 0; 2143 } 2144 2145 /* 2146 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2147 * 2148 * This function changes register-value to map I/O region for pccard. 2149 */ 2150 static void 2151 pccbb_pcmcia_do_io_map(struct pccbb_softc *sc, int win) 2152 { 2153 static u_int8_t pcic_iowidth[3] = { 2154 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2155 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2156 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2157 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2158 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2159 }; 2160 2161 #define PCIC_SIA_START_LOW 0 2162 #define PCIC_SIA_START_HIGH 1 2163 #define PCIC_SIA_STOP_LOW 2 2164 #define PCIC_SIA_STOP_HIGH 3 2165 2166 int regbase_win = 0x8 + win * 0x04; 2167 u_int8_t ioctl, enable; 2168 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2169 2170 DPRINTF(("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx " 2171 "width %d\n", win, (unsigned long)ph->io[win].addr, 2172 (unsigned long)ph->io[win].size, ph->io[win].width * 8)); 2173 2174 Pcic_write(sc, regbase_win + PCIC_SIA_START_LOW, 2175 ph->io[win].addr & 0xff); 2176 Pcic_write(sc, regbase_win + PCIC_SIA_START_HIGH, 2177 (ph->io[win].addr >> 8) & 0xff); 2178 2179 Pcic_write(sc, regbase_win + PCIC_SIA_STOP_LOW, 2180 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2181 Pcic_write(sc, regbase_win + PCIC_SIA_STOP_HIGH, 2182 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2183 2184 ioctl = Pcic_read(sc, PCIC_IOCTL); 2185 enable = Pcic_read(sc, PCIC_ADDRWIN_ENABLE); 2186 switch (win) { 2187 case 0: 2188 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2189 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2190 PCIC_IOCTL_IO0_DATASIZE_MASK); 2191 ioctl |= pcic_iowidth[ph->io[win].width]; 2192 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2193 break; 2194 case 1: 2195 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2196 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2197 PCIC_IOCTL_IO1_DATASIZE_MASK); 2198 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2199 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2200 break; 2201 } 2202 Pcic_write(sc, PCIC_IOCTL, ioctl); 2203 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, enable); 2204 #if defined(CBB_DEBUG) 2205 { 2206 u_int8_t start_low = 2207 Pcic_read(sc, regbase_win + PCIC_SIA_START_LOW); 2208 u_int8_t start_high = 2209 Pcic_read(sc, regbase_win + PCIC_SIA_START_HIGH); 2210 u_int8_t stop_low = 2211 Pcic_read(sc, regbase_win + PCIC_SIA_STOP_LOW); 2212 u_int8_t stop_high = 2213 Pcic_read(sc, regbase_win + PCIC_SIA_STOP_HIGH); 2214 printf("pccbb_pcmcia_do_io_map start %02x %02x, " 2215 "stop %02x %02x, ioctl %02x enable %02x\n", 2216 start_low, start_high, stop_low, stop_high, ioctl, enable); 2217 } 2218 #endif 2219 } 2220 2221 /* 2222 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2223 * 2224 * This function unmaps I/O region. No return value. 2225 */ 2226 STATIC void 2227 pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t pch, int win) 2228 { 2229 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2230 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2231 int reg; 2232 2233 if (win >= PCIC_IO_WINS || win < 0) { 2234 panic("pccbb_pcmcia_io_unmap: window out of range"); 2235 } 2236 2237 reg = Pcic_read(sc, PCIC_ADDRWIN_ENABLE); 2238 switch (win) { 2239 case 0: 2240 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2241 break; 2242 case 1: 2243 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2244 break; 2245 } 2246 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, reg); 2247 2248 ph->ioalloc &= ~(1 << win); 2249 } 2250 2251 static int 2252 pccbb_pcmcia_wait_ready(struct pccbb_softc *sc) 2253 { 2254 u_int8_t stat; 2255 int i; 2256 2257 /* wait an initial 10ms for quick cards */ 2258 stat = Pcic_read(sc, PCIC_IF_STATUS); 2259 if (stat & PCIC_IF_STATUS_READY) 2260 return (0); 2261 pccbb_pcmcia_delay(sc, 10, "pccwr0"); 2262 for (i = 0; i < 50; i++) { 2263 stat = Pcic_read(sc, PCIC_IF_STATUS); 2264 if (stat & PCIC_IF_STATUS_READY) 2265 return (0); 2266 if ((stat & PCIC_IF_STATUS_CARDDETECT_MASK) != 2267 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2268 return (ENXIO); 2269 /* wait .1s (100ms) each iteration now */ 2270 pccbb_pcmcia_delay(sc, 100, "pccwr1"); 2271 } 2272 2273 printf("pccbb_pcmcia_wait_ready: ready never happened, status=%02x\n", stat); 2274 return (EWOULDBLOCK); 2275 } 2276 2277 /* 2278 * Perform long (msec order) delay. timo is in milliseconds. 2279 */ 2280 static void 2281 pccbb_pcmcia_delay(struct pccbb_softc *sc, int timo, const char *wmesg) 2282 { 2283 #ifdef DIAGNOSTIC 2284 if (timo <= 0) 2285 panic("pccbb_pcmcia_delay: called with timeout %d", timo); 2286 if (!curlwp) 2287 panic("pccbb_pcmcia_delay: called in interrupt context"); 2288 #endif 2289 DPRINTF(("pccbb_pcmcia_delay: \"%s\", sleep %d ms\n", wmesg, timo)); 2290 tsleep(pccbb_pcmcia_delay, PWAIT, wmesg, roundup(timo * hz, 1000) / 1000); 2291 } 2292 2293 /* 2294 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2295 * 2296 * This function enables the card. All information is stored in 2297 * the first argument, pcmcia_chipset_handle_t. 2298 */ 2299 STATIC void 2300 pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2301 { 2302 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2303 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2304 pcireg_t spsr; 2305 int voltage; 2306 int win; 2307 u_int8_t power, intr; 2308 #ifdef DIAGNOSTIC 2309 int reg; 2310 #endif 2311 2312 /* this bit is mostly stolen from pcic_attach_card */ 2313 2314 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2315 2316 /* get card Vcc info */ 2317 spsr = 2318 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2319 CB_SOCKET_STAT); 2320 if (spsr & CB_SOCKET_STAT_5VCARD) { 2321 DPRINTF(("5V card\n")); 2322 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2323 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2324 DPRINTF(("3V card\n")); 2325 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2326 } else { 2327 DPRINTF(("?V card, 0x%x\n", spsr)); /* XXX */ 2328 return; 2329 } 2330 2331 /* disable interrupts; assert RESET */ 2332 intr = Pcic_read(sc, PCIC_INTR); 2333 intr &= PCIC_INTR_ENABLE; 2334 Pcic_write(sc, PCIC_INTR, intr); 2335 2336 /* zero out the address windows */ 2337 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, 0); 2338 2339 /* power down the socket to reset it, clear the card reset pin */ 2340 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2341 2342 /* power off; assert output enable bit */ 2343 power = PCIC_PWRCTL_OE; 2344 Pcic_write(sc, PCIC_PWRCTL, power); 2345 2346 /* power up the socket */ 2347 if (pccbb_power(sc, voltage) == 0) 2348 return; 2349 2350 /* 2351 * Table 4-18 and figure 4-6 of the PC Card specifiction say: 2352 * Vcc Rising Time (Tpr) = 100ms (handled in pccbb_power() above) 2353 * RESET Width (Th (Hi-z RESET)) = 1ms 2354 * RESET Width (Tw (RESET)) = 10us 2355 * 2356 * some machines require some more time to be settled 2357 * for example old toshiba topic bridges! 2358 * (100ms is added here). 2359 */ 2360 pccbb_pcmcia_delay(sc, 200 + 1, "pccen1"); 2361 2362 /* negate RESET */ 2363 intr |= PCIC_INTR_RESET; 2364 Pcic_write(sc, PCIC_INTR, intr); 2365 2366 /* 2367 * RESET Setup Time (Tsu (RESET)) = 20ms 2368 */ 2369 pccbb_pcmcia_delay(sc, 20, "pccen2"); 2370 2371 #ifdef DIAGNOSTIC 2372 reg = Pcic_read(sc, PCIC_IF_STATUS); 2373 if ((reg & PCIC_IF_STATUS_POWERACTIVE) == 0) 2374 printf("pccbb_pcmcia_socket_enable: no power, status=%x\n", reg); 2375 #endif 2376 2377 /* wait for the chip to finish initializing */ 2378 if (pccbb_pcmcia_wait_ready(sc)) { 2379 #ifdef DIAGNOSTIC 2380 printf("pccbb_pcmcia_socket_enable: never became ready\n"); 2381 #endif 2382 /* XXX return a failure status?? */ 2383 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2384 Pcic_write(sc, PCIC_PWRCTL, 0); 2385 return; 2386 } 2387 2388 /* reinstall all the memory and io mappings */ 2389 for (win = 0; win < PCIC_MEM_WINS; ++win) 2390 if (ph->memalloc & (1 << win)) 2391 pccbb_pcmcia_do_mem_map(sc, win); 2392 for (win = 0; win < PCIC_IO_WINS; ++win) 2393 if (ph->ioalloc & (1 << win)) 2394 pccbb_pcmcia_do_io_map(sc, win); 2395 } 2396 2397 /* 2398 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2399 * 2400 * This function disables the card. All information is stored in 2401 * the first argument, pcmcia_chipset_handle_t. 2402 */ 2403 STATIC void 2404 pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t pch) 2405 { 2406 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2407 u_int8_t intr; 2408 2409 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2410 2411 /* disable interrupts; assert RESET */ 2412 intr = Pcic_read(sc, PCIC_INTR); 2413 intr &= PCIC_INTR_ENABLE; 2414 Pcic_write(sc, PCIC_INTR, intr); 2415 2416 /* zero out the address windows */ 2417 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, 0); 2418 2419 /* power down the socket to reset it, clear the card reset pin */ 2420 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2421 2422 /* disable socket: negate output enable bit and power off */ 2423 Pcic_write(sc, PCIC_PWRCTL, 0); 2424 2425 /* 2426 * Vcc Falling Time (Tpf) = 300ms 2427 */ 2428 pccbb_pcmcia_delay(sc, 300, "pccwr1"); 2429 } 2430 2431 STATIC void 2432 pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t pch, int type) 2433 { 2434 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2435 u_int8_t intr; 2436 2437 /* set the card type */ 2438 2439 intr = Pcic_read(sc, PCIC_INTR); 2440 intr &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_CARDTYPE_MASK); 2441 if (type == PCMCIA_IFTYPE_IO) 2442 intr |= PCIC_INTR_CARDTYPE_IO; 2443 else 2444 intr |= PCIC_INTR_CARDTYPE_MEM; 2445 Pcic_write(sc, PCIC_INTR, intr); 2446 2447 DPRINTF(("%s: pccbb_pcmcia_socket_settype type %s %02x\n", 2448 device_xname(sc->sc_dev), 2449 ((type == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2450 } 2451 2452 /* 2453 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2454 * 2455 * This function detects whether a card is in the slot or not. 2456 * If a card is inserted, return 1. Otherwise, return 0. 2457 */ 2458 STATIC int 2459 pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch) 2460 { 2461 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2462 2463 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2464 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2465 } 2466 2467 #if 0 2468 STATIC int 2469 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2470 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2471 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2472 #endif 2473 /* 2474 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2475 * bus_size_t size, 2476 * struct pcmcia_mem_handle *pcmhp) 2477 * 2478 * This function only allocates memory region for pccard. This 2479 * function never maps the allocated region to pccard memory area. 2480 * 2481 * XXX: Why the argument of start address is not in? 2482 */ 2483 STATIC int 2484 pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 2485 struct pcmcia_mem_handle *pcmhp) 2486 { 2487 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2488 bus_space_handle_t memh; 2489 bus_addr_t addr; 2490 bus_size_t sizepg; 2491 #if rbus 2492 rbus_tag_t rb; 2493 #endif 2494 2495 /* Check that the card is still there. */ 2496 if ((Pcic_read(sc, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2497 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2498 return 1; 2499 2500 /* out of sc->memh, allocate as many pages as necessary */ 2501 2502 /* convert size to PCIC pages */ 2503 /* 2504 * This is not enough; when the requested region is on the page 2505 * boundaries, this may calculate wrong result. 2506 */ 2507 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2508 #if 0 2509 if (sizepg > PCIC_MAX_MEM_PAGES) { 2510 return 1; 2511 } 2512 #endif 2513 2514 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2515 return 1; 2516 } 2517 2518 addr = 0; /* XXX gcc -Wuninitialized */ 2519 2520 #if rbus 2521 rb = sc->sc_rbus_memt; 2522 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2523 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2524 &addr, &memh)) { 2525 return 1; 2526 } 2527 #else 2528 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2529 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2530 0, /* boundary */ 2531 0, /* flags */ 2532 &addr, &memh)) { 2533 return 1; 2534 } 2535 #endif 2536 2537 DPRINTF(("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, " 2538 "realsize 0x%lx\n", (unsigned long)addr, (unsigned long)size, 2539 (unsigned long)sizepg * PCIC_MEM_PAGESIZE)); 2540 2541 pcmhp->memt = sc->sc_memt; 2542 pcmhp->memh = memh; 2543 pcmhp->addr = addr; 2544 pcmhp->size = size; 2545 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2546 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2547 pcmhp->mhandle = 0; 2548 /* No offset??? Funny. */ 2549 2550 return 0; 2551 } 2552 2553 /* 2554 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2555 * struct pcmcia_mem_handle *pcmhp) 2556 * 2557 * This function release the memory space allocated by the function 2558 * pccbb_pcmcia_mem_alloc(). 2559 */ 2560 STATIC void 2561 pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2562 struct pcmcia_mem_handle *pcmhp) 2563 { 2564 #if rbus 2565 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2566 2567 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2568 #else 2569 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2570 #endif 2571 } 2572 2573 /* 2574 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2575 * 2576 * This function release the memory space allocated by the function 2577 * pccbb_pcmcia_mem_alloc(). 2578 */ 2579 STATIC void 2580 pccbb_pcmcia_do_mem_map(struct pccbb_softc *sc, int win) 2581 { 2582 int regbase_win; 2583 bus_addr_t phys_addr; 2584 bus_addr_t phys_end; 2585 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2586 2587 #define PCIC_SMM_START_LOW 0 2588 #define PCIC_SMM_START_HIGH 1 2589 #define PCIC_SMM_STOP_LOW 2 2590 #define PCIC_SMM_STOP_HIGH 3 2591 #define PCIC_CMA_LOW 4 2592 #define PCIC_CMA_HIGH 5 2593 2594 u_int8_t start_low, start_high = 0; 2595 u_int8_t stop_low, stop_high; 2596 u_int8_t off_low, off_high; 2597 u_int8_t mem_window; 2598 int reg; 2599 2600 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2601 int mem8 = 2602 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2603 || (kind == PCMCIA_MEM_ATTR); 2604 2605 regbase_win = 0x10 + win * 0x08; 2606 2607 phys_addr = ph->mem[win].addr; 2608 phys_end = phys_addr + ph->mem[win].size; 2609 2610 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2611 (unsigned long)phys_addr, (unsigned long)phys_end, 2612 (unsigned long)ph->mem[win].offset)); 2613 2614 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2615 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2616 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2617 2618 /* bit 19:12 */ 2619 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2620 /* bit 23:20 and bit 7 on */ 2621 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2622 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2623 /* bit 31:24, for 32-bit address */ 2624 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2625 2626 Pcic_write(sc, regbase_win + PCIC_SMM_START_LOW, start_low); 2627 Pcic_write(sc, regbase_win + PCIC_SMM_START_HIGH, start_high); 2628 2629 if (sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2630 Pcic_write(sc, 0x40 + win, mem_window); 2631 } 2632 2633 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2634 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2635 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2636 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2637 2638 Pcic_write(sc, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2639 Pcic_write(sc, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2640 2641 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2642 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2643 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2644 | ((kind == PCMCIA_MEM_ATTR) ? 2645 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2646 2647 Pcic_write(sc, regbase_win + PCIC_CMA_LOW, off_low); 2648 Pcic_write(sc, regbase_win + PCIC_CMA_HIGH, off_high); 2649 2650 reg = Pcic_read(sc, PCIC_ADDRWIN_ENABLE); 2651 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2652 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, reg); 2653 2654 #if defined(CBB_DEBUG) 2655 { 2656 int r1, r2, r3, r4, r5, r6, r7 = 0; 2657 2658 r1 = Pcic_read(sc, regbase_win + PCIC_SMM_START_LOW); 2659 r2 = Pcic_read(sc, regbase_win + PCIC_SMM_START_HIGH); 2660 r3 = Pcic_read(sc, regbase_win + PCIC_SMM_STOP_LOW); 2661 r4 = Pcic_read(sc, regbase_win + PCIC_SMM_STOP_HIGH); 2662 r5 = Pcic_read(sc, regbase_win + PCIC_CMA_LOW); 2663 r6 = Pcic_read(sc, regbase_win + PCIC_CMA_HIGH); 2664 if (sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2665 r7 = Pcic_read(sc, 0x40 + win); 2666 } 2667 2668 printf("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2669 "%02x%02x", win, r1, r2, r3, r4, r5, r6); 2670 if (sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2671 printf(" %02x", r7); 2672 } 2673 printf("\n"); 2674 } 2675 #endif 2676 } 2677 2678 /* 2679 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2680 * bus_addr_t card_addr, bus_size_t size, 2681 * struct pcmcia_mem_handle *pcmhp, 2682 * bus_addr_t *offsetp, int *windowp) 2683 * 2684 * This function maps memory space allocated by the function 2685 * pccbb_pcmcia_mem_alloc(). 2686 */ 2687 STATIC int 2688 pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2689 bus_addr_t card_addr, bus_size_t size, struct pcmcia_mem_handle *pcmhp, 2690 bus_size_t *offsetp, int *windowp) 2691 { 2692 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2693 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2694 bus_addr_t busaddr; 2695 long card_offset; 2696 int win; 2697 2698 /* Check that the card is still there. */ 2699 if ((Pcic_read(sc, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2700 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2701 return 1; 2702 2703 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2704 if ((ph->memalloc & (1 << win)) == 0) { 2705 ph->memalloc |= (1 << win); 2706 break; 2707 } 2708 } 2709 2710 if (win == PCIC_MEM_WINS) { 2711 return 1; 2712 } 2713 2714 *windowp = win; 2715 2716 /* XXX this is pretty gross */ 2717 2718 if (sc->sc_memt != pcmhp->memt) { 2719 panic("pccbb_pcmcia_mem_map memt is bogus"); 2720 } 2721 2722 busaddr = pcmhp->addr; 2723 2724 /* 2725 * compute the address offset to the pcmcia address space for the 2726 * pcic. this is intentionally signed. The masks and shifts below 2727 * will cause TRT to happen in the pcic registers. Deal with making 2728 * sure the address is aligned, and return the alignment offset. 2729 */ 2730 2731 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2732 card_addr -= *offsetp; 2733 2734 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2735 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2736 (u_long) card_addr)); 2737 2738 /* 2739 * include the offset in the size, and decrement size by one, since 2740 * the hw wants start/stop 2741 */ 2742 size += *offsetp - 1; 2743 2744 card_offset = (((long)card_addr) - ((long)busaddr)); 2745 2746 ph->mem[win].addr = busaddr; 2747 ph->mem[win].size = size; 2748 ph->mem[win].offset = card_offset; 2749 ph->mem[win].kind = kind; 2750 2751 pccbb_pcmcia_do_mem_map(sc, win); 2752 2753 return 0; 2754 } 2755 2756 /* 2757 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2758 * int window) 2759 * 2760 * This function unmaps memory space which mapped by the function 2761 * pccbb_pcmcia_mem_map(). 2762 */ 2763 STATIC void 2764 pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, int window) 2765 { 2766 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2767 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2768 int reg; 2769 2770 if (window >= PCIC_MEM_WINS) { 2771 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2772 } 2773 2774 reg = Pcic_read(sc, PCIC_ADDRWIN_ENABLE); 2775 reg &= ~(1 << window); 2776 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, reg); 2777 2778 ph->memalloc &= ~(1 << window); 2779 } 2780 2781 /* 2782 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2783 * struct pcmcia_function *pf, 2784 * int ipl, 2785 * int (*func)(void *), 2786 * void *arg); 2787 * 2788 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2789 */ 2790 STATIC void * 2791 pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2792 struct pcmcia_function *pf, int ipl, int (*func)(void *), void *arg) 2793 { 2794 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2795 2796 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2797 /* what should I do? */ 2798 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2799 DPRINTF(("%s does not provide edge nor pulse " 2800 "interrupt\n", device_xname(sc->sc_dev))); 2801 return NULL; 2802 } 2803 /* 2804 * XXX Noooooo! The interrupt flag must set properly!! 2805 * dumb pcmcia driver!! 2806 */ 2807 } 2808 2809 return pccbb_intr_establish(sc, 0, ipl, func, arg); 2810 } 2811 2812 /* 2813 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2814 * void *ih) 2815 * 2816 * This function disables PC-Card interrupt. 2817 */ 2818 STATIC void 2819 pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 2820 { 2821 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2822 2823 pccbb_intr_disestablish(sc, ih); 2824 } 2825 2826 #if rbus 2827 /* 2828 * static int 2829 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2830 * bus_addr_t addr, bus_size_t size, 2831 * bus_addr_t mask, bus_size_t align, 2832 * int flags, bus_addr_t *addrp; 2833 * bus_space_handle_t *bshp) 2834 * 2835 * This function allocates a portion of memory or io space for 2836 * clients. This function is called from CardBus card drivers. 2837 */ 2838 static int 2839 pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2840 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 2841 int flags, bus_addr_t *addrp, bus_space_handle_t *bshp) 2842 { 2843 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2844 2845 DPRINTF(("pccbb_rbus_cb_space_alloc: addr 0x%lx, size 0x%lx, " 2846 "mask 0x%lx, align 0x%lx\n", (unsigned long)addr, 2847 (unsigned long)size, (unsigned long)mask, (unsigned long)align)); 2848 2849 if (align == 0) { 2850 align = size; 2851 } 2852 2853 if (rb->rb_bt == sc->sc_memt) { 2854 if (align < 16) { 2855 return 1; 2856 } 2857 /* 2858 * XXX: align more than 0x1000 to avoid overwrapping 2859 * memory windows for two or more devices. 0x1000 2860 * means memory window's granularity. 2861 * 2862 * Two or more devices should be able to share same 2863 * memory window region. However, overrapping memory 2864 * window is not good because some devices, such as 2865 * 3Com 3C575[BC], have a broken address decoder and 2866 * intrude other's memory region. 2867 */ 2868 if (align < 0x1000) { 2869 align = 0x1000; 2870 } 2871 } else if (rb->rb_bt == sc->sc_iot) { 2872 if (align < 4) { 2873 return 1; 2874 } 2875 /* XXX: hack for avoiding ISA image */ 2876 if (mask < 0x0100) { 2877 mask = 0x3ff; 2878 addr = 0x300; 2879 } 2880 2881 } else { 2882 DPRINTF(("pccbb_rbus_cb_space_alloc: Bus space tag 0x%lx is " 2883 "NOT used. io: 0x%lx, mem: 0x%lx\n", 2884 (unsigned long)rb->rb_bt, (unsigned long)sc->sc_iot, 2885 (unsigned long)sc->sc_memt)); 2886 return 1; 2887 /* XXX: panic here? */ 2888 } 2889 2890 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 2891 aprint_normal_dev(sc->sc_dev, "<rbus> no bus space\n"); 2892 return 1; 2893 } 2894 2895 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 2896 2897 return 0; 2898 } 2899 2900 /* 2901 * static int 2902 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 2903 * bus_space_handle_t *bshp, bus_size_t size); 2904 * 2905 * This function is called from CardBus card drivers. 2906 */ 2907 static int 2908 pccbb_rbus_cb_space_free(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2909 bus_space_handle_t bsh, bus_size_t size) 2910 { 2911 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2912 bus_space_tag_t bt = rb->rb_bt; 2913 2914 pccbb_close_win(sc, bt, bsh, size); 2915 2916 if (bt == sc->sc_memt) { 2917 } else if (bt == sc->sc_iot) { 2918 } else { 2919 return 1; 2920 /* XXX: panic here? */ 2921 } 2922 2923 return rbus_space_free(rb, bsh, size, NULL); 2924 } 2925 #endif /* rbus */ 2926 2927 #if rbus 2928 2929 static int 2930 pccbb_open_win(struct pccbb_softc *sc, bus_space_tag_t bst, bus_addr_t addr, 2931 bus_size_t size, bus_space_handle_t bsh, int flags) 2932 { 2933 struct pccbb_win_chain_head *head; 2934 bus_addr_t align; 2935 2936 head = &sc->sc_iowindow; 2937 align = 0x04; 2938 if (sc->sc_memt == bst) { 2939 head = &sc->sc_memwindow; 2940 align = 0x1000; 2941 DPRINTF(("using memory window, 0x%lx 0x%lx 0x%lx\n\n", 2942 (unsigned long)sc->sc_iot, (unsigned long)sc->sc_memt, 2943 (unsigned long)bst)); 2944 } 2945 2946 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 2947 aprint_error_dev(sc->sc_dev, 2948 "pccbb_open_win: %s winlist insert failed\n", 2949 (head == &sc->sc_memwindow) ? "mem" : "io"); 2950 } 2951 pccbb_winset(align, sc, bst); 2952 2953 return 0; 2954 } 2955 2956 static int 2957 pccbb_close_win(struct pccbb_softc *sc, bus_space_tag_t bst, 2958 bus_space_handle_t bsh, bus_size_t size) 2959 { 2960 struct pccbb_win_chain_head *head; 2961 bus_addr_t align; 2962 2963 head = &sc->sc_iowindow; 2964 align = 0x04; 2965 if (sc->sc_memt == bst) { 2966 head = &sc->sc_memwindow; 2967 align = 0x1000; 2968 } 2969 2970 if (pccbb_winlist_delete(head, bsh, size)) { 2971 aprint_error_dev(sc->sc_dev, 2972 "pccbb_close_win: %s winlist delete failed\n", 2973 (head == &sc->sc_memwindow) ? "mem" : "io"); 2974 } 2975 pccbb_winset(align, sc, bst); 2976 2977 return 0; 2978 } 2979 2980 static int 2981 pccbb_winlist_insert(struct pccbb_win_chain_head *head, bus_addr_t start, 2982 bus_size_t size, bus_space_handle_t bsh, int flags) 2983 { 2984 struct pccbb_win_chain *chainp, *elem; 2985 2986 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 2987 M_NOWAIT)) == NULL) 2988 return (1); /* fail */ 2989 2990 elem->wc_start = start; 2991 elem->wc_end = start + (size - 1); 2992 elem->wc_handle = bsh; 2993 elem->wc_flags = flags; 2994 2995 TAILQ_FOREACH(chainp, head, wc_list) { 2996 if (chainp->wc_end >= start) 2997 break; 2998 } 2999 if (chainp != NULL) 3000 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 3001 else 3002 TAILQ_INSERT_TAIL(head, elem, wc_list); 3003 return (0); 3004 } 3005 3006 static int 3007 pccbb_winlist_delete(struct pccbb_win_chain_head *head, bus_space_handle_t bsh, 3008 bus_size_t size) 3009 { 3010 struct pccbb_win_chain *chainp; 3011 3012 TAILQ_FOREACH(chainp, head, wc_list) { 3013 if (memcmp(&chainp->wc_handle, &bsh, sizeof(bsh)) == 0) 3014 break; 3015 } 3016 if (chainp == NULL) 3017 return 1; /* fail: no candidate to remove */ 3018 3019 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 3020 printf("pccbb_winlist_delete: window 0x%lx size " 3021 "inconsistent: 0x%lx, 0x%lx\n", 3022 (unsigned long)chainp->wc_start, 3023 (unsigned long)(chainp->wc_end - chainp->wc_start), 3024 (unsigned long)(size - 1)); 3025 return 1; 3026 } 3027 3028 TAILQ_REMOVE(head, chainp, wc_list); 3029 free(chainp, M_DEVBUF); 3030 3031 return 0; 3032 } 3033 3034 static void 3035 pccbb_winset(bus_addr_t align, struct pccbb_softc *sc, bus_space_tag_t bst) 3036 { 3037 pci_chipset_tag_t pc; 3038 pcitag_t tag; 3039 bus_addr_t mask = ~(align - 1); 3040 struct { 3041 cardbusreg_t win_start; 3042 cardbusreg_t win_limit; 3043 int win_flags; 3044 } win[2]; 3045 struct pccbb_win_chain *chainp; 3046 int offs; 3047 3048 win[0].win_start = win[1].win_start = 0xffffffff; 3049 win[0].win_limit = win[1].win_limit = 0; 3050 win[0].win_flags = win[1].win_flags = 0; 3051 3052 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3053 offs = PCI_CB_IOBASE0; 3054 if (sc->sc_memt == bst) { 3055 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3056 offs = PCI_CB_MEMBASE0; 3057 } 3058 3059 if (chainp != NULL) { 3060 win[0].win_start = chainp->wc_start & mask; 3061 win[0].win_limit = chainp->wc_end & mask; 3062 win[0].win_flags = chainp->wc_flags; 3063 chainp = TAILQ_NEXT(chainp, wc_list); 3064 } 3065 3066 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3067 if (win[1].win_start == 0xffffffff) { 3068 /* window 1 is not used */ 3069 if ((win[0].win_flags == chainp->wc_flags) && 3070 (win[0].win_limit + align >= 3071 (chainp->wc_start & mask))) { 3072 /* concatenate */ 3073 win[0].win_limit = chainp->wc_end & mask; 3074 } else { 3075 /* make new window */ 3076 win[1].win_start = chainp->wc_start & mask; 3077 win[1].win_limit = chainp->wc_end & mask; 3078 win[1].win_flags = chainp->wc_flags; 3079 } 3080 continue; 3081 } 3082 3083 /* Both windows are engaged. */ 3084 if (win[0].win_flags == win[1].win_flags) { 3085 /* same flags */ 3086 if (win[0].win_flags == chainp->wc_flags) { 3087 if (win[1].win_start - (win[0].win_limit + 3088 align) < 3089 (chainp->wc_start & mask) - 3090 ((chainp->wc_end & mask) + align)) { 3091 /* 3092 * merge window 0 and 1, and set win1 3093 * to chainp 3094 */ 3095 win[0].win_limit = win[1].win_limit; 3096 win[1].win_start = 3097 chainp->wc_start & mask; 3098 win[1].win_limit = 3099 chainp->wc_end & mask; 3100 } else { 3101 win[1].win_limit = 3102 chainp->wc_end & mask; 3103 } 3104 } else { 3105 /* different flags */ 3106 3107 /* concatenate win0 and win1 */ 3108 win[0].win_limit = win[1].win_limit; 3109 /* allocate win[1] to new space */ 3110 win[1].win_start = chainp->wc_start & mask; 3111 win[1].win_limit = chainp->wc_end & mask; 3112 win[1].win_flags = chainp->wc_flags; 3113 } 3114 } else { 3115 /* the flags of win[0] and win[1] is different */ 3116 if (win[0].win_flags == chainp->wc_flags) { 3117 win[0].win_limit = chainp->wc_end & mask; 3118 /* 3119 * XXX this creates overlapping windows, so 3120 * what should the poor bridge do if one is 3121 * cachable, and the other is not? 3122 */ 3123 aprint_error_dev(sc->sc_dev, 3124 "overlapping windows\n"); 3125 } else { 3126 win[1].win_limit = chainp->wc_end & mask; 3127 } 3128 } 3129 } 3130 3131 pc = sc->sc_pc; 3132 tag = sc->sc_tag; 3133 pci_conf_write(pc, tag, offs, win[0].win_start); 3134 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3135 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3136 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3137 DPRINTF(("--pccbb_winset: win0 [0x%lx, 0x%lx), win1 [0x%lx, 0x%lx)\n", 3138 (unsigned long)pci_conf_read(pc, tag, offs), 3139 (unsigned long)pci_conf_read(pc, tag, offs + 4) + align, 3140 (unsigned long)pci_conf_read(pc, tag, offs + 8), 3141 (unsigned long)pci_conf_read(pc, tag, offs + 12) + align)); 3142 3143 if (bst == sc->sc_memt) { 3144 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BRIDGE_CONTROL_REG); 3145 3146 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 3147 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 3148 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3149 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 3150 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3151 pci_conf_write(pc, tag, PCI_BRIDGE_CONTROL_REG, bcr); 3152 } 3153 } 3154 3155 #endif /* rbus */ 3156 3157 static bool 3158 pccbb_suspend(device_t dv PMF_FN_ARGS) 3159 { 3160 struct pccbb_softc *sc = device_private(dv); 3161 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3162 bus_space_handle_t base_memh = sc->sc_base_memh; 3163 pcireg_t reg; 3164 3165 if (sc->sc_pil_intr_enable) 3166 (void)pccbbintr_function(sc); 3167 sc->sc_pil_intr_enable = 0; 3168 3169 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3170 /* Disable interrupts. */ 3171 reg &= ~(CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER); 3172 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3173 /* XXX joerg Disable power to the socket? */ 3174 3175 /* XXX flush PCI write */ 3176 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3177 3178 /* reset interrupt */ 3179 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, 3180 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT)); 3181 /* XXX flush PCI write */ 3182 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3183 3184 if (sc->sc_ih != NULL) { 3185 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 3186 sc->sc_ih = NULL; 3187 } 3188 3189 return true; 3190 } 3191 3192 static bool 3193 pccbb_resume(device_t dv PMF_FN_ARGS) 3194 { 3195 struct pccbb_softc *sc = device_private(dv); 3196 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3197 bus_space_handle_t base_memh = sc->sc_base_memh; 3198 pcireg_t reg; 3199 3200 pccbb_chipinit(sc); 3201 pccbb_intrinit(sc); 3202 /* setup memory and io space window for CB */ 3203 pccbb_winset(0x1000, sc, sc->sc_memt); 3204 pccbb_winset(0x04, sc, sc->sc_iot); 3205 3206 /* CSC Interrupt: Card detect interrupt on */ 3207 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3208 /* Card detect intr is turned on. */ 3209 reg |= CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; 3210 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3211 /* reset interrupt */ 3212 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3213 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3214 3215 /* 3216 * check for card insertion or removal during suspend period. 3217 * XXX: the code can't cope with card swap (remove then 3218 * insert). how can we detect such situation? 3219 */ 3220 (void)pccbbintr(sc); 3221 3222 sc->sc_pil_intr_enable = 1; 3223 3224 return true; 3225 } 3226
Indexes created Thu Sep 25 16:09:42 GMT 2025