pccbb.c revision 1.185
1 /* $NetBSD: pccbb.c,v 1.185 2009/04/02 00:09:33 dyoung Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: pccbb.c,v 1.185 2009/04/02 00:09:33 dyoung Exp $"); 35 36 /* 37 #define CBB_DEBUG 38 #define SHOW_REGS 39 */ 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/kernel.h> 44 #include <sys/errno.h> 45 #include <sys/ioctl.h> 46 #include <sys/reboot.h> /* for bootverbose */ 47 #include <sys/syslog.h> 48 #include <sys/device.h> 49 #include <sys/malloc.h> 50 #include <sys/proc.h> 51 52 #include <sys/intr.h> 53 #include <sys/bus.h> 54 55 #include <dev/pci/pcivar.h> 56 #include <dev/pci/pcireg.h> 57 #include <dev/pci/pcidevs.h> 58 59 #include <dev/pci/pccbbreg.h> 60 61 #include <dev/cardbus/cardslotvar.h> 62 63 #include <dev/cardbus/cardbusvar.h> 64 65 #include <dev/pcmcia/pcmciareg.h> 66 #include <dev/pcmcia/pcmciavar.h> 67 68 #include <dev/ic/i82365reg.h> 69 #include <dev/pci/pccbbvar.h> 70 71 #ifndef __NetBSD_Version__ 72 struct cfdriver cbb_cd = { 73 NULL, "cbb", DV_DULL 74 }; 75 #endif 76 77 #ifdef CBB_DEBUG 78 #define DPRINTF(x) printf x 79 #define STATIC 80 #else 81 #define DPRINTF(x) 82 #define STATIC static 83 #endif 84 85 int pccbb_burstup = 1; 86 87 /* 88 * delay_ms() is wait in milliseconds. It should be used instead 89 * of delay() if you want to wait more than 1 ms. 90 */ 91 static inline void 92 delay_ms(int millis, void *param) 93 { 94 if (cold) 95 delay(millis * 1000); 96 else 97 tsleep(param, PWAIT, "pccbb", MAX(2, hz * millis / 1000)); 98 } 99 100 int pcicbbmatch(device_t, struct cfdata *, void *); 101 void pccbbattach(device_t, device_t, void *); 102 int pccbbdetach(device_t, int); 103 int pccbbintr(void *); 104 static void pci113x_insert(void *); 105 static int pccbbintr_function(struct pccbb_softc *); 106 107 static int pccbb_detect_card(struct pccbb_softc *); 108 109 static void pccbb_pcmcia_write(struct pccbb_softc *, int, u_int8_t); 110 static u_int8_t pccbb_pcmcia_read(struct pccbb_softc *, int); 111 #define Pcic_read(sc, reg) pccbb_pcmcia_read((sc), (reg)) 112 #define Pcic_write(sc, reg, val) pccbb_pcmcia_write((sc), (reg), (val)) 113 114 STATIC int cb_reset(struct pccbb_softc *); 115 STATIC int cb_detect_voltage(struct pccbb_softc *); 116 STATIC int cbbprint(void *, const char *); 117 118 static int cb_chipset(u_int32_t, int *); 119 STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *, 120 struct pcmciabus_attach_args *); 121 122 STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int); 123 STATIC int pccbb_power(struct pccbb_softc *sc, int); 124 STATIC int pccbb_power_ct(cardbus_chipset_tag_t, int); 125 STATIC int pccbb_cardenable(struct pccbb_softc * sc, int function); 126 #if !rbus 127 static int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 128 static int pccbb_io_close(cardbus_chipset_tag_t, int); 129 static int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 130 static int pccbb_mem_close(cardbus_chipset_tag_t, int); 131 #endif /* !rbus */ 132 static void *pccbb_intr_establish(struct pccbb_softc *, 133 cardbus_intr_line_t irq, int level, int (*ih) (void *), void *sc); 134 static void pccbb_intr_disestablish(struct pccbb_softc *, void *ih); 135 136 static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t, 137 cardbus_intr_line_t irq, int level, int (*ih) (void *), void *sc); 138 static void pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih); 139 140 static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t, int, int); 141 static void pccbb_free_tag(cardbus_chipset_tag_t, cardbustag_t); 142 static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t, cardbustag_t, int); 143 static void pccbb_conf_write(cardbus_chipset_tag_t, cardbustag_t, int, 144 cardbusreg_t); 145 static void pccbb_chipinit(struct pccbb_softc *); 146 static void pccbb_intrinit(struct pccbb_softc *); 147 148 STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 149 struct pcmcia_mem_handle *); 150 STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t, 151 struct pcmcia_mem_handle *); 152 STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 153 bus_size_t, struct pcmcia_mem_handle *, bus_size_t *, int *); 154 STATIC void pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t, int); 155 STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 156 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 157 STATIC void pccbb_pcmcia_io_free(pcmcia_chipset_handle_t, 158 struct pcmcia_io_handle *); 159 STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 160 bus_size_t, struct pcmcia_io_handle *, int *); 161 STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t, int); 162 STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t, 163 struct pcmcia_function *, int, int (*)(void *), void *); 164 STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t, void *); 165 STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t); 166 STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t); 167 STATIC void pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t, int); 168 STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch); 169 170 static int pccbb_pcmcia_wait_ready(struct pccbb_softc *); 171 static void pccbb_pcmcia_delay(struct pccbb_softc *, int, const char *); 172 173 static void pccbb_pcmcia_do_io_map(struct pccbb_softc *, int); 174 static void pccbb_pcmcia_do_mem_map(struct pccbb_softc *, int); 175 176 /* bus-space allocation and deallocation functions */ 177 #if rbus 178 179 static int pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t, rbus_tag_t, 180 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 181 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp); 182 static int pccbb_rbus_cb_space_free(cardbus_chipset_tag_t, rbus_tag_t, 183 bus_space_handle_t, bus_size_t); 184 185 #endif /* rbus */ 186 187 #if rbus 188 189 static int pccbb_open_win(struct pccbb_softc *, bus_space_tag_t, 190 bus_addr_t, bus_size_t, bus_space_handle_t, int flags); 191 static int pccbb_close_win(struct pccbb_softc *, bus_space_tag_t, 192 bus_space_handle_t, bus_size_t); 193 static int pccbb_winlist_insert(struct pccbb_win_chain_head *, bus_addr_t, 194 bus_size_t, bus_space_handle_t, int); 195 static int pccbb_winlist_delete(struct pccbb_win_chain_head *, 196 bus_space_handle_t, bus_size_t); 197 static void pccbb_winset(bus_addr_t align, struct pccbb_softc *, 198 bus_space_tag_t); 199 void pccbb_winlist_show(struct pccbb_win_chain *); 200 201 #endif /* rbus */ 202 203 /* for config_defer */ 204 static void pccbb_pci_callback(device_t); 205 206 static bool pccbb_suspend(device_t PMF_FN_PROTO); 207 static bool pccbb_resume(device_t PMF_FN_PROTO); 208 209 #if defined SHOW_REGS 210 static void cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, 211 bus_space_tag_t memt, bus_space_handle_t memh); 212 #endif 213 214 CFATTACH_DECL3_NEW(cbb_pci, sizeof(struct pccbb_softc), 215 pcicbbmatch, pccbbattach, pccbbdetach, NULL, NULL, NULL, 216 DVF_DETACH_SHUTDOWN); 217 218 static const struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 219 pccbb_pcmcia_mem_alloc, 220 pccbb_pcmcia_mem_free, 221 pccbb_pcmcia_mem_map, 222 pccbb_pcmcia_mem_unmap, 223 pccbb_pcmcia_io_alloc, 224 pccbb_pcmcia_io_free, 225 pccbb_pcmcia_io_map, 226 pccbb_pcmcia_io_unmap, 227 pccbb_pcmcia_intr_establish, 228 pccbb_pcmcia_intr_disestablish, 229 pccbb_pcmcia_socket_enable, 230 pccbb_pcmcia_socket_disable, 231 pccbb_pcmcia_socket_settype, 232 pccbb_pcmcia_card_detect 233 }; 234 235 #if rbus 236 static const struct cardbus_functions pccbb_funcs = { 237 pccbb_rbus_cb_space_alloc, 238 pccbb_rbus_cb_space_free, 239 pccbb_cb_intr_establish, 240 pccbb_cb_intr_disestablish, 241 pccbb_ctrl, 242 pccbb_power_ct, 243 pccbb_make_tag, 244 pccbb_free_tag, 245 pccbb_conf_read, 246 pccbb_conf_write, 247 }; 248 #else 249 static const struct cardbus_functions pccbb_funcs = { 250 pccbb_ctrl, 251 pccbb_power_ct, 252 pccbb_mem_open, 253 pccbb_mem_close, 254 pccbb_io_open, 255 pccbb_io_close, 256 pccbb_cb_intr_establish, 257 pccbb_cb_intr_disestablish, 258 pccbb_make_tag, 259 pccbb_conf_read, 260 pccbb_conf_write, 261 }; 262 #endif 263 264 int 265 pcicbbmatch(device_t parent, struct cfdata *match, void *aux) 266 { 267 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 268 269 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 270 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 271 PCI_INTERFACE(pa->pa_class) == 0) { 272 return 1; 273 } 274 275 return 0; 276 } 277 278 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 279 | ((prod) << PCI_PRODUCT_SHIFT)) 280 281 const struct yenta_chipinfo { 282 pcireg_t yc_id; /* vendor tag | product tag */ 283 int yc_chiptype; 284 int yc_flags; 285 } yc_chipsets[] = { 286 /* Texas Instruments chips */ 287 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 288 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 289 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 290 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 291 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI125X, 292 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 293 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 294 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 295 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 296 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 297 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 298 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 299 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI125X, 300 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 301 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI125X, 302 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 303 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 304 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 305 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 306 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 307 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI1420, 308 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 309 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI125X, 310 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 311 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 312 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 313 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1520), CB_TI12XX, 314 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 315 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4410YENTA), CB_TI12XX, 316 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 317 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4520YENTA), CB_TI12XX, 318 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 319 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI7420YENTA), CB_TI12XX, 320 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 321 322 /* Ricoh chips */ 323 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 324 PCCBB_PCMCIA_MEM_32}, 325 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 326 PCCBB_PCMCIA_MEM_32}, 327 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 328 PCCBB_PCMCIA_MEM_32}, 329 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 330 PCCBB_PCMCIA_MEM_32}, 331 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 332 PCCBB_PCMCIA_MEM_32}, 333 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 334 PCCBB_PCMCIA_MEM_32}, 335 336 /* Toshiba products */ 337 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 338 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 339 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 340 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 341 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 342 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 343 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 344 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 345 346 /* Cirrus Logic products */ 347 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 348 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 349 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 350 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 351 352 /* O2 Micro products */ 353 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6729), 354 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 355 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6730), 356 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 357 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6832), 358 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 359 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6836), 360 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 361 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6872), 362 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 363 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6922), 364 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 365 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6933), 366 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 367 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6972), 368 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 369 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_7223), 370 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 371 372 /* sentinel, or Generic chip */ 373 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 374 }; 375 376 static int 377 cb_chipset(u_int32_t pci_id, int *flagp) 378 { 379 const struct yenta_chipinfo *yc; 380 381 /* Loop over except the last default entry. */ 382 for (yc = yc_chipsets; yc < yc_chipsets + 383 __arraycount(yc_chipsets) - 1; yc++) 384 if (pci_id == yc->yc_id) 385 break; 386 387 if (flagp != NULL) 388 *flagp = yc->yc_flags; 389 390 return (yc->yc_chiptype); 391 } 392 393 void 394 pccbbattach(device_t parent, device_t self, void *aux) 395 { 396 struct pccbb_softc *sc = device_private(self); 397 struct pci_attach_args *pa = aux; 398 pci_chipset_tag_t pc = pa->pa_pc; 399 pcireg_t busreg, reg, sock_base; 400 bus_addr_t sockbase; 401 char devinfo[256]; 402 int flags; 403 404 #ifdef __HAVE_PCCBB_ATTACH_HOOK 405 pccbb_attach_hook(parent, self, pa); 406 #endif 407 408 sc->sc_dev = self; 409 410 callout_init(&sc->sc_insert_ch, 0); 411 callout_setfunc(&sc->sc_insert_ch, pci113x_insert, sc); 412 413 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 414 415 aprint_naive("\n"); 416 417 pci_devinfo(pa->pa_id, 0, 0, devinfo, sizeof(devinfo)); 418 aprint_normal(": %s (rev. 0x%02x)", devinfo, 419 PCI_REVISION(pa->pa_class)); 420 DPRINTF((" (chipflags %x)", flags)); 421 aprint_normal("\n"); 422 423 TAILQ_INIT(&sc->sc_memwindow); 424 TAILQ_INIT(&sc->sc_iowindow); 425 426 #if rbus 427 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 428 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 429 430 #if 0 431 printf("pa->pa_memt: %08x vs rbus_mem->rb_bt: %08x\n", 432 pa->pa_memt, sc->sc_rbus_memt->rb_bt); 433 #endif 434 #endif /* rbus */ 435 436 sc->sc_flags &= ~CBB_MEMHMAPPED; 437 438 /* 439 * MAP socket registers and ExCA registers on memory-space 440 * When no valid address is set on socket base registers (on pci 441 * config space), get it not polite way. 442 */ 443 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 444 445 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 446 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 447 /* The address must be valid. */ 448 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 449 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, &sc->sc_base_size)) { 450 aprint_error_dev(self, 451 "can't map socket base address 0x%lx\n", 452 (unsigned long)sock_base); 453 /* 454 * I think it's funny: socket base registers must be 455 * mapped on memory space, but ... 456 */ 457 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 458 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 459 &sc->sc_base_size)) { 460 aprint_error_dev(self, 461 "can't map socket base address" 462 " 0x%lx: io mode\n", 463 (unsigned long)sockbase); 464 /* give up... allocate reg space via rbus. */ 465 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 466 } else 467 sc->sc_flags |= CBB_MEMHMAPPED; 468 } else { 469 DPRINTF(("%s: socket base address 0x%lx\n", 470 device_xname(self), 471 (unsigned long)sockbase)); 472 sc->sc_flags |= CBB_MEMHMAPPED; 473 } 474 } 475 476 sc->sc_mem_start = 0; /* XXX */ 477 sc->sc_mem_end = 0xffffffff; /* XXX */ 478 479 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 480 481 /* pccbb_machdep.c end */ 482 483 #if defined CBB_DEBUG 484 { 485 static const char *intrname[] = { "NON", "A", "B", "C", "D" }; 486 aprint_debug_dev(self, "intrpin %s, intrtag %d\n", 487 intrname[pa->pa_intrpin], pa->pa_intrline); 488 } 489 #endif 490 491 /* setup softc */ 492 sc->sc_pc = pc; 493 sc->sc_iot = pa->pa_iot; 494 sc->sc_memt = pa->pa_memt; 495 sc->sc_dmat = pa->pa_dmat; 496 sc->sc_tag = pa->pa_tag; 497 498 memcpy(&sc->sc_pa, pa, sizeof(*pa)); 499 500 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 501 502 /* Disable legacy register mapping. */ 503 switch (sc->sc_chipset) { 504 case CB_RX5C46X: /* fallthrough */ 505 #if 0 506 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 507 case CB_RX5C47X: 508 #endif 509 /* 510 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 511 * cannot be disabled by substituting 0 into PCI_LEGACY 512 * register. Ricoh CardBus bridges have special bits on Bridge 513 * control reg (addr 0x3e on PCI config space). 514 */ 515 reg = pci_conf_read(pc, pa->pa_tag, PCI_BRIDGE_CONTROL_REG); 516 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 517 pci_conf_write(pc, pa->pa_tag, PCI_BRIDGE_CONTROL_REG, reg); 518 break; 519 520 default: 521 /* XXX I don't know proper way to kill legacy I/O. */ 522 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 523 break; 524 } 525 526 if (!pmf_device_register(self, pccbb_suspend, pccbb_resume)) 527 aprint_error_dev(self, "couldn't establish power handler\n"); 528 529 config_defer(self, pccbb_pci_callback); 530 } 531 532 int 533 pccbbdetach(device_t self, int flags) 534 { 535 struct pccbb_softc *sc = device_private(self); 536 pci_chipset_tag_t pc = sc->sc_pa.pa_pc; 537 bus_space_tag_t bmt = sc->sc_base_memt; 538 bus_space_handle_t bmh = sc->sc_base_memh; 539 uint32_t sockmask; 540 int rc; 541 542 if ((rc = config_detach_children(self, flags)) != 0) 543 return rc; 544 545 if (!LIST_EMPTY(&sc->sc_pil)) { 546 panic("%s: interrupt handlers still registered", 547 device_xname(self)); 548 return EBUSY; 549 } 550 551 if (sc->sc_ih != NULL) { 552 pci_intr_disestablish(pc, sc->sc_ih); 553 sc->sc_ih = NULL; 554 } 555 556 /* CSC Interrupt: turn off card detect and power cycle interrupts */ 557 sockmask = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 558 sockmask &= ~(CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | 559 CB_SOCKET_MASK_POWER); 560 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, sockmask); 561 /* reset interrupt */ 562 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 563 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 564 565 switch (sc->sc_flags & (CBB_MEMHMAPPED|CBB_SPECMAPPED)) { 566 case CBB_MEMHMAPPED: 567 bus_space_unmap(bmt, bmh, sc->sc_base_size); 568 break; 569 case CBB_MEMHMAPPED|CBB_SPECMAPPED: 570 #if rbus 571 { 572 pcireg_t sockbase; 573 574 sockbase = pci_conf_read(pc, sc->sc_tag, PCI_SOCKBASE); 575 rbus_space_free(sc->sc_rbus_memt, bmh, 0x1000, 576 NULL); 577 } 578 #else 579 bus_space_free(bmt, bmh, 0x1000); 580 #endif 581 } 582 sc->sc_flags &= ~(CBB_MEMHMAPPED|CBB_SPECMAPPED); 583 584 if (!TAILQ_EMPTY(&sc->sc_iowindow)) 585 aprint_error_dev(self, "i/o windows not empty"); 586 if (!TAILQ_EMPTY(&sc->sc_memwindow)) 587 aprint_error_dev(self, "memory windows not empty"); 588 589 callout_stop(&sc->sc_insert_ch); 590 callout_destroy(&sc->sc_insert_ch); 591 return 0; 592 } 593 594 /* 595 * static void pccbb_pci_callback(device_t self) 596 * 597 * The actual attach routine: get memory space for YENTA register 598 * space, setup YENTA register and route interrupt. 599 * 600 * This function should be deferred because this device may obtain 601 * memory space dynamically. This function must avoid obtaining 602 * memory area which has already kept for another device. 603 */ 604 static void 605 pccbb_pci_callback(device_t self) 606 { 607 struct pccbb_softc *sc = device_private(self); 608 pci_chipset_tag_t pc = sc->sc_pc; 609 bus_addr_t sockbase; 610 struct cbslot_attach_args cba; 611 struct pcmciabus_attach_args paa; 612 struct cardslot_attach_args caa; 613 device_t csc; 614 615 if (!(sc->sc_flags & CBB_MEMHMAPPED)) { 616 /* The socket registers aren't mapped correctly. */ 617 #if rbus 618 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 619 (sc->sc_chipset == CB_RX5C47X 620 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 621 0, &sockbase, &sc->sc_base_memh)) { 622 return; 623 } 624 sc->sc_base_memt = sc->sc_memt; 625 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 626 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 627 device_xname(self), (unsigned long)sockbase, 628 (unsigned long)pci_conf_read(pc, sc->sc_tag, 629 PCI_SOCKBASE))); 630 #else 631 sc->sc_base_memt = sc->sc_memt; 632 #if !defined CBB_PCI_BASE 633 #define CBB_PCI_BASE 0x20000000 634 #endif 635 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 636 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 637 /* cannot allocate memory space */ 638 return; 639 } 640 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 641 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 642 device_xname(self), (unsigned long)sock_base, 643 (unsigned long)pci_conf_read(pc, 644 sc->sc_tag, PCI_SOCKBASE))); 645 #endif 646 sc->sc_flags |= CBB_MEMHMAPPED; 647 } 648 649 /* clear data structure for child device interrupt handlers */ 650 LIST_INIT(&sc->sc_pil); 651 652 /* bus bridge initialization */ 653 pccbb_chipinit(sc); 654 655 sc->sc_pil_intr_enable = 1; 656 657 { 658 u_int32_t sockstat; 659 660 sockstat = bus_space_read_4(sc->sc_base_memt, 661 sc->sc_base_memh, CB_SOCKET_STAT); 662 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 663 sc->sc_flags |= CBB_CARDEXIST; 664 } 665 } 666 667 /* 668 * attach cardbus 669 */ 670 { 671 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 672 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 673 674 /* initialize cbslot_attach */ 675 cba.cba_iot = sc->sc_iot; 676 cba.cba_memt = sc->sc_memt; 677 cba.cba_dmat = sc->sc_dmat; 678 cba.cba_bus = (busreg >> 8) & 0x0ff; 679 cba.cba_cc = (void *)sc; 680 cba.cba_cf = &pccbb_funcs; 681 cba.cba_intrline = 0; /* XXX dummy */ 682 683 #if rbus 684 cba.cba_rbus_iot = sc->sc_rbus_iot; 685 cba.cba_rbus_memt = sc->sc_rbus_memt; 686 #endif 687 688 cba.cba_cacheline = PCI_CACHELINE(bhlc); 689 cba.cba_max_lattimer = PCI_LATTIMER(bhlc); 690 691 aprint_verbose_dev(self, 692 "cacheline 0x%x lattimer 0x%x\n", 693 cba.cba_cacheline, 694 cba.cba_max_lattimer); 695 aprint_verbose_dev(self, "bhlc 0x%x\n", bhlc); 696 #if defined SHOW_REGS 697 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 698 sc->sc_base_memh); 699 #endif 700 } 701 702 pccbb_pcmcia_attach_setup(sc, &paa); 703 caa.caa_cb_attach = NULL; 704 if (cba.cba_bus == 0) 705 aprint_error_dev(self, 706 "secondary bus number uninitialized; try PCI_BUS_FIXUP\n"); 707 else 708 caa.caa_cb_attach = &cba; 709 caa.caa_16_attach = &paa; 710 711 pccbb_intrinit(sc); 712 713 if (NULL != (csc = config_found_ia(self, "pcmciaslot", &caa, 714 cbbprint))) { 715 DPRINTF(("%s: found cardslot\n", __func__)); 716 sc->sc_csc = device_private(csc); 717 } 718 719 return; 720 } 721 722 723 724 725 726 /* 727 * static void pccbb_chipinit(struct pccbb_softc *sc) 728 * 729 * This function initialize YENTA chip registers listed below: 730 * 1) PCI command reg, 731 * 2) PCI and CardBus latency timer, 732 * 3) route PCI interrupt, 733 * 4) close all memory and io windows. 734 * 5) turn off bus power. 735 * 6) card detect and power cycle interrupts on. 736 * 7) clear interrupt 737 */ 738 static void 739 pccbb_chipinit(struct pccbb_softc *sc) 740 { 741 pci_chipset_tag_t pc = sc->sc_pc; 742 pcitag_t tag = sc->sc_tag; 743 bus_space_tag_t bmt = sc->sc_base_memt; 744 bus_space_handle_t bmh = sc->sc_base_memh; 745 pcireg_t bcr, bhlc, cbctl, csr, lscp, mfunc, mrburst, slotctl, sockctl, 746 sysctrl; 747 748 /* 749 * Set PCI command reg. 750 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 751 */ 752 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 753 /* I believe it is harmless. */ 754 csr |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 755 PCI_COMMAND_MASTER_ENABLE); 756 757 /* All O2 Micro chips have broken parity-error reporting 758 * until proven otherwise. The OZ6933 PCI-CardBus Bridge 759 * is known to have the defect---see PR kern/38698. 760 */ 761 if (sc->sc_chipset != CB_O2MICRO) 762 csr |= PCI_COMMAND_PARITY_ENABLE; 763 764 csr |= PCI_COMMAND_SERR_ENABLE; 765 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 766 767 /* 768 * Set CardBus latency timer. 769 */ 770 lscp = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 771 if (PCI_CB_LATENCY(lscp) < 0x20) { 772 lscp &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 773 lscp |= (0x20 << PCI_CB_LATENCY_SHIFT); 774 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, lscp); 775 } 776 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 777 PCI_CB_LATENCY(lscp), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 778 779 /* 780 * Set PCI latency timer. 781 */ 782 bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG); 783 if (PCI_LATTIMER(bhlc) < 0x10) { 784 bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 785 bhlc |= (0x10 << PCI_LATTIMER_SHIFT); 786 pci_conf_write(pc, tag, PCI_BHLC_REG, bhlc); 787 } 788 DPRINTF(("PCI latency timer 0x%x (%x)\n", 789 PCI_LATTIMER(bhlc), pci_conf_read(pc, tag, PCI_BHLC_REG))); 790 791 792 /* Route functional interrupts to PCI. */ 793 bcr = pci_conf_read(pc, tag, PCI_BRIDGE_CONTROL_REG); 794 bcr |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 795 bcr |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 796 /* assert reset */ 797 bcr |= PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT; 798 /* Set master abort mode to 1, forward SERR# from secondary 799 * to primary, and detect parity errors on secondary. 800 */ 801 bcr |= PCI_BRIDGE_CONTROL_MABRT << PCI_BRIDGE_CONTROL_SHIFT; 802 bcr |= PCI_BRIDGE_CONTROL_SERR << PCI_BRIDGE_CONTROL_SHIFT; 803 bcr |= PCI_BRIDGE_CONTROL_PERE << PCI_BRIDGE_CONTROL_SHIFT; 804 pci_conf_write(pc, tag, PCI_BRIDGE_CONTROL_REG, bcr); 805 806 switch (sc->sc_chipset) { 807 case CB_TI113X: 808 cbctl = pci_conf_read(pc, tag, PCI_CBCTRL); 809 /* This bit is shared, but may read as 0 on some chips, so set 810 it explicitly on both functions. */ 811 cbctl |= PCI113X_CBCTRL_PCI_IRQ_ENA; 812 /* CSC intr enable */ 813 cbctl |= PCI113X_CBCTRL_PCI_CSC; 814 /* functional intr prohibit | prohibit ISA routing */ 815 cbctl &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 816 pci_conf_write(pc, tag, PCI_CBCTRL, cbctl); 817 break; 818 819 case CB_TI1420: 820 sysctrl = pci_conf_read(pc, tag, PCI_SYSCTRL); 821 mrburst = pccbb_burstup 822 ? PCI1420_SYSCTRL_MRBURST : PCI1420_SYSCTRL_MRBURSTDN; 823 if ((sysctrl & PCI1420_SYSCTRL_MRBURST) == mrburst) { 824 printf("%s: %swrite bursts enabled\n", 825 device_xname(sc->sc_dev), 826 pccbb_burstup ? "read/" : ""); 827 } else if (pccbb_burstup) { 828 printf("%s: enabling read/write bursts\n", 829 device_xname(sc->sc_dev)); 830 sysctrl |= PCI1420_SYSCTRL_MRBURST; 831 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 832 } else { 833 printf("%s: disabling read bursts, " 834 "enabling write bursts\n", 835 device_xname(sc->sc_dev)); 836 sysctrl |= PCI1420_SYSCTRL_MRBURSTDN; 837 sysctrl &= ~PCI1420_SYSCTRL_MRBURSTUP; 838 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 839 } 840 /*FALLTHROUGH*/ 841 case CB_TI12XX: 842 /* 843 * Some TI 12xx (and [14][45]xx) based pci cards 844 * sometimes have issues with the MFUNC register not 845 * being initialized due to a bad EEPROM on board. 846 * Laptops that this matters on have this register 847 * properly initialized. 848 * 849 * The TI125X parts have a different register. 850 */ 851 mfunc = pci_conf_read(pc, tag, PCI12XX_MFUNC); 852 if (mfunc == 0) { 853 mfunc &= ~PCI12XX_MFUNC_PIN0; 854 mfunc |= PCI12XX_MFUNC_PIN0_INTA; 855 if ((pci_conf_read(pc, tag, PCI_SYSCTRL) & 856 PCI12XX_SYSCTRL_INTRTIE) == 0) { 857 mfunc &= ~PCI12XX_MFUNC_PIN1; 858 mfunc |= PCI12XX_MFUNC_PIN1_INTB; 859 } 860 pci_conf_write(pc, tag, PCI12XX_MFUNC, mfunc); 861 } 862 /* fallthrough */ 863 864 case CB_TI125X: 865 /* 866 * Disable zoom video. Some machines initialize this 867 * improperly and experience has shown that this helps 868 * prevent strange behavior. 869 */ 870 pci_conf_write(pc, tag, PCI12XX_MMCTRL, 0); 871 872 sysctrl = pci_conf_read(pc, tag, PCI_SYSCTRL); 873 sysctrl |= PCI12XX_SYSCTRL_VCCPROT; 874 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 875 cbctl = pci_conf_read(pc, tag, PCI_CBCTRL); 876 cbctl |= PCI12XX_CBCTRL_CSC; 877 pci_conf_write(pc, tag, PCI_CBCTRL, cbctl); 878 break; 879 880 case CB_TOPIC95B: 881 sockctl = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 882 sockctl |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 883 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, sockctl); 884 slotctl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 885 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 886 device_xname(sc->sc_dev), slotctl)); 887 slotctl |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 888 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 889 slotctl &= ~TOPIC_SLOT_CTRL_SWDETECT; 890 DPRINTF(("0x%x\n", slotctl)); 891 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slotctl); 892 break; 893 894 case CB_TOPIC97: 895 slotctl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 896 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 897 device_xname(sc->sc_dev), slotctl)); 898 slotctl |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 899 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 900 slotctl &= ~TOPIC_SLOT_CTRL_SWDETECT; 901 slotctl |= TOPIC97_SLOT_CTRL_PCIINT; 902 slotctl &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 903 DPRINTF(("0x%x\n", slotctl)); 904 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slotctl); 905 /* make sure to assert LV card support bits */ 906 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 907 0x800 + 0x3e, 908 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 909 0x800 + 0x3e) | 0x03); 910 break; 911 } 912 913 /* Close all memory and I/O windows. */ 914 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 915 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 916 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 917 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 918 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 919 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 920 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 921 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 922 923 /* reset 16-bit pcmcia bus */ 924 bus_space_write_1(bmt, bmh, 0x800 + PCIC_INTR, 925 bus_space_read_1(bmt, bmh, 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 926 927 /* turn off power */ 928 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 929 } 930 931 static void 932 pccbb_intrinit(struct pccbb_softc *sc) 933 { 934 pcireg_t sockmask; 935 const char *intrstr = NULL; 936 pci_intr_handle_t ih; 937 pci_chipset_tag_t pc = sc->sc_pc; 938 bus_space_tag_t bmt = sc->sc_base_memt; 939 bus_space_handle_t bmh = sc->sc_base_memh; 940 941 /* Map and establish the interrupt. */ 942 if (pci_intr_map(&sc->sc_pa, &ih)) { 943 aprint_error_dev(sc->sc_dev, "couldn't map interrupt\n"); 944 return; 945 } 946 intrstr = pci_intr_string(pc, ih); 947 948 /* 949 * XXX pccbbintr should be called under the priority lower 950 * than any other hard interrupts. 951 */ 952 KASSERT(sc->sc_ih == NULL); 953 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 954 955 if (sc->sc_ih == NULL) { 956 aprint_error_dev(sc->sc_dev, "couldn't establish interrupt"); 957 if (intrstr != NULL) 958 aprint_error(" at %s\n", intrstr); 959 else 960 aprint_error("\n"); 961 return; 962 } 963 964 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 965 966 /* CSC Interrupt: Card detect and power cycle interrupts on */ 967 sockmask = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 968 sockmask |= CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | 969 CB_SOCKET_MASK_POWER; 970 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, sockmask); 971 /* reset interrupt */ 972 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 973 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 974 } 975 976 /* 977 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 978 * struct pcmciabus_attach_args *paa) 979 * 980 * This function attaches 16-bit PCcard bus. 981 */ 982 STATIC void 983 pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 984 struct pcmciabus_attach_args *paa) 985 { 986 #if rbus 987 rbus_tag_t rb; 988 #endif 989 /* 990 * We need to do a few things here: 991 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 992 * setting the IRQ numbers to 0. 993 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 994 * routing of CSC interrupts (e.g. card removal) to PCI while in 995 * PCMCIA mode. We just leave this set all the time. 996 * 3) Enable card insertion/removal interrupts in case the chip also 997 * needs that while in PCMCIA mode. 998 * 4) Clear any pending CSC interrupt. 999 */ 1000 Pcic_write(sc, PCIC_INTR, PCIC_INTR_ENABLE); 1001 if (sc->sc_chipset == CB_TI113X) { 1002 Pcic_write(sc, PCIC_CSC_INTR, 0); 1003 } else { 1004 Pcic_write(sc, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 1005 Pcic_read(sc, PCIC_CSC); 1006 } 1007 1008 /* initialize pcmcia bus attachment */ 1009 paa->paa_busname = "pcmcia"; 1010 paa->pct = &pccbb_pcmcia_funcs; 1011 paa->pch = sc; 1012 paa->iobase = 0; /* I don't use them */ 1013 paa->iosize = 0; 1014 #if rbus 1015 rb = sc->sc_rbus_iot; 1016 paa->iobase = rb->rb_start + rb->rb_offset; 1017 paa->iosize = rb->rb_end - rb->rb_start; 1018 #endif 1019 1020 return; 1021 } 1022 1023 /* 1024 * int pccbbintr(arg) 1025 * void *arg; 1026 * This routine handles the interrupt from Yenta PCI-CardBus bridge 1027 * itself. 1028 */ 1029 int 1030 pccbbintr(void *arg) 1031 { 1032 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1033 u_int32_t sockevent, sockstate; 1034 bus_space_tag_t memt = sc->sc_base_memt; 1035 bus_space_handle_t memh = sc->sc_base_memh; 1036 1037 if (!device_has_power(sc->sc_dev)) 1038 return 0; 1039 1040 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 1041 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 1042 Pcic_read(sc, PCIC_CSC); 1043 1044 if (sockevent != 0) { 1045 aprint_debug("%s: enter sockevent %" PRIx32 "\n", __func__, 1046 sockevent); 1047 } 1048 1049 /* XXX sockevent == CB_SOCKET_EVENT_CSTS|CB_SOCKET_EVENT_POWER 1050 * does occur in the wild. Check for a _POWER event before 1051 * possibly exiting because of an _CSTS event. 1052 */ 1053 if (sockevent & CB_SOCKET_EVENT_POWER) { 1054 DPRINTF(("Powercycling because of socket event\n")); 1055 /* XXX: Does not happen when attaching a 16-bit card */ 1056 sc->sc_pwrcycle++; 1057 wakeup(&sc->sc_pwrcycle); 1058 } 1059 1060 /* Sometimes a change of CSTSCHG# accompanies the first 1061 * interrupt from an Atheros WLAN. That generates a 1062 * CB_SOCKET_EVENT_CSTS event on the bridge. The event 1063 * isn't interesting to pccbb(4), so we used to ignore the 1064 * interrupt. Now, let the child devices try to handle 1065 * the interrupt, instead. The Atheros NIC produces 1066 * interrupts more reliably, now: used to be that it would 1067 * only interrupt if the driver avoided powering down the 1068 * NIC's cardslot, and then the NIC would only work after 1069 * it was reset a second time. 1070 */ 1071 if (sockevent == 0 || 1072 (sockevent & ~(CB_SOCKET_EVENT_POWER|CB_SOCKET_EVENT_CD)) != 0) { 1073 /* This intr is not for me: it may be for my child devices. */ 1074 if (sc->sc_pil_intr_enable) { 1075 return pccbbintr_function(sc); 1076 } else { 1077 return 0; 1078 } 1079 } 1080 1081 if (sockevent & CB_SOCKET_EVENT_CD) { 1082 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1083 if (0x00 != (sockstate & CB_SOCKET_STAT_CD)) { 1084 /* A card should be removed. */ 1085 if (sc->sc_flags & CBB_CARDEXIST) { 1086 DPRINTF(("%s: 0x%08x", 1087 device_xname(sc->sc_dev), sockevent)); 1088 DPRINTF((" card removed, 0x%08x\n", sockstate)); 1089 sc->sc_flags &= ~CBB_CARDEXIST; 1090 if (sc->sc_csc->sc_status & 1091 CARDSLOT_STATUS_CARD_16) { 1092 cardslot_event_throw(sc->sc_csc, 1093 CARDSLOT_EVENT_REMOVAL_16); 1094 } else if (sc->sc_csc->sc_status & 1095 CARDSLOT_STATUS_CARD_CB) { 1096 /* Cardbus intr removed */ 1097 cardslot_event_throw(sc->sc_csc, 1098 CARDSLOT_EVENT_REMOVAL_CB); 1099 } 1100 } else if (sc->sc_flags & CBB_INSERTING) { 1101 sc->sc_flags &= ~CBB_INSERTING; 1102 callout_stop(&sc->sc_insert_ch); 1103 } 1104 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 1105 /* 1106 * The pccbbintr may called from powerdown hook when 1107 * the system resumed, to detect the card 1108 * insertion/removal during suspension. 1109 */ 1110 (sc->sc_flags & CBB_CARDEXIST) == 0) { 1111 if (sc->sc_flags & CBB_INSERTING) { 1112 callout_stop(&sc->sc_insert_ch); 1113 } 1114 callout_schedule(&sc->sc_insert_ch, hz / 5); 1115 sc->sc_flags |= CBB_INSERTING; 1116 } 1117 } 1118 1119 return (1); 1120 } 1121 1122 /* 1123 * static int pccbbintr_function(struct pccbb_softc *sc) 1124 * 1125 * This function calls each interrupt handler registered at the 1126 * bridge. The interrupt handlers are called in registered order. 1127 */ 1128 static int 1129 pccbbintr_function(struct pccbb_softc *sc) 1130 { 1131 int retval = 0, val; 1132 struct pccbb_intrhand_list *pil; 1133 int s; 1134 1135 LIST_FOREACH(pil, &sc->sc_pil, pil_next) { 1136 s = splraiseipl(pil->pil_icookie); 1137 val = (*pil->pil_func)(pil->pil_arg); 1138 splx(s); 1139 1140 retval = retval == 1 ? 1 : 1141 retval == 0 ? val : val != 0 ? val : retval; 1142 } 1143 1144 return retval; 1145 } 1146 1147 static void 1148 pci113x_insert(void *arg) 1149 { 1150 struct pccbb_softc *sc = arg; 1151 u_int32_t sockevent, sockstate; 1152 1153 if (!(sc->sc_flags & CBB_INSERTING)) { 1154 /* We add a card only under inserting state. */ 1155 return; 1156 } 1157 sc->sc_flags &= ~CBB_INSERTING; 1158 1159 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1160 CB_SOCKET_EVENT); 1161 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1162 CB_SOCKET_STAT); 1163 1164 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1165 DPRINTF(("%s: 0x%08x", device_xname(sc->sc_dev), sockevent)); 1166 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1167 sc->sc_flags |= CBB_CARDEXIST; 1168 /* call pccard interrupt handler here */ 1169 if (sockstate & CB_SOCKET_STAT_16BIT) { 1170 /* 16-bit card found */ 1171 cardslot_event_throw(sc->sc_csc, 1172 CARDSLOT_EVENT_INSERTION_16); 1173 } else if (sockstate & CB_SOCKET_STAT_CB) { 1174 /* cardbus card found */ 1175 cardslot_event_throw(sc->sc_csc, 1176 CARDSLOT_EVENT_INSERTION_CB); 1177 } else { 1178 /* who are you? */ 1179 } 1180 } else { 1181 callout_schedule(&sc->sc_insert_ch, hz / 10); 1182 } 1183 } 1184 1185 #define PCCBB_PCMCIA_OFFSET 0x800 1186 static u_int8_t 1187 pccbb_pcmcia_read(struct pccbb_softc *sc, int reg) 1188 { 1189 bus_space_barrier(sc->sc_base_memt, sc->sc_base_memh, 1190 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1191 1192 return bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 1193 PCCBB_PCMCIA_OFFSET + reg); 1194 } 1195 1196 static void 1197 pccbb_pcmcia_write(struct pccbb_softc *sc, int reg, u_int8_t val) 1198 { 1199 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 1200 PCCBB_PCMCIA_OFFSET + reg, val); 1201 1202 bus_space_barrier(sc->sc_base_memt, sc->sc_base_memh, 1203 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1204 } 1205 1206 /* 1207 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1208 */ 1209 STATIC int 1210 pccbb_ctrl(cardbus_chipset_tag_t ct, int command) 1211 { 1212 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1213 1214 switch (command) { 1215 case CARDBUS_CD: 1216 if (2 == pccbb_detect_card(sc)) { 1217 int retval = 0; 1218 int status = cb_detect_voltage(sc); 1219 if (PCCARD_VCC_5V & status) { 1220 retval |= CARDBUS_5V_CARD; 1221 } 1222 if (PCCARD_VCC_3V & status) { 1223 retval |= CARDBUS_3V_CARD; 1224 } 1225 if (PCCARD_VCC_XV & status) { 1226 retval |= CARDBUS_XV_CARD; 1227 } 1228 if (PCCARD_VCC_YV & status) { 1229 retval |= CARDBUS_YV_CARD; 1230 } 1231 return retval; 1232 } else { 1233 return 0; 1234 } 1235 case CARDBUS_RESET: 1236 return cb_reset(sc); 1237 case CARDBUS_IO_ENABLE: /* fallthrough */ 1238 case CARDBUS_IO_DISABLE: /* fallthrough */ 1239 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1240 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1241 case CARDBUS_BM_ENABLE: /* fallthrough */ 1242 case CARDBUS_BM_DISABLE: /* fallthrough */ 1243 /* XXX: I think we don't need to call this function below. */ 1244 return pccbb_cardenable(sc, command); 1245 } 1246 1247 return 0; 1248 } 1249 1250 STATIC int 1251 pccbb_power_ct(cardbus_chipset_tag_t ct, int command) 1252 { 1253 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1254 1255 return pccbb_power(sc, command); 1256 } 1257 1258 /* 1259 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1260 * This function returns true when it succeeds and returns false when 1261 * it fails. 1262 */ 1263 STATIC int 1264 pccbb_power(struct pccbb_softc *sc, int command) 1265 { 1266 u_int32_t status, osock_ctrl, sock_ctrl, reg_ctrl; 1267 bus_space_tag_t memt = sc->sc_base_memt; 1268 bus_space_handle_t memh = sc->sc_base_memh; 1269 int on = 0, pwrcycle, s, times; 1270 struct timeval before, after, diff; 1271 1272 DPRINTF(("pccbb_power: %s and %s [0x%x]\n", 1273 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1274 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1275 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1276 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1277 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1278 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1279 "UNKNOWN", 1280 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1281 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1282 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1283 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1284 "UNKNOWN", command)); 1285 1286 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1287 osock_ctrl = sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1288 1289 switch (command & CARDBUS_VCCMASK) { 1290 case CARDBUS_VCC_UC: 1291 break; 1292 case CARDBUS_VCC_5V: 1293 on++; 1294 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1295 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1296 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1297 } else { 1298 aprint_error_dev(sc->sc_dev, 1299 "BAD voltage request: no 5 V card\n"); 1300 return 0; 1301 } 1302 break; 1303 case CARDBUS_VCC_3V: 1304 on++; 1305 if (CB_SOCKET_STAT_3VCARD & status) { 1306 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1307 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1308 } else { 1309 aprint_error_dev(sc->sc_dev, 1310 "BAD voltage request: no 3.3 V card\n"); 1311 return 0; 1312 } 1313 break; 1314 case CARDBUS_VCC_0V: 1315 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1316 break; 1317 default: 1318 return 0; /* power NEVER changed */ 1319 } 1320 1321 switch (command & CARDBUS_VPPMASK) { 1322 case CARDBUS_VPP_UC: 1323 break; 1324 case CARDBUS_VPP_0V: 1325 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1326 break; 1327 case CARDBUS_VPP_VCC: 1328 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1329 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1330 break; 1331 case CARDBUS_VPP_12V: 1332 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1333 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1334 break; 1335 } 1336 1337 pwrcycle = sc->sc_pwrcycle; 1338 aprint_debug_dev(sc->sc_dev, "osock_ctrl %#" PRIx32 1339 " sock_ctrl %#" PRIx32 "\n", osock_ctrl, sock_ctrl); 1340 1341 microtime(&before); 1342 s = splbio(); 1343 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1344 1345 /* 1346 * Wait as long as 200ms for a power-cycle interrupt. If 1347 * interrupts are enabled, but the socket has already 1348 * changed to the desired status, keep waiting for the 1349 * interrupt. "Consuming" the interrupt in this way keeps 1350 * the interrupt from prematurely waking some subsequent 1351 * pccbb_power call. 1352 * 1353 * XXX Not every bridge interrupts on the ->OFF transition. 1354 * XXX That's ok, we will time-out after 200ms. 1355 * 1356 * XXX The power cycle event will never happen when attaching 1357 * XXX a 16-bit card. That's ok, we will time-out after 1358 * XXX 200ms. 1359 */ 1360 for (times = 5; --times >= 0; ) { 1361 if (cold) 1362 DELAY(40 * 1000); 1363 else { 1364 (void)tsleep(&sc->sc_pwrcycle, PWAIT, "pccpwr", 1365 hz / 25); 1366 if (pwrcycle == sc->sc_pwrcycle) 1367 continue; 1368 } 1369 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1370 if ((status & CB_SOCKET_STAT_PWRCYCLE) != 0 && on) 1371 break; 1372 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0 && !on) 1373 break; 1374 } 1375 splx(s); 1376 microtime(&after); 1377 timersub(&after, &before, &diff); 1378 aprint_debug_dev(sc->sc_dev, "wait took%s %lld.%06lds\n", 1379 (on && times < 0) ? " too long" : "", (long long)diff.tv_sec, 1380 (long)diff.tv_usec); 1381 1382 /* 1383 * Ok, wait a bit longer for things to settle. 1384 */ 1385 if (on && sc->sc_chipset == CB_TOPIC95B) 1386 delay_ms(100, sc); 1387 1388 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1389 1390 if (on && sc->sc_chipset != CB_TOPIC95B) { 1391 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0) 1392 aprint_error_dev(sc->sc_dev, "power on failed?\n"); 1393 } 1394 1395 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1396 aprint_error_dev(sc->sc_dev, 1397 "bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1398 sock_ctrl, status); 1399 aprint_error_dev(sc->sc_dev, "disabling socket\n"); 1400 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1401 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1402 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1403 status &= ~CB_SOCKET_STAT_BADVCC; 1404 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, status); 1405 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1406 CB_SOCKET_STAT)); 1407 return 0; 1408 } 1409 1410 if (sc->sc_chipset == CB_TOPIC97) { 1411 reg_ctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL); 1412 reg_ctrl &= ~TOPIC97_REG_CTRL_TESTMODE; 1413 if ((command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V) 1414 reg_ctrl &= ~TOPIC97_REG_CTRL_CLKRUN_ENA; 1415 else 1416 reg_ctrl |= TOPIC97_REG_CTRL_CLKRUN_ENA; 1417 pci_conf_write(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL, reg_ctrl); 1418 } 1419 1420 return 1; /* power changed correctly */ 1421 } 1422 1423 /* 1424 * static int pccbb_detect_card(struct pccbb_softc *sc) 1425 * return value: 0 if no card exists. 1426 * 1 if 16-bit card exists. 1427 * 2 if cardbus card exists. 1428 */ 1429 static int 1430 pccbb_detect_card(struct pccbb_softc *sc) 1431 { 1432 bus_space_handle_t base_memh = sc->sc_base_memh; 1433 bus_space_tag_t base_memt = sc->sc_base_memt; 1434 u_int32_t sockstat = 1435 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1436 int retval = 0; 1437 1438 /* CD1 and CD2 asserted */ 1439 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1440 /* card must be present */ 1441 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1442 /* NOTACARD DEASSERTED */ 1443 if (CB_SOCKET_STAT_CB & sockstat) { 1444 /* CardBus mode */ 1445 retval = 2; 1446 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1447 /* 16-bit mode */ 1448 retval = 1; 1449 } 1450 } 1451 } 1452 return retval; 1453 } 1454 1455 /* 1456 * STATIC int cb_reset(struct pccbb_softc *sc) 1457 * This function resets CardBus card. 1458 */ 1459 STATIC int 1460 cb_reset(struct pccbb_softc *sc) 1461 { 1462 /* 1463 * Reset Assert at least 20 ms 1464 * Some machines request longer duration. 1465 */ 1466 int reset_duration = 1467 (sc->sc_chipset == CB_RX5C47X ? 400 : 50); 1468 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1469 aprint_debug("%s: enter bcr %" PRIx32 "\n", __func__, bcr); 1470 1471 /* Reset bit Assert (bit 6 at 0x3E) */ 1472 bcr |= PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT; 1473 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr); 1474 aprint_debug("%s: wrote bcr %" PRIx32 "\n", __func__, bcr); 1475 delay_ms(reset_duration, sc); 1476 1477 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1478 /* Reset bit Deassert (bit 6 at 0x3E) */ 1479 bcr &= ~(PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT); 1480 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, 1481 bcr); 1482 aprint_debug("%s: wrote bcr %" PRIx32 "\n", __func__, bcr); 1483 delay_ms(reset_duration, sc); 1484 aprint_debug("%s: end of delay\n", __func__); 1485 } 1486 /* No card found on the slot. Keep Reset. */ 1487 return 1; 1488 } 1489 1490 /* 1491 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1492 * This function detect card Voltage. 1493 */ 1494 STATIC int 1495 cb_detect_voltage(struct pccbb_softc *sc) 1496 { 1497 u_int32_t psr; /* socket present-state reg */ 1498 bus_space_tag_t iot = sc->sc_base_memt; 1499 bus_space_handle_t ioh = sc->sc_base_memh; 1500 int vol = PCCARD_VCC_UKN; /* set 0 */ 1501 1502 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1503 1504 if (0x400u & psr) { 1505 vol |= PCCARD_VCC_5V; 1506 } 1507 if (0x800u & psr) { 1508 vol |= PCCARD_VCC_3V; 1509 } 1510 1511 return vol; 1512 } 1513 1514 STATIC int 1515 cbbprint(void *aux, const char *pcic) 1516 { 1517 #if 0 1518 struct cbslot_attach_args *cba = aux; 1519 1520 if (cba->cba_slot >= 0) { 1521 aprint_normal(" slot %d", cba->cba_slot); 1522 } 1523 #endif 1524 return UNCONF; 1525 } 1526 1527 /* 1528 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1529 * This function enables and disables the card 1530 */ 1531 STATIC int 1532 pccbb_cardenable(struct pccbb_softc *sc, int function) 1533 { 1534 u_int32_t command = 1535 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1536 1537 DPRINTF(("pccbb_cardenable:")); 1538 switch (function) { 1539 case CARDBUS_IO_ENABLE: 1540 command |= PCI_COMMAND_IO_ENABLE; 1541 break; 1542 case CARDBUS_IO_DISABLE: 1543 command &= ~PCI_COMMAND_IO_ENABLE; 1544 break; 1545 case CARDBUS_MEM_ENABLE: 1546 command |= PCI_COMMAND_MEM_ENABLE; 1547 break; 1548 case CARDBUS_MEM_DISABLE: 1549 command &= ~PCI_COMMAND_MEM_ENABLE; 1550 break; 1551 case CARDBUS_BM_ENABLE: 1552 command |= PCI_COMMAND_MASTER_ENABLE; 1553 break; 1554 case CARDBUS_BM_DISABLE: 1555 command &= ~PCI_COMMAND_MASTER_ENABLE; 1556 break; 1557 default: 1558 return 0; 1559 } 1560 1561 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1562 DPRINTF((" command reg 0x%x\n", command)); 1563 return 1; 1564 } 1565 1566 #if !rbus 1567 static int 1568 pccbb_io_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 1569 { 1570 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1571 int basereg; 1572 int limitreg; 1573 1574 if ((win < 0) || (win > 2)) { 1575 #if defined DIAGNOSTIC 1576 printf("cardbus_io_open: window out of range %d\n", win); 1577 #endif 1578 return 0; 1579 } 1580 1581 basereg = win * 8 + PCI_CB_IOBASE0; 1582 limitreg = win * 8 + PCI_CB_IOLIMIT0; 1583 1584 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1585 start, basereg, end, limitreg)); 1586 1587 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1588 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1589 return 1; 1590 } 1591 1592 /* 1593 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1594 */ 1595 static int 1596 pccbb_io_close(cardbus_chipset_tag_t ct, int win) 1597 { 1598 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1599 int basereg; 1600 int limitreg; 1601 1602 if ((win < 0) || (win > 2)) { 1603 #if defined DIAGNOSTIC 1604 printf("cardbus_io_close: window out of range %d\n", win); 1605 #endif 1606 return 0; 1607 } 1608 1609 basereg = win * 8 + PCI_CB_IOBASE0; 1610 limitreg = win * 8 + PCI_CB_IOLIMIT0; 1611 1612 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1613 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1614 return 1; 1615 } 1616 1617 static int 1618 pccbb_mem_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 1619 { 1620 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1621 int basereg; 1622 int limitreg; 1623 1624 if ((win < 0) || (win > 2)) { 1625 #if defined DIAGNOSTIC 1626 printf("cardbus_mem_open: window out of range %d\n", win); 1627 #endif 1628 return 0; 1629 } 1630 1631 basereg = win * 8 + PCI_CB_MEMBASE0; 1632 limitreg = win * 8 + PCI_CB_MEMLIMIT0; 1633 1634 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1635 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1636 return 1; 1637 } 1638 1639 static int 1640 pccbb_mem_close(cardbus_chipset_tag_t ct, int win) 1641 { 1642 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1643 int basereg; 1644 int limitreg; 1645 1646 if ((win < 0) || (win > 2)) { 1647 #if defined DIAGNOSTIC 1648 printf("cardbus_mem_close: window out of range %d\n", win); 1649 #endif 1650 return 0; 1651 } 1652 1653 basereg = win * 8 + PCI_CB_MEMBASE0; 1654 limitreg = win * 8 + PCI_CB_MEMLIMIT0; 1655 1656 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1657 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1658 return 1; 1659 } 1660 #endif 1661 1662 /* 1663 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1664 * int irq, 1665 * int level, 1666 * int (* func)(void *), 1667 * void *arg) 1668 * 1669 * This function registers an interrupt handler at the bridge, in 1670 * order not to call the interrupt handlers of child devices when 1671 * a card-deletion interrupt occurs. 1672 * 1673 * The arguments irq and level are not used. 1674 */ 1675 static void * 1676 pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, cardbus_intr_line_t irq, 1677 int level, int (*func)(void *), void *arg) 1678 { 1679 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1680 1681 return pccbb_intr_establish(sc, irq, level, func, arg); 1682 } 1683 1684 1685 /* 1686 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1687 * void *ih) 1688 * 1689 * This function removes an interrupt handler pointed by ih. 1690 */ 1691 static void 1692 pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih) 1693 { 1694 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1695 1696 pccbb_intr_disestablish(sc, ih); 1697 } 1698 1699 1700 void 1701 pccbb_intr_route(struct pccbb_softc *sc) 1702 { 1703 pcireg_t bcr, cbctrl; 1704 1705 /* initialize bridge intr routing */ 1706 bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1707 bcr &= ~CB_BCR_INTR_IREQ_ENABLE; 1708 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr); 1709 1710 switch (sc->sc_chipset) { 1711 case CB_TI113X: 1712 cbctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1713 /* functional intr enabled */ 1714 cbctrl |= PCI113X_CBCTRL_PCI_INTR; 1715 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, cbctrl); 1716 break; 1717 default: 1718 break; 1719 } 1720 } 1721 1722 /* 1723 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1724 * int irq, 1725 * int level, 1726 * int (* func)(void *), 1727 * void *arg) 1728 * 1729 * This function registers an interrupt handler at the bridge, in 1730 * order not to call the interrupt handlers of child devices when 1731 * a card-deletion interrupt occurs. 1732 * 1733 * The arguments irq is not used because pccbb selects intr vector. 1734 */ 1735 static void * 1736 pccbb_intr_establish(struct pccbb_softc *sc, cardbus_intr_line_t irq, 1737 int level, int (*func)(void *), void *arg) 1738 { 1739 struct pccbb_intrhand_list *pil, *newpil; 1740 1741 DPRINTF(("pccbb_intr_establish start. %p\n", LIST_FIRST(&sc->sc_pil))); 1742 1743 if (LIST_EMPTY(&sc->sc_pil)) { 1744 pccbb_intr_route(sc); 1745 } 1746 1747 /* 1748 * Allocate a room for interrupt handler structure. 1749 */ 1750 if (NULL == (newpil = 1751 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1752 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1753 return NULL; 1754 } 1755 1756 newpil->pil_func = func; 1757 newpil->pil_arg = arg; 1758 newpil->pil_icookie = makeiplcookie(level); 1759 1760 if (LIST_EMPTY(&sc->sc_pil)) { 1761 LIST_INSERT_HEAD(&sc->sc_pil, newpil, pil_next); 1762 } else { 1763 for (pil = LIST_FIRST(&sc->sc_pil); 1764 LIST_NEXT(pil, pil_next) != NULL; 1765 pil = LIST_NEXT(pil, pil_next)); 1766 LIST_INSERT_AFTER(pil, newpil, pil_next); 1767 } 1768 1769 DPRINTF(("pccbb_intr_establish add pil. %p\n", 1770 LIST_FIRST(&sc->sc_pil))); 1771 1772 return newpil; 1773 } 1774 1775 /* 1776 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1777 * void *ih) 1778 * 1779 * This function removes an interrupt handler pointed by ih. ih 1780 * should be the value returned by cardbus_intr_establish() or 1781 * NULL. 1782 * 1783 * When ih is NULL, this function will do nothing. 1784 */ 1785 static void 1786 pccbb_intr_disestablish(struct pccbb_softc *sc, void *ih) 1787 { 1788 struct pccbb_intrhand_list *pil; 1789 pcireg_t reg; 1790 1791 DPRINTF(("pccbb_intr_disestablish start. %p\n", 1792 LIST_FIRST(&sc->sc_pil))); 1793 1794 if (ih == NULL) { 1795 /* intr handler is not set */ 1796 DPRINTF(("pccbb_intr_disestablish: no ih\n")); 1797 return; 1798 } 1799 1800 #ifdef DIAGNOSTIC 1801 LIST_FOREACH(pil, &sc->sc_pil, pil_next) { 1802 DPRINTF(("pccbb_intr_disestablish: pil %p\n", pil)); 1803 if (pil == ih) { 1804 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1805 break; 1806 } 1807 } 1808 if (pil == NULL) { 1809 panic("pccbb_intr_disestablish: %s cannot find pil %p", 1810 device_xname(sc->sc_dev), ih); 1811 } 1812 #endif 1813 1814 pil = (struct pccbb_intrhand_list *)ih; 1815 LIST_REMOVE(pil, pil_next); 1816 free(pil, M_DEVBUF); 1817 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1818 1819 if (LIST_EMPTY(&sc->sc_pil)) { 1820 /* No interrupt handlers */ 1821 1822 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1823 1824 /* stop routing PCI intr */ 1825 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1826 reg |= CB_BCR_INTR_IREQ_ENABLE; 1827 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, reg); 1828 1829 switch (sc->sc_chipset) { 1830 case CB_TI113X: 1831 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1832 /* functional intr disabled */ 1833 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1834 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1835 break; 1836 default: 1837 break; 1838 } 1839 } 1840 } 1841 1842 #if defined SHOW_REGS 1843 static void 1844 cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, bus_space_tag_t memt, 1845 bus_space_handle_t memh) 1846 { 1847 int i; 1848 printf("PCI config regs:"); 1849 for (i = 0; i < 0x50; i += 4) { 1850 if (i % 16 == 0) 1851 printf("\n 0x%02x:", i); 1852 printf(" %08x", pci_conf_read(pc, tag, i)); 1853 } 1854 for (i = 0x80; i < 0xb0; i += 4) { 1855 if (i % 16 == 0) 1856 printf("\n 0x%02x:", i); 1857 printf(" %08x", pci_conf_read(pc, tag, i)); 1858 } 1859 1860 if (memh == 0) { 1861 printf("\n"); 1862 return; 1863 } 1864 1865 printf("\nsocket regs:"); 1866 for (i = 0; i <= 0x10; i += 0x04) 1867 printf(" %08x", bus_space_read_4(memt, memh, i)); 1868 printf("\nExCA regs:"); 1869 for (i = 0; i < 0x08; ++i) 1870 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1871 printf("\n"); 1872 return; 1873 } 1874 #endif 1875 1876 /* 1877 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1878 * int busno, int function) 1879 * This is the function to make a tag to access config space of 1880 * a CardBus Card. It works same as pci_conf_read. 1881 */ 1882 static cardbustag_t 1883 pccbb_make_tag(cardbus_chipset_tag_t cc, int busno, int function) 1884 { 1885 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1886 1887 return pci_make_tag(sc->sc_pc, busno, 0, function); 1888 } 1889 1890 static void 1891 pccbb_free_tag(cardbus_chipset_tag_t cc, cardbustag_t tag) 1892 { 1893 } 1894 1895 /* 1896 * pccbb_conf_read 1897 * 1898 * This is the function to read the config space of a CardBus card. 1899 * It works the same as pci_conf_read(9). 1900 */ 1901 static cardbusreg_t 1902 pccbb_conf_read(cardbus_chipset_tag_t cc, cardbustag_t tag, int offset) 1903 { 1904 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1905 pcitag_t brtag = sc->sc_tag; 1906 cardbusreg_t reg; 1907 1908 /* 1909 * clear cardbus master abort status; it is OK to write without 1910 * reading before because all bits are r/o or w1tc 1911 */ 1912 pci_conf_write(sc->sc_pc, brtag, PCI_CBB_SECSTATUS, 1913 CBB_SECSTATUS_CBMABORT); 1914 reg = pci_conf_read(sc->sc_pc, tag, offset); 1915 /* check cardbus master abort status */ 1916 if (pci_conf_read(sc->sc_pc, brtag, PCI_CBB_SECSTATUS) 1917 & CBB_SECSTATUS_CBMABORT) 1918 return (0xffffffff); 1919 return reg; 1920 } 1921 1922 /* 1923 * pccbb_conf_write 1924 * 1925 * This is the function to write the config space of a CardBus 1926 * card. It works the same as pci_conf_write(9). 1927 */ 1928 static void 1929 pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, int reg, 1930 cardbusreg_t val) 1931 { 1932 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1933 1934 pci_conf_write(sc->sc_pc, tag, reg, val); 1935 } 1936 1937 #if 0 1938 STATIC int 1939 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1940 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 1941 int speed, int flags, 1942 bus_space_handle_t * iohp) 1943 #endif 1944 /* 1945 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1946 * bus_addr_t start, bus_size_t size, 1947 * bus_size_t align, 1948 * struct pcmcia_io_handle *pcihp 1949 * 1950 * This function only allocates I/O region for pccard. This function 1951 * never maps the allocated region to pccard I/O area. 1952 * 1953 * XXX: The interface of this function is not very good, I believe. 1954 */ 1955 STATIC int 1956 pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, 1957 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 1958 { 1959 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 1960 bus_addr_t ioaddr; 1961 int flags = 0; 1962 bus_space_tag_t iot; 1963 bus_space_handle_t ioh; 1964 bus_addr_t mask; 1965 #if rbus 1966 rbus_tag_t rb; 1967 #endif 1968 if (align == 0) { 1969 align = size; /* XXX: funny??? */ 1970 } 1971 1972 if (start != 0) { 1973 /* XXX: assume all card decode lower 10 bits by its hardware */ 1974 mask = 0x3ff; 1975 /* enforce to use only masked address */ 1976 start &= mask; 1977 } else { 1978 /* 1979 * calculate mask: 1980 * 1. get the most significant bit of size (call it msb). 1981 * 2. compare msb with the value of size. 1982 * 3. if size is larger, shift msb left once. 1983 * 4. obtain mask value to decrement msb. 1984 */ 1985 bus_size_t size_tmp = size; 1986 int shifts = 0; 1987 1988 mask = 1; 1989 while (size_tmp) { 1990 ++shifts; 1991 size_tmp >>= 1; 1992 } 1993 mask = (1 << shifts); 1994 if (mask < size) { 1995 mask <<= 1; 1996 } 1997 --mask; 1998 } 1999 2000 /* 2001 * Allocate some arbitrary I/O space. 2002 */ 2003 2004 iot = sc->sc_iot; 2005 2006 #if rbus 2007 rb = sc->sc_rbus_iot; 2008 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 2009 return 1; 2010 } 2011 DPRINTF(("pccbb_pcmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2012 (u_long) ioaddr, (u_long) size)); 2013 #else 2014 if (start) { 2015 ioaddr = start; 2016 if (bus_space_map(iot, start, size, 0, &ioh)) { 2017 return 1; 2018 } 2019 DPRINTF(("pccbb_pcmcia_io_alloc map port 0x%lx+0x%lx\n", 2020 (u_long) ioaddr, (u_long) size)); 2021 } else { 2022 flags |= PCMCIA_IO_ALLOCATED; 2023 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 2024 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 2025 size, align, 0, 0, &ioaddr, &ioh)) { 2026 /* No room be able to be get. */ 2027 return 1; 2028 } 2029 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2030 (u_long) ioaddr, (u_long) size)); 2031 } 2032 #endif 2033 2034 pcihp->iot = iot; 2035 pcihp->ioh = ioh; 2036 pcihp->addr = ioaddr; 2037 pcihp->size = size; 2038 pcihp->flags = flags; 2039 2040 return 0; 2041 } 2042 2043 /* 2044 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2045 * struct pcmcia_io_handle *pcihp) 2046 * 2047 * This function only frees I/O region for pccard. 2048 * 2049 * XXX: The interface of this function is not very good, I believe. 2050 */ 2051 void 2052 pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2053 struct pcmcia_io_handle *pcihp) 2054 { 2055 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2056 #if !rbus 2057 bus_space_tag_t iot = pcihp->iot; 2058 #endif 2059 bus_space_handle_t ioh = pcihp->ioh; 2060 bus_size_t size = pcihp->size; 2061 2062 #if rbus 2063 rbus_tag_t rb = sc->sc_rbus_iot; 2064 2065 rbus_space_free(rb, ioh, size, NULL); 2066 #else 2067 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 2068 bus_space_free(iot, ioh, size); 2069 else 2070 bus_space_unmap(iot, ioh, size); 2071 #endif 2072 } 2073 2074 /* 2075 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 2076 * bus_addr_t offset, bus_size_t size, 2077 * struct pcmcia_io_handle *pcihp, 2078 * int *windowp) 2079 * 2080 * This function maps the allocated I/O region to pccard. This function 2081 * never allocates any I/O region for pccard I/O area. I don't 2082 * understand why the original authors of pcmciabus separated alloc and 2083 * map. I believe the two must be unite. 2084 * 2085 * XXX: no wait timing control? 2086 */ 2087 int 2088 pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, bus_addr_t offset, 2089 bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp) 2090 { 2091 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2092 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2093 bus_addr_t ioaddr = pcihp->addr + offset; 2094 int i, win; 2095 #if defined CBB_DEBUG 2096 static const char *width_names[] = { "dynamic", "io8", "io16" }; 2097 #endif 2098 2099 /* Sanity check I/O handle. */ 2100 2101 if (sc->sc_iot != pcihp->iot) { 2102 panic("pccbb_pcmcia_io_map iot is bogus"); 2103 } 2104 2105 /* XXX Sanity check offset/size. */ 2106 2107 win = -1; 2108 for (i = 0; i < PCIC_IO_WINS; i++) { 2109 if ((ph->ioalloc & (1 << i)) == 0) { 2110 win = i; 2111 ph->ioalloc |= (1 << i); 2112 break; 2113 } 2114 } 2115 2116 if (win == -1) { 2117 return 1; 2118 } 2119 2120 *windowp = win; 2121 2122 /* XXX this is pretty gross */ 2123 2124 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2125 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2126 2127 /* XXX wtf is this doing here? */ 2128 2129 #if 0 2130 printf(" port 0x%lx", (u_long) ioaddr); 2131 if (size > 1) { 2132 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2133 } 2134 #endif 2135 2136 ph->io[win].addr = ioaddr; 2137 ph->io[win].size = size; 2138 ph->io[win].width = width; 2139 2140 /* actual dirty register-value changing in the function below. */ 2141 pccbb_pcmcia_do_io_map(sc, win); 2142 2143 return 0; 2144 } 2145 2146 /* 2147 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2148 * 2149 * This function changes register-value to map I/O region for pccard. 2150 */ 2151 static void 2152 pccbb_pcmcia_do_io_map(struct pccbb_softc *sc, int win) 2153 { 2154 static u_int8_t pcic_iowidth[3] = { 2155 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2156 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2157 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2158 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2159 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2160 }; 2161 2162 #define PCIC_SIA_START_LOW 0 2163 #define PCIC_SIA_START_HIGH 1 2164 #define PCIC_SIA_STOP_LOW 2 2165 #define PCIC_SIA_STOP_HIGH 3 2166 2167 int regbase_win = 0x8 + win * 0x04; 2168 u_int8_t ioctl, enable; 2169 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2170 2171 DPRINTF(("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx " 2172 "width %d\n", win, (unsigned long)ph->io[win].addr, 2173 (unsigned long)ph->io[win].size, ph->io[win].width * 8)); 2174 2175 Pcic_write(sc, regbase_win + PCIC_SIA_START_LOW, 2176 ph->io[win].addr & 0xff); 2177 Pcic_write(sc, regbase_win + PCIC_SIA_START_HIGH, 2178 (ph->io[win].addr >> 8) & 0xff); 2179 2180 Pcic_write(sc, regbase_win + PCIC_SIA_STOP_LOW, 2181 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2182 Pcic_write(sc, regbase_win + PCIC_SIA_STOP_HIGH, 2183 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2184 2185 ioctl = Pcic_read(sc, PCIC_IOCTL); 2186 enable = Pcic_read(sc, PCIC_ADDRWIN_ENABLE); 2187 switch (win) { 2188 case 0: 2189 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2190 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2191 PCIC_IOCTL_IO0_DATASIZE_MASK); 2192 ioctl |= pcic_iowidth[ph->io[win].width]; 2193 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2194 break; 2195 case 1: 2196 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2197 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2198 PCIC_IOCTL_IO1_DATASIZE_MASK); 2199 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2200 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2201 break; 2202 } 2203 Pcic_write(sc, PCIC_IOCTL, ioctl); 2204 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, enable); 2205 #if defined(CBB_DEBUG) 2206 { 2207 u_int8_t start_low = 2208 Pcic_read(sc, regbase_win + PCIC_SIA_START_LOW); 2209 u_int8_t start_high = 2210 Pcic_read(sc, regbase_win + PCIC_SIA_START_HIGH); 2211 u_int8_t stop_low = 2212 Pcic_read(sc, regbase_win + PCIC_SIA_STOP_LOW); 2213 u_int8_t stop_high = 2214 Pcic_read(sc, regbase_win + PCIC_SIA_STOP_HIGH); 2215 printf("pccbb_pcmcia_do_io_map start %02x %02x, " 2216 "stop %02x %02x, ioctl %02x enable %02x\n", 2217 start_low, start_high, stop_low, stop_high, ioctl, enable); 2218 } 2219 #endif 2220 } 2221 2222 /* 2223 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2224 * 2225 * This function unmaps I/O region. No return value. 2226 */ 2227 STATIC void 2228 pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t pch, int win) 2229 { 2230 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2231 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2232 int reg; 2233 2234 if (win >= PCIC_IO_WINS || win < 0) { 2235 panic("pccbb_pcmcia_io_unmap: window out of range"); 2236 } 2237 2238 reg = Pcic_read(sc, PCIC_ADDRWIN_ENABLE); 2239 switch (win) { 2240 case 0: 2241 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2242 break; 2243 case 1: 2244 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2245 break; 2246 } 2247 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, reg); 2248 2249 ph->ioalloc &= ~(1 << win); 2250 } 2251 2252 static int 2253 pccbb_pcmcia_wait_ready(struct pccbb_softc *sc) 2254 { 2255 u_int8_t stat; 2256 int i; 2257 2258 /* wait an initial 10ms for quick cards */ 2259 stat = Pcic_read(sc, PCIC_IF_STATUS); 2260 if (stat & PCIC_IF_STATUS_READY) 2261 return (0); 2262 pccbb_pcmcia_delay(sc, 10, "pccwr0"); 2263 for (i = 0; i < 50; i++) { 2264 stat = Pcic_read(sc, PCIC_IF_STATUS); 2265 if (stat & PCIC_IF_STATUS_READY) 2266 return (0); 2267 if ((stat & PCIC_IF_STATUS_CARDDETECT_MASK) != 2268 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2269 return (ENXIO); 2270 /* wait .1s (100ms) each iteration now */ 2271 pccbb_pcmcia_delay(sc, 100, "pccwr1"); 2272 } 2273 2274 printf("pccbb_pcmcia_wait_ready: ready never happened, status=%02x\n", stat); 2275 return (EWOULDBLOCK); 2276 } 2277 2278 /* 2279 * Perform long (msec order) delay. timo is in milliseconds. 2280 */ 2281 static void 2282 pccbb_pcmcia_delay(struct pccbb_softc *sc, int timo, const char *wmesg) 2283 { 2284 #ifdef DIAGNOSTIC 2285 if (timo <= 0) 2286 panic("pccbb_pcmcia_delay: called with timeout %d", timo); 2287 if (!curlwp) 2288 panic("pccbb_pcmcia_delay: called in interrupt context"); 2289 #endif 2290 DPRINTF(("pccbb_pcmcia_delay: \"%s\", sleep %d ms\n", wmesg, timo)); 2291 tsleep(pccbb_pcmcia_delay, PWAIT, wmesg, roundup(timo * hz, 1000) / 1000); 2292 } 2293 2294 /* 2295 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2296 * 2297 * This function enables the card. All information is stored in 2298 * the first argument, pcmcia_chipset_handle_t. 2299 */ 2300 STATIC void 2301 pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2302 { 2303 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2304 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2305 pcireg_t spsr; 2306 int voltage; 2307 int win; 2308 u_int8_t power, intr; 2309 #ifdef DIAGNOSTIC 2310 int reg; 2311 #endif 2312 2313 /* this bit is mostly stolen from pcic_attach_card */ 2314 2315 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2316 2317 /* get card Vcc info */ 2318 spsr = 2319 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2320 CB_SOCKET_STAT); 2321 if (spsr & CB_SOCKET_STAT_5VCARD) { 2322 DPRINTF(("5V card\n")); 2323 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2324 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2325 DPRINTF(("3V card\n")); 2326 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2327 } else { 2328 DPRINTF(("?V card, 0x%x\n", spsr)); /* XXX */ 2329 return; 2330 } 2331 2332 /* disable interrupts; assert RESET */ 2333 intr = Pcic_read(sc, PCIC_INTR); 2334 intr &= PCIC_INTR_ENABLE; 2335 Pcic_write(sc, PCIC_INTR, intr); 2336 2337 /* zero out the address windows */ 2338 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, 0); 2339 2340 /* power down the socket to reset it, clear the card reset pin */ 2341 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2342 2343 /* power off; assert output enable bit */ 2344 power = PCIC_PWRCTL_OE; 2345 Pcic_write(sc, PCIC_PWRCTL, power); 2346 2347 /* power up the socket */ 2348 if (pccbb_power(sc, voltage) == 0) 2349 return; 2350 2351 /* 2352 * Table 4-18 and figure 4-6 of the PC Card specifiction say: 2353 * Vcc Rising Time (Tpr) = 100ms (handled in pccbb_power() above) 2354 * RESET Width (Th (Hi-z RESET)) = 1ms 2355 * RESET Width (Tw (RESET)) = 10us 2356 * 2357 * some machines require some more time to be settled 2358 * for example old toshiba topic bridges! 2359 * (100ms is added here). 2360 */ 2361 pccbb_pcmcia_delay(sc, 200 + 1, "pccen1"); 2362 2363 /* negate RESET */ 2364 intr |= PCIC_INTR_RESET; 2365 Pcic_write(sc, PCIC_INTR, intr); 2366 2367 /* 2368 * RESET Setup Time (Tsu (RESET)) = 20ms 2369 */ 2370 pccbb_pcmcia_delay(sc, 20, "pccen2"); 2371 2372 #ifdef DIAGNOSTIC 2373 reg = Pcic_read(sc, PCIC_IF_STATUS); 2374 if ((reg & PCIC_IF_STATUS_POWERACTIVE) == 0) 2375 printf("pccbb_pcmcia_socket_enable: no power, status=%x\n", reg); 2376 #endif 2377 2378 /* wait for the chip to finish initializing */ 2379 if (pccbb_pcmcia_wait_ready(sc)) { 2380 #ifdef DIAGNOSTIC 2381 printf("pccbb_pcmcia_socket_enable: never became ready\n"); 2382 #endif 2383 /* XXX return a failure status?? */ 2384 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2385 Pcic_write(sc, PCIC_PWRCTL, 0); 2386 return; 2387 } 2388 2389 /* reinstall all the memory and io mappings */ 2390 for (win = 0; win < PCIC_MEM_WINS; ++win) 2391 if (ph->memalloc & (1 << win)) 2392 pccbb_pcmcia_do_mem_map(sc, win); 2393 for (win = 0; win < PCIC_IO_WINS; ++win) 2394 if (ph->ioalloc & (1 << win)) 2395 pccbb_pcmcia_do_io_map(sc, win); 2396 } 2397 2398 /* 2399 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2400 * 2401 * This function disables the card. All information is stored in 2402 * the first argument, pcmcia_chipset_handle_t. 2403 */ 2404 STATIC void 2405 pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t pch) 2406 { 2407 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2408 u_int8_t intr; 2409 2410 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2411 2412 /* disable interrupts; assert RESET */ 2413 intr = Pcic_read(sc, PCIC_INTR); 2414 intr &= PCIC_INTR_ENABLE; 2415 Pcic_write(sc, PCIC_INTR, intr); 2416 2417 /* zero out the address windows */ 2418 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, 0); 2419 2420 /* power down the socket to reset it, clear the card reset pin */ 2421 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2422 2423 /* disable socket: negate output enable bit and power off */ 2424 Pcic_write(sc, PCIC_PWRCTL, 0); 2425 2426 /* 2427 * Vcc Falling Time (Tpf) = 300ms 2428 */ 2429 pccbb_pcmcia_delay(sc, 300, "pccwr1"); 2430 } 2431 2432 STATIC void 2433 pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t pch, int type) 2434 { 2435 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2436 u_int8_t intr; 2437 2438 /* set the card type */ 2439 2440 intr = Pcic_read(sc, PCIC_INTR); 2441 intr &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_CARDTYPE_MASK); 2442 if (type == PCMCIA_IFTYPE_IO) 2443 intr |= PCIC_INTR_CARDTYPE_IO; 2444 else 2445 intr |= PCIC_INTR_CARDTYPE_MEM; 2446 Pcic_write(sc, PCIC_INTR, intr); 2447 2448 DPRINTF(("%s: pccbb_pcmcia_socket_settype type %s %02x\n", 2449 device_xname(sc->sc_dev), 2450 ((type == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2451 } 2452 2453 /* 2454 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2455 * 2456 * This function detects whether a card is in the slot or not. 2457 * If a card is inserted, return 1. Otherwise, return 0. 2458 */ 2459 STATIC int 2460 pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch) 2461 { 2462 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2463 2464 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2465 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2466 } 2467 2468 #if 0 2469 STATIC int 2470 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2471 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2472 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2473 #endif 2474 /* 2475 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2476 * bus_size_t size, 2477 * struct pcmcia_mem_handle *pcmhp) 2478 * 2479 * This function only allocates memory region for pccard. This 2480 * function never maps the allocated region to pccard memory area. 2481 * 2482 * XXX: Why the argument of start address is not in? 2483 */ 2484 STATIC int 2485 pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 2486 struct pcmcia_mem_handle *pcmhp) 2487 { 2488 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2489 bus_space_handle_t memh; 2490 bus_addr_t addr; 2491 bus_size_t sizepg; 2492 #if rbus 2493 rbus_tag_t rb; 2494 #endif 2495 2496 /* Check that the card is still there. */ 2497 if ((Pcic_read(sc, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2498 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2499 return 1; 2500 2501 /* out of sc->memh, allocate as many pages as necessary */ 2502 2503 /* convert size to PCIC pages */ 2504 /* 2505 * This is not enough; when the requested region is on the page 2506 * boundaries, this may calculate wrong result. 2507 */ 2508 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2509 #if 0 2510 if (sizepg > PCIC_MAX_MEM_PAGES) { 2511 return 1; 2512 } 2513 #endif 2514 2515 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2516 return 1; 2517 } 2518 2519 addr = 0; /* XXX gcc -Wuninitialized */ 2520 2521 #if rbus 2522 rb = sc->sc_rbus_memt; 2523 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2524 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2525 &addr, &memh)) { 2526 return 1; 2527 } 2528 #else 2529 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2530 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2531 0, /* boundary */ 2532 0, /* flags */ 2533 &addr, &memh)) { 2534 return 1; 2535 } 2536 #endif 2537 2538 DPRINTF(("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, " 2539 "realsize 0x%lx\n", (unsigned long)addr, (unsigned long)size, 2540 (unsigned long)sizepg * PCIC_MEM_PAGESIZE)); 2541 2542 pcmhp->memt = sc->sc_memt; 2543 pcmhp->memh = memh; 2544 pcmhp->addr = addr; 2545 pcmhp->size = size; 2546 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2547 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2548 pcmhp->mhandle = 0; 2549 /* No offset??? Funny. */ 2550 2551 return 0; 2552 } 2553 2554 /* 2555 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2556 * struct pcmcia_mem_handle *pcmhp) 2557 * 2558 * This function release the memory space allocated by the function 2559 * pccbb_pcmcia_mem_alloc(). 2560 */ 2561 STATIC void 2562 pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2563 struct pcmcia_mem_handle *pcmhp) 2564 { 2565 #if rbus 2566 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2567 2568 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2569 #else 2570 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2571 #endif 2572 } 2573 2574 /* 2575 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2576 * 2577 * This function release the memory space allocated by the function 2578 * pccbb_pcmcia_mem_alloc(). 2579 */ 2580 STATIC void 2581 pccbb_pcmcia_do_mem_map(struct pccbb_softc *sc, int win) 2582 { 2583 int regbase_win; 2584 bus_addr_t phys_addr; 2585 bus_addr_t phys_end; 2586 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2587 2588 #define PCIC_SMM_START_LOW 0 2589 #define PCIC_SMM_START_HIGH 1 2590 #define PCIC_SMM_STOP_LOW 2 2591 #define PCIC_SMM_STOP_HIGH 3 2592 #define PCIC_CMA_LOW 4 2593 #define PCIC_CMA_HIGH 5 2594 2595 u_int8_t start_low, start_high = 0; 2596 u_int8_t stop_low, stop_high; 2597 u_int8_t off_low, off_high; 2598 u_int8_t mem_window; 2599 int reg; 2600 2601 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2602 int mem8 = 2603 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2604 || (kind == PCMCIA_MEM_ATTR); 2605 2606 regbase_win = 0x10 + win * 0x08; 2607 2608 phys_addr = ph->mem[win].addr; 2609 phys_end = phys_addr + ph->mem[win].size; 2610 2611 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2612 (unsigned long)phys_addr, (unsigned long)phys_end, 2613 (unsigned long)ph->mem[win].offset)); 2614 2615 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2616 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2617 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2618 2619 /* bit 19:12 */ 2620 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2621 /* bit 23:20 and bit 7 on */ 2622 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2623 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2624 /* bit 31:24, for 32-bit address */ 2625 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2626 2627 Pcic_write(sc, regbase_win + PCIC_SMM_START_LOW, start_low); 2628 Pcic_write(sc, regbase_win + PCIC_SMM_START_HIGH, start_high); 2629 2630 if (sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2631 Pcic_write(sc, 0x40 + win, mem_window); 2632 } 2633 2634 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2635 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2636 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2637 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2638 2639 Pcic_write(sc, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2640 Pcic_write(sc, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2641 2642 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2643 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2644 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2645 | ((kind == PCMCIA_MEM_ATTR) ? 2646 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2647 2648 Pcic_write(sc, regbase_win + PCIC_CMA_LOW, off_low); 2649 Pcic_write(sc, regbase_win + PCIC_CMA_HIGH, off_high); 2650 2651 reg = Pcic_read(sc, PCIC_ADDRWIN_ENABLE); 2652 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2653 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, reg); 2654 2655 #if defined(CBB_DEBUG) 2656 { 2657 int r1, r2, r3, r4, r5, r6, r7 = 0; 2658 2659 r1 = Pcic_read(sc, regbase_win + PCIC_SMM_START_LOW); 2660 r2 = Pcic_read(sc, regbase_win + PCIC_SMM_START_HIGH); 2661 r3 = Pcic_read(sc, regbase_win + PCIC_SMM_STOP_LOW); 2662 r4 = Pcic_read(sc, regbase_win + PCIC_SMM_STOP_HIGH); 2663 r5 = Pcic_read(sc, regbase_win + PCIC_CMA_LOW); 2664 r6 = Pcic_read(sc, regbase_win + PCIC_CMA_HIGH); 2665 if (sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2666 r7 = Pcic_read(sc, 0x40 + win); 2667 } 2668 2669 printf("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2670 "%02x%02x", win, r1, r2, r3, r4, r5, r6); 2671 if (sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2672 printf(" %02x", r7); 2673 } 2674 printf("\n"); 2675 } 2676 #endif 2677 } 2678 2679 /* 2680 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2681 * bus_addr_t card_addr, bus_size_t size, 2682 * struct pcmcia_mem_handle *pcmhp, 2683 * bus_addr_t *offsetp, int *windowp) 2684 * 2685 * This function maps memory space allocated by the function 2686 * pccbb_pcmcia_mem_alloc(). 2687 */ 2688 STATIC int 2689 pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2690 bus_addr_t card_addr, bus_size_t size, struct pcmcia_mem_handle *pcmhp, 2691 bus_size_t *offsetp, int *windowp) 2692 { 2693 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2694 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2695 bus_addr_t busaddr; 2696 long card_offset; 2697 int win; 2698 2699 /* Check that the card is still there. */ 2700 if ((Pcic_read(sc, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2701 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2702 return 1; 2703 2704 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2705 if ((ph->memalloc & (1 << win)) == 0) { 2706 ph->memalloc |= (1 << win); 2707 break; 2708 } 2709 } 2710 2711 if (win == PCIC_MEM_WINS) { 2712 return 1; 2713 } 2714 2715 *windowp = win; 2716 2717 /* XXX this is pretty gross */ 2718 2719 if (sc->sc_memt != pcmhp->memt) { 2720 panic("pccbb_pcmcia_mem_map memt is bogus"); 2721 } 2722 2723 busaddr = pcmhp->addr; 2724 2725 /* 2726 * compute the address offset to the pcmcia address space for the 2727 * pcic. this is intentionally signed. The masks and shifts below 2728 * will cause TRT to happen in the pcic registers. Deal with making 2729 * sure the address is aligned, and return the alignment offset. 2730 */ 2731 2732 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2733 card_addr -= *offsetp; 2734 2735 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2736 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2737 (u_long) card_addr)); 2738 2739 /* 2740 * include the offset in the size, and decrement size by one, since 2741 * the hw wants start/stop 2742 */ 2743 size += *offsetp - 1; 2744 2745 card_offset = (((long)card_addr) - ((long)busaddr)); 2746 2747 ph->mem[win].addr = busaddr; 2748 ph->mem[win].size = size; 2749 ph->mem[win].offset = card_offset; 2750 ph->mem[win].kind = kind; 2751 2752 pccbb_pcmcia_do_mem_map(sc, win); 2753 2754 return 0; 2755 } 2756 2757 /* 2758 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2759 * int window) 2760 * 2761 * This function unmaps memory space which mapped by the function 2762 * pccbb_pcmcia_mem_map(). 2763 */ 2764 STATIC void 2765 pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, int window) 2766 { 2767 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2768 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2769 int reg; 2770 2771 if (window >= PCIC_MEM_WINS) { 2772 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2773 } 2774 2775 reg = Pcic_read(sc, PCIC_ADDRWIN_ENABLE); 2776 reg &= ~(1 << window); 2777 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, reg); 2778 2779 ph->memalloc &= ~(1 << window); 2780 } 2781 2782 /* 2783 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2784 * struct pcmcia_function *pf, 2785 * int ipl, 2786 * int (*func)(void *), 2787 * void *arg); 2788 * 2789 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2790 */ 2791 STATIC void * 2792 pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2793 struct pcmcia_function *pf, int ipl, int (*func)(void *), void *arg) 2794 { 2795 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2796 2797 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2798 /* what should I do? */ 2799 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2800 DPRINTF(("%s does not provide edge nor pulse " 2801 "interrupt\n", device_xname(sc->sc_dev))); 2802 return NULL; 2803 } 2804 /* 2805 * XXX Noooooo! The interrupt flag must set properly!! 2806 * dumb pcmcia driver!! 2807 */ 2808 } 2809 2810 return pccbb_intr_establish(sc, 0, ipl, func, arg); 2811 } 2812 2813 /* 2814 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2815 * void *ih) 2816 * 2817 * This function disables PC-Card interrupt. 2818 */ 2819 STATIC void 2820 pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 2821 { 2822 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2823 2824 pccbb_intr_disestablish(sc, ih); 2825 } 2826 2827 #if rbus 2828 /* 2829 * static int 2830 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2831 * bus_addr_t addr, bus_size_t size, 2832 * bus_addr_t mask, bus_size_t align, 2833 * int flags, bus_addr_t *addrp; 2834 * bus_space_handle_t *bshp) 2835 * 2836 * This function allocates a portion of memory or io space for 2837 * clients. This function is called from CardBus card drivers. 2838 */ 2839 static int 2840 pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2841 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 2842 int flags, bus_addr_t *addrp, bus_space_handle_t *bshp) 2843 { 2844 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2845 2846 DPRINTF(("pccbb_rbus_cb_space_alloc: addr 0x%lx, size 0x%lx, " 2847 "mask 0x%lx, align 0x%lx\n", (unsigned long)addr, 2848 (unsigned long)size, (unsigned long)mask, (unsigned long)align)); 2849 2850 if (align == 0) { 2851 align = size; 2852 } 2853 2854 if (rb->rb_bt == sc->sc_memt) { 2855 if (align < 16) { 2856 return 1; 2857 } 2858 /* 2859 * XXX: align more than 0x1000 to avoid overwrapping 2860 * memory windows for two or more devices. 0x1000 2861 * means memory window's granularity. 2862 * 2863 * Two or more devices should be able to share same 2864 * memory window region. However, overrapping memory 2865 * window is not good because some devices, such as 2866 * 3Com 3C575[BC], have a broken address decoder and 2867 * intrude other's memory region. 2868 */ 2869 if (align < 0x1000) { 2870 align = 0x1000; 2871 } 2872 } else if (rb->rb_bt == sc->sc_iot) { 2873 if (align < 4) { 2874 return 1; 2875 } 2876 /* XXX: hack for avoiding ISA image */ 2877 if (mask < 0x0100) { 2878 mask = 0x3ff; 2879 addr = 0x300; 2880 } 2881 2882 } else { 2883 DPRINTF(("pccbb_rbus_cb_space_alloc: Bus space tag 0x%lx is " 2884 "NOT used. io: 0x%lx, mem: 0x%lx\n", 2885 (unsigned long)rb->rb_bt, (unsigned long)sc->sc_iot, 2886 (unsigned long)sc->sc_memt)); 2887 return 1; 2888 /* XXX: panic here? */ 2889 } 2890 2891 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 2892 aprint_normal_dev(sc->sc_dev, "<rbus> no bus space\n"); 2893 return 1; 2894 } 2895 2896 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 2897 2898 return 0; 2899 } 2900 2901 /* 2902 * static int 2903 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 2904 * bus_space_handle_t *bshp, bus_size_t size); 2905 * 2906 * This function is called from CardBus card drivers. 2907 */ 2908 static int 2909 pccbb_rbus_cb_space_free(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2910 bus_space_handle_t bsh, bus_size_t size) 2911 { 2912 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2913 bus_space_tag_t bt = rb->rb_bt; 2914 2915 pccbb_close_win(sc, bt, bsh, size); 2916 2917 if (bt == sc->sc_memt) { 2918 } else if (bt == sc->sc_iot) { 2919 } else { 2920 return 1; 2921 /* XXX: panic here? */ 2922 } 2923 2924 return rbus_space_free(rb, bsh, size, NULL); 2925 } 2926 #endif /* rbus */ 2927 2928 #if rbus 2929 2930 static int 2931 pccbb_open_win(struct pccbb_softc *sc, bus_space_tag_t bst, bus_addr_t addr, 2932 bus_size_t size, bus_space_handle_t bsh, int flags) 2933 { 2934 struct pccbb_win_chain_head *head; 2935 bus_addr_t align; 2936 2937 head = &sc->sc_iowindow; 2938 align = 0x04; 2939 if (sc->sc_memt == bst) { 2940 head = &sc->sc_memwindow; 2941 align = 0x1000; 2942 DPRINTF(("using memory window, 0x%lx 0x%lx 0x%lx\n\n", 2943 (unsigned long)sc->sc_iot, (unsigned long)sc->sc_memt, 2944 (unsigned long)bst)); 2945 } 2946 2947 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 2948 aprint_error_dev(sc->sc_dev, 2949 "pccbb_open_win: %s winlist insert failed\n", 2950 (head == &sc->sc_memwindow) ? "mem" : "io"); 2951 } 2952 pccbb_winset(align, sc, bst); 2953 2954 return 0; 2955 } 2956 2957 static int 2958 pccbb_close_win(struct pccbb_softc *sc, bus_space_tag_t bst, 2959 bus_space_handle_t bsh, bus_size_t size) 2960 { 2961 struct pccbb_win_chain_head *head; 2962 bus_addr_t align; 2963 2964 head = &sc->sc_iowindow; 2965 align = 0x04; 2966 if (sc->sc_memt == bst) { 2967 head = &sc->sc_memwindow; 2968 align = 0x1000; 2969 } 2970 2971 if (pccbb_winlist_delete(head, bsh, size)) { 2972 aprint_error_dev(sc->sc_dev, 2973 "pccbb_close_win: %s winlist delete failed\n", 2974 (head == &sc->sc_memwindow) ? "mem" : "io"); 2975 } 2976 pccbb_winset(align, sc, bst); 2977 2978 return 0; 2979 } 2980 2981 static int 2982 pccbb_winlist_insert(struct pccbb_win_chain_head *head, bus_addr_t start, 2983 bus_size_t size, bus_space_handle_t bsh, int flags) 2984 { 2985 struct pccbb_win_chain *chainp, *elem; 2986 2987 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 2988 M_NOWAIT)) == NULL) 2989 return (1); /* fail */ 2990 2991 elem->wc_start = start; 2992 elem->wc_end = start + (size - 1); 2993 elem->wc_handle = bsh; 2994 elem->wc_flags = flags; 2995 2996 TAILQ_FOREACH(chainp, head, wc_list) { 2997 if (chainp->wc_end >= start) 2998 break; 2999 } 3000 if (chainp != NULL) 3001 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 3002 else 3003 TAILQ_INSERT_TAIL(head, elem, wc_list); 3004 return (0); 3005 } 3006 3007 static int 3008 pccbb_winlist_delete(struct pccbb_win_chain_head *head, bus_space_handle_t bsh, 3009 bus_size_t size) 3010 { 3011 struct pccbb_win_chain *chainp; 3012 3013 TAILQ_FOREACH(chainp, head, wc_list) { 3014 if (memcmp(&chainp->wc_handle, &bsh, sizeof(bsh)) == 0) 3015 break; 3016 } 3017 if (chainp == NULL) 3018 return 1; /* fail: no candidate to remove */ 3019 3020 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 3021 printf("pccbb_winlist_delete: window 0x%lx size " 3022 "inconsistent: 0x%lx, 0x%lx\n", 3023 (unsigned long)chainp->wc_start, 3024 (unsigned long)(chainp->wc_end - chainp->wc_start), 3025 (unsigned long)(size - 1)); 3026 return 1; 3027 } 3028 3029 TAILQ_REMOVE(head, chainp, wc_list); 3030 free(chainp, M_DEVBUF); 3031 3032 return 0; 3033 } 3034 3035 static void 3036 pccbb_winset(bus_addr_t align, struct pccbb_softc *sc, bus_space_tag_t bst) 3037 { 3038 pci_chipset_tag_t pc; 3039 pcitag_t tag; 3040 bus_addr_t mask = ~(align - 1); 3041 struct { 3042 cardbusreg_t win_start; 3043 cardbusreg_t win_limit; 3044 int win_flags; 3045 } win[2]; 3046 struct pccbb_win_chain *chainp; 3047 int offs; 3048 3049 win[0].win_start = win[1].win_start = 0xffffffff; 3050 win[0].win_limit = win[1].win_limit = 0; 3051 win[0].win_flags = win[1].win_flags = 0; 3052 3053 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3054 offs = PCI_CB_IOBASE0; 3055 if (sc->sc_memt == bst) { 3056 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3057 offs = PCI_CB_MEMBASE0; 3058 } 3059 3060 if (chainp != NULL) { 3061 win[0].win_start = chainp->wc_start & mask; 3062 win[0].win_limit = chainp->wc_end & mask; 3063 win[0].win_flags = chainp->wc_flags; 3064 chainp = TAILQ_NEXT(chainp, wc_list); 3065 } 3066 3067 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3068 if (win[1].win_start == 0xffffffff) { 3069 /* window 1 is not used */ 3070 if ((win[0].win_flags == chainp->wc_flags) && 3071 (win[0].win_limit + align >= 3072 (chainp->wc_start & mask))) { 3073 /* concatenate */ 3074 win[0].win_limit = chainp->wc_end & mask; 3075 } else { 3076 /* make new window */ 3077 win[1].win_start = chainp->wc_start & mask; 3078 win[1].win_limit = chainp->wc_end & mask; 3079 win[1].win_flags = chainp->wc_flags; 3080 } 3081 continue; 3082 } 3083 3084 /* Both windows are engaged. */ 3085 if (win[0].win_flags == win[1].win_flags) { 3086 /* same flags */ 3087 if (win[0].win_flags == chainp->wc_flags) { 3088 if (win[1].win_start - (win[0].win_limit + 3089 align) < 3090 (chainp->wc_start & mask) - 3091 ((chainp->wc_end & mask) + align)) { 3092 /* 3093 * merge window 0 and 1, and set win1 3094 * to chainp 3095 */ 3096 win[0].win_limit = win[1].win_limit; 3097 win[1].win_start = 3098 chainp->wc_start & mask; 3099 win[1].win_limit = 3100 chainp->wc_end & mask; 3101 } else { 3102 win[1].win_limit = 3103 chainp->wc_end & mask; 3104 } 3105 } else { 3106 /* different flags */ 3107 3108 /* concatenate win0 and win1 */ 3109 win[0].win_limit = win[1].win_limit; 3110 /* allocate win[1] to new space */ 3111 win[1].win_start = chainp->wc_start & mask; 3112 win[1].win_limit = chainp->wc_end & mask; 3113 win[1].win_flags = chainp->wc_flags; 3114 } 3115 } else { 3116 /* the flags of win[0] and win[1] is different */ 3117 if (win[0].win_flags == chainp->wc_flags) { 3118 win[0].win_limit = chainp->wc_end & mask; 3119 /* 3120 * XXX this creates overlapping windows, so 3121 * what should the poor bridge do if one is 3122 * cachable, and the other is not? 3123 */ 3124 aprint_error_dev(sc->sc_dev, 3125 "overlapping windows\n"); 3126 } else { 3127 win[1].win_limit = chainp->wc_end & mask; 3128 } 3129 } 3130 } 3131 3132 pc = sc->sc_pc; 3133 tag = sc->sc_tag; 3134 pci_conf_write(pc, tag, offs, win[0].win_start); 3135 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3136 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3137 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3138 DPRINTF(("--pccbb_winset: win0 [0x%lx, 0x%lx), win1 [0x%lx, 0x%lx)\n", 3139 (unsigned long)pci_conf_read(pc, tag, offs), 3140 (unsigned long)pci_conf_read(pc, tag, offs + 4) + align, 3141 (unsigned long)pci_conf_read(pc, tag, offs + 8), 3142 (unsigned long)pci_conf_read(pc, tag, offs + 12) + align)); 3143 3144 if (bst == sc->sc_memt) { 3145 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BRIDGE_CONTROL_REG); 3146 3147 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 3148 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 3149 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3150 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 3151 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3152 pci_conf_write(pc, tag, PCI_BRIDGE_CONTROL_REG, bcr); 3153 } 3154 } 3155 3156 #endif /* rbus */ 3157 3158 static bool 3159 pccbb_suspend(device_t dv PMF_FN_ARGS) 3160 { 3161 struct pccbb_softc *sc = device_private(dv); 3162 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3163 bus_space_handle_t base_memh = sc->sc_base_memh; 3164 pcireg_t reg; 3165 3166 if (sc->sc_pil_intr_enable) 3167 (void)pccbbintr_function(sc); 3168 sc->sc_pil_intr_enable = 0; 3169 3170 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3171 /* Disable interrupts. */ 3172 reg &= ~(CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER); 3173 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3174 /* XXX joerg Disable power to the socket? */ 3175 3176 /* XXX flush PCI write */ 3177 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3178 3179 /* reset interrupt */ 3180 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, 3181 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT)); 3182 /* XXX flush PCI write */ 3183 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3184 3185 if (sc->sc_ih != NULL) { 3186 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 3187 sc->sc_ih = NULL; 3188 } 3189 3190 return true; 3191 } 3192 3193 static bool 3194 pccbb_resume(device_t dv PMF_FN_ARGS) 3195 { 3196 struct pccbb_softc *sc = device_private(dv); 3197 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3198 bus_space_handle_t base_memh = sc->sc_base_memh; 3199 pcireg_t reg; 3200 3201 pccbb_chipinit(sc); 3202 pccbb_intrinit(sc); 3203 /* setup memory and io space window for CB */ 3204 pccbb_winset(0x1000, sc, sc->sc_memt); 3205 pccbb_winset(0x04, sc, sc->sc_iot); 3206 3207 /* CSC Interrupt: Card detect interrupt on */ 3208 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3209 /* Card detect intr is turned on. */ 3210 reg |= CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; 3211 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3212 /* reset interrupt */ 3213 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3214 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3215 3216 /* 3217 * check for card insertion or removal during suspend period. 3218 * XXX: the code can't cope with card swap (remove then 3219 * insert). how can we detect such situation? 3220 */ 3221 (void)pccbbintr(sc); 3222 3223 sc->sc_pil_intr_enable = 1; 3224 3225 return true; 3226 } 3227
Indexes created Fri Sep 26 08:10:20 GMT 2025