pccbb.c revision 1.188
1 /* $NetBSD: pccbb.c,v 1.188 2009/05/21 17:32:32 dyoung Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: pccbb.c,v 1.188 2009/05/21 17:32:32 dyoung Exp $"); 35 36 /* 37 #define CBB_DEBUG 38 #define SHOW_REGS 39 */ 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/kernel.h> 44 #include <sys/errno.h> 45 #include <sys/ioctl.h> 46 #include <sys/reboot.h> /* for bootverbose */ 47 #include <sys/syslog.h> 48 #include <sys/device.h> 49 #include <sys/malloc.h> 50 #include <sys/proc.h> 51 52 #include <sys/intr.h> 53 #include <sys/bus.h> 54 55 #include <dev/pci/pcivar.h> 56 #include <dev/pci/pcireg.h> 57 #include <dev/pci/pcidevs.h> 58 59 #include <dev/pci/pccbbreg.h> 60 61 #include <dev/cardbus/cardslotvar.h> 62 63 #include <dev/cardbus/cardbusvar.h> 64 65 #include <dev/pcmcia/pcmciareg.h> 66 #include <dev/pcmcia/pcmciavar.h> 67 68 #include <dev/ic/i82365reg.h> 69 #include <dev/pci/pccbbvar.h> 70 71 #ifndef __NetBSD_Version__ 72 struct cfdriver cbb_cd = { 73 NULL, "cbb", DV_DULL 74 }; 75 #endif 76 77 #ifdef CBB_DEBUG 78 #define DPRINTF(x) printf x 79 #define STATIC 80 #else 81 #define DPRINTF(x) 82 #define STATIC static 83 #endif 84 85 int pccbb_burstup = 1; 86 87 /* 88 * delay_ms() is wait in milliseconds. It should be used instead 89 * of delay() if you want to wait more than 1 ms. 90 */ 91 static inline void 92 delay_ms(int millis, void *param) 93 { 94 if (cold) 95 delay(millis * 1000); 96 else 97 tsleep(param, PWAIT, "pccbb", MAX(2, hz * millis / 1000)); 98 } 99 100 int pcicbbmatch(device_t, cfdata_t, void *); 101 void pccbbattach(device_t, device_t, void *); 102 void pccbbchilddet(device_t, device_t); 103 int pccbbdetach(device_t, int); 104 int pccbbintr(void *); 105 static void pci113x_insert(void *); 106 static int pccbbintr_function(struct pccbb_softc *); 107 108 static int pccbb_detect_card(struct pccbb_softc *); 109 110 static void pccbb_pcmcia_write(struct pccbb_softc *, int, u_int8_t); 111 static u_int8_t pccbb_pcmcia_read(struct pccbb_softc *, int); 112 #define Pcic_read(sc, reg) pccbb_pcmcia_read((sc), (reg)) 113 #define Pcic_write(sc, reg, val) pccbb_pcmcia_write((sc), (reg), (val)) 114 115 STATIC int cb_reset(struct pccbb_softc *); 116 STATIC int cb_detect_voltage(struct pccbb_softc *); 117 STATIC int cbbprint(void *, const char *); 118 119 static int cb_chipset(u_int32_t, int *); 120 STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *, 121 struct pcmciabus_attach_args *); 122 123 STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int); 124 STATIC int pccbb_power(struct pccbb_softc *sc, int); 125 STATIC int pccbb_power_ct(cardbus_chipset_tag_t, int); 126 STATIC int pccbb_cardenable(struct pccbb_softc * sc, int function); 127 #if !rbus 128 static int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 129 static int pccbb_io_close(cardbus_chipset_tag_t, int); 130 static int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 131 static int pccbb_mem_close(cardbus_chipset_tag_t, int); 132 #endif /* !rbus */ 133 static void *pccbb_intr_establish(struct pccbb_softc *, 134 cardbus_intr_line_t irq, int level, int (*ih) (void *), void *sc); 135 static void pccbb_intr_disestablish(struct pccbb_softc *, void *ih); 136 137 static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t, 138 cardbus_intr_line_t irq, int level, int (*ih) (void *), void *sc); 139 static void pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih); 140 141 static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t, int, int); 142 static void pccbb_free_tag(cardbus_chipset_tag_t, cardbustag_t); 143 static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t, cardbustag_t, int); 144 static void pccbb_conf_write(cardbus_chipset_tag_t, cardbustag_t, int, 145 cardbusreg_t); 146 static void pccbb_chipinit(struct pccbb_softc *); 147 static void pccbb_intrinit(struct pccbb_softc *); 148 149 STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 150 struct pcmcia_mem_handle *); 151 STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t, 152 struct pcmcia_mem_handle *); 153 STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 154 bus_size_t, struct pcmcia_mem_handle *, bus_size_t *, int *); 155 STATIC void pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t, int); 156 STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 157 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 158 STATIC void pccbb_pcmcia_io_free(pcmcia_chipset_handle_t, 159 struct pcmcia_io_handle *); 160 STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 161 bus_size_t, struct pcmcia_io_handle *, int *); 162 STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t, int); 163 STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t, 164 struct pcmcia_function *, int, int (*)(void *), void *); 165 STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t, void *); 166 STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t); 167 STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t); 168 STATIC void pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t, int); 169 STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch); 170 171 static int pccbb_pcmcia_wait_ready(struct pccbb_softc *); 172 static void pccbb_pcmcia_delay(struct pccbb_softc *, int, const char *); 173 174 static void pccbb_pcmcia_do_io_map(struct pccbb_softc *, int); 175 static void pccbb_pcmcia_do_mem_map(struct pccbb_softc *, int); 176 177 /* bus-space allocation and deallocation functions */ 178 #if rbus 179 180 static int pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t, rbus_tag_t, 181 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 182 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp); 183 static int pccbb_rbus_cb_space_free(cardbus_chipset_tag_t, rbus_tag_t, 184 bus_space_handle_t, bus_size_t); 185 186 #endif /* rbus */ 187 188 #if rbus 189 190 static int pccbb_open_win(struct pccbb_softc *, bus_space_tag_t, 191 bus_addr_t, bus_size_t, bus_space_handle_t, int flags); 192 static int pccbb_close_win(struct pccbb_softc *, bus_space_tag_t, 193 bus_space_handle_t, bus_size_t); 194 static int pccbb_winlist_insert(struct pccbb_win_chain_head *, bus_addr_t, 195 bus_size_t, bus_space_handle_t, int); 196 static int pccbb_winlist_delete(struct pccbb_win_chain_head *, 197 bus_space_handle_t, bus_size_t); 198 static void pccbb_winset(bus_addr_t align, struct pccbb_softc *, 199 bus_space_tag_t); 200 void pccbb_winlist_show(struct pccbb_win_chain *); 201 202 #endif /* rbus */ 203 204 /* for config_defer */ 205 static void pccbb_pci_callback(device_t); 206 207 static bool pccbb_suspend(device_t PMF_FN_PROTO); 208 static bool pccbb_resume(device_t PMF_FN_PROTO); 209 210 #if defined SHOW_REGS 211 static void cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, 212 bus_space_tag_t memt, bus_space_handle_t memh); 213 #endif 214 215 CFATTACH_DECL3_NEW(cbb_pci, sizeof(struct pccbb_softc), 216 pcicbbmatch, pccbbattach, pccbbdetach, NULL, NULL, pccbbchilddet, 217 DVF_DETACH_SHUTDOWN); 218 219 static const struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 220 pccbb_pcmcia_mem_alloc, 221 pccbb_pcmcia_mem_free, 222 pccbb_pcmcia_mem_map, 223 pccbb_pcmcia_mem_unmap, 224 pccbb_pcmcia_io_alloc, 225 pccbb_pcmcia_io_free, 226 pccbb_pcmcia_io_map, 227 pccbb_pcmcia_io_unmap, 228 pccbb_pcmcia_intr_establish, 229 pccbb_pcmcia_intr_disestablish, 230 pccbb_pcmcia_socket_enable, 231 pccbb_pcmcia_socket_disable, 232 pccbb_pcmcia_socket_settype, 233 pccbb_pcmcia_card_detect 234 }; 235 236 #if rbus 237 static const struct cardbus_functions pccbb_funcs = { 238 pccbb_rbus_cb_space_alloc, 239 pccbb_rbus_cb_space_free, 240 pccbb_cb_intr_establish, 241 pccbb_cb_intr_disestablish, 242 pccbb_ctrl, 243 pccbb_power_ct, 244 pccbb_make_tag, 245 pccbb_free_tag, 246 pccbb_conf_read, 247 pccbb_conf_write, 248 }; 249 #else 250 static const struct cardbus_functions pccbb_funcs = { 251 pccbb_ctrl, 252 pccbb_power_ct, 253 pccbb_mem_open, 254 pccbb_mem_close, 255 pccbb_io_open, 256 pccbb_io_close, 257 pccbb_cb_intr_establish, 258 pccbb_cb_intr_disestablish, 259 pccbb_make_tag, 260 pccbb_conf_read, 261 pccbb_conf_write, 262 }; 263 #endif 264 265 int 266 pcicbbmatch(device_t parent, cfdata_t match, void *aux) 267 { 268 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 269 270 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 271 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 272 PCI_INTERFACE(pa->pa_class) == 0) { 273 return 1; 274 } 275 276 return 0; 277 } 278 279 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 280 | ((prod) << PCI_PRODUCT_SHIFT)) 281 282 const struct yenta_chipinfo { 283 pcireg_t yc_id; /* vendor tag | product tag */ 284 int yc_chiptype; 285 int yc_flags; 286 } yc_chipsets[] = { 287 /* Texas Instruments chips */ 288 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 289 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 290 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 291 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 292 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI125X, 293 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 294 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 295 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 296 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 297 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 298 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 299 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 300 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI125X, 301 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 302 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI125X, 303 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 304 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 305 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 306 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 307 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 308 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI1420, 309 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 310 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI125X, 311 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 312 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 313 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 314 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1520), CB_TI12XX, 315 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 316 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4410YENTA), CB_TI12XX, 317 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 318 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4520YENTA), CB_TI12XX, 319 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 320 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI7420YENTA), CB_TI12XX, 321 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 322 323 /* Ricoh chips */ 324 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 325 PCCBB_PCMCIA_MEM_32}, 326 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 327 PCCBB_PCMCIA_MEM_32}, 328 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 329 PCCBB_PCMCIA_MEM_32}, 330 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 331 PCCBB_PCMCIA_MEM_32}, 332 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 333 PCCBB_PCMCIA_MEM_32}, 334 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 335 PCCBB_PCMCIA_MEM_32}, 336 337 /* Toshiba products */ 338 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 339 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 340 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 341 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 342 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 343 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 344 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 345 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 346 347 /* Cirrus Logic products */ 348 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 349 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 350 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 351 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 352 353 /* O2 Micro products */ 354 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6729), 355 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 356 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6730), 357 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 358 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6832), 359 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 360 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6836), 361 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 362 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6872), 363 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 364 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6922), 365 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 366 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6933), 367 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 368 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6972), 369 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 370 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_7223), 371 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 372 373 /* sentinel, or Generic chip */ 374 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 375 }; 376 377 static int 378 cb_chipset(u_int32_t pci_id, int *flagp) 379 { 380 const struct yenta_chipinfo *yc; 381 382 /* Loop over except the last default entry. */ 383 for (yc = yc_chipsets; yc < yc_chipsets + 384 __arraycount(yc_chipsets) - 1; yc++) 385 if (pci_id == yc->yc_id) 386 break; 387 388 if (flagp != NULL) 389 *flagp = yc->yc_flags; 390 391 return (yc->yc_chiptype); 392 } 393 394 void 395 pccbbchilddet(device_t self, device_t child) 396 { 397 struct pccbb_softc *sc = device_private(self); 398 int s; 399 400 KASSERT(sc->sc_csc == device_private(child)); 401 402 s = splbio(); 403 if (sc->sc_csc == device_private(child)) 404 sc->sc_csc = NULL; 405 splx(s); 406 } 407 408 void 409 pccbbattach(device_t parent, device_t self, void *aux) 410 { 411 struct pccbb_softc *sc = device_private(self); 412 struct pci_attach_args *pa = aux; 413 pci_chipset_tag_t pc = pa->pa_pc; 414 pcireg_t busreg, reg, sock_base; 415 bus_addr_t sockbase; 416 char devinfo[256]; 417 int flags; 418 419 #ifdef __HAVE_PCCBB_ATTACH_HOOK 420 pccbb_attach_hook(parent, self, pa); 421 #endif 422 423 sc->sc_dev = self; 424 425 callout_init(&sc->sc_insert_ch, 0); 426 callout_setfunc(&sc->sc_insert_ch, pci113x_insert, sc); 427 428 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 429 430 aprint_naive("\n"); 431 432 pci_devinfo(pa->pa_id, 0, 0, devinfo, sizeof(devinfo)); 433 aprint_normal(": %s (rev. 0x%02x)", devinfo, 434 PCI_REVISION(pa->pa_class)); 435 DPRINTF((" (chipflags %x)", flags)); 436 aprint_normal("\n"); 437 438 TAILQ_INIT(&sc->sc_memwindow); 439 TAILQ_INIT(&sc->sc_iowindow); 440 441 #if rbus 442 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 443 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 444 445 #if 0 446 printf("pa->pa_memt: %08x vs rbus_mem->rb_bt: %08x\n", 447 pa->pa_memt, sc->sc_rbus_memt->rb_bt); 448 #endif 449 #endif /* rbus */ 450 451 sc->sc_flags &= ~CBB_MEMHMAPPED; 452 453 /* 454 * MAP socket registers and ExCA registers on memory-space 455 * When no valid address is set on socket base registers (on pci 456 * config space), get it not polite way. 457 */ 458 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 459 460 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 461 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 462 /* The address must be valid. */ 463 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 464 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, &sc->sc_base_size)) { 465 aprint_error_dev(self, 466 "can't map socket base address 0x%lx\n", 467 (unsigned long)sock_base); 468 /* 469 * I think it's funny: socket base registers must be 470 * mapped on memory space, but ... 471 */ 472 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 473 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 474 &sc->sc_base_size)) { 475 aprint_error_dev(self, 476 "can't map socket base address" 477 " 0x%lx: io mode\n", 478 (unsigned long)sockbase); 479 /* give up... allocate reg space via rbus. */ 480 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 481 } else 482 sc->sc_flags |= CBB_MEMHMAPPED; 483 } else { 484 DPRINTF(("%s: socket base address 0x%lx\n", 485 device_xname(self), 486 (unsigned long)sockbase)); 487 sc->sc_flags |= CBB_MEMHMAPPED; 488 } 489 } 490 491 sc->sc_mem_start = 0; /* XXX */ 492 sc->sc_mem_end = 0xffffffff; /* XXX */ 493 494 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 495 496 /* pccbb_machdep.c end */ 497 498 #if defined CBB_DEBUG 499 { 500 static const char *intrname[] = { "NON", "A", "B", "C", "D" }; 501 aprint_debug_dev(self, "intrpin %s, intrtag %d\n", 502 intrname[pa->pa_intrpin], pa->pa_intrline); 503 } 504 #endif 505 506 /* setup softc */ 507 sc->sc_pc = pc; 508 sc->sc_iot = pa->pa_iot; 509 sc->sc_memt = pa->pa_memt; 510 sc->sc_dmat = pa->pa_dmat; 511 sc->sc_tag = pa->pa_tag; 512 513 memcpy(&sc->sc_pa, pa, sizeof(*pa)); 514 515 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 516 517 /* Disable legacy register mapping. */ 518 switch (sc->sc_chipset) { 519 case CB_RX5C46X: /* fallthrough */ 520 #if 0 521 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 522 case CB_RX5C47X: 523 #endif 524 /* 525 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 526 * cannot be disabled by substituting 0 into PCI_LEGACY 527 * register. Ricoh CardBus bridges have special bits on Bridge 528 * control reg (addr 0x3e on PCI config space). 529 */ 530 reg = pci_conf_read(pc, pa->pa_tag, PCI_BRIDGE_CONTROL_REG); 531 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 532 pci_conf_write(pc, pa->pa_tag, PCI_BRIDGE_CONTROL_REG, reg); 533 break; 534 535 default: 536 /* XXX I don't know proper way to kill legacy I/O. */ 537 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 538 break; 539 } 540 541 if (!pmf_device_register(self, pccbb_suspend, pccbb_resume)) 542 aprint_error_dev(self, "couldn't establish power handler\n"); 543 544 config_defer(self, pccbb_pci_callback); 545 } 546 547 int 548 pccbbdetach(device_t self, int flags) 549 { 550 struct pccbb_softc *sc = device_private(self); 551 pci_chipset_tag_t pc = sc->sc_pa.pa_pc; 552 bus_space_tag_t bmt = sc->sc_base_memt; 553 bus_space_handle_t bmh = sc->sc_base_memh; 554 uint32_t sockmask; 555 int rc; 556 557 if ((rc = config_detach_children(self, flags)) != 0) 558 return rc; 559 560 if (!LIST_EMPTY(&sc->sc_pil)) { 561 panic("%s: interrupt handlers still registered", 562 device_xname(self)); 563 return EBUSY; 564 } 565 566 if (sc->sc_ih != NULL) { 567 pci_intr_disestablish(pc, sc->sc_ih); 568 sc->sc_ih = NULL; 569 } 570 571 /* CSC Interrupt: turn off card detect and power cycle interrupts */ 572 sockmask = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 573 sockmask &= ~(CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | 574 CB_SOCKET_MASK_POWER); 575 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, sockmask); 576 /* reset interrupt */ 577 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 578 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 579 580 switch (sc->sc_flags & (CBB_MEMHMAPPED|CBB_SPECMAPPED)) { 581 case CBB_MEMHMAPPED: 582 bus_space_unmap(bmt, bmh, sc->sc_base_size); 583 break; 584 case CBB_MEMHMAPPED|CBB_SPECMAPPED: 585 #if rbus 586 { 587 pcireg_t sockbase; 588 589 sockbase = pci_conf_read(pc, sc->sc_tag, PCI_SOCKBASE); 590 rbus_space_free(sc->sc_rbus_memt, bmh, 0x1000, 591 NULL); 592 } 593 #else 594 bus_space_free(bmt, bmh, 0x1000); 595 #endif 596 } 597 sc->sc_flags &= ~(CBB_MEMHMAPPED|CBB_SPECMAPPED); 598 599 if (!TAILQ_EMPTY(&sc->sc_iowindow)) 600 aprint_error_dev(self, "i/o windows not empty"); 601 if (!TAILQ_EMPTY(&sc->sc_memwindow)) 602 aprint_error_dev(self, "memory windows not empty"); 603 604 callout_stop(&sc->sc_insert_ch); 605 callout_destroy(&sc->sc_insert_ch); 606 return 0; 607 } 608 609 /* 610 * static void pccbb_pci_callback(device_t self) 611 * 612 * The actual attach routine: get memory space for YENTA register 613 * space, setup YENTA register and route interrupt. 614 * 615 * This function should be deferred because this device may obtain 616 * memory space dynamically. This function must avoid obtaining 617 * memory area which has already kept for another device. 618 */ 619 static void 620 pccbb_pci_callback(device_t self) 621 { 622 struct pccbb_softc *sc = device_private(self); 623 pci_chipset_tag_t pc = sc->sc_pc; 624 bus_addr_t sockbase; 625 struct cbslot_attach_args cba; 626 struct pcmciabus_attach_args paa; 627 struct cardslot_attach_args caa; 628 device_t csc; 629 630 if (!(sc->sc_flags & CBB_MEMHMAPPED)) { 631 /* The socket registers aren't mapped correctly. */ 632 #if rbus 633 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 634 (sc->sc_chipset == CB_RX5C47X 635 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 636 0, &sockbase, &sc->sc_base_memh)) { 637 return; 638 } 639 sc->sc_base_memt = sc->sc_memt; 640 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 641 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 642 device_xname(self), (unsigned long)sockbase, 643 (unsigned long)pci_conf_read(pc, sc->sc_tag, 644 PCI_SOCKBASE))); 645 #else 646 sc->sc_base_memt = sc->sc_memt; 647 #if !defined CBB_PCI_BASE 648 #define CBB_PCI_BASE 0x20000000 649 #endif 650 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 651 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 652 /* cannot allocate memory space */ 653 return; 654 } 655 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 656 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 657 device_xname(self), (unsigned long)sock_base, 658 (unsigned long)pci_conf_read(pc, 659 sc->sc_tag, PCI_SOCKBASE))); 660 #endif 661 sc->sc_flags |= CBB_MEMHMAPPED|CBB_SPECMAPPED; 662 } 663 664 /* clear data structure for child device interrupt handlers */ 665 LIST_INIT(&sc->sc_pil); 666 667 /* bus bridge initialization */ 668 pccbb_chipinit(sc); 669 670 sc->sc_pil_intr_enable = 1; 671 672 { 673 u_int32_t sockstat; 674 675 sockstat = bus_space_read_4(sc->sc_base_memt, 676 sc->sc_base_memh, CB_SOCKET_STAT); 677 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 678 sc->sc_flags |= CBB_CARDEXIST; 679 } 680 } 681 682 /* 683 * attach cardbus 684 */ 685 { 686 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 687 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 688 689 /* initialize cbslot_attach */ 690 cba.cba_iot = sc->sc_iot; 691 cba.cba_memt = sc->sc_memt; 692 cba.cba_dmat = sc->sc_dmat; 693 cba.cba_bus = (busreg >> 8) & 0x0ff; 694 cba.cba_cc = (void *)sc; 695 cba.cba_cf = &pccbb_funcs; 696 cba.cba_intrline = 0; /* XXX dummy */ 697 698 #if rbus 699 cba.cba_rbus_iot = sc->sc_rbus_iot; 700 cba.cba_rbus_memt = sc->sc_rbus_memt; 701 #endif 702 703 cba.cba_cacheline = PCI_CACHELINE(bhlc); 704 cba.cba_max_lattimer = PCI_LATTIMER(bhlc); 705 706 aprint_verbose_dev(self, 707 "cacheline 0x%x lattimer 0x%x\n", 708 cba.cba_cacheline, 709 cba.cba_max_lattimer); 710 aprint_verbose_dev(self, "bhlc 0x%x\n", bhlc); 711 #if defined SHOW_REGS 712 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 713 sc->sc_base_memh); 714 #endif 715 } 716 717 pccbb_pcmcia_attach_setup(sc, &paa); 718 caa.caa_cb_attach = NULL; 719 if (cba.cba_bus == 0) 720 aprint_error_dev(self, 721 "secondary bus number uninitialized; try PCI_BUS_FIXUP\n"); 722 else 723 caa.caa_cb_attach = &cba; 724 caa.caa_16_attach = &paa; 725 726 pccbb_intrinit(sc); 727 728 if (NULL != (csc = config_found_ia(self, "pcmciaslot", &caa, 729 cbbprint))) { 730 DPRINTF(("%s: found cardslot\n", __func__)); 731 sc->sc_csc = device_private(csc); 732 } 733 734 return; 735 } 736 737 738 739 740 741 /* 742 * static void pccbb_chipinit(struct pccbb_softc *sc) 743 * 744 * This function initialize YENTA chip registers listed below: 745 * 1) PCI command reg, 746 * 2) PCI and CardBus latency timer, 747 * 3) route PCI interrupt, 748 * 4) close all memory and io windows. 749 * 5) turn off bus power. 750 * 6) card detect and power cycle interrupts on. 751 * 7) clear interrupt 752 */ 753 static void 754 pccbb_chipinit(struct pccbb_softc *sc) 755 { 756 pci_chipset_tag_t pc = sc->sc_pc; 757 pcitag_t tag = sc->sc_tag; 758 bus_space_tag_t bmt = sc->sc_base_memt; 759 bus_space_handle_t bmh = sc->sc_base_memh; 760 pcireg_t bcr, bhlc, cbctl, csr, lscp, mfunc, mrburst, slotctl, sockctl, 761 sysctrl; 762 763 /* 764 * Set PCI command reg. 765 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 766 */ 767 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 768 /* I believe it is harmless. */ 769 csr |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 770 PCI_COMMAND_MASTER_ENABLE); 771 772 /* All O2 Micro chips have broken parity-error reporting 773 * until proven otherwise. The OZ6933 PCI-CardBus Bridge 774 * is known to have the defect---see PR kern/38698. 775 */ 776 if (sc->sc_chipset != CB_O2MICRO) 777 csr |= PCI_COMMAND_PARITY_ENABLE; 778 779 csr |= PCI_COMMAND_SERR_ENABLE; 780 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 781 782 /* 783 * Set CardBus latency timer. 784 */ 785 lscp = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 786 if (PCI_CB_LATENCY(lscp) < 0x20) { 787 lscp &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 788 lscp |= (0x20 << PCI_CB_LATENCY_SHIFT); 789 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, lscp); 790 } 791 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 792 PCI_CB_LATENCY(lscp), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 793 794 /* 795 * Set PCI latency timer. 796 */ 797 bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG); 798 if (PCI_LATTIMER(bhlc) < 0x10) { 799 bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 800 bhlc |= (0x10 << PCI_LATTIMER_SHIFT); 801 pci_conf_write(pc, tag, PCI_BHLC_REG, bhlc); 802 } 803 DPRINTF(("PCI latency timer 0x%x (%x)\n", 804 PCI_LATTIMER(bhlc), pci_conf_read(pc, tag, PCI_BHLC_REG))); 805 806 807 /* Route functional interrupts to PCI. */ 808 bcr = pci_conf_read(pc, tag, PCI_BRIDGE_CONTROL_REG); 809 bcr |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 810 bcr |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 811 /* assert reset */ 812 bcr |= PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT; 813 /* Set master abort mode to 1, forward SERR# from secondary 814 * to primary, and detect parity errors on secondary. 815 */ 816 bcr |= PCI_BRIDGE_CONTROL_MABRT << PCI_BRIDGE_CONTROL_SHIFT; 817 bcr |= PCI_BRIDGE_CONTROL_SERR << PCI_BRIDGE_CONTROL_SHIFT; 818 bcr |= PCI_BRIDGE_CONTROL_PERE << PCI_BRIDGE_CONTROL_SHIFT; 819 pci_conf_write(pc, tag, PCI_BRIDGE_CONTROL_REG, bcr); 820 821 switch (sc->sc_chipset) { 822 case CB_TI113X: 823 cbctl = pci_conf_read(pc, tag, PCI_CBCTRL); 824 /* This bit is shared, but may read as 0 on some chips, so set 825 it explicitly on both functions. */ 826 cbctl |= PCI113X_CBCTRL_PCI_IRQ_ENA; 827 /* CSC intr enable */ 828 cbctl |= PCI113X_CBCTRL_PCI_CSC; 829 /* functional intr prohibit | prohibit ISA routing */ 830 cbctl &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 831 pci_conf_write(pc, tag, PCI_CBCTRL, cbctl); 832 break; 833 834 case CB_TI1420: 835 sysctrl = pci_conf_read(pc, tag, PCI_SYSCTRL); 836 mrburst = pccbb_burstup 837 ? PCI1420_SYSCTRL_MRBURST : PCI1420_SYSCTRL_MRBURSTDN; 838 if ((sysctrl & PCI1420_SYSCTRL_MRBURST) == mrburst) { 839 printf("%s: %swrite bursts enabled\n", 840 device_xname(sc->sc_dev), 841 pccbb_burstup ? "read/" : ""); 842 } else if (pccbb_burstup) { 843 printf("%s: enabling read/write bursts\n", 844 device_xname(sc->sc_dev)); 845 sysctrl |= PCI1420_SYSCTRL_MRBURST; 846 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 847 } else { 848 printf("%s: disabling read bursts, " 849 "enabling write bursts\n", 850 device_xname(sc->sc_dev)); 851 sysctrl |= PCI1420_SYSCTRL_MRBURSTDN; 852 sysctrl &= ~PCI1420_SYSCTRL_MRBURSTUP; 853 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 854 } 855 /*FALLTHROUGH*/ 856 case CB_TI12XX: 857 /* 858 * Some TI 12xx (and [14][45]xx) based pci cards 859 * sometimes have issues with the MFUNC register not 860 * being initialized due to a bad EEPROM on board. 861 * Laptops that this matters on have this register 862 * properly initialized. 863 * 864 * The TI125X parts have a different register. 865 */ 866 mfunc = pci_conf_read(pc, tag, PCI12XX_MFUNC); 867 if (mfunc == 0) { 868 mfunc &= ~PCI12XX_MFUNC_PIN0; 869 mfunc |= PCI12XX_MFUNC_PIN0_INTA; 870 if ((pci_conf_read(pc, tag, PCI_SYSCTRL) & 871 PCI12XX_SYSCTRL_INTRTIE) == 0) { 872 mfunc &= ~PCI12XX_MFUNC_PIN1; 873 mfunc |= PCI12XX_MFUNC_PIN1_INTB; 874 } 875 pci_conf_write(pc, tag, PCI12XX_MFUNC, mfunc); 876 } 877 /* fallthrough */ 878 879 case CB_TI125X: 880 /* 881 * Disable zoom video. Some machines initialize this 882 * improperly and experience has shown that this helps 883 * prevent strange behavior. 884 */ 885 pci_conf_write(pc, tag, PCI12XX_MMCTRL, 0); 886 887 sysctrl = pci_conf_read(pc, tag, PCI_SYSCTRL); 888 sysctrl |= PCI12XX_SYSCTRL_VCCPROT; 889 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 890 cbctl = pci_conf_read(pc, tag, PCI_CBCTRL); 891 cbctl |= PCI12XX_CBCTRL_CSC; 892 pci_conf_write(pc, tag, PCI_CBCTRL, cbctl); 893 break; 894 895 case CB_TOPIC95B: 896 sockctl = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 897 sockctl |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 898 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, sockctl); 899 slotctl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 900 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 901 device_xname(sc->sc_dev), slotctl)); 902 slotctl |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 903 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 904 slotctl &= ~TOPIC_SLOT_CTRL_SWDETECT; 905 DPRINTF(("0x%x\n", slotctl)); 906 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slotctl); 907 break; 908 909 case CB_TOPIC97: 910 slotctl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 911 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 912 device_xname(sc->sc_dev), slotctl)); 913 slotctl |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 914 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 915 slotctl &= ~TOPIC_SLOT_CTRL_SWDETECT; 916 slotctl |= TOPIC97_SLOT_CTRL_PCIINT; 917 slotctl &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 918 DPRINTF(("0x%x\n", slotctl)); 919 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slotctl); 920 /* make sure to assert LV card support bits */ 921 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 922 0x800 + 0x3e, 923 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 924 0x800 + 0x3e) | 0x03); 925 break; 926 } 927 928 /* Close all memory and I/O windows. */ 929 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 930 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 931 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 932 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 933 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 934 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 935 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 936 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 937 938 /* reset 16-bit pcmcia bus */ 939 bus_space_write_1(bmt, bmh, 0x800 + PCIC_INTR, 940 bus_space_read_1(bmt, bmh, 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 941 942 /* turn off power */ 943 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 944 } 945 946 static void 947 pccbb_intrinit(struct pccbb_softc *sc) 948 { 949 pcireg_t sockmask; 950 const char *intrstr = NULL; 951 pci_intr_handle_t ih; 952 pci_chipset_tag_t pc = sc->sc_pc; 953 bus_space_tag_t bmt = sc->sc_base_memt; 954 bus_space_handle_t bmh = sc->sc_base_memh; 955 956 /* Map and establish the interrupt. */ 957 if (pci_intr_map(&sc->sc_pa, &ih)) { 958 aprint_error_dev(sc->sc_dev, "couldn't map interrupt\n"); 959 return; 960 } 961 intrstr = pci_intr_string(pc, ih); 962 963 /* 964 * XXX pccbbintr should be called under the priority lower 965 * than any other hard interrupts. 966 */ 967 KASSERT(sc->sc_ih == NULL); 968 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 969 970 if (sc->sc_ih == NULL) { 971 aprint_error_dev(sc->sc_dev, "couldn't establish interrupt"); 972 if (intrstr != NULL) 973 aprint_error(" at %s\n", intrstr); 974 else 975 aprint_error("\n"); 976 return; 977 } 978 979 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 980 981 /* CSC Interrupt: Card detect and power cycle interrupts on */ 982 sockmask = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 983 sockmask |= CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | 984 CB_SOCKET_MASK_POWER; 985 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, sockmask); 986 /* reset interrupt */ 987 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 988 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 989 } 990 991 /* 992 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 993 * struct pcmciabus_attach_args *paa) 994 * 995 * This function attaches 16-bit PCcard bus. 996 */ 997 STATIC void 998 pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 999 struct pcmciabus_attach_args *paa) 1000 { 1001 #if rbus 1002 rbus_tag_t rb; 1003 #endif 1004 /* 1005 * We need to do a few things here: 1006 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 1007 * setting the IRQ numbers to 0. 1008 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 1009 * routing of CSC interrupts (e.g. card removal) to PCI while in 1010 * PCMCIA mode. We just leave this set all the time. 1011 * 3) Enable card insertion/removal interrupts in case the chip also 1012 * needs that while in PCMCIA mode. 1013 * 4) Clear any pending CSC interrupt. 1014 */ 1015 Pcic_write(sc, PCIC_INTR, PCIC_INTR_ENABLE); 1016 if (sc->sc_chipset == CB_TI113X) { 1017 Pcic_write(sc, PCIC_CSC_INTR, 0); 1018 } else { 1019 Pcic_write(sc, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 1020 Pcic_read(sc, PCIC_CSC); 1021 } 1022 1023 /* initialize pcmcia bus attachment */ 1024 paa->paa_busname = "pcmcia"; 1025 paa->pct = &pccbb_pcmcia_funcs; 1026 paa->pch = sc; 1027 paa->iobase = 0; /* I don't use them */ 1028 paa->iosize = 0; 1029 #if rbus 1030 rb = sc->sc_rbus_iot; 1031 paa->iobase = rb->rb_start + rb->rb_offset; 1032 paa->iosize = rb->rb_end - rb->rb_start; 1033 #endif 1034 1035 return; 1036 } 1037 1038 /* 1039 * int pccbbintr(arg) 1040 * void *arg; 1041 * This routine handles the interrupt from Yenta PCI-CardBus bridge 1042 * itself. 1043 */ 1044 int 1045 pccbbintr(void *arg) 1046 { 1047 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1048 struct cardslot_softc *csc; 1049 u_int32_t sockevent, sockstate; 1050 bus_space_tag_t memt = sc->sc_base_memt; 1051 bus_space_handle_t memh = sc->sc_base_memh; 1052 1053 if (!device_has_power(sc->sc_dev)) 1054 return 0; 1055 1056 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 1057 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 1058 Pcic_read(sc, PCIC_CSC); 1059 1060 if (sockevent != 0) { 1061 aprint_debug("%s: enter sockevent %" PRIx32 "\n", __func__, 1062 sockevent); 1063 } 1064 1065 /* XXX sockevent == CB_SOCKET_EVENT_CSTS|CB_SOCKET_EVENT_POWER 1066 * does occur in the wild. Check for a _POWER event before 1067 * possibly exiting because of an _CSTS event. 1068 */ 1069 if (sockevent & CB_SOCKET_EVENT_POWER) { 1070 DPRINTF(("Powercycling because of socket event\n")); 1071 /* XXX: Does not happen when attaching a 16-bit card */ 1072 sc->sc_pwrcycle++; 1073 wakeup(&sc->sc_pwrcycle); 1074 } 1075 1076 /* Sometimes a change of CSTSCHG# accompanies the first 1077 * interrupt from an Atheros WLAN. That generates a 1078 * CB_SOCKET_EVENT_CSTS event on the bridge. The event 1079 * isn't interesting to pccbb(4), so we used to ignore the 1080 * interrupt. Now, let the child devices try to handle 1081 * the interrupt, instead. The Atheros NIC produces 1082 * interrupts more reliably, now: used to be that it would 1083 * only interrupt if the driver avoided powering down the 1084 * NIC's cardslot, and then the NIC would only work after 1085 * it was reset a second time. 1086 */ 1087 if (sockevent == 0 || 1088 (sockevent & ~(CB_SOCKET_EVENT_POWER|CB_SOCKET_EVENT_CD)) != 0) { 1089 /* This intr is not for me: it may be for my child devices. */ 1090 if (sc->sc_pil_intr_enable) { 1091 return pccbbintr_function(sc); 1092 } else { 1093 return 0; 1094 } 1095 } 1096 1097 if (sockevent & CB_SOCKET_EVENT_CD) { 1098 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1099 if (0x00 != (sockstate & CB_SOCKET_STAT_CD)) { 1100 /* A card should be removed. */ 1101 if (sc->sc_flags & CBB_CARDEXIST) { 1102 DPRINTF(("%s: 0x%08x", 1103 device_xname(sc->sc_dev), sockevent)); 1104 DPRINTF((" card removed, 0x%08x\n", sockstate)); 1105 sc->sc_flags &= ~CBB_CARDEXIST; 1106 if ((csc = sc->sc_csc) == NULL) 1107 ; 1108 else if (csc->sc_status & 1109 CARDSLOT_STATUS_CARD_16) { 1110 cardslot_event_throw(csc, 1111 CARDSLOT_EVENT_REMOVAL_16); 1112 } else if (csc->sc_status & 1113 CARDSLOT_STATUS_CARD_CB) { 1114 /* Cardbus intr removed */ 1115 cardslot_event_throw(csc, 1116 CARDSLOT_EVENT_REMOVAL_CB); 1117 } 1118 } else if (sc->sc_flags & CBB_INSERTING) { 1119 sc->sc_flags &= ~CBB_INSERTING; 1120 callout_stop(&sc->sc_insert_ch); 1121 } 1122 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 1123 /* 1124 * The pccbbintr may called from powerdown hook when 1125 * the system resumed, to detect the card 1126 * insertion/removal during suspension. 1127 */ 1128 (sc->sc_flags & CBB_CARDEXIST) == 0) { 1129 if (sc->sc_flags & CBB_INSERTING) { 1130 callout_stop(&sc->sc_insert_ch); 1131 } 1132 callout_schedule(&sc->sc_insert_ch, hz / 5); 1133 sc->sc_flags |= CBB_INSERTING; 1134 } 1135 } 1136 1137 return (1); 1138 } 1139 1140 /* 1141 * static int pccbbintr_function(struct pccbb_softc *sc) 1142 * 1143 * This function calls each interrupt handler registered at the 1144 * bridge. The interrupt handlers are called in registered order. 1145 */ 1146 static int 1147 pccbbintr_function(struct pccbb_softc *sc) 1148 { 1149 int retval = 0, val; 1150 struct pccbb_intrhand_list *pil; 1151 int s; 1152 1153 LIST_FOREACH(pil, &sc->sc_pil, pil_next) { 1154 s = splraiseipl(pil->pil_icookie); 1155 val = (*pil->pil_func)(pil->pil_arg); 1156 splx(s); 1157 1158 retval = retval == 1 ? 1 : 1159 retval == 0 ? val : val != 0 ? val : retval; 1160 } 1161 1162 return retval; 1163 } 1164 1165 static void 1166 pci113x_insert(void *arg) 1167 { 1168 struct pccbb_softc *sc = arg; 1169 struct cardslot_softc *csc; 1170 u_int32_t sockevent, sockstate; 1171 1172 if (!(sc->sc_flags & CBB_INSERTING)) { 1173 /* We add a card only under inserting state. */ 1174 return; 1175 } 1176 sc->sc_flags &= ~CBB_INSERTING; 1177 1178 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1179 CB_SOCKET_EVENT); 1180 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1181 CB_SOCKET_STAT); 1182 1183 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1184 DPRINTF(("%s: 0x%08x", device_xname(sc->sc_dev), sockevent)); 1185 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1186 sc->sc_flags |= CBB_CARDEXIST; 1187 /* call pccard interrupt handler here */ 1188 if ((csc = sc->sc_csc) == NULL) 1189 ; 1190 else if (sockstate & CB_SOCKET_STAT_16BIT) { 1191 /* 16-bit card found */ 1192 cardslot_event_throw(csc, CARDSLOT_EVENT_INSERTION_16); 1193 } else if (sockstate & CB_SOCKET_STAT_CB) { 1194 /* cardbus card found */ 1195 cardslot_event_throw(csc, CARDSLOT_EVENT_INSERTION_CB); 1196 } else { 1197 /* who are you? */ 1198 } 1199 } else { 1200 callout_schedule(&sc->sc_insert_ch, hz / 10); 1201 } 1202 } 1203 1204 #define PCCBB_PCMCIA_OFFSET 0x800 1205 static u_int8_t 1206 pccbb_pcmcia_read(struct pccbb_softc *sc, int reg) 1207 { 1208 bus_space_barrier(sc->sc_base_memt, sc->sc_base_memh, 1209 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1210 1211 return bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 1212 PCCBB_PCMCIA_OFFSET + reg); 1213 } 1214 1215 static void 1216 pccbb_pcmcia_write(struct pccbb_softc *sc, int reg, u_int8_t val) 1217 { 1218 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 1219 PCCBB_PCMCIA_OFFSET + reg, val); 1220 1221 bus_space_barrier(sc->sc_base_memt, sc->sc_base_memh, 1222 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1223 } 1224 1225 /* 1226 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1227 */ 1228 STATIC int 1229 pccbb_ctrl(cardbus_chipset_tag_t ct, int command) 1230 { 1231 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1232 1233 switch (command) { 1234 case CARDBUS_CD: 1235 if (2 == pccbb_detect_card(sc)) { 1236 int retval = 0; 1237 int status = cb_detect_voltage(sc); 1238 if (PCCARD_VCC_5V & status) { 1239 retval |= CARDBUS_5V_CARD; 1240 } 1241 if (PCCARD_VCC_3V & status) { 1242 retval |= CARDBUS_3V_CARD; 1243 } 1244 if (PCCARD_VCC_XV & status) { 1245 retval |= CARDBUS_XV_CARD; 1246 } 1247 if (PCCARD_VCC_YV & status) { 1248 retval |= CARDBUS_YV_CARD; 1249 } 1250 return retval; 1251 } else { 1252 return 0; 1253 } 1254 case CARDBUS_RESET: 1255 return cb_reset(sc); 1256 case CARDBUS_IO_ENABLE: /* fallthrough */ 1257 case CARDBUS_IO_DISABLE: /* fallthrough */ 1258 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1259 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1260 case CARDBUS_BM_ENABLE: /* fallthrough */ 1261 case CARDBUS_BM_DISABLE: /* fallthrough */ 1262 /* XXX: I think we don't need to call this function below. */ 1263 return pccbb_cardenable(sc, command); 1264 } 1265 1266 return 0; 1267 } 1268 1269 STATIC int 1270 pccbb_power_ct(cardbus_chipset_tag_t ct, int command) 1271 { 1272 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1273 1274 return pccbb_power(sc, command); 1275 } 1276 1277 /* 1278 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1279 * This function returns true when it succeeds and returns false when 1280 * it fails. 1281 */ 1282 STATIC int 1283 pccbb_power(struct pccbb_softc *sc, int command) 1284 { 1285 u_int32_t status, osock_ctrl, sock_ctrl, reg_ctrl; 1286 bus_space_tag_t memt = sc->sc_base_memt; 1287 bus_space_handle_t memh = sc->sc_base_memh; 1288 int on = 0, pwrcycle, s, times; 1289 struct timeval before, after, diff; 1290 1291 DPRINTF(("pccbb_power: %s and %s [0x%x]\n", 1292 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1293 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1294 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1295 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1296 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1297 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1298 "UNKNOWN", 1299 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1300 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1301 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1302 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1303 "UNKNOWN", command)); 1304 1305 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1306 osock_ctrl = sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1307 1308 switch (command & CARDBUS_VCCMASK) { 1309 case CARDBUS_VCC_UC: 1310 break; 1311 case CARDBUS_VCC_5V: 1312 on++; 1313 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1314 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1315 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1316 } else { 1317 aprint_error_dev(sc->sc_dev, 1318 "BAD voltage request: no 5 V card\n"); 1319 return 0; 1320 } 1321 break; 1322 case CARDBUS_VCC_3V: 1323 on++; 1324 if (CB_SOCKET_STAT_3VCARD & status) { 1325 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1326 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1327 } else { 1328 aprint_error_dev(sc->sc_dev, 1329 "BAD voltage request: no 3.3 V card\n"); 1330 return 0; 1331 } 1332 break; 1333 case CARDBUS_VCC_0V: 1334 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1335 break; 1336 default: 1337 return 0; /* power NEVER changed */ 1338 } 1339 1340 switch (command & CARDBUS_VPPMASK) { 1341 case CARDBUS_VPP_UC: 1342 break; 1343 case CARDBUS_VPP_0V: 1344 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1345 break; 1346 case CARDBUS_VPP_VCC: 1347 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1348 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1349 break; 1350 case CARDBUS_VPP_12V: 1351 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1352 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1353 break; 1354 } 1355 1356 pwrcycle = sc->sc_pwrcycle; 1357 aprint_debug_dev(sc->sc_dev, "osock_ctrl %#" PRIx32 1358 " sock_ctrl %#" PRIx32 "\n", osock_ctrl, sock_ctrl); 1359 1360 microtime(&before); 1361 s = splbio(); 1362 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1363 1364 /* 1365 * Wait as long as 200ms for a power-cycle interrupt. If 1366 * interrupts are enabled, but the socket has already 1367 * changed to the desired status, keep waiting for the 1368 * interrupt. "Consuming" the interrupt in this way keeps 1369 * the interrupt from prematurely waking some subsequent 1370 * pccbb_power call. 1371 * 1372 * XXX Not every bridge interrupts on the ->OFF transition. 1373 * XXX That's ok, we will time-out after 200ms. 1374 * 1375 * XXX The power cycle event will never happen when attaching 1376 * XXX a 16-bit card. That's ok, we will time-out after 1377 * XXX 200ms. 1378 */ 1379 for (times = 5; --times >= 0; ) { 1380 if (cold) 1381 DELAY(40 * 1000); 1382 else { 1383 (void)tsleep(&sc->sc_pwrcycle, PWAIT, "pccpwr", 1384 hz / 25); 1385 if (pwrcycle == sc->sc_pwrcycle) 1386 continue; 1387 } 1388 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1389 if ((status & CB_SOCKET_STAT_PWRCYCLE) != 0 && on) 1390 break; 1391 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0 && !on) 1392 break; 1393 } 1394 splx(s); 1395 microtime(&after); 1396 timersub(&after, &before, &diff); 1397 aprint_debug_dev(sc->sc_dev, "wait took%s %lld.%06lds\n", 1398 (on && times < 0) ? " too long" : "", (long long)diff.tv_sec, 1399 (long)diff.tv_usec); 1400 1401 /* 1402 * Ok, wait a bit longer for things to settle. 1403 */ 1404 if (on && sc->sc_chipset == CB_TOPIC95B) 1405 delay_ms(100, sc); 1406 1407 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1408 1409 if (on && sc->sc_chipset != CB_TOPIC95B) { 1410 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0) 1411 aprint_error_dev(sc->sc_dev, "power on failed?\n"); 1412 } 1413 1414 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1415 aprint_error_dev(sc->sc_dev, 1416 "bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1417 sock_ctrl, status); 1418 aprint_error_dev(sc->sc_dev, "disabling socket\n"); 1419 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1420 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1421 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1422 status &= ~CB_SOCKET_STAT_BADVCC; 1423 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, status); 1424 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1425 CB_SOCKET_STAT)); 1426 return 0; 1427 } 1428 1429 if (sc->sc_chipset == CB_TOPIC97) { 1430 reg_ctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL); 1431 reg_ctrl &= ~TOPIC97_REG_CTRL_TESTMODE; 1432 if ((command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V) 1433 reg_ctrl &= ~TOPIC97_REG_CTRL_CLKRUN_ENA; 1434 else 1435 reg_ctrl |= TOPIC97_REG_CTRL_CLKRUN_ENA; 1436 pci_conf_write(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL, reg_ctrl); 1437 } 1438 1439 return 1; /* power changed correctly */ 1440 } 1441 1442 /* 1443 * static int pccbb_detect_card(struct pccbb_softc *sc) 1444 * return value: 0 if no card exists. 1445 * 1 if 16-bit card exists. 1446 * 2 if cardbus card exists. 1447 */ 1448 static int 1449 pccbb_detect_card(struct pccbb_softc *sc) 1450 { 1451 bus_space_handle_t base_memh = sc->sc_base_memh; 1452 bus_space_tag_t base_memt = sc->sc_base_memt; 1453 u_int32_t sockstat = 1454 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1455 int retval = 0; 1456 1457 /* CD1 and CD2 asserted */ 1458 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1459 /* card must be present */ 1460 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1461 /* NOTACARD DEASSERTED */ 1462 if (CB_SOCKET_STAT_CB & sockstat) { 1463 /* CardBus mode */ 1464 retval = 2; 1465 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1466 /* 16-bit mode */ 1467 retval = 1; 1468 } 1469 } 1470 } 1471 return retval; 1472 } 1473 1474 /* 1475 * STATIC int cb_reset(struct pccbb_softc *sc) 1476 * This function resets CardBus card. 1477 */ 1478 STATIC int 1479 cb_reset(struct pccbb_softc *sc) 1480 { 1481 /* 1482 * Reset Assert at least 20 ms 1483 * Some machines request longer duration. 1484 */ 1485 int reset_duration = 1486 (sc->sc_chipset == CB_RX5C47X ? 400 : 50); 1487 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1488 aprint_debug("%s: enter bcr %" PRIx32 "\n", __func__, bcr); 1489 1490 /* Reset bit Assert (bit 6 at 0x3E) */ 1491 bcr |= PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT; 1492 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr); 1493 aprint_debug("%s: wrote bcr %" PRIx32 "\n", __func__, bcr); 1494 delay_ms(reset_duration, sc); 1495 1496 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1497 /* Reset bit Deassert (bit 6 at 0x3E) */ 1498 bcr &= ~(PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT); 1499 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, 1500 bcr); 1501 aprint_debug("%s: wrote bcr %" PRIx32 "\n", __func__, bcr); 1502 delay_ms(reset_duration, sc); 1503 aprint_debug("%s: end of delay\n", __func__); 1504 } 1505 /* No card found on the slot. Keep Reset. */ 1506 return 1; 1507 } 1508 1509 /* 1510 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1511 * This function detect card Voltage. 1512 */ 1513 STATIC int 1514 cb_detect_voltage(struct pccbb_softc *sc) 1515 { 1516 u_int32_t psr; /* socket present-state reg */ 1517 bus_space_tag_t iot = sc->sc_base_memt; 1518 bus_space_handle_t ioh = sc->sc_base_memh; 1519 int vol = PCCARD_VCC_UKN; /* set 0 */ 1520 1521 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1522 1523 if (0x400u & psr) { 1524 vol |= PCCARD_VCC_5V; 1525 } 1526 if (0x800u & psr) { 1527 vol |= PCCARD_VCC_3V; 1528 } 1529 1530 return vol; 1531 } 1532 1533 STATIC int 1534 cbbprint(void *aux, const char *pcic) 1535 { 1536 #if 0 1537 struct cbslot_attach_args *cba = aux; 1538 1539 if (cba->cba_slot >= 0) { 1540 aprint_normal(" slot %d", cba->cba_slot); 1541 } 1542 #endif 1543 return UNCONF; 1544 } 1545 1546 /* 1547 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1548 * This function enables and disables the card 1549 */ 1550 STATIC int 1551 pccbb_cardenable(struct pccbb_softc *sc, int function) 1552 { 1553 u_int32_t command = 1554 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1555 1556 DPRINTF(("pccbb_cardenable:")); 1557 switch (function) { 1558 case CARDBUS_IO_ENABLE: 1559 command |= PCI_COMMAND_IO_ENABLE; 1560 break; 1561 case CARDBUS_IO_DISABLE: 1562 command &= ~PCI_COMMAND_IO_ENABLE; 1563 break; 1564 case CARDBUS_MEM_ENABLE: 1565 command |= PCI_COMMAND_MEM_ENABLE; 1566 break; 1567 case CARDBUS_MEM_DISABLE: 1568 command &= ~PCI_COMMAND_MEM_ENABLE; 1569 break; 1570 case CARDBUS_BM_ENABLE: 1571 command |= PCI_COMMAND_MASTER_ENABLE; 1572 break; 1573 case CARDBUS_BM_DISABLE: 1574 command &= ~PCI_COMMAND_MASTER_ENABLE; 1575 break; 1576 default: 1577 return 0; 1578 } 1579 1580 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1581 DPRINTF((" command reg 0x%x\n", command)); 1582 return 1; 1583 } 1584 1585 #if !rbus 1586 static int 1587 pccbb_io_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 1588 { 1589 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1590 int basereg; 1591 int limitreg; 1592 1593 if ((win < 0) || (win > 2)) { 1594 #if defined DIAGNOSTIC 1595 printf("cardbus_io_open: window out of range %d\n", win); 1596 #endif 1597 return 0; 1598 } 1599 1600 basereg = win * 8 + PCI_CB_IOBASE0; 1601 limitreg = win * 8 + PCI_CB_IOLIMIT0; 1602 1603 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1604 start, basereg, end, limitreg)); 1605 1606 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1607 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1608 return 1; 1609 } 1610 1611 /* 1612 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1613 */ 1614 static int 1615 pccbb_io_close(cardbus_chipset_tag_t ct, int win) 1616 { 1617 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1618 int basereg; 1619 int limitreg; 1620 1621 if ((win < 0) || (win > 2)) { 1622 #if defined DIAGNOSTIC 1623 printf("cardbus_io_close: window out of range %d\n", win); 1624 #endif 1625 return 0; 1626 } 1627 1628 basereg = win * 8 + PCI_CB_IOBASE0; 1629 limitreg = win * 8 + PCI_CB_IOLIMIT0; 1630 1631 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1632 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1633 return 1; 1634 } 1635 1636 static int 1637 pccbb_mem_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 1638 { 1639 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1640 int basereg; 1641 int limitreg; 1642 1643 if ((win < 0) || (win > 2)) { 1644 #if defined DIAGNOSTIC 1645 printf("cardbus_mem_open: window out of range %d\n", win); 1646 #endif 1647 return 0; 1648 } 1649 1650 basereg = win * 8 + PCI_CB_MEMBASE0; 1651 limitreg = win * 8 + PCI_CB_MEMLIMIT0; 1652 1653 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1654 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1655 return 1; 1656 } 1657 1658 static int 1659 pccbb_mem_close(cardbus_chipset_tag_t ct, int win) 1660 { 1661 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1662 int basereg; 1663 int limitreg; 1664 1665 if ((win < 0) || (win > 2)) { 1666 #if defined DIAGNOSTIC 1667 printf("cardbus_mem_close: window out of range %d\n", win); 1668 #endif 1669 return 0; 1670 } 1671 1672 basereg = win * 8 + PCI_CB_MEMBASE0; 1673 limitreg = win * 8 + PCI_CB_MEMLIMIT0; 1674 1675 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1676 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1677 return 1; 1678 } 1679 #endif 1680 1681 /* 1682 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1683 * int irq, 1684 * int level, 1685 * int (* func)(void *), 1686 * void *arg) 1687 * 1688 * This function registers an interrupt handler at the bridge, in 1689 * order not to call the interrupt handlers of child devices when 1690 * a card-deletion interrupt occurs. 1691 * 1692 * The arguments irq and level are not used. 1693 */ 1694 static void * 1695 pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, cardbus_intr_line_t irq, 1696 int level, int (*func)(void *), void *arg) 1697 { 1698 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1699 1700 return pccbb_intr_establish(sc, irq, level, func, arg); 1701 } 1702 1703 1704 /* 1705 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1706 * void *ih) 1707 * 1708 * This function removes an interrupt handler pointed by ih. 1709 */ 1710 static void 1711 pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih) 1712 { 1713 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1714 1715 pccbb_intr_disestablish(sc, ih); 1716 } 1717 1718 1719 void 1720 pccbb_intr_route(struct pccbb_softc *sc) 1721 { 1722 pcireg_t bcr, cbctrl; 1723 1724 /* initialize bridge intr routing */ 1725 bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1726 bcr &= ~CB_BCR_INTR_IREQ_ENABLE; 1727 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr); 1728 1729 switch (sc->sc_chipset) { 1730 case CB_TI113X: 1731 cbctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1732 /* functional intr enabled */ 1733 cbctrl |= PCI113X_CBCTRL_PCI_INTR; 1734 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, cbctrl); 1735 break; 1736 default: 1737 break; 1738 } 1739 } 1740 1741 /* 1742 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1743 * int irq, 1744 * int level, 1745 * int (* func)(void *), 1746 * void *arg) 1747 * 1748 * This function registers an interrupt handler at the bridge, in 1749 * order not to call the interrupt handlers of child devices when 1750 * a card-deletion interrupt occurs. 1751 * 1752 * The arguments irq is not used because pccbb selects intr vector. 1753 */ 1754 static void * 1755 pccbb_intr_establish(struct pccbb_softc *sc, cardbus_intr_line_t irq, 1756 int level, int (*func)(void *), void *arg) 1757 { 1758 struct pccbb_intrhand_list *pil, *newpil; 1759 1760 DPRINTF(("pccbb_intr_establish start. %p\n", LIST_FIRST(&sc->sc_pil))); 1761 1762 if (LIST_EMPTY(&sc->sc_pil)) { 1763 pccbb_intr_route(sc); 1764 } 1765 1766 /* 1767 * Allocate a room for interrupt handler structure. 1768 */ 1769 if (NULL == (newpil = 1770 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1771 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1772 return NULL; 1773 } 1774 1775 newpil->pil_func = func; 1776 newpil->pil_arg = arg; 1777 newpil->pil_icookie = makeiplcookie(level); 1778 1779 if (LIST_EMPTY(&sc->sc_pil)) { 1780 LIST_INSERT_HEAD(&sc->sc_pil, newpil, pil_next); 1781 } else { 1782 for (pil = LIST_FIRST(&sc->sc_pil); 1783 LIST_NEXT(pil, pil_next) != NULL; 1784 pil = LIST_NEXT(pil, pil_next)); 1785 LIST_INSERT_AFTER(pil, newpil, pil_next); 1786 } 1787 1788 DPRINTF(("pccbb_intr_establish add pil. %p\n", 1789 LIST_FIRST(&sc->sc_pil))); 1790 1791 return newpil; 1792 } 1793 1794 /* 1795 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1796 * void *ih) 1797 * 1798 * This function removes an interrupt handler pointed by ih. ih 1799 * should be the value returned by cardbus_intr_establish() or 1800 * NULL. 1801 * 1802 * When ih is NULL, this function will do nothing. 1803 */ 1804 static void 1805 pccbb_intr_disestablish(struct pccbb_softc *sc, void *ih) 1806 { 1807 struct pccbb_intrhand_list *pil; 1808 pcireg_t reg; 1809 1810 DPRINTF(("pccbb_intr_disestablish start. %p\n", 1811 LIST_FIRST(&sc->sc_pil))); 1812 1813 if (ih == NULL) { 1814 /* intr handler is not set */ 1815 DPRINTF(("pccbb_intr_disestablish: no ih\n")); 1816 return; 1817 } 1818 1819 #ifdef DIAGNOSTIC 1820 LIST_FOREACH(pil, &sc->sc_pil, pil_next) { 1821 DPRINTF(("pccbb_intr_disestablish: pil %p\n", pil)); 1822 if (pil == ih) { 1823 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1824 break; 1825 } 1826 } 1827 if (pil == NULL) { 1828 panic("pccbb_intr_disestablish: %s cannot find pil %p", 1829 device_xname(sc->sc_dev), ih); 1830 } 1831 #endif 1832 1833 pil = (struct pccbb_intrhand_list *)ih; 1834 LIST_REMOVE(pil, pil_next); 1835 free(pil, M_DEVBUF); 1836 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1837 1838 if (LIST_EMPTY(&sc->sc_pil)) { 1839 /* No interrupt handlers */ 1840 1841 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1842 1843 /* stop routing PCI intr */ 1844 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1845 reg |= CB_BCR_INTR_IREQ_ENABLE; 1846 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, reg); 1847 1848 switch (sc->sc_chipset) { 1849 case CB_TI113X: 1850 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1851 /* functional intr disabled */ 1852 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1853 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1854 break; 1855 default: 1856 break; 1857 } 1858 } 1859 } 1860 1861 #if defined SHOW_REGS 1862 static void 1863 cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, bus_space_tag_t memt, 1864 bus_space_handle_t memh) 1865 { 1866 int i; 1867 printf("PCI config regs:"); 1868 for (i = 0; i < 0x50; i += 4) { 1869 if (i % 16 == 0) 1870 printf("\n 0x%02x:", i); 1871 printf(" %08x", pci_conf_read(pc, tag, i)); 1872 } 1873 for (i = 0x80; i < 0xb0; i += 4) { 1874 if (i % 16 == 0) 1875 printf("\n 0x%02x:", i); 1876 printf(" %08x", pci_conf_read(pc, tag, i)); 1877 } 1878 1879 if (memh == 0) { 1880 printf("\n"); 1881 return; 1882 } 1883 1884 printf("\nsocket regs:"); 1885 for (i = 0; i <= 0x10; i += 0x04) 1886 printf(" %08x", bus_space_read_4(memt, memh, i)); 1887 printf("\nExCA regs:"); 1888 for (i = 0; i < 0x08; ++i) 1889 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1890 printf("\n"); 1891 return; 1892 } 1893 #endif 1894 1895 /* 1896 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1897 * int busno, int function) 1898 * This is the function to make a tag to access config space of 1899 * a CardBus Card. It works same as pci_conf_read. 1900 */ 1901 static cardbustag_t 1902 pccbb_make_tag(cardbus_chipset_tag_t cc, int busno, int function) 1903 { 1904 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1905 1906 return pci_make_tag(sc->sc_pc, busno, 0, function); 1907 } 1908 1909 static void 1910 pccbb_free_tag(cardbus_chipset_tag_t cc, cardbustag_t tag) 1911 { 1912 } 1913 1914 /* 1915 * pccbb_conf_read 1916 * 1917 * This is the function to read the config space of a CardBus card. 1918 * It works the same as pci_conf_read(9). 1919 */ 1920 static cardbusreg_t 1921 pccbb_conf_read(cardbus_chipset_tag_t cc, cardbustag_t tag, int offset) 1922 { 1923 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1924 pcitag_t brtag = sc->sc_tag; 1925 cardbusreg_t reg; 1926 1927 /* 1928 * clear cardbus master abort status; it is OK to write without 1929 * reading before because all bits are r/o or w1tc 1930 */ 1931 pci_conf_write(sc->sc_pc, brtag, PCI_CBB_SECSTATUS, 1932 CBB_SECSTATUS_CBMABORT); 1933 reg = pci_conf_read(sc->sc_pc, tag, offset); 1934 /* check cardbus master abort status */ 1935 if (pci_conf_read(sc->sc_pc, brtag, PCI_CBB_SECSTATUS) 1936 & CBB_SECSTATUS_CBMABORT) 1937 return (0xffffffff); 1938 return reg; 1939 } 1940 1941 /* 1942 * pccbb_conf_write 1943 * 1944 * This is the function to write the config space of a CardBus 1945 * card. It works the same as pci_conf_write(9). 1946 */ 1947 static void 1948 pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, int reg, 1949 cardbusreg_t val) 1950 { 1951 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1952 1953 pci_conf_write(sc->sc_pc, tag, reg, val); 1954 } 1955 1956 #if 0 1957 STATIC int 1958 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1959 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 1960 int speed, int flags, 1961 bus_space_handle_t * iohp) 1962 #endif 1963 /* 1964 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1965 * bus_addr_t start, bus_size_t size, 1966 * bus_size_t align, 1967 * struct pcmcia_io_handle *pcihp 1968 * 1969 * This function only allocates I/O region for pccard. This function 1970 * never maps the allocated region to pccard I/O area. 1971 * 1972 * XXX: The interface of this function is not very good, I believe. 1973 */ 1974 STATIC int 1975 pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, 1976 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 1977 { 1978 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 1979 bus_addr_t ioaddr; 1980 int flags = 0; 1981 bus_space_tag_t iot; 1982 bus_space_handle_t ioh; 1983 bus_addr_t mask; 1984 #if rbus 1985 rbus_tag_t rb; 1986 #endif 1987 if (align == 0) { 1988 align = size; /* XXX: funny??? */ 1989 } 1990 1991 if (start != 0) { 1992 /* XXX: assume all card decode lower 10 bits by its hardware */ 1993 mask = 0x3ff; 1994 /* enforce to use only masked address */ 1995 start &= mask; 1996 } else { 1997 /* 1998 * calculate mask: 1999 * 1. get the most significant bit of size (call it msb). 2000 * 2. compare msb with the value of size. 2001 * 3. if size is larger, shift msb left once. 2002 * 4. obtain mask value to decrement msb. 2003 */ 2004 bus_size_t size_tmp = size; 2005 int shifts = 0; 2006 2007 mask = 1; 2008 while (size_tmp) { 2009 ++shifts; 2010 size_tmp >>= 1; 2011 } 2012 mask = (1 << shifts); 2013 if (mask < size) { 2014 mask <<= 1; 2015 } 2016 --mask; 2017 } 2018 2019 /* 2020 * Allocate some arbitrary I/O space. 2021 */ 2022 2023 iot = sc->sc_iot; 2024 2025 #if rbus 2026 rb = sc->sc_rbus_iot; 2027 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 2028 return 1; 2029 } 2030 DPRINTF(("pccbb_pcmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2031 (u_long) ioaddr, (u_long) size)); 2032 #else 2033 if (start) { 2034 ioaddr = start; 2035 if (bus_space_map(iot, start, size, 0, &ioh)) { 2036 return 1; 2037 } 2038 DPRINTF(("pccbb_pcmcia_io_alloc map port 0x%lx+0x%lx\n", 2039 (u_long) ioaddr, (u_long) size)); 2040 } else { 2041 flags |= PCMCIA_IO_ALLOCATED; 2042 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 2043 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 2044 size, align, 0, 0, &ioaddr, &ioh)) { 2045 /* No room be able to be get. */ 2046 return 1; 2047 } 2048 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2049 (u_long) ioaddr, (u_long) size)); 2050 } 2051 #endif 2052 2053 pcihp->iot = iot; 2054 pcihp->ioh = ioh; 2055 pcihp->addr = ioaddr; 2056 pcihp->size = size; 2057 pcihp->flags = flags; 2058 2059 return 0; 2060 } 2061 2062 /* 2063 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2064 * struct pcmcia_io_handle *pcihp) 2065 * 2066 * This function only frees I/O region for pccard. 2067 * 2068 * XXX: The interface of this function is not very good, I believe. 2069 */ 2070 void 2071 pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2072 struct pcmcia_io_handle *pcihp) 2073 { 2074 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2075 #if !rbus 2076 bus_space_tag_t iot = pcihp->iot; 2077 #endif 2078 bus_space_handle_t ioh = pcihp->ioh; 2079 bus_size_t size = pcihp->size; 2080 2081 #if rbus 2082 rbus_tag_t rb = sc->sc_rbus_iot; 2083 2084 rbus_space_free(rb, ioh, size, NULL); 2085 #else 2086 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 2087 bus_space_free(iot, ioh, size); 2088 else 2089 bus_space_unmap(iot, ioh, size); 2090 #endif 2091 } 2092 2093 /* 2094 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 2095 * bus_addr_t offset, bus_size_t size, 2096 * struct pcmcia_io_handle *pcihp, 2097 * int *windowp) 2098 * 2099 * This function maps the allocated I/O region to pccard. This function 2100 * never allocates any I/O region for pccard I/O area. I don't 2101 * understand why the original authors of pcmciabus separated alloc and 2102 * map. I believe the two must be unite. 2103 * 2104 * XXX: no wait timing control? 2105 */ 2106 int 2107 pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, bus_addr_t offset, 2108 bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp) 2109 { 2110 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2111 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2112 bus_addr_t ioaddr = pcihp->addr + offset; 2113 int i, win; 2114 #if defined CBB_DEBUG 2115 static const char *width_names[] = { "dynamic", "io8", "io16" }; 2116 #endif 2117 2118 /* Sanity check I/O handle. */ 2119 2120 if (sc->sc_iot != pcihp->iot) { 2121 panic("pccbb_pcmcia_io_map iot is bogus"); 2122 } 2123 2124 /* XXX Sanity check offset/size. */ 2125 2126 win = -1; 2127 for (i = 0; i < PCIC_IO_WINS; i++) { 2128 if ((ph->ioalloc & (1 << i)) == 0) { 2129 win = i; 2130 ph->ioalloc |= (1 << i); 2131 break; 2132 } 2133 } 2134 2135 if (win == -1) { 2136 return 1; 2137 } 2138 2139 *windowp = win; 2140 2141 /* XXX this is pretty gross */ 2142 2143 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2144 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2145 2146 /* XXX wtf is this doing here? */ 2147 2148 #if 0 2149 printf(" port 0x%lx", (u_long) ioaddr); 2150 if (size > 1) { 2151 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2152 } 2153 #endif 2154 2155 ph->io[win].addr = ioaddr; 2156 ph->io[win].size = size; 2157 ph->io[win].width = width; 2158 2159 /* actual dirty register-value changing in the function below. */ 2160 pccbb_pcmcia_do_io_map(sc, win); 2161 2162 return 0; 2163 } 2164 2165 /* 2166 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2167 * 2168 * This function changes register-value to map I/O region for pccard. 2169 */ 2170 static void 2171 pccbb_pcmcia_do_io_map(struct pccbb_softc *sc, int win) 2172 { 2173 static u_int8_t pcic_iowidth[3] = { 2174 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2175 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2176 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2177 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2178 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2179 }; 2180 2181 #define PCIC_SIA_START_LOW 0 2182 #define PCIC_SIA_START_HIGH 1 2183 #define PCIC_SIA_STOP_LOW 2 2184 #define PCIC_SIA_STOP_HIGH 3 2185 2186 int regbase_win = 0x8 + win * 0x04; 2187 u_int8_t ioctl, enable; 2188 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2189 2190 DPRINTF(("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx " 2191 "width %d\n", win, (unsigned long)ph->io[win].addr, 2192 (unsigned long)ph->io[win].size, ph->io[win].width * 8)); 2193 2194 Pcic_write(sc, regbase_win + PCIC_SIA_START_LOW, 2195 ph->io[win].addr & 0xff); 2196 Pcic_write(sc, regbase_win + PCIC_SIA_START_HIGH, 2197 (ph->io[win].addr >> 8) & 0xff); 2198 2199 Pcic_write(sc, regbase_win + PCIC_SIA_STOP_LOW, 2200 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2201 Pcic_write(sc, regbase_win + PCIC_SIA_STOP_HIGH, 2202 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2203 2204 ioctl = Pcic_read(sc, PCIC_IOCTL); 2205 enable = Pcic_read(sc, PCIC_ADDRWIN_ENABLE); 2206 switch (win) { 2207 case 0: 2208 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2209 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2210 PCIC_IOCTL_IO0_DATASIZE_MASK); 2211 ioctl |= pcic_iowidth[ph->io[win].width]; 2212 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2213 break; 2214 case 1: 2215 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2216 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2217 PCIC_IOCTL_IO1_DATASIZE_MASK); 2218 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2219 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2220 break; 2221 } 2222 Pcic_write(sc, PCIC_IOCTL, ioctl); 2223 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, enable); 2224 #if defined(CBB_DEBUG) 2225 { 2226 u_int8_t start_low = 2227 Pcic_read(sc, regbase_win + PCIC_SIA_START_LOW); 2228 u_int8_t start_high = 2229 Pcic_read(sc, regbase_win + PCIC_SIA_START_HIGH); 2230 u_int8_t stop_low = 2231 Pcic_read(sc, regbase_win + PCIC_SIA_STOP_LOW); 2232 u_int8_t stop_high = 2233 Pcic_read(sc, regbase_win + PCIC_SIA_STOP_HIGH); 2234 printf("pccbb_pcmcia_do_io_map start %02x %02x, " 2235 "stop %02x %02x, ioctl %02x enable %02x\n", 2236 start_low, start_high, stop_low, stop_high, ioctl, enable); 2237 } 2238 #endif 2239 } 2240 2241 /* 2242 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2243 * 2244 * This function unmaps I/O region. No return value. 2245 */ 2246 STATIC void 2247 pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t pch, int win) 2248 { 2249 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2250 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2251 int reg; 2252 2253 if (win >= PCIC_IO_WINS || win < 0) { 2254 panic("pccbb_pcmcia_io_unmap: window out of range"); 2255 } 2256 2257 reg = Pcic_read(sc, PCIC_ADDRWIN_ENABLE); 2258 switch (win) { 2259 case 0: 2260 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2261 break; 2262 case 1: 2263 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2264 break; 2265 } 2266 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, reg); 2267 2268 ph->ioalloc &= ~(1 << win); 2269 } 2270 2271 static int 2272 pccbb_pcmcia_wait_ready(struct pccbb_softc *sc) 2273 { 2274 u_int8_t stat; 2275 int i; 2276 2277 /* wait an initial 10ms for quick cards */ 2278 stat = Pcic_read(sc, PCIC_IF_STATUS); 2279 if (stat & PCIC_IF_STATUS_READY) 2280 return (0); 2281 pccbb_pcmcia_delay(sc, 10, "pccwr0"); 2282 for (i = 0; i < 50; i++) { 2283 stat = Pcic_read(sc, PCIC_IF_STATUS); 2284 if (stat & PCIC_IF_STATUS_READY) 2285 return (0); 2286 if ((stat & PCIC_IF_STATUS_CARDDETECT_MASK) != 2287 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2288 return (ENXIO); 2289 /* wait .1s (100ms) each iteration now */ 2290 pccbb_pcmcia_delay(sc, 100, "pccwr1"); 2291 } 2292 2293 printf("pccbb_pcmcia_wait_ready: ready never happened, status=%02x\n", stat); 2294 return (EWOULDBLOCK); 2295 } 2296 2297 /* 2298 * Perform long (msec order) delay. timo is in milliseconds. 2299 */ 2300 static void 2301 pccbb_pcmcia_delay(struct pccbb_softc *sc, int timo, const char *wmesg) 2302 { 2303 #ifdef DIAGNOSTIC 2304 if (timo <= 0) 2305 panic("pccbb_pcmcia_delay: called with timeout %d", timo); 2306 if (!curlwp) 2307 panic("pccbb_pcmcia_delay: called in interrupt context"); 2308 #endif 2309 DPRINTF(("pccbb_pcmcia_delay: \"%s\", sleep %d ms\n", wmesg, timo)); 2310 tsleep(pccbb_pcmcia_delay, PWAIT, wmesg, roundup(timo * hz, 1000) / 1000); 2311 } 2312 2313 /* 2314 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2315 * 2316 * This function enables the card. All information is stored in 2317 * the first argument, pcmcia_chipset_handle_t. 2318 */ 2319 STATIC void 2320 pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2321 { 2322 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2323 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2324 pcireg_t spsr; 2325 int voltage; 2326 int win; 2327 u_int8_t power, intr; 2328 #ifdef DIAGNOSTIC 2329 int reg; 2330 #endif 2331 2332 /* this bit is mostly stolen from pcic_attach_card */ 2333 2334 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2335 2336 /* get card Vcc info */ 2337 spsr = 2338 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2339 CB_SOCKET_STAT); 2340 if (spsr & CB_SOCKET_STAT_5VCARD) { 2341 DPRINTF(("5V card\n")); 2342 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2343 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2344 DPRINTF(("3V card\n")); 2345 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2346 } else { 2347 DPRINTF(("?V card, 0x%x\n", spsr)); /* XXX */ 2348 return; 2349 } 2350 2351 /* disable interrupts; assert RESET */ 2352 intr = Pcic_read(sc, PCIC_INTR); 2353 intr &= PCIC_INTR_ENABLE; 2354 Pcic_write(sc, PCIC_INTR, intr); 2355 2356 /* zero out the address windows */ 2357 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, 0); 2358 2359 /* power down the socket to reset it, clear the card reset pin */ 2360 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2361 2362 /* power off; assert output enable bit */ 2363 power = PCIC_PWRCTL_OE; 2364 Pcic_write(sc, PCIC_PWRCTL, power); 2365 2366 /* power up the socket */ 2367 if (pccbb_power(sc, voltage) == 0) 2368 return; 2369 2370 /* 2371 * Table 4-18 and figure 4-6 of the PC Card specifiction say: 2372 * Vcc Rising Time (Tpr) = 100ms (handled in pccbb_power() above) 2373 * RESET Width (Th (Hi-z RESET)) = 1ms 2374 * RESET Width (Tw (RESET)) = 10us 2375 * 2376 * some machines require some more time to be settled 2377 * for example old toshiba topic bridges! 2378 * (100ms is added here). 2379 */ 2380 pccbb_pcmcia_delay(sc, 200 + 1, "pccen1"); 2381 2382 /* negate RESET */ 2383 intr |= PCIC_INTR_RESET; 2384 Pcic_write(sc, PCIC_INTR, intr); 2385 2386 /* 2387 * RESET Setup Time (Tsu (RESET)) = 20ms 2388 */ 2389 pccbb_pcmcia_delay(sc, 20, "pccen2"); 2390 2391 #ifdef DIAGNOSTIC 2392 reg = Pcic_read(sc, PCIC_IF_STATUS); 2393 if ((reg & PCIC_IF_STATUS_POWERACTIVE) == 0) 2394 printf("pccbb_pcmcia_socket_enable: no power, status=%x\n", reg); 2395 #endif 2396 2397 /* wait for the chip to finish initializing */ 2398 if (pccbb_pcmcia_wait_ready(sc)) { 2399 #ifdef DIAGNOSTIC 2400 printf("pccbb_pcmcia_socket_enable: never became ready\n"); 2401 #endif 2402 /* XXX return a failure status?? */ 2403 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2404 Pcic_write(sc, PCIC_PWRCTL, 0); 2405 return; 2406 } 2407 2408 /* reinstall all the memory and io mappings */ 2409 for (win = 0; win < PCIC_MEM_WINS; ++win) 2410 if (ph->memalloc & (1 << win)) 2411 pccbb_pcmcia_do_mem_map(sc, win); 2412 for (win = 0; win < PCIC_IO_WINS; ++win) 2413 if (ph->ioalloc & (1 << win)) 2414 pccbb_pcmcia_do_io_map(sc, win); 2415 } 2416 2417 /* 2418 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2419 * 2420 * This function disables the card. All information is stored in 2421 * the first argument, pcmcia_chipset_handle_t. 2422 */ 2423 STATIC void 2424 pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t pch) 2425 { 2426 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2427 u_int8_t intr; 2428 2429 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2430 2431 /* disable interrupts; assert RESET */ 2432 intr = Pcic_read(sc, PCIC_INTR); 2433 intr &= PCIC_INTR_ENABLE; 2434 Pcic_write(sc, PCIC_INTR, intr); 2435 2436 /* zero out the address windows */ 2437 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, 0); 2438 2439 /* power down the socket to reset it, clear the card reset pin */ 2440 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2441 2442 /* disable socket: negate output enable bit and power off */ 2443 Pcic_write(sc, PCIC_PWRCTL, 0); 2444 2445 /* 2446 * Vcc Falling Time (Tpf) = 300ms 2447 */ 2448 pccbb_pcmcia_delay(sc, 300, "pccwr1"); 2449 } 2450 2451 STATIC void 2452 pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t pch, int type) 2453 { 2454 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2455 u_int8_t intr; 2456 2457 /* set the card type */ 2458 2459 intr = Pcic_read(sc, PCIC_INTR); 2460 intr &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_CARDTYPE_MASK); 2461 if (type == PCMCIA_IFTYPE_IO) 2462 intr |= PCIC_INTR_CARDTYPE_IO; 2463 else 2464 intr |= PCIC_INTR_CARDTYPE_MEM; 2465 Pcic_write(sc, PCIC_INTR, intr); 2466 2467 DPRINTF(("%s: pccbb_pcmcia_socket_settype type %s %02x\n", 2468 device_xname(sc->sc_dev), 2469 ((type == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2470 } 2471 2472 /* 2473 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2474 * 2475 * This function detects whether a card is in the slot or not. 2476 * If a card is inserted, return 1. Otherwise, return 0. 2477 */ 2478 STATIC int 2479 pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch) 2480 { 2481 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2482 2483 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2484 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2485 } 2486 2487 #if 0 2488 STATIC int 2489 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2490 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2491 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2492 #endif 2493 /* 2494 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2495 * bus_size_t size, 2496 * struct pcmcia_mem_handle *pcmhp) 2497 * 2498 * This function only allocates memory region for pccard. This 2499 * function never maps the allocated region to pccard memory area. 2500 * 2501 * XXX: Why the argument of start address is not in? 2502 */ 2503 STATIC int 2504 pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 2505 struct pcmcia_mem_handle *pcmhp) 2506 { 2507 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2508 bus_space_handle_t memh; 2509 bus_addr_t addr; 2510 bus_size_t sizepg; 2511 #if rbus 2512 rbus_tag_t rb; 2513 #endif 2514 2515 /* Check that the card is still there. */ 2516 if ((Pcic_read(sc, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2517 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2518 return 1; 2519 2520 /* out of sc->memh, allocate as many pages as necessary */ 2521 2522 /* convert size to PCIC pages */ 2523 /* 2524 * This is not enough; when the requested region is on the page 2525 * boundaries, this may calculate wrong result. 2526 */ 2527 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2528 #if 0 2529 if (sizepg > PCIC_MAX_MEM_PAGES) { 2530 return 1; 2531 } 2532 #endif 2533 2534 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2535 return 1; 2536 } 2537 2538 addr = 0; /* XXX gcc -Wuninitialized */ 2539 2540 #if rbus 2541 rb = sc->sc_rbus_memt; 2542 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2543 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2544 &addr, &memh)) { 2545 return 1; 2546 } 2547 #else 2548 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2549 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2550 0, /* boundary */ 2551 0, /* flags */ 2552 &addr, &memh)) { 2553 return 1; 2554 } 2555 #endif 2556 2557 DPRINTF(("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, " 2558 "realsize 0x%lx\n", (unsigned long)addr, (unsigned long)size, 2559 (unsigned long)sizepg * PCIC_MEM_PAGESIZE)); 2560 2561 pcmhp->memt = sc->sc_memt; 2562 pcmhp->memh = memh; 2563 pcmhp->addr = addr; 2564 pcmhp->size = size; 2565 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2566 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2567 pcmhp->mhandle = 0; 2568 /* No offset??? Funny. */ 2569 2570 return 0; 2571 } 2572 2573 /* 2574 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2575 * struct pcmcia_mem_handle *pcmhp) 2576 * 2577 * This function release the memory space allocated by the function 2578 * pccbb_pcmcia_mem_alloc(). 2579 */ 2580 STATIC void 2581 pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2582 struct pcmcia_mem_handle *pcmhp) 2583 { 2584 #if rbus 2585 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2586 2587 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2588 #else 2589 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2590 #endif 2591 } 2592 2593 /* 2594 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2595 * 2596 * This function release the memory space allocated by the function 2597 * pccbb_pcmcia_mem_alloc(). 2598 */ 2599 STATIC void 2600 pccbb_pcmcia_do_mem_map(struct pccbb_softc *sc, int win) 2601 { 2602 int regbase_win; 2603 bus_addr_t phys_addr; 2604 bus_addr_t phys_end; 2605 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2606 2607 #define PCIC_SMM_START_LOW 0 2608 #define PCIC_SMM_START_HIGH 1 2609 #define PCIC_SMM_STOP_LOW 2 2610 #define PCIC_SMM_STOP_HIGH 3 2611 #define PCIC_CMA_LOW 4 2612 #define PCIC_CMA_HIGH 5 2613 2614 u_int8_t start_low, start_high = 0; 2615 u_int8_t stop_low, stop_high; 2616 u_int8_t off_low, off_high; 2617 u_int8_t mem_window; 2618 int reg; 2619 2620 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2621 int mem8 = 2622 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2623 || (kind == PCMCIA_MEM_ATTR); 2624 2625 regbase_win = 0x10 + win * 0x08; 2626 2627 phys_addr = ph->mem[win].addr; 2628 phys_end = phys_addr + ph->mem[win].size; 2629 2630 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2631 (unsigned long)phys_addr, (unsigned long)phys_end, 2632 (unsigned long)ph->mem[win].offset)); 2633 2634 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2635 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2636 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2637 2638 /* bit 19:12 */ 2639 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2640 /* bit 23:20 and bit 7 on */ 2641 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2642 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2643 /* bit 31:24, for 32-bit address */ 2644 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2645 2646 Pcic_write(sc, regbase_win + PCIC_SMM_START_LOW, start_low); 2647 Pcic_write(sc, regbase_win + PCIC_SMM_START_HIGH, start_high); 2648 2649 if (sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2650 Pcic_write(sc, 0x40 + win, mem_window); 2651 } 2652 2653 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2654 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2655 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2656 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2657 2658 Pcic_write(sc, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2659 Pcic_write(sc, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2660 2661 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2662 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2663 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2664 | ((kind == PCMCIA_MEM_ATTR) ? 2665 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2666 2667 Pcic_write(sc, regbase_win + PCIC_CMA_LOW, off_low); 2668 Pcic_write(sc, regbase_win + PCIC_CMA_HIGH, off_high); 2669 2670 reg = Pcic_read(sc, PCIC_ADDRWIN_ENABLE); 2671 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2672 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, reg); 2673 2674 #if defined(CBB_DEBUG) 2675 { 2676 int r1, r2, r3, r4, r5, r6, r7 = 0; 2677 2678 r1 = Pcic_read(sc, regbase_win + PCIC_SMM_START_LOW); 2679 r2 = Pcic_read(sc, regbase_win + PCIC_SMM_START_HIGH); 2680 r3 = Pcic_read(sc, regbase_win + PCIC_SMM_STOP_LOW); 2681 r4 = Pcic_read(sc, regbase_win + PCIC_SMM_STOP_HIGH); 2682 r5 = Pcic_read(sc, regbase_win + PCIC_CMA_LOW); 2683 r6 = Pcic_read(sc, regbase_win + PCIC_CMA_HIGH); 2684 if (sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2685 r7 = Pcic_read(sc, 0x40 + win); 2686 } 2687 2688 printf("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2689 "%02x%02x", win, r1, r2, r3, r4, r5, r6); 2690 if (sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2691 printf(" %02x", r7); 2692 } 2693 printf("\n"); 2694 } 2695 #endif 2696 } 2697 2698 /* 2699 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2700 * bus_addr_t card_addr, bus_size_t size, 2701 * struct pcmcia_mem_handle *pcmhp, 2702 * bus_addr_t *offsetp, int *windowp) 2703 * 2704 * This function maps memory space allocated by the function 2705 * pccbb_pcmcia_mem_alloc(). 2706 */ 2707 STATIC int 2708 pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2709 bus_addr_t card_addr, bus_size_t size, struct pcmcia_mem_handle *pcmhp, 2710 bus_size_t *offsetp, int *windowp) 2711 { 2712 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2713 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2714 bus_addr_t busaddr; 2715 long card_offset; 2716 int win; 2717 2718 /* Check that the card is still there. */ 2719 if ((Pcic_read(sc, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2720 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2721 return 1; 2722 2723 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2724 if ((ph->memalloc & (1 << win)) == 0) { 2725 ph->memalloc |= (1 << win); 2726 break; 2727 } 2728 } 2729 2730 if (win == PCIC_MEM_WINS) { 2731 return 1; 2732 } 2733 2734 *windowp = win; 2735 2736 /* XXX this is pretty gross */ 2737 2738 if (sc->sc_memt != pcmhp->memt) { 2739 panic("pccbb_pcmcia_mem_map memt is bogus"); 2740 } 2741 2742 busaddr = pcmhp->addr; 2743 2744 /* 2745 * compute the address offset to the pcmcia address space for the 2746 * pcic. this is intentionally signed. The masks and shifts below 2747 * will cause TRT to happen in the pcic registers. Deal with making 2748 * sure the address is aligned, and return the alignment offset. 2749 */ 2750 2751 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2752 card_addr -= *offsetp; 2753 2754 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2755 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2756 (u_long) card_addr)); 2757 2758 /* 2759 * include the offset in the size, and decrement size by one, since 2760 * the hw wants start/stop 2761 */ 2762 size += *offsetp - 1; 2763 2764 card_offset = (((long)card_addr) - ((long)busaddr)); 2765 2766 ph->mem[win].addr = busaddr; 2767 ph->mem[win].size = size; 2768 ph->mem[win].offset = card_offset; 2769 ph->mem[win].kind = kind; 2770 2771 pccbb_pcmcia_do_mem_map(sc, win); 2772 2773 return 0; 2774 } 2775 2776 /* 2777 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2778 * int window) 2779 * 2780 * This function unmaps memory space which mapped by the function 2781 * pccbb_pcmcia_mem_map(). 2782 */ 2783 STATIC void 2784 pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, int window) 2785 { 2786 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2787 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2788 int reg; 2789 2790 if (window >= PCIC_MEM_WINS) { 2791 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2792 } 2793 2794 reg = Pcic_read(sc, PCIC_ADDRWIN_ENABLE); 2795 reg &= ~(1 << window); 2796 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, reg); 2797 2798 ph->memalloc &= ~(1 << window); 2799 } 2800 2801 /* 2802 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2803 * struct pcmcia_function *pf, 2804 * int ipl, 2805 * int (*func)(void *), 2806 * void *arg); 2807 * 2808 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2809 */ 2810 STATIC void * 2811 pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2812 struct pcmcia_function *pf, int ipl, int (*func)(void *), void *arg) 2813 { 2814 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2815 2816 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2817 /* what should I do? */ 2818 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2819 DPRINTF(("%s does not provide edge nor pulse " 2820 "interrupt\n", device_xname(sc->sc_dev))); 2821 return NULL; 2822 } 2823 /* 2824 * XXX Noooooo! The interrupt flag must set properly!! 2825 * dumb pcmcia driver!! 2826 */ 2827 } 2828 2829 return pccbb_intr_establish(sc, 0, ipl, func, arg); 2830 } 2831 2832 /* 2833 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2834 * void *ih) 2835 * 2836 * This function disables PC-Card interrupt. 2837 */ 2838 STATIC void 2839 pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 2840 { 2841 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2842 2843 pccbb_intr_disestablish(sc, ih); 2844 } 2845 2846 #if rbus 2847 /* 2848 * static int 2849 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2850 * bus_addr_t addr, bus_size_t size, 2851 * bus_addr_t mask, bus_size_t align, 2852 * int flags, bus_addr_t *addrp; 2853 * bus_space_handle_t *bshp) 2854 * 2855 * This function allocates a portion of memory or io space for 2856 * clients. This function is called from CardBus card drivers. 2857 */ 2858 static int 2859 pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2860 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 2861 int flags, bus_addr_t *addrp, bus_space_handle_t *bshp) 2862 { 2863 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2864 2865 DPRINTF(("pccbb_rbus_cb_space_alloc: addr 0x%lx, size 0x%lx, " 2866 "mask 0x%lx, align 0x%lx\n", (unsigned long)addr, 2867 (unsigned long)size, (unsigned long)mask, (unsigned long)align)); 2868 2869 if (align == 0) { 2870 align = size; 2871 } 2872 2873 if (rb->rb_bt == sc->sc_memt) { 2874 if (align < 16) { 2875 return 1; 2876 } 2877 /* 2878 * XXX: align more than 0x1000 to avoid overwrapping 2879 * memory windows for two or more devices. 0x1000 2880 * means memory window's granularity. 2881 * 2882 * Two or more devices should be able to share same 2883 * memory window region. However, overrapping memory 2884 * window is not good because some devices, such as 2885 * 3Com 3C575[BC], have a broken address decoder and 2886 * intrude other's memory region. 2887 */ 2888 if (align < 0x1000) { 2889 align = 0x1000; 2890 } 2891 } else if (rb->rb_bt == sc->sc_iot) { 2892 if (align < 4) { 2893 return 1; 2894 } 2895 /* XXX: hack for avoiding ISA image */ 2896 if (mask < 0x0100) { 2897 mask = 0x3ff; 2898 addr = 0x300; 2899 } 2900 2901 } else { 2902 DPRINTF(("pccbb_rbus_cb_space_alloc: Bus space tag 0x%lx is " 2903 "NOT used. io: 0x%lx, mem: 0x%lx\n", 2904 (unsigned long)rb->rb_bt, (unsigned long)sc->sc_iot, 2905 (unsigned long)sc->sc_memt)); 2906 return 1; 2907 /* XXX: panic here? */ 2908 } 2909 2910 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 2911 aprint_normal_dev(sc->sc_dev, "<rbus> no bus space\n"); 2912 return 1; 2913 } 2914 2915 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 2916 2917 return 0; 2918 } 2919 2920 /* 2921 * static int 2922 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 2923 * bus_space_handle_t *bshp, bus_size_t size); 2924 * 2925 * This function is called from CardBus card drivers. 2926 */ 2927 static int 2928 pccbb_rbus_cb_space_free(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2929 bus_space_handle_t bsh, bus_size_t size) 2930 { 2931 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2932 bus_space_tag_t bt = rb->rb_bt; 2933 2934 pccbb_close_win(sc, bt, bsh, size); 2935 2936 if (bt == sc->sc_memt) { 2937 } else if (bt == sc->sc_iot) { 2938 } else { 2939 return 1; 2940 /* XXX: panic here? */ 2941 } 2942 2943 return rbus_space_free(rb, bsh, size, NULL); 2944 } 2945 #endif /* rbus */ 2946 2947 #if rbus 2948 2949 static int 2950 pccbb_open_win(struct pccbb_softc *sc, bus_space_tag_t bst, bus_addr_t addr, 2951 bus_size_t size, bus_space_handle_t bsh, int flags) 2952 { 2953 struct pccbb_win_chain_head *head; 2954 bus_addr_t align; 2955 2956 head = &sc->sc_iowindow; 2957 align = 0x04; 2958 if (sc->sc_memt == bst) { 2959 head = &sc->sc_memwindow; 2960 align = 0x1000; 2961 DPRINTF(("using memory window, 0x%lx 0x%lx 0x%lx\n\n", 2962 (unsigned long)sc->sc_iot, (unsigned long)sc->sc_memt, 2963 (unsigned long)bst)); 2964 } 2965 2966 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 2967 aprint_error_dev(sc->sc_dev, 2968 "pccbb_open_win: %s winlist insert failed\n", 2969 (head == &sc->sc_memwindow) ? "mem" : "io"); 2970 } 2971 pccbb_winset(align, sc, bst); 2972 2973 return 0; 2974 } 2975 2976 static int 2977 pccbb_close_win(struct pccbb_softc *sc, bus_space_tag_t bst, 2978 bus_space_handle_t bsh, bus_size_t size) 2979 { 2980 struct pccbb_win_chain_head *head; 2981 bus_addr_t align; 2982 2983 head = &sc->sc_iowindow; 2984 align = 0x04; 2985 if (sc->sc_memt == bst) { 2986 head = &sc->sc_memwindow; 2987 align = 0x1000; 2988 } 2989 2990 if (pccbb_winlist_delete(head, bsh, size)) { 2991 aprint_error_dev(sc->sc_dev, 2992 "pccbb_close_win: %s winlist delete failed\n", 2993 (head == &sc->sc_memwindow) ? "mem" : "io"); 2994 } 2995 pccbb_winset(align, sc, bst); 2996 2997 return 0; 2998 } 2999 3000 static int 3001 pccbb_winlist_insert(struct pccbb_win_chain_head *head, bus_addr_t start, 3002 bus_size_t size, bus_space_handle_t bsh, int flags) 3003 { 3004 struct pccbb_win_chain *chainp, *elem; 3005 3006 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 3007 M_NOWAIT)) == NULL) 3008 return (1); /* fail */ 3009 3010 elem->wc_start = start; 3011 elem->wc_end = start + (size - 1); 3012 elem->wc_handle = bsh; 3013 elem->wc_flags = flags; 3014 3015 TAILQ_FOREACH(chainp, head, wc_list) { 3016 if (chainp->wc_end >= start) 3017 break; 3018 } 3019 if (chainp != NULL) 3020 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 3021 else 3022 TAILQ_INSERT_TAIL(head, elem, wc_list); 3023 return (0); 3024 } 3025 3026 static int 3027 pccbb_winlist_delete(struct pccbb_win_chain_head *head, bus_space_handle_t bsh, 3028 bus_size_t size) 3029 { 3030 struct pccbb_win_chain *chainp; 3031 3032 TAILQ_FOREACH(chainp, head, wc_list) { 3033 if (memcmp(&chainp->wc_handle, &bsh, sizeof(bsh)) == 0) 3034 break; 3035 } 3036 if (chainp == NULL) 3037 return 1; /* fail: no candidate to remove */ 3038 3039 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 3040 printf("pccbb_winlist_delete: window 0x%lx size " 3041 "inconsistent: 0x%lx, 0x%lx\n", 3042 (unsigned long)chainp->wc_start, 3043 (unsigned long)(chainp->wc_end - chainp->wc_start), 3044 (unsigned long)(size - 1)); 3045 return 1; 3046 } 3047 3048 TAILQ_REMOVE(head, chainp, wc_list); 3049 free(chainp, M_DEVBUF); 3050 3051 return 0; 3052 } 3053 3054 static void 3055 pccbb_winset(bus_addr_t align, struct pccbb_softc *sc, bus_space_tag_t bst) 3056 { 3057 pci_chipset_tag_t pc; 3058 pcitag_t tag; 3059 bus_addr_t mask = ~(align - 1); 3060 struct { 3061 cardbusreg_t win_start; 3062 cardbusreg_t win_limit; 3063 int win_flags; 3064 } win[2]; 3065 struct pccbb_win_chain *chainp; 3066 int offs; 3067 3068 win[0].win_start = win[1].win_start = 0xffffffff; 3069 win[0].win_limit = win[1].win_limit = 0; 3070 win[0].win_flags = win[1].win_flags = 0; 3071 3072 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3073 offs = PCI_CB_IOBASE0; 3074 if (sc->sc_memt == bst) { 3075 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3076 offs = PCI_CB_MEMBASE0; 3077 } 3078 3079 if (chainp != NULL) { 3080 win[0].win_start = chainp->wc_start & mask; 3081 win[0].win_limit = chainp->wc_end & mask; 3082 win[0].win_flags = chainp->wc_flags; 3083 chainp = TAILQ_NEXT(chainp, wc_list); 3084 } 3085 3086 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3087 if (win[1].win_start == 0xffffffff) { 3088 /* window 1 is not used */ 3089 if ((win[0].win_flags == chainp->wc_flags) && 3090 (win[0].win_limit + align >= 3091 (chainp->wc_start & mask))) { 3092 /* concatenate */ 3093 win[0].win_limit = chainp->wc_end & mask; 3094 } else { 3095 /* make new window */ 3096 win[1].win_start = chainp->wc_start & mask; 3097 win[1].win_limit = chainp->wc_end & mask; 3098 win[1].win_flags = chainp->wc_flags; 3099 } 3100 continue; 3101 } 3102 3103 /* Both windows are engaged. */ 3104 if (win[0].win_flags == win[1].win_flags) { 3105 /* same flags */ 3106 if (win[0].win_flags == chainp->wc_flags) { 3107 if (win[1].win_start - (win[0].win_limit + 3108 align) < 3109 (chainp->wc_start & mask) - 3110 ((chainp->wc_end & mask) + align)) { 3111 /* 3112 * merge window 0 and 1, and set win1 3113 * to chainp 3114 */ 3115 win[0].win_limit = win[1].win_limit; 3116 win[1].win_start = 3117 chainp->wc_start & mask; 3118 win[1].win_limit = 3119 chainp->wc_end & mask; 3120 } else { 3121 win[1].win_limit = 3122 chainp->wc_end & mask; 3123 } 3124 } else { 3125 /* different flags */ 3126 3127 /* concatenate win0 and win1 */ 3128 win[0].win_limit = win[1].win_limit; 3129 /* allocate win[1] to new space */ 3130 win[1].win_start = chainp->wc_start & mask; 3131 win[1].win_limit = chainp->wc_end & mask; 3132 win[1].win_flags = chainp->wc_flags; 3133 } 3134 } else { 3135 /* the flags of win[0] and win[1] is different */ 3136 if (win[0].win_flags == chainp->wc_flags) { 3137 win[0].win_limit = chainp->wc_end & mask; 3138 /* 3139 * XXX this creates overlapping windows, so 3140 * what should the poor bridge do if one is 3141 * cachable, and the other is not? 3142 */ 3143 aprint_error_dev(sc->sc_dev, 3144 "overlapping windows\n"); 3145 } else { 3146 win[1].win_limit = chainp->wc_end & mask; 3147 } 3148 } 3149 } 3150 3151 pc = sc->sc_pc; 3152 tag = sc->sc_tag; 3153 pci_conf_write(pc, tag, offs, win[0].win_start); 3154 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3155 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3156 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3157 DPRINTF(("--pccbb_winset: win0 [0x%lx, 0x%lx), win1 [0x%lx, 0x%lx)\n", 3158 (unsigned long)pci_conf_read(pc, tag, offs), 3159 (unsigned long)pci_conf_read(pc, tag, offs + 4) + align, 3160 (unsigned long)pci_conf_read(pc, tag, offs + 8), 3161 (unsigned long)pci_conf_read(pc, tag, offs + 12) + align)); 3162 3163 if (bst == sc->sc_memt) { 3164 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BRIDGE_CONTROL_REG); 3165 3166 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 3167 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 3168 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3169 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 3170 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3171 pci_conf_write(pc, tag, PCI_BRIDGE_CONTROL_REG, bcr); 3172 } 3173 } 3174 3175 #endif /* rbus */ 3176 3177 static bool 3178 pccbb_suspend(device_t dv PMF_FN_ARGS) 3179 { 3180 struct pccbb_softc *sc = device_private(dv); 3181 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3182 bus_space_handle_t base_memh = sc->sc_base_memh; 3183 pcireg_t reg; 3184 3185 if (sc->sc_pil_intr_enable) 3186 (void)pccbbintr_function(sc); 3187 sc->sc_pil_intr_enable = 0; 3188 3189 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3190 /* Disable interrupts. */ 3191 reg &= ~(CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER); 3192 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3193 /* XXX joerg Disable power to the socket? */ 3194 3195 /* XXX flush PCI write */ 3196 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3197 3198 /* reset interrupt */ 3199 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, 3200 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT)); 3201 /* XXX flush PCI write */ 3202 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3203 3204 if (sc->sc_ih != NULL) { 3205 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 3206 sc->sc_ih = NULL; 3207 } 3208 3209 return true; 3210 } 3211 3212 static bool 3213 pccbb_resume(device_t dv PMF_FN_ARGS) 3214 { 3215 struct pccbb_softc *sc = device_private(dv); 3216 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3217 bus_space_handle_t base_memh = sc->sc_base_memh; 3218 pcireg_t reg; 3219 3220 pccbb_chipinit(sc); 3221 pccbb_intrinit(sc); 3222 /* setup memory and io space window for CB */ 3223 pccbb_winset(0x1000, sc, sc->sc_memt); 3224 pccbb_winset(0x04, sc, sc->sc_iot); 3225 3226 /* CSC Interrupt: Card detect interrupt on */ 3227 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3228 /* Card detect intr is turned on. */ 3229 reg |= CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; 3230 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3231 /* reset interrupt */ 3232 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3233 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3234 3235 /* 3236 * check for card insertion or removal during suspend period. 3237 * XXX: the code can't cope with card swap (remove then 3238 * insert). how can we detect such situation? 3239 */ 3240 (void)pccbbintr(sc); 3241 3242 sc->sc_pil_intr_enable = 1; 3243 3244 return true; 3245 } 3246
Indexes created Fri Sep 26 20:09:58 GMT 2025