pccbb.c revision 1.193.2.1
1 /* $NetBSD: pccbb.c,v 1.193.2.1 2010/04/30 14:43:39 uebayasi Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: pccbb.c,v 1.193.2.1 2010/04/30 14:43:39 uebayasi Exp $"); 30 31 /* 32 #define CBB_DEBUG 33 #define SHOW_REGS 34 */ 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/kernel.h> 39 #include <sys/errno.h> 40 #include <sys/ioctl.h> 41 #include <sys/reboot.h> /* for bootverbose */ 42 #include <sys/syslog.h> 43 #include <sys/device.h> 44 #include <sys/malloc.h> 45 #include <sys/proc.h> 46 47 #include <sys/intr.h> 48 #include <sys/bus.h> 49 50 #include <dev/pci/pcivar.h> 51 #include <dev/pci/pcireg.h> 52 #include <dev/pci/pcidevs.h> 53 54 #include <dev/pci/pccbbreg.h> 55 56 #include <dev/cardbus/cardslotvar.h> 57 58 #include <dev/cardbus/cardbusvar.h> 59 60 #include <dev/pcmcia/pcmciareg.h> 61 #include <dev/pcmcia/pcmciavar.h> 62 63 #include <dev/ic/i82365reg.h> 64 #include <dev/pci/pccbbvar.h> 65 66 #ifndef __NetBSD_Version__ 67 struct cfdriver cbb_cd = { 68 NULL, "cbb", DV_DULL 69 }; 70 #endif 71 72 #ifdef CBB_DEBUG 73 #define DPRINTF(x) printf x 74 #define STATIC 75 #else 76 #define DPRINTF(x) 77 #define STATIC static 78 #endif 79 80 int pccbb_burstup = 1; 81 82 /* 83 * delay_ms() is wait in milliseconds. It should be used instead 84 * of delay() if you want to wait more than 1 ms. 85 */ 86 static inline void 87 delay_ms(int millis, struct pccbb_softc *sc) 88 { 89 if (cold) 90 delay(millis * 1000); 91 else 92 kpause("pccbb", false, mstohz(millis), NULL); 93 } 94 95 int pcicbbmatch(device_t, cfdata_t, void *); 96 void pccbbattach(device_t, device_t, void *); 97 void pccbbchilddet(device_t, device_t); 98 int pccbbdetach(device_t, int); 99 int pccbbintr(void *); 100 static void pci113x_insert(void *); 101 static int pccbbintr_function(struct pccbb_softc *); 102 103 static int pccbb_detect_card(struct pccbb_softc *); 104 105 static void pccbb_pcmcia_write(struct pccbb_softc *, int, u_int8_t); 106 static u_int8_t pccbb_pcmcia_read(struct pccbb_softc *, int); 107 #define Pcic_read(sc, reg) pccbb_pcmcia_read((sc), (reg)) 108 #define Pcic_write(sc, reg, val) pccbb_pcmcia_write((sc), (reg), (val)) 109 110 STATIC int cb_reset(struct pccbb_softc *); 111 STATIC int cb_detect_voltage(struct pccbb_softc *); 112 STATIC int cbbprint(void *, const char *); 113 114 static int cb_chipset(u_int32_t, int *); 115 STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *, 116 struct pcmciabus_attach_args *); 117 118 STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int); 119 STATIC int pccbb_power(struct pccbb_softc *sc, int); 120 STATIC int pccbb_power_ct(cardbus_chipset_tag_t, int); 121 STATIC int pccbb_cardenable(struct pccbb_softc * sc, int function); 122 static void *pccbb_intr_establish(struct pccbb_softc *, 123 cardbus_intr_line_t irq, int level, int (*ih) (void *), void *sc); 124 static void pccbb_intr_disestablish(struct pccbb_softc *, void *ih); 125 126 static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t, 127 cardbus_intr_line_t irq, int level, int (*ih) (void *), void *sc); 128 static void pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih); 129 130 static pcitag_t pccbb_make_tag(cardbus_chipset_tag_t, int, int); 131 static pcireg_t pccbb_conf_read(cardbus_chipset_tag_t, pcitag_t, int); 132 static void pccbb_conf_write(cardbus_chipset_tag_t, pcitag_t, int, 133 pcireg_t); 134 static void pccbb_chipinit(struct pccbb_softc *); 135 static void pccbb_intrinit(struct pccbb_softc *); 136 137 STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 138 struct pcmcia_mem_handle *); 139 STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t, 140 struct pcmcia_mem_handle *); 141 STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 142 bus_size_t, struct pcmcia_mem_handle *, bus_size_t *, int *); 143 STATIC void pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t, int); 144 STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 145 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 146 STATIC void pccbb_pcmcia_io_free(pcmcia_chipset_handle_t, 147 struct pcmcia_io_handle *); 148 STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 149 bus_size_t, struct pcmcia_io_handle *, int *); 150 STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t, int); 151 STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t, 152 struct pcmcia_function *, int, int (*)(void *), void *); 153 STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t, void *); 154 STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t); 155 STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t); 156 STATIC void pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t, int); 157 STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch); 158 159 static int pccbb_pcmcia_wait_ready(struct pccbb_softc *); 160 static void pccbb_pcmcia_delay(struct pccbb_softc *, int, const char *); 161 162 static void pccbb_pcmcia_do_io_map(struct pccbb_softc *, int); 163 static void pccbb_pcmcia_do_mem_map(struct pccbb_softc *, int); 164 165 /* bus-space allocation and deallocation functions */ 166 167 static int pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t, rbus_tag_t, 168 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 169 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp); 170 static int pccbb_rbus_cb_space_free(cardbus_chipset_tag_t, rbus_tag_t, 171 bus_space_handle_t, bus_size_t); 172 173 174 175 static int pccbb_open_win(struct pccbb_softc *, bus_space_tag_t, 176 bus_addr_t, bus_size_t, bus_space_handle_t, int flags); 177 static int pccbb_close_win(struct pccbb_softc *, bus_space_tag_t, 178 bus_space_handle_t, bus_size_t); 179 static int pccbb_winlist_insert(struct pccbb_win_chain_head *, bus_addr_t, 180 bus_size_t, bus_space_handle_t, int); 181 static int pccbb_winlist_delete(struct pccbb_win_chain_head *, 182 bus_space_handle_t, bus_size_t); 183 static void pccbb_winset(bus_addr_t align, struct pccbb_softc *, 184 bus_space_tag_t); 185 void pccbb_winlist_show(struct pccbb_win_chain *); 186 187 188 /* for config_defer */ 189 static void pccbb_pci_callback(device_t); 190 191 static bool pccbb_suspend(device_t, const pmf_qual_t *); 192 static bool pccbb_resume(device_t, const pmf_qual_t *); 193 194 #if defined SHOW_REGS 195 static void cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, 196 bus_space_tag_t memt, bus_space_handle_t memh); 197 #endif 198 199 CFATTACH_DECL3_NEW(cbb_pci, sizeof(struct pccbb_softc), 200 pcicbbmatch, pccbbattach, pccbbdetach, NULL, NULL, pccbbchilddet, 201 DVF_DETACH_SHUTDOWN); 202 203 static const struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 204 pccbb_pcmcia_mem_alloc, 205 pccbb_pcmcia_mem_free, 206 pccbb_pcmcia_mem_map, 207 pccbb_pcmcia_mem_unmap, 208 pccbb_pcmcia_io_alloc, 209 pccbb_pcmcia_io_free, 210 pccbb_pcmcia_io_map, 211 pccbb_pcmcia_io_unmap, 212 pccbb_pcmcia_intr_establish, 213 pccbb_pcmcia_intr_disestablish, 214 pccbb_pcmcia_socket_enable, 215 pccbb_pcmcia_socket_disable, 216 pccbb_pcmcia_socket_settype, 217 pccbb_pcmcia_card_detect 218 }; 219 220 static const struct cardbus_functions pccbb_funcs = { 221 pccbb_rbus_cb_space_alloc, 222 pccbb_rbus_cb_space_free, 223 pccbb_cb_intr_establish, 224 pccbb_cb_intr_disestablish, 225 pccbb_ctrl, 226 pccbb_power_ct, 227 pccbb_make_tag, 228 pccbb_conf_read, 229 pccbb_conf_write, 230 }; 231 232 int 233 pcicbbmatch(device_t parent, cfdata_t match, void *aux) 234 { 235 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 236 237 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 238 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 239 PCI_INTERFACE(pa->pa_class) == 0) { 240 return 1; 241 } 242 243 return 0; 244 } 245 246 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 247 | ((prod) << PCI_PRODUCT_SHIFT)) 248 249 const struct yenta_chipinfo { 250 pcireg_t yc_id; /* vendor tag | product tag */ 251 int yc_chiptype; 252 int yc_flags; 253 } yc_chipsets[] = { 254 /* Texas Instruments chips */ 255 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 256 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 257 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 258 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 259 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI125X, 260 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 261 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 262 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 263 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 264 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 265 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 266 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 267 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI125X, 268 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 269 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI125X, 270 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 271 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 272 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 273 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 274 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 275 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI1420, 276 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 277 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI125X, 278 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 279 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 280 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 281 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1520), CB_TI12XX, 282 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 283 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4410YENTA), CB_TI12XX, 284 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 285 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4520YENTA), CB_TI12XX, 286 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 287 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI7420YENTA), CB_TI12XX, 288 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 289 290 /* Ricoh chips */ 291 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 292 PCCBB_PCMCIA_MEM_32}, 293 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 294 PCCBB_PCMCIA_MEM_32}, 295 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 296 PCCBB_PCMCIA_MEM_32}, 297 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 298 PCCBB_PCMCIA_MEM_32}, 299 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 300 PCCBB_PCMCIA_MEM_32}, 301 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 302 PCCBB_PCMCIA_MEM_32}, 303 304 /* Toshiba products */ 305 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 306 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 307 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 308 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 309 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 310 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 311 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 312 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 313 314 /* Cirrus Logic products */ 315 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 316 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 317 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 318 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 319 320 /* O2 Micro products */ 321 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6729), 322 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 323 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6730), 324 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 325 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6832), 326 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 327 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6836), 328 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 329 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6872), 330 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 331 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6922), 332 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 333 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6933), 334 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 335 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6972), 336 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 337 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_7223), 338 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 339 340 /* sentinel, or Generic chip */ 341 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 342 }; 343 344 static int 345 cb_chipset(u_int32_t pci_id, int *flagp) 346 { 347 const struct yenta_chipinfo *yc; 348 349 /* Loop over except the last default entry. */ 350 for (yc = yc_chipsets; yc < yc_chipsets + 351 __arraycount(yc_chipsets) - 1; yc++) 352 if (pci_id == yc->yc_id) 353 break; 354 355 if (flagp != NULL) 356 *flagp = yc->yc_flags; 357 358 return (yc->yc_chiptype); 359 } 360 361 void 362 pccbbchilddet(device_t self, device_t child) 363 { 364 struct pccbb_softc *sc = device_private(self); 365 int s; 366 367 KASSERT(sc->sc_csc == device_private(child)); 368 369 s = splbio(); 370 if (sc->sc_csc == device_private(child)) 371 sc->sc_csc = NULL; 372 splx(s); 373 } 374 375 void 376 pccbbattach(device_t parent, device_t self, void *aux) 377 { 378 struct pccbb_softc *sc = device_private(self); 379 struct pci_attach_args *pa = aux; 380 pci_chipset_tag_t pc = pa->pa_pc; 381 pcireg_t busreg, reg, sock_base; 382 bus_addr_t sockbase; 383 char devinfo[256]; 384 int flags; 385 386 #ifdef __HAVE_PCCBB_ATTACH_HOOK 387 pccbb_attach_hook(parent, self, pa); 388 #endif 389 390 sc->sc_dev = self; 391 392 mutex_init(&sc->sc_pwr_mtx, MUTEX_DEFAULT, IPL_BIO); 393 cv_init(&sc->sc_pwr_cv, "pccpwr"); 394 395 callout_init(&sc->sc_insert_ch, 0); 396 callout_setfunc(&sc->sc_insert_ch, pci113x_insert, sc); 397 398 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 399 400 aprint_naive("\n"); 401 402 pci_devinfo(pa->pa_id, 0, 0, devinfo, sizeof(devinfo)); 403 aprint_normal(": %s (rev. 0x%02x)", devinfo, 404 PCI_REVISION(pa->pa_class)); 405 DPRINTF((" (chipflags %x)", flags)); 406 aprint_normal("\n"); 407 408 TAILQ_INIT(&sc->sc_memwindow); 409 TAILQ_INIT(&sc->sc_iowindow); 410 411 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 412 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 413 414 #if 0 415 printf("pa->pa_memt: %08x vs rbus_mem->rb_bt: %08x\n", 416 pa->pa_memt, sc->sc_rbus_memt->rb_bt); 417 #endif 418 419 sc->sc_flags &= ~CBB_MEMHMAPPED; 420 421 /* 422 * MAP socket registers and ExCA registers on memory-space 423 * When no valid address is set on socket base registers (on pci 424 * config space), get it not polite way. 425 */ 426 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 427 428 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 429 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 430 /* The address must be valid. */ 431 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 432 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, &sc->sc_base_size)) { 433 aprint_error_dev(self, 434 "can't map socket base address 0x%lx\n", 435 (unsigned long)sock_base); 436 /* 437 * I think it's funny: socket base registers must be 438 * mapped on memory space, but ... 439 */ 440 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 441 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 442 &sc->sc_base_size)) { 443 aprint_error_dev(self, 444 "can't map socket base address" 445 " 0x%lx: io mode\n", 446 (unsigned long)sockbase); 447 /* give up... allocate reg space via rbus. */ 448 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 449 } else 450 sc->sc_flags |= CBB_MEMHMAPPED; 451 } else { 452 DPRINTF(("%s: socket base address 0x%lx\n", 453 device_xname(self), 454 (unsigned long)sockbase)); 455 sc->sc_flags |= CBB_MEMHMAPPED; 456 } 457 } 458 459 sc->sc_mem_start = 0; /* XXX */ 460 sc->sc_mem_end = 0xffffffff; /* XXX */ 461 462 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 463 464 /* pccbb_machdep.c end */ 465 466 #if defined CBB_DEBUG 467 { 468 static const char *intrname[] = { "NON", "A", "B", "C", "D" }; 469 aprint_debug_dev(self, "intrpin %s, intrtag %d\n", 470 intrname[pa->pa_intrpin], pa->pa_intrline); 471 } 472 #endif 473 474 /* setup softc */ 475 sc->sc_pc = pc; 476 sc->sc_iot = pa->pa_iot; 477 sc->sc_memt = pa->pa_memt; 478 sc->sc_dmat = pa->pa_dmat; 479 sc->sc_tag = pa->pa_tag; 480 481 memcpy(&sc->sc_pa, pa, sizeof(*pa)); 482 483 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 484 485 /* Disable legacy register mapping. */ 486 switch (sc->sc_chipset) { 487 case CB_RX5C46X: /* fallthrough */ 488 #if 0 489 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 490 case CB_RX5C47X: 491 #endif 492 /* 493 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 494 * cannot be disabled by substituting 0 into PCI_LEGACY 495 * register. Ricoh CardBus bridges have special bits on Bridge 496 * control reg (addr 0x3e on PCI config space). 497 */ 498 reg = pci_conf_read(pc, pa->pa_tag, PCI_BRIDGE_CONTROL_REG); 499 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 500 pci_conf_write(pc, pa->pa_tag, PCI_BRIDGE_CONTROL_REG, reg); 501 break; 502 503 default: 504 /* XXX I don't know proper way to kill legacy I/O. */ 505 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 506 break; 507 } 508 509 if (!pmf_device_register(self, pccbb_suspend, pccbb_resume)) 510 aprint_error_dev(self, "couldn't establish power handler\n"); 511 512 config_defer(self, pccbb_pci_callback); 513 } 514 515 int 516 pccbbdetach(device_t self, int flags) 517 { 518 struct pccbb_softc *sc = device_private(self); 519 pci_chipset_tag_t pc = sc->sc_pa.pa_pc; 520 bus_space_tag_t bmt = sc->sc_base_memt; 521 bus_space_handle_t bmh = sc->sc_base_memh; 522 uint32_t sockmask; 523 int rc; 524 525 if ((rc = config_detach_children(self, flags)) != 0) 526 return rc; 527 528 if (!LIST_EMPTY(&sc->sc_pil)) { 529 panic("%s: interrupt handlers still registered", 530 device_xname(self)); 531 return EBUSY; 532 } 533 534 if (sc->sc_ih != NULL) { 535 pci_intr_disestablish(pc, sc->sc_ih); 536 sc->sc_ih = NULL; 537 } 538 539 /* CSC Interrupt: turn off card detect and power cycle interrupts */ 540 sockmask = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 541 sockmask &= ~(CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | 542 CB_SOCKET_MASK_POWER); 543 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, sockmask); 544 /* reset interrupt */ 545 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 546 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 547 548 switch (sc->sc_flags & (CBB_MEMHMAPPED|CBB_SPECMAPPED)) { 549 case CBB_MEMHMAPPED: 550 bus_space_unmap(bmt, bmh, sc->sc_base_size); 551 break; 552 case CBB_MEMHMAPPED|CBB_SPECMAPPED: 553 #if rbus 554 { 555 pcireg_t sockbase; 556 557 sockbase = pci_conf_read(pc, sc->sc_tag, PCI_SOCKBASE); 558 rbus_space_free(sc->sc_rbus_memt, bmh, 0x1000, 559 NULL); 560 } 561 #else 562 bus_space_free(bmt, bmh, 0x1000); 563 #endif 564 } 565 sc->sc_flags &= ~(CBB_MEMHMAPPED|CBB_SPECMAPPED); 566 567 if (!TAILQ_EMPTY(&sc->sc_iowindow)) 568 aprint_error_dev(self, "i/o windows not empty"); 569 if (!TAILQ_EMPTY(&sc->sc_memwindow)) 570 aprint_error_dev(self, "memory windows not empty"); 571 572 callout_stop(&sc->sc_insert_ch); 573 callout_destroy(&sc->sc_insert_ch); 574 575 mutex_destroy(&sc->sc_pwr_mtx); 576 cv_destroy(&sc->sc_pwr_cv); 577 578 return 0; 579 } 580 581 /* 582 * static void pccbb_pci_callback(device_t self) 583 * 584 * The actual attach routine: get memory space for YENTA register 585 * space, setup YENTA register and route interrupt. 586 * 587 * This function should be deferred because this device may obtain 588 * memory space dynamically. This function must avoid obtaining 589 * memory area which has already kept for another device. 590 */ 591 static void 592 pccbb_pci_callback(device_t self) 593 { 594 struct pccbb_softc *sc = device_private(self); 595 pci_chipset_tag_t pc = sc->sc_pc; 596 bus_addr_t sockbase; 597 struct cbslot_attach_args cba; 598 struct pcmciabus_attach_args paa; 599 struct cardslot_attach_args caa; 600 device_t csc; 601 602 if (!(sc->sc_flags & CBB_MEMHMAPPED)) { 603 /* The socket registers aren't mapped correctly. */ 604 #if rbus 605 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 606 (sc->sc_chipset == CB_RX5C47X 607 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 608 0, &sockbase, &sc->sc_base_memh)) { 609 return; 610 } 611 sc->sc_base_memt = sc->sc_memt; 612 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 613 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 614 device_xname(self), (unsigned long)sockbase, 615 (unsigned long)pci_conf_read(pc, sc->sc_tag, 616 PCI_SOCKBASE))); 617 #else 618 sc->sc_base_memt = sc->sc_memt; 619 #if !defined CBB_PCI_BASE 620 #define CBB_PCI_BASE 0x20000000 621 #endif 622 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 623 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 624 /* cannot allocate memory space */ 625 return; 626 } 627 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 628 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 629 device_xname(self), (unsigned long)sock_base, 630 (unsigned long)pci_conf_read(pc, 631 sc->sc_tag, PCI_SOCKBASE))); 632 #endif 633 sc->sc_flags |= CBB_MEMHMAPPED|CBB_SPECMAPPED; 634 } 635 636 /* clear data structure for child device interrupt handlers */ 637 LIST_INIT(&sc->sc_pil); 638 639 /* bus bridge initialization */ 640 pccbb_chipinit(sc); 641 642 sc->sc_pil_intr_enable = true; 643 644 { 645 u_int32_t sockstat; 646 647 sockstat = bus_space_read_4(sc->sc_base_memt, 648 sc->sc_base_memh, CB_SOCKET_STAT); 649 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 650 sc->sc_flags |= CBB_CARDEXIST; 651 } 652 } 653 654 /* 655 * attach cardbus 656 */ 657 { 658 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 659 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 660 661 /* initialize cbslot_attach */ 662 cba.cba_iot = sc->sc_iot; 663 cba.cba_memt = sc->sc_memt; 664 cba.cba_dmat = sc->sc_dmat; 665 cba.cba_bus = (busreg >> 8) & 0x0ff; 666 cba.cba_cc = (void *)sc; 667 cba.cba_cf = &pccbb_funcs; 668 cba.cba_intrline = 0; /* XXX dummy */ 669 670 #if rbus 671 cba.cba_rbus_iot = sc->sc_rbus_iot; 672 cba.cba_rbus_memt = sc->sc_rbus_memt; 673 #endif 674 675 cba.cba_cacheline = PCI_CACHELINE(bhlc); 676 cba.cba_max_lattimer = PCI_LATTIMER(bhlc); 677 678 aprint_verbose_dev(self, 679 "cacheline 0x%x lattimer 0x%x\n", 680 cba.cba_cacheline, 681 cba.cba_max_lattimer); 682 aprint_verbose_dev(self, "bhlc 0x%x\n", bhlc); 683 #if defined SHOW_REGS 684 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 685 sc->sc_base_memh); 686 #endif 687 } 688 689 pccbb_pcmcia_attach_setup(sc, &paa); 690 caa.caa_cb_attach = NULL; 691 if (cba.cba_bus == 0) 692 aprint_error_dev(self, 693 "secondary bus number uninitialized; try PCI_BUS_FIXUP\n"); 694 else 695 caa.caa_cb_attach = &cba; 696 caa.caa_16_attach = &paa; 697 698 pccbb_intrinit(sc); 699 700 if (NULL != (csc = config_found_ia(self, "pcmciaslot", &caa, 701 cbbprint))) { 702 DPRINTF(("%s: found cardslot\n", __func__)); 703 sc->sc_csc = device_private(csc); 704 } 705 706 return; 707 } 708 709 710 711 712 713 /* 714 * static void pccbb_chipinit(struct pccbb_softc *sc) 715 * 716 * This function initialize YENTA chip registers listed below: 717 * 1) PCI command reg, 718 * 2) PCI and CardBus latency timer, 719 * 3) route PCI interrupt, 720 * 4) close all memory and io windows. 721 * 5) turn off bus power. 722 * 6) card detect and power cycle interrupts on. 723 * 7) clear interrupt 724 */ 725 static void 726 pccbb_chipinit(struct pccbb_softc *sc) 727 { 728 pci_chipset_tag_t pc = sc->sc_pc; 729 pcitag_t tag = sc->sc_tag; 730 bus_space_tag_t bmt = sc->sc_base_memt; 731 bus_space_handle_t bmh = sc->sc_base_memh; 732 pcireg_t bcr, bhlc, cbctl, csr, lscp, mfunc, mrburst, slotctl, sockctl, 733 sysctrl; 734 735 /* 736 * Set PCI command reg. 737 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 738 */ 739 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 740 /* I believe it is harmless. */ 741 csr |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 742 PCI_COMMAND_MASTER_ENABLE); 743 744 /* All O2 Micro chips have broken parity-error reporting 745 * until proven otherwise. The OZ6933 PCI-CardBus Bridge 746 * is known to have the defect---see PR kern/38698. 747 */ 748 if (sc->sc_chipset != CB_O2MICRO) 749 csr |= PCI_COMMAND_PARITY_ENABLE; 750 751 csr |= PCI_COMMAND_SERR_ENABLE; 752 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 753 754 /* 755 * Set CardBus latency timer. 756 */ 757 lscp = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 758 if (PCI_CB_LATENCY(lscp) < 0x20) { 759 lscp &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 760 lscp |= (0x20 << PCI_CB_LATENCY_SHIFT); 761 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, lscp); 762 } 763 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 764 PCI_CB_LATENCY(lscp), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 765 766 /* 767 * Set PCI latency timer. 768 */ 769 bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG); 770 if (PCI_LATTIMER(bhlc) < 0x10) { 771 bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 772 bhlc |= (0x10 << PCI_LATTIMER_SHIFT); 773 pci_conf_write(pc, tag, PCI_BHLC_REG, bhlc); 774 } 775 DPRINTF(("PCI latency timer 0x%x (%x)\n", 776 PCI_LATTIMER(bhlc), pci_conf_read(pc, tag, PCI_BHLC_REG))); 777 778 779 /* Route functional interrupts to PCI. */ 780 bcr = pci_conf_read(pc, tag, PCI_BRIDGE_CONTROL_REG); 781 bcr |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 782 bcr |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 783 /* assert reset */ 784 bcr |= PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT; 785 /* Set master abort mode to 1, forward SERR# from secondary 786 * to primary, and detect parity errors on secondary. 787 */ 788 bcr |= PCI_BRIDGE_CONTROL_MABRT << PCI_BRIDGE_CONTROL_SHIFT; 789 bcr |= PCI_BRIDGE_CONTROL_SERR << PCI_BRIDGE_CONTROL_SHIFT; 790 bcr |= PCI_BRIDGE_CONTROL_PERE << PCI_BRIDGE_CONTROL_SHIFT; 791 pci_conf_write(pc, tag, PCI_BRIDGE_CONTROL_REG, bcr); 792 793 switch (sc->sc_chipset) { 794 case CB_TI113X: 795 cbctl = pci_conf_read(pc, tag, PCI_CBCTRL); 796 /* This bit is shared, but may read as 0 on some chips, so set 797 it explicitly on both functions. */ 798 cbctl |= PCI113X_CBCTRL_PCI_IRQ_ENA; 799 /* CSC intr enable */ 800 cbctl |= PCI113X_CBCTRL_PCI_CSC; 801 /* functional intr prohibit | prohibit ISA routing */ 802 cbctl &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 803 pci_conf_write(pc, tag, PCI_CBCTRL, cbctl); 804 break; 805 806 case CB_TI1420: 807 sysctrl = pci_conf_read(pc, tag, PCI_SYSCTRL); 808 mrburst = pccbb_burstup 809 ? PCI1420_SYSCTRL_MRBURST : PCI1420_SYSCTRL_MRBURSTDN; 810 if ((sysctrl & PCI1420_SYSCTRL_MRBURST) == mrburst) { 811 printf("%s: %swrite bursts enabled\n", 812 device_xname(sc->sc_dev), 813 pccbb_burstup ? "read/" : ""); 814 } else if (pccbb_burstup) { 815 printf("%s: enabling read/write bursts\n", 816 device_xname(sc->sc_dev)); 817 sysctrl |= PCI1420_SYSCTRL_MRBURST; 818 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 819 } else { 820 printf("%s: disabling read bursts, " 821 "enabling write bursts\n", 822 device_xname(sc->sc_dev)); 823 sysctrl |= PCI1420_SYSCTRL_MRBURSTDN; 824 sysctrl &= ~PCI1420_SYSCTRL_MRBURSTUP; 825 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 826 } 827 /*FALLTHROUGH*/ 828 case CB_TI12XX: 829 /* 830 * Some TI 12xx (and [14][45]xx) based pci cards 831 * sometimes have issues with the MFUNC register not 832 * being initialized due to a bad EEPROM on board. 833 * Laptops that this matters on have this register 834 * properly initialized. 835 * 836 * The TI125X parts have a different register. 837 */ 838 mfunc = pci_conf_read(pc, tag, PCI12XX_MFUNC); 839 if (mfunc == 0) { 840 mfunc &= ~PCI12XX_MFUNC_PIN0; 841 mfunc |= PCI12XX_MFUNC_PIN0_INTA; 842 if ((pci_conf_read(pc, tag, PCI_SYSCTRL) & 843 PCI12XX_SYSCTRL_INTRTIE) == 0) { 844 mfunc &= ~PCI12XX_MFUNC_PIN1; 845 mfunc |= PCI12XX_MFUNC_PIN1_INTB; 846 } 847 pci_conf_write(pc, tag, PCI12XX_MFUNC, mfunc); 848 } 849 /* fallthrough */ 850 851 case CB_TI125X: 852 /* 853 * Disable zoom video. Some machines initialize this 854 * improperly and experience has shown that this helps 855 * prevent strange behavior. 856 */ 857 pci_conf_write(pc, tag, PCI12XX_MMCTRL, 0); 858 859 sysctrl = pci_conf_read(pc, tag, PCI_SYSCTRL); 860 sysctrl |= PCI12XX_SYSCTRL_VCCPROT; 861 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 862 cbctl = pci_conf_read(pc, tag, PCI_CBCTRL); 863 cbctl |= PCI12XX_CBCTRL_CSC; 864 pci_conf_write(pc, tag, PCI_CBCTRL, cbctl); 865 break; 866 867 case CB_TOPIC95B: 868 sockctl = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 869 sockctl |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 870 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, sockctl); 871 slotctl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 872 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 873 device_xname(sc->sc_dev), slotctl)); 874 slotctl |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 875 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 876 slotctl &= ~TOPIC_SLOT_CTRL_SWDETECT; 877 DPRINTF(("0x%x\n", slotctl)); 878 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slotctl); 879 break; 880 881 case CB_TOPIC97: 882 slotctl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 883 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 884 device_xname(sc->sc_dev), slotctl)); 885 slotctl |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 886 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 887 slotctl &= ~TOPIC_SLOT_CTRL_SWDETECT; 888 slotctl |= TOPIC97_SLOT_CTRL_PCIINT; 889 slotctl &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 890 DPRINTF(("0x%x\n", slotctl)); 891 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slotctl); 892 /* make sure to assert LV card support bits */ 893 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 894 0x800 + 0x3e, 895 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 896 0x800 + 0x3e) | 0x03); 897 break; 898 } 899 900 /* Close all memory and I/O windows. */ 901 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 902 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 903 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 904 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 905 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 906 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 907 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 908 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 909 910 /* reset 16-bit pcmcia bus */ 911 bus_space_write_1(bmt, bmh, 0x800 + PCIC_INTR, 912 bus_space_read_1(bmt, bmh, 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 913 914 /* turn off power */ 915 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 916 } 917 918 static void 919 pccbb_intrinit(struct pccbb_softc *sc) 920 { 921 pcireg_t sockmask; 922 const char *intrstr = NULL; 923 pci_intr_handle_t ih; 924 pci_chipset_tag_t pc = sc->sc_pc; 925 bus_space_tag_t bmt = sc->sc_base_memt; 926 bus_space_handle_t bmh = sc->sc_base_memh; 927 928 /* Map and establish the interrupt. */ 929 if (pci_intr_map(&sc->sc_pa, &ih)) { 930 aprint_error_dev(sc->sc_dev, "couldn't map interrupt\n"); 931 return; 932 } 933 intrstr = pci_intr_string(pc, ih); 934 935 /* 936 * XXX pccbbintr should be called under the priority lower 937 * than any other hard interrupts. 938 */ 939 KASSERT(sc->sc_ih == NULL); 940 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 941 942 if (sc->sc_ih == NULL) { 943 aprint_error_dev(sc->sc_dev, "couldn't establish interrupt"); 944 if (intrstr != NULL) 945 aprint_error(" at %s\n", intrstr); 946 else 947 aprint_error("\n"); 948 return; 949 } 950 951 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 952 953 /* CSC Interrupt: Card detect and power cycle interrupts on */ 954 sockmask = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 955 sockmask |= CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | 956 CB_SOCKET_MASK_POWER; 957 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, sockmask); 958 /* reset interrupt */ 959 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 960 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 961 } 962 963 /* 964 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 965 * struct pcmciabus_attach_args *paa) 966 * 967 * This function attaches 16-bit PCcard bus. 968 */ 969 STATIC void 970 pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 971 struct pcmciabus_attach_args *paa) 972 { 973 #if rbus 974 rbus_tag_t rb; 975 #endif 976 /* 977 * We need to do a few things here: 978 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 979 * setting the IRQ numbers to 0. 980 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 981 * routing of CSC interrupts (e.g. card removal) to PCI while in 982 * PCMCIA mode. We just leave this set all the time. 983 * 3) Enable card insertion/removal interrupts in case the chip also 984 * needs that while in PCMCIA mode. 985 * 4) Clear any pending CSC interrupt. 986 */ 987 Pcic_write(sc, PCIC_INTR, PCIC_INTR_ENABLE); 988 if (sc->sc_chipset == CB_TI113X) { 989 Pcic_write(sc, PCIC_CSC_INTR, 0); 990 } else { 991 Pcic_write(sc, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 992 Pcic_read(sc, PCIC_CSC); 993 } 994 995 /* initialize pcmcia bus attachment */ 996 paa->paa_busname = "pcmcia"; 997 paa->pct = &pccbb_pcmcia_funcs; 998 paa->pch = sc; 999 paa->iobase = 0; /* I don't use them */ 1000 paa->iosize = 0; 1001 #if rbus 1002 rb = sc->sc_rbus_iot; 1003 paa->iobase = rb->rb_start + rb->rb_offset; 1004 paa->iosize = rb->rb_end - rb->rb_start; 1005 #endif 1006 1007 return; 1008 } 1009 1010 /* 1011 * int pccbbintr(arg) 1012 * void *arg; 1013 * This routine handles the interrupt from Yenta PCI-CardBus bridge 1014 * itself. 1015 */ 1016 int 1017 pccbbintr(void *arg) 1018 { 1019 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1020 struct cardslot_softc *csc; 1021 u_int32_t sockevent, sockstate; 1022 bus_space_tag_t memt = sc->sc_base_memt; 1023 bus_space_handle_t memh = sc->sc_base_memh; 1024 1025 if (!device_has_power(sc->sc_dev)) 1026 return 0; 1027 1028 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 1029 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 1030 Pcic_read(sc, PCIC_CSC); 1031 1032 if (sockevent != 0) { 1033 aprint_debug("%s: enter sockevent %" PRIx32 "\n", __func__, 1034 sockevent); 1035 } 1036 1037 /* XXX sockevent == CB_SOCKET_EVENT_CSTS|CB_SOCKET_EVENT_POWER 1038 * does occur in the wild. Check for a _POWER event before 1039 * possibly exiting because of an _CSTS event. 1040 */ 1041 if (sockevent & CB_SOCKET_EVENT_POWER) { 1042 DPRINTF(("Powercycling because of socket event\n")); 1043 /* XXX: Does not happen when attaching a 16-bit card */ 1044 mutex_enter(&sc->sc_pwr_mtx); 1045 sc->sc_pwrcycle++; 1046 cv_signal(&sc->sc_pwr_cv); 1047 mutex_exit(&sc->sc_pwr_mtx); 1048 } 1049 1050 /* Sometimes a change of CSTSCHG# accompanies the first 1051 * interrupt from an Atheros WLAN. That generates a 1052 * CB_SOCKET_EVENT_CSTS event on the bridge. The event 1053 * isn't interesting to pccbb(4), so we used to ignore the 1054 * interrupt. Now, let the child devices try to handle 1055 * the interrupt, instead. The Atheros NIC produces 1056 * interrupts more reliably, now: used to be that it would 1057 * only interrupt if the driver avoided powering down the 1058 * NIC's cardslot, and then the NIC would only work after 1059 * it was reset a second time. 1060 */ 1061 if (sockevent == 0 || 1062 (sockevent & ~(CB_SOCKET_EVENT_POWER|CB_SOCKET_EVENT_CD)) != 0) { 1063 /* This intr is not for me: it may be for my child devices. */ 1064 if (sc->sc_pil_intr_enable) { 1065 return pccbbintr_function(sc); 1066 } else { 1067 return 0; 1068 } 1069 } 1070 1071 if (sockevent & CB_SOCKET_EVENT_CD) { 1072 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1073 if (0x00 != (sockstate & CB_SOCKET_STAT_CD)) { 1074 /* A card should be removed. */ 1075 if (sc->sc_flags & CBB_CARDEXIST) { 1076 DPRINTF(("%s: 0x%08x", 1077 device_xname(sc->sc_dev), sockevent)); 1078 DPRINTF((" card removed, 0x%08x\n", sockstate)); 1079 sc->sc_flags &= ~CBB_CARDEXIST; 1080 if ((csc = sc->sc_csc) == NULL) 1081 ; 1082 else if (csc->sc_status & 1083 CARDSLOT_STATUS_CARD_16) { 1084 cardslot_event_throw(csc, 1085 CARDSLOT_EVENT_REMOVAL_16); 1086 } else if (csc->sc_status & 1087 CARDSLOT_STATUS_CARD_CB) { 1088 /* Cardbus intr removed */ 1089 cardslot_event_throw(csc, 1090 CARDSLOT_EVENT_REMOVAL_CB); 1091 } 1092 } else if (sc->sc_flags & CBB_INSERTING) { 1093 sc->sc_flags &= ~CBB_INSERTING; 1094 callout_stop(&sc->sc_insert_ch); 1095 } 1096 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 1097 /* 1098 * The pccbbintr may called from powerdown hook when 1099 * the system resumed, to detect the card 1100 * insertion/removal during suspension. 1101 */ 1102 (sc->sc_flags & CBB_CARDEXIST) == 0) { 1103 if (sc->sc_flags & CBB_INSERTING) { 1104 callout_stop(&sc->sc_insert_ch); 1105 } 1106 callout_schedule(&sc->sc_insert_ch, mstohz(200)); 1107 sc->sc_flags |= CBB_INSERTING; 1108 } 1109 } 1110 1111 return (1); 1112 } 1113 1114 /* 1115 * static int pccbbintr_function(struct pccbb_softc *sc) 1116 * 1117 * This function calls each interrupt handler registered at the 1118 * bridge. The interrupt handlers are called in registered order. 1119 */ 1120 static int 1121 pccbbintr_function(struct pccbb_softc *sc) 1122 { 1123 int retval = 0, val; 1124 struct pccbb_intrhand_list *pil; 1125 int s; 1126 1127 LIST_FOREACH(pil, &sc->sc_pil, pil_next) { 1128 s = splraiseipl(pil->pil_icookie); 1129 val = (*pil->pil_func)(pil->pil_arg); 1130 splx(s); 1131 1132 retval = retval == 1 ? 1 : 1133 retval == 0 ? val : val != 0 ? val : retval; 1134 } 1135 1136 return retval; 1137 } 1138 1139 static void 1140 pci113x_insert(void *arg) 1141 { 1142 struct pccbb_softc *sc = arg; 1143 struct cardslot_softc *csc; 1144 u_int32_t sockevent, sockstate; 1145 1146 if (!(sc->sc_flags & CBB_INSERTING)) { 1147 /* We add a card only under inserting state. */ 1148 return; 1149 } 1150 sc->sc_flags &= ~CBB_INSERTING; 1151 1152 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1153 CB_SOCKET_EVENT); 1154 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1155 CB_SOCKET_STAT); 1156 1157 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1158 DPRINTF(("%s: 0x%08x", device_xname(sc->sc_dev), sockevent)); 1159 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1160 sc->sc_flags |= CBB_CARDEXIST; 1161 /* call pccard interrupt handler here */ 1162 if ((csc = sc->sc_csc) == NULL) 1163 ; 1164 else if (sockstate & CB_SOCKET_STAT_16BIT) { 1165 /* 16-bit card found */ 1166 cardslot_event_throw(csc, CARDSLOT_EVENT_INSERTION_16); 1167 } else if (sockstate & CB_SOCKET_STAT_CB) { 1168 /* cardbus card found */ 1169 cardslot_event_throw(csc, CARDSLOT_EVENT_INSERTION_CB); 1170 } else { 1171 /* who are you? */ 1172 } 1173 } else { 1174 callout_schedule(&sc->sc_insert_ch, mstohz(100)); 1175 } 1176 } 1177 1178 #define PCCBB_PCMCIA_OFFSET 0x800 1179 static u_int8_t 1180 pccbb_pcmcia_read(struct pccbb_softc *sc, int reg) 1181 { 1182 bus_space_barrier(sc->sc_base_memt, sc->sc_base_memh, 1183 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1184 1185 return bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 1186 PCCBB_PCMCIA_OFFSET + reg); 1187 } 1188 1189 static void 1190 pccbb_pcmcia_write(struct pccbb_softc *sc, int reg, u_int8_t val) 1191 { 1192 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 1193 PCCBB_PCMCIA_OFFSET + reg, val); 1194 1195 bus_space_barrier(sc->sc_base_memt, sc->sc_base_memh, 1196 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1197 } 1198 1199 /* 1200 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1201 */ 1202 STATIC int 1203 pccbb_ctrl(cardbus_chipset_tag_t ct, int command) 1204 { 1205 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1206 1207 switch (command) { 1208 case CARDBUS_CD: 1209 if (2 == pccbb_detect_card(sc)) { 1210 int retval = 0; 1211 int status = cb_detect_voltage(sc); 1212 if (PCCARD_VCC_5V & status) { 1213 retval |= CARDBUS_5V_CARD; 1214 } 1215 if (PCCARD_VCC_3V & status) { 1216 retval |= CARDBUS_3V_CARD; 1217 } 1218 if (PCCARD_VCC_XV & status) { 1219 retval |= CARDBUS_XV_CARD; 1220 } 1221 if (PCCARD_VCC_YV & status) { 1222 retval |= CARDBUS_YV_CARD; 1223 } 1224 return retval; 1225 } else { 1226 return 0; 1227 } 1228 case CARDBUS_RESET: 1229 return cb_reset(sc); 1230 case CARDBUS_IO_ENABLE: /* fallthrough */ 1231 case CARDBUS_IO_DISABLE: /* fallthrough */ 1232 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1233 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1234 case CARDBUS_BM_ENABLE: /* fallthrough */ 1235 case CARDBUS_BM_DISABLE: /* fallthrough */ 1236 /* XXX: I think we don't need to call this function below. */ 1237 return pccbb_cardenable(sc, command); 1238 } 1239 1240 return 0; 1241 } 1242 1243 STATIC int 1244 pccbb_power_ct(cardbus_chipset_tag_t ct, int command) 1245 { 1246 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1247 1248 return pccbb_power(sc, command); 1249 } 1250 1251 /* 1252 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1253 * This function returns true when it succeeds and returns false when 1254 * it fails. 1255 */ 1256 STATIC int 1257 pccbb_power(struct pccbb_softc *sc, int command) 1258 { 1259 u_int32_t status, osock_ctrl, sock_ctrl, reg_ctrl; 1260 bus_space_tag_t memt = sc->sc_base_memt; 1261 bus_space_handle_t memh = sc->sc_base_memh; 1262 int on = 0, pwrcycle, times; 1263 struct timeval before, after, diff; 1264 1265 DPRINTF(("pccbb_power: %s and %s [0x%x]\n", 1266 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1267 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1268 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1269 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1270 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1271 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1272 "UNKNOWN", 1273 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1274 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1275 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1276 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1277 "UNKNOWN", command)); 1278 1279 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1280 osock_ctrl = sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1281 1282 switch (command & CARDBUS_VCCMASK) { 1283 case CARDBUS_VCC_UC: 1284 break; 1285 case CARDBUS_VCC_5V: 1286 on++; 1287 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1288 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1289 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1290 } else { 1291 aprint_error_dev(sc->sc_dev, 1292 "BAD voltage request: no 5 V card\n"); 1293 return 0; 1294 } 1295 break; 1296 case CARDBUS_VCC_3V: 1297 on++; 1298 if (CB_SOCKET_STAT_3VCARD & status) { 1299 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1300 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1301 } else { 1302 aprint_error_dev(sc->sc_dev, 1303 "BAD voltage request: no 3.3 V card\n"); 1304 return 0; 1305 } 1306 break; 1307 case CARDBUS_VCC_0V: 1308 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1309 break; 1310 default: 1311 return 0; /* power NEVER changed */ 1312 } 1313 1314 switch (command & CARDBUS_VPPMASK) { 1315 case CARDBUS_VPP_UC: 1316 break; 1317 case CARDBUS_VPP_0V: 1318 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1319 break; 1320 case CARDBUS_VPP_VCC: 1321 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1322 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1323 break; 1324 case CARDBUS_VPP_12V: 1325 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1326 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1327 break; 1328 } 1329 aprint_debug_dev(sc->sc_dev, "osock_ctrl %#" PRIx32 1330 " sock_ctrl %#" PRIx32 "\n", osock_ctrl, sock_ctrl); 1331 1332 microtime(&before); 1333 mutex_enter(&sc->sc_pwr_mtx); 1334 pwrcycle = sc->sc_pwrcycle; 1335 1336 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1337 1338 /* 1339 * Wait as long as 200ms for a power-cycle interrupt. If 1340 * interrupts are enabled, but the socket has already 1341 * changed to the desired status, keep waiting for the 1342 * interrupt. "Consuming" the interrupt in this way keeps 1343 * the interrupt from prematurely waking some subsequent 1344 * pccbb_power call. 1345 * 1346 * XXX Not every bridge interrupts on the ->OFF transition. 1347 * XXX That's ok, we will time-out after 200ms. 1348 * 1349 * XXX The power cycle event will never happen when attaching 1350 * XXX a 16-bit card. That's ok, we will time-out after 1351 * XXX 200ms. 1352 */ 1353 for (times = 5; --times >= 0; ) { 1354 if (cold) 1355 DELAY(40 * 1000); 1356 else { 1357 (void)cv_timedwait(&sc->sc_pwr_cv, &sc->sc_pwr_mtx, 1358 mstohz(40)); 1359 if (pwrcycle == sc->sc_pwrcycle) 1360 continue; 1361 } 1362 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1363 if ((status & CB_SOCKET_STAT_PWRCYCLE) != 0 && on) 1364 break; 1365 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0 && !on) 1366 break; 1367 } 1368 mutex_exit(&sc->sc_pwr_mtx); 1369 microtime(&after); 1370 timersub(&after, &before, &diff); 1371 aprint_debug_dev(sc->sc_dev, "wait took%s %lld.%06lds\n", 1372 (on && times < 0) ? " too long" : "", (long long)diff.tv_sec, 1373 (long)diff.tv_usec); 1374 1375 /* 1376 * Ok, wait a bit longer for things to settle. 1377 */ 1378 if (on && sc->sc_chipset == CB_TOPIC95B) 1379 delay_ms(100, sc); 1380 1381 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1382 1383 if (on && sc->sc_chipset != CB_TOPIC95B) { 1384 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0) 1385 aprint_error_dev(sc->sc_dev, "power on failed?\n"); 1386 } 1387 1388 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1389 aprint_error_dev(sc->sc_dev, 1390 "bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1391 sock_ctrl, status); 1392 aprint_error_dev(sc->sc_dev, "disabling socket\n"); 1393 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1394 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1395 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1396 status &= ~CB_SOCKET_STAT_BADVCC; 1397 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, status); 1398 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1399 CB_SOCKET_STAT)); 1400 return 0; 1401 } 1402 1403 if (sc->sc_chipset == CB_TOPIC97) { 1404 reg_ctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL); 1405 reg_ctrl &= ~TOPIC97_REG_CTRL_TESTMODE; 1406 if ((command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V) 1407 reg_ctrl &= ~TOPIC97_REG_CTRL_CLKRUN_ENA; 1408 else 1409 reg_ctrl |= TOPIC97_REG_CTRL_CLKRUN_ENA; 1410 pci_conf_write(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL, reg_ctrl); 1411 } 1412 1413 return 1; /* power changed correctly */ 1414 } 1415 1416 /* 1417 * static int pccbb_detect_card(struct pccbb_softc *sc) 1418 * return value: 0 if no card exists. 1419 * 1 if 16-bit card exists. 1420 * 2 if cardbus card exists. 1421 */ 1422 static int 1423 pccbb_detect_card(struct pccbb_softc *sc) 1424 { 1425 bus_space_handle_t base_memh = sc->sc_base_memh; 1426 bus_space_tag_t base_memt = sc->sc_base_memt; 1427 u_int32_t sockstat = 1428 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1429 int retval = 0; 1430 1431 /* CD1 and CD2 asserted */ 1432 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1433 /* card must be present */ 1434 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1435 /* NOTACARD DEASSERTED */ 1436 if (CB_SOCKET_STAT_CB & sockstat) { 1437 /* CardBus mode */ 1438 retval = 2; 1439 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1440 /* 16-bit mode */ 1441 retval = 1; 1442 } 1443 } 1444 } 1445 return retval; 1446 } 1447 1448 /* 1449 * STATIC int cb_reset(struct pccbb_softc *sc) 1450 * This function resets CardBus card. 1451 */ 1452 STATIC int 1453 cb_reset(struct pccbb_softc *sc) 1454 { 1455 /* 1456 * Reset Assert at least 20 ms 1457 * Some machines request longer duration. 1458 */ 1459 int reset_duration = 1460 (sc->sc_chipset == CB_RX5C47X ? 400 : 50); 1461 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1462 aprint_debug("%s: enter bcr %" PRIx32 "\n", __func__, bcr); 1463 1464 /* Reset bit Assert (bit 6 at 0x3E) */ 1465 bcr |= PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT; 1466 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr); 1467 aprint_debug("%s: wrote bcr %" PRIx32 "\n", __func__, bcr); 1468 delay_ms(reset_duration, sc); 1469 1470 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1471 /* Reset bit Deassert (bit 6 at 0x3E) */ 1472 bcr &= ~(PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT); 1473 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, 1474 bcr); 1475 aprint_debug("%s: wrote bcr %" PRIx32 "\n", __func__, bcr); 1476 delay_ms(reset_duration, sc); 1477 aprint_debug("%s: end of delay\n", __func__); 1478 } 1479 /* No card found on the slot. Keep Reset. */ 1480 return 1; 1481 } 1482 1483 /* 1484 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1485 * This function detect card Voltage. 1486 */ 1487 STATIC int 1488 cb_detect_voltage(struct pccbb_softc *sc) 1489 { 1490 u_int32_t psr; /* socket present-state reg */ 1491 bus_space_tag_t iot = sc->sc_base_memt; 1492 bus_space_handle_t ioh = sc->sc_base_memh; 1493 int vol = PCCARD_VCC_UKN; /* set 0 */ 1494 1495 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1496 1497 if (0x400u & psr) { 1498 vol |= PCCARD_VCC_5V; 1499 } 1500 if (0x800u & psr) { 1501 vol |= PCCARD_VCC_3V; 1502 } 1503 1504 return vol; 1505 } 1506 1507 STATIC int 1508 cbbprint(void *aux, const char *pcic) 1509 { 1510 #if 0 1511 struct cbslot_attach_args *cba = aux; 1512 1513 if (cba->cba_slot >= 0) { 1514 aprint_normal(" slot %d", cba->cba_slot); 1515 } 1516 #endif 1517 return UNCONF; 1518 } 1519 1520 /* 1521 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1522 * This function enables and disables the card 1523 */ 1524 STATIC int 1525 pccbb_cardenable(struct pccbb_softc *sc, int function) 1526 { 1527 u_int32_t command = 1528 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1529 1530 DPRINTF(("pccbb_cardenable:")); 1531 switch (function) { 1532 case CARDBUS_IO_ENABLE: 1533 command |= PCI_COMMAND_IO_ENABLE; 1534 break; 1535 case CARDBUS_IO_DISABLE: 1536 command &= ~PCI_COMMAND_IO_ENABLE; 1537 break; 1538 case CARDBUS_MEM_ENABLE: 1539 command |= PCI_COMMAND_MEM_ENABLE; 1540 break; 1541 case CARDBUS_MEM_DISABLE: 1542 command &= ~PCI_COMMAND_MEM_ENABLE; 1543 break; 1544 case CARDBUS_BM_ENABLE: 1545 command |= PCI_COMMAND_MASTER_ENABLE; 1546 break; 1547 case CARDBUS_BM_DISABLE: 1548 command &= ~PCI_COMMAND_MASTER_ENABLE; 1549 break; 1550 default: 1551 return 0; 1552 } 1553 1554 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1555 DPRINTF((" command reg 0x%x\n", command)); 1556 return 1; 1557 } 1558 1559 #if !rbus 1560 static int 1561 pccbb_io_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 1562 { 1563 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1564 int basereg; 1565 int limitreg; 1566 1567 if ((win < 0) || (win > 2)) { 1568 #if defined DIAGNOSTIC 1569 printf("cardbus_io_open: window out of range %d\n", win); 1570 #endif 1571 return 0; 1572 } 1573 1574 basereg = win * 8 + PCI_CB_IOBASE0; 1575 limitreg = win * 8 + PCI_CB_IOLIMIT0; 1576 1577 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1578 start, basereg, end, limitreg)); 1579 1580 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1581 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1582 return 1; 1583 } 1584 1585 /* 1586 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1587 */ 1588 static int 1589 pccbb_io_close(cardbus_chipset_tag_t ct, int win) 1590 { 1591 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1592 int basereg; 1593 int limitreg; 1594 1595 if ((win < 0) || (win > 2)) { 1596 #if defined DIAGNOSTIC 1597 printf("cardbus_io_close: window out of range %d\n", win); 1598 #endif 1599 return 0; 1600 } 1601 1602 basereg = win * 8 + PCI_CB_IOBASE0; 1603 limitreg = win * 8 + PCI_CB_IOLIMIT0; 1604 1605 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1606 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1607 return 1; 1608 } 1609 1610 static int 1611 pccbb_mem_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 1612 { 1613 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1614 int basereg; 1615 int limitreg; 1616 1617 if ((win < 0) || (win > 2)) { 1618 #if defined DIAGNOSTIC 1619 printf("cardbus_mem_open: window out of range %d\n", win); 1620 #endif 1621 return 0; 1622 } 1623 1624 basereg = win * 8 + PCI_CB_MEMBASE0; 1625 limitreg = win * 8 + PCI_CB_MEMLIMIT0; 1626 1627 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1628 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1629 return 1; 1630 } 1631 1632 static int 1633 pccbb_mem_close(cardbus_chipset_tag_t ct, int win) 1634 { 1635 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1636 int basereg; 1637 int limitreg; 1638 1639 if ((win < 0) || (win > 2)) { 1640 #if defined DIAGNOSTIC 1641 printf("cardbus_mem_close: window out of range %d\n", win); 1642 #endif 1643 return 0; 1644 } 1645 1646 basereg = win * 8 + PCI_CB_MEMBASE0; 1647 limitreg = win * 8 + PCI_CB_MEMLIMIT0; 1648 1649 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1650 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1651 return 1; 1652 } 1653 #endif 1654 1655 /* 1656 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1657 * int irq, 1658 * int level, 1659 * int (* func)(void *), 1660 * void *arg) 1661 * 1662 * This function registers an interrupt handler at the bridge, in 1663 * order not to call the interrupt handlers of child devices when 1664 * a card-deletion interrupt occurs. 1665 * 1666 * The arguments irq and level are not used. 1667 */ 1668 static void * 1669 pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, cardbus_intr_line_t irq, 1670 int level, int (*func)(void *), void *arg) 1671 { 1672 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1673 1674 return pccbb_intr_establish(sc, irq, level, func, arg); 1675 } 1676 1677 1678 /* 1679 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1680 * void *ih) 1681 * 1682 * This function removes an interrupt handler pointed by ih. 1683 */ 1684 static void 1685 pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih) 1686 { 1687 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1688 1689 pccbb_intr_disestablish(sc, ih); 1690 } 1691 1692 1693 void 1694 pccbb_intr_route(struct pccbb_softc *sc) 1695 { 1696 pcireg_t bcr, cbctrl; 1697 1698 /* initialize bridge intr routing */ 1699 bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1700 bcr &= ~CB_BCR_INTR_IREQ_ENABLE; 1701 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr); 1702 1703 switch (sc->sc_chipset) { 1704 case CB_TI113X: 1705 cbctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1706 /* functional intr enabled */ 1707 cbctrl |= PCI113X_CBCTRL_PCI_INTR; 1708 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, cbctrl); 1709 break; 1710 default: 1711 break; 1712 } 1713 } 1714 1715 /* 1716 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1717 * int irq, 1718 * int level, 1719 * int (* func)(void *), 1720 * void *arg) 1721 * 1722 * This function registers an interrupt handler at the bridge, in 1723 * order not to call the interrupt handlers of child devices when 1724 * a card-deletion interrupt occurs. 1725 * 1726 * The arguments irq is not used because pccbb selects intr vector. 1727 */ 1728 static void * 1729 pccbb_intr_establish(struct pccbb_softc *sc, cardbus_intr_line_t irq, 1730 int level, int (*func)(void *), void *arg) 1731 { 1732 struct pccbb_intrhand_list *pil, *newpil; 1733 1734 DPRINTF(("pccbb_intr_establish start. %p\n", LIST_FIRST(&sc->sc_pil))); 1735 1736 if (LIST_EMPTY(&sc->sc_pil)) { 1737 pccbb_intr_route(sc); 1738 } 1739 1740 /* 1741 * Allocate a room for interrupt handler structure. 1742 */ 1743 if (NULL == (newpil = 1744 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1745 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1746 return NULL; 1747 } 1748 1749 newpil->pil_func = func; 1750 newpil->pil_arg = arg; 1751 newpil->pil_icookie = makeiplcookie(level); 1752 1753 if (LIST_EMPTY(&sc->sc_pil)) { 1754 LIST_INSERT_HEAD(&sc->sc_pil, newpil, pil_next); 1755 } else { 1756 for (pil = LIST_FIRST(&sc->sc_pil); 1757 LIST_NEXT(pil, pil_next) != NULL; 1758 pil = LIST_NEXT(pil, pil_next)); 1759 LIST_INSERT_AFTER(pil, newpil, pil_next); 1760 } 1761 1762 DPRINTF(("pccbb_intr_establish add pil. %p\n", 1763 LIST_FIRST(&sc->sc_pil))); 1764 1765 return newpil; 1766 } 1767 1768 /* 1769 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1770 * void *ih) 1771 * 1772 * This function removes an interrupt handler pointed by ih. ih 1773 * should be the value returned by cardbus_intr_establish() or 1774 * NULL. 1775 * 1776 * When ih is NULL, this function will do nothing. 1777 */ 1778 static void 1779 pccbb_intr_disestablish(struct pccbb_softc *sc, void *ih) 1780 { 1781 struct pccbb_intrhand_list *pil; 1782 pcireg_t reg; 1783 1784 DPRINTF(("pccbb_intr_disestablish start. %p\n", 1785 LIST_FIRST(&sc->sc_pil))); 1786 1787 if (ih == NULL) { 1788 /* intr handler is not set */ 1789 DPRINTF(("pccbb_intr_disestablish: no ih\n")); 1790 return; 1791 } 1792 1793 #ifdef DIAGNOSTIC 1794 LIST_FOREACH(pil, &sc->sc_pil, pil_next) { 1795 DPRINTF(("pccbb_intr_disestablish: pil %p\n", pil)); 1796 if (pil == ih) { 1797 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1798 break; 1799 } 1800 } 1801 if (pil == NULL) { 1802 panic("pccbb_intr_disestablish: %s cannot find pil %p", 1803 device_xname(sc->sc_dev), ih); 1804 } 1805 #endif 1806 1807 pil = (struct pccbb_intrhand_list *)ih; 1808 LIST_REMOVE(pil, pil_next); 1809 free(pil, M_DEVBUF); 1810 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1811 1812 if (LIST_EMPTY(&sc->sc_pil)) { 1813 /* No interrupt handlers */ 1814 1815 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1816 1817 /* stop routing PCI intr */ 1818 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1819 reg |= CB_BCR_INTR_IREQ_ENABLE; 1820 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, reg); 1821 1822 switch (sc->sc_chipset) { 1823 case CB_TI113X: 1824 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1825 /* functional intr disabled */ 1826 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1827 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1828 break; 1829 default: 1830 break; 1831 } 1832 } 1833 } 1834 1835 #if defined SHOW_REGS 1836 static void 1837 cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, bus_space_tag_t memt, 1838 bus_space_handle_t memh) 1839 { 1840 int i; 1841 printf("PCI config regs:"); 1842 for (i = 0; i < 0x50; i += 4) { 1843 if (i % 16 == 0) 1844 printf("\n 0x%02x:", i); 1845 printf(" %08x", pci_conf_read(pc, tag, i)); 1846 } 1847 for (i = 0x80; i < 0xb0; i += 4) { 1848 if (i % 16 == 0) 1849 printf("\n 0x%02x:", i); 1850 printf(" %08x", pci_conf_read(pc, tag, i)); 1851 } 1852 1853 if (memh == 0) { 1854 printf("\n"); 1855 return; 1856 } 1857 1858 printf("\nsocket regs:"); 1859 for (i = 0; i <= 0x10; i += 0x04) 1860 printf(" %08x", bus_space_read_4(memt, memh, i)); 1861 printf("\nExCA regs:"); 1862 for (i = 0; i < 0x08; ++i) 1863 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1864 printf("\n"); 1865 return; 1866 } 1867 #endif 1868 1869 /* 1870 * static pcitag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1871 * int busno, int function) 1872 * This is the function to make a tag to access config space of 1873 * a CardBus Card. It works same as pci_conf_read. 1874 */ 1875 static pcitag_t 1876 pccbb_make_tag(cardbus_chipset_tag_t cc, int busno, int function) 1877 { 1878 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1879 1880 return pci_make_tag(sc->sc_pc, busno, 0, function); 1881 } 1882 1883 /* 1884 * pccbb_conf_read 1885 * 1886 * This is the function to read the config space of a CardBus card. 1887 * It works the same as pci_conf_read(9). 1888 */ 1889 static pcireg_t 1890 pccbb_conf_read(cardbus_chipset_tag_t cc, pcitag_t tag, int offset) 1891 { 1892 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1893 pcitag_t brtag = sc->sc_tag; 1894 pcireg_t reg; 1895 1896 /* 1897 * clear cardbus master abort status; it is OK to write without 1898 * reading before because all bits are r/o or w1tc 1899 */ 1900 pci_conf_write(sc->sc_pc, brtag, PCI_CBB_SECSTATUS, 1901 CBB_SECSTATUS_CBMABORT); 1902 reg = pci_conf_read(sc->sc_pc, tag, offset); 1903 /* check cardbus master abort status */ 1904 if (pci_conf_read(sc->sc_pc, brtag, PCI_CBB_SECSTATUS) 1905 & CBB_SECSTATUS_CBMABORT) 1906 return (0xffffffff); 1907 return reg; 1908 } 1909 1910 /* 1911 * pccbb_conf_write 1912 * 1913 * This is the function to write the config space of a CardBus 1914 * card. It works the same as pci_conf_write(9). 1915 */ 1916 static void 1917 pccbb_conf_write(cardbus_chipset_tag_t cc, pcitag_t tag, int reg, pcireg_t val) 1918 { 1919 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1920 1921 pci_conf_write(sc->sc_pc, tag, reg, val); 1922 } 1923 1924 #if 0 1925 STATIC int 1926 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1927 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 1928 int speed, int flags, 1929 bus_space_handle_t * iohp) 1930 #endif 1931 /* 1932 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1933 * bus_addr_t start, bus_size_t size, 1934 * bus_size_t align, 1935 * struct pcmcia_io_handle *pcihp 1936 * 1937 * This function only allocates I/O region for pccard. This function 1938 * never maps the allocated region to pccard I/O area. 1939 * 1940 * XXX: The interface of this function is not very good, I believe. 1941 */ 1942 STATIC int 1943 pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, 1944 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 1945 { 1946 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 1947 bus_addr_t ioaddr; 1948 int flags = 0; 1949 bus_space_tag_t iot; 1950 bus_space_handle_t ioh; 1951 bus_addr_t mask; 1952 #if rbus 1953 rbus_tag_t rb; 1954 #endif 1955 if (align == 0) { 1956 align = size; /* XXX: funny??? */ 1957 } 1958 1959 if (start != 0) { 1960 /* XXX: assume all card decode lower 10 bits by its hardware */ 1961 mask = 0x3ff; 1962 /* enforce to use only masked address */ 1963 start &= mask; 1964 } else { 1965 /* 1966 * calculate mask: 1967 * 1. get the most significant bit of size (call it msb). 1968 * 2. compare msb with the value of size. 1969 * 3. if size is larger, shift msb left once. 1970 * 4. obtain mask value to decrement msb. 1971 */ 1972 bus_size_t size_tmp = size; 1973 int shifts = 0; 1974 1975 mask = 1; 1976 while (size_tmp) { 1977 ++shifts; 1978 size_tmp >>= 1; 1979 } 1980 mask = (1 << shifts); 1981 if (mask < size) { 1982 mask <<= 1; 1983 } 1984 --mask; 1985 } 1986 1987 /* 1988 * Allocate some arbitrary I/O space. 1989 */ 1990 1991 iot = sc->sc_iot; 1992 1993 #if rbus 1994 rb = sc->sc_rbus_iot; 1995 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 1996 return 1; 1997 } 1998 DPRINTF(("pccbb_pcmcia_io_alloc alloc port 0x%lx+0x%lx\n", 1999 (u_long) ioaddr, (u_long) size)); 2000 #else 2001 if (start) { 2002 ioaddr = start; 2003 if (bus_space_map(iot, start, size, 0, &ioh)) { 2004 return 1; 2005 } 2006 DPRINTF(("pccbb_pcmcia_io_alloc map port 0x%lx+0x%lx\n", 2007 (u_long) ioaddr, (u_long) size)); 2008 } else { 2009 flags |= PCMCIA_IO_ALLOCATED; 2010 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 2011 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 2012 size, align, 0, 0, &ioaddr, &ioh)) { 2013 /* No room be able to be get. */ 2014 return 1; 2015 } 2016 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2017 (u_long) ioaddr, (u_long) size)); 2018 } 2019 #endif 2020 2021 pcihp->iot = iot; 2022 pcihp->ioh = ioh; 2023 pcihp->addr = ioaddr; 2024 pcihp->size = size; 2025 pcihp->flags = flags; 2026 2027 return 0; 2028 } 2029 2030 /* 2031 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2032 * struct pcmcia_io_handle *pcihp) 2033 * 2034 * This function only frees I/O region for pccard. 2035 * 2036 * XXX: The interface of this function is not very good, I believe. 2037 */ 2038 void 2039 pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2040 struct pcmcia_io_handle *pcihp) 2041 { 2042 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2043 #if !rbus 2044 bus_space_tag_t iot = pcihp->iot; 2045 #endif 2046 bus_space_handle_t ioh = pcihp->ioh; 2047 bus_size_t size = pcihp->size; 2048 2049 #if rbus 2050 rbus_tag_t rb = sc->sc_rbus_iot; 2051 2052 rbus_space_free(rb, ioh, size, NULL); 2053 #else 2054 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 2055 bus_space_free(iot, ioh, size); 2056 else 2057 bus_space_unmap(iot, ioh, size); 2058 #endif 2059 } 2060 2061 /* 2062 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 2063 * bus_addr_t offset, bus_size_t size, 2064 * struct pcmcia_io_handle *pcihp, 2065 * int *windowp) 2066 * 2067 * This function maps the allocated I/O region to pccard. This function 2068 * never allocates any I/O region for pccard I/O area. I don't 2069 * understand why the original authors of pcmciabus separated alloc and 2070 * map. I believe the two must be unite. 2071 * 2072 * XXX: no wait timing control? 2073 */ 2074 int 2075 pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, bus_addr_t offset, 2076 bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp) 2077 { 2078 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2079 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2080 bus_addr_t ioaddr = pcihp->addr + offset; 2081 int i, win; 2082 #if defined CBB_DEBUG 2083 static const char *width_names[] = { "dynamic", "io8", "io16" }; 2084 #endif 2085 2086 /* Sanity check I/O handle. */ 2087 2088 if (!bus_space_is_equal(sc->sc_iot, pcihp->iot)) { 2089 panic("pccbb_pcmcia_io_map iot is bogus"); 2090 } 2091 2092 /* XXX Sanity check offset/size. */ 2093 2094 win = -1; 2095 for (i = 0; i < PCIC_IO_WINS; i++) { 2096 if ((ph->ioalloc & (1 << i)) == 0) { 2097 win = i; 2098 ph->ioalloc |= (1 << i); 2099 break; 2100 } 2101 } 2102 2103 if (win == -1) { 2104 return 1; 2105 } 2106 2107 *windowp = win; 2108 2109 /* XXX this is pretty gross */ 2110 2111 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2112 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2113 2114 /* XXX wtf is this doing here? */ 2115 2116 #if 0 2117 printf(" port 0x%lx", (u_long) ioaddr); 2118 if (size > 1) { 2119 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2120 } 2121 #endif 2122 2123 ph->io[win].addr = ioaddr; 2124 ph->io[win].size = size; 2125 ph->io[win].width = width; 2126 2127 /* actual dirty register-value changing in the function below. */ 2128 pccbb_pcmcia_do_io_map(sc, win); 2129 2130 return 0; 2131 } 2132 2133 /* 2134 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2135 * 2136 * This function changes register-value to map I/O region for pccard. 2137 */ 2138 static void 2139 pccbb_pcmcia_do_io_map(struct pccbb_softc *sc, int win) 2140 { 2141 static u_int8_t pcic_iowidth[3] = { 2142 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2143 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2144 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2145 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2146 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2147 }; 2148 2149 #define PCIC_SIA_START_LOW 0 2150 #define PCIC_SIA_START_HIGH 1 2151 #define PCIC_SIA_STOP_LOW 2 2152 #define PCIC_SIA_STOP_HIGH 3 2153 2154 int regbase_win = 0x8 + win * 0x04; 2155 u_int8_t ioctl, enable; 2156 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2157 2158 DPRINTF(("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx " 2159 "width %d\n", win, (unsigned long)ph->io[win].addr, 2160 (unsigned long)ph->io[win].size, ph->io[win].width * 8)); 2161 2162 Pcic_write(sc, regbase_win + PCIC_SIA_START_LOW, 2163 ph->io[win].addr & 0xff); 2164 Pcic_write(sc, regbase_win + PCIC_SIA_START_HIGH, 2165 (ph->io[win].addr >> 8) & 0xff); 2166 2167 Pcic_write(sc, regbase_win + PCIC_SIA_STOP_LOW, 2168 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2169 Pcic_write(sc, regbase_win + PCIC_SIA_STOP_HIGH, 2170 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2171 2172 ioctl = Pcic_read(sc, PCIC_IOCTL); 2173 enable = Pcic_read(sc, PCIC_ADDRWIN_ENABLE); 2174 switch (win) { 2175 case 0: 2176 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2177 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2178 PCIC_IOCTL_IO0_DATASIZE_MASK); 2179 ioctl |= pcic_iowidth[ph->io[win].width]; 2180 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2181 break; 2182 case 1: 2183 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2184 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2185 PCIC_IOCTL_IO1_DATASIZE_MASK); 2186 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2187 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2188 break; 2189 } 2190 Pcic_write(sc, PCIC_IOCTL, ioctl); 2191 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, enable); 2192 #if defined(CBB_DEBUG) 2193 { 2194 u_int8_t start_low = 2195 Pcic_read(sc, regbase_win + PCIC_SIA_START_LOW); 2196 u_int8_t start_high = 2197 Pcic_read(sc, regbase_win + PCIC_SIA_START_HIGH); 2198 u_int8_t stop_low = 2199 Pcic_read(sc, regbase_win + PCIC_SIA_STOP_LOW); 2200 u_int8_t stop_high = 2201 Pcic_read(sc, regbase_win + PCIC_SIA_STOP_HIGH); 2202 printf("pccbb_pcmcia_do_io_map start %02x %02x, " 2203 "stop %02x %02x, ioctl %02x enable %02x\n", 2204 start_low, start_high, stop_low, stop_high, ioctl, enable); 2205 } 2206 #endif 2207 } 2208 2209 /* 2210 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2211 * 2212 * This function unmaps I/O region. No return value. 2213 */ 2214 STATIC void 2215 pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t pch, int win) 2216 { 2217 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2218 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2219 int reg; 2220 2221 if (win >= PCIC_IO_WINS || win < 0) { 2222 panic("pccbb_pcmcia_io_unmap: window out of range"); 2223 } 2224 2225 reg = Pcic_read(sc, PCIC_ADDRWIN_ENABLE); 2226 switch (win) { 2227 case 0: 2228 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2229 break; 2230 case 1: 2231 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2232 break; 2233 } 2234 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, reg); 2235 2236 ph->ioalloc &= ~(1 << win); 2237 } 2238 2239 static int 2240 pccbb_pcmcia_wait_ready(struct pccbb_softc *sc) 2241 { 2242 u_int8_t stat; 2243 int i; 2244 2245 /* wait an initial 10ms for quick cards */ 2246 stat = Pcic_read(sc, PCIC_IF_STATUS); 2247 if (stat & PCIC_IF_STATUS_READY) 2248 return (0); 2249 pccbb_pcmcia_delay(sc, 10, "pccwr0"); 2250 for (i = 0; i < 50; i++) { 2251 stat = Pcic_read(sc, PCIC_IF_STATUS); 2252 if (stat & PCIC_IF_STATUS_READY) 2253 return (0); 2254 if ((stat & PCIC_IF_STATUS_CARDDETECT_MASK) != 2255 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2256 return (ENXIO); 2257 /* wait .1s (100ms) each iteration now */ 2258 pccbb_pcmcia_delay(sc, 100, "pccwr1"); 2259 } 2260 2261 printf("pccbb_pcmcia_wait_ready: ready never happened, status=%02x\n", stat); 2262 return (EWOULDBLOCK); 2263 } 2264 2265 /* 2266 * Perform long (msec order) delay. timo is in milliseconds. 2267 */ 2268 static void 2269 pccbb_pcmcia_delay(struct pccbb_softc *sc, int timo, const char *wmesg) 2270 { 2271 #ifdef DIAGNOSTIC 2272 if (timo <= 0) 2273 panic("pccbb_pcmcia_delay: called with timeout %d", timo); 2274 if (!curlwp) 2275 panic("pccbb_pcmcia_delay: called in interrupt context"); 2276 #endif 2277 DPRINTF(("pccbb_pcmcia_delay: \"%s\", sleep %d ms\n", wmesg, timo)); 2278 kpause(wmesg, false, max(mstohz(timo), 1), NULL); 2279 } 2280 2281 /* 2282 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2283 * 2284 * This function enables the card. All information is stored in 2285 * the first argument, pcmcia_chipset_handle_t. 2286 */ 2287 STATIC void 2288 pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2289 { 2290 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2291 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2292 pcireg_t spsr; 2293 int voltage; 2294 int win; 2295 u_int8_t power, intr; 2296 #ifdef DIAGNOSTIC 2297 int reg; 2298 #endif 2299 2300 /* this bit is mostly stolen from pcic_attach_card */ 2301 2302 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2303 2304 /* get card Vcc info */ 2305 spsr = 2306 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2307 CB_SOCKET_STAT); 2308 if (spsr & CB_SOCKET_STAT_5VCARD) { 2309 DPRINTF(("5V card\n")); 2310 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2311 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2312 DPRINTF(("3V card\n")); 2313 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2314 } else { 2315 DPRINTF(("?V card, 0x%x\n", spsr)); /* XXX */ 2316 return; 2317 } 2318 2319 /* disable interrupts; assert RESET */ 2320 intr = Pcic_read(sc, PCIC_INTR); 2321 intr &= PCIC_INTR_ENABLE; 2322 Pcic_write(sc, PCIC_INTR, intr); 2323 2324 /* zero out the address windows */ 2325 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, 0); 2326 2327 /* power down the socket to reset it, clear the card reset pin */ 2328 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2329 2330 /* power off; assert output enable bit */ 2331 power = PCIC_PWRCTL_OE; 2332 Pcic_write(sc, PCIC_PWRCTL, power); 2333 2334 /* power up the socket */ 2335 if (pccbb_power(sc, voltage) == 0) 2336 return; 2337 2338 /* 2339 * Table 4-18 and figure 4-6 of the PC Card specifiction say: 2340 * Vcc Rising Time (Tpr) = 100ms (handled in pccbb_power() above) 2341 * RESET Width (Th (Hi-z RESET)) = 1ms 2342 * RESET Width (Tw (RESET)) = 10us 2343 * 2344 * some machines require some more time to be settled 2345 * for example old toshiba topic bridges! 2346 * (100ms is added here). 2347 */ 2348 pccbb_pcmcia_delay(sc, 200 + 1, "pccen1"); 2349 2350 /* negate RESET */ 2351 intr |= PCIC_INTR_RESET; 2352 Pcic_write(sc, PCIC_INTR, intr); 2353 2354 /* 2355 * RESET Setup Time (Tsu (RESET)) = 20ms 2356 */ 2357 pccbb_pcmcia_delay(sc, 20, "pccen2"); 2358 2359 #ifdef DIAGNOSTIC 2360 reg = Pcic_read(sc, PCIC_IF_STATUS); 2361 if ((reg & PCIC_IF_STATUS_POWERACTIVE) == 0) 2362 printf("pccbb_pcmcia_socket_enable: no power, status=%x\n", reg); 2363 #endif 2364 2365 /* wait for the chip to finish initializing */ 2366 if (pccbb_pcmcia_wait_ready(sc)) { 2367 #ifdef DIAGNOSTIC 2368 printf("pccbb_pcmcia_socket_enable: never became ready\n"); 2369 #endif 2370 /* XXX return a failure status?? */ 2371 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2372 Pcic_write(sc, PCIC_PWRCTL, 0); 2373 return; 2374 } 2375 2376 /* reinstall all the memory and io mappings */ 2377 for (win = 0; win < PCIC_MEM_WINS; ++win) 2378 if (ph->memalloc & (1 << win)) 2379 pccbb_pcmcia_do_mem_map(sc, win); 2380 for (win = 0; win < PCIC_IO_WINS; ++win) 2381 if (ph->ioalloc & (1 << win)) 2382 pccbb_pcmcia_do_io_map(sc, win); 2383 } 2384 2385 /* 2386 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2387 * 2388 * This function disables the card. All information is stored in 2389 * the first argument, pcmcia_chipset_handle_t. 2390 */ 2391 STATIC void 2392 pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t pch) 2393 { 2394 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2395 u_int8_t intr; 2396 2397 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2398 2399 /* disable interrupts; assert RESET */ 2400 intr = Pcic_read(sc, PCIC_INTR); 2401 intr &= PCIC_INTR_ENABLE; 2402 Pcic_write(sc, PCIC_INTR, intr); 2403 2404 /* zero out the address windows */ 2405 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, 0); 2406 2407 /* power down the socket to reset it, clear the card reset pin */ 2408 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2409 2410 /* disable socket: negate output enable bit and power off */ 2411 Pcic_write(sc, PCIC_PWRCTL, 0); 2412 2413 /* 2414 * Vcc Falling Time (Tpf) = 300ms 2415 */ 2416 pccbb_pcmcia_delay(sc, 300, "pccwr1"); 2417 } 2418 2419 STATIC void 2420 pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t pch, int type) 2421 { 2422 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2423 u_int8_t intr; 2424 2425 /* set the card type */ 2426 2427 intr = Pcic_read(sc, PCIC_INTR); 2428 intr &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_CARDTYPE_MASK); 2429 if (type == PCMCIA_IFTYPE_IO) 2430 intr |= PCIC_INTR_CARDTYPE_IO; 2431 else 2432 intr |= PCIC_INTR_CARDTYPE_MEM; 2433 Pcic_write(sc, PCIC_INTR, intr); 2434 2435 DPRINTF(("%s: pccbb_pcmcia_socket_settype type %s %02x\n", 2436 device_xname(sc->sc_dev), 2437 ((type == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2438 } 2439 2440 /* 2441 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2442 * 2443 * This function detects whether a card is in the slot or not. 2444 * If a card is inserted, return 1. Otherwise, return 0. 2445 */ 2446 STATIC int 2447 pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch) 2448 { 2449 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2450 2451 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2452 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2453 } 2454 2455 #if 0 2456 STATIC int 2457 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2458 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2459 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2460 #endif 2461 /* 2462 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2463 * bus_size_t size, 2464 * struct pcmcia_mem_handle *pcmhp) 2465 * 2466 * This function only allocates memory region for pccard. This 2467 * function never maps the allocated region to pccard memory area. 2468 * 2469 * XXX: Why the argument of start address is not in? 2470 */ 2471 STATIC int 2472 pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 2473 struct pcmcia_mem_handle *pcmhp) 2474 { 2475 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2476 bus_space_handle_t memh; 2477 bus_addr_t addr; 2478 bus_size_t sizepg; 2479 #if rbus 2480 rbus_tag_t rb; 2481 #endif 2482 2483 /* Check that the card is still there. */ 2484 if ((Pcic_read(sc, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2485 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2486 return 1; 2487 2488 /* out of sc->memh, allocate as many pages as necessary */ 2489 2490 /* convert size to PCIC pages */ 2491 /* 2492 * This is not enough; when the requested region is on the page 2493 * boundaries, this may calculate wrong result. 2494 */ 2495 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2496 #if 0 2497 if (sizepg > PCIC_MAX_MEM_PAGES) { 2498 return 1; 2499 } 2500 #endif 2501 2502 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2503 return 1; 2504 } 2505 2506 addr = 0; /* XXX gcc -Wuninitialized */ 2507 2508 #if rbus 2509 rb = sc->sc_rbus_memt; 2510 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2511 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2512 &addr, &memh)) { 2513 return 1; 2514 } 2515 #else 2516 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2517 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2518 0, /* boundary */ 2519 0, /* flags */ 2520 &addr, &memh)) { 2521 return 1; 2522 } 2523 #endif 2524 2525 DPRINTF(("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, " 2526 "realsize 0x%lx\n", (unsigned long)addr, (unsigned long)size, 2527 (unsigned long)sizepg * PCIC_MEM_PAGESIZE)); 2528 2529 pcmhp->memt = sc->sc_memt; 2530 pcmhp->memh = memh; 2531 pcmhp->addr = addr; 2532 pcmhp->size = size; 2533 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2534 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2535 pcmhp->mhandle = 0; 2536 /* No offset??? Funny. */ 2537 2538 return 0; 2539 } 2540 2541 /* 2542 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2543 * struct pcmcia_mem_handle *pcmhp) 2544 * 2545 * This function release the memory space allocated by the function 2546 * pccbb_pcmcia_mem_alloc(). 2547 */ 2548 STATIC void 2549 pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2550 struct pcmcia_mem_handle *pcmhp) 2551 { 2552 #if rbus 2553 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2554 2555 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2556 #else 2557 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2558 #endif 2559 } 2560 2561 /* 2562 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2563 * 2564 * This function release the memory space allocated by the function 2565 * pccbb_pcmcia_mem_alloc(). 2566 */ 2567 STATIC void 2568 pccbb_pcmcia_do_mem_map(struct pccbb_softc *sc, int win) 2569 { 2570 int regbase_win; 2571 bus_addr_t phys_addr; 2572 bus_addr_t phys_end; 2573 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2574 2575 #define PCIC_SMM_START_LOW 0 2576 #define PCIC_SMM_START_HIGH 1 2577 #define PCIC_SMM_STOP_LOW 2 2578 #define PCIC_SMM_STOP_HIGH 3 2579 #define PCIC_CMA_LOW 4 2580 #define PCIC_CMA_HIGH 5 2581 2582 u_int8_t start_low, start_high = 0; 2583 u_int8_t stop_low, stop_high; 2584 u_int8_t off_low, off_high; 2585 u_int8_t mem_window; 2586 int reg; 2587 2588 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2589 int mem8 = 2590 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2591 || (kind == PCMCIA_MEM_ATTR); 2592 2593 regbase_win = 0x10 + win * 0x08; 2594 2595 phys_addr = ph->mem[win].addr; 2596 phys_end = phys_addr + ph->mem[win].size; 2597 2598 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2599 (unsigned long)phys_addr, (unsigned long)phys_end, 2600 (unsigned long)ph->mem[win].offset)); 2601 2602 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2603 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2604 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2605 2606 /* bit 19:12 */ 2607 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2608 /* bit 23:20 and bit 7 on */ 2609 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2610 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2611 /* bit 31:24, for 32-bit address */ 2612 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2613 2614 Pcic_write(sc, regbase_win + PCIC_SMM_START_LOW, start_low); 2615 Pcic_write(sc, regbase_win + PCIC_SMM_START_HIGH, start_high); 2616 2617 if (sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2618 Pcic_write(sc, 0x40 + win, mem_window); 2619 } 2620 2621 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2622 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2623 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2624 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2625 2626 Pcic_write(sc, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2627 Pcic_write(sc, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2628 2629 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2630 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2631 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2632 | ((kind == PCMCIA_MEM_ATTR) ? 2633 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2634 2635 Pcic_write(sc, regbase_win + PCIC_CMA_LOW, off_low); 2636 Pcic_write(sc, regbase_win + PCIC_CMA_HIGH, off_high); 2637 2638 reg = Pcic_read(sc, PCIC_ADDRWIN_ENABLE); 2639 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2640 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, reg); 2641 2642 #if defined(CBB_DEBUG) 2643 { 2644 int r1, r2, r3, r4, r5, r6, r7 = 0; 2645 2646 r1 = Pcic_read(sc, regbase_win + PCIC_SMM_START_LOW); 2647 r2 = Pcic_read(sc, regbase_win + PCIC_SMM_START_HIGH); 2648 r3 = Pcic_read(sc, regbase_win + PCIC_SMM_STOP_LOW); 2649 r4 = Pcic_read(sc, regbase_win + PCIC_SMM_STOP_HIGH); 2650 r5 = Pcic_read(sc, regbase_win + PCIC_CMA_LOW); 2651 r6 = Pcic_read(sc, regbase_win + PCIC_CMA_HIGH); 2652 if (sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2653 r7 = Pcic_read(sc, 0x40 + win); 2654 } 2655 2656 printf("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2657 "%02x%02x", win, r1, r2, r3, r4, r5, r6); 2658 if (sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2659 printf(" %02x", r7); 2660 } 2661 printf("\n"); 2662 } 2663 #endif 2664 } 2665 2666 /* 2667 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2668 * bus_addr_t card_addr, bus_size_t size, 2669 * struct pcmcia_mem_handle *pcmhp, 2670 * bus_addr_t *offsetp, int *windowp) 2671 * 2672 * This function maps memory space allocated by the function 2673 * pccbb_pcmcia_mem_alloc(). 2674 */ 2675 STATIC int 2676 pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2677 bus_addr_t card_addr, bus_size_t size, struct pcmcia_mem_handle *pcmhp, 2678 bus_size_t *offsetp, int *windowp) 2679 { 2680 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2681 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2682 bus_addr_t busaddr; 2683 long card_offset; 2684 int win; 2685 2686 /* Check that the card is still there. */ 2687 if ((Pcic_read(sc, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2688 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2689 return 1; 2690 2691 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2692 if ((ph->memalloc & (1 << win)) == 0) { 2693 ph->memalloc |= (1 << win); 2694 break; 2695 } 2696 } 2697 2698 if (win == PCIC_MEM_WINS) { 2699 return 1; 2700 } 2701 2702 *windowp = win; 2703 2704 /* XXX this is pretty gross */ 2705 2706 if (!bus_space_is_equal(sc->sc_memt, pcmhp->memt)) { 2707 panic("pccbb_pcmcia_mem_map memt is bogus"); 2708 } 2709 2710 busaddr = pcmhp->addr; 2711 2712 /* 2713 * compute the address offset to the pcmcia address space for the 2714 * pcic. this is intentionally signed. The masks and shifts below 2715 * will cause TRT to happen in the pcic registers. Deal with making 2716 * sure the address is aligned, and return the alignment offset. 2717 */ 2718 2719 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2720 card_addr -= *offsetp; 2721 2722 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2723 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2724 (u_long) card_addr)); 2725 2726 /* 2727 * include the offset in the size, and decrement size by one, since 2728 * the hw wants start/stop 2729 */ 2730 size += *offsetp - 1; 2731 2732 card_offset = (((long)card_addr) - ((long)busaddr)); 2733 2734 ph->mem[win].addr = busaddr; 2735 ph->mem[win].size = size; 2736 ph->mem[win].offset = card_offset; 2737 ph->mem[win].kind = kind; 2738 2739 pccbb_pcmcia_do_mem_map(sc, win); 2740 2741 return 0; 2742 } 2743 2744 /* 2745 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2746 * int window) 2747 * 2748 * This function unmaps memory space which mapped by the function 2749 * pccbb_pcmcia_mem_map(). 2750 */ 2751 STATIC void 2752 pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, int window) 2753 { 2754 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2755 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2756 int reg; 2757 2758 if (window >= PCIC_MEM_WINS) { 2759 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2760 } 2761 2762 reg = Pcic_read(sc, PCIC_ADDRWIN_ENABLE); 2763 reg &= ~(1 << window); 2764 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, reg); 2765 2766 ph->memalloc &= ~(1 << window); 2767 } 2768 2769 /* 2770 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2771 * struct pcmcia_function *pf, 2772 * int ipl, 2773 * int (*func)(void *), 2774 * void *arg); 2775 * 2776 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2777 */ 2778 STATIC void * 2779 pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2780 struct pcmcia_function *pf, int ipl, int (*func)(void *), void *arg) 2781 { 2782 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2783 2784 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2785 /* what should I do? */ 2786 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2787 DPRINTF(("%s does not provide edge nor pulse " 2788 "interrupt\n", device_xname(sc->sc_dev))); 2789 return NULL; 2790 } 2791 /* 2792 * XXX Noooooo! The interrupt flag must set properly!! 2793 * dumb pcmcia driver!! 2794 */ 2795 } 2796 2797 return pccbb_intr_establish(sc, 0, ipl, func, arg); 2798 } 2799 2800 /* 2801 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2802 * void *ih) 2803 * 2804 * This function disables PC-Card interrupt. 2805 */ 2806 STATIC void 2807 pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 2808 { 2809 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2810 2811 pccbb_intr_disestablish(sc, ih); 2812 } 2813 2814 #if rbus 2815 /* 2816 * static int 2817 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2818 * bus_addr_t addr, bus_size_t size, 2819 * bus_addr_t mask, bus_size_t align, 2820 * int flags, bus_addr_t *addrp; 2821 * bus_space_handle_t *bshp) 2822 * 2823 * This function allocates a portion of memory or io space for 2824 * clients. This function is called from CardBus card drivers. 2825 */ 2826 static int 2827 pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2828 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 2829 int flags, bus_addr_t *addrp, bus_space_handle_t *bshp) 2830 { 2831 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2832 2833 DPRINTF(("pccbb_rbus_cb_space_alloc: addr 0x%lx, size 0x%lx, " 2834 "mask 0x%lx, align 0x%lx\n", (unsigned long)addr, 2835 (unsigned long)size, (unsigned long)mask, (unsigned long)align)); 2836 2837 if (align == 0) { 2838 align = size; 2839 } 2840 2841 if (bus_space_is_equal(rb->rb_bt, sc->sc_memt)) { 2842 if (align < 16) { 2843 return 1; 2844 } 2845 /* 2846 * XXX: align more than 0x1000 to avoid overwrapping 2847 * memory windows for two or more devices. 0x1000 2848 * means memory window's granularity. 2849 * 2850 * Two or more devices should be able to share same 2851 * memory window region. However, overrapping memory 2852 * window is not good because some devices, such as 2853 * 3Com 3C575[BC], have a broken address decoder and 2854 * intrude other's memory region. 2855 */ 2856 if (align < 0x1000) { 2857 align = 0x1000; 2858 } 2859 } else if (bus_space_is_equal(rb->rb_bt, sc->sc_iot)) { 2860 if (align < 4) { 2861 return 1; 2862 } 2863 /* XXX: hack for avoiding ISA image */ 2864 if (mask < 0x0100) { 2865 mask = 0x3ff; 2866 addr = 0x300; 2867 } 2868 2869 } else { 2870 DPRINTF(("pccbb_rbus_cb_space_alloc: Bus space tag 0x%lx is " 2871 "NOT used. io: 0x%lx, mem: 0x%lx\n", 2872 (unsigned long)rb->rb_bt, (unsigned long)sc->sc_iot, 2873 (unsigned long)sc->sc_memt)); 2874 return 1; 2875 /* XXX: panic here? */ 2876 } 2877 2878 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 2879 aprint_normal_dev(sc->sc_dev, "<rbus> no bus space\n"); 2880 return 1; 2881 } 2882 2883 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 2884 2885 return 0; 2886 } 2887 2888 /* 2889 * static int 2890 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 2891 * bus_space_handle_t *bshp, bus_size_t size); 2892 * 2893 * This function is called from CardBus card drivers. 2894 */ 2895 static int 2896 pccbb_rbus_cb_space_free(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2897 bus_space_handle_t bsh, bus_size_t size) 2898 { 2899 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2900 bus_space_tag_t bt = rb->rb_bt; 2901 2902 pccbb_close_win(sc, bt, bsh, size); 2903 2904 if (bus_space_is_equal(bt, sc->sc_memt)) { 2905 } else if (bus_space_is_equal(bt, sc->sc_iot)) { 2906 } else { 2907 return 1; 2908 /* XXX: panic here? */ 2909 } 2910 2911 return rbus_space_free(rb, bsh, size, NULL); 2912 } 2913 #endif /* rbus */ 2914 2915 #if rbus 2916 2917 static int 2918 pccbb_open_win(struct pccbb_softc *sc, bus_space_tag_t bst, bus_addr_t addr, 2919 bus_size_t size, bus_space_handle_t bsh, int flags) 2920 { 2921 struct pccbb_win_chain_head *head; 2922 bus_addr_t align; 2923 2924 head = &sc->sc_iowindow; 2925 align = 0x04; 2926 if (bus_space_is_equal(sc->sc_memt, bst)) { 2927 head = &sc->sc_memwindow; 2928 align = 0x1000; 2929 DPRINTF(("using memory window, 0x%lx 0x%lx 0x%lx\n\n", 2930 (unsigned long)sc->sc_iot, (unsigned long)sc->sc_memt, 2931 (unsigned long)bst)); 2932 } 2933 2934 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 2935 aprint_error_dev(sc->sc_dev, 2936 "pccbb_open_win: %s winlist insert failed\n", 2937 (head == &sc->sc_memwindow) ? "mem" : "io"); 2938 } 2939 pccbb_winset(align, sc, bst); 2940 2941 return 0; 2942 } 2943 2944 static int 2945 pccbb_close_win(struct pccbb_softc *sc, bus_space_tag_t bst, 2946 bus_space_handle_t bsh, bus_size_t size) 2947 { 2948 struct pccbb_win_chain_head *head; 2949 bus_addr_t align; 2950 2951 head = &sc->sc_iowindow; 2952 align = 0x04; 2953 if (bus_space_is_equal(sc->sc_memt, bst)) { 2954 head = &sc->sc_memwindow; 2955 align = 0x1000; 2956 } 2957 2958 if (pccbb_winlist_delete(head, bsh, size)) { 2959 aprint_error_dev(sc->sc_dev, 2960 "pccbb_close_win: %s winlist delete failed\n", 2961 (head == &sc->sc_memwindow) ? "mem" : "io"); 2962 } 2963 pccbb_winset(align, sc, bst); 2964 2965 return 0; 2966 } 2967 2968 static int 2969 pccbb_winlist_insert(struct pccbb_win_chain_head *head, bus_addr_t start, 2970 bus_size_t size, bus_space_handle_t bsh, int flags) 2971 { 2972 struct pccbb_win_chain *chainp, *elem; 2973 2974 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 2975 M_NOWAIT)) == NULL) 2976 return (1); /* fail */ 2977 2978 elem->wc_start = start; 2979 elem->wc_end = start + (size - 1); 2980 elem->wc_handle = bsh; 2981 elem->wc_flags = flags; 2982 2983 TAILQ_FOREACH(chainp, head, wc_list) { 2984 if (chainp->wc_end >= start) 2985 break; 2986 } 2987 if (chainp != NULL) 2988 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 2989 else 2990 TAILQ_INSERT_TAIL(head, elem, wc_list); 2991 return (0); 2992 } 2993 2994 static int 2995 pccbb_winlist_delete(struct pccbb_win_chain_head *head, bus_space_handle_t bsh, 2996 bus_size_t size) 2997 { 2998 struct pccbb_win_chain *chainp; 2999 3000 TAILQ_FOREACH(chainp, head, wc_list) { 3001 if (memcmp(&chainp->wc_handle, &bsh, sizeof(bsh)) == 0) 3002 break; 3003 } 3004 if (chainp == NULL) 3005 return 1; /* fail: no candidate to remove */ 3006 3007 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 3008 printf("pccbb_winlist_delete: window 0x%lx size " 3009 "inconsistent: 0x%lx, 0x%lx\n", 3010 (unsigned long)chainp->wc_start, 3011 (unsigned long)(chainp->wc_end - chainp->wc_start), 3012 (unsigned long)(size - 1)); 3013 return 1; 3014 } 3015 3016 TAILQ_REMOVE(head, chainp, wc_list); 3017 free(chainp, M_DEVBUF); 3018 3019 return 0; 3020 } 3021 3022 static void 3023 pccbb_winset(bus_addr_t align, struct pccbb_softc *sc, bus_space_tag_t bst) 3024 { 3025 pci_chipset_tag_t pc; 3026 pcitag_t tag; 3027 bus_addr_t mask = ~(align - 1); 3028 struct { 3029 pcireg_t win_start; 3030 pcireg_t win_limit; 3031 int win_flags; 3032 } win[2]; 3033 struct pccbb_win_chain *chainp; 3034 int offs; 3035 3036 win[0].win_start = win[1].win_start = 0xffffffff; 3037 win[0].win_limit = win[1].win_limit = 0; 3038 win[0].win_flags = win[1].win_flags = 0; 3039 3040 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3041 offs = PCI_CB_IOBASE0; 3042 if (bus_space_is_equal(sc->sc_memt, bst)) { 3043 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3044 offs = PCI_CB_MEMBASE0; 3045 } 3046 3047 if (chainp != NULL) { 3048 win[0].win_start = chainp->wc_start & mask; 3049 win[0].win_limit = chainp->wc_end & mask; 3050 win[0].win_flags = chainp->wc_flags; 3051 chainp = TAILQ_NEXT(chainp, wc_list); 3052 } 3053 3054 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3055 if (win[1].win_start == 0xffffffff) { 3056 /* window 1 is not used */ 3057 if ((win[0].win_flags == chainp->wc_flags) && 3058 (win[0].win_limit + align >= 3059 (chainp->wc_start & mask))) { 3060 /* concatenate */ 3061 win[0].win_limit = chainp->wc_end & mask; 3062 } else { 3063 /* make new window */ 3064 win[1].win_start = chainp->wc_start & mask; 3065 win[1].win_limit = chainp->wc_end & mask; 3066 win[1].win_flags = chainp->wc_flags; 3067 } 3068 continue; 3069 } 3070 3071 /* Both windows are engaged. */ 3072 if (win[0].win_flags == win[1].win_flags) { 3073 /* same flags */ 3074 if (win[0].win_flags == chainp->wc_flags) { 3075 if (win[1].win_start - (win[0].win_limit + 3076 align) < 3077 (chainp->wc_start & mask) - 3078 ((chainp->wc_end & mask) + align)) { 3079 /* 3080 * merge window 0 and 1, and set win1 3081 * to chainp 3082 */ 3083 win[0].win_limit = win[1].win_limit; 3084 win[1].win_start = 3085 chainp->wc_start & mask; 3086 win[1].win_limit = 3087 chainp->wc_end & mask; 3088 } else { 3089 win[1].win_limit = 3090 chainp->wc_end & mask; 3091 } 3092 } else { 3093 /* different flags */ 3094 3095 /* concatenate win0 and win1 */ 3096 win[0].win_limit = win[1].win_limit; 3097 /* allocate win[1] to new space */ 3098 win[1].win_start = chainp->wc_start & mask; 3099 win[1].win_limit = chainp->wc_end & mask; 3100 win[1].win_flags = chainp->wc_flags; 3101 } 3102 } else { 3103 /* the flags of win[0] and win[1] is different */ 3104 if (win[0].win_flags == chainp->wc_flags) { 3105 win[0].win_limit = chainp->wc_end & mask; 3106 /* 3107 * XXX this creates overlapping windows, so 3108 * what should the poor bridge do if one is 3109 * cachable, and the other is not? 3110 */ 3111 aprint_error_dev(sc->sc_dev, 3112 "overlapping windows\n"); 3113 } else { 3114 win[1].win_limit = chainp->wc_end & mask; 3115 } 3116 } 3117 } 3118 3119 pc = sc->sc_pc; 3120 tag = sc->sc_tag; 3121 pci_conf_write(pc, tag, offs, win[0].win_start); 3122 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3123 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3124 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3125 DPRINTF(("--pccbb_winset: win0 [0x%lx, 0x%lx), win1 [0x%lx, 0x%lx)\n", 3126 (unsigned long)pci_conf_read(pc, tag, offs), 3127 (unsigned long)pci_conf_read(pc, tag, offs + 4) + align, 3128 (unsigned long)pci_conf_read(pc, tag, offs + 8), 3129 (unsigned long)pci_conf_read(pc, tag, offs + 12) + align)); 3130 3131 if (bus_space_is_equal(bst, sc->sc_memt)) { 3132 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BRIDGE_CONTROL_REG); 3133 3134 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 3135 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 3136 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3137 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 3138 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3139 pci_conf_write(pc, tag, PCI_BRIDGE_CONTROL_REG, bcr); 3140 } 3141 } 3142 3143 #endif /* rbus */ 3144 3145 static bool 3146 pccbb_suspend(device_t dv, const pmf_qual_t *qual) 3147 { 3148 struct pccbb_softc *sc = device_private(dv); 3149 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3150 bus_space_handle_t base_memh = sc->sc_base_memh; 3151 pcireg_t reg; 3152 3153 if (sc->sc_pil_intr_enable) 3154 (void)pccbbintr_function(sc); 3155 sc->sc_pil_intr_enable = false; 3156 3157 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3158 /* Disable interrupts. */ 3159 reg &= ~(CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER); 3160 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3161 /* XXX joerg Disable power to the socket? */ 3162 3163 /* XXX flush PCI write */ 3164 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3165 3166 /* reset interrupt */ 3167 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, 3168 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT)); 3169 /* XXX flush PCI write */ 3170 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3171 3172 if (sc->sc_ih != NULL) { 3173 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 3174 sc->sc_ih = NULL; 3175 } 3176 3177 return true; 3178 } 3179 3180 static bool 3181 pccbb_resume(device_t dv, const pmf_qual_t *qual) 3182 { 3183 struct pccbb_softc *sc = device_private(dv); 3184 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3185 bus_space_handle_t base_memh = sc->sc_base_memh; 3186 pcireg_t reg; 3187 3188 pccbb_chipinit(sc); 3189 pccbb_intrinit(sc); 3190 /* setup memory and io space window for CB */ 3191 pccbb_winset(0x1000, sc, sc->sc_memt); 3192 pccbb_winset(0x04, sc, sc->sc_iot); 3193 3194 /* CSC Interrupt: Card detect interrupt on */ 3195 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3196 /* Card detect intr is turned on. */ 3197 reg |= CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; 3198 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3199 /* reset interrupt */ 3200 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3201 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3202 3203 /* 3204 * check for card insertion or removal during suspend period. 3205 * XXX: the code can't cope with card swap (remove then 3206 * insert). how can we detect such situation? 3207 */ 3208 (void)pccbbintr(sc); 3209 3210 sc->sc_pil_intr_enable = true; 3211 3212 return true; 3213 } 3214
Indexes created Tue Oct 14 15:09:51 GMT 2025