pccbb.c revision 1.194
1 /* $NetBSD: pccbb.c,v 1.194 2010/02/24 22:38:01 dyoung Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: pccbb.c,v 1.194 2010/02/24 22:38:01 dyoung Exp $"); 30 31 /* 32 #define CBB_DEBUG 33 #define SHOW_REGS 34 */ 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/kernel.h> 39 #include <sys/errno.h> 40 #include <sys/ioctl.h> 41 #include <sys/reboot.h> /* for bootverbose */ 42 #include <sys/syslog.h> 43 #include <sys/device.h> 44 #include <sys/malloc.h> 45 #include <sys/proc.h> 46 47 #include <sys/intr.h> 48 #include <sys/bus.h> 49 50 #include <dev/pci/pcivar.h> 51 #include <dev/pci/pcireg.h> 52 #include <dev/pci/pcidevs.h> 53 54 #include <dev/pci/pccbbreg.h> 55 56 #include <dev/cardbus/cardslotvar.h> 57 58 #include <dev/cardbus/cardbusvar.h> 59 60 #include <dev/pcmcia/pcmciareg.h> 61 #include <dev/pcmcia/pcmciavar.h> 62 63 #include <dev/ic/i82365reg.h> 64 #include <dev/pci/pccbbvar.h> 65 66 #ifndef __NetBSD_Version__ 67 struct cfdriver cbb_cd = { 68 NULL, "cbb", DV_DULL 69 }; 70 #endif 71 72 #ifdef CBB_DEBUG 73 #define DPRINTF(x) printf x 74 #define STATIC 75 #else 76 #define DPRINTF(x) 77 #define STATIC static 78 #endif 79 80 int pccbb_burstup = 1; 81 82 /* 83 * delay_ms() is wait in milliseconds. It should be used instead 84 * of delay() if you want to wait more than 1 ms. 85 */ 86 static inline void 87 delay_ms(int millis, struct pccbb_softc *sc) 88 { 89 if (cold) 90 delay(millis * 1000); 91 else 92 kpause("pccbb", false, mstohz(millis), NULL); 93 } 94 95 int pcicbbmatch(device_t, cfdata_t, void *); 96 void pccbbattach(device_t, device_t, void *); 97 void pccbbchilddet(device_t, device_t); 98 int pccbbdetach(device_t, int); 99 int pccbbintr(void *); 100 static void pci113x_insert(void *); 101 static int pccbbintr_function(struct pccbb_softc *); 102 103 static int pccbb_detect_card(struct pccbb_softc *); 104 105 static void pccbb_pcmcia_write(struct pccbb_softc *, int, u_int8_t); 106 static u_int8_t pccbb_pcmcia_read(struct pccbb_softc *, int); 107 #define Pcic_read(sc, reg) pccbb_pcmcia_read((sc), (reg)) 108 #define Pcic_write(sc, reg, val) pccbb_pcmcia_write((sc), (reg), (val)) 109 110 STATIC int cb_reset(struct pccbb_softc *); 111 STATIC int cb_detect_voltage(struct pccbb_softc *); 112 STATIC int cbbprint(void *, const char *); 113 114 static int cb_chipset(u_int32_t, int *); 115 STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *, 116 struct pcmciabus_attach_args *); 117 118 STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int); 119 STATIC int pccbb_power(struct pccbb_softc *sc, int); 120 STATIC int pccbb_power_ct(cardbus_chipset_tag_t, int); 121 STATIC int pccbb_cardenable(struct pccbb_softc * sc, int function); 122 #if !rbus 123 static int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 124 static int pccbb_io_close(cardbus_chipset_tag_t, int); 125 static int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 126 static int pccbb_mem_close(cardbus_chipset_tag_t, int); 127 #endif /* !rbus */ 128 static void *pccbb_intr_establish(struct pccbb_softc *, 129 cardbus_intr_line_t irq, int level, int (*ih) (void *), void *sc); 130 static void pccbb_intr_disestablish(struct pccbb_softc *, void *ih); 131 132 static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t, 133 cardbus_intr_line_t irq, int level, int (*ih) (void *), void *sc); 134 static void pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih); 135 136 static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t, int, int); 137 static void pccbb_free_tag(cardbus_chipset_tag_t, cardbustag_t); 138 static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t, cardbustag_t, int); 139 static void pccbb_conf_write(cardbus_chipset_tag_t, cardbustag_t, int, 140 cardbusreg_t); 141 static void pccbb_chipinit(struct pccbb_softc *); 142 static void pccbb_intrinit(struct pccbb_softc *); 143 144 STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 145 struct pcmcia_mem_handle *); 146 STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t, 147 struct pcmcia_mem_handle *); 148 STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 149 bus_size_t, struct pcmcia_mem_handle *, bus_size_t *, int *); 150 STATIC void pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t, int); 151 STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 152 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 153 STATIC void pccbb_pcmcia_io_free(pcmcia_chipset_handle_t, 154 struct pcmcia_io_handle *); 155 STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 156 bus_size_t, struct pcmcia_io_handle *, int *); 157 STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t, int); 158 STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t, 159 struct pcmcia_function *, int, int (*)(void *), void *); 160 STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t, void *); 161 STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t); 162 STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t); 163 STATIC void pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t, int); 164 STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch); 165 166 static int pccbb_pcmcia_wait_ready(struct pccbb_softc *); 167 static void pccbb_pcmcia_delay(struct pccbb_softc *, int, const char *); 168 169 static void pccbb_pcmcia_do_io_map(struct pccbb_softc *, int); 170 static void pccbb_pcmcia_do_mem_map(struct pccbb_softc *, int); 171 172 /* bus-space allocation and deallocation functions */ 173 #if rbus 174 175 static int pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t, rbus_tag_t, 176 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 177 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp); 178 static int pccbb_rbus_cb_space_free(cardbus_chipset_tag_t, rbus_tag_t, 179 bus_space_handle_t, bus_size_t); 180 181 #endif /* rbus */ 182 183 #if rbus 184 185 static int pccbb_open_win(struct pccbb_softc *, bus_space_tag_t, 186 bus_addr_t, bus_size_t, bus_space_handle_t, int flags); 187 static int pccbb_close_win(struct pccbb_softc *, bus_space_tag_t, 188 bus_space_handle_t, bus_size_t); 189 static int pccbb_winlist_insert(struct pccbb_win_chain_head *, bus_addr_t, 190 bus_size_t, bus_space_handle_t, int); 191 static int pccbb_winlist_delete(struct pccbb_win_chain_head *, 192 bus_space_handle_t, bus_size_t); 193 static void pccbb_winset(bus_addr_t align, struct pccbb_softc *, 194 bus_space_tag_t); 195 void pccbb_winlist_show(struct pccbb_win_chain *); 196 197 #endif /* rbus */ 198 199 /* for config_defer */ 200 static void pccbb_pci_callback(device_t); 201 202 static bool pccbb_suspend(device_t, const pmf_qual_t *); 203 static bool pccbb_resume(device_t, const pmf_qual_t *); 204 205 #if defined SHOW_REGS 206 static void cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, 207 bus_space_tag_t memt, bus_space_handle_t memh); 208 #endif 209 210 CFATTACH_DECL3_NEW(cbb_pci, sizeof(struct pccbb_softc), 211 pcicbbmatch, pccbbattach, pccbbdetach, NULL, NULL, pccbbchilddet, 212 DVF_DETACH_SHUTDOWN); 213 214 static const struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 215 pccbb_pcmcia_mem_alloc, 216 pccbb_pcmcia_mem_free, 217 pccbb_pcmcia_mem_map, 218 pccbb_pcmcia_mem_unmap, 219 pccbb_pcmcia_io_alloc, 220 pccbb_pcmcia_io_free, 221 pccbb_pcmcia_io_map, 222 pccbb_pcmcia_io_unmap, 223 pccbb_pcmcia_intr_establish, 224 pccbb_pcmcia_intr_disestablish, 225 pccbb_pcmcia_socket_enable, 226 pccbb_pcmcia_socket_disable, 227 pccbb_pcmcia_socket_settype, 228 pccbb_pcmcia_card_detect 229 }; 230 231 #if rbus 232 static const struct cardbus_functions pccbb_funcs = { 233 pccbb_rbus_cb_space_alloc, 234 pccbb_rbus_cb_space_free, 235 pccbb_cb_intr_establish, 236 pccbb_cb_intr_disestablish, 237 pccbb_ctrl, 238 pccbb_power_ct, 239 pccbb_make_tag, 240 pccbb_free_tag, 241 pccbb_conf_read, 242 pccbb_conf_write, 243 }; 244 #else 245 static const struct cardbus_functions pccbb_funcs = { 246 pccbb_ctrl, 247 pccbb_power_ct, 248 pccbb_mem_open, 249 pccbb_mem_close, 250 pccbb_io_open, 251 pccbb_io_close, 252 pccbb_cb_intr_establish, 253 pccbb_cb_intr_disestablish, 254 pccbb_make_tag, 255 pccbb_conf_read, 256 pccbb_conf_write, 257 }; 258 #endif 259 260 int 261 pcicbbmatch(device_t parent, cfdata_t match, void *aux) 262 { 263 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 264 265 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 266 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 267 PCI_INTERFACE(pa->pa_class) == 0) { 268 return 1; 269 } 270 271 return 0; 272 } 273 274 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 275 | ((prod) << PCI_PRODUCT_SHIFT)) 276 277 const struct yenta_chipinfo { 278 pcireg_t yc_id; /* vendor tag | product tag */ 279 int yc_chiptype; 280 int yc_flags; 281 } yc_chipsets[] = { 282 /* Texas Instruments chips */ 283 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 284 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 285 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 286 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 287 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI125X, 288 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 289 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 290 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 291 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 292 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 293 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 294 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 295 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI125X, 296 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 297 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI125X, 298 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 299 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 300 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 301 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 302 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 303 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI1420, 304 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 305 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI125X, 306 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 307 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 308 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 309 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1520), CB_TI12XX, 310 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 311 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4410YENTA), CB_TI12XX, 312 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 313 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4520YENTA), CB_TI12XX, 314 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 315 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI7420YENTA), CB_TI12XX, 316 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 317 318 /* Ricoh chips */ 319 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 320 PCCBB_PCMCIA_MEM_32}, 321 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 322 PCCBB_PCMCIA_MEM_32}, 323 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 324 PCCBB_PCMCIA_MEM_32}, 325 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 326 PCCBB_PCMCIA_MEM_32}, 327 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 328 PCCBB_PCMCIA_MEM_32}, 329 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 330 PCCBB_PCMCIA_MEM_32}, 331 332 /* Toshiba products */ 333 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 334 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 335 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 336 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 337 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 338 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 339 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 340 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 341 342 /* Cirrus Logic products */ 343 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 344 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 345 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 346 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 347 348 /* O2 Micro products */ 349 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6729), 350 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 351 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6730), 352 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 353 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6832), 354 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 355 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6836), 356 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 357 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6872), 358 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 359 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6922), 360 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 361 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6933), 362 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 363 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6972), 364 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 365 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_7223), 366 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 367 368 /* sentinel, or Generic chip */ 369 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 370 }; 371 372 static int 373 cb_chipset(u_int32_t pci_id, int *flagp) 374 { 375 const struct yenta_chipinfo *yc; 376 377 /* Loop over except the last default entry. */ 378 for (yc = yc_chipsets; yc < yc_chipsets + 379 __arraycount(yc_chipsets) - 1; yc++) 380 if (pci_id == yc->yc_id) 381 break; 382 383 if (flagp != NULL) 384 *flagp = yc->yc_flags; 385 386 return (yc->yc_chiptype); 387 } 388 389 void 390 pccbbchilddet(device_t self, device_t child) 391 { 392 struct pccbb_softc *sc = device_private(self); 393 int s; 394 395 KASSERT(sc->sc_csc == device_private(child)); 396 397 s = splbio(); 398 if (sc->sc_csc == device_private(child)) 399 sc->sc_csc = NULL; 400 splx(s); 401 } 402 403 void 404 pccbbattach(device_t parent, device_t self, void *aux) 405 { 406 struct pccbb_softc *sc = device_private(self); 407 struct pci_attach_args *pa = aux; 408 pci_chipset_tag_t pc = pa->pa_pc; 409 pcireg_t busreg, reg, sock_base; 410 bus_addr_t sockbase; 411 char devinfo[256]; 412 int flags; 413 414 #ifdef __HAVE_PCCBB_ATTACH_HOOK 415 pccbb_attach_hook(parent, self, pa); 416 #endif 417 418 sc->sc_dev = self; 419 420 mutex_init(&sc->sc_pwr_mtx, MUTEX_DEFAULT, IPL_BIO); 421 cv_init(&sc->sc_pwr_cv, "pccpwr"); 422 423 callout_init(&sc->sc_insert_ch, 0); 424 callout_setfunc(&sc->sc_insert_ch, pci113x_insert, sc); 425 426 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 427 428 aprint_naive("\n"); 429 430 pci_devinfo(pa->pa_id, 0, 0, devinfo, sizeof(devinfo)); 431 aprint_normal(": %s (rev. 0x%02x)", devinfo, 432 PCI_REVISION(pa->pa_class)); 433 DPRINTF((" (chipflags %x)", flags)); 434 aprint_normal("\n"); 435 436 TAILQ_INIT(&sc->sc_memwindow); 437 TAILQ_INIT(&sc->sc_iowindow); 438 439 #if rbus 440 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 441 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 442 443 #if 0 444 printf("pa->pa_memt: %08x vs rbus_mem->rb_bt: %08x\n", 445 pa->pa_memt, sc->sc_rbus_memt->rb_bt); 446 #endif 447 #endif /* rbus */ 448 449 sc->sc_flags &= ~CBB_MEMHMAPPED; 450 451 /* 452 * MAP socket registers and ExCA registers on memory-space 453 * When no valid address is set on socket base registers (on pci 454 * config space), get it not polite way. 455 */ 456 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 457 458 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 459 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 460 /* The address must be valid. */ 461 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 462 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, &sc->sc_base_size)) { 463 aprint_error_dev(self, 464 "can't map socket base address 0x%lx\n", 465 (unsigned long)sock_base); 466 /* 467 * I think it's funny: socket base registers must be 468 * mapped on memory space, but ... 469 */ 470 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 471 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 472 &sc->sc_base_size)) { 473 aprint_error_dev(self, 474 "can't map socket base address" 475 " 0x%lx: io mode\n", 476 (unsigned long)sockbase); 477 /* give up... allocate reg space via rbus. */ 478 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 479 } else 480 sc->sc_flags |= CBB_MEMHMAPPED; 481 } else { 482 DPRINTF(("%s: socket base address 0x%lx\n", 483 device_xname(self), 484 (unsigned long)sockbase)); 485 sc->sc_flags |= CBB_MEMHMAPPED; 486 } 487 } 488 489 sc->sc_mem_start = 0; /* XXX */ 490 sc->sc_mem_end = 0xffffffff; /* XXX */ 491 492 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 493 494 /* pccbb_machdep.c end */ 495 496 #if defined CBB_DEBUG 497 { 498 static const char *intrname[] = { "NON", "A", "B", "C", "D" }; 499 aprint_debug_dev(self, "intrpin %s, intrtag %d\n", 500 intrname[pa->pa_intrpin], pa->pa_intrline); 501 } 502 #endif 503 504 /* setup softc */ 505 sc->sc_pc = pc; 506 sc->sc_iot = pa->pa_iot; 507 sc->sc_memt = pa->pa_memt; 508 sc->sc_dmat = pa->pa_dmat; 509 sc->sc_tag = pa->pa_tag; 510 511 memcpy(&sc->sc_pa, pa, sizeof(*pa)); 512 513 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 514 515 /* Disable legacy register mapping. */ 516 switch (sc->sc_chipset) { 517 case CB_RX5C46X: /* fallthrough */ 518 #if 0 519 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 520 case CB_RX5C47X: 521 #endif 522 /* 523 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 524 * cannot be disabled by substituting 0 into PCI_LEGACY 525 * register. Ricoh CardBus bridges have special bits on Bridge 526 * control reg (addr 0x3e on PCI config space). 527 */ 528 reg = pci_conf_read(pc, pa->pa_tag, PCI_BRIDGE_CONTROL_REG); 529 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 530 pci_conf_write(pc, pa->pa_tag, PCI_BRIDGE_CONTROL_REG, reg); 531 break; 532 533 default: 534 /* XXX I don't know proper way to kill legacy I/O. */ 535 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 536 break; 537 } 538 539 if (!pmf_device_register(self, pccbb_suspend, pccbb_resume)) 540 aprint_error_dev(self, "couldn't establish power handler\n"); 541 542 config_defer(self, pccbb_pci_callback); 543 } 544 545 int 546 pccbbdetach(device_t self, int flags) 547 { 548 struct pccbb_softc *sc = device_private(self); 549 pci_chipset_tag_t pc = sc->sc_pa.pa_pc; 550 bus_space_tag_t bmt = sc->sc_base_memt; 551 bus_space_handle_t bmh = sc->sc_base_memh; 552 uint32_t sockmask; 553 int rc; 554 555 if ((rc = config_detach_children(self, flags)) != 0) 556 return rc; 557 558 if (!LIST_EMPTY(&sc->sc_pil)) { 559 panic("%s: interrupt handlers still registered", 560 device_xname(self)); 561 return EBUSY; 562 } 563 564 if (sc->sc_ih != NULL) { 565 pci_intr_disestablish(pc, sc->sc_ih); 566 sc->sc_ih = NULL; 567 } 568 569 /* CSC Interrupt: turn off card detect and power cycle interrupts */ 570 sockmask = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 571 sockmask &= ~(CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | 572 CB_SOCKET_MASK_POWER); 573 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, sockmask); 574 /* reset interrupt */ 575 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 576 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 577 578 switch (sc->sc_flags & (CBB_MEMHMAPPED|CBB_SPECMAPPED)) { 579 case CBB_MEMHMAPPED: 580 bus_space_unmap(bmt, bmh, sc->sc_base_size); 581 break; 582 case CBB_MEMHMAPPED|CBB_SPECMAPPED: 583 #if rbus 584 { 585 pcireg_t sockbase; 586 587 sockbase = pci_conf_read(pc, sc->sc_tag, PCI_SOCKBASE); 588 rbus_space_free(sc->sc_rbus_memt, bmh, 0x1000, 589 NULL); 590 } 591 #else 592 bus_space_free(bmt, bmh, 0x1000); 593 #endif 594 } 595 sc->sc_flags &= ~(CBB_MEMHMAPPED|CBB_SPECMAPPED); 596 597 if (!TAILQ_EMPTY(&sc->sc_iowindow)) 598 aprint_error_dev(self, "i/o windows not empty"); 599 if (!TAILQ_EMPTY(&sc->sc_memwindow)) 600 aprint_error_dev(self, "memory windows not empty"); 601 602 callout_stop(&sc->sc_insert_ch); 603 callout_destroy(&sc->sc_insert_ch); 604 605 mutex_destroy(&sc->sc_pwr_mtx); 606 cv_destroy(&sc->sc_pwr_cv); 607 608 return 0; 609 } 610 611 /* 612 * static void pccbb_pci_callback(device_t self) 613 * 614 * The actual attach routine: get memory space for YENTA register 615 * space, setup YENTA register and route interrupt. 616 * 617 * This function should be deferred because this device may obtain 618 * memory space dynamically. This function must avoid obtaining 619 * memory area which has already kept for another device. 620 */ 621 static void 622 pccbb_pci_callback(device_t self) 623 { 624 struct pccbb_softc *sc = device_private(self); 625 pci_chipset_tag_t pc = sc->sc_pc; 626 bus_addr_t sockbase; 627 struct cbslot_attach_args cba; 628 struct pcmciabus_attach_args paa; 629 struct cardslot_attach_args caa; 630 device_t csc; 631 632 if (!(sc->sc_flags & CBB_MEMHMAPPED)) { 633 /* The socket registers aren't mapped correctly. */ 634 #if rbus 635 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 636 (sc->sc_chipset == CB_RX5C47X 637 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 638 0, &sockbase, &sc->sc_base_memh)) { 639 return; 640 } 641 sc->sc_base_memt = sc->sc_memt; 642 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 643 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 644 device_xname(self), (unsigned long)sockbase, 645 (unsigned long)pci_conf_read(pc, sc->sc_tag, 646 PCI_SOCKBASE))); 647 #else 648 sc->sc_base_memt = sc->sc_memt; 649 #if !defined CBB_PCI_BASE 650 #define CBB_PCI_BASE 0x20000000 651 #endif 652 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 653 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 654 /* cannot allocate memory space */ 655 return; 656 } 657 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 658 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 659 device_xname(self), (unsigned long)sock_base, 660 (unsigned long)pci_conf_read(pc, 661 sc->sc_tag, PCI_SOCKBASE))); 662 #endif 663 sc->sc_flags |= CBB_MEMHMAPPED|CBB_SPECMAPPED; 664 } 665 666 /* clear data structure for child device interrupt handlers */ 667 LIST_INIT(&sc->sc_pil); 668 669 /* bus bridge initialization */ 670 pccbb_chipinit(sc); 671 672 sc->sc_pil_intr_enable = 1; 673 674 { 675 u_int32_t sockstat; 676 677 sockstat = bus_space_read_4(sc->sc_base_memt, 678 sc->sc_base_memh, CB_SOCKET_STAT); 679 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 680 sc->sc_flags |= CBB_CARDEXIST; 681 } 682 } 683 684 /* 685 * attach cardbus 686 */ 687 { 688 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 689 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 690 691 /* initialize cbslot_attach */ 692 cba.cba_iot = sc->sc_iot; 693 cba.cba_memt = sc->sc_memt; 694 cba.cba_dmat = sc->sc_dmat; 695 cba.cba_bus = (busreg >> 8) & 0x0ff; 696 cba.cba_cc = (void *)sc; 697 cba.cba_cf = &pccbb_funcs; 698 cba.cba_intrline = 0; /* XXX dummy */ 699 700 #if rbus 701 cba.cba_rbus_iot = sc->sc_rbus_iot; 702 cba.cba_rbus_memt = sc->sc_rbus_memt; 703 #endif 704 705 cba.cba_cacheline = PCI_CACHELINE(bhlc); 706 cba.cba_max_lattimer = PCI_LATTIMER(bhlc); 707 708 aprint_verbose_dev(self, 709 "cacheline 0x%x lattimer 0x%x\n", 710 cba.cba_cacheline, 711 cba.cba_max_lattimer); 712 aprint_verbose_dev(self, "bhlc 0x%x\n", bhlc); 713 #if defined SHOW_REGS 714 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 715 sc->sc_base_memh); 716 #endif 717 } 718 719 pccbb_pcmcia_attach_setup(sc, &paa); 720 caa.caa_cb_attach = NULL; 721 if (cba.cba_bus == 0) 722 aprint_error_dev(self, 723 "secondary bus number uninitialized; try PCI_BUS_FIXUP\n"); 724 else 725 caa.caa_cb_attach = &cba; 726 caa.caa_16_attach = &paa; 727 728 pccbb_intrinit(sc); 729 730 if (NULL != (csc = config_found_ia(self, "pcmciaslot", &caa, 731 cbbprint))) { 732 DPRINTF(("%s: found cardslot\n", __func__)); 733 sc->sc_csc = device_private(csc); 734 } 735 736 return; 737 } 738 739 740 741 742 743 /* 744 * static void pccbb_chipinit(struct pccbb_softc *sc) 745 * 746 * This function initialize YENTA chip registers listed below: 747 * 1) PCI command reg, 748 * 2) PCI and CardBus latency timer, 749 * 3) route PCI interrupt, 750 * 4) close all memory and io windows. 751 * 5) turn off bus power. 752 * 6) card detect and power cycle interrupts on. 753 * 7) clear interrupt 754 */ 755 static void 756 pccbb_chipinit(struct pccbb_softc *sc) 757 { 758 pci_chipset_tag_t pc = sc->sc_pc; 759 pcitag_t tag = sc->sc_tag; 760 bus_space_tag_t bmt = sc->sc_base_memt; 761 bus_space_handle_t bmh = sc->sc_base_memh; 762 pcireg_t bcr, bhlc, cbctl, csr, lscp, mfunc, mrburst, slotctl, sockctl, 763 sysctrl; 764 765 /* 766 * Set PCI command reg. 767 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 768 */ 769 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 770 /* I believe it is harmless. */ 771 csr |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 772 PCI_COMMAND_MASTER_ENABLE); 773 774 /* All O2 Micro chips have broken parity-error reporting 775 * until proven otherwise. The OZ6933 PCI-CardBus Bridge 776 * is known to have the defect---see PR kern/38698. 777 */ 778 if (sc->sc_chipset != CB_O2MICRO) 779 csr |= PCI_COMMAND_PARITY_ENABLE; 780 781 csr |= PCI_COMMAND_SERR_ENABLE; 782 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 783 784 /* 785 * Set CardBus latency timer. 786 */ 787 lscp = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 788 if (PCI_CB_LATENCY(lscp) < 0x20) { 789 lscp &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 790 lscp |= (0x20 << PCI_CB_LATENCY_SHIFT); 791 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, lscp); 792 } 793 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 794 PCI_CB_LATENCY(lscp), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 795 796 /* 797 * Set PCI latency timer. 798 */ 799 bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG); 800 if (PCI_LATTIMER(bhlc) < 0x10) { 801 bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 802 bhlc |= (0x10 << PCI_LATTIMER_SHIFT); 803 pci_conf_write(pc, tag, PCI_BHLC_REG, bhlc); 804 } 805 DPRINTF(("PCI latency timer 0x%x (%x)\n", 806 PCI_LATTIMER(bhlc), pci_conf_read(pc, tag, PCI_BHLC_REG))); 807 808 809 /* Route functional interrupts to PCI. */ 810 bcr = pci_conf_read(pc, tag, PCI_BRIDGE_CONTROL_REG); 811 bcr |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 812 bcr |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 813 /* assert reset */ 814 bcr |= PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT; 815 /* Set master abort mode to 1, forward SERR# from secondary 816 * to primary, and detect parity errors on secondary. 817 */ 818 bcr |= PCI_BRIDGE_CONTROL_MABRT << PCI_BRIDGE_CONTROL_SHIFT; 819 bcr |= PCI_BRIDGE_CONTROL_SERR << PCI_BRIDGE_CONTROL_SHIFT; 820 bcr |= PCI_BRIDGE_CONTROL_PERE << PCI_BRIDGE_CONTROL_SHIFT; 821 pci_conf_write(pc, tag, PCI_BRIDGE_CONTROL_REG, bcr); 822 823 switch (sc->sc_chipset) { 824 case CB_TI113X: 825 cbctl = pci_conf_read(pc, tag, PCI_CBCTRL); 826 /* This bit is shared, but may read as 0 on some chips, so set 827 it explicitly on both functions. */ 828 cbctl |= PCI113X_CBCTRL_PCI_IRQ_ENA; 829 /* CSC intr enable */ 830 cbctl |= PCI113X_CBCTRL_PCI_CSC; 831 /* functional intr prohibit | prohibit ISA routing */ 832 cbctl &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 833 pci_conf_write(pc, tag, PCI_CBCTRL, cbctl); 834 break; 835 836 case CB_TI1420: 837 sysctrl = pci_conf_read(pc, tag, PCI_SYSCTRL); 838 mrburst = pccbb_burstup 839 ? PCI1420_SYSCTRL_MRBURST : PCI1420_SYSCTRL_MRBURSTDN; 840 if ((sysctrl & PCI1420_SYSCTRL_MRBURST) == mrburst) { 841 printf("%s: %swrite bursts enabled\n", 842 device_xname(sc->sc_dev), 843 pccbb_burstup ? "read/" : ""); 844 } else if (pccbb_burstup) { 845 printf("%s: enabling read/write bursts\n", 846 device_xname(sc->sc_dev)); 847 sysctrl |= PCI1420_SYSCTRL_MRBURST; 848 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 849 } else { 850 printf("%s: disabling read bursts, " 851 "enabling write bursts\n", 852 device_xname(sc->sc_dev)); 853 sysctrl |= PCI1420_SYSCTRL_MRBURSTDN; 854 sysctrl &= ~PCI1420_SYSCTRL_MRBURSTUP; 855 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 856 } 857 /*FALLTHROUGH*/ 858 case CB_TI12XX: 859 /* 860 * Some TI 12xx (and [14][45]xx) based pci cards 861 * sometimes have issues with the MFUNC register not 862 * being initialized due to a bad EEPROM on board. 863 * Laptops that this matters on have this register 864 * properly initialized. 865 * 866 * The TI125X parts have a different register. 867 */ 868 mfunc = pci_conf_read(pc, tag, PCI12XX_MFUNC); 869 if (mfunc == 0) { 870 mfunc &= ~PCI12XX_MFUNC_PIN0; 871 mfunc |= PCI12XX_MFUNC_PIN0_INTA; 872 if ((pci_conf_read(pc, tag, PCI_SYSCTRL) & 873 PCI12XX_SYSCTRL_INTRTIE) == 0) { 874 mfunc &= ~PCI12XX_MFUNC_PIN1; 875 mfunc |= PCI12XX_MFUNC_PIN1_INTB; 876 } 877 pci_conf_write(pc, tag, PCI12XX_MFUNC, mfunc); 878 } 879 /* fallthrough */ 880 881 case CB_TI125X: 882 /* 883 * Disable zoom video. Some machines initialize this 884 * improperly and experience has shown that this helps 885 * prevent strange behavior. 886 */ 887 pci_conf_write(pc, tag, PCI12XX_MMCTRL, 0); 888 889 sysctrl = pci_conf_read(pc, tag, PCI_SYSCTRL); 890 sysctrl |= PCI12XX_SYSCTRL_VCCPROT; 891 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 892 cbctl = pci_conf_read(pc, tag, PCI_CBCTRL); 893 cbctl |= PCI12XX_CBCTRL_CSC; 894 pci_conf_write(pc, tag, PCI_CBCTRL, cbctl); 895 break; 896 897 case CB_TOPIC95B: 898 sockctl = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 899 sockctl |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 900 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, sockctl); 901 slotctl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 902 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 903 device_xname(sc->sc_dev), slotctl)); 904 slotctl |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 905 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 906 slotctl &= ~TOPIC_SLOT_CTRL_SWDETECT; 907 DPRINTF(("0x%x\n", slotctl)); 908 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slotctl); 909 break; 910 911 case CB_TOPIC97: 912 slotctl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 913 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 914 device_xname(sc->sc_dev), slotctl)); 915 slotctl |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 916 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 917 slotctl &= ~TOPIC_SLOT_CTRL_SWDETECT; 918 slotctl |= TOPIC97_SLOT_CTRL_PCIINT; 919 slotctl &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 920 DPRINTF(("0x%x\n", slotctl)); 921 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slotctl); 922 /* make sure to assert LV card support bits */ 923 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 924 0x800 + 0x3e, 925 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 926 0x800 + 0x3e) | 0x03); 927 break; 928 } 929 930 /* Close all memory and I/O windows. */ 931 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 932 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 933 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 934 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 935 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 936 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 937 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 938 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 939 940 /* reset 16-bit pcmcia bus */ 941 bus_space_write_1(bmt, bmh, 0x800 + PCIC_INTR, 942 bus_space_read_1(bmt, bmh, 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 943 944 /* turn off power */ 945 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 946 } 947 948 static void 949 pccbb_intrinit(struct pccbb_softc *sc) 950 { 951 pcireg_t sockmask; 952 const char *intrstr = NULL; 953 pci_intr_handle_t ih; 954 pci_chipset_tag_t pc = sc->sc_pc; 955 bus_space_tag_t bmt = sc->sc_base_memt; 956 bus_space_handle_t bmh = sc->sc_base_memh; 957 958 /* Map and establish the interrupt. */ 959 if (pci_intr_map(&sc->sc_pa, &ih)) { 960 aprint_error_dev(sc->sc_dev, "couldn't map interrupt\n"); 961 return; 962 } 963 intrstr = pci_intr_string(pc, ih); 964 965 /* 966 * XXX pccbbintr should be called under the priority lower 967 * than any other hard interrupts. 968 */ 969 KASSERT(sc->sc_ih == NULL); 970 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 971 972 if (sc->sc_ih == NULL) { 973 aprint_error_dev(sc->sc_dev, "couldn't establish interrupt"); 974 if (intrstr != NULL) 975 aprint_error(" at %s\n", intrstr); 976 else 977 aprint_error("\n"); 978 return; 979 } 980 981 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 982 983 /* CSC Interrupt: Card detect and power cycle interrupts on */ 984 sockmask = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 985 sockmask |= CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | 986 CB_SOCKET_MASK_POWER; 987 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, sockmask); 988 /* reset interrupt */ 989 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 990 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 991 } 992 993 /* 994 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 995 * struct pcmciabus_attach_args *paa) 996 * 997 * This function attaches 16-bit PCcard bus. 998 */ 999 STATIC void 1000 pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 1001 struct pcmciabus_attach_args *paa) 1002 { 1003 #if rbus 1004 rbus_tag_t rb; 1005 #endif 1006 /* 1007 * We need to do a few things here: 1008 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 1009 * setting the IRQ numbers to 0. 1010 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 1011 * routing of CSC interrupts (e.g. card removal) to PCI while in 1012 * PCMCIA mode. We just leave this set all the time. 1013 * 3) Enable card insertion/removal interrupts in case the chip also 1014 * needs that while in PCMCIA mode. 1015 * 4) Clear any pending CSC interrupt. 1016 */ 1017 Pcic_write(sc, PCIC_INTR, PCIC_INTR_ENABLE); 1018 if (sc->sc_chipset == CB_TI113X) { 1019 Pcic_write(sc, PCIC_CSC_INTR, 0); 1020 } else { 1021 Pcic_write(sc, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 1022 Pcic_read(sc, PCIC_CSC); 1023 } 1024 1025 /* initialize pcmcia bus attachment */ 1026 paa->paa_busname = "pcmcia"; 1027 paa->pct = &pccbb_pcmcia_funcs; 1028 paa->pch = sc; 1029 paa->iobase = 0; /* I don't use them */ 1030 paa->iosize = 0; 1031 #if rbus 1032 rb = sc->sc_rbus_iot; 1033 paa->iobase = rb->rb_start + rb->rb_offset; 1034 paa->iosize = rb->rb_end - rb->rb_start; 1035 #endif 1036 1037 return; 1038 } 1039 1040 /* 1041 * int pccbbintr(arg) 1042 * void *arg; 1043 * This routine handles the interrupt from Yenta PCI-CardBus bridge 1044 * itself. 1045 */ 1046 int 1047 pccbbintr(void *arg) 1048 { 1049 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1050 struct cardslot_softc *csc; 1051 u_int32_t sockevent, sockstate; 1052 bus_space_tag_t memt = sc->sc_base_memt; 1053 bus_space_handle_t memh = sc->sc_base_memh; 1054 1055 if (!device_has_power(sc->sc_dev)) 1056 return 0; 1057 1058 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 1059 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 1060 Pcic_read(sc, PCIC_CSC); 1061 1062 if (sockevent != 0) { 1063 aprint_debug("%s: enter sockevent %" PRIx32 "\n", __func__, 1064 sockevent); 1065 } 1066 1067 /* XXX sockevent == CB_SOCKET_EVENT_CSTS|CB_SOCKET_EVENT_POWER 1068 * does occur in the wild. Check for a _POWER event before 1069 * possibly exiting because of an _CSTS event. 1070 */ 1071 if (sockevent & CB_SOCKET_EVENT_POWER) { 1072 DPRINTF(("Powercycling because of socket event\n")); 1073 /* XXX: Does not happen when attaching a 16-bit card */ 1074 mutex_enter(&sc->sc_pwr_mtx); 1075 sc->sc_pwrcycle++; 1076 cv_signal(&sc->sc_pwr_cv); 1077 mutex_exit(&sc->sc_pwr_mtx); 1078 } 1079 1080 /* Sometimes a change of CSTSCHG# accompanies the first 1081 * interrupt from an Atheros WLAN. That generates a 1082 * CB_SOCKET_EVENT_CSTS event on the bridge. The event 1083 * isn't interesting to pccbb(4), so we used to ignore the 1084 * interrupt. Now, let the child devices try to handle 1085 * the interrupt, instead. The Atheros NIC produces 1086 * interrupts more reliably, now: used to be that it would 1087 * only interrupt if the driver avoided powering down the 1088 * NIC's cardslot, and then the NIC would only work after 1089 * it was reset a second time. 1090 */ 1091 if (sockevent == 0 || 1092 (sockevent & ~(CB_SOCKET_EVENT_POWER|CB_SOCKET_EVENT_CD)) != 0) { 1093 /* This intr is not for me: it may be for my child devices. */ 1094 if (sc->sc_pil_intr_enable) { 1095 return pccbbintr_function(sc); 1096 } else { 1097 return 0; 1098 } 1099 } 1100 1101 if (sockevent & CB_SOCKET_EVENT_CD) { 1102 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1103 if (0x00 != (sockstate & CB_SOCKET_STAT_CD)) { 1104 /* A card should be removed. */ 1105 if (sc->sc_flags & CBB_CARDEXIST) { 1106 DPRINTF(("%s: 0x%08x", 1107 device_xname(sc->sc_dev), sockevent)); 1108 DPRINTF((" card removed, 0x%08x\n", sockstate)); 1109 sc->sc_flags &= ~CBB_CARDEXIST; 1110 if ((csc = sc->sc_csc) == NULL) 1111 ; 1112 else if (csc->sc_status & 1113 CARDSLOT_STATUS_CARD_16) { 1114 cardslot_event_throw(csc, 1115 CARDSLOT_EVENT_REMOVAL_16); 1116 } else if (csc->sc_status & 1117 CARDSLOT_STATUS_CARD_CB) { 1118 /* Cardbus intr removed */ 1119 cardslot_event_throw(csc, 1120 CARDSLOT_EVENT_REMOVAL_CB); 1121 } 1122 } else if (sc->sc_flags & CBB_INSERTING) { 1123 sc->sc_flags &= ~CBB_INSERTING; 1124 callout_stop(&sc->sc_insert_ch); 1125 } 1126 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 1127 /* 1128 * The pccbbintr may called from powerdown hook when 1129 * the system resumed, to detect the card 1130 * insertion/removal during suspension. 1131 */ 1132 (sc->sc_flags & CBB_CARDEXIST) == 0) { 1133 if (sc->sc_flags & CBB_INSERTING) { 1134 callout_stop(&sc->sc_insert_ch); 1135 } 1136 callout_schedule(&sc->sc_insert_ch, mstohz(200)); 1137 sc->sc_flags |= CBB_INSERTING; 1138 } 1139 } 1140 1141 return (1); 1142 } 1143 1144 /* 1145 * static int pccbbintr_function(struct pccbb_softc *sc) 1146 * 1147 * This function calls each interrupt handler registered at the 1148 * bridge. The interrupt handlers are called in registered order. 1149 */ 1150 static int 1151 pccbbintr_function(struct pccbb_softc *sc) 1152 { 1153 int retval = 0, val; 1154 struct pccbb_intrhand_list *pil; 1155 int s; 1156 1157 LIST_FOREACH(pil, &sc->sc_pil, pil_next) { 1158 s = splraiseipl(pil->pil_icookie); 1159 val = (*pil->pil_func)(pil->pil_arg); 1160 splx(s); 1161 1162 retval = retval == 1 ? 1 : 1163 retval == 0 ? val : val != 0 ? val : retval; 1164 } 1165 1166 return retval; 1167 } 1168 1169 static void 1170 pci113x_insert(void *arg) 1171 { 1172 struct pccbb_softc *sc = arg; 1173 struct cardslot_softc *csc; 1174 u_int32_t sockevent, sockstate; 1175 1176 if (!(sc->sc_flags & CBB_INSERTING)) { 1177 /* We add a card only under inserting state. */ 1178 return; 1179 } 1180 sc->sc_flags &= ~CBB_INSERTING; 1181 1182 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1183 CB_SOCKET_EVENT); 1184 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1185 CB_SOCKET_STAT); 1186 1187 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1188 DPRINTF(("%s: 0x%08x", device_xname(sc->sc_dev), sockevent)); 1189 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1190 sc->sc_flags |= CBB_CARDEXIST; 1191 /* call pccard interrupt handler here */ 1192 if ((csc = sc->sc_csc) == NULL) 1193 ; 1194 else if (sockstate & CB_SOCKET_STAT_16BIT) { 1195 /* 16-bit card found */ 1196 cardslot_event_throw(csc, CARDSLOT_EVENT_INSERTION_16); 1197 } else if (sockstate & CB_SOCKET_STAT_CB) { 1198 /* cardbus card found */ 1199 cardslot_event_throw(csc, CARDSLOT_EVENT_INSERTION_CB); 1200 } else { 1201 /* who are you? */ 1202 } 1203 } else { 1204 callout_schedule(&sc->sc_insert_ch, mstohz(100)); 1205 } 1206 } 1207 1208 #define PCCBB_PCMCIA_OFFSET 0x800 1209 static u_int8_t 1210 pccbb_pcmcia_read(struct pccbb_softc *sc, int reg) 1211 { 1212 bus_space_barrier(sc->sc_base_memt, sc->sc_base_memh, 1213 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1214 1215 return bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 1216 PCCBB_PCMCIA_OFFSET + reg); 1217 } 1218 1219 static void 1220 pccbb_pcmcia_write(struct pccbb_softc *sc, int reg, u_int8_t val) 1221 { 1222 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 1223 PCCBB_PCMCIA_OFFSET + reg, val); 1224 1225 bus_space_barrier(sc->sc_base_memt, sc->sc_base_memh, 1226 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1227 } 1228 1229 /* 1230 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1231 */ 1232 STATIC int 1233 pccbb_ctrl(cardbus_chipset_tag_t ct, int command) 1234 { 1235 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1236 1237 switch (command) { 1238 case CARDBUS_CD: 1239 if (2 == pccbb_detect_card(sc)) { 1240 int retval = 0; 1241 int status = cb_detect_voltage(sc); 1242 if (PCCARD_VCC_5V & status) { 1243 retval |= CARDBUS_5V_CARD; 1244 } 1245 if (PCCARD_VCC_3V & status) { 1246 retval |= CARDBUS_3V_CARD; 1247 } 1248 if (PCCARD_VCC_XV & status) { 1249 retval |= CARDBUS_XV_CARD; 1250 } 1251 if (PCCARD_VCC_YV & status) { 1252 retval |= CARDBUS_YV_CARD; 1253 } 1254 return retval; 1255 } else { 1256 return 0; 1257 } 1258 case CARDBUS_RESET: 1259 return cb_reset(sc); 1260 case CARDBUS_IO_ENABLE: /* fallthrough */ 1261 case CARDBUS_IO_DISABLE: /* fallthrough */ 1262 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1263 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1264 case CARDBUS_BM_ENABLE: /* fallthrough */ 1265 case CARDBUS_BM_DISABLE: /* fallthrough */ 1266 /* XXX: I think we don't need to call this function below. */ 1267 return pccbb_cardenable(sc, command); 1268 } 1269 1270 return 0; 1271 } 1272 1273 STATIC int 1274 pccbb_power_ct(cardbus_chipset_tag_t ct, int command) 1275 { 1276 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1277 1278 return pccbb_power(sc, command); 1279 } 1280 1281 /* 1282 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1283 * This function returns true when it succeeds and returns false when 1284 * it fails. 1285 */ 1286 STATIC int 1287 pccbb_power(struct pccbb_softc *sc, int command) 1288 { 1289 u_int32_t status, osock_ctrl, sock_ctrl, reg_ctrl; 1290 bus_space_tag_t memt = sc->sc_base_memt; 1291 bus_space_handle_t memh = sc->sc_base_memh; 1292 int on = 0, pwrcycle, times; 1293 struct timeval before, after, diff; 1294 1295 DPRINTF(("pccbb_power: %s and %s [0x%x]\n", 1296 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1297 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1298 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1299 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1300 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1301 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1302 "UNKNOWN", 1303 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1304 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1305 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1306 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1307 "UNKNOWN", command)); 1308 1309 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1310 osock_ctrl = sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1311 1312 switch (command & CARDBUS_VCCMASK) { 1313 case CARDBUS_VCC_UC: 1314 break; 1315 case CARDBUS_VCC_5V: 1316 on++; 1317 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1318 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1319 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1320 } else { 1321 aprint_error_dev(sc->sc_dev, 1322 "BAD voltage request: no 5 V card\n"); 1323 return 0; 1324 } 1325 break; 1326 case CARDBUS_VCC_3V: 1327 on++; 1328 if (CB_SOCKET_STAT_3VCARD & status) { 1329 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1330 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1331 } else { 1332 aprint_error_dev(sc->sc_dev, 1333 "BAD voltage request: no 3.3 V card\n"); 1334 return 0; 1335 } 1336 break; 1337 case CARDBUS_VCC_0V: 1338 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1339 break; 1340 default: 1341 return 0; /* power NEVER changed */ 1342 } 1343 1344 switch (command & CARDBUS_VPPMASK) { 1345 case CARDBUS_VPP_UC: 1346 break; 1347 case CARDBUS_VPP_0V: 1348 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1349 break; 1350 case CARDBUS_VPP_VCC: 1351 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1352 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1353 break; 1354 case CARDBUS_VPP_12V: 1355 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1356 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1357 break; 1358 } 1359 aprint_debug_dev(sc->sc_dev, "osock_ctrl %#" PRIx32 1360 " sock_ctrl %#" PRIx32 "\n", osock_ctrl, sock_ctrl); 1361 1362 microtime(&before); 1363 mutex_enter(&sc->sc_pwr_mtx); 1364 pwrcycle = sc->sc_pwrcycle; 1365 1366 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1367 1368 /* 1369 * Wait as long as 200ms for a power-cycle interrupt. If 1370 * interrupts are enabled, but the socket has already 1371 * changed to the desired status, keep waiting for the 1372 * interrupt. "Consuming" the interrupt in this way keeps 1373 * the interrupt from prematurely waking some subsequent 1374 * pccbb_power call. 1375 * 1376 * XXX Not every bridge interrupts on the ->OFF transition. 1377 * XXX That's ok, we will time-out after 200ms. 1378 * 1379 * XXX The power cycle event will never happen when attaching 1380 * XXX a 16-bit card. That's ok, we will time-out after 1381 * XXX 200ms. 1382 */ 1383 for (times = 5; --times >= 0; ) { 1384 if (cold) 1385 DELAY(40 * 1000); 1386 else { 1387 (void)cv_timedwait(&sc->sc_pwr_cv, &sc->sc_pwr_mtx, 1388 mstohz(40)); 1389 if (pwrcycle == sc->sc_pwrcycle) 1390 continue; 1391 } 1392 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1393 if ((status & CB_SOCKET_STAT_PWRCYCLE) != 0 && on) 1394 break; 1395 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0 && !on) 1396 break; 1397 } 1398 mutex_exit(&sc->sc_pwr_mtx); 1399 microtime(&after); 1400 timersub(&after, &before, &diff); 1401 aprint_debug_dev(sc->sc_dev, "wait took%s %lld.%06lds\n", 1402 (on && times < 0) ? " too long" : "", (long long)diff.tv_sec, 1403 (long)diff.tv_usec); 1404 1405 /* 1406 * Ok, wait a bit longer for things to settle. 1407 */ 1408 if (on && sc->sc_chipset == CB_TOPIC95B) 1409 delay_ms(100, sc); 1410 1411 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1412 1413 if (on && sc->sc_chipset != CB_TOPIC95B) { 1414 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0) 1415 aprint_error_dev(sc->sc_dev, "power on failed?\n"); 1416 } 1417 1418 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1419 aprint_error_dev(sc->sc_dev, 1420 "bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1421 sock_ctrl, status); 1422 aprint_error_dev(sc->sc_dev, "disabling socket\n"); 1423 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1424 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1425 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1426 status &= ~CB_SOCKET_STAT_BADVCC; 1427 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, status); 1428 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1429 CB_SOCKET_STAT)); 1430 return 0; 1431 } 1432 1433 if (sc->sc_chipset == CB_TOPIC97) { 1434 reg_ctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL); 1435 reg_ctrl &= ~TOPIC97_REG_CTRL_TESTMODE; 1436 if ((command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V) 1437 reg_ctrl &= ~TOPIC97_REG_CTRL_CLKRUN_ENA; 1438 else 1439 reg_ctrl |= TOPIC97_REG_CTRL_CLKRUN_ENA; 1440 pci_conf_write(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL, reg_ctrl); 1441 } 1442 1443 return 1; /* power changed correctly */ 1444 } 1445 1446 /* 1447 * static int pccbb_detect_card(struct pccbb_softc *sc) 1448 * return value: 0 if no card exists. 1449 * 1 if 16-bit card exists. 1450 * 2 if cardbus card exists. 1451 */ 1452 static int 1453 pccbb_detect_card(struct pccbb_softc *sc) 1454 { 1455 bus_space_handle_t base_memh = sc->sc_base_memh; 1456 bus_space_tag_t base_memt = sc->sc_base_memt; 1457 u_int32_t sockstat = 1458 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1459 int retval = 0; 1460 1461 /* CD1 and CD2 asserted */ 1462 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1463 /* card must be present */ 1464 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1465 /* NOTACARD DEASSERTED */ 1466 if (CB_SOCKET_STAT_CB & sockstat) { 1467 /* CardBus mode */ 1468 retval = 2; 1469 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1470 /* 16-bit mode */ 1471 retval = 1; 1472 } 1473 } 1474 } 1475 return retval; 1476 } 1477 1478 /* 1479 * STATIC int cb_reset(struct pccbb_softc *sc) 1480 * This function resets CardBus card. 1481 */ 1482 STATIC int 1483 cb_reset(struct pccbb_softc *sc) 1484 { 1485 /* 1486 * Reset Assert at least 20 ms 1487 * Some machines request longer duration. 1488 */ 1489 int reset_duration = 1490 (sc->sc_chipset == CB_RX5C47X ? 400 : 50); 1491 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1492 aprint_debug("%s: enter bcr %" PRIx32 "\n", __func__, bcr); 1493 1494 /* Reset bit Assert (bit 6 at 0x3E) */ 1495 bcr |= PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT; 1496 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr); 1497 aprint_debug("%s: wrote bcr %" PRIx32 "\n", __func__, bcr); 1498 delay_ms(reset_duration, sc); 1499 1500 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1501 /* Reset bit Deassert (bit 6 at 0x3E) */ 1502 bcr &= ~(PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT); 1503 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, 1504 bcr); 1505 aprint_debug("%s: wrote bcr %" PRIx32 "\n", __func__, bcr); 1506 delay_ms(reset_duration, sc); 1507 aprint_debug("%s: end of delay\n", __func__); 1508 } 1509 /* No card found on the slot. Keep Reset. */ 1510 return 1; 1511 } 1512 1513 /* 1514 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1515 * This function detect card Voltage. 1516 */ 1517 STATIC int 1518 cb_detect_voltage(struct pccbb_softc *sc) 1519 { 1520 u_int32_t psr; /* socket present-state reg */ 1521 bus_space_tag_t iot = sc->sc_base_memt; 1522 bus_space_handle_t ioh = sc->sc_base_memh; 1523 int vol = PCCARD_VCC_UKN; /* set 0 */ 1524 1525 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1526 1527 if (0x400u & psr) { 1528 vol |= PCCARD_VCC_5V; 1529 } 1530 if (0x800u & psr) { 1531 vol |= PCCARD_VCC_3V; 1532 } 1533 1534 return vol; 1535 } 1536 1537 STATIC int 1538 cbbprint(void *aux, const char *pcic) 1539 { 1540 #if 0 1541 struct cbslot_attach_args *cba = aux; 1542 1543 if (cba->cba_slot >= 0) { 1544 aprint_normal(" slot %d", cba->cba_slot); 1545 } 1546 #endif 1547 return UNCONF; 1548 } 1549 1550 /* 1551 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1552 * This function enables and disables the card 1553 */ 1554 STATIC int 1555 pccbb_cardenable(struct pccbb_softc *sc, int function) 1556 { 1557 u_int32_t command = 1558 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1559 1560 DPRINTF(("pccbb_cardenable:")); 1561 switch (function) { 1562 case CARDBUS_IO_ENABLE: 1563 command |= PCI_COMMAND_IO_ENABLE; 1564 break; 1565 case CARDBUS_IO_DISABLE: 1566 command &= ~PCI_COMMAND_IO_ENABLE; 1567 break; 1568 case CARDBUS_MEM_ENABLE: 1569 command |= PCI_COMMAND_MEM_ENABLE; 1570 break; 1571 case CARDBUS_MEM_DISABLE: 1572 command &= ~PCI_COMMAND_MEM_ENABLE; 1573 break; 1574 case CARDBUS_BM_ENABLE: 1575 command |= PCI_COMMAND_MASTER_ENABLE; 1576 break; 1577 case CARDBUS_BM_DISABLE: 1578 command &= ~PCI_COMMAND_MASTER_ENABLE; 1579 break; 1580 default: 1581 return 0; 1582 } 1583 1584 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1585 DPRINTF((" command reg 0x%x\n", command)); 1586 return 1; 1587 } 1588 1589 #if !rbus 1590 static int 1591 pccbb_io_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 1592 { 1593 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1594 int basereg; 1595 int limitreg; 1596 1597 if ((win < 0) || (win > 2)) { 1598 #if defined DIAGNOSTIC 1599 printf("cardbus_io_open: window out of range %d\n", win); 1600 #endif 1601 return 0; 1602 } 1603 1604 basereg = win * 8 + PCI_CB_IOBASE0; 1605 limitreg = win * 8 + PCI_CB_IOLIMIT0; 1606 1607 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1608 start, basereg, end, limitreg)); 1609 1610 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1611 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1612 return 1; 1613 } 1614 1615 /* 1616 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1617 */ 1618 static int 1619 pccbb_io_close(cardbus_chipset_tag_t ct, int win) 1620 { 1621 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1622 int basereg; 1623 int limitreg; 1624 1625 if ((win < 0) || (win > 2)) { 1626 #if defined DIAGNOSTIC 1627 printf("cardbus_io_close: window out of range %d\n", win); 1628 #endif 1629 return 0; 1630 } 1631 1632 basereg = win * 8 + PCI_CB_IOBASE0; 1633 limitreg = win * 8 + PCI_CB_IOLIMIT0; 1634 1635 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1636 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1637 return 1; 1638 } 1639 1640 static int 1641 pccbb_mem_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 1642 { 1643 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1644 int basereg; 1645 int limitreg; 1646 1647 if ((win < 0) || (win > 2)) { 1648 #if defined DIAGNOSTIC 1649 printf("cardbus_mem_open: window out of range %d\n", win); 1650 #endif 1651 return 0; 1652 } 1653 1654 basereg = win * 8 + PCI_CB_MEMBASE0; 1655 limitreg = win * 8 + PCI_CB_MEMLIMIT0; 1656 1657 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1658 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1659 return 1; 1660 } 1661 1662 static int 1663 pccbb_mem_close(cardbus_chipset_tag_t ct, int win) 1664 { 1665 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1666 int basereg; 1667 int limitreg; 1668 1669 if ((win < 0) || (win > 2)) { 1670 #if defined DIAGNOSTIC 1671 printf("cardbus_mem_close: window out of range %d\n", win); 1672 #endif 1673 return 0; 1674 } 1675 1676 basereg = win * 8 + PCI_CB_MEMBASE0; 1677 limitreg = win * 8 + PCI_CB_MEMLIMIT0; 1678 1679 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1680 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1681 return 1; 1682 } 1683 #endif 1684 1685 /* 1686 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1687 * int irq, 1688 * int level, 1689 * int (* func)(void *), 1690 * void *arg) 1691 * 1692 * This function registers an interrupt handler at the bridge, in 1693 * order not to call the interrupt handlers of child devices when 1694 * a card-deletion interrupt occurs. 1695 * 1696 * The arguments irq and level are not used. 1697 */ 1698 static void * 1699 pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, cardbus_intr_line_t irq, 1700 int level, int (*func)(void *), void *arg) 1701 { 1702 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1703 1704 return pccbb_intr_establish(sc, irq, level, func, arg); 1705 } 1706 1707 1708 /* 1709 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1710 * void *ih) 1711 * 1712 * This function removes an interrupt handler pointed by ih. 1713 */ 1714 static void 1715 pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih) 1716 { 1717 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1718 1719 pccbb_intr_disestablish(sc, ih); 1720 } 1721 1722 1723 void 1724 pccbb_intr_route(struct pccbb_softc *sc) 1725 { 1726 pcireg_t bcr, cbctrl; 1727 1728 /* initialize bridge intr routing */ 1729 bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1730 bcr &= ~CB_BCR_INTR_IREQ_ENABLE; 1731 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr); 1732 1733 switch (sc->sc_chipset) { 1734 case CB_TI113X: 1735 cbctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1736 /* functional intr enabled */ 1737 cbctrl |= PCI113X_CBCTRL_PCI_INTR; 1738 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, cbctrl); 1739 break; 1740 default: 1741 break; 1742 } 1743 } 1744 1745 /* 1746 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1747 * int irq, 1748 * int level, 1749 * int (* func)(void *), 1750 * void *arg) 1751 * 1752 * This function registers an interrupt handler at the bridge, in 1753 * order not to call the interrupt handlers of child devices when 1754 * a card-deletion interrupt occurs. 1755 * 1756 * The arguments irq is not used because pccbb selects intr vector. 1757 */ 1758 static void * 1759 pccbb_intr_establish(struct pccbb_softc *sc, cardbus_intr_line_t irq, 1760 int level, int (*func)(void *), void *arg) 1761 { 1762 struct pccbb_intrhand_list *pil, *newpil; 1763 1764 DPRINTF(("pccbb_intr_establish start. %p\n", LIST_FIRST(&sc->sc_pil))); 1765 1766 if (LIST_EMPTY(&sc->sc_pil)) { 1767 pccbb_intr_route(sc); 1768 } 1769 1770 /* 1771 * Allocate a room for interrupt handler structure. 1772 */ 1773 if (NULL == (newpil = 1774 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1775 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1776 return NULL; 1777 } 1778 1779 newpil->pil_func = func; 1780 newpil->pil_arg = arg; 1781 newpil->pil_icookie = makeiplcookie(level); 1782 1783 if (LIST_EMPTY(&sc->sc_pil)) { 1784 LIST_INSERT_HEAD(&sc->sc_pil, newpil, pil_next); 1785 } else { 1786 for (pil = LIST_FIRST(&sc->sc_pil); 1787 LIST_NEXT(pil, pil_next) != NULL; 1788 pil = LIST_NEXT(pil, pil_next)); 1789 LIST_INSERT_AFTER(pil, newpil, pil_next); 1790 } 1791 1792 DPRINTF(("pccbb_intr_establish add pil. %p\n", 1793 LIST_FIRST(&sc->sc_pil))); 1794 1795 return newpil; 1796 } 1797 1798 /* 1799 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1800 * void *ih) 1801 * 1802 * This function removes an interrupt handler pointed by ih. ih 1803 * should be the value returned by cardbus_intr_establish() or 1804 * NULL. 1805 * 1806 * When ih is NULL, this function will do nothing. 1807 */ 1808 static void 1809 pccbb_intr_disestablish(struct pccbb_softc *sc, void *ih) 1810 { 1811 struct pccbb_intrhand_list *pil; 1812 pcireg_t reg; 1813 1814 DPRINTF(("pccbb_intr_disestablish start. %p\n", 1815 LIST_FIRST(&sc->sc_pil))); 1816 1817 if (ih == NULL) { 1818 /* intr handler is not set */ 1819 DPRINTF(("pccbb_intr_disestablish: no ih\n")); 1820 return; 1821 } 1822 1823 #ifdef DIAGNOSTIC 1824 LIST_FOREACH(pil, &sc->sc_pil, pil_next) { 1825 DPRINTF(("pccbb_intr_disestablish: pil %p\n", pil)); 1826 if (pil == ih) { 1827 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1828 break; 1829 } 1830 } 1831 if (pil == NULL) { 1832 panic("pccbb_intr_disestablish: %s cannot find pil %p", 1833 device_xname(sc->sc_dev), ih); 1834 } 1835 #endif 1836 1837 pil = (struct pccbb_intrhand_list *)ih; 1838 LIST_REMOVE(pil, pil_next); 1839 free(pil, M_DEVBUF); 1840 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1841 1842 if (LIST_EMPTY(&sc->sc_pil)) { 1843 /* No interrupt handlers */ 1844 1845 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1846 1847 /* stop routing PCI intr */ 1848 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1849 reg |= CB_BCR_INTR_IREQ_ENABLE; 1850 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, reg); 1851 1852 switch (sc->sc_chipset) { 1853 case CB_TI113X: 1854 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1855 /* functional intr disabled */ 1856 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1857 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1858 break; 1859 default: 1860 break; 1861 } 1862 } 1863 } 1864 1865 #if defined SHOW_REGS 1866 static void 1867 cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, bus_space_tag_t memt, 1868 bus_space_handle_t memh) 1869 { 1870 int i; 1871 printf("PCI config regs:"); 1872 for (i = 0; i < 0x50; i += 4) { 1873 if (i % 16 == 0) 1874 printf("\n 0x%02x:", i); 1875 printf(" %08x", pci_conf_read(pc, tag, i)); 1876 } 1877 for (i = 0x80; i < 0xb0; i += 4) { 1878 if (i % 16 == 0) 1879 printf("\n 0x%02x:", i); 1880 printf(" %08x", pci_conf_read(pc, tag, i)); 1881 } 1882 1883 if (memh == 0) { 1884 printf("\n"); 1885 return; 1886 } 1887 1888 printf("\nsocket regs:"); 1889 for (i = 0; i <= 0x10; i += 0x04) 1890 printf(" %08x", bus_space_read_4(memt, memh, i)); 1891 printf("\nExCA regs:"); 1892 for (i = 0; i < 0x08; ++i) 1893 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1894 printf("\n"); 1895 return; 1896 } 1897 #endif 1898 1899 /* 1900 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1901 * int busno, int function) 1902 * This is the function to make a tag to access config space of 1903 * a CardBus Card. It works same as pci_conf_read. 1904 */ 1905 static cardbustag_t 1906 pccbb_make_tag(cardbus_chipset_tag_t cc, int busno, int function) 1907 { 1908 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1909 1910 return pci_make_tag(sc->sc_pc, busno, 0, function); 1911 } 1912 1913 static void 1914 pccbb_free_tag(cardbus_chipset_tag_t cc, cardbustag_t tag) 1915 { 1916 } 1917 1918 /* 1919 * pccbb_conf_read 1920 * 1921 * This is the function to read the config space of a CardBus card. 1922 * It works the same as pci_conf_read(9). 1923 */ 1924 static cardbusreg_t 1925 pccbb_conf_read(cardbus_chipset_tag_t cc, cardbustag_t tag, int offset) 1926 { 1927 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1928 pcitag_t brtag = sc->sc_tag; 1929 cardbusreg_t reg; 1930 1931 /* 1932 * clear cardbus master abort status; it is OK to write without 1933 * reading before because all bits are r/o or w1tc 1934 */ 1935 pci_conf_write(sc->sc_pc, brtag, PCI_CBB_SECSTATUS, 1936 CBB_SECSTATUS_CBMABORT); 1937 reg = pci_conf_read(sc->sc_pc, tag, offset); 1938 /* check cardbus master abort status */ 1939 if (pci_conf_read(sc->sc_pc, brtag, PCI_CBB_SECSTATUS) 1940 & CBB_SECSTATUS_CBMABORT) 1941 return (0xffffffff); 1942 return reg; 1943 } 1944 1945 /* 1946 * pccbb_conf_write 1947 * 1948 * This is the function to write the config space of a CardBus 1949 * card. It works the same as pci_conf_write(9). 1950 */ 1951 static void 1952 pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, int reg, 1953 cardbusreg_t val) 1954 { 1955 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1956 1957 pci_conf_write(sc->sc_pc, tag, reg, val); 1958 } 1959 1960 #if 0 1961 STATIC int 1962 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1963 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 1964 int speed, int flags, 1965 bus_space_handle_t * iohp) 1966 #endif 1967 /* 1968 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1969 * bus_addr_t start, bus_size_t size, 1970 * bus_size_t align, 1971 * struct pcmcia_io_handle *pcihp 1972 * 1973 * This function only allocates I/O region for pccard. This function 1974 * never maps the allocated region to pccard I/O area. 1975 * 1976 * XXX: The interface of this function is not very good, I believe. 1977 */ 1978 STATIC int 1979 pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, 1980 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 1981 { 1982 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 1983 bus_addr_t ioaddr; 1984 int flags = 0; 1985 bus_space_tag_t iot; 1986 bus_space_handle_t ioh; 1987 bus_addr_t mask; 1988 #if rbus 1989 rbus_tag_t rb; 1990 #endif 1991 if (align == 0) { 1992 align = size; /* XXX: funny??? */ 1993 } 1994 1995 if (start != 0) { 1996 /* XXX: assume all card decode lower 10 bits by its hardware */ 1997 mask = 0x3ff; 1998 /* enforce to use only masked address */ 1999 start &= mask; 2000 } else { 2001 /* 2002 * calculate mask: 2003 * 1. get the most significant bit of size (call it msb). 2004 * 2. compare msb with the value of size. 2005 * 3. if size is larger, shift msb left once. 2006 * 4. obtain mask value to decrement msb. 2007 */ 2008 bus_size_t size_tmp = size; 2009 int shifts = 0; 2010 2011 mask = 1; 2012 while (size_tmp) { 2013 ++shifts; 2014 size_tmp >>= 1; 2015 } 2016 mask = (1 << shifts); 2017 if (mask < size) { 2018 mask <<= 1; 2019 } 2020 --mask; 2021 } 2022 2023 /* 2024 * Allocate some arbitrary I/O space. 2025 */ 2026 2027 iot = sc->sc_iot; 2028 2029 #if rbus 2030 rb = sc->sc_rbus_iot; 2031 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 2032 return 1; 2033 } 2034 DPRINTF(("pccbb_pcmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2035 (u_long) ioaddr, (u_long) size)); 2036 #else 2037 if (start) { 2038 ioaddr = start; 2039 if (bus_space_map(iot, start, size, 0, &ioh)) { 2040 return 1; 2041 } 2042 DPRINTF(("pccbb_pcmcia_io_alloc map port 0x%lx+0x%lx\n", 2043 (u_long) ioaddr, (u_long) size)); 2044 } else { 2045 flags |= PCMCIA_IO_ALLOCATED; 2046 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 2047 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 2048 size, align, 0, 0, &ioaddr, &ioh)) { 2049 /* No room be able to be get. */ 2050 return 1; 2051 } 2052 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2053 (u_long) ioaddr, (u_long) size)); 2054 } 2055 #endif 2056 2057 pcihp->iot = iot; 2058 pcihp->ioh = ioh; 2059 pcihp->addr = ioaddr; 2060 pcihp->size = size; 2061 pcihp->flags = flags; 2062 2063 return 0; 2064 } 2065 2066 /* 2067 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2068 * struct pcmcia_io_handle *pcihp) 2069 * 2070 * This function only frees I/O region for pccard. 2071 * 2072 * XXX: The interface of this function is not very good, I believe. 2073 */ 2074 void 2075 pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2076 struct pcmcia_io_handle *pcihp) 2077 { 2078 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2079 #if !rbus 2080 bus_space_tag_t iot = pcihp->iot; 2081 #endif 2082 bus_space_handle_t ioh = pcihp->ioh; 2083 bus_size_t size = pcihp->size; 2084 2085 #if rbus 2086 rbus_tag_t rb = sc->sc_rbus_iot; 2087 2088 rbus_space_free(rb, ioh, size, NULL); 2089 #else 2090 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 2091 bus_space_free(iot, ioh, size); 2092 else 2093 bus_space_unmap(iot, ioh, size); 2094 #endif 2095 } 2096 2097 /* 2098 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 2099 * bus_addr_t offset, bus_size_t size, 2100 * struct pcmcia_io_handle *pcihp, 2101 * int *windowp) 2102 * 2103 * This function maps the allocated I/O region to pccard. This function 2104 * never allocates any I/O region for pccard I/O area. I don't 2105 * understand why the original authors of pcmciabus separated alloc and 2106 * map. I believe the two must be unite. 2107 * 2108 * XXX: no wait timing control? 2109 */ 2110 int 2111 pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, bus_addr_t offset, 2112 bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp) 2113 { 2114 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2115 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2116 bus_addr_t ioaddr = pcihp->addr + offset; 2117 int i, win; 2118 #if defined CBB_DEBUG 2119 static const char *width_names[] = { "dynamic", "io8", "io16" }; 2120 #endif 2121 2122 /* Sanity check I/O handle. */ 2123 2124 if (sc->sc_iot != pcihp->iot) { 2125 panic("pccbb_pcmcia_io_map iot is bogus"); 2126 } 2127 2128 /* XXX Sanity check offset/size. */ 2129 2130 win = -1; 2131 for (i = 0; i < PCIC_IO_WINS; i++) { 2132 if ((ph->ioalloc & (1 << i)) == 0) { 2133 win = i; 2134 ph->ioalloc |= (1 << i); 2135 break; 2136 } 2137 } 2138 2139 if (win == -1) { 2140 return 1; 2141 } 2142 2143 *windowp = win; 2144 2145 /* XXX this is pretty gross */ 2146 2147 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2148 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2149 2150 /* XXX wtf is this doing here? */ 2151 2152 #if 0 2153 printf(" port 0x%lx", (u_long) ioaddr); 2154 if (size > 1) { 2155 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2156 } 2157 #endif 2158 2159 ph->io[win].addr = ioaddr; 2160 ph->io[win].size = size; 2161 ph->io[win].width = width; 2162 2163 /* actual dirty register-value changing in the function below. */ 2164 pccbb_pcmcia_do_io_map(sc, win); 2165 2166 return 0; 2167 } 2168 2169 /* 2170 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2171 * 2172 * This function changes register-value to map I/O region for pccard. 2173 */ 2174 static void 2175 pccbb_pcmcia_do_io_map(struct pccbb_softc *sc, int win) 2176 { 2177 static u_int8_t pcic_iowidth[3] = { 2178 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2179 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2180 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2181 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2182 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2183 }; 2184 2185 #define PCIC_SIA_START_LOW 0 2186 #define PCIC_SIA_START_HIGH 1 2187 #define PCIC_SIA_STOP_LOW 2 2188 #define PCIC_SIA_STOP_HIGH 3 2189 2190 int regbase_win = 0x8 + win * 0x04; 2191 u_int8_t ioctl, enable; 2192 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2193 2194 DPRINTF(("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx " 2195 "width %d\n", win, (unsigned long)ph->io[win].addr, 2196 (unsigned long)ph->io[win].size, ph->io[win].width * 8)); 2197 2198 Pcic_write(sc, regbase_win + PCIC_SIA_START_LOW, 2199 ph->io[win].addr & 0xff); 2200 Pcic_write(sc, regbase_win + PCIC_SIA_START_HIGH, 2201 (ph->io[win].addr >> 8) & 0xff); 2202 2203 Pcic_write(sc, regbase_win + PCIC_SIA_STOP_LOW, 2204 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2205 Pcic_write(sc, regbase_win + PCIC_SIA_STOP_HIGH, 2206 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2207 2208 ioctl = Pcic_read(sc, PCIC_IOCTL); 2209 enable = Pcic_read(sc, PCIC_ADDRWIN_ENABLE); 2210 switch (win) { 2211 case 0: 2212 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2213 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2214 PCIC_IOCTL_IO0_DATASIZE_MASK); 2215 ioctl |= pcic_iowidth[ph->io[win].width]; 2216 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2217 break; 2218 case 1: 2219 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2220 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2221 PCIC_IOCTL_IO1_DATASIZE_MASK); 2222 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2223 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2224 break; 2225 } 2226 Pcic_write(sc, PCIC_IOCTL, ioctl); 2227 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, enable); 2228 #if defined(CBB_DEBUG) 2229 { 2230 u_int8_t start_low = 2231 Pcic_read(sc, regbase_win + PCIC_SIA_START_LOW); 2232 u_int8_t start_high = 2233 Pcic_read(sc, regbase_win + PCIC_SIA_START_HIGH); 2234 u_int8_t stop_low = 2235 Pcic_read(sc, regbase_win + PCIC_SIA_STOP_LOW); 2236 u_int8_t stop_high = 2237 Pcic_read(sc, regbase_win + PCIC_SIA_STOP_HIGH); 2238 printf("pccbb_pcmcia_do_io_map start %02x %02x, " 2239 "stop %02x %02x, ioctl %02x enable %02x\n", 2240 start_low, start_high, stop_low, stop_high, ioctl, enable); 2241 } 2242 #endif 2243 } 2244 2245 /* 2246 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2247 * 2248 * This function unmaps I/O region. No return value. 2249 */ 2250 STATIC void 2251 pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t pch, int win) 2252 { 2253 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2254 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2255 int reg; 2256 2257 if (win >= PCIC_IO_WINS || win < 0) { 2258 panic("pccbb_pcmcia_io_unmap: window out of range"); 2259 } 2260 2261 reg = Pcic_read(sc, PCIC_ADDRWIN_ENABLE); 2262 switch (win) { 2263 case 0: 2264 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2265 break; 2266 case 1: 2267 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2268 break; 2269 } 2270 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, reg); 2271 2272 ph->ioalloc &= ~(1 << win); 2273 } 2274 2275 static int 2276 pccbb_pcmcia_wait_ready(struct pccbb_softc *sc) 2277 { 2278 u_int8_t stat; 2279 int i; 2280 2281 /* wait an initial 10ms for quick cards */ 2282 stat = Pcic_read(sc, PCIC_IF_STATUS); 2283 if (stat & PCIC_IF_STATUS_READY) 2284 return (0); 2285 pccbb_pcmcia_delay(sc, 10, "pccwr0"); 2286 for (i = 0; i < 50; i++) { 2287 stat = Pcic_read(sc, PCIC_IF_STATUS); 2288 if (stat & PCIC_IF_STATUS_READY) 2289 return (0); 2290 if ((stat & PCIC_IF_STATUS_CARDDETECT_MASK) != 2291 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2292 return (ENXIO); 2293 /* wait .1s (100ms) each iteration now */ 2294 pccbb_pcmcia_delay(sc, 100, "pccwr1"); 2295 } 2296 2297 printf("pccbb_pcmcia_wait_ready: ready never happened, status=%02x\n", stat); 2298 return (EWOULDBLOCK); 2299 } 2300 2301 /* 2302 * Perform long (msec order) delay. timo is in milliseconds. 2303 */ 2304 static void 2305 pccbb_pcmcia_delay(struct pccbb_softc *sc, int timo, const char *wmesg) 2306 { 2307 #ifdef DIAGNOSTIC 2308 if (timo <= 0) 2309 panic("pccbb_pcmcia_delay: called with timeout %d", timo); 2310 if (!curlwp) 2311 panic("pccbb_pcmcia_delay: called in interrupt context"); 2312 #endif 2313 DPRINTF(("pccbb_pcmcia_delay: \"%s\", sleep %d ms\n", wmesg, timo)); 2314 kpause(wmesg, false, max(mstohz(timo), 1), NULL); 2315 } 2316 2317 /* 2318 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2319 * 2320 * This function enables the card. All information is stored in 2321 * the first argument, pcmcia_chipset_handle_t. 2322 */ 2323 STATIC void 2324 pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2325 { 2326 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2327 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2328 pcireg_t spsr; 2329 int voltage; 2330 int win; 2331 u_int8_t power, intr; 2332 #ifdef DIAGNOSTIC 2333 int reg; 2334 #endif 2335 2336 /* this bit is mostly stolen from pcic_attach_card */ 2337 2338 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2339 2340 /* get card Vcc info */ 2341 spsr = 2342 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2343 CB_SOCKET_STAT); 2344 if (spsr & CB_SOCKET_STAT_5VCARD) { 2345 DPRINTF(("5V card\n")); 2346 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2347 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2348 DPRINTF(("3V card\n")); 2349 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2350 } else { 2351 DPRINTF(("?V card, 0x%x\n", spsr)); /* XXX */ 2352 return; 2353 } 2354 2355 /* disable interrupts; assert RESET */ 2356 intr = Pcic_read(sc, PCIC_INTR); 2357 intr &= PCIC_INTR_ENABLE; 2358 Pcic_write(sc, PCIC_INTR, intr); 2359 2360 /* zero out the address windows */ 2361 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, 0); 2362 2363 /* power down the socket to reset it, clear the card reset pin */ 2364 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2365 2366 /* power off; assert output enable bit */ 2367 power = PCIC_PWRCTL_OE; 2368 Pcic_write(sc, PCIC_PWRCTL, power); 2369 2370 /* power up the socket */ 2371 if (pccbb_power(sc, voltage) == 0) 2372 return; 2373 2374 /* 2375 * Table 4-18 and figure 4-6 of the PC Card specifiction say: 2376 * Vcc Rising Time (Tpr) = 100ms (handled in pccbb_power() above) 2377 * RESET Width (Th (Hi-z RESET)) = 1ms 2378 * RESET Width (Tw (RESET)) = 10us 2379 * 2380 * some machines require some more time to be settled 2381 * for example old toshiba topic bridges! 2382 * (100ms is added here). 2383 */ 2384 pccbb_pcmcia_delay(sc, 200 + 1, "pccen1"); 2385 2386 /* negate RESET */ 2387 intr |= PCIC_INTR_RESET; 2388 Pcic_write(sc, PCIC_INTR, intr); 2389 2390 /* 2391 * RESET Setup Time (Tsu (RESET)) = 20ms 2392 */ 2393 pccbb_pcmcia_delay(sc, 20, "pccen2"); 2394 2395 #ifdef DIAGNOSTIC 2396 reg = Pcic_read(sc, PCIC_IF_STATUS); 2397 if ((reg & PCIC_IF_STATUS_POWERACTIVE) == 0) 2398 printf("pccbb_pcmcia_socket_enable: no power, status=%x\n", reg); 2399 #endif 2400 2401 /* wait for the chip to finish initializing */ 2402 if (pccbb_pcmcia_wait_ready(sc)) { 2403 #ifdef DIAGNOSTIC 2404 printf("pccbb_pcmcia_socket_enable: never became ready\n"); 2405 #endif 2406 /* XXX return a failure status?? */ 2407 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2408 Pcic_write(sc, PCIC_PWRCTL, 0); 2409 return; 2410 } 2411 2412 /* reinstall all the memory and io mappings */ 2413 for (win = 0; win < PCIC_MEM_WINS; ++win) 2414 if (ph->memalloc & (1 << win)) 2415 pccbb_pcmcia_do_mem_map(sc, win); 2416 for (win = 0; win < PCIC_IO_WINS; ++win) 2417 if (ph->ioalloc & (1 << win)) 2418 pccbb_pcmcia_do_io_map(sc, win); 2419 } 2420 2421 /* 2422 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2423 * 2424 * This function disables the card. All information is stored in 2425 * the first argument, pcmcia_chipset_handle_t. 2426 */ 2427 STATIC void 2428 pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t pch) 2429 { 2430 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2431 u_int8_t intr; 2432 2433 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2434 2435 /* disable interrupts; assert RESET */ 2436 intr = Pcic_read(sc, PCIC_INTR); 2437 intr &= PCIC_INTR_ENABLE; 2438 Pcic_write(sc, PCIC_INTR, intr); 2439 2440 /* zero out the address windows */ 2441 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, 0); 2442 2443 /* power down the socket to reset it, clear the card reset pin */ 2444 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2445 2446 /* disable socket: negate output enable bit and power off */ 2447 Pcic_write(sc, PCIC_PWRCTL, 0); 2448 2449 /* 2450 * Vcc Falling Time (Tpf) = 300ms 2451 */ 2452 pccbb_pcmcia_delay(sc, 300, "pccwr1"); 2453 } 2454 2455 STATIC void 2456 pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t pch, int type) 2457 { 2458 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2459 u_int8_t intr; 2460 2461 /* set the card type */ 2462 2463 intr = Pcic_read(sc, PCIC_INTR); 2464 intr &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_CARDTYPE_MASK); 2465 if (type == PCMCIA_IFTYPE_IO) 2466 intr |= PCIC_INTR_CARDTYPE_IO; 2467 else 2468 intr |= PCIC_INTR_CARDTYPE_MEM; 2469 Pcic_write(sc, PCIC_INTR, intr); 2470 2471 DPRINTF(("%s: pccbb_pcmcia_socket_settype type %s %02x\n", 2472 device_xname(sc->sc_dev), 2473 ((type == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2474 } 2475 2476 /* 2477 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2478 * 2479 * This function detects whether a card is in the slot or not. 2480 * If a card is inserted, return 1. Otherwise, return 0. 2481 */ 2482 STATIC int 2483 pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch) 2484 { 2485 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2486 2487 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2488 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2489 } 2490 2491 #if 0 2492 STATIC int 2493 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2494 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2495 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2496 #endif 2497 /* 2498 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2499 * bus_size_t size, 2500 * struct pcmcia_mem_handle *pcmhp) 2501 * 2502 * This function only allocates memory region for pccard. This 2503 * function never maps the allocated region to pccard memory area. 2504 * 2505 * XXX: Why the argument of start address is not in? 2506 */ 2507 STATIC int 2508 pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 2509 struct pcmcia_mem_handle *pcmhp) 2510 { 2511 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2512 bus_space_handle_t memh; 2513 bus_addr_t addr; 2514 bus_size_t sizepg; 2515 #if rbus 2516 rbus_tag_t rb; 2517 #endif 2518 2519 /* Check that the card is still there. */ 2520 if ((Pcic_read(sc, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2521 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2522 return 1; 2523 2524 /* out of sc->memh, allocate as many pages as necessary */ 2525 2526 /* convert size to PCIC pages */ 2527 /* 2528 * This is not enough; when the requested region is on the page 2529 * boundaries, this may calculate wrong result. 2530 */ 2531 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2532 #if 0 2533 if (sizepg > PCIC_MAX_MEM_PAGES) { 2534 return 1; 2535 } 2536 #endif 2537 2538 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2539 return 1; 2540 } 2541 2542 addr = 0; /* XXX gcc -Wuninitialized */ 2543 2544 #if rbus 2545 rb = sc->sc_rbus_memt; 2546 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2547 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2548 &addr, &memh)) { 2549 return 1; 2550 } 2551 #else 2552 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2553 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2554 0, /* boundary */ 2555 0, /* flags */ 2556 &addr, &memh)) { 2557 return 1; 2558 } 2559 #endif 2560 2561 DPRINTF(("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, " 2562 "realsize 0x%lx\n", (unsigned long)addr, (unsigned long)size, 2563 (unsigned long)sizepg * PCIC_MEM_PAGESIZE)); 2564 2565 pcmhp->memt = sc->sc_memt; 2566 pcmhp->memh = memh; 2567 pcmhp->addr = addr; 2568 pcmhp->size = size; 2569 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2570 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2571 pcmhp->mhandle = 0; 2572 /* No offset??? Funny. */ 2573 2574 return 0; 2575 } 2576 2577 /* 2578 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2579 * struct pcmcia_mem_handle *pcmhp) 2580 * 2581 * This function release the memory space allocated by the function 2582 * pccbb_pcmcia_mem_alloc(). 2583 */ 2584 STATIC void 2585 pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2586 struct pcmcia_mem_handle *pcmhp) 2587 { 2588 #if rbus 2589 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2590 2591 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2592 #else 2593 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2594 #endif 2595 } 2596 2597 /* 2598 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2599 * 2600 * This function release the memory space allocated by the function 2601 * pccbb_pcmcia_mem_alloc(). 2602 */ 2603 STATIC void 2604 pccbb_pcmcia_do_mem_map(struct pccbb_softc *sc, int win) 2605 { 2606 int regbase_win; 2607 bus_addr_t phys_addr; 2608 bus_addr_t phys_end; 2609 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2610 2611 #define PCIC_SMM_START_LOW 0 2612 #define PCIC_SMM_START_HIGH 1 2613 #define PCIC_SMM_STOP_LOW 2 2614 #define PCIC_SMM_STOP_HIGH 3 2615 #define PCIC_CMA_LOW 4 2616 #define PCIC_CMA_HIGH 5 2617 2618 u_int8_t start_low, start_high = 0; 2619 u_int8_t stop_low, stop_high; 2620 u_int8_t off_low, off_high; 2621 u_int8_t mem_window; 2622 int reg; 2623 2624 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2625 int mem8 = 2626 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2627 || (kind == PCMCIA_MEM_ATTR); 2628 2629 regbase_win = 0x10 + win * 0x08; 2630 2631 phys_addr = ph->mem[win].addr; 2632 phys_end = phys_addr + ph->mem[win].size; 2633 2634 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2635 (unsigned long)phys_addr, (unsigned long)phys_end, 2636 (unsigned long)ph->mem[win].offset)); 2637 2638 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2639 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2640 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2641 2642 /* bit 19:12 */ 2643 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2644 /* bit 23:20 and bit 7 on */ 2645 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2646 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2647 /* bit 31:24, for 32-bit address */ 2648 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2649 2650 Pcic_write(sc, regbase_win + PCIC_SMM_START_LOW, start_low); 2651 Pcic_write(sc, regbase_win + PCIC_SMM_START_HIGH, start_high); 2652 2653 if (sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2654 Pcic_write(sc, 0x40 + win, mem_window); 2655 } 2656 2657 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2658 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2659 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2660 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2661 2662 Pcic_write(sc, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2663 Pcic_write(sc, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2664 2665 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2666 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2667 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2668 | ((kind == PCMCIA_MEM_ATTR) ? 2669 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2670 2671 Pcic_write(sc, regbase_win + PCIC_CMA_LOW, off_low); 2672 Pcic_write(sc, regbase_win + PCIC_CMA_HIGH, off_high); 2673 2674 reg = Pcic_read(sc, PCIC_ADDRWIN_ENABLE); 2675 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2676 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, reg); 2677 2678 #if defined(CBB_DEBUG) 2679 { 2680 int r1, r2, r3, r4, r5, r6, r7 = 0; 2681 2682 r1 = Pcic_read(sc, regbase_win + PCIC_SMM_START_LOW); 2683 r2 = Pcic_read(sc, regbase_win + PCIC_SMM_START_HIGH); 2684 r3 = Pcic_read(sc, regbase_win + PCIC_SMM_STOP_LOW); 2685 r4 = Pcic_read(sc, regbase_win + PCIC_SMM_STOP_HIGH); 2686 r5 = Pcic_read(sc, regbase_win + PCIC_CMA_LOW); 2687 r6 = Pcic_read(sc, regbase_win + PCIC_CMA_HIGH); 2688 if (sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2689 r7 = Pcic_read(sc, 0x40 + win); 2690 } 2691 2692 printf("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2693 "%02x%02x", win, r1, r2, r3, r4, r5, r6); 2694 if (sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2695 printf(" %02x", r7); 2696 } 2697 printf("\n"); 2698 } 2699 #endif 2700 } 2701 2702 /* 2703 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2704 * bus_addr_t card_addr, bus_size_t size, 2705 * struct pcmcia_mem_handle *pcmhp, 2706 * bus_addr_t *offsetp, int *windowp) 2707 * 2708 * This function maps memory space allocated by the function 2709 * pccbb_pcmcia_mem_alloc(). 2710 */ 2711 STATIC int 2712 pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2713 bus_addr_t card_addr, bus_size_t size, struct pcmcia_mem_handle *pcmhp, 2714 bus_size_t *offsetp, int *windowp) 2715 { 2716 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2717 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2718 bus_addr_t busaddr; 2719 long card_offset; 2720 int win; 2721 2722 /* Check that the card is still there. */ 2723 if ((Pcic_read(sc, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2724 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2725 return 1; 2726 2727 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2728 if ((ph->memalloc & (1 << win)) == 0) { 2729 ph->memalloc |= (1 << win); 2730 break; 2731 } 2732 } 2733 2734 if (win == PCIC_MEM_WINS) { 2735 return 1; 2736 } 2737 2738 *windowp = win; 2739 2740 /* XXX this is pretty gross */ 2741 2742 if (sc->sc_memt != pcmhp->memt) { 2743 panic("pccbb_pcmcia_mem_map memt is bogus"); 2744 } 2745 2746 busaddr = pcmhp->addr; 2747 2748 /* 2749 * compute the address offset to the pcmcia address space for the 2750 * pcic. this is intentionally signed. The masks and shifts below 2751 * will cause TRT to happen in the pcic registers. Deal with making 2752 * sure the address is aligned, and return the alignment offset. 2753 */ 2754 2755 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2756 card_addr -= *offsetp; 2757 2758 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2759 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2760 (u_long) card_addr)); 2761 2762 /* 2763 * include the offset in the size, and decrement size by one, since 2764 * the hw wants start/stop 2765 */ 2766 size += *offsetp - 1; 2767 2768 card_offset = (((long)card_addr) - ((long)busaddr)); 2769 2770 ph->mem[win].addr = busaddr; 2771 ph->mem[win].size = size; 2772 ph->mem[win].offset = card_offset; 2773 ph->mem[win].kind = kind; 2774 2775 pccbb_pcmcia_do_mem_map(sc, win); 2776 2777 return 0; 2778 } 2779 2780 /* 2781 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2782 * int window) 2783 * 2784 * This function unmaps memory space which mapped by the function 2785 * pccbb_pcmcia_mem_map(). 2786 */ 2787 STATIC void 2788 pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, int window) 2789 { 2790 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2791 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2792 int reg; 2793 2794 if (window >= PCIC_MEM_WINS) { 2795 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2796 } 2797 2798 reg = Pcic_read(sc, PCIC_ADDRWIN_ENABLE); 2799 reg &= ~(1 << window); 2800 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, reg); 2801 2802 ph->memalloc &= ~(1 << window); 2803 } 2804 2805 /* 2806 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2807 * struct pcmcia_function *pf, 2808 * int ipl, 2809 * int (*func)(void *), 2810 * void *arg); 2811 * 2812 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2813 */ 2814 STATIC void * 2815 pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2816 struct pcmcia_function *pf, int ipl, int (*func)(void *), void *arg) 2817 { 2818 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2819 2820 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2821 /* what should I do? */ 2822 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2823 DPRINTF(("%s does not provide edge nor pulse " 2824 "interrupt\n", device_xname(sc->sc_dev))); 2825 return NULL; 2826 } 2827 /* 2828 * XXX Noooooo! The interrupt flag must set properly!! 2829 * dumb pcmcia driver!! 2830 */ 2831 } 2832 2833 return pccbb_intr_establish(sc, 0, ipl, func, arg); 2834 } 2835 2836 /* 2837 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2838 * void *ih) 2839 * 2840 * This function disables PC-Card interrupt. 2841 */ 2842 STATIC void 2843 pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 2844 { 2845 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2846 2847 pccbb_intr_disestablish(sc, ih); 2848 } 2849 2850 #if rbus 2851 /* 2852 * static int 2853 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2854 * bus_addr_t addr, bus_size_t size, 2855 * bus_addr_t mask, bus_size_t align, 2856 * int flags, bus_addr_t *addrp; 2857 * bus_space_handle_t *bshp) 2858 * 2859 * This function allocates a portion of memory or io space for 2860 * clients. This function is called from CardBus card drivers. 2861 */ 2862 static int 2863 pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2864 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 2865 int flags, bus_addr_t *addrp, bus_space_handle_t *bshp) 2866 { 2867 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2868 2869 DPRINTF(("pccbb_rbus_cb_space_alloc: addr 0x%lx, size 0x%lx, " 2870 "mask 0x%lx, align 0x%lx\n", (unsigned long)addr, 2871 (unsigned long)size, (unsigned long)mask, (unsigned long)align)); 2872 2873 if (align == 0) { 2874 align = size; 2875 } 2876 2877 if (rb->rb_bt == sc->sc_memt) { 2878 if (align < 16) { 2879 return 1; 2880 } 2881 /* 2882 * XXX: align more than 0x1000 to avoid overwrapping 2883 * memory windows for two or more devices. 0x1000 2884 * means memory window's granularity. 2885 * 2886 * Two or more devices should be able to share same 2887 * memory window region. However, overrapping memory 2888 * window is not good because some devices, such as 2889 * 3Com 3C575[BC], have a broken address decoder and 2890 * intrude other's memory region. 2891 */ 2892 if (align < 0x1000) { 2893 align = 0x1000; 2894 } 2895 } else if (rb->rb_bt == sc->sc_iot) { 2896 if (align < 4) { 2897 return 1; 2898 } 2899 /* XXX: hack for avoiding ISA image */ 2900 if (mask < 0x0100) { 2901 mask = 0x3ff; 2902 addr = 0x300; 2903 } 2904 2905 } else { 2906 DPRINTF(("pccbb_rbus_cb_space_alloc: Bus space tag 0x%lx is " 2907 "NOT used. io: 0x%lx, mem: 0x%lx\n", 2908 (unsigned long)rb->rb_bt, (unsigned long)sc->sc_iot, 2909 (unsigned long)sc->sc_memt)); 2910 return 1; 2911 /* XXX: panic here? */ 2912 } 2913 2914 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 2915 aprint_normal_dev(sc->sc_dev, "<rbus> no bus space\n"); 2916 return 1; 2917 } 2918 2919 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 2920 2921 return 0; 2922 } 2923 2924 /* 2925 * static int 2926 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 2927 * bus_space_handle_t *bshp, bus_size_t size); 2928 * 2929 * This function is called from CardBus card drivers. 2930 */ 2931 static int 2932 pccbb_rbus_cb_space_free(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2933 bus_space_handle_t bsh, bus_size_t size) 2934 { 2935 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2936 bus_space_tag_t bt = rb->rb_bt; 2937 2938 pccbb_close_win(sc, bt, bsh, size); 2939 2940 if (bt == sc->sc_memt) { 2941 } else if (bt == sc->sc_iot) { 2942 } else { 2943 return 1; 2944 /* XXX: panic here? */ 2945 } 2946 2947 return rbus_space_free(rb, bsh, size, NULL); 2948 } 2949 #endif /* rbus */ 2950 2951 #if rbus 2952 2953 static int 2954 pccbb_open_win(struct pccbb_softc *sc, bus_space_tag_t bst, bus_addr_t addr, 2955 bus_size_t size, bus_space_handle_t bsh, int flags) 2956 { 2957 struct pccbb_win_chain_head *head; 2958 bus_addr_t align; 2959 2960 head = &sc->sc_iowindow; 2961 align = 0x04; 2962 if (sc->sc_memt == bst) { 2963 head = &sc->sc_memwindow; 2964 align = 0x1000; 2965 DPRINTF(("using memory window, 0x%lx 0x%lx 0x%lx\n\n", 2966 (unsigned long)sc->sc_iot, (unsigned long)sc->sc_memt, 2967 (unsigned long)bst)); 2968 } 2969 2970 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 2971 aprint_error_dev(sc->sc_dev, 2972 "pccbb_open_win: %s winlist insert failed\n", 2973 (head == &sc->sc_memwindow) ? "mem" : "io"); 2974 } 2975 pccbb_winset(align, sc, bst); 2976 2977 return 0; 2978 } 2979 2980 static int 2981 pccbb_close_win(struct pccbb_softc *sc, bus_space_tag_t bst, 2982 bus_space_handle_t bsh, bus_size_t size) 2983 { 2984 struct pccbb_win_chain_head *head; 2985 bus_addr_t align; 2986 2987 head = &sc->sc_iowindow; 2988 align = 0x04; 2989 if (sc->sc_memt == bst) { 2990 head = &sc->sc_memwindow; 2991 align = 0x1000; 2992 } 2993 2994 if (pccbb_winlist_delete(head, bsh, size)) { 2995 aprint_error_dev(sc->sc_dev, 2996 "pccbb_close_win: %s winlist delete failed\n", 2997 (head == &sc->sc_memwindow) ? "mem" : "io"); 2998 } 2999 pccbb_winset(align, sc, bst); 3000 3001 return 0; 3002 } 3003 3004 static int 3005 pccbb_winlist_insert(struct pccbb_win_chain_head *head, bus_addr_t start, 3006 bus_size_t size, bus_space_handle_t bsh, int flags) 3007 { 3008 struct pccbb_win_chain *chainp, *elem; 3009 3010 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 3011 M_NOWAIT)) == NULL) 3012 return (1); /* fail */ 3013 3014 elem->wc_start = start; 3015 elem->wc_end = start + (size - 1); 3016 elem->wc_handle = bsh; 3017 elem->wc_flags = flags; 3018 3019 TAILQ_FOREACH(chainp, head, wc_list) { 3020 if (chainp->wc_end >= start) 3021 break; 3022 } 3023 if (chainp != NULL) 3024 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 3025 else 3026 TAILQ_INSERT_TAIL(head, elem, wc_list); 3027 return (0); 3028 } 3029 3030 static int 3031 pccbb_winlist_delete(struct pccbb_win_chain_head *head, bus_space_handle_t bsh, 3032 bus_size_t size) 3033 { 3034 struct pccbb_win_chain *chainp; 3035 3036 TAILQ_FOREACH(chainp, head, wc_list) { 3037 if (memcmp(&chainp->wc_handle, &bsh, sizeof(bsh)) == 0) 3038 break; 3039 } 3040 if (chainp == NULL) 3041 return 1; /* fail: no candidate to remove */ 3042 3043 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 3044 printf("pccbb_winlist_delete: window 0x%lx size " 3045 "inconsistent: 0x%lx, 0x%lx\n", 3046 (unsigned long)chainp->wc_start, 3047 (unsigned long)(chainp->wc_end - chainp->wc_start), 3048 (unsigned long)(size - 1)); 3049 return 1; 3050 } 3051 3052 TAILQ_REMOVE(head, chainp, wc_list); 3053 free(chainp, M_DEVBUF); 3054 3055 return 0; 3056 } 3057 3058 static void 3059 pccbb_winset(bus_addr_t align, struct pccbb_softc *sc, bus_space_tag_t bst) 3060 { 3061 pci_chipset_tag_t pc; 3062 pcitag_t tag; 3063 bus_addr_t mask = ~(align - 1); 3064 struct { 3065 cardbusreg_t win_start; 3066 cardbusreg_t win_limit; 3067 int win_flags; 3068 } win[2]; 3069 struct pccbb_win_chain *chainp; 3070 int offs; 3071 3072 win[0].win_start = win[1].win_start = 0xffffffff; 3073 win[0].win_limit = win[1].win_limit = 0; 3074 win[0].win_flags = win[1].win_flags = 0; 3075 3076 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3077 offs = PCI_CB_IOBASE0; 3078 if (sc->sc_memt == bst) { 3079 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3080 offs = PCI_CB_MEMBASE0; 3081 } 3082 3083 if (chainp != NULL) { 3084 win[0].win_start = chainp->wc_start & mask; 3085 win[0].win_limit = chainp->wc_end & mask; 3086 win[0].win_flags = chainp->wc_flags; 3087 chainp = TAILQ_NEXT(chainp, wc_list); 3088 } 3089 3090 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3091 if (win[1].win_start == 0xffffffff) { 3092 /* window 1 is not used */ 3093 if ((win[0].win_flags == chainp->wc_flags) && 3094 (win[0].win_limit + align >= 3095 (chainp->wc_start & mask))) { 3096 /* concatenate */ 3097 win[0].win_limit = chainp->wc_end & mask; 3098 } else { 3099 /* make new window */ 3100 win[1].win_start = chainp->wc_start & mask; 3101 win[1].win_limit = chainp->wc_end & mask; 3102 win[1].win_flags = chainp->wc_flags; 3103 } 3104 continue; 3105 } 3106 3107 /* Both windows are engaged. */ 3108 if (win[0].win_flags == win[1].win_flags) { 3109 /* same flags */ 3110 if (win[0].win_flags == chainp->wc_flags) { 3111 if (win[1].win_start - (win[0].win_limit + 3112 align) < 3113 (chainp->wc_start & mask) - 3114 ((chainp->wc_end & mask) + align)) { 3115 /* 3116 * merge window 0 and 1, and set win1 3117 * to chainp 3118 */ 3119 win[0].win_limit = win[1].win_limit; 3120 win[1].win_start = 3121 chainp->wc_start & mask; 3122 win[1].win_limit = 3123 chainp->wc_end & mask; 3124 } else { 3125 win[1].win_limit = 3126 chainp->wc_end & mask; 3127 } 3128 } else { 3129 /* different flags */ 3130 3131 /* concatenate win0 and win1 */ 3132 win[0].win_limit = win[1].win_limit; 3133 /* allocate win[1] to new space */ 3134 win[1].win_start = chainp->wc_start & mask; 3135 win[1].win_limit = chainp->wc_end & mask; 3136 win[1].win_flags = chainp->wc_flags; 3137 } 3138 } else { 3139 /* the flags of win[0] and win[1] is different */ 3140 if (win[0].win_flags == chainp->wc_flags) { 3141 win[0].win_limit = chainp->wc_end & mask; 3142 /* 3143 * XXX this creates overlapping windows, so 3144 * what should the poor bridge do if one is 3145 * cachable, and the other is not? 3146 */ 3147 aprint_error_dev(sc->sc_dev, 3148 "overlapping windows\n"); 3149 } else { 3150 win[1].win_limit = chainp->wc_end & mask; 3151 } 3152 } 3153 } 3154 3155 pc = sc->sc_pc; 3156 tag = sc->sc_tag; 3157 pci_conf_write(pc, tag, offs, win[0].win_start); 3158 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3159 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3160 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3161 DPRINTF(("--pccbb_winset: win0 [0x%lx, 0x%lx), win1 [0x%lx, 0x%lx)\n", 3162 (unsigned long)pci_conf_read(pc, tag, offs), 3163 (unsigned long)pci_conf_read(pc, tag, offs + 4) + align, 3164 (unsigned long)pci_conf_read(pc, tag, offs + 8), 3165 (unsigned long)pci_conf_read(pc, tag, offs + 12) + align)); 3166 3167 if (bst == sc->sc_memt) { 3168 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BRIDGE_CONTROL_REG); 3169 3170 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 3171 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 3172 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3173 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 3174 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3175 pci_conf_write(pc, tag, PCI_BRIDGE_CONTROL_REG, bcr); 3176 } 3177 } 3178 3179 #endif /* rbus */ 3180 3181 static bool 3182 pccbb_suspend(device_t dv, const pmf_qual_t *qual) 3183 { 3184 struct pccbb_softc *sc = device_private(dv); 3185 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3186 bus_space_handle_t base_memh = sc->sc_base_memh; 3187 pcireg_t reg; 3188 3189 if (sc->sc_pil_intr_enable) 3190 (void)pccbbintr_function(sc); 3191 sc->sc_pil_intr_enable = 0; 3192 3193 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3194 /* Disable interrupts. */ 3195 reg &= ~(CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER); 3196 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3197 /* XXX joerg Disable power to the socket? */ 3198 3199 /* XXX flush PCI write */ 3200 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3201 3202 /* reset interrupt */ 3203 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, 3204 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT)); 3205 /* XXX flush PCI write */ 3206 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3207 3208 if (sc->sc_ih != NULL) { 3209 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 3210 sc->sc_ih = NULL; 3211 } 3212 3213 return true; 3214 } 3215 3216 static bool 3217 pccbb_resume(device_t dv, const pmf_qual_t *qual) 3218 { 3219 struct pccbb_softc *sc = device_private(dv); 3220 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3221 bus_space_handle_t base_memh = sc->sc_base_memh; 3222 pcireg_t reg; 3223 3224 pccbb_chipinit(sc); 3225 pccbb_intrinit(sc); 3226 /* setup memory and io space window for CB */ 3227 pccbb_winset(0x1000, sc, sc->sc_memt); 3228 pccbb_winset(0x04, sc, sc->sc_iot); 3229 3230 /* CSC Interrupt: Card detect interrupt on */ 3231 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3232 /* Card detect intr is turned on. */ 3233 reg |= CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; 3234 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3235 /* reset interrupt */ 3236 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3237 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3238 3239 /* 3240 * check for card insertion or removal during suspend period. 3241 * XXX: the code can't cope with card swap (remove then 3242 * insert). how can we detect such situation? 3243 */ 3244 (void)pccbbintr(sc); 3245 3246 sc->sc_pil_intr_enable = 1; 3247 3248 return true; 3249 } 3250
Indexes created Thu Sep 25 16:09:42 GMT 2025