pccbb.c revision 1.200
1 /* $NetBSD: pccbb.c,v 1.200 2010/12/27 19:02:32 phx Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: pccbb.c,v 1.200 2010/12/27 19:02:32 phx Exp $"); 30 31 /* 32 #define CBB_DEBUG 33 #define SHOW_REGS 34 */ 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/kernel.h> 39 #include <sys/errno.h> 40 #include <sys/ioctl.h> 41 #include <sys/reboot.h> /* for bootverbose */ 42 #include <sys/syslog.h> 43 #include <sys/device.h> 44 #include <sys/malloc.h> 45 #include <sys/proc.h> 46 47 #include <sys/intr.h> 48 #include <sys/bus.h> 49 50 #include <dev/pci/pcivar.h> 51 #include <dev/pci/pcireg.h> 52 #include <dev/pci/pcidevs.h> 53 54 #include <dev/pci/pccbbreg.h> 55 56 #include <dev/cardbus/cardslotvar.h> 57 58 #include <dev/cardbus/cardbusvar.h> 59 60 #include <dev/pcmcia/pcmciareg.h> 61 #include <dev/pcmcia/pcmciavar.h> 62 63 #include <dev/ic/i82365reg.h> 64 #include <dev/pci/pccbbvar.h> 65 66 #ifndef __NetBSD_Version__ 67 struct cfdriver cbb_cd = { 68 NULL, "cbb", DV_DULL 69 }; 70 #endif 71 72 #ifdef CBB_DEBUG 73 #define DPRINTF(x) printf x 74 #define STATIC 75 #else 76 #define DPRINTF(x) 77 #define STATIC static 78 #endif 79 80 int pccbb_burstup = 1; 81 82 /* 83 * delay_ms() is wait in milliseconds. It should be used instead 84 * of delay() if you want to wait more than 1 ms. 85 */ 86 static inline void 87 delay_ms(int millis, struct pccbb_softc *sc) 88 { 89 if (cold) 90 delay(millis * 1000); 91 else 92 kpause("pccbb", false, mstohz(millis), NULL); 93 } 94 95 int pcicbbmatch(device_t, cfdata_t, void *); 96 void pccbbattach(device_t, device_t, void *); 97 void pccbbchilddet(device_t, device_t); 98 int pccbbdetach(device_t, int); 99 int pccbbintr(void *); 100 static void pci113x_insert(void *); 101 static int pccbbintr_function(struct pccbb_softc *); 102 103 static int pccbb_detect_card(struct pccbb_softc *); 104 105 static void pccbb_pcmcia_write(struct pccbb_softc *, int, u_int8_t); 106 static u_int8_t pccbb_pcmcia_read(struct pccbb_softc *, int); 107 #define Pcic_read(sc, reg) pccbb_pcmcia_read((sc), (reg)) 108 #define Pcic_write(sc, reg, val) pccbb_pcmcia_write((sc), (reg), (val)) 109 110 STATIC int cb_reset(struct pccbb_softc *); 111 STATIC int cb_detect_voltage(struct pccbb_softc *); 112 STATIC int cbbprint(void *, const char *); 113 114 static int cb_chipset(u_int32_t, int *); 115 STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *, 116 struct pcmciabus_attach_args *); 117 118 STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int); 119 STATIC int pccbb_power(struct pccbb_softc *sc, int); 120 STATIC int pccbb_power_ct(cardbus_chipset_tag_t, int); 121 STATIC int pccbb_cardenable(struct pccbb_softc * sc, int function); 122 static void *pccbb_intr_establish(struct pccbb_softc *, 123 cardbus_intr_line_t irq, int level, int (*ih) (void *), void *sc); 124 static void pccbb_intr_disestablish(struct pccbb_softc *, void *ih); 125 126 static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t, 127 cardbus_intr_line_t irq, int level, int (*ih) (void *), void *sc); 128 static void pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih); 129 130 static pcitag_t pccbb_make_tag(cardbus_chipset_tag_t, int, int); 131 static pcireg_t pccbb_conf_read(cardbus_chipset_tag_t, pcitag_t, int); 132 static void pccbb_conf_write(cardbus_chipset_tag_t, pcitag_t, int, 133 pcireg_t); 134 static void pccbb_chipinit(struct pccbb_softc *); 135 static void pccbb_intrinit(struct pccbb_softc *); 136 137 STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 138 struct pcmcia_mem_handle *); 139 STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t, 140 struct pcmcia_mem_handle *); 141 STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 142 bus_size_t, struct pcmcia_mem_handle *, bus_size_t *, int *); 143 STATIC void pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t, int); 144 STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 145 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 146 STATIC void pccbb_pcmcia_io_free(pcmcia_chipset_handle_t, 147 struct pcmcia_io_handle *); 148 STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 149 bus_size_t, struct pcmcia_io_handle *, int *); 150 STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t, int); 151 STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t, 152 struct pcmcia_function *, int, int (*)(void *), void *); 153 STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t, void *); 154 STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t); 155 STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t); 156 STATIC void pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t, int); 157 STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch); 158 159 static int pccbb_pcmcia_wait_ready(struct pccbb_softc *); 160 static void pccbb_pcmcia_delay(struct pccbb_softc *, int, const char *); 161 162 static void pccbb_pcmcia_do_io_map(struct pccbb_softc *, int); 163 static void pccbb_pcmcia_do_mem_map(struct pccbb_softc *, int); 164 165 /* bus-space allocation and deallocation functions */ 166 167 static int pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t, rbus_tag_t, 168 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 169 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp); 170 static int pccbb_rbus_cb_space_free(cardbus_chipset_tag_t, rbus_tag_t, 171 bus_space_handle_t, bus_size_t); 172 173 174 175 static int pccbb_open_win(struct pccbb_softc *, bus_space_tag_t, 176 bus_addr_t, bus_size_t, bus_space_handle_t, int flags); 177 static int pccbb_close_win(struct pccbb_softc *, bus_space_tag_t, 178 bus_space_handle_t, bus_size_t); 179 static int pccbb_winlist_insert(struct pccbb_win_chain_head *, bus_addr_t, 180 bus_size_t, bus_space_handle_t, int); 181 static int pccbb_winlist_delete(struct pccbb_win_chain_head *, 182 bus_space_handle_t, bus_size_t); 183 static void pccbb_winset(bus_addr_t align, struct pccbb_softc *, 184 bus_space_tag_t); 185 void pccbb_winlist_show(struct pccbb_win_chain *); 186 187 188 /* for config_defer */ 189 static void pccbb_pci_callback(device_t); 190 191 static bool pccbb_suspend(device_t, const pmf_qual_t *); 192 static bool pccbb_resume(device_t, const pmf_qual_t *); 193 194 #if defined SHOW_REGS 195 static void cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, 196 bus_space_tag_t memt, bus_space_handle_t memh); 197 #endif 198 199 CFATTACH_DECL3_NEW(cbb_pci, sizeof(struct pccbb_softc), 200 pcicbbmatch, pccbbattach, pccbbdetach, NULL, NULL, pccbbchilddet, 201 DVF_DETACH_SHUTDOWN); 202 203 static const struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 204 pccbb_pcmcia_mem_alloc, 205 pccbb_pcmcia_mem_free, 206 pccbb_pcmcia_mem_map, 207 pccbb_pcmcia_mem_unmap, 208 pccbb_pcmcia_io_alloc, 209 pccbb_pcmcia_io_free, 210 pccbb_pcmcia_io_map, 211 pccbb_pcmcia_io_unmap, 212 pccbb_pcmcia_intr_establish, 213 pccbb_pcmcia_intr_disestablish, 214 pccbb_pcmcia_socket_enable, 215 pccbb_pcmcia_socket_disable, 216 pccbb_pcmcia_socket_settype, 217 pccbb_pcmcia_card_detect 218 }; 219 220 static const struct cardbus_functions pccbb_funcs = { 221 pccbb_rbus_cb_space_alloc, 222 pccbb_rbus_cb_space_free, 223 pccbb_cb_intr_establish, 224 pccbb_cb_intr_disestablish, 225 pccbb_ctrl, 226 pccbb_power_ct, 227 pccbb_make_tag, 228 pccbb_conf_read, 229 pccbb_conf_write, 230 }; 231 232 int 233 pcicbbmatch(device_t parent, cfdata_t match, void *aux) 234 { 235 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 236 237 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 238 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 239 PCI_INTERFACE(pa->pa_class) == 0) { 240 return 1; 241 } 242 243 return 0; 244 } 245 246 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 247 | ((prod) << PCI_PRODUCT_SHIFT)) 248 249 const struct yenta_chipinfo { 250 pcireg_t yc_id; /* vendor tag | product tag */ 251 int yc_chiptype; 252 int yc_flags; 253 } yc_chipsets[] = { 254 /* Texas Instruments chips */ 255 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 256 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 257 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 258 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 259 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI125X, 260 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 261 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 262 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 263 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 264 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 265 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 266 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 267 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI125X, 268 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 269 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI125X, 270 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 271 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 272 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 273 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 274 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 275 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI1420, 276 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 277 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI125X, 278 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 279 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 280 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 281 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1510), CB_TI12XX, 282 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 283 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1520), CB_TI12XX, 284 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 285 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4410YENTA), CB_TI12XX, 286 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 287 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4520YENTA), CB_TI12XX, 288 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 289 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI7420YENTA), CB_TI12XX, 290 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 291 292 /* Ricoh chips */ 293 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 294 PCCBB_PCMCIA_MEM_32}, 295 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 296 PCCBB_PCMCIA_MEM_32}, 297 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 298 PCCBB_PCMCIA_MEM_32}, 299 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 300 PCCBB_PCMCIA_MEM_32}, 301 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 302 PCCBB_PCMCIA_MEM_32}, 303 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 304 PCCBB_PCMCIA_MEM_32}, 305 306 /* Toshiba products */ 307 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 308 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 309 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 310 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 311 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 312 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 313 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 314 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 315 316 /* Cirrus Logic products */ 317 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 318 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 319 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 320 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 321 322 /* O2 Micro products */ 323 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6729), 324 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 325 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6730), 326 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 327 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6832), 328 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 329 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6836), 330 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 331 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6872), 332 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 333 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6922), 334 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 335 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6933), 336 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 337 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6972), 338 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 339 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_7223), 340 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 341 342 /* sentinel, or Generic chip */ 343 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 344 }; 345 346 static int 347 cb_chipset(u_int32_t pci_id, int *flagp) 348 { 349 const struct yenta_chipinfo *yc; 350 351 /* Loop over except the last default entry. */ 352 for (yc = yc_chipsets; yc < yc_chipsets + 353 __arraycount(yc_chipsets) - 1; yc++) 354 if (pci_id == yc->yc_id) 355 break; 356 357 if (flagp != NULL) 358 *flagp = yc->yc_flags; 359 360 return (yc->yc_chiptype); 361 } 362 363 void 364 pccbbchilddet(device_t self, device_t child) 365 { 366 struct pccbb_softc *sc = device_private(self); 367 int s; 368 369 KASSERT(sc->sc_csc == device_private(child)); 370 371 s = splbio(); 372 if (sc->sc_csc == device_private(child)) 373 sc->sc_csc = NULL; 374 splx(s); 375 } 376 377 void 378 pccbbattach(device_t parent, device_t self, void *aux) 379 { 380 struct pccbb_softc *sc = device_private(self); 381 struct pci_attach_args *pa = aux; 382 pci_chipset_tag_t pc = pa->pa_pc; 383 pcireg_t busreg, reg, sock_base; 384 bus_addr_t sockbase; 385 char devinfo[256]; 386 int flags; 387 388 #ifdef __HAVE_PCCBB_ATTACH_HOOK 389 pccbb_attach_hook(parent, self, pa); 390 #endif 391 392 sc->sc_dev = self; 393 394 mutex_init(&sc->sc_pwr_mtx, MUTEX_DEFAULT, IPL_BIO); 395 cv_init(&sc->sc_pwr_cv, "pccpwr"); 396 397 callout_init(&sc->sc_insert_ch, 0); 398 callout_setfunc(&sc->sc_insert_ch, pci113x_insert, sc); 399 400 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 401 402 aprint_naive("\n"); 403 404 pci_devinfo(pa->pa_id, 0, 0, devinfo, sizeof(devinfo)); 405 aprint_normal(": %s (rev. 0x%02x)", devinfo, 406 PCI_REVISION(pa->pa_class)); 407 DPRINTF((" (chipflags %x)", flags)); 408 aprint_normal("\n"); 409 410 TAILQ_INIT(&sc->sc_memwindow); 411 TAILQ_INIT(&sc->sc_iowindow); 412 413 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 414 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 415 416 #if 0 417 printf("pa->pa_memt: %08x vs rbus_mem->rb_bt: %08x\n", 418 pa->pa_memt, sc->sc_rbus_memt->rb_bt); 419 #endif 420 421 sc->sc_flags &= ~CBB_MEMHMAPPED; 422 423 /* 424 * MAP socket registers and ExCA registers on memory-space 425 * When no valid address is set on socket base registers (on pci 426 * config space), get it not polite way. 427 */ 428 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 429 430 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 431 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 432 /* The address must be valid. */ 433 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 434 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, &sc->sc_base_size)) { 435 aprint_error_dev(self, 436 "can't map socket base address 0x%lx\n", 437 (unsigned long)sock_base); 438 /* 439 * I think it's funny: socket base registers must be 440 * mapped on memory space, but ... 441 */ 442 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 443 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 444 &sc->sc_base_size)) { 445 aprint_error_dev(self, 446 "can't map socket base address" 447 " 0x%lx: io mode\n", 448 (unsigned long)sockbase); 449 /* give up... allocate reg space via rbus. */ 450 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 451 } else 452 sc->sc_flags |= CBB_MEMHMAPPED; 453 } else { 454 DPRINTF(("%s: socket base address 0x%lx\n", 455 device_xname(self), 456 (unsigned long)sockbase)); 457 sc->sc_flags |= CBB_MEMHMAPPED; 458 } 459 } 460 461 sc->sc_mem_start = 0; /* XXX */ 462 sc->sc_mem_end = 0xffffffff; /* XXX */ 463 464 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 465 466 /* pccbb_machdep.c end */ 467 468 #if defined CBB_DEBUG 469 { 470 static const char *intrname[] = { "NON", "A", "B", "C", "D" }; 471 aprint_debug_dev(self, "intrpin %s, intrtag %d\n", 472 intrname[pa->pa_intrpin], pa->pa_intrline); 473 } 474 #endif 475 476 /* setup softc */ 477 sc->sc_pc = pc; 478 sc->sc_iot = pa->pa_iot; 479 sc->sc_memt = pa->pa_memt; 480 sc->sc_dmat = pa->pa_dmat; 481 sc->sc_tag = pa->pa_tag; 482 483 memcpy(&sc->sc_pa, pa, sizeof(*pa)); 484 485 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 486 487 /* Disable legacy register mapping. */ 488 switch (sc->sc_chipset) { 489 case CB_RX5C46X: /* fallthrough */ 490 #if 0 491 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 492 case CB_RX5C47X: 493 #endif 494 /* 495 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 496 * cannot be disabled by substituting 0 into PCI_LEGACY 497 * register. Ricoh CardBus bridges have special bits on Bridge 498 * control reg (addr 0x3e on PCI config space). 499 */ 500 reg = pci_conf_read(pc, pa->pa_tag, PCI_BRIDGE_CONTROL_REG); 501 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 502 pci_conf_write(pc, pa->pa_tag, PCI_BRIDGE_CONTROL_REG, reg); 503 break; 504 505 default: 506 /* XXX I don't know proper way to kill legacy I/O. */ 507 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 508 break; 509 } 510 511 if (!pmf_device_register(self, pccbb_suspend, pccbb_resume)) 512 aprint_error_dev(self, "couldn't establish power handler\n"); 513 514 config_defer(self, pccbb_pci_callback); 515 } 516 517 int 518 pccbbdetach(device_t self, int flags) 519 { 520 struct pccbb_softc *sc = device_private(self); 521 pci_chipset_tag_t pc = sc->sc_pa.pa_pc; 522 bus_space_tag_t bmt = sc->sc_base_memt; 523 bus_space_handle_t bmh = sc->sc_base_memh; 524 uint32_t sockmask; 525 int rc; 526 527 if ((rc = config_detach_children(self, flags)) != 0) 528 return rc; 529 530 if (!LIST_EMPTY(&sc->sc_pil)) { 531 panic("%s: interrupt handlers still registered", 532 device_xname(self)); 533 return EBUSY; 534 } 535 536 if (sc->sc_ih != NULL) { 537 pci_intr_disestablish(pc, sc->sc_ih); 538 sc->sc_ih = NULL; 539 } 540 541 /* CSC Interrupt: turn off card detect and power cycle interrupts */ 542 sockmask = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 543 sockmask &= ~(CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | 544 CB_SOCKET_MASK_POWER); 545 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, sockmask); 546 /* reset interrupt */ 547 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 548 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 549 550 switch (sc->sc_flags & (CBB_MEMHMAPPED|CBB_SPECMAPPED)) { 551 case CBB_MEMHMAPPED: 552 bus_space_unmap(bmt, bmh, sc->sc_base_size); 553 break; 554 case CBB_MEMHMAPPED|CBB_SPECMAPPED: 555 #if rbus 556 { 557 pcireg_t sockbase; 558 559 sockbase = pci_conf_read(pc, sc->sc_tag, PCI_SOCKBASE); 560 rbus_space_free(sc->sc_rbus_memt, bmh, 0x1000, 561 NULL); 562 } 563 #else 564 bus_space_free(bmt, bmh, 0x1000); 565 #endif 566 } 567 sc->sc_flags &= ~(CBB_MEMHMAPPED|CBB_SPECMAPPED); 568 569 if (!TAILQ_EMPTY(&sc->sc_iowindow)) 570 aprint_error_dev(self, "i/o windows not empty"); 571 if (!TAILQ_EMPTY(&sc->sc_memwindow)) 572 aprint_error_dev(self, "memory windows not empty"); 573 574 callout_stop(&sc->sc_insert_ch); 575 callout_destroy(&sc->sc_insert_ch); 576 577 mutex_destroy(&sc->sc_pwr_mtx); 578 cv_destroy(&sc->sc_pwr_cv); 579 580 return 0; 581 } 582 583 /* 584 * static void pccbb_pci_callback(device_t self) 585 * 586 * The actual attach routine: get memory space for YENTA register 587 * space, setup YENTA register and route interrupt. 588 * 589 * This function should be deferred because this device may obtain 590 * memory space dynamically. This function must avoid obtaining 591 * memory area which has already kept for another device. 592 */ 593 static void 594 pccbb_pci_callback(device_t self) 595 { 596 struct pccbb_softc *sc = device_private(self); 597 pci_chipset_tag_t pc = sc->sc_pc; 598 bus_addr_t sockbase; 599 struct cbslot_attach_args cba; 600 struct pcmciabus_attach_args paa; 601 struct cardslot_attach_args caa; 602 device_t csc; 603 604 if (!(sc->sc_flags & CBB_MEMHMAPPED)) { 605 /* The socket registers aren't mapped correctly. */ 606 #if rbus 607 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 608 (sc->sc_chipset == CB_RX5C47X 609 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 610 0, &sockbase, &sc->sc_base_memh)) { 611 return; 612 } 613 sc->sc_base_memt = sc->sc_memt; 614 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 615 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 616 device_xname(self), (unsigned long)sockbase, 617 (unsigned long)pci_conf_read(pc, sc->sc_tag, 618 PCI_SOCKBASE))); 619 #else 620 sc->sc_base_memt = sc->sc_memt; 621 #if !defined CBB_PCI_BASE 622 #define CBB_PCI_BASE 0x20000000 623 #endif 624 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 625 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 626 /* cannot allocate memory space */ 627 return; 628 } 629 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 630 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 631 device_xname(self), (unsigned long)sock_base, 632 (unsigned long)pci_conf_read(pc, 633 sc->sc_tag, PCI_SOCKBASE))); 634 #endif 635 sc->sc_flags |= CBB_MEMHMAPPED|CBB_SPECMAPPED; 636 } 637 638 /* clear data structure for child device interrupt handlers */ 639 LIST_INIT(&sc->sc_pil); 640 641 /* bus bridge initialization */ 642 pccbb_chipinit(sc); 643 644 sc->sc_pil_intr_enable = true; 645 646 { 647 u_int32_t sockstat; 648 649 sockstat = bus_space_read_4(sc->sc_base_memt, 650 sc->sc_base_memh, CB_SOCKET_STAT); 651 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 652 sc->sc_flags |= CBB_CARDEXIST; 653 } 654 } 655 656 /* 657 * attach cardbus 658 */ 659 { 660 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 661 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 662 663 /* initialize cbslot_attach */ 664 cba.cba_iot = sc->sc_iot; 665 cba.cba_memt = sc->sc_memt; 666 cba.cba_dmat = sc->sc_dmat; 667 cba.cba_bus = (busreg >> 8) & 0x0ff; 668 cba.cba_cc = (void *)sc; 669 cba.cba_cf = &pccbb_funcs; 670 cba.cba_intrline = 0; /* XXX dummy */ 671 672 #if rbus 673 cba.cba_rbus_iot = sc->sc_rbus_iot; 674 cba.cba_rbus_memt = sc->sc_rbus_memt; 675 #endif 676 677 cba.cba_cacheline = PCI_CACHELINE(bhlc); 678 cba.cba_max_lattimer = PCI_LATTIMER(bhlc); 679 680 aprint_verbose_dev(self, 681 "cacheline 0x%x lattimer 0x%x\n", 682 cba.cba_cacheline, 683 cba.cba_max_lattimer); 684 aprint_verbose_dev(self, "bhlc 0x%x\n", bhlc); 685 #if defined SHOW_REGS 686 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 687 sc->sc_base_memh); 688 #endif 689 } 690 691 pccbb_pcmcia_attach_setup(sc, &paa); 692 caa.caa_cb_attach = NULL; 693 if (cba.cba_bus == 0) 694 aprint_error_dev(self, 695 "secondary bus number uninitialized; try PCI_BUS_FIXUP\n"); 696 else 697 caa.caa_cb_attach = &cba; 698 caa.caa_16_attach = &paa; 699 700 pccbb_intrinit(sc); 701 702 if (NULL != (csc = config_found_ia(self, "pcmciaslot", &caa, 703 cbbprint))) { 704 DPRINTF(("%s: found cardslot\n", __func__)); 705 sc->sc_csc = device_private(csc); 706 } 707 708 return; 709 } 710 711 712 713 714 715 /* 716 * static void pccbb_chipinit(struct pccbb_softc *sc) 717 * 718 * This function initialize YENTA chip registers listed below: 719 * 1) PCI command reg, 720 * 2) PCI and CardBus latency timer, 721 * 3) route PCI interrupt, 722 * 4) close all memory and io windows. 723 * 5) turn off bus power. 724 * 6) card detect and power cycle interrupts on. 725 * 7) clear interrupt 726 */ 727 static void 728 pccbb_chipinit(struct pccbb_softc *sc) 729 { 730 pci_chipset_tag_t pc = sc->sc_pc; 731 pcitag_t tag = sc->sc_tag; 732 bus_space_tag_t bmt = sc->sc_base_memt; 733 bus_space_handle_t bmh = sc->sc_base_memh; 734 pcireg_t bcr, bhlc, cbctl, csr, lscp, mfunc, mrburst, slotctl, sockctl, 735 sysctrl; 736 737 /* 738 * Set PCI command reg. 739 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 740 */ 741 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 742 /* I believe it is harmless. */ 743 csr |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 744 PCI_COMMAND_MASTER_ENABLE); 745 746 /* All O2 Micro chips have broken parity-error reporting 747 * until proven otherwise. The OZ6933 PCI-CardBus Bridge 748 * is known to have the defect---see PR kern/38698. 749 */ 750 if (sc->sc_chipset != CB_O2MICRO) 751 csr |= PCI_COMMAND_PARITY_ENABLE; 752 753 csr |= PCI_COMMAND_SERR_ENABLE; 754 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 755 756 /* 757 * Set CardBus latency timer. 758 */ 759 lscp = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 760 if (PCI_CB_LATENCY(lscp) < 0x20) { 761 lscp &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 762 lscp |= (0x20 << PCI_CB_LATENCY_SHIFT); 763 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, lscp); 764 } 765 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 766 PCI_CB_LATENCY(lscp), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 767 768 /* 769 * Set PCI latency timer. 770 */ 771 bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG); 772 if (PCI_LATTIMER(bhlc) < 0x10) { 773 bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 774 bhlc |= (0x10 << PCI_LATTIMER_SHIFT); 775 pci_conf_write(pc, tag, PCI_BHLC_REG, bhlc); 776 } 777 DPRINTF(("PCI latency timer 0x%x (%x)\n", 778 PCI_LATTIMER(bhlc), pci_conf_read(pc, tag, PCI_BHLC_REG))); 779 780 781 /* Route functional interrupts to PCI. */ 782 bcr = pci_conf_read(pc, tag, PCI_BRIDGE_CONTROL_REG); 783 bcr |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 784 bcr |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 785 /* assert reset */ 786 bcr |= PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT; 787 /* Set master abort mode to 1, forward SERR# from secondary 788 * to primary, and detect parity errors on secondary. 789 */ 790 bcr |= PCI_BRIDGE_CONTROL_MABRT << PCI_BRIDGE_CONTROL_SHIFT; 791 bcr |= PCI_BRIDGE_CONTROL_SERR << PCI_BRIDGE_CONTROL_SHIFT; 792 bcr |= PCI_BRIDGE_CONTROL_PERE << PCI_BRIDGE_CONTROL_SHIFT; 793 pci_conf_write(pc, tag, PCI_BRIDGE_CONTROL_REG, bcr); 794 795 switch (sc->sc_chipset) { 796 case CB_TI113X: 797 cbctl = pci_conf_read(pc, tag, PCI_CBCTRL); 798 /* This bit is shared, but may read as 0 on some chips, so set 799 it explicitly on both functions. */ 800 cbctl |= PCI113X_CBCTRL_PCI_IRQ_ENA; 801 /* CSC intr enable */ 802 cbctl |= PCI113X_CBCTRL_PCI_CSC; 803 /* functional intr prohibit | prohibit ISA routing */ 804 cbctl &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 805 pci_conf_write(pc, tag, PCI_CBCTRL, cbctl); 806 break; 807 808 case CB_TI1420: 809 sysctrl = pci_conf_read(pc, tag, PCI_SYSCTRL); 810 mrburst = pccbb_burstup 811 ? PCI1420_SYSCTRL_MRBURST : PCI1420_SYSCTRL_MRBURSTDN; 812 if ((sysctrl & PCI1420_SYSCTRL_MRBURST) == mrburst) { 813 printf("%s: %swrite bursts enabled\n", 814 device_xname(sc->sc_dev), 815 pccbb_burstup ? "read/" : ""); 816 } else if (pccbb_burstup) { 817 printf("%s: enabling read/write bursts\n", 818 device_xname(sc->sc_dev)); 819 sysctrl |= PCI1420_SYSCTRL_MRBURST; 820 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 821 } else { 822 printf("%s: disabling read bursts, " 823 "enabling write bursts\n", 824 device_xname(sc->sc_dev)); 825 sysctrl |= PCI1420_SYSCTRL_MRBURSTDN; 826 sysctrl &= ~PCI1420_SYSCTRL_MRBURSTUP; 827 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 828 } 829 /*FALLTHROUGH*/ 830 case CB_TI12XX: 831 /* 832 * Some TI 12xx (and [14][45]xx) based pci cards 833 * sometimes have issues with the MFUNC register not 834 * being initialized due to a bad EEPROM on board. 835 * Laptops that this matters on have this register 836 * properly initialized. 837 * 838 * The TI125X parts have a different register. 839 */ 840 mfunc = pci_conf_read(pc, tag, PCI12XX_MFUNC); 841 if ((mfunc & (PCI12XX_MFUNC_PIN0 | PCI12XX_MFUNC_PIN1)) == 0) { 842 /* Enable PCI interrupt /INTA */ 843 mfunc |= PCI12XX_MFUNC_PIN0_INTA; 844 845 /* XXX this is TI1520 only */ 846 if ((pci_conf_read(pc, tag, PCI_SYSCTRL) & 847 PCI12XX_SYSCTRL_INTRTIE) == 0) 848 /* Enable PCI interrupt /INTB */ 849 mfunc |= PCI12XX_MFUNC_PIN1_INTB; 850 851 pci_conf_write(pc, tag, PCI12XX_MFUNC, mfunc); 852 } 853 /* fallthrough */ 854 855 case CB_TI125X: 856 /* 857 * Disable zoom video. Some machines initialize this 858 * improperly and experience has shown that this helps 859 * prevent strange behavior. 860 */ 861 pci_conf_write(pc, tag, PCI12XX_MMCTRL, 0); 862 863 sysctrl = pci_conf_read(pc, tag, PCI_SYSCTRL); 864 sysctrl |= PCI12XX_SYSCTRL_VCCPROT; 865 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 866 cbctl = pci_conf_read(pc, tag, PCI_CBCTRL); 867 cbctl |= PCI12XX_CBCTRL_CSC; 868 pci_conf_write(pc, tag, PCI_CBCTRL, cbctl); 869 break; 870 871 case CB_TOPIC95B: 872 sockctl = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 873 sockctl |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 874 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, sockctl); 875 slotctl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 876 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 877 device_xname(sc->sc_dev), slotctl)); 878 slotctl |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 879 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 880 slotctl &= ~TOPIC_SLOT_CTRL_SWDETECT; 881 DPRINTF(("0x%x\n", slotctl)); 882 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slotctl); 883 break; 884 885 case CB_TOPIC97: 886 slotctl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 887 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 888 device_xname(sc->sc_dev), slotctl)); 889 slotctl |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 890 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 891 slotctl &= ~TOPIC_SLOT_CTRL_SWDETECT; 892 slotctl |= TOPIC97_SLOT_CTRL_PCIINT; 893 slotctl &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 894 DPRINTF(("0x%x\n", slotctl)); 895 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slotctl); 896 /* make sure to assert LV card support bits */ 897 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 898 0x800 + 0x3e, 899 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 900 0x800 + 0x3e) | 0x03); 901 break; 902 } 903 904 /* Close all memory and I/O windows. */ 905 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 906 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 907 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 908 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 909 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 910 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 911 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 912 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 913 914 /* reset 16-bit pcmcia bus */ 915 bus_space_write_1(bmt, bmh, 0x800 + PCIC_INTR, 916 bus_space_read_1(bmt, bmh, 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 917 918 /* turn off power */ 919 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 920 } 921 922 static void 923 pccbb_intrinit(struct pccbb_softc *sc) 924 { 925 pcireg_t sockmask; 926 const char *intrstr = NULL; 927 pci_intr_handle_t ih; 928 pci_chipset_tag_t pc = sc->sc_pc; 929 bus_space_tag_t bmt = sc->sc_base_memt; 930 bus_space_handle_t bmh = sc->sc_base_memh; 931 932 /* Map and establish the interrupt. */ 933 if (pci_intr_map(&sc->sc_pa, &ih)) { 934 aprint_error_dev(sc->sc_dev, "couldn't map interrupt\n"); 935 return; 936 } 937 intrstr = pci_intr_string(pc, ih); 938 939 /* 940 * XXX pccbbintr should be called under the priority lower 941 * than any other hard interrupts. 942 */ 943 KASSERT(sc->sc_ih == NULL); 944 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 945 946 if (sc->sc_ih == NULL) { 947 aprint_error_dev(sc->sc_dev, "couldn't establish interrupt"); 948 if (intrstr != NULL) 949 aprint_error(" at %s\n", intrstr); 950 else 951 aprint_error("\n"); 952 return; 953 } 954 955 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 956 957 /* CSC Interrupt: Card detect and power cycle interrupts on */ 958 sockmask = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 959 sockmask |= CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | 960 CB_SOCKET_MASK_POWER; 961 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, sockmask); 962 /* reset interrupt */ 963 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 964 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 965 } 966 967 /* 968 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 969 * struct pcmciabus_attach_args *paa) 970 * 971 * This function attaches 16-bit PCcard bus. 972 */ 973 STATIC void 974 pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 975 struct pcmciabus_attach_args *paa) 976 { 977 #if rbus 978 rbus_tag_t rb; 979 #endif 980 /* 981 * We need to do a few things here: 982 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 983 * setting the IRQ numbers to 0. 984 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 985 * routing of CSC interrupts (e.g. card removal) to PCI while in 986 * PCMCIA mode. We just leave this set all the time. 987 * 3) Enable card insertion/removal interrupts in case the chip also 988 * needs that while in PCMCIA mode. 989 * 4) Clear any pending CSC interrupt. 990 */ 991 Pcic_write(sc, PCIC_INTR, PCIC_INTR_ENABLE); 992 if (sc->sc_chipset == CB_TI113X) { 993 Pcic_write(sc, PCIC_CSC_INTR, 0); 994 } else { 995 Pcic_write(sc, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 996 Pcic_read(sc, PCIC_CSC); 997 } 998 999 /* initialize pcmcia bus attachment */ 1000 paa->paa_busname = "pcmcia"; 1001 paa->pct = &pccbb_pcmcia_funcs; 1002 paa->pch = sc; 1003 paa->iobase = 0; /* I don't use them */ 1004 paa->iosize = 0; 1005 #if rbus 1006 rb = sc->sc_rbus_iot; 1007 paa->iobase = rb->rb_start + rb->rb_offset; 1008 paa->iosize = rb->rb_end - rb->rb_start; 1009 #endif 1010 1011 return; 1012 } 1013 1014 /* 1015 * int pccbbintr(arg) 1016 * void *arg; 1017 * This routine handles the interrupt from Yenta PCI-CardBus bridge 1018 * itself. 1019 */ 1020 int 1021 pccbbintr(void *arg) 1022 { 1023 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1024 struct cardslot_softc *csc; 1025 u_int32_t sockevent, sockstate; 1026 bus_space_tag_t memt = sc->sc_base_memt; 1027 bus_space_handle_t memh = sc->sc_base_memh; 1028 1029 if (!device_has_power(sc->sc_dev)) 1030 return 0; 1031 1032 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 1033 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 1034 Pcic_read(sc, PCIC_CSC); 1035 1036 if (sockevent != 0) { 1037 aprint_debug("%s: enter sockevent %" PRIx32 "\n", __func__, 1038 sockevent); 1039 } 1040 1041 /* XXX sockevent == CB_SOCKET_EVENT_CSTS|CB_SOCKET_EVENT_POWER 1042 * does occur in the wild. Check for a _POWER event before 1043 * possibly exiting because of an _CSTS event. 1044 */ 1045 if (sockevent & CB_SOCKET_EVENT_POWER) { 1046 DPRINTF(("Powercycling because of socket event\n")); 1047 /* XXX: Does not happen when attaching a 16-bit card */ 1048 mutex_enter(&sc->sc_pwr_mtx); 1049 sc->sc_pwrcycle++; 1050 cv_signal(&sc->sc_pwr_cv); 1051 mutex_exit(&sc->sc_pwr_mtx); 1052 } 1053 1054 /* Sometimes a change of CSTSCHG# accompanies the first 1055 * interrupt from an Atheros WLAN. That generates a 1056 * CB_SOCKET_EVENT_CSTS event on the bridge. The event 1057 * isn't interesting to pccbb(4), so we used to ignore the 1058 * interrupt. Now, let the child devices try to handle 1059 * the interrupt, instead. The Atheros NIC produces 1060 * interrupts more reliably, now: used to be that it would 1061 * only interrupt if the driver avoided powering down the 1062 * NIC's cardslot, and then the NIC would only work after 1063 * it was reset a second time. 1064 */ 1065 if (sockevent == 0 || 1066 (sockevent & ~(CB_SOCKET_EVENT_POWER|CB_SOCKET_EVENT_CD)) != 0) { 1067 /* This intr is not for me: it may be for my child devices. */ 1068 if (sc->sc_pil_intr_enable) { 1069 return pccbbintr_function(sc); 1070 } else { 1071 return 0; 1072 } 1073 } 1074 1075 if (sockevent & CB_SOCKET_EVENT_CD) { 1076 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1077 if (0x00 != (sockstate & CB_SOCKET_STAT_CD)) { 1078 /* A card should be removed. */ 1079 if (sc->sc_flags & CBB_CARDEXIST) { 1080 DPRINTF(("%s: 0x%08x", 1081 device_xname(sc->sc_dev), sockevent)); 1082 DPRINTF((" card removed, 0x%08x\n", sockstate)); 1083 sc->sc_flags &= ~CBB_CARDEXIST; 1084 if ((csc = sc->sc_csc) == NULL) 1085 ; 1086 else if (csc->sc_status & 1087 CARDSLOT_STATUS_CARD_16) { 1088 cardslot_event_throw(csc, 1089 CARDSLOT_EVENT_REMOVAL_16); 1090 } else if (csc->sc_status & 1091 CARDSLOT_STATUS_CARD_CB) { 1092 /* Cardbus intr removed */ 1093 cardslot_event_throw(csc, 1094 CARDSLOT_EVENT_REMOVAL_CB); 1095 } 1096 } else if (sc->sc_flags & CBB_INSERTING) { 1097 sc->sc_flags &= ~CBB_INSERTING; 1098 callout_stop(&sc->sc_insert_ch); 1099 } 1100 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 1101 /* 1102 * The pccbbintr may called from powerdown hook when 1103 * the system resumed, to detect the card 1104 * insertion/removal during suspension. 1105 */ 1106 (sc->sc_flags & CBB_CARDEXIST) == 0) { 1107 if (sc->sc_flags & CBB_INSERTING) { 1108 callout_stop(&sc->sc_insert_ch); 1109 } 1110 callout_schedule(&sc->sc_insert_ch, mstohz(200)); 1111 sc->sc_flags |= CBB_INSERTING; 1112 } 1113 } 1114 1115 return (1); 1116 } 1117 1118 /* 1119 * static int pccbbintr_function(struct pccbb_softc *sc) 1120 * 1121 * This function calls each interrupt handler registered at the 1122 * bridge. The interrupt handlers are called in registered order. 1123 */ 1124 static int 1125 pccbbintr_function(struct pccbb_softc *sc) 1126 { 1127 int retval = 0, val; 1128 struct pccbb_intrhand_list *pil; 1129 int s; 1130 1131 LIST_FOREACH(pil, &sc->sc_pil, pil_next) { 1132 s = splraiseipl(pil->pil_icookie); 1133 val = (*pil->pil_func)(pil->pil_arg); 1134 splx(s); 1135 1136 retval = retval == 1 ? 1 : 1137 retval == 0 ? val : val != 0 ? val : retval; 1138 } 1139 1140 return retval; 1141 } 1142 1143 static void 1144 pci113x_insert(void *arg) 1145 { 1146 struct pccbb_softc *sc = arg; 1147 struct cardslot_softc *csc; 1148 u_int32_t sockevent, sockstate; 1149 1150 if (!(sc->sc_flags & CBB_INSERTING)) { 1151 /* We add a card only under inserting state. */ 1152 return; 1153 } 1154 sc->sc_flags &= ~CBB_INSERTING; 1155 1156 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1157 CB_SOCKET_EVENT); 1158 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1159 CB_SOCKET_STAT); 1160 1161 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1162 DPRINTF(("%s: 0x%08x", device_xname(sc->sc_dev), sockevent)); 1163 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1164 sc->sc_flags |= CBB_CARDEXIST; 1165 /* call pccard interrupt handler here */ 1166 if ((csc = sc->sc_csc) == NULL) 1167 ; 1168 else if (sockstate & CB_SOCKET_STAT_16BIT) { 1169 /* 16-bit card found */ 1170 cardslot_event_throw(csc, CARDSLOT_EVENT_INSERTION_16); 1171 } else if (sockstate & CB_SOCKET_STAT_CB) { 1172 /* cardbus card found */ 1173 cardslot_event_throw(csc, CARDSLOT_EVENT_INSERTION_CB); 1174 } else { 1175 /* who are you? */ 1176 } 1177 } else { 1178 callout_schedule(&sc->sc_insert_ch, mstohz(100)); 1179 } 1180 } 1181 1182 #define PCCBB_PCMCIA_OFFSET 0x800 1183 static u_int8_t 1184 pccbb_pcmcia_read(struct pccbb_softc *sc, int reg) 1185 { 1186 bus_space_barrier(sc->sc_base_memt, sc->sc_base_memh, 1187 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1188 1189 return bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 1190 PCCBB_PCMCIA_OFFSET + reg); 1191 } 1192 1193 static void 1194 pccbb_pcmcia_write(struct pccbb_softc *sc, int reg, u_int8_t val) 1195 { 1196 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 1197 PCCBB_PCMCIA_OFFSET + reg, val); 1198 1199 bus_space_barrier(sc->sc_base_memt, sc->sc_base_memh, 1200 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1201 } 1202 1203 /* 1204 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1205 */ 1206 STATIC int 1207 pccbb_ctrl(cardbus_chipset_tag_t ct, int command) 1208 { 1209 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1210 1211 switch (command) { 1212 case CARDBUS_CD: 1213 if (2 == pccbb_detect_card(sc)) { 1214 int retval = 0; 1215 int status = cb_detect_voltage(sc); 1216 if (PCCARD_VCC_5V & status) { 1217 retval |= CARDBUS_5V_CARD; 1218 } 1219 if (PCCARD_VCC_3V & status) { 1220 retval |= CARDBUS_3V_CARD; 1221 } 1222 if (PCCARD_VCC_XV & status) { 1223 retval |= CARDBUS_XV_CARD; 1224 } 1225 if (PCCARD_VCC_YV & status) { 1226 retval |= CARDBUS_YV_CARD; 1227 } 1228 return retval; 1229 } else { 1230 return 0; 1231 } 1232 case CARDBUS_RESET: 1233 return cb_reset(sc); 1234 case CARDBUS_IO_ENABLE: /* fallthrough */ 1235 case CARDBUS_IO_DISABLE: /* fallthrough */ 1236 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1237 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1238 case CARDBUS_BM_ENABLE: /* fallthrough */ 1239 case CARDBUS_BM_DISABLE: /* fallthrough */ 1240 /* XXX: I think we don't need to call this function below. */ 1241 return pccbb_cardenable(sc, command); 1242 } 1243 1244 return 0; 1245 } 1246 1247 STATIC int 1248 pccbb_power_ct(cardbus_chipset_tag_t ct, int command) 1249 { 1250 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1251 1252 return pccbb_power(sc, command); 1253 } 1254 1255 /* 1256 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1257 * This function returns true when it succeeds and returns false when 1258 * it fails. 1259 */ 1260 STATIC int 1261 pccbb_power(struct pccbb_softc *sc, int command) 1262 { 1263 u_int32_t status, osock_ctrl, sock_ctrl, reg_ctrl; 1264 bus_space_tag_t memt = sc->sc_base_memt; 1265 bus_space_handle_t memh = sc->sc_base_memh; 1266 int on = 0, pwrcycle, times; 1267 struct timeval before, after, diff; 1268 1269 DPRINTF(("pccbb_power: %s and %s [0x%x]\n", 1270 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1271 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1272 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1273 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1274 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1275 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1276 "UNKNOWN", 1277 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1278 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1279 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1280 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1281 "UNKNOWN", command)); 1282 1283 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1284 osock_ctrl = sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1285 1286 switch (command & CARDBUS_VCCMASK) { 1287 case CARDBUS_VCC_UC: 1288 break; 1289 case CARDBUS_VCC_5V: 1290 on++; 1291 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1292 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1293 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1294 } else { 1295 aprint_error_dev(sc->sc_dev, 1296 "BAD voltage request: no 5 V card\n"); 1297 return 0; 1298 } 1299 break; 1300 case CARDBUS_VCC_3V: 1301 on++; 1302 if (CB_SOCKET_STAT_3VCARD & status) { 1303 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1304 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1305 } else { 1306 aprint_error_dev(sc->sc_dev, 1307 "BAD voltage request: no 3.3 V card\n"); 1308 return 0; 1309 } 1310 break; 1311 case CARDBUS_VCC_0V: 1312 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1313 break; 1314 default: 1315 return 0; /* power NEVER changed */ 1316 } 1317 1318 switch (command & CARDBUS_VPPMASK) { 1319 case CARDBUS_VPP_UC: 1320 break; 1321 case CARDBUS_VPP_0V: 1322 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1323 break; 1324 case CARDBUS_VPP_VCC: 1325 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1326 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1327 break; 1328 case CARDBUS_VPP_12V: 1329 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1330 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1331 break; 1332 } 1333 aprint_debug_dev(sc->sc_dev, "osock_ctrl %#" PRIx32 1334 " sock_ctrl %#" PRIx32 "\n", osock_ctrl, sock_ctrl); 1335 1336 microtime(&before); 1337 mutex_enter(&sc->sc_pwr_mtx); 1338 pwrcycle = sc->sc_pwrcycle; 1339 1340 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1341 1342 /* 1343 * Wait as long as 200ms for a power-cycle interrupt. If 1344 * interrupts are enabled, but the socket has already 1345 * changed to the desired status, keep waiting for the 1346 * interrupt. "Consuming" the interrupt in this way keeps 1347 * the interrupt from prematurely waking some subsequent 1348 * pccbb_power call. 1349 * 1350 * XXX Not every bridge interrupts on the ->OFF transition. 1351 * XXX That's ok, we will time-out after 200ms. 1352 * 1353 * XXX The power cycle event will never happen when attaching 1354 * XXX a 16-bit card. That's ok, we will time-out after 1355 * XXX 200ms. 1356 */ 1357 for (times = 5; --times >= 0; ) { 1358 if (cold) 1359 DELAY(40 * 1000); 1360 else { 1361 (void)cv_timedwait(&sc->sc_pwr_cv, &sc->sc_pwr_mtx, 1362 mstohz(40)); 1363 if (pwrcycle == sc->sc_pwrcycle) 1364 continue; 1365 } 1366 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1367 if ((status & CB_SOCKET_STAT_PWRCYCLE) != 0 && on) 1368 break; 1369 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0 && !on) 1370 break; 1371 } 1372 mutex_exit(&sc->sc_pwr_mtx); 1373 microtime(&after); 1374 timersub(&after, &before, &diff); 1375 aprint_debug_dev(sc->sc_dev, "wait took%s %lld.%06lds\n", 1376 (on && times < 0) ? " too long" : "", (long long)diff.tv_sec, 1377 (long)diff.tv_usec); 1378 1379 /* 1380 * Ok, wait a bit longer for things to settle. 1381 */ 1382 if (on && sc->sc_chipset == CB_TOPIC95B) 1383 delay_ms(100, sc); 1384 1385 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1386 1387 if (on && sc->sc_chipset != CB_TOPIC95B) { 1388 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0) 1389 aprint_error_dev(sc->sc_dev, "power on failed?\n"); 1390 } 1391 1392 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1393 aprint_error_dev(sc->sc_dev, 1394 "bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1395 sock_ctrl, status); 1396 aprint_error_dev(sc->sc_dev, "disabling socket\n"); 1397 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1398 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1399 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1400 status &= ~CB_SOCKET_STAT_BADVCC; 1401 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, status); 1402 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1403 CB_SOCKET_STAT)); 1404 return 0; 1405 } 1406 1407 if (sc->sc_chipset == CB_TOPIC97) { 1408 reg_ctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL); 1409 reg_ctrl &= ~TOPIC97_REG_CTRL_TESTMODE; 1410 if ((command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V) 1411 reg_ctrl &= ~TOPIC97_REG_CTRL_CLKRUN_ENA; 1412 else 1413 reg_ctrl |= TOPIC97_REG_CTRL_CLKRUN_ENA; 1414 pci_conf_write(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL, reg_ctrl); 1415 } 1416 1417 return 1; /* power changed correctly */ 1418 } 1419 1420 /* 1421 * static int pccbb_detect_card(struct pccbb_softc *sc) 1422 * return value: 0 if no card exists. 1423 * 1 if 16-bit card exists. 1424 * 2 if cardbus card exists. 1425 */ 1426 static int 1427 pccbb_detect_card(struct pccbb_softc *sc) 1428 { 1429 bus_space_handle_t base_memh = sc->sc_base_memh; 1430 bus_space_tag_t base_memt = sc->sc_base_memt; 1431 u_int32_t sockstat = 1432 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1433 int retval = 0; 1434 1435 /* CD1 and CD2 asserted */ 1436 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1437 /* card must be present */ 1438 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1439 /* NOTACARD DEASSERTED */ 1440 if (CB_SOCKET_STAT_CB & sockstat) { 1441 /* CardBus mode */ 1442 retval = 2; 1443 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1444 /* 16-bit mode */ 1445 retval = 1; 1446 } 1447 } 1448 } 1449 return retval; 1450 } 1451 1452 /* 1453 * STATIC int cb_reset(struct pccbb_softc *sc) 1454 * This function resets CardBus card. 1455 */ 1456 STATIC int 1457 cb_reset(struct pccbb_softc *sc) 1458 { 1459 /* 1460 * Reset Assert at least 20 ms 1461 * Some machines request longer duration. 1462 */ 1463 int reset_duration = 1464 (sc->sc_chipset == CB_RX5C47X ? 400 : 50); 1465 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1466 aprint_debug("%s: enter bcr %" PRIx32 "\n", __func__, bcr); 1467 1468 /* Reset bit Assert (bit 6 at 0x3E) */ 1469 bcr |= PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT; 1470 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr); 1471 aprint_debug("%s: wrote bcr %" PRIx32 "\n", __func__, bcr); 1472 delay_ms(reset_duration, sc); 1473 1474 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1475 /* Reset bit Deassert (bit 6 at 0x3E) */ 1476 bcr &= ~(PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT); 1477 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, 1478 bcr); 1479 aprint_debug("%s: wrote bcr %" PRIx32 "\n", __func__, bcr); 1480 delay_ms(reset_duration, sc); 1481 aprint_debug("%s: end of delay\n", __func__); 1482 } 1483 /* No card found on the slot. Keep Reset. */ 1484 return 1; 1485 } 1486 1487 /* 1488 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1489 * This function detect card Voltage. 1490 */ 1491 STATIC int 1492 cb_detect_voltage(struct pccbb_softc *sc) 1493 { 1494 u_int32_t psr; /* socket present-state reg */ 1495 bus_space_tag_t iot = sc->sc_base_memt; 1496 bus_space_handle_t ioh = sc->sc_base_memh; 1497 int vol = PCCARD_VCC_UKN; /* set 0 */ 1498 1499 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1500 1501 if (0x400u & psr) { 1502 vol |= PCCARD_VCC_5V; 1503 } 1504 if (0x800u & psr) { 1505 vol |= PCCARD_VCC_3V; 1506 } 1507 1508 return vol; 1509 } 1510 1511 STATIC int 1512 cbbprint(void *aux, const char *pcic) 1513 { 1514 #if 0 1515 struct cbslot_attach_args *cba = aux; 1516 1517 if (cba->cba_slot >= 0) { 1518 aprint_normal(" slot %d", cba->cba_slot); 1519 } 1520 #endif 1521 return UNCONF; 1522 } 1523 1524 /* 1525 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1526 * This function enables and disables the card 1527 */ 1528 STATIC int 1529 pccbb_cardenable(struct pccbb_softc *sc, int function) 1530 { 1531 u_int32_t command = 1532 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1533 1534 DPRINTF(("pccbb_cardenable:")); 1535 switch (function) { 1536 case CARDBUS_IO_ENABLE: 1537 command |= PCI_COMMAND_IO_ENABLE; 1538 break; 1539 case CARDBUS_IO_DISABLE: 1540 command &= ~PCI_COMMAND_IO_ENABLE; 1541 break; 1542 case CARDBUS_MEM_ENABLE: 1543 command |= PCI_COMMAND_MEM_ENABLE; 1544 break; 1545 case CARDBUS_MEM_DISABLE: 1546 command &= ~PCI_COMMAND_MEM_ENABLE; 1547 break; 1548 case CARDBUS_BM_ENABLE: 1549 command |= PCI_COMMAND_MASTER_ENABLE; 1550 break; 1551 case CARDBUS_BM_DISABLE: 1552 command &= ~PCI_COMMAND_MASTER_ENABLE; 1553 break; 1554 default: 1555 return 0; 1556 } 1557 1558 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1559 DPRINTF((" command reg 0x%x\n", command)); 1560 return 1; 1561 } 1562 1563 #if !rbus 1564 static int 1565 pccbb_io_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 1566 { 1567 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1568 int basereg; 1569 int limitreg; 1570 1571 if ((win < 0) || (win > 2)) { 1572 #if defined DIAGNOSTIC 1573 printf("cardbus_io_open: window out of range %d\n", win); 1574 #endif 1575 return 0; 1576 } 1577 1578 basereg = win * 8 + PCI_CB_IOBASE0; 1579 limitreg = win * 8 + PCI_CB_IOLIMIT0; 1580 1581 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1582 start, basereg, end, limitreg)); 1583 1584 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1585 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1586 return 1; 1587 } 1588 1589 /* 1590 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1591 */ 1592 static int 1593 pccbb_io_close(cardbus_chipset_tag_t ct, int win) 1594 { 1595 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1596 int basereg; 1597 int limitreg; 1598 1599 if ((win < 0) || (win > 2)) { 1600 #if defined DIAGNOSTIC 1601 printf("cardbus_io_close: window out of range %d\n", win); 1602 #endif 1603 return 0; 1604 } 1605 1606 basereg = win * 8 + PCI_CB_IOBASE0; 1607 limitreg = win * 8 + PCI_CB_IOLIMIT0; 1608 1609 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1610 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1611 return 1; 1612 } 1613 1614 static int 1615 pccbb_mem_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 1616 { 1617 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1618 int basereg; 1619 int limitreg; 1620 1621 if ((win < 0) || (win > 2)) { 1622 #if defined DIAGNOSTIC 1623 printf("cardbus_mem_open: window out of range %d\n", win); 1624 #endif 1625 return 0; 1626 } 1627 1628 basereg = win * 8 + PCI_CB_MEMBASE0; 1629 limitreg = win * 8 + PCI_CB_MEMLIMIT0; 1630 1631 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1632 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1633 return 1; 1634 } 1635 1636 static int 1637 pccbb_mem_close(cardbus_chipset_tag_t ct, int win) 1638 { 1639 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1640 int basereg; 1641 int limitreg; 1642 1643 if ((win < 0) || (win > 2)) { 1644 #if defined DIAGNOSTIC 1645 printf("cardbus_mem_close: window out of range %d\n", win); 1646 #endif 1647 return 0; 1648 } 1649 1650 basereg = win * 8 + PCI_CB_MEMBASE0; 1651 limitreg = win * 8 + PCI_CB_MEMLIMIT0; 1652 1653 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1654 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1655 return 1; 1656 } 1657 #endif 1658 1659 /* 1660 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1661 * int irq, 1662 * int level, 1663 * int (* func)(void *), 1664 * void *arg) 1665 * 1666 * This function registers an interrupt handler at the bridge, in 1667 * order not to call the interrupt handlers of child devices when 1668 * a card-deletion interrupt occurs. 1669 * 1670 * The arguments irq and level are not used. 1671 */ 1672 static void * 1673 pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, cardbus_intr_line_t irq, 1674 int level, int (*func)(void *), void *arg) 1675 { 1676 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1677 1678 return pccbb_intr_establish(sc, irq, level, func, arg); 1679 } 1680 1681 1682 /* 1683 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1684 * void *ih) 1685 * 1686 * This function removes an interrupt handler pointed by ih. 1687 */ 1688 static void 1689 pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih) 1690 { 1691 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1692 1693 pccbb_intr_disestablish(sc, ih); 1694 } 1695 1696 1697 void 1698 pccbb_intr_route(struct pccbb_softc *sc) 1699 { 1700 pcireg_t bcr, cbctrl; 1701 1702 /* initialize bridge intr routing */ 1703 bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1704 bcr &= ~CB_BCR_INTR_IREQ_ENABLE; 1705 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr); 1706 1707 switch (sc->sc_chipset) { 1708 case CB_TI113X: 1709 cbctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1710 /* functional intr enabled */ 1711 cbctrl |= PCI113X_CBCTRL_PCI_INTR; 1712 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, cbctrl); 1713 break; 1714 default: 1715 break; 1716 } 1717 } 1718 1719 /* 1720 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1721 * int irq, 1722 * int level, 1723 * int (* func)(void *), 1724 * void *arg) 1725 * 1726 * This function registers an interrupt handler at the bridge, in 1727 * order not to call the interrupt handlers of child devices when 1728 * a card-deletion interrupt occurs. 1729 * 1730 * The arguments irq is not used because pccbb selects intr vector. 1731 */ 1732 static void * 1733 pccbb_intr_establish(struct pccbb_softc *sc, cardbus_intr_line_t irq, 1734 int level, int (*func)(void *), void *arg) 1735 { 1736 struct pccbb_intrhand_list *pil, *newpil; 1737 1738 DPRINTF(("pccbb_intr_establish start. %p\n", LIST_FIRST(&sc->sc_pil))); 1739 1740 if (LIST_EMPTY(&sc->sc_pil)) { 1741 pccbb_intr_route(sc); 1742 } 1743 1744 /* 1745 * Allocate a room for interrupt handler structure. 1746 */ 1747 if (NULL == (newpil = 1748 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1749 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1750 return NULL; 1751 } 1752 1753 newpil->pil_func = func; 1754 newpil->pil_arg = arg; 1755 newpil->pil_icookie = makeiplcookie(level); 1756 1757 if (LIST_EMPTY(&sc->sc_pil)) { 1758 LIST_INSERT_HEAD(&sc->sc_pil, newpil, pil_next); 1759 } else { 1760 for (pil = LIST_FIRST(&sc->sc_pil); 1761 LIST_NEXT(pil, pil_next) != NULL; 1762 pil = LIST_NEXT(pil, pil_next)); 1763 LIST_INSERT_AFTER(pil, newpil, pil_next); 1764 } 1765 1766 DPRINTF(("pccbb_intr_establish add pil. %p\n", 1767 LIST_FIRST(&sc->sc_pil))); 1768 1769 return newpil; 1770 } 1771 1772 /* 1773 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1774 * void *ih) 1775 * 1776 * This function removes an interrupt handler pointed by ih. ih 1777 * should be the value returned by cardbus_intr_establish() or 1778 * NULL. 1779 * 1780 * When ih is NULL, this function will do nothing. 1781 */ 1782 static void 1783 pccbb_intr_disestablish(struct pccbb_softc *sc, void *ih) 1784 { 1785 struct pccbb_intrhand_list *pil; 1786 pcireg_t reg; 1787 1788 DPRINTF(("pccbb_intr_disestablish start. %p\n", 1789 LIST_FIRST(&sc->sc_pil))); 1790 1791 if (ih == NULL) { 1792 /* intr handler is not set */ 1793 DPRINTF(("pccbb_intr_disestablish: no ih\n")); 1794 return; 1795 } 1796 1797 #ifdef DIAGNOSTIC 1798 LIST_FOREACH(pil, &sc->sc_pil, pil_next) { 1799 DPRINTF(("pccbb_intr_disestablish: pil %p\n", pil)); 1800 if (pil == ih) { 1801 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1802 break; 1803 } 1804 } 1805 if (pil == NULL) { 1806 panic("pccbb_intr_disestablish: %s cannot find pil %p", 1807 device_xname(sc->sc_dev), ih); 1808 } 1809 #endif 1810 1811 pil = (struct pccbb_intrhand_list *)ih; 1812 LIST_REMOVE(pil, pil_next); 1813 free(pil, M_DEVBUF); 1814 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1815 1816 if (LIST_EMPTY(&sc->sc_pil)) { 1817 /* No interrupt handlers */ 1818 1819 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1820 1821 /* stop routing PCI intr */ 1822 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1823 reg |= CB_BCR_INTR_IREQ_ENABLE; 1824 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, reg); 1825 1826 switch (sc->sc_chipset) { 1827 case CB_TI113X: 1828 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1829 /* functional intr disabled */ 1830 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1831 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1832 break; 1833 default: 1834 break; 1835 } 1836 } 1837 } 1838 1839 #if defined SHOW_REGS 1840 static void 1841 cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, bus_space_tag_t memt, 1842 bus_space_handle_t memh) 1843 { 1844 int i; 1845 printf("PCI config regs:"); 1846 for (i = 0; i < 0x50; i += 4) { 1847 if (i % 16 == 0) 1848 printf("\n 0x%02x:", i); 1849 printf(" %08x", pci_conf_read(pc, tag, i)); 1850 } 1851 for (i = 0x80; i < 0xb0; i += 4) { 1852 if (i % 16 == 0) 1853 printf("\n 0x%02x:", i); 1854 printf(" %08x", pci_conf_read(pc, tag, i)); 1855 } 1856 1857 if (memh == 0) { 1858 printf("\n"); 1859 return; 1860 } 1861 1862 printf("\nsocket regs:"); 1863 for (i = 0; i <= 0x10; i += 0x04) 1864 printf(" %08x", bus_space_read_4(memt, memh, i)); 1865 printf("\nExCA regs:"); 1866 for (i = 0; i < 0x08; ++i) 1867 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1868 printf("\n"); 1869 return; 1870 } 1871 #endif 1872 1873 /* 1874 * static pcitag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1875 * int busno, int function) 1876 * This is the function to make a tag to access config space of 1877 * a CardBus Card. It works same as pci_conf_read. 1878 */ 1879 static pcitag_t 1880 pccbb_make_tag(cardbus_chipset_tag_t cc, int busno, int function) 1881 { 1882 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1883 1884 return pci_make_tag(sc->sc_pc, busno, 0, function); 1885 } 1886 1887 /* 1888 * pccbb_conf_read 1889 * 1890 * This is the function to read the config space of a CardBus card. 1891 * It works the same as pci_conf_read(9). 1892 */ 1893 static pcireg_t 1894 pccbb_conf_read(cardbus_chipset_tag_t cc, pcitag_t tag, int offset) 1895 { 1896 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1897 pcitag_t brtag = sc->sc_tag; 1898 pcireg_t reg; 1899 1900 /* 1901 * clear cardbus master abort status; it is OK to write without 1902 * reading before because all bits are r/o or w1tc 1903 */ 1904 pci_conf_write(sc->sc_pc, brtag, PCI_CBB_SECSTATUS, 1905 CBB_SECSTATUS_CBMABORT); 1906 reg = pci_conf_read(sc->sc_pc, tag, offset); 1907 /* check cardbus master abort status */ 1908 if (pci_conf_read(sc->sc_pc, brtag, PCI_CBB_SECSTATUS) 1909 & CBB_SECSTATUS_CBMABORT) 1910 return (0xffffffff); 1911 return reg; 1912 } 1913 1914 /* 1915 * pccbb_conf_write 1916 * 1917 * This is the function to write the config space of a CardBus 1918 * card. It works the same as pci_conf_write(9). 1919 */ 1920 static void 1921 pccbb_conf_write(cardbus_chipset_tag_t cc, pcitag_t tag, int reg, pcireg_t val) 1922 { 1923 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1924 1925 pci_conf_write(sc->sc_pc, tag, reg, val); 1926 } 1927 1928 #if 0 1929 STATIC int 1930 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1931 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 1932 int speed, int flags, 1933 bus_space_handle_t * iohp) 1934 #endif 1935 /* 1936 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1937 * bus_addr_t start, bus_size_t size, 1938 * bus_size_t align, 1939 * struct pcmcia_io_handle *pcihp 1940 * 1941 * This function only allocates I/O region for pccard. This function 1942 * never maps the allocated region to pccard I/O area. 1943 * 1944 * XXX: The interface of this function is not very good, I believe. 1945 */ 1946 STATIC int 1947 pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, 1948 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 1949 { 1950 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 1951 bus_addr_t ioaddr; 1952 int flags = 0; 1953 bus_space_tag_t iot; 1954 bus_space_handle_t ioh; 1955 bus_addr_t mask; 1956 #if rbus 1957 rbus_tag_t rb; 1958 #endif 1959 if (align == 0) { 1960 align = size; /* XXX: funny??? */ 1961 } 1962 1963 if (start != 0) { 1964 /* XXX: assume all card decode lower 10 bits by its hardware */ 1965 mask = 0x3ff; 1966 /* enforce to use only masked address */ 1967 start &= mask; 1968 } else { 1969 /* 1970 * calculate mask: 1971 * 1. get the most significant bit of size (call it msb). 1972 * 2. compare msb with the value of size. 1973 * 3. if size is larger, shift msb left once. 1974 * 4. obtain mask value to decrement msb. 1975 */ 1976 bus_size_t size_tmp = size; 1977 int shifts = 0; 1978 1979 mask = 1; 1980 while (size_tmp) { 1981 ++shifts; 1982 size_tmp >>= 1; 1983 } 1984 mask = (1 << shifts); 1985 if (mask < size) { 1986 mask <<= 1; 1987 } 1988 --mask; 1989 } 1990 1991 /* 1992 * Allocate some arbitrary I/O space. 1993 */ 1994 1995 iot = sc->sc_iot; 1996 1997 #if rbus 1998 rb = sc->sc_rbus_iot; 1999 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 2000 return 1; 2001 } 2002 DPRINTF(("pccbb_pcmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2003 (u_long) ioaddr, (u_long) size)); 2004 #else 2005 if (start) { 2006 ioaddr = start; 2007 if (bus_space_map(iot, start, size, 0, &ioh)) { 2008 return 1; 2009 } 2010 DPRINTF(("pccbb_pcmcia_io_alloc map port 0x%lx+0x%lx\n", 2011 (u_long) ioaddr, (u_long) size)); 2012 } else { 2013 flags |= PCMCIA_IO_ALLOCATED; 2014 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 2015 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 2016 size, align, 0, 0, &ioaddr, &ioh)) { 2017 /* No room be able to be get. */ 2018 return 1; 2019 } 2020 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2021 (u_long) ioaddr, (u_long) size)); 2022 } 2023 #endif 2024 2025 pcihp->iot = iot; 2026 pcihp->ioh = ioh; 2027 pcihp->addr = ioaddr; 2028 pcihp->size = size; 2029 pcihp->flags = flags; 2030 2031 return 0; 2032 } 2033 2034 /* 2035 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2036 * struct pcmcia_io_handle *pcihp) 2037 * 2038 * This function only frees I/O region for pccard. 2039 * 2040 * XXX: The interface of this function is not very good, I believe. 2041 */ 2042 void 2043 pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2044 struct pcmcia_io_handle *pcihp) 2045 { 2046 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2047 #if !rbus 2048 bus_space_tag_t iot = pcihp->iot; 2049 #endif 2050 bus_space_handle_t ioh = pcihp->ioh; 2051 bus_size_t size = pcihp->size; 2052 2053 #if rbus 2054 rbus_tag_t rb = sc->sc_rbus_iot; 2055 2056 rbus_space_free(rb, ioh, size, NULL); 2057 #else 2058 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 2059 bus_space_free(iot, ioh, size); 2060 else 2061 bus_space_unmap(iot, ioh, size); 2062 #endif 2063 } 2064 2065 /* 2066 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 2067 * bus_addr_t offset, bus_size_t size, 2068 * struct pcmcia_io_handle *pcihp, 2069 * int *windowp) 2070 * 2071 * This function maps the allocated I/O region to pccard. This function 2072 * never allocates any I/O region for pccard I/O area. I don't 2073 * understand why the original authors of pcmciabus separated alloc and 2074 * map. I believe the two must be unite. 2075 * 2076 * XXX: no wait timing control? 2077 */ 2078 int 2079 pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, bus_addr_t offset, 2080 bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp) 2081 { 2082 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2083 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2084 bus_addr_t ioaddr = pcihp->addr + offset; 2085 int i, win; 2086 #if defined CBB_DEBUG 2087 static const char *width_names[] = { "dynamic", "io8", "io16" }; 2088 #endif 2089 2090 /* Sanity check I/O handle. */ 2091 2092 if (!bus_space_is_equal(sc->sc_iot, pcihp->iot)) { 2093 panic("pccbb_pcmcia_io_map iot is bogus"); 2094 } 2095 2096 /* XXX Sanity check offset/size. */ 2097 2098 win = -1; 2099 for (i = 0; i < PCIC_IO_WINS; i++) { 2100 if ((ph->ioalloc & (1 << i)) == 0) { 2101 win = i; 2102 ph->ioalloc |= (1 << i); 2103 break; 2104 } 2105 } 2106 2107 if (win == -1) { 2108 return 1; 2109 } 2110 2111 *windowp = win; 2112 2113 /* XXX this is pretty gross */ 2114 2115 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2116 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2117 2118 /* XXX wtf is this doing here? */ 2119 2120 #if 0 2121 printf(" port 0x%lx", (u_long) ioaddr); 2122 if (size > 1) { 2123 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2124 } 2125 #endif 2126 2127 ph->io[win].addr = ioaddr; 2128 ph->io[win].size = size; 2129 ph->io[win].width = width; 2130 2131 /* actual dirty register-value changing in the function below. */ 2132 pccbb_pcmcia_do_io_map(sc, win); 2133 2134 return 0; 2135 } 2136 2137 /* 2138 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2139 * 2140 * This function changes register-value to map I/O region for pccard. 2141 */ 2142 static void 2143 pccbb_pcmcia_do_io_map(struct pccbb_softc *sc, int win) 2144 { 2145 static u_int8_t pcic_iowidth[3] = { 2146 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2147 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2148 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2149 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2150 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2151 }; 2152 2153 #define PCIC_SIA_START_LOW 0 2154 #define PCIC_SIA_START_HIGH 1 2155 #define PCIC_SIA_STOP_LOW 2 2156 #define PCIC_SIA_STOP_HIGH 3 2157 2158 int regbase_win = 0x8 + win * 0x04; 2159 u_int8_t ioctl, enable; 2160 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2161 2162 DPRINTF(("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx " 2163 "width %d\n", win, (unsigned long)ph->io[win].addr, 2164 (unsigned long)ph->io[win].size, ph->io[win].width * 8)); 2165 2166 Pcic_write(sc, regbase_win + PCIC_SIA_START_LOW, 2167 ph->io[win].addr & 0xff); 2168 Pcic_write(sc, regbase_win + PCIC_SIA_START_HIGH, 2169 (ph->io[win].addr >> 8) & 0xff); 2170 2171 Pcic_write(sc, regbase_win + PCIC_SIA_STOP_LOW, 2172 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2173 Pcic_write(sc, regbase_win + PCIC_SIA_STOP_HIGH, 2174 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2175 2176 ioctl = Pcic_read(sc, PCIC_IOCTL); 2177 enable = Pcic_read(sc, PCIC_ADDRWIN_ENABLE); 2178 switch (win) { 2179 case 0: 2180 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2181 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2182 PCIC_IOCTL_IO0_DATASIZE_MASK); 2183 ioctl |= pcic_iowidth[ph->io[win].width]; 2184 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2185 break; 2186 case 1: 2187 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2188 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2189 PCIC_IOCTL_IO1_DATASIZE_MASK); 2190 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2191 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2192 break; 2193 } 2194 Pcic_write(sc, PCIC_IOCTL, ioctl); 2195 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, enable); 2196 #if defined(CBB_DEBUG) 2197 { 2198 u_int8_t start_low = 2199 Pcic_read(sc, regbase_win + PCIC_SIA_START_LOW); 2200 u_int8_t start_high = 2201 Pcic_read(sc, regbase_win + PCIC_SIA_START_HIGH); 2202 u_int8_t stop_low = 2203 Pcic_read(sc, regbase_win + PCIC_SIA_STOP_LOW); 2204 u_int8_t stop_high = 2205 Pcic_read(sc, regbase_win + PCIC_SIA_STOP_HIGH); 2206 printf("pccbb_pcmcia_do_io_map start %02x %02x, " 2207 "stop %02x %02x, ioctl %02x enable %02x\n", 2208 start_low, start_high, stop_low, stop_high, ioctl, enable); 2209 } 2210 #endif 2211 } 2212 2213 /* 2214 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2215 * 2216 * This function unmaps I/O region. No return value. 2217 */ 2218 STATIC void 2219 pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t pch, int win) 2220 { 2221 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2222 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2223 int reg; 2224 2225 if (win >= PCIC_IO_WINS || win < 0) { 2226 panic("pccbb_pcmcia_io_unmap: window out of range"); 2227 } 2228 2229 reg = Pcic_read(sc, PCIC_ADDRWIN_ENABLE); 2230 switch (win) { 2231 case 0: 2232 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2233 break; 2234 case 1: 2235 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2236 break; 2237 } 2238 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, reg); 2239 2240 ph->ioalloc &= ~(1 << win); 2241 } 2242 2243 static int 2244 pccbb_pcmcia_wait_ready(struct pccbb_softc *sc) 2245 { 2246 u_int8_t stat; 2247 int i; 2248 2249 /* wait an initial 10ms for quick cards */ 2250 stat = Pcic_read(sc, PCIC_IF_STATUS); 2251 if (stat & PCIC_IF_STATUS_READY) 2252 return (0); 2253 pccbb_pcmcia_delay(sc, 10, "pccwr0"); 2254 for (i = 0; i < 50; i++) { 2255 stat = Pcic_read(sc, PCIC_IF_STATUS); 2256 if (stat & PCIC_IF_STATUS_READY) 2257 return (0); 2258 if ((stat & PCIC_IF_STATUS_CARDDETECT_MASK) != 2259 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2260 return (ENXIO); 2261 /* wait .1s (100ms) each iteration now */ 2262 pccbb_pcmcia_delay(sc, 100, "pccwr1"); 2263 } 2264 2265 printf("pccbb_pcmcia_wait_ready: ready never happened, status=%02x\n", stat); 2266 return (EWOULDBLOCK); 2267 } 2268 2269 /* 2270 * Perform long (msec order) delay. timo is in milliseconds. 2271 */ 2272 static void 2273 pccbb_pcmcia_delay(struct pccbb_softc *sc, int timo, const char *wmesg) 2274 { 2275 #ifdef DIAGNOSTIC 2276 if (timo <= 0) 2277 panic("pccbb_pcmcia_delay: called with timeout %d", timo); 2278 if (!curlwp) 2279 panic("pccbb_pcmcia_delay: called in interrupt context"); 2280 #endif 2281 DPRINTF(("pccbb_pcmcia_delay: \"%s\", sleep %d ms\n", wmesg, timo)); 2282 kpause(wmesg, false, max(mstohz(timo), 1), NULL); 2283 } 2284 2285 /* 2286 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2287 * 2288 * This function enables the card. All information is stored in 2289 * the first argument, pcmcia_chipset_handle_t. 2290 */ 2291 STATIC void 2292 pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2293 { 2294 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2295 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2296 pcireg_t spsr; 2297 int voltage; 2298 int win; 2299 u_int8_t power, intr; 2300 #ifdef DIAGNOSTIC 2301 int reg; 2302 #endif 2303 2304 /* this bit is mostly stolen from pcic_attach_card */ 2305 2306 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2307 2308 /* get card Vcc info */ 2309 spsr = 2310 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2311 CB_SOCKET_STAT); 2312 if (spsr & CB_SOCKET_STAT_5VCARD) { 2313 DPRINTF(("5V card\n")); 2314 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2315 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2316 DPRINTF(("3V card\n")); 2317 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2318 } else { 2319 DPRINTF(("?V card, 0x%x\n", spsr)); /* XXX */ 2320 return; 2321 } 2322 2323 /* disable interrupts; assert RESET */ 2324 intr = Pcic_read(sc, PCIC_INTR); 2325 intr &= PCIC_INTR_ENABLE; 2326 Pcic_write(sc, PCIC_INTR, intr); 2327 2328 /* zero out the address windows */ 2329 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, 0); 2330 2331 /* power down the socket to reset it, clear the card reset pin */ 2332 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2333 2334 /* power off; assert output enable bit */ 2335 power = PCIC_PWRCTL_OE; 2336 Pcic_write(sc, PCIC_PWRCTL, power); 2337 2338 /* power up the socket */ 2339 if (pccbb_power(sc, voltage) == 0) 2340 return; 2341 2342 /* 2343 * Table 4-18 and figure 4-6 of the PC Card specifiction say: 2344 * Vcc Rising Time (Tpr) = 100ms (handled in pccbb_power() above) 2345 * RESET Width (Th (Hi-z RESET)) = 1ms 2346 * RESET Width (Tw (RESET)) = 10us 2347 * 2348 * some machines require some more time to be settled 2349 * for example old toshiba topic bridges! 2350 * (100ms is added here). 2351 */ 2352 pccbb_pcmcia_delay(sc, 200 + 1, "pccen1"); 2353 2354 /* negate RESET */ 2355 intr |= PCIC_INTR_RESET; 2356 Pcic_write(sc, PCIC_INTR, intr); 2357 2358 /* 2359 * RESET Setup Time (Tsu (RESET)) = 20ms 2360 */ 2361 pccbb_pcmcia_delay(sc, 20, "pccen2"); 2362 2363 #ifdef DIAGNOSTIC 2364 reg = Pcic_read(sc, PCIC_IF_STATUS); 2365 if ((reg & PCIC_IF_STATUS_POWERACTIVE) == 0) 2366 printf("pccbb_pcmcia_socket_enable: no power, status=%x\n", reg); 2367 #endif 2368 2369 /* wait for the chip to finish initializing */ 2370 if (pccbb_pcmcia_wait_ready(sc)) { 2371 #ifdef DIAGNOSTIC 2372 printf("pccbb_pcmcia_socket_enable: never became ready\n"); 2373 #endif 2374 /* XXX return a failure status?? */ 2375 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2376 Pcic_write(sc, PCIC_PWRCTL, 0); 2377 return; 2378 } 2379 2380 /* reinstall all the memory and io mappings */ 2381 for (win = 0; win < PCIC_MEM_WINS; ++win) 2382 if (ph->memalloc & (1 << win)) 2383 pccbb_pcmcia_do_mem_map(sc, win); 2384 for (win = 0; win < PCIC_IO_WINS; ++win) 2385 if (ph->ioalloc & (1 << win)) 2386 pccbb_pcmcia_do_io_map(sc, win); 2387 } 2388 2389 /* 2390 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2391 * 2392 * This function disables the card. All information is stored in 2393 * the first argument, pcmcia_chipset_handle_t. 2394 */ 2395 STATIC void 2396 pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t pch) 2397 { 2398 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2399 u_int8_t intr; 2400 2401 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2402 2403 /* disable interrupts; assert RESET */ 2404 intr = Pcic_read(sc, PCIC_INTR); 2405 intr &= PCIC_INTR_ENABLE; 2406 Pcic_write(sc, PCIC_INTR, intr); 2407 2408 /* zero out the address windows */ 2409 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, 0); 2410 2411 /* power down the socket to reset it, clear the card reset pin */ 2412 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2413 2414 /* disable socket: negate output enable bit and power off */ 2415 Pcic_write(sc, PCIC_PWRCTL, 0); 2416 2417 /* 2418 * Vcc Falling Time (Tpf) = 300ms 2419 */ 2420 pccbb_pcmcia_delay(sc, 300, "pccwr1"); 2421 } 2422 2423 STATIC void 2424 pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t pch, int type) 2425 { 2426 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2427 u_int8_t intr; 2428 2429 /* set the card type */ 2430 2431 intr = Pcic_read(sc, PCIC_INTR); 2432 intr &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_CARDTYPE_MASK); 2433 if (type == PCMCIA_IFTYPE_IO) 2434 intr |= PCIC_INTR_CARDTYPE_IO; 2435 else 2436 intr |= PCIC_INTR_CARDTYPE_MEM; 2437 Pcic_write(sc, PCIC_INTR, intr); 2438 2439 DPRINTF(("%s: pccbb_pcmcia_socket_settype type %s %02x\n", 2440 device_xname(sc->sc_dev), 2441 ((type == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2442 } 2443 2444 /* 2445 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2446 * 2447 * This function detects whether a card is in the slot or not. 2448 * If a card is inserted, return 1. Otherwise, return 0. 2449 */ 2450 STATIC int 2451 pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch) 2452 { 2453 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2454 2455 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2456 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2457 } 2458 2459 #if 0 2460 STATIC int 2461 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2462 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2463 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2464 #endif 2465 /* 2466 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2467 * bus_size_t size, 2468 * struct pcmcia_mem_handle *pcmhp) 2469 * 2470 * This function only allocates memory region for pccard. This 2471 * function never maps the allocated region to pccard memory area. 2472 * 2473 * XXX: Why the argument of start address is not in? 2474 */ 2475 STATIC int 2476 pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 2477 struct pcmcia_mem_handle *pcmhp) 2478 { 2479 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2480 bus_space_handle_t memh; 2481 bus_addr_t addr; 2482 bus_size_t sizepg; 2483 #if rbus 2484 rbus_tag_t rb; 2485 #endif 2486 2487 /* Check that the card is still there. */ 2488 if ((Pcic_read(sc, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2489 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2490 return 1; 2491 2492 /* out of sc->memh, allocate as many pages as necessary */ 2493 2494 /* convert size to PCIC pages */ 2495 /* 2496 * This is not enough; when the requested region is on the page 2497 * boundaries, this may calculate wrong result. 2498 */ 2499 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2500 #if 0 2501 if (sizepg > PCIC_MAX_MEM_PAGES) { 2502 return 1; 2503 } 2504 #endif 2505 2506 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2507 return 1; 2508 } 2509 2510 addr = 0; /* XXX gcc -Wuninitialized */ 2511 2512 #if rbus 2513 rb = sc->sc_rbus_memt; 2514 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2515 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2516 &addr, &memh)) { 2517 return 1; 2518 } 2519 #else 2520 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2521 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2522 0, /* boundary */ 2523 0, /* flags */ 2524 &addr, &memh)) { 2525 return 1; 2526 } 2527 #endif 2528 2529 DPRINTF(("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, " 2530 "realsize 0x%lx\n", (unsigned long)addr, (unsigned long)size, 2531 (unsigned long)sizepg * PCIC_MEM_PAGESIZE)); 2532 2533 pcmhp->memt = sc->sc_memt; 2534 pcmhp->memh = memh; 2535 pcmhp->addr = addr; 2536 pcmhp->size = size; 2537 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2538 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2539 pcmhp->mhandle = 0; 2540 /* No offset??? Funny. */ 2541 2542 return 0; 2543 } 2544 2545 /* 2546 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2547 * struct pcmcia_mem_handle *pcmhp) 2548 * 2549 * This function release the memory space allocated by the function 2550 * pccbb_pcmcia_mem_alloc(). 2551 */ 2552 STATIC void 2553 pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2554 struct pcmcia_mem_handle *pcmhp) 2555 { 2556 #if rbus 2557 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2558 2559 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2560 #else 2561 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2562 #endif 2563 } 2564 2565 /* 2566 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2567 * 2568 * This function release the memory space allocated by the function 2569 * pccbb_pcmcia_mem_alloc(). 2570 */ 2571 STATIC void 2572 pccbb_pcmcia_do_mem_map(struct pccbb_softc *sc, int win) 2573 { 2574 int regbase_win; 2575 bus_addr_t phys_addr; 2576 bus_addr_t phys_end; 2577 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2578 2579 #define PCIC_SMM_START_LOW 0 2580 #define PCIC_SMM_START_HIGH 1 2581 #define PCIC_SMM_STOP_LOW 2 2582 #define PCIC_SMM_STOP_HIGH 3 2583 #define PCIC_CMA_LOW 4 2584 #define PCIC_CMA_HIGH 5 2585 2586 u_int8_t start_low, start_high = 0; 2587 u_int8_t stop_low, stop_high; 2588 u_int8_t off_low, off_high; 2589 u_int8_t mem_window; 2590 int reg; 2591 2592 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2593 int mem8 = 2594 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2595 || (kind == PCMCIA_MEM_ATTR); 2596 2597 regbase_win = 0x10 + win * 0x08; 2598 2599 phys_addr = ph->mem[win].addr; 2600 phys_end = phys_addr + ph->mem[win].size; 2601 2602 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2603 (unsigned long)phys_addr, (unsigned long)phys_end, 2604 (unsigned long)ph->mem[win].offset)); 2605 2606 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2607 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2608 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2609 2610 /* bit 19:12 */ 2611 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2612 /* bit 23:20 and bit 7 on */ 2613 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2614 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2615 /* bit 31:24, for 32-bit address */ 2616 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2617 2618 Pcic_write(sc, regbase_win + PCIC_SMM_START_LOW, start_low); 2619 Pcic_write(sc, regbase_win + PCIC_SMM_START_HIGH, start_high); 2620 2621 if (sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2622 Pcic_write(sc, 0x40 + win, mem_window); 2623 } 2624 2625 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2626 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2627 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2628 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2629 2630 Pcic_write(sc, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2631 Pcic_write(sc, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2632 2633 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2634 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2635 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2636 | ((kind == PCMCIA_MEM_ATTR) ? 2637 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2638 2639 Pcic_write(sc, regbase_win + PCIC_CMA_LOW, off_low); 2640 Pcic_write(sc, regbase_win + PCIC_CMA_HIGH, off_high); 2641 2642 reg = Pcic_read(sc, PCIC_ADDRWIN_ENABLE); 2643 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2644 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, reg); 2645 2646 #if defined(CBB_DEBUG) 2647 { 2648 int r1, r2, r3, r4, r5, r6, r7 = 0; 2649 2650 r1 = Pcic_read(sc, regbase_win + PCIC_SMM_START_LOW); 2651 r2 = Pcic_read(sc, regbase_win + PCIC_SMM_START_HIGH); 2652 r3 = Pcic_read(sc, regbase_win + PCIC_SMM_STOP_LOW); 2653 r4 = Pcic_read(sc, regbase_win + PCIC_SMM_STOP_HIGH); 2654 r5 = Pcic_read(sc, regbase_win + PCIC_CMA_LOW); 2655 r6 = Pcic_read(sc, regbase_win + PCIC_CMA_HIGH); 2656 if (sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2657 r7 = Pcic_read(sc, 0x40 + win); 2658 } 2659 2660 printf("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2661 "%02x%02x", win, r1, r2, r3, r4, r5, r6); 2662 if (sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2663 printf(" %02x", r7); 2664 } 2665 printf("\n"); 2666 } 2667 #endif 2668 } 2669 2670 /* 2671 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2672 * bus_addr_t card_addr, bus_size_t size, 2673 * struct pcmcia_mem_handle *pcmhp, 2674 * bus_addr_t *offsetp, int *windowp) 2675 * 2676 * This function maps memory space allocated by the function 2677 * pccbb_pcmcia_mem_alloc(). 2678 */ 2679 STATIC int 2680 pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2681 bus_addr_t card_addr, bus_size_t size, struct pcmcia_mem_handle *pcmhp, 2682 bus_size_t *offsetp, int *windowp) 2683 { 2684 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2685 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2686 bus_addr_t busaddr; 2687 long card_offset; 2688 int win; 2689 2690 /* Check that the card is still there. */ 2691 if ((Pcic_read(sc, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2692 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2693 return 1; 2694 2695 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2696 if ((ph->memalloc & (1 << win)) == 0) { 2697 ph->memalloc |= (1 << win); 2698 break; 2699 } 2700 } 2701 2702 if (win == PCIC_MEM_WINS) { 2703 return 1; 2704 } 2705 2706 *windowp = win; 2707 2708 /* XXX this is pretty gross */ 2709 2710 if (!bus_space_is_equal(sc->sc_memt, pcmhp->memt)) { 2711 panic("pccbb_pcmcia_mem_map memt is bogus"); 2712 } 2713 2714 busaddr = pcmhp->addr; 2715 2716 /* 2717 * compute the address offset to the pcmcia address space for the 2718 * pcic. this is intentionally signed. The masks and shifts below 2719 * will cause TRT to happen in the pcic registers. Deal with making 2720 * sure the address is aligned, and return the alignment offset. 2721 */ 2722 2723 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2724 card_addr -= *offsetp; 2725 2726 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2727 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2728 (u_long) card_addr)); 2729 2730 /* 2731 * include the offset in the size, and decrement size by one, since 2732 * the hw wants start/stop 2733 */ 2734 size += *offsetp - 1; 2735 2736 card_offset = (((long)card_addr) - ((long)busaddr)); 2737 2738 ph->mem[win].addr = busaddr; 2739 ph->mem[win].size = size; 2740 ph->mem[win].offset = card_offset; 2741 ph->mem[win].kind = kind; 2742 2743 pccbb_pcmcia_do_mem_map(sc, win); 2744 2745 return 0; 2746 } 2747 2748 /* 2749 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2750 * int window) 2751 * 2752 * This function unmaps memory space which mapped by the function 2753 * pccbb_pcmcia_mem_map(). 2754 */ 2755 STATIC void 2756 pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, int window) 2757 { 2758 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2759 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2760 int reg; 2761 2762 if (window >= PCIC_MEM_WINS) { 2763 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2764 } 2765 2766 reg = Pcic_read(sc, PCIC_ADDRWIN_ENABLE); 2767 reg &= ~(1 << window); 2768 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, reg); 2769 2770 ph->memalloc &= ~(1 << window); 2771 } 2772 2773 /* 2774 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2775 * struct pcmcia_function *pf, 2776 * int ipl, 2777 * int (*func)(void *), 2778 * void *arg); 2779 * 2780 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2781 */ 2782 STATIC void * 2783 pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2784 struct pcmcia_function *pf, int ipl, int (*func)(void *), void *arg) 2785 { 2786 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2787 2788 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2789 /* what should I do? */ 2790 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2791 DPRINTF(("%s does not provide edge nor pulse " 2792 "interrupt\n", device_xname(sc->sc_dev))); 2793 return NULL; 2794 } 2795 /* 2796 * XXX Noooooo! The interrupt flag must set properly!! 2797 * dumb pcmcia driver!! 2798 */ 2799 } 2800 2801 return pccbb_intr_establish(sc, 0, ipl, func, arg); 2802 } 2803 2804 /* 2805 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2806 * void *ih) 2807 * 2808 * This function disables PC-Card interrupt. 2809 */ 2810 STATIC void 2811 pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 2812 { 2813 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2814 2815 pccbb_intr_disestablish(sc, ih); 2816 } 2817 2818 #if rbus 2819 /* 2820 * static int 2821 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2822 * bus_addr_t addr, bus_size_t size, 2823 * bus_addr_t mask, bus_size_t align, 2824 * int flags, bus_addr_t *addrp; 2825 * bus_space_handle_t *bshp) 2826 * 2827 * This function allocates a portion of memory or io space for 2828 * clients. This function is called from CardBus card drivers. 2829 */ 2830 static int 2831 pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2832 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 2833 int flags, bus_addr_t *addrp, bus_space_handle_t *bshp) 2834 { 2835 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2836 2837 DPRINTF(("pccbb_rbus_cb_space_alloc: addr 0x%lx, size 0x%lx, " 2838 "mask 0x%lx, align 0x%lx\n", (unsigned long)addr, 2839 (unsigned long)size, (unsigned long)mask, (unsigned long)align)); 2840 2841 if (align == 0) { 2842 align = size; 2843 } 2844 2845 if (bus_space_is_equal(rb->rb_bt, sc->sc_memt)) { 2846 if (align < 16) { 2847 return 1; 2848 } 2849 /* 2850 * XXX: align more than 0x1000 to avoid overwrapping 2851 * memory windows for two or more devices. 0x1000 2852 * means memory window's granularity. 2853 * 2854 * Two or more devices should be able to share same 2855 * memory window region. However, overrapping memory 2856 * window is not good because some devices, such as 2857 * 3Com 3C575[BC], have a broken address decoder and 2858 * intrude other's memory region. 2859 */ 2860 if (align < 0x1000) { 2861 align = 0x1000; 2862 } 2863 } else if (bus_space_is_equal(rb->rb_bt, sc->sc_iot)) { 2864 if (align < 4) { 2865 return 1; 2866 } 2867 /* XXX: hack for avoiding ISA image */ 2868 if (mask < 0x0100) { 2869 mask = 0x3ff; 2870 addr = 0x300; 2871 } 2872 2873 } else { 2874 DPRINTF(("pccbb_rbus_cb_space_alloc: Bus space tag 0x%lx is " 2875 "NOT used. io: 0x%lx, mem: 0x%lx\n", 2876 (unsigned long)rb->rb_bt, (unsigned long)sc->sc_iot, 2877 (unsigned long)sc->sc_memt)); 2878 return 1; 2879 /* XXX: panic here? */ 2880 } 2881 2882 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 2883 aprint_normal_dev(sc->sc_dev, "<rbus> no bus space\n"); 2884 return 1; 2885 } 2886 2887 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 2888 2889 return 0; 2890 } 2891 2892 /* 2893 * static int 2894 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 2895 * bus_space_handle_t *bshp, bus_size_t size); 2896 * 2897 * This function is called from CardBus card drivers. 2898 */ 2899 static int 2900 pccbb_rbus_cb_space_free(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2901 bus_space_handle_t bsh, bus_size_t size) 2902 { 2903 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2904 bus_space_tag_t bt = rb->rb_bt; 2905 2906 pccbb_close_win(sc, bt, bsh, size); 2907 2908 if (bus_space_is_equal(bt, sc->sc_memt)) { 2909 } else if (bus_space_is_equal(bt, sc->sc_iot)) { 2910 } else { 2911 return 1; 2912 /* XXX: panic here? */ 2913 } 2914 2915 return rbus_space_free(rb, bsh, size, NULL); 2916 } 2917 #endif /* rbus */ 2918 2919 #if rbus 2920 2921 static int 2922 pccbb_open_win(struct pccbb_softc *sc, bus_space_tag_t bst, bus_addr_t addr, 2923 bus_size_t size, bus_space_handle_t bsh, int flags) 2924 { 2925 struct pccbb_win_chain_head *head; 2926 bus_addr_t align; 2927 2928 head = &sc->sc_iowindow; 2929 align = 0x04; 2930 if (bus_space_is_equal(sc->sc_memt, bst)) { 2931 head = &sc->sc_memwindow; 2932 align = 0x1000; 2933 DPRINTF(("using memory window, 0x%lx 0x%lx 0x%lx\n\n", 2934 (unsigned long)sc->sc_iot, (unsigned long)sc->sc_memt, 2935 (unsigned long)bst)); 2936 } 2937 2938 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 2939 aprint_error_dev(sc->sc_dev, 2940 "pccbb_open_win: %s winlist insert failed\n", 2941 (head == &sc->sc_memwindow) ? "mem" : "io"); 2942 } 2943 pccbb_winset(align, sc, bst); 2944 2945 return 0; 2946 } 2947 2948 static int 2949 pccbb_close_win(struct pccbb_softc *sc, bus_space_tag_t bst, 2950 bus_space_handle_t bsh, bus_size_t size) 2951 { 2952 struct pccbb_win_chain_head *head; 2953 bus_addr_t align; 2954 2955 head = &sc->sc_iowindow; 2956 align = 0x04; 2957 if (bus_space_is_equal(sc->sc_memt, bst)) { 2958 head = &sc->sc_memwindow; 2959 align = 0x1000; 2960 } 2961 2962 if (pccbb_winlist_delete(head, bsh, size)) { 2963 aprint_error_dev(sc->sc_dev, 2964 "pccbb_close_win: %s winlist delete failed\n", 2965 (head == &sc->sc_memwindow) ? "mem" : "io"); 2966 } 2967 pccbb_winset(align, sc, bst); 2968 2969 return 0; 2970 } 2971 2972 static int 2973 pccbb_winlist_insert(struct pccbb_win_chain_head *head, bus_addr_t start, 2974 bus_size_t size, bus_space_handle_t bsh, int flags) 2975 { 2976 struct pccbb_win_chain *chainp, *elem; 2977 2978 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 2979 M_NOWAIT)) == NULL) 2980 return (1); /* fail */ 2981 2982 elem->wc_start = start; 2983 elem->wc_end = start + (size - 1); 2984 elem->wc_handle = bsh; 2985 elem->wc_flags = flags; 2986 2987 TAILQ_FOREACH(chainp, head, wc_list) { 2988 if (chainp->wc_end >= start) 2989 break; 2990 } 2991 if (chainp != NULL) 2992 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 2993 else 2994 TAILQ_INSERT_TAIL(head, elem, wc_list); 2995 return (0); 2996 } 2997 2998 static int 2999 pccbb_winlist_delete(struct pccbb_win_chain_head *head, bus_space_handle_t bsh, 3000 bus_size_t size) 3001 { 3002 struct pccbb_win_chain *chainp; 3003 3004 TAILQ_FOREACH(chainp, head, wc_list) { 3005 if (memcmp(&chainp->wc_handle, &bsh, sizeof(bsh)) == 0) 3006 break; 3007 } 3008 if (chainp == NULL) 3009 return 1; /* fail: no candidate to remove */ 3010 3011 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 3012 printf("pccbb_winlist_delete: window 0x%lx size " 3013 "inconsistent: 0x%lx, 0x%lx\n", 3014 (unsigned long)chainp->wc_start, 3015 (unsigned long)(chainp->wc_end - chainp->wc_start), 3016 (unsigned long)(size - 1)); 3017 return 1; 3018 } 3019 3020 TAILQ_REMOVE(head, chainp, wc_list); 3021 free(chainp, M_DEVBUF); 3022 3023 return 0; 3024 } 3025 3026 static void 3027 pccbb_winset(bus_addr_t align, struct pccbb_softc *sc, bus_space_tag_t bst) 3028 { 3029 pci_chipset_tag_t pc; 3030 pcitag_t tag; 3031 bus_addr_t mask = ~(align - 1); 3032 struct { 3033 pcireg_t win_start; 3034 pcireg_t win_limit; 3035 int win_flags; 3036 } win[2]; 3037 struct pccbb_win_chain *chainp; 3038 int offs; 3039 3040 win[0].win_start = win[1].win_start = 0xffffffff; 3041 win[0].win_limit = win[1].win_limit = 0; 3042 win[0].win_flags = win[1].win_flags = 0; 3043 3044 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3045 offs = PCI_CB_IOBASE0; 3046 if (bus_space_is_equal(sc->sc_memt, bst)) { 3047 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3048 offs = PCI_CB_MEMBASE0; 3049 } 3050 3051 if (chainp != NULL) { 3052 win[0].win_start = chainp->wc_start & mask; 3053 win[0].win_limit = chainp->wc_end & mask; 3054 win[0].win_flags = chainp->wc_flags; 3055 chainp = TAILQ_NEXT(chainp, wc_list); 3056 } 3057 3058 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3059 if (win[1].win_start == 0xffffffff) { 3060 /* window 1 is not used */ 3061 if ((win[0].win_flags == chainp->wc_flags) && 3062 (win[0].win_limit + align >= 3063 (chainp->wc_start & mask))) { 3064 /* concatenate */ 3065 win[0].win_limit = chainp->wc_end & mask; 3066 } else { 3067 /* make new window */ 3068 win[1].win_start = chainp->wc_start & mask; 3069 win[1].win_limit = chainp->wc_end & mask; 3070 win[1].win_flags = chainp->wc_flags; 3071 } 3072 continue; 3073 } 3074 3075 /* Both windows are engaged. */ 3076 if (win[0].win_flags == win[1].win_flags) { 3077 /* same flags */ 3078 if (win[0].win_flags == chainp->wc_flags) { 3079 if (win[1].win_start - (win[0].win_limit + 3080 align) < 3081 (chainp->wc_start & mask) - 3082 ((chainp->wc_end & mask) + align)) { 3083 /* 3084 * merge window 0 and 1, and set win1 3085 * to chainp 3086 */ 3087 win[0].win_limit = win[1].win_limit; 3088 win[1].win_start = 3089 chainp->wc_start & mask; 3090 win[1].win_limit = 3091 chainp->wc_end & mask; 3092 } else { 3093 win[1].win_limit = 3094 chainp->wc_end & mask; 3095 } 3096 } else { 3097 /* different flags */ 3098 3099 /* concatenate win0 and win1 */ 3100 win[0].win_limit = win[1].win_limit; 3101 /* allocate win[1] to new space */ 3102 win[1].win_start = chainp->wc_start & mask; 3103 win[1].win_limit = chainp->wc_end & mask; 3104 win[1].win_flags = chainp->wc_flags; 3105 } 3106 } else { 3107 /* the flags of win[0] and win[1] is different */ 3108 if (win[0].win_flags == chainp->wc_flags) { 3109 win[0].win_limit = chainp->wc_end & mask; 3110 /* 3111 * XXX this creates overlapping windows, so 3112 * what should the poor bridge do if one is 3113 * cachable, and the other is not? 3114 */ 3115 aprint_error_dev(sc->sc_dev, 3116 "overlapping windows\n"); 3117 } else { 3118 win[1].win_limit = chainp->wc_end & mask; 3119 } 3120 } 3121 } 3122 3123 pc = sc->sc_pc; 3124 tag = sc->sc_tag; 3125 pci_conf_write(pc, tag, offs, win[0].win_start); 3126 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3127 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3128 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3129 DPRINTF(("--pccbb_winset: win0 [0x%lx, 0x%lx), win1 [0x%lx, 0x%lx)\n", 3130 (unsigned long)pci_conf_read(pc, tag, offs), 3131 (unsigned long)pci_conf_read(pc, tag, offs + 4) + align, 3132 (unsigned long)pci_conf_read(pc, tag, offs + 8), 3133 (unsigned long)pci_conf_read(pc, tag, offs + 12) + align)); 3134 3135 if (bus_space_is_equal(bst, sc->sc_memt)) { 3136 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BRIDGE_CONTROL_REG); 3137 3138 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 3139 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 3140 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3141 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 3142 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3143 pci_conf_write(pc, tag, PCI_BRIDGE_CONTROL_REG, bcr); 3144 } 3145 } 3146 3147 #endif /* rbus */ 3148 3149 static bool 3150 pccbb_suspend(device_t dv, const pmf_qual_t *qual) 3151 { 3152 struct pccbb_softc *sc = device_private(dv); 3153 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3154 bus_space_handle_t base_memh = sc->sc_base_memh; 3155 pcireg_t reg; 3156 3157 if (sc->sc_pil_intr_enable) 3158 (void)pccbbintr_function(sc); 3159 sc->sc_pil_intr_enable = false; 3160 3161 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3162 /* Disable interrupts. */ 3163 reg &= ~(CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER); 3164 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3165 /* XXX joerg Disable power to the socket? */ 3166 3167 /* XXX flush PCI write */ 3168 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3169 3170 /* reset interrupt */ 3171 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, 3172 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT)); 3173 /* XXX flush PCI write */ 3174 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3175 3176 if (sc->sc_ih != NULL) { 3177 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 3178 sc->sc_ih = NULL; 3179 } 3180 3181 return true; 3182 } 3183 3184 static bool 3185 pccbb_resume(device_t dv, const pmf_qual_t *qual) 3186 { 3187 struct pccbb_softc *sc = device_private(dv); 3188 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3189 bus_space_handle_t base_memh = sc->sc_base_memh; 3190 pcireg_t reg; 3191 3192 pccbb_chipinit(sc); 3193 pccbb_intrinit(sc); 3194 /* setup memory and io space window for CB */ 3195 pccbb_winset(0x1000, sc, sc->sc_memt); 3196 pccbb_winset(0x04, sc, sc->sc_iot); 3197 3198 /* CSC Interrupt: Card detect interrupt on */ 3199 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3200 /* Card detect intr is turned on. */ 3201 reg |= CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; 3202 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3203 /* reset interrupt */ 3204 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3205 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3206 3207 /* 3208 * check for card insertion or removal during suspend period. 3209 * XXX: the code can't cope with card swap (remove then 3210 * insert). how can we detect such situation? 3211 */ 3212 (void)pccbbintr(sc); 3213 3214 sc->sc_pil_intr_enable = true; 3215 3216 return true; 3217 } 3218
Indexes created Thu Sep 25 16:09:42 GMT 2025