pccbb.c revision 1.203
1 /* $NetBSD: pccbb.c,v 1.203 2011/08/01 11:20:26 drochner Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: pccbb.c,v 1.203 2011/08/01 11:20:26 drochner Exp $"); 30 31 /* 32 #define CBB_DEBUG 33 #define SHOW_REGS 34 */ 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/kernel.h> 39 #include <sys/errno.h> 40 #include <sys/ioctl.h> 41 #include <sys/reboot.h> /* for bootverbose */ 42 #include <sys/syslog.h> 43 #include <sys/device.h> 44 #include <sys/malloc.h> 45 #include <sys/proc.h> 46 47 #include <sys/intr.h> 48 #include <sys/bus.h> 49 50 #include <dev/pci/pcivar.h> 51 #include <dev/pci/pcireg.h> 52 #include <dev/pci/pcidevs.h> 53 54 #include <dev/pci/pccbbreg.h> 55 56 #include <dev/cardbus/cardslotvar.h> 57 58 #include <dev/cardbus/cardbusvar.h> 59 60 #include <dev/pcmcia/pcmciareg.h> 61 #include <dev/pcmcia/pcmciavar.h> 62 63 #include <dev/ic/i82365reg.h> 64 #include <dev/pci/pccbbvar.h> 65 66 #ifndef __NetBSD_Version__ 67 struct cfdriver cbb_cd = { 68 NULL, "cbb", DV_DULL 69 }; 70 #endif 71 72 #ifdef CBB_DEBUG 73 #define DPRINTF(x) printf x 74 #define STATIC 75 #else 76 #define DPRINTF(x) 77 #define STATIC static 78 #endif 79 80 int pccbb_burstup = 1; 81 82 /* 83 * delay_ms() is wait in milliseconds. It should be used instead 84 * of delay() if you want to wait more than 1 ms. 85 */ 86 static inline void 87 delay_ms(int millis, struct pccbb_softc *sc) 88 { 89 if (cold) 90 delay(millis * 1000); 91 else 92 kpause("pccbb", false, mstohz(millis), NULL); 93 } 94 95 int pcicbbmatch(device_t, cfdata_t, void *); 96 void pccbbattach(device_t, device_t, void *); 97 void pccbbchilddet(device_t, device_t); 98 int pccbbdetach(device_t, int); 99 int pccbbintr(void *); 100 static void pci113x_insert(void *); 101 static int pccbbintr_function(struct pccbb_softc *); 102 103 static int pccbb_detect_card(struct pccbb_softc *); 104 105 static void pccbb_pcmcia_write(struct pccbb_softc *, int, u_int8_t); 106 static u_int8_t pccbb_pcmcia_read(struct pccbb_softc *, int); 107 #define Pcic_read(sc, reg) pccbb_pcmcia_read((sc), (reg)) 108 #define Pcic_write(sc, reg, val) pccbb_pcmcia_write((sc), (reg), (val)) 109 110 STATIC int cb_reset(struct pccbb_softc *); 111 STATIC int cb_detect_voltage(struct pccbb_softc *); 112 STATIC int cbbprint(void *, const char *); 113 114 static int cb_chipset(u_int32_t, int *); 115 STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *, 116 struct pcmciabus_attach_args *); 117 118 STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int); 119 STATIC int pccbb_power(struct pccbb_softc *sc, int); 120 STATIC int pccbb_power_ct(cardbus_chipset_tag_t, int); 121 STATIC int pccbb_cardenable(struct pccbb_softc * sc, int function); 122 static void *pccbb_intr_establish(struct pccbb_softc *, 123 int level, int (*ih) (void *), void *sc); 124 static void pccbb_intr_disestablish(struct pccbb_softc *, void *ih); 125 126 static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t, 127 int level, int (*ih) (void *), void *sc); 128 static void pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih); 129 130 static pcitag_t pccbb_make_tag(cardbus_chipset_tag_t, int, int); 131 static pcireg_t pccbb_conf_read(cardbus_chipset_tag_t, pcitag_t, int); 132 static void pccbb_conf_write(cardbus_chipset_tag_t, pcitag_t, int, 133 pcireg_t); 134 static void pccbb_chipinit(struct pccbb_softc *); 135 static void pccbb_intrinit(struct pccbb_softc *); 136 137 STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 138 struct pcmcia_mem_handle *); 139 STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t, 140 struct pcmcia_mem_handle *); 141 STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 142 bus_size_t, struct pcmcia_mem_handle *, bus_size_t *, int *); 143 STATIC void pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t, int); 144 STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 145 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 146 STATIC void pccbb_pcmcia_io_free(pcmcia_chipset_handle_t, 147 struct pcmcia_io_handle *); 148 STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 149 bus_size_t, struct pcmcia_io_handle *, int *); 150 STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t, int); 151 STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t, 152 struct pcmcia_function *, int, int (*)(void *), void *); 153 STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t, void *); 154 STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t); 155 STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t); 156 STATIC void pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t, int); 157 STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch); 158 159 static int pccbb_pcmcia_wait_ready(struct pccbb_softc *); 160 static void pccbb_pcmcia_delay(struct pccbb_softc *, int, const char *); 161 162 static void pccbb_pcmcia_do_io_map(struct pccbb_softc *, int); 163 static void pccbb_pcmcia_do_mem_map(struct pccbb_softc *, int); 164 165 /* bus-space allocation and deallocation functions */ 166 167 static int pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t, rbus_tag_t, 168 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 169 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp); 170 static int pccbb_rbus_cb_space_free(cardbus_chipset_tag_t, rbus_tag_t, 171 bus_space_handle_t, bus_size_t); 172 173 174 175 static int pccbb_open_win(struct pccbb_softc *, bus_space_tag_t, 176 bus_addr_t, bus_size_t, bus_space_handle_t, int flags); 177 static int pccbb_close_win(struct pccbb_softc *, bus_space_tag_t, 178 bus_space_handle_t, bus_size_t); 179 static int pccbb_winlist_insert(struct pccbb_win_chain_head *, bus_addr_t, 180 bus_size_t, bus_space_handle_t, int); 181 static int pccbb_winlist_delete(struct pccbb_win_chain_head *, 182 bus_space_handle_t, bus_size_t); 183 static void pccbb_winset(bus_addr_t align, struct pccbb_softc *, 184 bus_space_tag_t); 185 void pccbb_winlist_show(struct pccbb_win_chain *); 186 187 188 /* for config_defer */ 189 static void pccbb_pci_callback(device_t); 190 191 static bool pccbb_suspend(device_t, const pmf_qual_t *); 192 static bool pccbb_resume(device_t, const pmf_qual_t *); 193 194 #if defined SHOW_REGS 195 static void cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, 196 bus_space_tag_t memt, bus_space_handle_t memh); 197 #endif 198 199 CFATTACH_DECL3_NEW(cbb_pci, sizeof(struct pccbb_softc), 200 pcicbbmatch, pccbbattach, pccbbdetach, NULL, NULL, pccbbchilddet, 201 DVF_DETACH_SHUTDOWN); 202 203 static const struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 204 pccbb_pcmcia_mem_alloc, 205 pccbb_pcmcia_mem_free, 206 pccbb_pcmcia_mem_map, 207 pccbb_pcmcia_mem_unmap, 208 pccbb_pcmcia_io_alloc, 209 pccbb_pcmcia_io_free, 210 pccbb_pcmcia_io_map, 211 pccbb_pcmcia_io_unmap, 212 pccbb_pcmcia_intr_establish, 213 pccbb_pcmcia_intr_disestablish, 214 pccbb_pcmcia_socket_enable, 215 pccbb_pcmcia_socket_disable, 216 pccbb_pcmcia_socket_settype, 217 pccbb_pcmcia_card_detect 218 }; 219 220 static const struct cardbus_functions pccbb_funcs = { 221 pccbb_rbus_cb_space_alloc, 222 pccbb_rbus_cb_space_free, 223 pccbb_cb_intr_establish, 224 pccbb_cb_intr_disestablish, 225 pccbb_ctrl, 226 pccbb_power_ct, 227 pccbb_make_tag, 228 pccbb_conf_read, 229 pccbb_conf_write, 230 }; 231 232 int 233 pcicbbmatch(device_t parent, cfdata_t match, void *aux) 234 { 235 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 236 237 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 238 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 239 PCI_INTERFACE(pa->pa_class) == 0) { 240 return 1; 241 } 242 243 return 0; 244 } 245 246 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 247 | ((prod) << PCI_PRODUCT_SHIFT)) 248 249 const struct yenta_chipinfo { 250 pcireg_t yc_id; /* vendor tag | product tag */ 251 int yc_chiptype; 252 int yc_flags; 253 } yc_chipsets[] = { 254 /* Texas Instruments chips */ 255 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 256 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 257 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 258 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 259 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI125X, 260 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 261 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 262 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 263 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 264 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 265 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 266 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 267 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI125X, 268 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 269 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI125X, 270 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 271 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 272 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 273 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 274 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 275 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI1420, 276 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 277 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI125X, 278 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 279 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 280 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 281 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1510), CB_TI12XX, 282 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 283 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1520), CB_TI12XX, 284 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 285 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4410YENTA), CB_TI12XX, 286 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 287 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4520YENTA), CB_TI12XX, 288 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 289 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI7420YENTA), CB_TI12XX, 290 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 291 292 /* Ricoh chips */ 293 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 294 PCCBB_PCMCIA_MEM_32}, 295 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 296 PCCBB_PCMCIA_MEM_32}, 297 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 298 PCCBB_PCMCIA_MEM_32}, 299 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 300 PCCBB_PCMCIA_MEM_32}, 301 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 302 PCCBB_PCMCIA_MEM_32}, 303 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 304 PCCBB_PCMCIA_MEM_32}, 305 306 /* Toshiba products */ 307 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 308 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 309 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 310 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 311 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 312 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 313 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 314 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 315 316 /* Cirrus Logic products */ 317 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 318 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 319 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 320 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 321 322 /* O2 Micro products */ 323 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6729), 324 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 325 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6730), 326 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 327 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6832), 328 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 329 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6836), 330 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 331 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6872), 332 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 333 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6922), 334 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 335 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6933), 336 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 337 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6972), 338 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 339 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_7223), 340 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 341 342 /* sentinel, or Generic chip */ 343 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 344 }; 345 346 static int 347 cb_chipset(u_int32_t pci_id, int *flagp) 348 { 349 const struct yenta_chipinfo *yc; 350 351 /* Loop over except the last default entry. */ 352 for (yc = yc_chipsets; yc < yc_chipsets + 353 __arraycount(yc_chipsets) - 1; yc++) 354 if (pci_id == yc->yc_id) 355 break; 356 357 if (flagp != NULL) 358 *flagp = yc->yc_flags; 359 360 return (yc->yc_chiptype); 361 } 362 363 void 364 pccbbchilddet(device_t self, device_t child) 365 { 366 struct pccbb_softc *sc = device_private(self); 367 int s; 368 369 KASSERT(sc->sc_csc == device_private(child)); 370 371 s = splbio(); 372 if (sc->sc_csc == device_private(child)) 373 sc->sc_csc = NULL; 374 splx(s); 375 } 376 377 void 378 pccbbattach(device_t parent, device_t self, void *aux) 379 { 380 struct pccbb_softc *sc = device_private(self); 381 struct pci_attach_args *pa = aux; 382 pci_chipset_tag_t pc = pa->pa_pc; 383 pcireg_t busreg, reg, sock_base; 384 bus_addr_t sockbase; 385 char devinfo[256]; 386 int flags; 387 388 #ifdef __HAVE_PCCBB_ATTACH_HOOK 389 pccbb_attach_hook(parent, self, pa); 390 #endif 391 392 sc->sc_dev = self; 393 394 mutex_init(&sc->sc_pwr_mtx, MUTEX_DEFAULT, IPL_BIO); 395 cv_init(&sc->sc_pwr_cv, "pccpwr"); 396 397 callout_init(&sc->sc_insert_ch, 0); 398 callout_setfunc(&sc->sc_insert_ch, pci113x_insert, sc); 399 400 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 401 402 aprint_naive("\n"); 403 404 pci_devinfo(pa->pa_id, 0, 0, devinfo, sizeof(devinfo)); 405 aprint_normal(": %s (rev. 0x%02x)", devinfo, 406 PCI_REVISION(pa->pa_class)); 407 DPRINTF((" (chipflags %x)", flags)); 408 aprint_normal("\n"); 409 410 TAILQ_INIT(&sc->sc_memwindow); 411 TAILQ_INIT(&sc->sc_iowindow); 412 413 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 414 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 415 416 #if 0 417 printf("pa->pa_memt: %08x vs rbus_mem->rb_bt: %08x\n", 418 pa->pa_memt, sc->sc_rbus_memt->rb_bt); 419 #endif 420 421 sc->sc_flags &= ~CBB_MEMHMAPPED; 422 423 /* 424 * MAP socket registers and ExCA registers on memory-space 425 * When no valid address is set on socket base registers (on pci 426 * config space), get it not polite way. 427 */ 428 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 429 430 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 431 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 432 /* The address must be valid. */ 433 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 434 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, &sc->sc_base_size)) { 435 aprint_error_dev(self, 436 "can't map socket base address 0x%lx\n", 437 (unsigned long)sock_base); 438 /* 439 * I think it's funny: socket base registers must be 440 * mapped on memory space, but ... 441 */ 442 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 443 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 444 &sc->sc_base_size)) { 445 aprint_error_dev(self, 446 "can't map socket base address" 447 " 0x%lx: io mode\n", 448 (unsigned long)sockbase); 449 /* give up... allocate reg space via rbus. */ 450 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 451 } else 452 sc->sc_flags |= CBB_MEMHMAPPED; 453 } else { 454 DPRINTF(("%s: socket base address 0x%lx\n", 455 device_xname(self), 456 (unsigned long)sockbase)); 457 sc->sc_flags |= CBB_MEMHMAPPED; 458 } 459 } 460 461 sc->sc_mem_start = 0; /* XXX */ 462 sc->sc_mem_end = 0xffffffff; /* XXX */ 463 464 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 465 466 /* pccbb_machdep.c end */ 467 468 #if defined CBB_DEBUG 469 { 470 static const char *intrname[] = { "NON", "A", "B", "C", "D" }; 471 aprint_debug_dev(self, "intrpin %s, intrtag %d\n", 472 intrname[pa->pa_intrpin], pa->pa_intrline); 473 } 474 #endif 475 476 /* setup softc */ 477 sc->sc_pc = pc; 478 sc->sc_iot = pa->pa_iot; 479 sc->sc_memt = pa->pa_memt; 480 sc->sc_dmat = pa->pa_dmat; 481 sc->sc_tag = pa->pa_tag; 482 483 memcpy(&sc->sc_pa, pa, sizeof(*pa)); 484 485 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 486 487 /* Disable legacy register mapping. */ 488 switch (sc->sc_chipset) { 489 case CB_RX5C46X: /* fallthrough */ 490 #if 0 491 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 492 case CB_RX5C47X: 493 #endif 494 /* 495 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 496 * cannot be disabled by substituting 0 into PCI_LEGACY 497 * register. Ricoh CardBus bridges have special bits on Bridge 498 * control reg (addr 0x3e on PCI config space). 499 */ 500 reg = pci_conf_read(pc, pa->pa_tag, PCI_BRIDGE_CONTROL_REG); 501 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 502 pci_conf_write(pc, pa->pa_tag, PCI_BRIDGE_CONTROL_REG, reg); 503 break; 504 505 default: 506 /* XXX I don't know proper way to kill legacy I/O. */ 507 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 508 break; 509 } 510 511 if (!pmf_device_register(self, pccbb_suspend, pccbb_resume)) 512 aprint_error_dev(self, "couldn't establish power handler\n"); 513 514 config_defer(self, pccbb_pci_callback); 515 } 516 517 int 518 pccbbdetach(device_t self, int flags) 519 { 520 struct pccbb_softc *sc = device_private(self); 521 pci_chipset_tag_t pc = sc->sc_pa.pa_pc; 522 bus_space_tag_t bmt = sc->sc_base_memt; 523 bus_space_handle_t bmh = sc->sc_base_memh; 524 uint32_t sockmask; 525 int rc; 526 527 if ((rc = config_detach_children(self, flags)) != 0) 528 return rc; 529 530 if (!LIST_EMPTY(&sc->sc_pil)) { 531 panic("%s: interrupt handlers still registered", 532 device_xname(self)); 533 return EBUSY; 534 } 535 536 if (sc->sc_ih != NULL) { 537 pci_intr_disestablish(pc, sc->sc_ih); 538 sc->sc_ih = NULL; 539 } 540 541 /* CSC Interrupt: turn off card detect and power cycle interrupts */ 542 sockmask = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 543 sockmask &= ~(CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | 544 CB_SOCKET_MASK_POWER); 545 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, sockmask); 546 /* reset interrupt */ 547 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 548 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 549 550 switch (sc->sc_flags & (CBB_MEMHMAPPED|CBB_SPECMAPPED)) { 551 case CBB_MEMHMAPPED: 552 bus_space_unmap(bmt, bmh, sc->sc_base_size); 553 break; 554 case CBB_MEMHMAPPED|CBB_SPECMAPPED: 555 #if rbus 556 { 557 pcireg_t sockbase; 558 559 sockbase = pci_conf_read(pc, sc->sc_tag, PCI_SOCKBASE); 560 rbus_space_free(sc->sc_rbus_memt, bmh, 0x1000, 561 NULL); 562 } 563 #else 564 bus_space_free(bmt, bmh, 0x1000); 565 #endif 566 } 567 sc->sc_flags &= ~(CBB_MEMHMAPPED|CBB_SPECMAPPED); 568 569 if (!TAILQ_EMPTY(&sc->sc_iowindow)) 570 aprint_error_dev(self, "i/o windows not empty"); 571 if (!TAILQ_EMPTY(&sc->sc_memwindow)) 572 aprint_error_dev(self, "memory windows not empty"); 573 574 callout_stop(&sc->sc_insert_ch); 575 callout_destroy(&sc->sc_insert_ch); 576 577 mutex_destroy(&sc->sc_pwr_mtx); 578 cv_destroy(&sc->sc_pwr_cv); 579 580 return 0; 581 } 582 583 /* 584 * static void pccbb_pci_callback(device_t self) 585 * 586 * The actual attach routine: get memory space for YENTA register 587 * space, setup YENTA register and route interrupt. 588 * 589 * This function should be deferred because this device may obtain 590 * memory space dynamically. This function must avoid obtaining 591 * memory area which has already kept for another device. 592 */ 593 static void 594 pccbb_pci_callback(device_t self) 595 { 596 struct pccbb_softc *sc = device_private(self); 597 pci_chipset_tag_t pc = sc->sc_pc; 598 bus_addr_t sockbase; 599 struct cbslot_attach_args cba; 600 struct pcmciabus_attach_args paa; 601 struct cardslot_attach_args caa; 602 device_t csc; 603 604 if (!(sc->sc_flags & CBB_MEMHMAPPED)) { 605 /* The socket registers aren't mapped correctly. */ 606 #if rbus 607 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 608 (sc->sc_chipset == CB_RX5C47X 609 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 610 0, &sockbase, &sc->sc_base_memh)) { 611 return; 612 } 613 sc->sc_base_memt = sc->sc_memt; 614 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 615 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 616 device_xname(self), (unsigned long)sockbase, 617 (unsigned long)pci_conf_read(pc, sc->sc_tag, 618 PCI_SOCKBASE))); 619 #else 620 sc->sc_base_memt = sc->sc_memt; 621 #if !defined CBB_PCI_BASE 622 #define CBB_PCI_BASE 0x20000000 623 #endif 624 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 625 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 626 /* cannot allocate memory space */ 627 return; 628 } 629 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 630 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 631 device_xname(self), (unsigned long)sock_base, 632 (unsigned long)pci_conf_read(pc, 633 sc->sc_tag, PCI_SOCKBASE))); 634 #endif 635 sc->sc_flags |= CBB_MEMHMAPPED|CBB_SPECMAPPED; 636 } 637 638 /* clear data structure for child device interrupt handlers */ 639 LIST_INIT(&sc->sc_pil); 640 641 /* bus bridge initialization */ 642 pccbb_chipinit(sc); 643 644 sc->sc_pil_intr_enable = true; 645 646 { 647 u_int32_t sockstat; 648 649 sockstat = bus_space_read_4(sc->sc_base_memt, 650 sc->sc_base_memh, CB_SOCKET_STAT); 651 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 652 sc->sc_flags |= CBB_CARDEXIST; 653 } 654 } 655 656 /* 657 * attach cardbus 658 */ 659 { 660 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 661 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 662 663 /* initialize cbslot_attach */ 664 cba.cba_iot = sc->sc_iot; 665 cba.cba_memt = sc->sc_memt; 666 cba.cba_dmat = sc->sc_dmat; 667 cba.cba_bus = (busreg >> 8) & 0x0ff; 668 cba.cba_cc = (void *)sc; 669 cba.cba_cf = &pccbb_funcs; 670 671 #if rbus 672 cba.cba_rbus_iot = sc->sc_rbus_iot; 673 cba.cba_rbus_memt = sc->sc_rbus_memt; 674 #endif 675 676 cba.cba_cacheline = PCI_CACHELINE(bhlc); 677 cba.cba_max_lattimer = PCI_LATTIMER(bhlc); 678 679 aprint_verbose_dev(self, 680 "cacheline 0x%x lattimer 0x%x\n", 681 cba.cba_cacheline, 682 cba.cba_max_lattimer); 683 aprint_verbose_dev(self, "bhlc 0x%x\n", bhlc); 684 #if defined SHOW_REGS 685 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 686 sc->sc_base_memh); 687 #endif 688 } 689 690 pccbb_pcmcia_attach_setup(sc, &paa); 691 caa.caa_cb_attach = NULL; 692 if (cba.cba_bus == 0) 693 aprint_error_dev(self, 694 "secondary bus number uninitialized; try PCI_BUS_FIXUP\n"); 695 else 696 caa.caa_cb_attach = &cba; 697 caa.caa_16_attach = &paa; 698 699 pccbb_intrinit(sc); 700 701 if (NULL != (csc = config_found_ia(self, "pcmciaslot", &caa, 702 cbbprint))) { 703 DPRINTF(("%s: found cardslot\n", __func__)); 704 sc->sc_csc = device_private(csc); 705 } 706 707 return; 708 } 709 710 711 712 713 714 /* 715 * static void pccbb_chipinit(struct pccbb_softc *sc) 716 * 717 * This function initialize YENTA chip registers listed below: 718 * 1) PCI command reg, 719 * 2) PCI and CardBus latency timer, 720 * 3) route PCI interrupt, 721 * 4) close all memory and io windows. 722 * 5) turn off bus power. 723 * 6) card detect and power cycle interrupts on. 724 * 7) clear interrupt 725 */ 726 static void 727 pccbb_chipinit(struct pccbb_softc *sc) 728 { 729 pci_chipset_tag_t pc = sc->sc_pc; 730 pcitag_t tag = sc->sc_tag; 731 bus_space_tag_t bmt = sc->sc_base_memt; 732 bus_space_handle_t bmh = sc->sc_base_memh; 733 pcireg_t bcr, bhlc, cbctl, csr, lscp, mfunc, mrburst, slotctl, sockctl, 734 sysctrl; 735 736 /* 737 * Set PCI command reg. 738 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 739 */ 740 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 741 /* I believe it is harmless. */ 742 csr |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 743 PCI_COMMAND_MASTER_ENABLE); 744 745 /* All O2 Micro chips have broken parity-error reporting 746 * until proven otherwise. The OZ6933 PCI-CardBus Bridge 747 * is known to have the defect---see PR kern/38698. 748 */ 749 if (sc->sc_chipset != CB_O2MICRO) 750 csr |= PCI_COMMAND_PARITY_ENABLE; 751 752 csr |= PCI_COMMAND_SERR_ENABLE; 753 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 754 755 /* 756 * Set CardBus latency timer. 757 */ 758 lscp = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 759 if (PCI_CB_LATENCY(lscp) < 0x20) { 760 lscp &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 761 lscp |= (0x20 << PCI_CB_LATENCY_SHIFT); 762 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, lscp); 763 } 764 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 765 PCI_CB_LATENCY(lscp), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 766 767 /* 768 * Set PCI latency timer. 769 */ 770 bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG); 771 if (PCI_LATTIMER(bhlc) < 0x10) { 772 bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 773 bhlc |= (0x10 << PCI_LATTIMER_SHIFT); 774 pci_conf_write(pc, tag, PCI_BHLC_REG, bhlc); 775 } 776 DPRINTF(("PCI latency timer 0x%x (%x)\n", 777 PCI_LATTIMER(bhlc), pci_conf_read(pc, tag, PCI_BHLC_REG))); 778 779 780 /* Route functional interrupts to PCI. */ 781 bcr = pci_conf_read(pc, tag, PCI_BRIDGE_CONTROL_REG); 782 bcr |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 783 bcr |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 784 /* assert reset */ 785 bcr |= PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT; 786 /* Set master abort mode to 1, forward SERR# from secondary 787 * to primary, and detect parity errors on secondary. 788 */ 789 bcr |= PCI_BRIDGE_CONTROL_MABRT << PCI_BRIDGE_CONTROL_SHIFT; 790 bcr |= PCI_BRIDGE_CONTROL_SERR << PCI_BRIDGE_CONTROL_SHIFT; 791 bcr |= PCI_BRIDGE_CONTROL_PERE << PCI_BRIDGE_CONTROL_SHIFT; 792 pci_conf_write(pc, tag, PCI_BRIDGE_CONTROL_REG, bcr); 793 794 switch (sc->sc_chipset) { 795 case CB_TI113X: 796 cbctl = pci_conf_read(pc, tag, PCI_CBCTRL); 797 /* This bit is shared, but may read as 0 on some chips, so set 798 it explicitly on both functions. */ 799 cbctl |= PCI113X_CBCTRL_PCI_IRQ_ENA; 800 /* CSC intr enable */ 801 cbctl |= PCI113X_CBCTRL_PCI_CSC; 802 /* functional intr prohibit | prohibit ISA routing */ 803 cbctl &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 804 pci_conf_write(pc, tag, PCI_CBCTRL, cbctl); 805 break; 806 807 case CB_TI1420: 808 sysctrl = pci_conf_read(pc, tag, PCI_SYSCTRL); 809 mrburst = pccbb_burstup 810 ? PCI1420_SYSCTRL_MRBURST : PCI1420_SYSCTRL_MRBURSTDN; 811 if ((sysctrl & PCI1420_SYSCTRL_MRBURST) == mrburst) { 812 printf("%s: %swrite bursts enabled\n", 813 device_xname(sc->sc_dev), 814 pccbb_burstup ? "read/" : ""); 815 } else if (pccbb_burstup) { 816 printf("%s: enabling read/write bursts\n", 817 device_xname(sc->sc_dev)); 818 sysctrl |= PCI1420_SYSCTRL_MRBURST; 819 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 820 } else { 821 printf("%s: disabling read bursts, " 822 "enabling write bursts\n", 823 device_xname(sc->sc_dev)); 824 sysctrl |= PCI1420_SYSCTRL_MRBURSTDN; 825 sysctrl &= ~PCI1420_SYSCTRL_MRBURSTUP; 826 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 827 } 828 /*FALLTHROUGH*/ 829 case CB_TI12XX: 830 /* 831 * Some TI 12xx (and [14][45]xx) based pci cards 832 * sometimes have issues with the MFUNC register not 833 * being initialized due to a bad EEPROM on board. 834 * Laptops that this matters on have this register 835 * properly initialized. 836 * 837 * The TI125X parts have a different register. 838 */ 839 mfunc = pci_conf_read(pc, tag, PCI12XX_MFUNC); 840 if ((mfunc & (PCI12XX_MFUNC_PIN0 | PCI12XX_MFUNC_PIN1)) == 0) { 841 /* Enable PCI interrupt /INTA */ 842 mfunc |= PCI12XX_MFUNC_PIN0_INTA; 843 844 /* XXX this is TI1520 only */ 845 if ((pci_conf_read(pc, tag, PCI_SYSCTRL) & 846 PCI12XX_SYSCTRL_INTRTIE) == 0) 847 /* Enable PCI interrupt /INTB */ 848 mfunc |= PCI12XX_MFUNC_PIN1_INTB; 849 850 pci_conf_write(pc, tag, PCI12XX_MFUNC, mfunc); 851 } 852 /* fallthrough */ 853 854 case CB_TI125X: 855 /* 856 * Disable zoom video. Some machines initialize this 857 * improperly and experience has shown that this helps 858 * prevent strange behavior. 859 */ 860 pci_conf_write(pc, tag, PCI12XX_MMCTRL, 0); 861 862 sysctrl = pci_conf_read(pc, tag, PCI_SYSCTRL); 863 sysctrl |= PCI12XX_SYSCTRL_VCCPROT; 864 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 865 cbctl = pci_conf_read(pc, tag, PCI_CBCTRL); 866 cbctl |= PCI12XX_CBCTRL_CSC; 867 pci_conf_write(pc, tag, PCI_CBCTRL, cbctl); 868 break; 869 870 case CB_TOPIC95B: 871 sockctl = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 872 sockctl |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 873 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, sockctl); 874 slotctl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 875 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 876 device_xname(sc->sc_dev), slotctl)); 877 slotctl |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 878 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 879 slotctl &= ~TOPIC_SLOT_CTRL_SWDETECT; 880 DPRINTF(("0x%x\n", slotctl)); 881 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slotctl); 882 break; 883 884 case CB_TOPIC97: 885 slotctl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 886 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 887 device_xname(sc->sc_dev), slotctl)); 888 slotctl |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 889 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 890 slotctl &= ~TOPIC_SLOT_CTRL_SWDETECT; 891 slotctl |= TOPIC97_SLOT_CTRL_PCIINT; 892 slotctl &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 893 DPRINTF(("0x%x\n", slotctl)); 894 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slotctl); 895 /* make sure to assert LV card support bits */ 896 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 897 0x800 + 0x3e, 898 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 899 0x800 + 0x3e) | 0x03); 900 break; 901 } 902 903 /* Close all memory and I/O windows. */ 904 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 905 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 906 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 907 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 908 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 909 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 910 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 911 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 912 913 /* reset 16-bit pcmcia bus */ 914 bus_space_write_1(bmt, bmh, 0x800 + PCIC_INTR, 915 bus_space_read_1(bmt, bmh, 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 916 917 /* turn off power */ 918 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 919 } 920 921 static void 922 pccbb_intrinit(struct pccbb_softc *sc) 923 { 924 pcireg_t sockmask; 925 const char *intrstr = NULL; 926 pci_intr_handle_t ih; 927 pci_chipset_tag_t pc = sc->sc_pc; 928 bus_space_tag_t bmt = sc->sc_base_memt; 929 bus_space_handle_t bmh = sc->sc_base_memh; 930 931 /* Map and establish the interrupt. */ 932 if (pci_intr_map(&sc->sc_pa, &ih)) { 933 aprint_error_dev(sc->sc_dev, "couldn't map interrupt\n"); 934 return; 935 } 936 intrstr = pci_intr_string(pc, ih); 937 938 /* 939 * XXX pccbbintr should be called under the priority lower 940 * than any other hard interrupts. 941 */ 942 KASSERT(sc->sc_ih == NULL); 943 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 944 945 if (sc->sc_ih == NULL) { 946 aprint_error_dev(sc->sc_dev, "couldn't establish interrupt"); 947 if (intrstr != NULL) 948 aprint_error(" at %s\n", intrstr); 949 else 950 aprint_error("\n"); 951 return; 952 } 953 954 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 955 956 /* CSC Interrupt: Card detect and power cycle interrupts on */ 957 sockmask = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 958 sockmask |= CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | 959 CB_SOCKET_MASK_POWER; 960 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, sockmask); 961 /* reset interrupt */ 962 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 963 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 964 } 965 966 /* 967 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 968 * struct pcmciabus_attach_args *paa) 969 * 970 * This function attaches 16-bit PCcard bus. 971 */ 972 STATIC void 973 pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 974 struct pcmciabus_attach_args *paa) 975 { 976 #if rbus 977 rbus_tag_t rb; 978 #endif 979 /* 980 * We need to do a few things here: 981 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 982 * setting the IRQ numbers to 0. 983 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 984 * routing of CSC interrupts (e.g. card removal) to PCI while in 985 * PCMCIA mode. We just leave this set all the time. 986 * 3) Enable card insertion/removal interrupts in case the chip also 987 * needs that while in PCMCIA mode. 988 * 4) Clear any pending CSC interrupt. 989 */ 990 Pcic_write(sc, PCIC_INTR, PCIC_INTR_ENABLE); 991 if (sc->sc_chipset == CB_TI113X) { 992 Pcic_write(sc, PCIC_CSC_INTR, 0); 993 } else { 994 Pcic_write(sc, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 995 Pcic_read(sc, PCIC_CSC); 996 } 997 998 /* initialize pcmcia bus attachment */ 999 paa->paa_busname = "pcmcia"; 1000 paa->pct = &pccbb_pcmcia_funcs; 1001 paa->pch = sc; 1002 #if rbus 1003 rb = sc->sc_rbus_iot; 1004 #endif 1005 1006 return; 1007 } 1008 1009 /* 1010 * int pccbbintr(arg) 1011 * void *arg; 1012 * This routine handles the interrupt from Yenta PCI-CardBus bridge 1013 * itself. 1014 */ 1015 int 1016 pccbbintr(void *arg) 1017 { 1018 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1019 struct cardslot_softc *csc; 1020 u_int32_t sockevent, sockstate; 1021 bus_space_tag_t memt = sc->sc_base_memt; 1022 bus_space_handle_t memh = sc->sc_base_memh; 1023 1024 if (!device_has_power(sc->sc_dev)) 1025 return 0; 1026 1027 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 1028 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 1029 Pcic_read(sc, PCIC_CSC); 1030 1031 if (sockevent != 0) { 1032 DPRINTF(("%s: enter sockevent %" PRIx32 "\n", 1033 __func__, sockevent)); 1034 } 1035 1036 /* XXX sockevent == CB_SOCKET_EVENT_CSTS|CB_SOCKET_EVENT_POWER 1037 * does occur in the wild. Check for a _POWER event before 1038 * possibly exiting because of an _CSTS event. 1039 */ 1040 if (sockevent & CB_SOCKET_EVENT_POWER) { 1041 DPRINTF(("Powercycling because of socket event\n")); 1042 /* XXX: Does not happen when attaching a 16-bit card */ 1043 mutex_enter(&sc->sc_pwr_mtx); 1044 sc->sc_pwrcycle++; 1045 cv_signal(&sc->sc_pwr_cv); 1046 mutex_exit(&sc->sc_pwr_mtx); 1047 } 1048 1049 /* Sometimes a change of CSTSCHG# accompanies the first 1050 * interrupt from an Atheros WLAN. That generates a 1051 * CB_SOCKET_EVENT_CSTS event on the bridge. The event 1052 * isn't interesting to pccbb(4), so we used to ignore the 1053 * interrupt. Now, let the child devices try to handle 1054 * the interrupt, instead. The Atheros NIC produces 1055 * interrupts more reliably, now: used to be that it would 1056 * only interrupt if the driver avoided powering down the 1057 * NIC's cardslot, and then the NIC would only work after 1058 * it was reset a second time. 1059 */ 1060 if (sockevent == 0 || 1061 (sockevent & ~(CB_SOCKET_EVENT_POWER|CB_SOCKET_EVENT_CD)) != 0) { 1062 /* This intr is not for me: it may be for my child devices. */ 1063 if (sc->sc_pil_intr_enable) { 1064 return pccbbintr_function(sc); 1065 } else { 1066 return 0; 1067 } 1068 } 1069 1070 if (sockevent & CB_SOCKET_EVENT_CD) { 1071 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1072 if (0x00 != (sockstate & CB_SOCKET_STAT_CD)) { 1073 /* A card should be removed. */ 1074 if (sc->sc_flags & CBB_CARDEXIST) { 1075 DPRINTF(("%s: 0x%08x", 1076 device_xname(sc->sc_dev), sockevent)); 1077 DPRINTF((" card removed, 0x%08x\n", sockstate)); 1078 sc->sc_flags &= ~CBB_CARDEXIST; 1079 if ((csc = sc->sc_csc) == NULL) 1080 ; 1081 else if (csc->sc_status & 1082 CARDSLOT_STATUS_CARD_16) { 1083 cardslot_event_throw(csc, 1084 CARDSLOT_EVENT_REMOVAL_16); 1085 } else if (csc->sc_status & 1086 CARDSLOT_STATUS_CARD_CB) { 1087 /* Cardbus intr removed */ 1088 cardslot_event_throw(csc, 1089 CARDSLOT_EVENT_REMOVAL_CB); 1090 } 1091 } else if (sc->sc_flags & CBB_INSERTING) { 1092 sc->sc_flags &= ~CBB_INSERTING; 1093 callout_stop(&sc->sc_insert_ch); 1094 } 1095 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 1096 /* 1097 * The pccbbintr may called from powerdown hook when 1098 * the system resumed, to detect the card 1099 * insertion/removal during suspension. 1100 */ 1101 (sc->sc_flags & CBB_CARDEXIST) == 0) { 1102 if (sc->sc_flags & CBB_INSERTING) { 1103 callout_stop(&sc->sc_insert_ch); 1104 } 1105 callout_schedule(&sc->sc_insert_ch, mstohz(200)); 1106 sc->sc_flags |= CBB_INSERTING; 1107 } 1108 } 1109 1110 return (1); 1111 } 1112 1113 /* 1114 * static int pccbbintr_function(struct pccbb_softc *sc) 1115 * 1116 * This function calls each interrupt handler registered at the 1117 * bridge. The interrupt handlers are called in registered order. 1118 */ 1119 static int 1120 pccbbintr_function(struct pccbb_softc *sc) 1121 { 1122 int retval = 0, val; 1123 struct pccbb_intrhand_list *pil; 1124 int s; 1125 1126 LIST_FOREACH(pil, &sc->sc_pil, pil_next) { 1127 s = splraiseipl(pil->pil_icookie); 1128 val = (*pil->pil_func)(pil->pil_arg); 1129 splx(s); 1130 1131 retval = retval == 1 ? 1 : 1132 retval == 0 ? val : val != 0 ? val : retval; 1133 } 1134 1135 return retval; 1136 } 1137 1138 static void 1139 pci113x_insert(void *arg) 1140 { 1141 struct pccbb_softc *sc = arg; 1142 struct cardslot_softc *csc; 1143 u_int32_t sockevent, sockstate; 1144 1145 if (!(sc->sc_flags & CBB_INSERTING)) { 1146 /* We add a card only under inserting state. */ 1147 return; 1148 } 1149 sc->sc_flags &= ~CBB_INSERTING; 1150 1151 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1152 CB_SOCKET_EVENT); 1153 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1154 CB_SOCKET_STAT); 1155 1156 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1157 DPRINTF(("%s: 0x%08x", device_xname(sc->sc_dev), sockevent)); 1158 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1159 sc->sc_flags |= CBB_CARDEXIST; 1160 /* call pccard interrupt handler here */ 1161 if ((csc = sc->sc_csc) == NULL) 1162 ; 1163 else if (sockstate & CB_SOCKET_STAT_16BIT) { 1164 /* 16-bit card found */ 1165 cardslot_event_throw(csc, CARDSLOT_EVENT_INSERTION_16); 1166 } else if (sockstate & CB_SOCKET_STAT_CB) { 1167 /* cardbus card found */ 1168 cardslot_event_throw(csc, CARDSLOT_EVENT_INSERTION_CB); 1169 } else { 1170 /* who are you? */ 1171 } 1172 } else { 1173 callout_schedule(&sc->sc_insert_ch, mstohz(100)); 1174 } 1175 } 1176 1177 #define PCCBB_PCMCIA_OFFSET 0x800 1178 static u_int8_t 1179 pccbb_pcmcia_read(struct pccbb_softc *sc, int reg) 1180 { 1181 bus_space_barrier(sc->sc_base_memt, sc->sc_base_memh, 1182 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1183 1184 return bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 1185 PCCBB_PCMCIA_OFFSET + reg); 1186 } 1187 1188 static void 1189 pccbb_pcmcia_write(struct pccbb_softc *sc, int reg, u_int8_t val) 1190 { 1191 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 1192 PCCBB_PCMCIA_OFFSET + reg, val); 1193 1194 bus_space_barrier(sc->sc_base_memt, sc->sc_base_memh, 1195 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1196 } 1197 1198 /* 1199 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1200 */ 1201 STATIC int 1202 pccbb_ctrl(cardbus_chipset_tag_t ct, int command) 1203 { 1204 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1205 1206 switch (command) { 1207 case CARDBUS_CD: 1208 if (2 == pccbb_detect_card(sc)) { 1209 int retval = 0; 1210 int status = cb_detect_voltage(sc); 1211 if (PCCARD_VCC_5V & status) { 1212 retval |= CARDBUS_5V_CARD; 1213 } 1214 if (PCCARD_VCC_3V & status) { 1215 retval |= CARDBUS_3V_CARD; 1216 } 1217 if (PCCARD_VCC_XV & status) { 1218 retval |= CARDBUS_XV_CARD; 1219 } 1220 if (PCCARD_VCC_YV & status) { 1221 retval |= CARDBUS_YV_CARD; 1222 } 1223 return retval; 1224 } else { 1225 return 0; 1226 } 1227 case CARDBUS_RESET: 1228 return cb_reset(sc); 1229 case CARDBUS_IO_ENABLE: /* fallthrough */ 1230 case CARDBUS_IO_DISABLE: /* fallthrough */ 1231 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1232 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1233 case CARDBUS_BM_ENABLE: /* fallthrough */ 1234 case CARDBUS_BM_DISABLE: /* fallthrough */ 1235 /* XXX: I think we don't need to call this function below. */ 1236 return pccbb_cardenable(sc, command); 1237 } 1238 1239 return 0; 1240 } 1241 1242 STATIC int 1243 pccbb_power_ct(cardbus_chipset_tag_t ct, int command) 1244 { 1245 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1246 1247 return pccbb_power(sc, command); 1248 } 1249 1250 /* 1251 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1252 * This function returns true when it succeeds and returns false when 1253 * it fails. 1254 */ 1255 STATIC int 1256 pccbb_power(struct pccbb_softc *sc, int command) 1257 { 1258 u_int32_t status, osock_ctrl, sock_ctrl, reg_ctrl; 1259 bus_space_tag_t memt = sc->sc_base_memt; 1260 bus_space_handle_t memh = sc->sc_base_memh; 1261 int on = 0, pwrcycle, times; 1262 struct timeval before, after, diff; 1263 1264 DPRINTF(("pccbb_power: %s and %s [0x%x]\n", 1265 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1266 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1267 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1268 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1269 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1270 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1271 "UNKNOWN", 1272 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1273 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1274 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1275 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1276 "UNKNOWN", command)); 1277 1278 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1279 osock_ctrl = sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1280 1281 switch (command & CARDBUS_VCCMASK) { 1282 case CARDBUS_VCC_UC: 1283 break; 1284 case CARDBUS_VCC_5V: 1285 on++; 1286 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1287 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1288 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1289 } else { 1290 aprint_error_dev(sc->sc_dev, 1291 "BAD voltage request: no 5 V card\n"); 1292 return 0; 1293 } 1294 break; 1295 case CARDBUS_VCC_3V: 1296 on++; 1297 if (CB_SOCKET_STAT_3VCARD & status) { 1298 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1299 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1300 } else { 1301 aprint_error_dev(sc->sc_dev, 1302 "BAD voltage request: no 3.3 V card\n"); 1303 return 0; 1304 } 1305 break; 1306 case CARDBUS_VCC_0V: 1307 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1308 break; 1309 default: 1310 return 0; /* power NEVER changed */ 1311 } 1312 1313 switch (command & CARDBUS_VPPMASK) { 1314 case CARDBUS_VPP_UC: 1315 break; 1316 case CARDBUS_VPP_0V: 1317 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1318 break; 1319 case CARDBUS_VPP_VCC: 1320 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1321 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1322 break; 1323 case CARDBUS_VPP_12V: 1324 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1325 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1326 break; 1327 } 1328 aprint_debug_dev(sc->sc_dev, "osock_ctrl %#" PRIx32 1329 " sock_ctrl %#" PRIx32 "\n", osock_ctrl, sock_ctrl); 1330 1331 microtime(&before); 1332 mutex_enter(&sc->sc_pwr_mtx); 1333 pwrcycle = sc->sc_pwrcycle; 1334 1335 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1336 1337 /* 1338 * Wait as long as 200ms for a power-cycle interrupt. If 1339 * interrupts are enabled, but the socket has already 1340 * changed to the desired status, keep waiting for the 1341 * interrupt. "Consuming" the interrupt in this way keeps 1342 * the interrupt from prematurely waking some subsequent 1343 * pccbb_power call. 1344 * 1345 * XXX Not every bridge interrupts on the ->OFF transition. 1346 * XXX That's ok, we will time-out after 200ms. 1347 * 1348 * XXX The power cycle event will never happen when attaching 1349 * XXX a 16-bit card. That's ok, we will time-out after 1350 * XXX 200ms. 1351 */ 1352 for (times = 5; --times >= 0; ) { 1353 if (cold) 1354 DELAY(40 * 1000); 1355 else { 1356 (void)cv_timedwait(&sc->sc_pwr_cv, &sc->sc_pwr_mtx, 1357 mstohz(40)); 1358 if (pwrcycle == sc->sc_pwrcycle) 1359 continue; 1360 } 1361 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1362 if ((status & CB_SOCKET_STAT_PWRCYCLE) != 0 && on) 1363 break; 1364 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0 && !on) 1365 break; 1366 } 1367 mutex_exit(&sc->sc_pwr_mtx); 1368 microtime(&after); 1369 timersub(&after, &before, &diff); 1370 aprint_debug_dev(sc->sc_dev, "wait took%s %lld.%06lds\n", 1371 (on && times < 0) ? " too long" : "", (long long)diff.tv_sec, 1372 (long)diff.tv_usec); 1373 1374 /* 1375 * Ok, wait a bit longer for things to settle. 1376 */ 1377 if (on && sc->sc_chipset == CB_TOPIC95B) 1378 delay_ms(100, sc); 1379 1380 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1381 1382 if (on && sc->sc_chipset != CB_TOPIC95B) { 1383 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0) 1384 aprint_error_dev(sc->sc_dev, "power on failed?\n"); 1385 } 1386 1387 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1388 aprint_error_dev(sc->sc_dev, 1389 "bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1390 sock_ctrl, status); 1391 aprint_error_dev(sc->sc_dev, "disabling socket\n"); 1392 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1393 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1394 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1395 status &= ~CB_SOCKET_STAT_BADVCC; 1396 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, status); 1397 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1398 CB_SOCKET_STAT)); 1399 return 0; 1400 } 1401 1402 if (sc->sc_chipset == CB_TOPIC97) { 1403 reg_ctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL); 1404 reg_ctrl &= ~TOPIC97_REG_CTRL_TESTMODE; 1405 if ((command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V) 1406 reg_ctrl &= ~TOPIC97_REG_CTRL_CLKRUN_ENA; 1407 else 1408 reg_ctrl |= TOPIC97_REG_CTRL_CLKRUN_ENA; 1409 pci_conf_write(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL, reg_ctrl); 1410 } 1411 1412 return 1; /* power changed correctly */ 1413 } 1414 1415 /* 1416 * static int pccbb_detect_card(struct pccbb_softc *sc) 1417 * return value: 0 if no card exists. 1418 * 1 if 16-bit card exists. 1419 * 2 if cardbus card exists. 1420 */ 1421 static int 1422 pccbb_detect_card(struct pccbb_softc *sc) 1423 { 1424 bus_space_handle_t base_memh = sc->sc_base_memh; 1425 bus_space_tag_t base_memt = sc->sc_base_memt; 1426 u_int32_t sockstat = 1427 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1428 int retval = 0; 1429 1430 /* CD1 and CD2 asserted */ 1431 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1432 /* card must be present */ 1433 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1434 /* NOTACARD DEASSERTED */ 1435 if (CB_SOCKET_STAT_CB & sockstat) { 1436 /* CardBus mode */ 1437 retval = 2; 1438 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1439 /* 16-bit mode */ 1440 retval = 1; 1441 } 1442 } 1443 } 1444 return retval; 1445 } 1446 1447 /* 1448 * STATIC int cb_reset(struct pccbb_softc *sc) 1449 * This function resets CardBus card. 1450 */ 1451 STATIC int 1452 cb_reset(struct pccbb_softc *sc) 1453 { 1454 /* 1455 * Reset Assert at least 20 ms 1456 * Some machines request longer duration. 1457 */ 1458 int reset_duration = 1459 (sc->sc_chipset == CB_RX5C47X ? 400 : 50); 1460 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1461 aprint_debug("%s: enter bcr %" PRIx32 "\n", __func__, bcr); 1462 1463 /* Reset bit Assert (bit 6 at 0x3E) */ 1464 bcr |= PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT; 1465 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr); 1466 aprint_debug("%s: wrote bcr %" PRIx32 "\n", __func__, bcr); 1467 delay_ms(reset_duration, sc); 1468 1469 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1470 /* Reset bit Deassert (bit 6 at 0x3E) */ 1471 bcr &= ~(PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT); 1472 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, 1473 bcr); 1474 aprint_debug("%s: wrote bcr %" PRIx32 "\n", __func__, bcr); 1475 delay_ms(reset_duration, sc); 1476 aprint_debug("%s: end of delay\n", __func__); 1477 } 1478 /* No card found on the slot. Keep Reset. */ 1479 return 1; 1480 } 1481 1482 /* 1483 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1484 * This function detect card Voltage. 1485 */ 1486 STATIC int 1487 cb_detect_voltage(struct pccbb_softc *sc) 1488 { 1489 u_int32_t psr; /* socket present-state reg */ 1490 bus_space_tag_t iot = sc->sc_base_memt; 1491 bus_space_handle_t ioh = sc->sc_base_memh; 1492 int vol = PCCARD_VCC_UKN; /* set 0 */ 1493 1494 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1495 1496 if (0x400u & psr) { 1497 vol |= PCCARD_VCC_5V; 1498 } 1499 if (0x800u & psr) { 1500 vol |= PCCARD_VCC_3V; 1501 } 1502 1503 return vol; 1504 } 1505 1506 STATIC int 1507 cbbprint(void *aux, const char *pcic) 1508 { 1509 #if 0 1510 struct cbslot_attach_args *cba = aux; 1511 1512 if (cba->cba_slot >= 0) { 1513 aprint_normal(" slot %d", cba->cba_slot); 1514 } 1515 #endif 1516 return UNCONF; 1517 } 1518 1519 /* 1520 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1521 * This function enables and disables the card 1522 */ 1523 STATIC int 1524 pccbb_cardenable(struct pccbb_softc *sc, int function) 1525 { 1526 u_int32_t command = 1527 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1528 1529 DPRINTF(("pccbb_cardenable:")); 1530 switch (function) { 1531 case CARDBUS_IO_ENABLE: 1532 command |= PCI_COMMAND_IO_ENABLE; 1533 break; 1534 case CARDBUS_IO_DISABLE: 1535 command &= ~PCI_COMMAND_IO_ENABLE; 1536 break; 1537 case CARDBUS_MEM_ENABLE: 1538 command |= PCI_COMMAND_MEM_ENABLE; 1539 break; 1540 case CARDBUS_MEM_DISABLE: 1541 command &= ~PCI_COMMAND_MEM_ENABLE; 1542 break; 1543 case CARDBUS_BM_ENABLE: 1544 command |= PCI_COMMAND_MASTER_ENABLE; 1545 break; 1546 case CARDBUS_BM_DISABLE: 1547 command &= ~PCI_COMMAND_MASTER_ENABLE; 1548 break; 1549 default: 1550 return 0; 1551 } 1552 1553 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1554 DPRINTF((" command reg 0x%x\n", command)); 1555 return 1; 1556 } 1557 1558 #if !rbus 1559 static int 1560 pccbb_io_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 1561 { 1562 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1563 int basereg; 1564 int limitreg; 1565 1566 if ((win < 0) || (win > 2)) { 1567 #if defined DIAGNOSTIC 1568 printf("cardbus_io_open: window out of range %d\n", win); 1569 #endif 1570 return 0; 1571 } 1572 1573 basereg = win * 8 + PCI_CB_IOBASE0; 1574 limitreg = win * 8 + PCI_CB_IOLIMIT0; 1575 1576 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1577 start, basereg, end, limitreg)); 1578 1579 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1580 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1581 return 1; 1582 } 1583 1584 /* 1585 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1586 */ 1587 static int 1588 pccbb_io_close(cardbus_chipset_tag_t ct, int win) 1589 { 1590 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1591 int basereg; 1592 int limitreg; 1593 1594 if ((win < 0) || (win > 2)) { 1595 #if defined DIAGNOSTIC 1596 printf("cardbus_io_close: window out of range %d\n", win); 1597 #endif 1598 return 0; 1599 } 1600 1601 basereg = win * 8 + PCI_CB_IOBASE0; 1602 limitreg = win * 8 + PCI_CB_IOLIMIT0; 1603 1604 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1605 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1606 return 1; 1607 } 1608 1609 static int 1610 pccbb_mem_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 1611 { 1612 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1613 int basereg; 1614 int limitreg; 1615 1616 if ((win < 0) || (win > 2)) { 1617 #if defined DIAGNOSTIC 1618 printf("cardbus_mem_open: window out of range %d\n", win); 1619 #endif 1620 return 0; 1621 } 1622 1623 basereg = win * 8 + PCI_CB_MEMBASE0; 1624 limitreg = win * 8 + PCI_CB_MEMLIMIT0; 1625 1626 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1627 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1628 return 1; 1629 } 1630 1631 static int 1632 pccbb_mem_close(cardbus_chipset_tag_t ct, int win) 1633 { 1634 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1635 int basereg; 1636 int limitreg; 1637 1638 if ((win < 0) || (win > 2)) { 1639 #if defined DIAGNOSTIC 1640 printf("cardbus_mem_close: window out of range %d\n", win); 1641 #endif 1642 return 0; 1643 } 1644 1645 basereg = win * 8 + PCI_CB_MEMBASE0; 1646 limitreg = win * 8 + PCI_CB_MEMLIMIT0; 1647 1648 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1649 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1650 return 1; 1651 } 1652 #endif 1653 1654 /* 1655 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1656 * int level, 1657 * int (* func)(void *), 1658 * void *arg) 1659 * 1660 * This function registers an interrupt handler at the bridge, in 1661 * order not to call the interrupt handlers of child devices when 1662 * a card-deletion interrupt occurs. 1663 * 1664 * The argument level is not used. 1665 */ 1666 static void * 1667 pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, int level, 1668 int (*func)(void *), void *arg) 1669 { 1670 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1671 1672 return pccbb_intr_establish(sc, level, func, arg); 1673 } 1674 1675 1676 /* 1677 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1678 * void *ih) 1679 * 1680 * This function removes an interrupt handler pointed by ih. 1681 */ 1682 static void 1683 pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih) 1684 { 1685 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1686 1687 pccbb_intr_disestablish(sc, ih); 1688 } 1689 1690 1691 void 1692 pccbb_intr_route(struct pccbb_softc *sc) 1693 { 1694 pcireg_t bcr, cbctrl; 1695 1696 /* initialize bridge intr routing */ 1697 bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1698 bcr &= ~CB_BCR_INTR_IREQ_ENABLE; 1699 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr); 1700 1701 switch (sc->sc_chipset) { 1702 case CB_TI113X: 1703 cbctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1704 /* functional intr enabled */ 1705 cbctrl |= PCI113X_CBCTRL_PCI_INTR; 1706 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, cbctrl); 1707 break; 1708 default: 1709 break; 1710 } 1711 } 1712 1713 /* 1714 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1715 * int irq, 1716 * int level, 1717 * int (* func)(void *), 1718 * void *arg) 1719 * 1720 * This function registers an interrupt handler at the bridge, in 1721 * order not to call the interrupt handlers of child devices when 1722 * a card-deletion interrupt occurs. 1723 * 1724 */ 1725 static void * 1726 pccbb_intr_establish(struct pccbb_softc *sc, int level, 1727 int (*func)(void *), void *arg) 1728 { 1729 struct pccbb_intrhand_list *pil, *newpil; 1730 1731 DPRINTF(("pccbb_intr_establish start. %p\n", LIST_FIRST(&sc->sc_pil))); 1732 1733 if (LIST_EMPTY(&sc->sc_pil)) { 1734 pccbb_intr_route(sc); 1735 } 1736 1737 /* 1738 * Allocate a room for interrupt handler structure. 1739 */ 1740 if (NULL == (newpil = 1741 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1742 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1743 return NULL; 1744 } 1745 1746 newpil->pil_func = func; 1747 newpil->pil_arg = arg; 1748 newpil->pil_icookie = makeiplcookie(level); 1749 1750 if (LIST_EMPTY(&sc->sc_pil)) { 1751 LIST_INSERT_HEAD(&sc->sc_pil, newpil, pil_next); 1752 } else { 1753 for (pil = LIST_FIRST(&sc->sc_pil); 1754 LIST_NEXT(pil, pil_next) != NULL; 1755 pil = LIST_NEXT(pil, pil_next)); 1756 LIST_INSERT_AFTER(pil, newpil, pil_next); 1757 } 1758 1759 DPRINTF(("pccbb_intr_establish add pil. %p\n", 1760 LIST_FIRST(&sc->sc_pil))); 1761 1762 return newpil; 1763 } 1764 1765 /* 1766 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1767 * void *ih) 1768 * 1769 * This function removes an interrupt handler pointed by ih. ih 1770 * should be the value returned by cardbus_intr_establish() or 1771 * NULL. 1772 * 1773 * When ih is NULL, this function will do nothing. 1774 */ 1775 static void 1776 pccbb_intr_disestablish(struct pccbb_softc *sc, void *ih) 1777 { 1778 struct pccbb_intrhand_list *pil; 1779 pcireg_t reg; 1780 1781 DPRINTF(("pccbb_intr_disestablish start. %p\n", 1782 LIST_FIRST(&sc->sc_pil))); 1783 1784 if (ih == NULL) { 1785 /* intr handler is not set */ 1786 DPRINTF(("pccbb_intr_disestablish: no ih\n")); 1787 return; 1788 } 1789 1790 #ifdef DIAGNOSTIC 1791 LIST_FOREACH(pil, &sc->sc_pil, pil_next) { 1792 DPRINTF(("pccbb_intr_disestablish: pil %p\n", pil)); 1793 if (pil == ih) { 1794 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1795 break; 1796 } 1797 } 1798 if (pil == NULL) { 1799 panic("pccbb_intr_disestablish: %s cannot find pil %p", 1800 device_xname(sc->sc_dev), ih); 1801 } 1802 #endif 1803 1804 pil = (struct pccbb_intrhand_list *)ih; 1805 LIST_REMOVE(pil, pil_next); 1806 free(pil, M_DEVBUF); 1807 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1808 1809 if (LIST_EMPTY(&sc->sc_pil)) { 1810 /* No interrupt handlers */ 1811 1812 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1813 1814 /* stop routing PCI intr */ 1815 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1816 reg |= CB_BCR_INTR_IREQ_ENABLE; 1817 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, reg); 1818 1819 switch (sc->sc_chipset) { 1820 case CB_TI113X: 1821 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1822 /* functional intr disabled */ 1823 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1824 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1825 break; 1826 default: 1827 break; 1828 } 1829 } 1830 } 1831 1832 #if defined SHOW_REGS 1833 static void 1834 cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, bus_space_tag_t memt, 1835 bus_space_handle_t memh) 1836 { 1837 int i; 1838 printf("PCI config regs:"); 1839 for (i = 0; i < 0x50; i += 4) { 1840 if (i % 16 == 0) 1841 printf("\n 0x%02x:", i); 1842 printf(" %08x", pci_conf_read(pc, tag, i)); 1843 } 1844 for (i = 0x80; i < 0xb0; i += 4) { 1845 if (i % 16 == 0) 1846 printf("\n 0x%02x:", i); 1847 printf(" %08x", pci_conf_read(pc, tag, i)); 1848 } 1849 1850 if (memh == 0) { 1851 printf("\n"); 1852 return; 1853 } 1854 1855 printf("\nsocket regs:"); 1856 for (i = 0; i <= 0x10; i += 0x04) 1857 printf(" %08x", bus_space_read_4(memt, memh, i)); 1858 printf("\nExCA regs:"); 1859 for (i = 0; i < 0x08; ++i) 1860 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1861 printf("\n"); 1862 return; 1863 } 1864 #endif 1865 1866 /* 1867 * static pcitag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1868 * int busno, int function) 1869 * This is the function to make a tag to access config space of 1870 * a CardBus Card. It works same as pci_conf_read. 1871 */ 1872 static pcitag_t 1873 pccbb_make_tag(cardbus_chipset_tag_t cc, int busno, int function) 1874 { 1875 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1876 1877 return pci_make_tag(sc->sc_pc, busno, 0, function); 1878 } 1879 1880 /* 1881 * pccbb_conf_read 1882 * 1883 * This is the function to read the config space of a CardBus card. 1884 * It works the same as pci_conf_read(9). 1885 */ 1886 static pcireg_t 1887 pccbb_conf_read(cardbus_chipset_tag_t cc, pcitag_t tag, int offset) 1888 { 1889 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1890 pcitag_t brtag = sc->sc_tag; 1891 pcireg_t reg; 1892 1893 /* 1894 * clear cardbus master abort status; it is OK to write without 1895 * reading before because all bits are r/o or w1tc 1896 */ 1897 pci_conf_write(sc->sc_pc, brtag, PCI_CBB_SECSTATUS, 1898 CBB_SECSTATUS_CBMABORT); 1899 reg = pci_conf_read(sc->sc_pc, tag, offset); 1900 /* check cardbus master abort status */ 1901 if (pci_conf_read(sc->sc_pc, brtag, PCI_CBB_SECSTATUS) 1902 & CBB_SECSTATUS_CBMABORT) 1903 return (0xffffffff); 1904 return reg; 1905 } 1906 1907 /* 1908 * pccbb_conf_write 1909 * 1910 * This is the function to write the config space of a CardBus 1911 * card. It works the same as pci_conf_write(9). 1912 */ 1913 static void 1914 pccbb_conf_write(cardbus_chipset_tag_t cc, pcitag_t tag, int reg, pcireg_t val) 1915 { 1916 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1917 1918 pci_conf_write(sc->sc_pc, tag, reg, val); 1919 } 1920 1921 #if 0 1922 STATIC int 1923 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1924 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 1925 int speed, int flags, 1926 bus_space_handle_t * iohp) 1927 #endif 1928 /* 1929 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1930 * bus_addr_t start, bus_size_t size, 1931 * bus_size_t align, 1932 * struct pcmcia_io_handle *pcihp 1933 * 1934 * This function only allocates I/O region for pccard. This function 1935 * never maps the allocated region to pccard I/O area. 1936 * 1937 * XXX: The interface of this function is not very good, I believe. 1938 */ 1939 STATIC int 1940 pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, 1941 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 1942 { 1943 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 1944 bus_addr_t ioaddr; 1945 int flags = 0; 1946 bus_space_tag_t iot; 1947 bus_space_handle_t ioh; 1948 bus_addr_t mask; 1949 #if rbus 1950 rbus_tag_t rb; 1951 #endif 1952 if (align == 0) { 1953 align = size; /* XXX: funny??? */ 1954 } 1955 1956 if (start != 0) { 1957 /* XXX: assume all card decode lower 10 bits by its hardware */ 1958 mask = 0x3ff; 1959 /* enforce to use only masked address */ 1960 start &= mask; 1961 } else { 1962 /* 1963 * calculate mask: 1964 * 1. get the most significant bit of size (call it msb). 1965 * 2. compare msb with the value of size. 1966 * 3. if size is larger, shift msb left once. 1967 * 4. obtain mask value to decrement msb. 1968 */ 1969 bus_size_t size_tmp = size; 1970 int shifts = 0; 1971 1972 mask = 1; 1973 while (size_tmp) { 1974 ++shifts; 1975 size_tmp >>= 1; 1976 } 1977 mask = (1 << shifts); 1978 if (mask < size) { 1979 mask <<= 1; 1980 } 1981 --mask; 1982 } 1983 1984 /* 1985 * Allocate some arbitrary I/O space. 1986 */ 1987 1988 iot = sc->sc_iot; 1989 1990 #if rbus 1991 rb = sc->sc_rbus_iot; 1992 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 1993 return 1; 1994 } 1995 DPRINTF(("pccbb_pcmcia_io_alloc alloc port 0x%lx+0x%lx\n", 1996 (u_long) ioaddr, (u_long) size)); 1997 #else 1998 if (start) { 1999 ioaddr = start; 2000 if (bus_space_map(iot, start, size, 0, &ioh)) { 2001 return 1; 2002 } 2003 DPRINTF(("pccbb_pcmcia_io_alloc map port 0x%lx+0x%lx\n", 2004 (u_long) ioaddr, (u_long) size)); 2005 } else { 2006 flags |= PCMCIA_IO_ALLOCATED; 2007 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 2008 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 2009 size, align, 0, 0, &ioaddr, &ioh)) { 2010 /* No room be able to be get. */ 2011 return 1; 2012 } 2013 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2014 (u_long) ioaddr, (u_long) size)); 2015 } 2016 #endif 2017 2018 pcihp->iot = iot; 2019 pcihp->ioh = ioh; 2020 pcihp->addr = ioaddr; 2021 pcihp->size = size; 2022 pcihp->flags = flags; 2023 2024 return 0; 2025 } 2026 2027 /* 2028 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2029 * struct pcmcia_io_handle *pcihp) 2030 * 2031 * This function only frees I/O region for pccard. 2032 * 2033 * XXX: The interface of this function is not very good, I believe. 2034 */ 2035 void 2036 pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2037 struct pcmcia_io_handle *pcihp) 2038 { 2039 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2040 #if !rbus 2041 bus_space_tag_t iot = pcihp->iot; 2042 #endif 2043 bus_space_handle_t ioh = pcihp->ioh; 2044 bus_size_t size = pcihp->size; 2045 2046 #if rbus 2047 rbus_tag_t rb = sc->sc_rbus_iot; 2048 2049 rbus_space_free(rb, ioh, size, NULL); 2050 #else 2051 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 2052 bus_space_free(iot, ioh, size); 2053 else 2054 bus_space_unmap(iot, ioh, size); 2055 #endif 2056 } 2057 2058 /* 2059 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 2060 * bus_addr_t offset, bus_size_t size, 2061 * struct pcmcia_io_handle *pcihp, 2062 * int *windowp) 2063 * 2064 * This function maps the allocated I/O region to pccard. This function 2065 * never allocates any I/O region for pccard I/O area. I don't 2066 * understand why the original authors of pcmciabus separated alloc and 2067 * map. I believe the two must be unite. 2068 * 2069 * XXX: no wait timing control? 2070 */ 2071 int 2072 pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, bus_addr_t offset, 2073 bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp) 2074 { 2075 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2076 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2077 bus_addr_t ioaddr = pcihp->addr + offset; 2078 int i, win; 2079 #if defined CBB_DEBUG 2080 static const char *width_names[] = { "dynamic", "io8", "io16" }; 2081 #endif 2082 2083 /* Sanity check I/O handle. */ 2084 2085 if (!bus_space_is_equal(sc->sc_iot, pcihp->iot)) { 2086 panic("pccbb_pcmcia_io_map iot is bogus"); 2087 } 2088 2089 /* XXX Sanity check offset/size. */ 2090 2091 win = -1; 2092 for (i = 0; i < PCIC_IO_WINS; i++) { 2093 if ((ph->ioalloc & (1 << i)) == 0) { 2094 win = i; 2095 ph->ioalloc |= (1 << i); 2096 break; 2097 } 2098 } 2099 2100 if (win == -1) { 2101 return 1; 2102 } 2103 2104 *windowp = win; 2105 2106 /* XXX this is pretty gross */ 2107 2108 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2109 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2110 2111 /* XXX wtf is this doing here? */ 2112 2113 #if 0 2114 printf(" port 0x%lx", (u_long) ioaddr); 2115 if (size > 1) { 2116 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2117 } 2118 #endif 2119 2120 ph->io[win].addr = ioaddr; 2121 ph->io[win].size = size; 2122 ph->io[win].width = width; 2123 2124 /* actual dirty register-value changing in the function below. */ 2125 pccbb_pcmcia_do_io_map(sc, win); 2126 2127 return 0; 2128 } 2129 2130 /* 2131 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2132 * 2133 * This function changes register-value to map I/O region for pccard. 2134 */ 2135 static void 2136 pccbb_pcmcia_do_io_map(struct pccbb_softc *sc, int win) 2137 { 2138 static u_int8_t pcic_iowidth[3] = { 2139 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2140 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2141 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2142 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2143 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2144 }; 2145 2146 #define PCIC_SIA_START_LOW 0 2147 #define PCIC_SIA_START_HIGH 1 2148 #define PCIC_SIA_STOP_LOW 2 2149 #define PCIC_SIA_STOP_HIGH 3 2150 2151 int regbase_win = 0x8 + win * 0x04; 2152 u_int8_t ioctl, enable; 2153 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2154 2155 DPRINTF(("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx " 2156 "width %d\n", win, (unsigned long)ph->io[win].addr, 2157 (unsigned long)ph->io[win].size, ph->io[win].width * 8)); 2158 2159 Pcic_write(sc, regbase_win + PCIC_SIA_START_LOW, 2160 ph->io[win].addr & 0xff); 2161 Pcic_write(sc, regbase_win + PCIC_SIA_START_HIGH, 2162 (ph->io[win].addr >> 8) & 0xff); 2163 2164 Pcic_write(sc, regbase_win + PCIC_SIA_STOP_LOW, 2165 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2166 Pcic_write(sc, regbase_win + PCIC_SIA_STOP_HIGH, 2167 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2168 2169 ioctl = Pcic_read(sc, PCIC_IOCTL); 2170 enable = Pcic_read(sc, PCIC_ADDRWIN_ENABLE); 2171 switch (win) { 2172 case 0: 2173 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2174 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2175 PCIC_IOCTL_IO0_DATASIZE_MASK); 2176 ioctl |= pcic_iowidth[ph->io[win].width]; 2177 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2178 break; 2179 case 1: 2180 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2181 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2182 PCIC_IOCTL_IO1_DATASIZE_MASK); 2183 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2184 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2185 break; 2186 } 2187 Pcic_write(sc, PCIC_IOCTL, ioctl); 2188 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, enable); 2189 #if defined(CBB_DEBUG) 2190 { 2191 u_int8_t start_low = 2192 Pcic_read(sc, regbase_win + PCIC_SIA_START_LOW); 2193 u_int8_t start_high = 2194 Pcic_read(sc, regbase_win + PCIC_SIA_START_HIGH); 2195 u_int8_t stop_low = 2196 Pcic_read(sc, regbase_win + PCIC_SIA_STOP_LOW); 2197 u_int8_t stop_high = 2198 Pcic_read(sc, regbase_win + PCIC_SIA_STOP_HIGH); 2199 printf("pccbb_pcmcia_do_io_map start %02x %02x, " 2200 "stop %02x %02x, ioctl %02x enable %02x\n", 2201 start_low, start_high, stop_low, stop_high, ioctl, enable); 2202 } 2203 #endif 2204 } 2205 2206 /* 2207 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2208 * 2209 * This function unmaps I/O region. No return value. 2210 */ 2211 STATIC void 2212 pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t pch, int win) 2213 { 2214 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2215 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2216 int reg; 2217 2218 if (win >= PCIC_IO_WINS || win < 0) { 2219 panic("pccbb_pcmcia_io_unmap: window out of range"); 2220 } 2221 2222 reg = Pcic_read(sc, PCIC_ADDRWIN_ENABLE); 2223 switch (win) { 2224 case 0: 2225 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2226 break; 2227 case 1: 2228 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2229 break; 2230 } 2231 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, reg); 2232 2233 ph->ioalloc &= ~(1 << win); 2234 } 2235 2236 static int 2237 pccbb_pcmcia_wait_ready(struct pccbb_softc *sc) 2238 { 2239 u_int8_t stat; 2240 int i; 2241 2242 /* wait an initial 10ms for quick cards */ 2243 stat = Pcic_read(sc, PCIC_IF_STATUS); 2244 if (stat & PCIC_IF_STATUS_READY) 2245 return (0); 2246 pccbb_pcmcia_delay(sc, 10, "pccwr0"); 2247 for (i = 0; i < 50; i++) { 2248 stat = Pcic_read(sc, PCIC_IF_STATUS); 2249 if (stat & PCIC_IF_STATUS_READY) 2250 return (0); 2251 if ((stat & PCIC_IF_STATUS_CARDDETECT_MASK) != 2252 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2253 return (ENXIO); 2254 /* wait .1s (100ms) each iteration now */ 2255 pccbb_pcmcia_delay(sc, 100, "pccwr1"); 2256 } 2257 2258 printf("pccbb_pcmcia_wait_ready: ready never happened, status=%02x\n", stat); 2259 return (EWOULDBLOCK); 2260 } 2261 2262 /* 2263 * Perform long (msec order) delay. timo is in milliseconds. 2264 */ 2265 static void 2266 pccbb_pcmcia_delay(struct pccbb_softc *sc, int timo, const char *wmesg) 2267 { 2268 #ifdef DIAGNOSTIC 2269 if (timo <= 0) 2270 panic("pccbb_pcmcia_delay: called with timeout %d", timo); 2271 if (!curlwp) 2272 panic("pccbb_pcmcia_delay: called in interrupt context"); 2273 #endif 2274 DPRINTF(("pccbb_pcmcia_delay: \"%s\", sleep %d ms\n", wmesg, timo)); 2275 kpause(wmesg, false, max(mstohz(timo), 1), NULL); 2276 } 2277 2278 /* 2279 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2280 * 2281 * This function enables the card. All information is stored in 2282 * the first argument, pcmcia_chipset_handle_t. 2283 */ 2284 STATIC void 2285 pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2286 { 2287 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2288 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2289 pcireg_t spsr; 2290 int voltage; 2291 int win; 2292 u_int8_t power, intr; 2293 #ifdef DIAGNOSTIC 2294 int reg; 2295 #endif 2296 2297 /* this bit is mostly stolen from pcic_attach_card */ 2298 2299 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2300 2301 /* get card Vcc info */ 2302 spsr = 2303 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2304 CB_SOCKET_STAT); 2305 if (spsr & CB_SOCKET_STAT_5VCARD) { 2306 DPRINTF(("5V card\n")); 2307 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2308 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2309 DPRINTF(("3V card\n")); 2310 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2311 } else { 2312 DPRINTF(("?V card, 0x%x\n", spsr)); /* XXX */ 2313 return; 2314 } 2315 2316 /* disable interrupts; assert RESET */ 2317 intr = Pcic_read(sc, PCIC_INTR); 2318 intr &= PCIC_INTR_ENABLE; 2319 Pcic_write(sc, PCIC_INTR, intr); 2320 2321 /* zero out the address windows */ 2322 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, 0); 2323 2324 /* power down the socket to reset it, clear the card reset pin */ 2325 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2326 2327 /* power off; assert output enable bit */ 2328 power = PCIC_PWRCTL_OE; 2329 Pcic_write(sc, PCIC_PWRCTL, power); 2330 2331 /* power up the socket */ 2332 if (pccbb_power(sc, voltage) == 0) 2333 return; 2334 2335 /* 2336 * Table 4-18 and figure 4-6 of the PC Card specifiction say: 2337 * Vcc Rising Time (Tpr) = 100ms (handled in pccbb_power() above) 2338 * RESET Width (Th (Hi-z RESET)) = 1ms 2339 * RESET Width (Tw (RESET)) = 10us 2340 * 2341 * some machines require some more time to be settled 2342 * for example old toshiba topic bridges! 2343 * (100ms is added here). 2344 */ 2345 pccbb_pcmcia_delay(sc, 200 + 1, "pccen1"); 2346 2347 /* negate RESET */ 2348 intr |= PCIC_INTR_RESET; 2349 Pcic_write(sc, PCIC_INTR, intr); 2350 2351 /* 2352 * RESET Setup Time (Tsu (RESET)) = 20ms 2353 */ 2354 pccbb_pcmcia_delay(sc, 20, "pccen2"); 2355 2356 #ifdef DIAGNOSTIC 2357 reg = Pcic_read(sc, PCIC_IF_STATUS); 2358 if ((reg & PCIC_IF_STATUS_POWERACTIVE) == 0) 2359 printf("pccbb_pcmcia_socket_enable: no power, status=%x\n", reg); 2360 #endif 2361 2362 /* wait for the chip to finish initializing */ 2363 if (pccbb_pcmcia_wait_ready(sc)) { 2364 #ifdef DIAGNOSTIC 2365 printf("pccbb_pcmcia_socket_enable: never became ready\n"); 2366 #endif 2367 /* XXX return a failure status?? */ 2368 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2369 Pcic_write(sc, PCIC_PWRCTL, 0); 2370 return; 2371 } 2372 2373 /* reinstall all the memory and io mappings */ 2374 for (win = 0; win < PCIC_MEM_WINS; ++win) 2375 if (ph->memalloc & (1 << win)) 2376 pccbb_pcmcia_do_mem_map(sc, win); 2377 for (win = 0; win < PCIC_IO_WINS; ++win) 2378 if (ph->ioalloc & (1 << win)) 2379 pccbb_pcmcia_do_io_map(sc, win); 2380 } 2381 2382 /* 2383 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2384 * 2385 * This function disables the card. All information is stored in 2386 * the first argument, pcmcia_chipset_handle_t. 2387 */ 2388 STATIC void 2389 pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t pch) 2390 { 2391 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2392 u_int8_t intr; 2393 2394 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2395 2396 /* disable interrupts; assert RESET */ 2397 intr = Pcic_read(sc, PCIC_INTR); 2398 intr &= PCIC_INTR_ENABLE; 2399 Pcic_write(sc, PCIC_INTR, intr); 2400 2401 /* zero out the address windows */ 2402 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, 0); 2403 2404 /* power down the socket to reset it, clear the card reset pin */ 2405 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2406 2407 /* disable socket: negate output enable bit and power off */ 2408 Pcic_write(sc, PCIC_PWRCTL, 0); 2409 2410 /* 2411 * Vcc Falling Time (Tpf) = 300ms 2412 */ 2413 pccbb_pcmcia_delay(sc, 300, "pccwr1"); 2414 } 2415 2416 STATIC void 2417 pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t pch, int type) 2418 { 2419 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2420 u_int8_t intr; 2421 2422 /* set the card type */ 2423 2424 intr = Pcic_read(sc, PCIC_INTR); 2425 intr &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_CARDTYPE_MASK); 2426 if (type == PCMCIA_IFTYPE_IO) 2427 intr |= PCIC_INTR_CARDTYPE_IO; 2428 else 2429 intr |= PCIC_INTR_CARDTYPE_MEM; 2430 Pcic_write(sc, PCIC_INTR, intr); 2431 2432 DPRINTF(("%s: pccbb_pcmcia_socket_settype type %s %02x\n", 2433 device_xname(sc->sc_dev), 2434 ((type == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2435 } 2436 2437 /* 2438 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2439 * 2440 * This function detects whether a card is in the slot or not. 2441 * If a card is inserted, return 1. Otherwise, return 0. 2442 */ 2443 STATIC int 2444 pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch) 2445 { 2446 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2447 2448 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2449 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2450 } 2451 2452 #if 0 2453 STATIC int 2454 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2455 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2456 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2457 #endif 2458 /* 2459 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2460 * bus_size_t size, 2461 * struct pcmcia_mem_handle *pcmhp) 2462 * 2463 * This function only allocates memory region for pccard. This 2464 * function never maps the allocated region to pccard memory area. 2465 * 2466 * XXX: Why the argument of start address is not in? 2467 */ 2468 STATIC int 2469 pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 2470 struct pcmcia_mem_handle *pcmhp) 2471 { 2472 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2473 bus_space_handle_t memh; 2474 bus_addr_t addr; 2475 bus_size_t sizepg; 2476 #if rbus 2477 rbus_tag_t rb; 2478 #endif 2479 2480 /* Check that the card is still there. */ 2481 if ((Pcic_read(sc, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2482 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2483 return 1; 2484 2485 /* out of sc->memh, allocate as many pages as necessary */ 2486 2487 /* convert size to PCIC pages */ 2488 /* 2489 * This is not enough; when the requested region is on the page 2490 * boundaries, this may calculate wrong result. 2491 */ 2492 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2493 #if 0 2494 if (sizepg > PCIC_MAX_MEM_PAGES) { 2495 return 1; 2496 } 2497 #endif 2498 2499 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2500 return 1; 2501 } 2502 2503 addr = 0; /* XXX gcc -Wuninitialized */ 2504 2505 #if rbus 2506 rb = sc->sc_rbus_memt; 2507 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2508 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2509 &addr, &memh)) { 2510 return 1; 2511 } 2512 #else 2513 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2514 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2515 0, /* boundary */ 2516 0, /* flags */ 2517 &addr, &memh)) { 2518 return 1; 2519 } 2520 #endif 2521 2522 DPRINTF(("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, " 2523 "realsize 0x%lx\n", (unsigned long)addr, (unsigned long)size, 2524 (unsigned long)sizepg * PCIC_MEM_PAGESIZE)); 2525 2526 pcmhp->memt = sc->sc_memt; 2527 pcmhp->memh = memh; 2528 pcmhp->addr = addr; 2529 pcmhp->size = size; 2530 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2531 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2532 pcmhp->mhandle = 0; 2533 /* No offset??? Funny. */ 2534 2535 return 0; 2536 } 2537 2538 /* 2539 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2540 * struct pcmcia_mem_handle *pcmhp) 2541 * 2542 * This function release the memory space allocated by the function 2543 * pccbb_pcmcia_mem_alloc(). 2544 */ 2545 STATIC void 2546 pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2547 struct pcmcia_mem_handle *pcmhp) 2548 { 2549 #if rbus 2550 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2551 2552 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2553 #else 2554 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2555 #endif 2556 } 2557 2558 /* 2559 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2560 * 2561 * This function release the memory space allocated by the function 2562 * pccbb_pcmcia_mem_alloc(). 2563 */ 2564 STATIC void 2565 pccbb_pcmcia_do_mem_map(struct pccbb_softc *sc, int win) 2566 { 2567 int regbase_win; 2568 bus_addr_t phys_addr; 2569 bus_addr_t phys_end; 2570 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2571 2572 #define PCIC_SMM_START_LOW 0 2573 #define PCIC_SMM_START_HIGH 1 2574 #define PCIC_SMM_STOP_LOW 2 2575 #define PCIC_SMM_STOP_HIGH 3 2576 #define PCIC_CMA_LOW 4 2577 #define PCIC_CMA_HIGH 5 2578 2579 u_int8_t start_low, start_high = 0; 2580 u_int8_t stop_low, stop_high; 2581 u_int8_t off_low, off_high; 2582 u_int8_t mem_window; 2583 int reg; 2584 2585 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2586 int mem8 = 2587 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2588 || (kind == PCMCIA_MEM_ATTR); 2589 2590 regbase_win = 0x10 + win * 0x08; 2591 2592 phys_addr = ph->mem[win].addr; 2593 phys_end = phys_addr + ph->mem[win].size; 2594 2595 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2596 (unsigned long)phys_addr, (unsigned long)phys_end, 2597 (unsigned long)ph->mem[win].offset)); 2598 2599 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2600 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2601 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2602 2603 /* bit 19:12 */ 2604 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2605 /* bit 23:20 and bit 7 on */ 2606 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2607 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2608 /* bit 31:24, for 32-bit address */ 2609 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2610 2611 Pcic_write(sc, regbase_win + PCIC_SMM_START_LOW, start_low); 2612 Pcic_write(sc, regbase_win + PCIC_SMM_START_HIGH, start_high); 2613 2614 if (sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2615 Pcic_write(sc, 0x40 + win, mem_window); 2616 } 2617 2618 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2619 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2620 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2621 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2622 2623 Pcic_write(sc, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2624 Pcic_write(sc, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2625 2626 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2627 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2628 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2629 | ((kind == PCMCIA_MEM_ATTR) ? 2630 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2631 2632 Pcic_write(sc, regbase_win + PCIC_CMA_LOW, off_low); 2633 Pcic_write(sc, regbase_win + PCIC_CMA_HIGH, off_high); 2634 2635 reg = Pcic_read(sc, PCIC_ADDRWIN_ENABLE); 2636 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2637 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, reg); 2638 2639 #if defined(CBB_DEBUG) 2640 { 2641 int r1, r2, r3, r4, r5, r6, r7 = 0; 2642 2643 r1 = Pcic_read(sc, regbase_win + PCIC_SMM_START_LOW); 2644 r2 = Pcic_read(sc, regbase_win + PCIC_SMM_START_HIGH); 2645 r3 = Pcic_read(sc, regbase_win + PCIC_SMM_STOP_LOW); 2646 r4 = Pcic_read(sc, regbase_win + PCIC_SMM_STOP_HIGH); 2647 r5 = Pcic_read(sc, regbase_win + PCIC_CMA_LOW); 2648 r6 = Pcic_read(sc, regbase_win + PCIC_CMA_HIGH); 2649 if (sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2650 r7 = Pcic_read(sc, 0x40 + win); 2651 } 2652 2653 printf("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2654 "%02x%02x", win, r1, r2, r3, r4, r5, r6); 2655 if (sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2656 printf(" %02x", r7); 2657 } 2658 printf("\n"); 2659 } 2660 #endif 2661 } 2662 2663 /* 2664 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2665 * bus_addr_t card_addr, bus_size_t size, 2666 * struct pcmcia_mem_handle *pcmhp, 2667 * bus_addr_t *offsetp, int *windowp) 2668 * 2669 * This function maps memory space allocated by the function 2670 * pccbb_pcmcia_mem_alloc(). 2671 */ 2672 STATIC int 2673 pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2674 bus_addr_t card_addr, bus_size_t size, struct pcmcia_mem_handle *pcmhp, 2675 bus_size_t *offsetp, int *windowp) 2676 { 2677 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2678 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2679 bus_addr_t busaddr; 2680 long card_offset; 2681 int win; 2682 2683 /* Check that the card is still there. */ 2684 if ((Pcic_read(sc, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2685 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2686 return 1; 2687 2688 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2689 if ((ph->memalloc & (1 << win)) == 0) { 2690 ph->memalloc |= (1 << win); 2691 break; 2692 } 2693 } 2694 2695 if (win == PCIC_MEM_WINS) { 2696 return 1; 2697 } 2698 2699 *windowp = win; 2700 2701 /* XXX this is pretty gross */ 2702 2703 if (!bus_space_is_equal(sc->sc_memt, pcmhp->memt)) { 2704 panic("pccbb_pcmcia_mem_map memt is bogus"); 2705 } 2706 2707 busaddr = pcmhp->addr; 2708 2709 /* 2710 * compute the address offset to the pcmcia address space for the 2711 * pcic. this is intentionally signed. The masks and shifts below 2712 * will cause TRT to happen in the pcic registers. Deal with making 2713 * sure the address is aligned, and return the alignment offset. 2714 */ 2715 2716 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2717 card_addr -= *offsetp; 2718 2719 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2720 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2721 (u_long) card_addr)); 2722 2723 /* 2724 * include the offset in the size, and decrement size by one, since 2725 * the hw wants start/stop 2726 */ 2727 size += *offsetp - 1; 2728 2729 card_offset = (((long)card_addr) - ((long)busaddr)); 2730 2731 ph->mem[win].addr = busaddr; 2732 ph->mem[win].size = size; 2733 ph->mem[win].offset = card_offset; 2734 ph->mem[win].kind = kind; 2735 2736 pccbb_pcmcia_do_mem_map(sc, win); 2737 2738 return 0; 2739 } 2740 2741 /* 2742 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2743 * int window) 2744 * 2745 * This function unmaps memory space which mapped by the function 2746 * pccbb_pcmcia_mem_map(). 2747 */ 2748 STATIC void 2749 pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, int window) 2750 { 2751 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2752 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2753 int reg; 2754 2755 if (window >= PCIC_MEM_WINS) { 2756 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2757 } 2758 2759 reg = Pcic_read(sc, PCIC_ADDRWIN_ENABLE); 2760 reg &= ~(1 << window); 2761 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, reg); 2762 2763 ph->memalloc &= ~(1 << window); 2764 } 2765 2766 /* 2767 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2768 * struct pcmcia_function *pf, 2769 * int ipl, 2770 * int (*func)(void *), 2771 * void *arg); 2772 * 2773 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2774 */ 2775 STATIC void * 2776 pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2777 struct pcmcia_function *pf, int ipl, int (*func)(void *), void *arg) 2778 { 2779 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2780 2781 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2782 /* what should I do? */ 2783 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2784 DPRINTF(("%s does not provide edge nor pulse " 2785 "interrupt\n", device_xname(sc->sc_dev))); 2786 return NULL; 2787 } 2788 /* 2789 * XXX Noooooo! The interrupt flag must set properly!! 2790 * dumb pcmcia driver!! 2791 */ 2792 } 2793 2794 return pccbb_intr_establish(sc, ipl, func, arg); 2795 } 2796 2797 /* 2798 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2799 * void *ih) 2800 * 2801 * This function disables PC-Card interrupt. 2802 */ 2803 STATIC void 2804 pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 2805 { 2806 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2807 2808 pccbb_intr_disestablish(sc, ih); 2809 } 2810 2811 #if rbus 2812 /* 2813 * static int 2814 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2815 * bus_addr_t addr, bus_size_t size, 2816 * bus_addr_t mask, bus_size_t align, 2817 * int flags, bus_addr_t *addrp; 2818 * bus_space_handle_t *bshp) 2819 * 2820 * This function allocates a portion of memory or io space for 2821 * clients. This function is called from CardBus card drivers. 2822 */ 2823 static int 2824 pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2825 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 2826 int flags, bus_addr_t *addrp, bus_space_handle_t *bshp) 2827 { 2828 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2829 2830 DPRINTF(("pccbb_rbus_cb_space_alloc: addr 0x%lx, size 0x%lx, " 2831 "mask 0x%lx, align 0x%lx\n", (unsigned long)addr, 2832 (unsigned long)size, (unsigned long)mask, (unsigned long)align)); 2833 2834 if (align == 0) { 2835 align = size; 2836 } 2837 2838 if (bus_space_is_equal(rb->rb_bt, sc->sc_memt)) { 2839 if (align < 16) { 2840 return 1; 2841 } 2842 /* 2843 * XXX: align more than 0x1000 to avoid overwrapping 2844 * memory windows for two or more devices. 0x1000 2845 * means memory window's granularity. 2846 * 2847 * Two or more devices should be able to share same 2848 * memory window region. However, overrapping memory 2849 * window is not good because some devices, such as 2850 * 3Com 3C575[BC], have a broken address decoder and 2851 * intrude other's memory region. 2852 */ 2853 if (align < 0x1000) { 2854 align = 0x1000; 2855 } 2856 } else if (bus_space_is_equal(rb->rb_bt, sc->sc_iot)) { 2857 if (align < 4) { 2858 return 1; 2859 } 2860 /* XXX: hack for avoiding ISA image */ 2861 if (mask < 0x0100) { 2862 mask = 0x3ff; 2863 addr = 0x300; 2864 } 2865 2866 } else { 2867 DPRINTF(("pccbb_rbus_cb_space_alloc: Bus space tag 0x%lx is " 2868 "NOT used. io: 0x%lx, mem: 0x%lx\n", 2869 (unsigned long)rb->rb_bt, (unsigned long)sc->sc_iot, 2870 (unsigned long)sc->sc_memt)); 2871 return 1; 2872 /* XXX: panic here? */ 2873 } 2874 2875 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 2876 aprint_normal_dev(sc->sc_dev, "<rbus> no bus space\n"); 2877 return 1; 2878 } 2879 2880 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 2881 2882 return 0; 2883 } 2884 2885 /* 2886 * static int 2887 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 2888 * bus_space_handle_t *bshp, bus_size_t size); 2889 * 2890 * This function is called from CardBus card drivers. 2891 */ 2892 static int 2893 pccbb_rbus_cb_space_free(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2894 bus_space_handle_t bsh, bus_size_t size) 2895 { 2896 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2897 bus_space_tag_t bt = rb->rb_bt; 2898 2899 pccbb_close_win(sc, bt, bsh, size); 2900 2901 if (bus_space_is_equal(bt, sc->sc_memt)) { 2902 } else if (bus_space_is_equal(bt, sc->sc_iot)) { 2903 } else { 2904 return 1; 2905 /* XXX: panic here? */ 2906 } 2907 2908 return rbus_space_free(rb, bsh, size, NULL); 2909 } 2910 #endif /* rbus */ 2911 2912 #if rbus 2913 2914 static int 2915 pccbb_open_win(struct pccbb_softc *sc, bus_space_tag_t bst, bus_addr_t addr, 2916 bus_size_t size, bus_space_handle_t bsh, int flags) 2917 { 2918 struct pccbb_win_chain_head *head; 2919 bus_addr_t align; 2920 2921 head = &sc->sc_iowindow; 2922 align = 0x04; 2923 if (bus_space_is_equal(sc->sc_memt, bst)) { 2924 head = &sc->sc_memwindow; 2925 align = 0x1000; 2926 DPRINTF(("using memory window, 0x%lx 0x%lx 0x%lx\n\n", 2927 (unsigned long)sc->sc_iot, (unsigned long)sc->sc_memt, 2928 (unsigned long)bst)); 2929 } 2930 2931 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 2932 aprint_error_dev(sc->sc_dev, 2933 "pccbb_open_win: %s winlist insert failed\n", 2934 (head == &sc->sc_memwindow) ? "mem" : "io"); 2935 } 2936 pccbb_winset(align, sc, bst); 2937 2938 return 0; 2939 } 2940 2941 static int 2942 pccbb_close_win(struct pccbb_softc *sc, bus_space_tag_t bst, 2943 bus_space_handle_t bsh, bus_size_t size) 2944 { 2945 struct pccbb_win_chain_head *head; 2946 bus_addr_t align; 2947 2948 head = &sc->sc_iowindow; 2949 align = 0x04; 2950 if (bus_space_is_equal(sc->sc_memt, bst)) { 2951 head = &sc->sc_memwindow; 2952 align = 0x1000; 2953 } 2954 2955 if (pccbb_winlist_delete(head, bsh, size)) { 2956 aprint_error_dev(sc->sc_dev, 2957 "pccbb_close_win: %s winlist delete failed\n", 2958 (head == &sc->sc_memwindow) ? "mem" : "io"); 2959 } 2960 pccbb_winset(align, sc, bst); 2961 2962 return 0; 2963 } 2964 2965 static int 2966 pccbb_winlist_insert(struct pccbb_win_chain_head *head, bus_addr_t start, 2967 bus_size_t size, bus_space_handle_t bsh, int flags) 2968 { 2969 struct pccbb_win_chain *chainp, *elem; 2970 2971 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 2972 M_NOWAIT)) == NULL) 2973 return (1); /* fail */ 2974 2975 elem->wc_start = start; 2976 elem->wc_end = start + (size - 1); 2977 elem->wc_handle = bsh; 2978 elem->wc_flags = flags; 2979 2980 TAILQ_FOREACH(chainp, head, wc_list) { 2981 if (chainp->wc_end >= start) 2982 break; 2983 } 2984 if (chainp != NULL) 2985 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 2986 else 2987 TAILQ_INSERT_TAIL(head, elem, wc_list); 2988 return (0); 2989 } 2990 2991 static int 2992 pccbb_winlist_delete(struct pccbb_win_chain_head *head, bus_space_handle_t bsh, 2993 bus_size_t size) 2994 { 2995 struct pccbb_win_chain *chainp; 2996 2997 TAILQ_FOREACH(chainp, head, wc_list) { 2998 if (memcmp(&chainp->wc_handle, &bsh, sizeof(bsh)) == 0) 2999 break; 3000 } 3001 if (chainp == NULL) 3002 return 1; /* fail: no candidate to remove */ 3003 3004 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 3005 printf("pccbb_winlist_delete: window 0x%lx size " 3006 "inconsistent: 0x%lx, 0x%lx\n", 3007 (unsigned long)chainp->wc_start, 3008 (unsigned long)(chainp->wc_end - chainp->wc_start), 3009 (unsigned long)(size - 1)); 3010 return 1; 3011 } 3012 3013 TAILQ_REMOVE(head, chainp, wc_list); 3014 free(chainp, M_DEVBUF); 3015 3016 return 0; 3017 } 3018 3019 static void 3020 pccbb_winset(bus_addr_t align, struct pccbb_softc *sc, bus_space_tag_t bst) 3021 { 3022 pci_chipset_tag_t pc; 3023 pcitag_t tag; 3024 bus_addr_t mask = ~(align - 1); 3025 struct { 3026 pcireg_t win_start; 3027 pcireg_t win_limit; 3028 int win_flags; 3029 } win[2]; 3030 struct pccbb_win_chain *chainp; 3031 int offs; 3032 3033 win[0].win_start = win[1].win_start = 0xffffffff; 3034 win[0].win_limit = win[1].win_limit = 0; 3035 win[0].win_flags = win[1].win_flags = 0; 3036 3037 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3038 offs = PCI_CB_IOBASE0; 3039 if (bus_space_is_equal(sc->sc_memt, bst)) { 3040 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3041 offs = PCI_CB_MEMBASE0; 3042 } 3043 3044 if (chainp != NULL) { 3045 win[0].win_start = chainp->wc_start & mask; 3046 win[0].win_limit = chainp->wc_end & mask; 3047 win[0].win_flags = chainp->wc_flags; 3048 chainp = TAILQ_NEXT(chainp, wc_list); 3049 } 3050 3051 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3052 if (win[1].win_start == 0xffffffff) { 3053 /* window 1 is not used */ 3054 if ((win[0].win_flags == chainp->wc_flags) && 3055 (win[0].win_limit + align >= 3056 (chainp->wc_start & mask))) { 3057 /* concatenate */ 3058 win[0].win_limit = chainp->wc_end & mask; 3059 } else { 3060 /* make new window */ 3061 win[1].win_start = chainp->wc_start & mask; 3062 win[1].win_limit = chainp->wc_end & mask; 3063 win[1].win_flags = chainp->wc_flags; 3064 } 3065 continue; 3066 } 3067 3068 /* Both windows are engaged. */ 3069 if (win[0].win_flags == win[1].win_flags) { 3070 /* same flags */ 3071 if (win[0].win_flags == chainp->wc_flags) { 3072 if (win[1].win_start - (win[0].win_limit + 3073 align) < 3074 (chainp->wc_start & mask) - 3075 ((chainp->wc_end & mask) + align)) { 3076 /* 3077 * merge window 0 and 1, and set win1 3078 * to chainp 3079 */ 3080 win[0].win_limit = win[1].win_limit; 3081 win[1].win_start = 3082 chainp->wc_start & mask; 3083 win[1].win_limit = 3084 chainp->wc_end & mask; 3085 } else { 3086 win[1].win_limit = 3087 chainp->wc_end & mask; 3088 } 3089 } else { 3090 /* different flags */ 3091 3092 /* concatenate win0 and win1 */ 3093 win[0].win_limit = win[1].win_limit; 3094 /* allocate win[1] to new space */ 3095 win[1].win_start = chainp->wc_start & mask; 3096 win[1].win_limit = chainp->wc_end & mask; 3097 win[1].win_flags = chainp->wc_flags; 3098 } 3099 } else { 3100 /* the flags of win[0] and win[1] is different */ 3101 if (win[0].win_flags == chainp->wc_flags) { 3102 win[0].win_limit = chainp->wc_end & mask; 3103 /* 3104 * XXX this creates overlapping windows, so 3105 * what should the poor bridge do if one is 3106 * cachable, and the other is not? 3107 */ 3108 aprint_error_dev(sc->sc_dev, 3109 "overlapping windows\n"); 3110 } else { 3111 win[1].win_limit = chainp->wc_end & mask; 3112 } 3113 } 3114 } 3115 3116 pc = sc->sc_pc; 3117 tag = sc->sc_tag; 3118 pci_conf_write(pc, tag, offs, win[0].win_start); 3119 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3120 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3121 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3122 DPRINTF(("--pccbb_winset: win0 [0x%lx, 0x%lx), win1 [0x%lx, 0x%lx)\n", 3123 (unsigned long)pci_conf_read(pc, tag, offs), 3124 (unsigned long)pci_conf_read(pc, tag, offs + 4) + align, 3125 (unsigned long)pci_conf_read(pc, tag, offs + 8), 3126 (unsigned long)pci_conf_read(pc, tag, offs + 12) + align)); 3127 3128 if (bus_space_is_equal(bst, sc->sc_memt)) { 3129 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BRIDGE_CONTROL_REG); 3130 3131 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 3132 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 3133 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3134 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 3135 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3136 pci_conf_write(pc, tag, PCI_BRIDGE_CONTROL_REG, bcr); 3137 } 3138 } 3139 3140 #endif /* rbus */ 3141 3142 static bool 3143 pccbb_suspend(device_t dv, const pmf_qual_t *qual) 3144 { 3145 struct pccbb_softc *sc = device_private(dv); 3146 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3147 bus_space_handle_t base_memh = sc->sc_base_memh; 3148 pcireg_t reg; 3149 3150 if (sc->sc_pil_intr_enable) 3151 (void)pccbbintr_function(sc); 3152 sc->sc_pil_intr_enable = false; 3153 3154 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3155 /* Disable interrupts. */ 3156 reg &= ~(CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER); 3157 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3158 /* XXX joerg Disable power to the socket? */ 3159 3160 /* XXX flush PCI write */ 3161 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3162 3163 /* reset interrupt */ 3164 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, 3165 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT)); 3166 /* XXX flush PCI write */ 3167 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3168 3169 if (sc->sc_ih != NULL) { 3170 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 3171 sc->sc_ih = NULL; 3172 } 3173 3174 return true; 3175 } 3176 3177 static bool 3178 pccbb_resume(device_t dv, const pmf_qual_t *qual) 3179 { 3180 struct pccbb_softc *sc = device_private(dv); 3181 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3182 bus_space_handle_t base_memh = sc->sc_base_memh; 3183 pcireg_t reg; 3184 3185 pccbb_chipinit(sc); 3186 pccbb_intrinit(sc); 3187 /* setup memory and io space window for CB */ 3188 pccbb_winset(0x1000, sc, sc->sc_memt); 3189 pccbb_winset(0x04, sc, sc->sc_iot); 3190 3191 /* CSC Interrupt: Card detect interrupt on */ 3192 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3193 /* Card detect intr is turned on. */ 3194 reg |= CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; 3195 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3196 /* reset interrupt */ 3197 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3198 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3199 3200 /* 3201 * check for card insertion or removal during suspend period. 3202 * XXX: the code can't cope with card swap (remove then 3203 * insert). how can we detect such situation? 3204 */ 3205 (void)pccbbintr(sc); 3206 3207 sc->sc_pil_intr_enable = true; 3208 3209 return true; 3210 } 3211
Indexes created Fri Sep 26 20:09:58 GMT 2025