pccbb.c revision 1.203.2.1
1 /* $NetBSD: pccbb.c,v 1.203.2.1 2012/04/17 00:07:51 yamt Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: pccbb.c,v 1.203.2.1 2012/04/17 00:07:51 yamt Exp $"); 30 31 /* 32 #define CBB_DEBUG 33 #define SHOW_REGS 34 */ 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/kernel.h> 39 #include <sys/errno.h> 40 #include <sys/ioctl.h> 41 #include <sys/reboot.h> /* for bootverbose */ 42 #include <sys/syslog.h> 43 #include <sys/device.h> 44 #include <sys/malloc.h> 45 #include <sys/proc.h> 46 47 #include <sys/intr.h> 48 #include <sys/bus.h> 49 50 #include <dev/pci/pcivar.h> 51 #include <dev/pci/pcireg.h> 52 #include <dev/pci/pcidevs.h> 53 54 #include <dev/pci/pccbbreg.h> 55 56 #include <dev/cardbus/cardslotvar.h> 57 58 #include <dev/cardbus/cardbusvar.h> 59 60 #include <dev/pcmcia/pcmciareg.h> 61 #include <dev/pcmcia/pcmciavar.h> 62 63 #include <dev/ic/i82365reg.h> 64 #include <dev/pci/pccbbvar.h> 65 66 #ifndef __NetBSD_Version__ 67 struct cfdriver cbb_cd = { 68 NULL, "cbb", DV_DULL 69 }; 70 #endif 71 72 #ifdef CBB_DEBUG 73 #define DPRINTF(x) printf x 74 #define STATIC 75 #else 76 #define DPRINTF(x) 77 #define STATIC static 78 #endif 79 80 int pccbb_burstup = 1; 81 82 /* 83 * delay_ms() is wait in milliseconds. It should be used instead 84 * of delay() if you want to wait more than 1 ms. 85 */ 86 static inline void 87 delay_ms(int millis, struct pccbb_softc *sc) 88 { 89 if (cold) 90 delay(millis * 1000); 91 else 92 kpause("pccbb", false, mstohz(millis), NULL); 93 } 94 95 int pcicbbmatch(device_t, cfdata_t, void *); 96 void pccbbattach(device_t, device_t, void *); 97 void pccbbchilddet(device_t, device_t); 98 int pccbbdetach(device_t, int); 99 int pccbbintr(void *); 100 static void pci113x_insert(void *); 101 static int pccbbintr_function(struct pccbb_softc *); 102 103 static int pccbb_detect_card(struct pccbb_softc *); 104 105 static void pccbb_pcmcia_write(struct pccbb_softc *, int, u_int8_t); 106 static u_int8_t pccbb_pcmcia_read(struct pccbb_softc *, int); 107 #define Pcic_read(sc, reg) pccbb_pcmcia_read((sc), (reg)) 108 #define Pcic_write(sc, reg, val) pccbb_pcmcia_write((sc), (reg), (val)) 109 110 STATIC int cb_reset(struct pccbb_softc *); 111 STATIC int cb_detect_voltage(struct pccbb_softc *); 112 STATIC int cbbprint(void *, const char *); 113 114 static int cb_chipset(u_int32_t, int *); 115 STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *, 116 struct pcmciabus_attach_args *); 117 118 STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int); 119 STATIC int pccbb_power(struct pccbb_softc *sc, int); 120 STATIC int pccbb_power_ct(cardbus_chipset_tag_t, int); 121 STATIC int pccbb_cardenable(struct pccbb_softc * sc, int function); 122 static void *pccbb_intr_establish(struct pccbb_softc *, 123 int level, int (*ih) (void *), void *sc); 124 static void pccbb_intr_disestablish(struct pccbb_softc *, void *ih); 125 126 static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t, 127 int level, int (*ih) (void *), void *sc); 128 static void pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih); 129 130 static pcitag_t pccbb_make_tag(cardbus_chipset_tag_t, int, int); 131 static pcireg_t pccbb_conf_read(cardbus_chipset_tag_t, pcitag_t, int); 132 static void pccbb_conf_write(cardbus_chipset_tag_t, pcitag_t, int, 133 pcireg_t); 134 static void pccbb_chipinit(struct pccbb_softc *); 135 static void pccbb_intrinit(struct pccbb_softc *); 136 137 STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 138 struct pcmcia_mem_handle *); 139 STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t, 140 struct pcmcia_mem_handle *); 141 STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 142 bus_size_t, struct pcmcia_mem_handle *, bus_size_t *, int *); 143 STATIC void pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t, int); 144 STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 145 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 146 STATIC void pccbb_pcmcia_io_free(pcmcia_chipset_handle_t, 147 struct pcmcia_io_handle *); 148 STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 149 bus_size_t, struct pcmcia_io_handle *, int *); 150 STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t, int); 151 STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t, 152 struct pcmcia_function *, int, int (*)(void *), void *); 153 STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t, void *); 154 STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t); 155 STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t); 156 STATIC void pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t, int); 157 STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch); 158 159 static int pccbb_pcmcia_wait_ready(struct pccbb_softc *); 160 static void pccbb_pcmcia_delay(struct pccbb_softc *, int, const char *); 161 162 static void pccbb_pcmcia_do_io_map(struct pccbb_softc *, int); 163 static void pccbb_pcmcia_do_mem_map(struct pccbb_softc *, int); 164 165 /* bus-space allocation and deallocation functions */ 166 167 static int pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t, rbus_tag_t, 168 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 169 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp); 170 static int pccbb_rbus_cb_space_free(cardbus_chipset_tag_t, rbus_tag_t, 171 bus_space_handle_t, bus_size_t); 172 173 174 175 static int pccbb_open_win(struct pccbb_softc *, bus_space_tag_t, 176 bus_addr_t, bus_size_t, bus_space_handle_t, int flags); 177 static int pccbb_close_win(struct pccbb_softc *, bus_space_tag_t, 178 bus_space_handle_t, bus_size_t); 179 static int pccbb_winlist_insert(struct pccbb_win_chain_head *, bus_addr_t, 180 bus_size_t, bus_space_handle_t, int); 181 static int pccbb_winlist_delete(struct pccbb_win_chain_head *, 182 bus_space_handle_t, bus_size_t); 183 static void pccbb_winset(bus_addr_t align, struct pccbb_softc *, 184 bus_space_tag_t); 185 void pccbb_winlist_show(struct pccbb_win_chain *); 186 187 188 /* for config_defer */ 189 static void pccbb_pci_callback(device_t); 190 191 static bool pccbb_suspend(device_t, const pmf_qual_t *); 192 static bool pccbb_resume(device_t, const pmf_qual_t *); 193 194 #if defined SHOW_REGS 195 static void cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, 196 bus_space_tag_t memt, bus_space_handle_t memh); 197 #endif 198 199 CFATTACH_DECL3_NEW(cbb_pci, sizeof(struct pccbb_softc), 200 pcicbbmatch, pccbbattach, pccbbdetach, NULL, NULL, pccbbchilddet, 201 DVF_DETACH_SHUTDOWN); 202 203 static const struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 204 pccbb_pcmcia_mem_alloc, 205 pccbb_pcmcia_mem_free, 206 pccbb_pcmcia_mem_map, 207 pccbb_pcmcia_mem_unmap, 208 pccbb_pcmcia_io_alloc, 209 pccbb_pcmcia_io_free, 210 pccbb_pcmcia_io_map, 211 pccbb_pcmcia_io_unmap, 212 pccbb_pcmcia_intr_establish, 213 pccbb_pcmcia_intr_disestablish, 214 pccbb_pcmcia_socket_enable, 215 pccbb_pcmcia_socket_disable, 216 pccbb_pcmcia_socket_settype, 217 pccbb_pcmcia_card_detect 218 }; 219 220 static const struct cardbus_functions pccbb_funcs = { 221 pccbb_rbus_cb_space_alloc, 222 pccbb_rbus_cb_space_free, 223 pccbb_cb_intr_establish, 224 pccbb_cb_intr_disestablish, 225 pccbb_ctrl, 226 pccbb_power_ct, 227 pccbb_make_tag, 228 pccbb_conf_read, 229 pccbb_conf_write, 230 }; 231 232 int 233 pcicbbmatch(device_t parent, cfdata_t match, void *aux) 234 { 235 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 236 237 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 238 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 239 PCI_INTERFACE(pa->pa_class) == 0) { 240 return 1; 241 } 242 243 return 0; 244 } 245 246 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 247 | ((prod) << PCI_PRODUCT_SHIFT)) 248 249 const struct yenta_chipinfo { 250 pcireg_t yc_id; /* vendor tag | product tag */ 251 int yc_chiptype; 252 int yc_flags; 253 } yc_chipsets[] = { 254 /* Texas Instruments chips */ 255 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 256 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 257 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 258 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 259 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI125X, 260 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 261 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 262 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 263 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 264 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 265 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 266 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 267 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI125X, 268 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 269 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI125X, 270 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 271 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 272 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 273 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 274 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 275 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI1420, 276 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 277 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI125X, 278 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 279 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 280 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 281 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1510), CB_TI12XX, 282 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 283 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1520), CB_TI12XX, 284 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 285 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4410YENTA), CB_TI12XX, 286 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 287 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4520YENTA), CB_TI12XX, 288 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 289 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI7420YENTA), CB_TI12XX, 290 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 291 292 /* Ricoh chips */ 293 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 294 PCCBB_PCMCIA_MEM_32}, 295 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 296 PCCBB_PCMCIA_MEM_32}, 297 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 298 PCCBB_PCMCIA_MEM_32}, 299 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 300 PCCBB_PCMCIA_MEM_32}, 301 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 302 PCCBB_PCMCIA_MEM_32}, 303 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 304 PCCBB_PCMCIA_MEM_32}, 305 306 /* Toshiba products */ 307 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 308 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 309 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 310 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 311 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 312 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 313 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 314 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 315 316 /* Cirrus Logic products */ 317 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 318 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 319 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 320 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 321 322 /* O2 Micro products */ 323 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6729), 324 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 325 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6730), 326 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 327 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6832), 328 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 329 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6836), 330 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 331 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6872), 332 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 333 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6922), 334 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 335 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6933), 336 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 337 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6972), 338 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 339 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_7223), 340 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 341 342 /* sentinel, or Generic chip */ 343 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 344 }; 345 346 static int 347 cb_chipset(u_int32_t pci_id, int *flagp) 348 { 349 const struct yenta_chipinfo *yc; 350 351 /* Loop over except the last default entry. */ 352 for (yc = yc_chipsets; yc < yc_chipsets + 353 __arraycount(yc_chipsets) - 1; yc++) 354 if (pci_id == yc->yc_id) 355 break; 356 357 if (flagp != NULL) 358 *flagp = yc->yc_flags; 359 360 return (yc->yc_chiptype); 361 } 362 363 void 364 pccbbchilddet(device_t self, device_t child) 365 { 366 struct pccbb_softc *sc = device_private(self); 367 int s; 368 369 KASSERT(sc->sc_csc == device_private(child)); 370 371 s = splbio(); 372 if (sc->sc_csc == device_private(child)) 373 sc->sc_csc = NULL; 374 splx(s); 375 } 376 377 void 378 pccbbattach(device_t parent, device_t self, void *aux) 379 { 380 struct pccbb_softc *sc = device_private(self); 381 struct pci_attach_args *pa = aux; 382 pci_chipset_tag_t pc = pa->pa_pc; 383 pcireg_t busreg, reg, sock_base; 384 bus_addr_t sockbase; 385 int flags; 386 387 #ifdef __HAVE_PCCBB_ATTACH_HOOK 388 pccbb_attach_hook(parent, self, pa); 389 #endif 390 391 sc->sc_dev = self; 392 393 mutex_init(&sc->sc_pwr_mtx, MUTEX_DEFAULT, IPL_BIO); 394 cv_init(&sc->sc_pwr_cv, "pccpwr"); 395 396 callout_init(&sc->sc_insert_ch, 0); 397 callout_setfunc(&sc->sc_insert_ch, pci113x_insert, sc); 398 399 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 400 401 pci_aprint_devinfo(pa, NULL); 402 DPRINTF(("(chipflags %x)", flags)); 403 404 TAILQ_INIT(&sc->sc_memwindow); 405 TAILQ_INIT(&sc->sc_iowindow); 406 407 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 408 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 409 410 #if 0 411 printf("pa->pa_memt: %08x vs rbus_mem->rb_bt: %08x\n", 412 pa->pa_memt, sc->sc_rbus_memt->rb_bt); 413 #endif 414 415 sc->sc_flags &= ~CBB_MEMHMAPPED; 416 417 /* 418 * MAP socket registers and ExCA registers on memory-space 419 * When no valid address is set on socket base registers (on pci 420 * config space), get it not polite way. 421 */ 422 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 423 424 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 425 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 426 /* The address must be valid. */ 427 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 428 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, &sc->sc_base_size)) { 429 aprint_error_dev(self, 430 "can't map socket base address 0x%lx\n", 431 (unsigned long)sock_base); 432 /* 433 * I think it's funny: socket base registers must be 434 * mapped on memory space, but ... 435 */ 436 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 437 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 438 &sc->sc_base_size)) { 439 aprint_error_dev(self, 440 "can't map socket base address" 441 " 0x%lx: io mode\n", 442 (unsigned long)sockbase); 443 /* give up... allocate reg space via rbus. */ 444 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 445 } else 446 sc->sc_flags |= CBB_MEMHMAPPED; 447 } else { 448 DPRINTF(("%s: socket base address 0x%lx\n", 449 device_xname(self), 450 (unsigned long)sockbase)); 451 sc->sc_flags |= CBB_MEMHMAPPED; 452 } 453 } 454 455 sc->sc_mem_start = 0; /* XXX */ 456 sc->sc_mem_end = 0xffffffff; /* XXX */ 457 458 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 459 460 /* pccbb_machdep.c end */ 461 462 #if defined CBB_DEBUG 463 { 464 static const char *intrname[] = { "NON", "A", "B", "C", "D" }; 465 aprint_debug_dev(self, "intrpin %s, intrtag %d\n", 466 intrname[pa->pa_intrpin], pa->pa_intrline); 467 } 468 #endif 469 470 /* setup softc */ 471 sc->sc_pc = pc; 472 sc->sc_iot = pa->pa_iot; 473 sc->sc_memt = pa->pa_memt; 474 sc->sc_dmat = pa->pa_dmat; 475 sc->sc_tag = pa->pa_tag; 476 477 memcpy(&sc->sc_pa, pa, sizeof(*pa)); 478 479 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 480 481 /* Disable legacy register mapping. */ 482 switch (sc->sc_chipset) { 483 case CB_RX5C46X: /* fallthrough */ 484 #if 0 485 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 486 case CB_RX5C47X: 487 #endif 488 /* 489 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 490 * cannot be disabled by substituting 0 into PCI_LEGACY 491 * register. Ricoh CardBus bridges have special bits on Bridge 492 * control reg (addr 0x3e on PCI config space). 493 */ 494 reg = pci_conf_read(pc, pa->pa_tag, PCI_BRIDGE_CONTROL_REG); 495 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 496 pci_conf_write(pc, pa->pa_tag, PCI_BRIDGE_CONTROL_REG, reg); 497 break; 498 499 default: 500 /* XXX I don't know proper way to kill legacy I/O. */ 501 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 502 break; 503 } 504 505 if (!pmf_device_register(self, pccbb_suspend, pccbb_resume)) 506 aprint_error_dev(self, "couldn't establish power handler\n"); 507 508 config_defer(self, pccbb_pci_callback); 509 } 510 511 int 512 pccbbdetach(device_t self, int flags) 513 { 514 struct pccbb_softc *sc = device_private(self); 515 pci_chipset_tag_t pc = sc->sc_pa.pa_pc; 516 bus_space_tag_t bmt = sc->sc_base_memt; 517 bus_space_handle_t bmh = sc->sc_base_memh; 518 uint32_t sockmask; 519 int rc; 520 521 if ((rc = config_detach_children(self, flags)) != 0) 522 return rc; 523 524 if (!LIST_EMPTY(&sc->sc_pil)) { 525 panic("%s: interrupt handlers still registered", 526 device_xname(self)); 527 return EBUSY; 528 } 529 530 if (sc->sc_ih != NULL) { 531 pci_intr_disestablish(pc, sc->sc_ih); 532 sc->sc_ih = NULL; 533 } 534 535 /* CSC Interrupt: turn off card detect and power cycle interrupts */ 536 sockmask = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 537 sockmask &= ~(CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | 538 CB_SOCKET_MASK_POWER); 539 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, sockmask); 540 /* reset interrupt */ 541 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 542 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 543 544 switch (sc->sc_flags & (CBB_MEMHMAPPED|CBB_SPECMAPPED)) { 545 case CBB_MEMHMAPPED: 546 bus_space_unmap(bmt, bmh, sc->sc_base_size); 547 break; 548 case CBB_MEMHMAPPED|CBB_SPECMAPPED: 549 #if rbus 550 { 551 pcireg_t sockbase; 552 553 sockbase = pci_conf_read(pc, sc->sc_tag, PCI_SOCKBASE); 554 rbus_space_free(sc->sc_rbus_memt, bmh, 0x1000, 555 NULL); 556 } 557 #else 558 bus_space_free(bmt, bmh, 0x1000); 559 #endif 560 } 561 sc->sc_flags &= ~(CBB_MEMHMAPPED|CBB_SPECMAPPED); 562 563 if (!TAILQ_EMPTY(&sc->sc_iowindow)) 564 aprint_error_dev(self, "i/o windows not empty"); 565 if (!TAILQ_EMPTY(&sc->sc_memwindow)) 566 aprint_error_dev(self, "memory windows not empty"); 567 568 callout_stop(&sc->sc_insert_ch); 569 callout_destroy(&sc->sc_insert_ch); 570 571 mutex_destroy(&sc->sc_pwr_mtx); 572 cv_destroy(&sc->sc_pwr_cv); 573 574 return 0; 575 } 576 577 /* 578 * static void pccbb_pci_callback(device_t self) 579 * 580 * The actual attach routine: get memory space for YENTA register 581 * space, setup YENTA register and route interrupt. 582 * 583 * This function should be deferred because this device may obtain 584 * memory space dynamically. This function must avoid obtaining 585 * memory area which has already kept for another device. 586 */ 587 static void 588 pccbb_pci_callback(device_t self) 589 { 590 struct pccbb_softc *sc = device_private(self); 591 pci_chipset_tag_t pc = sc->sc_pc; 592 bus_addr_t sockbase; 593 struct cbslot_attach_args cba; 594 struct pcmciabus_attach_args paa; 595 struct cardslot_attach_args caa; 596 device_t csc; 597 598 if (!(sc->sc_flags & CBB_MEMHMAPPED)) { 599 /* The socket registers aren't mapped correctly. */ 600 #if rbus 601 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 602 (sc->sc_chipset == CB_RX5C47X 603 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 604 0, &sockbase, &sc->sc_base_memh)) { 605 return; 606 } 607 sc->sc_base_memt = sc->sc_memt; 608 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 609 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 610 device_xname(self), (unsigned long)sockbase, 611 (unsigned long)pci_conf_read(pc, sc->sc_tag, 612 PCI_SOCKBASE))); 613 #else 614 sc->sc_base_memt = sc->sc_memt; 615 #if !defined CBB_PCI_BASE 616 #define CBB_PCI_BASE 0x20000000 617 #endif 618 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 619 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 620 /* cannot allocate memory space */ 621 return; 622 } 623 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 624 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 625 device_xname(self), (unsigned long)sock_base, 626 (unsigned long)pci_conf_read(pc, 627 sc->sc_tag, PCI_SOCKBASE))); 628 #endif 629 sc->sc_flags |= CBB_MEMHMAPPED|CBB_SPECMAPPED; 630 } 631 632 /* clear data structure for child device interrupt handlers */ 633 LIST_INIT(&sc->sc_pil); 634 635 /* bus bridge initialization */ 636 pccbb_chipinit(sc); 637 638 sc->sc_pil_intr_enable = true; 639 640 { 641 u_int32_t sockstat; 642 643 sockstat = bus_space_read_4(sc->sc_base_memt, 644 sc->sc_base_memh, CB_SOCKET_STAT); 645 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 646 sc->sc_flags |= CBB_CARDEXIST; 647 } 648 } 649 650 /* 651 * attach cardbus 652 */ 653 { 654 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 655 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 656 657 /* initialize cbslot_attach */ 658 cba.cba_iot = sc->sc_iot; 659 cba.cba_memt = sc->sc_memt; 660 cba.cba_dmat = sc->sc_dmat; 661 cba.cba_bus = (busreg >> 8) & 0x0ff; 662 cba.cba_cc = (void *)sc; 663 cba.cba_cf = &pccbb_funcs; 664 665 #if rbus 666 cba.cba_rbus_iot = sc->sc_rbus_iot; 667 cba.cba_rbus_memt = sc->sc_rbus_memt; 668 #endif 669 670 cba.cba_cacheline = PCI_CACHELINE(bhlc); 671 cba.cba_max_lattimer = PCI_LATTIMER(bhlc); 672 673 aprint_verbose_dev(self, 674 "cacheline 0x%x lattimer 0x%x\n", 675 cba.cba_cacheline, 676 cba.cba_max_lattimer); 677 aprint_verbose_dev(self, "bhlc 0x%x\n", bhlc); 678 #if defined SHOW_REGS 679 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 680 sc->sc_base_memh); 681 #endif 682 } 683 684 pccbb_pcmcia_attach_setup(sc, &paa); 685 caa.caa_cb_attach = NULL; 686 if (cba.cba_bus == 0) 687 aprint_error_dev(self, 688 "secondary bus number uninitialized; try PCI_BUS_FIXUP\n"); 689 else 690 caa.caa_cb_attach = &cba; 691 caa.caa_16_attach = &paa; 692 693 pccbb_intrinit(sc); 694 695 if (NULL != (csc = config_found_ia(self, "pcmciaslot", &caa, 696 cbbprint))) { 697 DPRINTF(("%s: found cardslot\n", __func__)); 698 sc->sc_csc = device_private(csc); 699 } 700 701 return; 702 } 703 704 705 706 707 708 /* 709 * static void pccbb_chipinit(struct pccbb_softc *sc) 710 * 711 * This function initialize YENTA chip registers listed below: 712 * 1) PCI command reg, 713 * 2) PCI and CardBus latency timer, 714 * 3) route PCI interrupt, 715 * 4) close all memory and io windows. 716 * 5) turn off bus power. 717 * 6) card detect and power cycle interrupts on. 718 * 7) clear interrupt 719 */ 720 static void 721 pccbb_chipinit(struct pccbb_softc *sc) 722 { 723 pci_chipset_tag_t pc = sc->sc_pc; 724 pcitag_t tag = sc->sc_tag; 725 bus_space_tag_t bmt = sc->sc_base_memt; 726 bus_space_handle_t bmh = sc->sc_base_memh; 727 pcireg_t bcr, bhlc, cbctl, csr, lscp, mfunc, mrburst, slotctl, sockctl, 728 sysctrl; 729 730 /* 731 * Set PCI command reg. 732 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 733 */ 734 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 735 /* I believe it is harmless. */ 736 csr |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 737 PCI_COMMAND_MASTER_ENABLE); 738 739 /* All O2 Micro chips have broken parity-error reporting 740 * until proven otherwise. The OZ6933 PCI-CardBus Bridge 741 * is known to have the defect---see PR kern/38698. 742 */ 743 if (sc->sc_chipset != CB_O2MICRO) 744 csr |= PCI_COMMAND_PARITY_ENABLE; 745 746 csr |= PCI_COMMAND_SERR_ENABLE; 747 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 748 749 /* 750 * Set CardBus latency timer. 751 */ 752 lscp = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 753 if (PCI_CB_LATENCY(lscp) < 0x20) { 754 lscp &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 755 lscp |= (0x20 << PCI_CB_LATENCY_SHIFT); 756 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, lscp); 757 } 758 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 759 PCI_CB_LATENCY(lscp), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 760 761 /* 762 * Set PCI latency timer. 763 */ 764 bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG); 765 if (PCI_LATTIMER(bhlc) < 0x10) { 766 bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 767 bhlc |= (0x10 << PCI_LATTIMER_SHIFT); 768 pci_conf_write(pc, tag, PCI_BHLC_REG, bhlc); 769 } 770 DPRINTF(("PCI latency timer 0x%x (%x)\n", 771 PCI_LATTIMER(bhlc), pci_conf_read(pc, tag, PCI_BHLC_REG))); 772 773 774 /* Route functional interrupts to PCI. */ 775 bcr = pci_conf_read(pc, tag, PCI_BRIDGE_CONTROL_REG); 776 bcr |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 777 bcr |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 778 /* assert reset */ 779 bcr |= PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT; 780 /* Set master abort mode to 1, forward SERR# from secondary 781 * to primary, and detect parity errors on secondary. 782 */ 783 bcr |= PCI_BRIDGE_CONTROL_MABRT << PCI_BRIDGE_CONTROL_SHIFT; 784 bcr |= PCI_BRIDGE_CONTROL_SERR << PCI_BRIDGE_CONTROL_SHIFT; 785 bcr |= PCI_BRIDGE_CONTROL_PERE << PCI_BRIDGE_CONTROL_SHIFT; 786 pci_conf_write(pc, tag, PCI_BRIDGE_CONTROL_REG, bcr); 787 788 switch (sc->sc_chipset) { 789 case CB_TI113X: 790 cbctl = pci_conf_read(pc, tag, PCI_CBCTRL); 791 /* This bit is shared, but may read as 0 on some chips, so set 792 it explicitly on both functions. */ 793 cbctl |= PCI113X_CBCTRL_PCI_IRQ_ENA; 794 /* CSC intr enable */ 795 cbctl |= PCI113X_CBCTRL_PCI_CSC; 796 /* functional intr prohibit | prohibit ISA routing */ 797 cbctl &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 798 pci_conf_write(pc, tag, PCI_CBCTRL, cbctl); 799 break; 800 801 case CB_TI1420: 802 sysctrl = pci_conf_read(pc, tag, PCI_SYSCTRL); 803 mrburst = pccbb_burstup 804 ? PCI1420_SYSCTRL_MRBURST : PCI1420_SYSCTRL_MRBURSTDN; 805 if ((sysctrl & PCI1420_SYSCTRL_MRBURST) == mrburst) { 806 printf("%s: %swrite bursts enabled\n", 807 device_xname(sc->sc_dev), 808 pccbb_burstup ? "read/" : ""); 809 } else if (pccbb_burstup) { 810 printf("%s: enabling read/write bursts\n", 811 device_xname(sc->sc_dev)); 812 sysctrl |= PCI1420_SYSCTRL_MRBURST; 813 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 814 } else { 815 printf("%s: disabling read bursts, " 816 "enabling write bursts\n", 817 device_xname(sc->sc_dev)); 818 sysctrl |= PCI1420_SYSCTRL_MRBURSTDN; 819 sysctrl &= ~PCI1420_SYSCTRL_MRBURSTUP; 820 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 821 } 822 /*FALLTHROUGH*/ 823 case CB_TI12XX: 824 /* 825 * Some TI 12xx (and [14][45]xx) based pci cards 826 * sometimes have issues with the MFUNC register not 827 * being initialized due to a bad EEPROM on board. 828 * Laptops that this matters on have this register 829 * properly initialized. 830 * 831 * The TI125X parts have a different register. 832 */ 833 mfunc = pci_conf_read(pc, tag, PCI12XX_MFUNC); 834 if ((mfunc & (PCI12XX_MFUNC_PIN0 | PCI12XX_MFUNC_PIN1)) == 0) { 835 /* Enable PCI interrupt /INTA */ 836 mfunc |= PCI12XX_MFUNC_PIN0_INTA; 837 838 /* XXX this is TI1520 only */ 839 if ((pci_conf_read(pc, tag, PCI_SYSCTRL) & 840 PCI12XX_SYSCTRL_INTRTIE) == 0) 841 /* Enable PCI interrupt /INTB */ 842 mfunc |= PCI12XX_MFUNC_PIN1_INTB; 843 844 pci_conf_write(pc, tag, PCI12XX_MFUNC, mfunc); 845 } 846 /* fallthrough */ 847 848 case CB_TI125X: 849 /* 850 * Disable zoom video. Some machines initialize this 851 * improperly and experience has shown that this helps 852 * prevent strange behavior. 853 */ 854 pci_conf_write(pc, tag, PCI12XX_MMCTRL, 0); 855 856 sysctrl = pci_conf_read(pc, tag, PCI_SYSCTRL); 857 sysctrl |= PCI12XX_SYSCTRL_VCCPROT; 858 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 859 cbctl = pci_conf_read(pc, tag, PCI_CBCTRL); 860 cbctl |= PCI12XX_CBCTRL_CSC; 861 pci_conf_write(pc, tag, PCI_CBCTRL, cbctl); 862 break; 863 864 case CB_TOPIC95B: 865 sockctl = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 866 sockctl |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 867 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, sockctl); 868 slotctl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 869 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 870 device_xname(sc->sc_dev), slotctl)); 871 slotctl |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 872 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 873 slotctl &= ~TOPIC_SLOT_CTRL_SWDETECT; 874 DPRINTF(("0x%x\n", slotctl)); 875 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slotctl); 876 break; 877 878 case CB_TOPIC97: 879 slotctl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 880 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 881 device_xname(sc->sc_dev), slotctl)); 882 slotctl |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 883 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 884 slotctl &= ~TOPIC_SLOT_CTRL_SWDETECT; 885 slotctl |= TOPIC97_SLOT_CTRL_PCIINT; 886 slotctl &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 887 DPRINTF(("0x%x\n", slotctl)); 888 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slotctl); 889 /* make sure to assert LV card support bits */ 890 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 891 0x800 + 0x3e, 892 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 893 0x800 + 0x3e) | 0x03); 894 break; 895 } 896 897 /* Close all memory and I/O windows. */ 898 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 899 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 900 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 901 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 902 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 903 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 904 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 905 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 906 907 /* reset 16-bit pcmcia bus */ 908 bus_space_write_1(bmt, bmh, 0x800 + PCIC_INTR, 909 bus_space_read_1(bmt, bmh, 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 910 911 /* turn off power */ 912 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 913 } 914 915 static void 916 pccbb_intrinit(struct pccbb_softc *sc) 917 { 918 pcireg_t sockmask; 919 const char *intrstr = NULL; 920 pci_intr_handle_t ih; 921 pci_chipset_tag_t pc = sc->sc_pc; 922 bus_space_tag_t bmt = sc->sc_base_memt; 923 bus_space_handle_t bmh = sc->sc_base_memh; 924 925 /* Map and establish the interrupt. */ 926 if (pci_intr_map(&sc->sc_pa, &ih)) { 927 aprint_error_dev(sc->sc_dev, "couldn't map interrupt\n"); 928 return; 929 } 930 intrstr = pci_intr_string(pc, ih); 931 932 /* 933 * XXX pccbbintr should be called under the priority lower 934 * than any other hard interrupts. 935 */ 936 KASSERT(sc->sc_ih == NULL); 937 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 938 939 if (sc->sc_ih == NULL) { 940 aprint_error_dev(sc->sc_dev, "couldn't establish interrupt"); 941 if (intrstr != NULL) 942 aprint_error(" at %s\n", intrstr); 943 else 944 aprint_error("\n"); 945 return; 946 } 947 948 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 949 950 /* CSC Interrupt: Card detect and power cycle interrupts on */ 951 sockmask = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 952 sockmask |= CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | 953 CB_SOCKET_MASK_POWER; 954 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, sockmask); 955 /* reset interrupt */ 956 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 957 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 958 } 959 960 /* 961 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 962 * struct pcmciabus_attach_args *paa) 963 * 964 * This function attaches 16-bit PCcard bus. 965 */ 966 STATIC void 967 pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 968 struct pcmciabus_attach_args *paa) 969 { 970 #if rbus 971 rbus_tag_t rb; 972 #endif 973 /* 974 * We need to do a few things here: 975 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 976 * setting the IRQ numbers to 0. 977 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 978 * routing of CSC interrupts (e.g. card removal) to PCI while in 979 * PCMCIA mode. We just leave this set all the time. 980 * 3) Enable card insertion/removal interrupts in case the chip also 981 * needs that while in PCMCIA mode. 982 * 4) Clear any pending CSC interrupt. 983 */ 984 Pcic_write(sc, PCIC_INTR, PCIC_INTR_ENABLE); 985 if (sc->sc_chipset == CB_TI113X) { 986 Pcic_write(sc, PCIC_CSC_INTR, 0); 987 } else { 988 Pcic_write(sc, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 989 Pcic_read(sc, PCIC_CSC); 990 } 991 992 /* initialize pcmcia bus attachment */ 993 paa->paa_busname = "pcmcia"; 994 paa->pct = &pccbb_pcmcia_funcs; 995 paa->pch = sc; 996 #if rbus 997 rb = sc->sc_rbus_iot; 998 #endif 999 1000 return; 1001 } 1002 1003 /* 1004 * int pccbbintr(arg) 1005 * void *arg; 1006 * This routine handles the interrupt from Yenta PCI-CardBus bridge 1007 * itself. 1008 */ 1009 int 1010 pccbbintr(void *arg) 1011 { 1012 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1013 struct cardslot_softc *csc; 1014 u_int32_t sockevent, sockstate; 1015 bus_space_tag_t memt = sc->sc_base_memt; 1016 bus_space_handle_t memh = sc->sc_base_memh; 1017 1018 if (!device_has_power(sc->sc_dev)) 1019 return 0; 1020 1021 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 1022 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 1023 Pcic_read(sc, PCIC_CSC); 1024 1025 if (sockevent != 0) { 1026 DPRINTF(("%s: enter sockevent %" PRIx32 "\n", 1027 __func__, sockevent)); 1028 } 1029 1030 /* XXX sockevent == CB_SOCKET_EVENT_CSTS|CB_SOCKET_EVENT_POWER 1031 * does occur in the wild. Check for a _POWER event before 1032 * possibly exiting because of an _CSTS event. 1033 */ 1034 if (sockevent & CB_SOCKET_EVENT_POWER) { 1035 DPRINTF(("Powercycling because of socket event\n")); 1036 /* XXX: Does not happen when attaching a 16-bit card */ 1037 mutex_enter(&sc->sc_pwr_mtx); 1038 sc->sc_pwrcycle++; 1039 cv_signal(&sc->sc_pwr_cv); 1040 mutex_exit(&sc->sc_pwr_mtx); 1041 } 1042 1043 /* Sometimes a change of CSTSCHG# accompanies the first 1044 * interrupt from an Atheros WLAN. That generates a 1045 * CB_SOCKET_EVENT_CSTS event on the bridge. The event 1046 * isn't interesting to pccbb(4), so we used to ignore the 1047 * interrupt. Now, let the child devices try to handle 1048 * the interrupt, instead. The Atheros NIC produces 1049 * interrupts more reliably, now: used to be that it would 1050 * only interrupt if the driver avoided powering down the 1051 * NIC's cardslot, and then the NIC would only work after 1052 * it was reset a second time. 1053 */ 1054 if (sockevent == 0 || 1055 (sockevent & ~(CB_SOCKET_EVENT_POWER|CB_SOCKET_EVENT_CD)) != 0) { 1056 /* This intr is not for me: it may be for my child devices. */ 1057 if (sc->sc_pil_intr_enable) { 1058 return pccbbintr_function(sc); 1059 } else { 1060 return 0; 1061 } 1062 } 1063 1064 if (sockevent & CB_SOCKET_EVENT_CD) { 1065 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1066 if (0x00 != (sockstate & CB_SOCKET_STAT_CD)) { 1067 /* A card should be removed. */ 1068 if (sc->sc_flags & CBB_CARDEXIST) { 1069 DPRINTF(("%s: 0x%08x", 1070 device_xname(sc->sc_dev), sockevent)); 1071 DPRINTF((" card removed, 0x%08x\n", sockstate)); 1072 sc->sc_flags &= ~CBB_CARDEXIST; 1073 if ((csc = sc->sc_csc) == NULL) 1074 ; 1075 else if (csc->sc_status & 1076 CARDSLOT_STATUS_CARD_16) { 1077 cardslot_event_throw(csc, 1078 CARDSLOT_EVENT_REMOVAL_16); 1079 } else if (csc->sc_status & 1080 CARDSLOT_STATUS_CARD_CB) { 1081 /* Cardbus intr removed */ 1082 cardslot_event_throw(csc, 1083 CARDSLOT_EVENT_REMOVAL_CB); 1084 } 1085 } else if (sc->sc_flags & CBB_INSERTING) { 1086 sc->sc_flags &= ~CBB_INSERTING; 1087 callout_stop(&sc->sc_insert_ch); 1088 } 1089 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 1090 /* 1091 * The pccbbintr may called from powerdown hook when 1092 * the system resumed, to detect the card 1093 * insertion/removal during suspension. 1094 */ 1095 (sc->sc_flags & CBB_CARDEXIST) == 0) { 1096 if (sc->sc_flags & CBB_INSERTING) { 1097 callout_stop(&sc->sc_insert_ch); 1098 } 1099 callout_schedule(&sc->sc_insert_ch, mstohz(200)); 1100 sc->sc_flags |= CBB_INSERTING; 1101 } 1102 } 1103 1104 return (1); 1105 } 1106 1107 /* 1108 * static int pccbbintr_function(struct pccbb_softc *sc) 1109 * 1110 * This function calls each interrupt handler registered at the 1111 * bridge. The interrupt handlers are called in registered order. 1112 */ 1113 static int 1114 pccbbintr_function(struct pccbb_softc *sc) 1115 { 1116 int retval = 0, val; 1117 struct pccbb_intrhand_list *pil; 1118 int s; 1119 1120 LIST_FOREACH(pil, &sc->sc_pil, pil_next) { 1121 s = splraiseipl(pil->pil_icookie); 1122 val = (*pil->pil_func)(pil->pil_arg); 1123 splx(s); 1124 1125 retval = retval == 1 ? 1 : 1126 retval == 0 ? val : val != 0 ? val : retval; 1127 } 1128 1129 return retval; 1130 } 1131 1132 static void 1133 pci113x_insert(void *arg) 1134 { 1135 struct pccbb_softc *sc = arg; 1136 struct cardslot_softc *csc; 1137 u_int32_t sockevent, sockstate; 1138 1139 if (!(sc->sc_flags & CBB_INSERTING)) { 1140 /* We add a card only under inserting state. */ 1141 return; 1142 } 1143 sc->sc_flags &= ~CBB_INSERTING; 1144 1145 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1146 CB_SOCKET_EVENT); 1147 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1148 CB_SOCKET_STAT); 1149 1150 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1151 DPRINTF(("%s: 0x%08x", device_xname(sc->sc_dev), sockevent)); 1152 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1153 sc->sc_flags |= CBB_CARDEXIST; 1154 /* call pccard interrupt handler here */ 1155 if ((csc = sc->sc_csc) == NULL) 1156 ; 1157 else if (sockstate & CB_SOCKET_STAT_16BIT) { 1158 /* 16-bit card found */ 1159 cardslot_event_throw(csc, CARDSLOT_EVENT_INSERTION_16); 1160 } else if (sockstate & CB_SOCKET_STAT_CB) { 1161 /* cardbus card found */ 1162 cardslot_event_throw(csc, CARDSLOT_EVENT_INSERTION_CB); 1163 } else { 1164 /* who are you? */ 1165 } 1166 } else { 1167 callout_schedule(&sc->sc_insert_ch, mstohz(100)); 1168 } 1169 } 1170 1171 #define PCCBB_PCMCIA_OFFSET 0x800 1172 static u_int8_t 1173 pccbb_pcmcia_read(struct pccbb_softc *sc, int reg) 1174 { 1175 bus_space_barrier(sc->sc_base_memt, sc->sc_base_memh, 1176 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1177 1178 return bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 1179 PCCBB_PCMCIA_OFFSET + reg); 1180 } 1181 1182 static void 1183 pccbb_pcmcia_write(struct pccbb_softc *sc, int reg, u_int8_t val) 1184 { 1185 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 1186 PCCBB_PCMCIA_OFFSET + reg, val); 1187 1188 bus_space_barrier(sc->sc_base_memt, sc->sc_base_memh, 1189 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1190 } 1191 1192 /* 1193 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1194 */ 1195 STATIC int 1196 pccbb_ctrl(cardbus_chipset_tag_t ct, int command) 1197 { 1198 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1199 1200 switch (command) { 1201 case CARDBUS_CD: 1202 if (2 == pccbb_detect_card(sc)) { 1203 int retval = 0; 1204 int status = cb_detect_voltage(sc); 1205 if (PCCARD_VCC_5V & status) { 1206 retval |= CARDBUS_5V_CARD; 1207 } 1208 if (PCCARD_VCC_3V & status) { 1209 retval |= CARDBUS_3V_CARD; 1210 } 1211 if (PCCARD_VCC_XV & status) { 1212 retval |= CARDBUS_XV_CARD; 1213 } 1214 if (PCCARD_VCC_YV & status) { 1215 retval |= CARDBUS_YV_CARD; 1216 } 1217 return retval; 1218 } else { 1219 return 0; 1220 } 1221 case CARDBUS_RESET: 1222 return cb_reset(sc); 1223 case CARDBUS_IO_ENABLE: /* fallthrough */ 1224 case CARDBUS_IO_DISABLE: /* fallthrough */ 1225 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1226 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1227 case CARDBUS_BM_ENABLE: /* fallthrough */ 1228 case CARDBUS_BM_DISABLE: /* fallthrough */ 1229 /* XXX: I think we don't need to call this function below. */ 1230 return pccbb_cardenable(sc, command); 1231 } 1232 1233 return 0; 1234 } 1235 1236 STATIC int 1237 pccbb_power_ct(cardbus_chipset_tag_t ct, int command) 1238 { 1239 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1240 1241 return pccbb_power(sc, command); 1242 } 1243 1244 /* 1245 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1246 * This function returns true when it succeeds and returns false when 1247 * it fails. 1248 */ 1249 STATIC int 1250 pccbb_power(struct pccbb_softc *sc, int command) 1251 { 1252 u_int32_t status, osock_ctrl, sock_ctrl, reg_ctrl; 1253 bus_space_tag_t memt = sc->sc_base_memt; 1254 bus_space_handle_t memh = sc->sc_base_memh; 1255 int on = 0, pwrcycle, times; 1256 struct timeval before, after, diff; 1257 1258 DPRINTF(("pccbb_power: %s and %s [0x%x]\n", 1259 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1260 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1261 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1262 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1263 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1264 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1265 "UNKNOWN", 1266 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1267 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1268 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1269 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1270 "UNKNOWN", command)); 1271 1272 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1273 osock_ctrl = sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1274 1275 switch (command & CARDBUS_VCCMASK) { 1276 case CARDBUS_VCC_UC: 1277 break; 1278 case CARDBUS_VCC_5V: 1279 on++; 1280 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1281 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1282 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1283 } else { 1284 aprint_error_dev(sc->sc_dev, 1285 "BAD voltage request: no 5 V card\n"); 1286 return 0; 1287 } 1288 break; 1289 case CARDBUS_VCC_3V: 1290 on++; 1291 if (CB_SOCKET_STAT_3VCARD & status) { 1292 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1293 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1294 } else { 1295 aprint_error_dev(sc->sc_dev, 1296 "BAD voltage request: no 3.3 V card\n"); 1297 return 0; 1298 } 1299 break; 1300 case CARDBUS_VCC_0V: 1301 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1302 break; 1303 default: 1304 return 0; /* power NEVER changed */ 1305 } 1306 1307 switch (command & CARDBUS_VPPMASK) { 1308 case CARDBUS_VPP_UC: 1309 break; 1310 case CARDBUS_VPP_0V: 1311 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1312 break; 1313 case CARDBUS_VPP_VCC: 1314 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1315 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1316 break; 1317 case CARDBUS_VPP_12V: 1318 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1319 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1320 break; 1321 } 1322 aprint_debug_dev(sc->sc_dev, "osock_ctrl %#" PRIx32 1323 " sock_ctrl %#" PRIx32 "\n", osock_ctrl, sock_ctrl); 1324 1325 microtime(&before); 1326 mutex_enter(&sc->sc_pwr_mtx); 1327 pwrcycle = sc->sc_pwrcycle; 1328 1329 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1330 1331 /* 1332 * Wait as long as 200ms for a power-cycle interrupt. If 1333 * interrupts are enabled, but the socket has already 1334 * changed to the desired status, keep waiting for the 1335 * interrupt. "Consuming" the interrupt in this way keeps 1336 * the interrupt from prematurely waking some subsequent 1337 * pccbb_power call. 1338 * 1339 * XXX Not every bridge interrupts on the ->OFF transition. 1340 * XXX That's ok, we will time-out after 200ms. 1341 * 1342 * XXX The power cycle event will never happen when attaching 1343 * XXX a 16-bit card. That's ok, we will time-out after 1344 * XXX 200ms. 1345 */ 1346 for (times = 5; --times >= 0; ) { 1347 if (cold) 1348 DELAY(40 * 1000); 1349 else { 1350 (void)cv_timedwait(&sc->sc_pwr_cv, &sc->sc_pwr_mtx, 1351 mstohz(40)); 1352 if (pwrcycle == sc->sc_pwrcycle) 1353 continue; 1354 } 1355 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1356 if ((status & CB_SOCKET_STAT_PWRCYCLE) != 0 && on) 1357 break; 1358 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0 && !on) 1359 break; 1360 } 1361 mutex_exit(&sc->sc_pwr_mtx); 1362 microtime(&after); 1363 timersub(&after, &before, &diff); 1364 aprint_debug_dev(sc->sc_dev, "wait took%s %lld.%06lds\n", 1365 (on && times < 0) ? " too long" : "", (long long)diff.tv_sec, 1366 (long)diff.tv_usec); 1367 1368 /* 1369 * Ok, wait a bit longer for things to settle. 1370 */ 1371 if (on && sc->sc_chipset == CB_TOPIC95B) 1372 delay_ms(100, sc); 1373 1374 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1375 1376 if (on && sc->sc_chipset != CB_TOPIC95B) { 1377 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0) 1378 aprint_error_dev(sc->sc_dev, "power on failed?\n"); 1379 } 1380 1381 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1382 aprint_error_dev(sc->sc_dev, 1383 "bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1384 sock_ctrl, status); 1385 aprint_error_dev(sc->sc_dev, "disabling socket\n"); 1386 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1387 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1388 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1389 status &= ~CB_SOCKET_STAT_BADVCC; 1390 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, status); 1391 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1392 CB_SOCKET_STAT)); 1393 return 0; 1394 } 1395 1396 if (sc->sc_chipset == CB_TOPIC97) { 1397 reg_ctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL); 1398 reg_ctrl &= ~TOPIC97_REG_CTRL_TESTMODE; 1399 if ((command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V) 1400 reg_ctrl &= ~TOPIC97_REG_CTRL_CLKRUN_ENA; 1401 else 1402 reg_ctrl |= TOPIC97_REG_CTRL_CLKRUN_ENA; 1403 pci_conf_write(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL, reg_ctrl); 1404 } 1405 1406 return 1; /* power changed correctly */ 1407 } 1408 1409 /* 1410 * static int pccbb_detect_card(struct pccbb_softc *sc) 1411 * return value: 0 if no card exists. 1412 * 1 if 16-bit card exists. 1413 * 2 if cardbus card exists. 1414 */ 1415 static int 1416 pccbb_detect_card(struct pccbb_softc *sc) 1417 { 1418 bus_space_handle_t base_memh = sc->sc_base_memh; 1419 bus_space_tag_t base_memt = sc->sc_base_memt; 1420 u_int32_t sockstat = 1421 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1422 int retval = 0; 1423 1424 /* CD1 and CD2 asserted */ 1425 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1426 /* card must be present */ 1427 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1428 /* NOTACARD DEASSERTED */ 1429 if (CB_SOCKET_STAT_CB & sockstat) { 1430 /* CardBus mode */ 1431 retval = 2; 1432 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1433 /* 16-bit mode */ 1434 retval = 1; 1435 } 1436 } 1437 } 1438 return retval; 1439 } 1440 1441 /* 1442 * STATIC int cb_reset(struct pccbb_softc *sc) 1443 * This function resets CardBus card. 1444 */ 1445 STATIC int 1446 cb_reset(struct pccbb_softc *sc) 1447 { 1448 /* 1449 * Reset Assert at least 20 ms 1450 * Some machines request longer duration. 1451 */ 1452 int reset_duration = 1453 (sc->sc_chipset == CB_RX5C47X ? 400 : 50); 1454 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1455 aprint_debug("%s: enter bcr %" PRIx32 "\n", __func__, bcr); 1456 1457 /* Reset bit Assert (bit 6 at 0x3E) */ 1458 bcr |= PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT; 1459 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr); 1460 aprint_debug("%s: wrote bcr %" PRIx32 "\n", __func__, bcr); 1461 delay_ms(reset_duration, sc); 1462 1463 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1464 /* Reset bit Deassert (bit 6 at 0x3E) */ 1465 bcr &= ~(PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT); 1466 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, 1467 bcr); 1468 aprint_debug("%s: wrote bcr %" PRIx32 "\n", __func__, bcr); 1469 delay_ms(reset_duration, sc); 1470 aprint_debug("%s: end of delay\n", __func__); 1471 } 1472 /* No card found on the slot. Keep Reset. */ 1473 return 1; 1474 } 1475 1476 /* 1477 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1478 * This function detect card Voltage. 1479 */ 1480 STATIC int 1481 cb_detect_voltage(struct pccbb_softc *sc) 1482 { 1483 u_int32_t psr; /* socket present-state reg */ 1484 bus_space_tag_t iot = sc->sc_base_memt; 1485 bus_space_handle_t ioh = sc->sc_base_memh; 1486 int vol = PCCARD_VCC_UKN; /* set 0 */ 1487 1488 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1489 1490 if (0x400u & psr) { 1491 vol |= PCCARD_VCC_5V; 1492 } 1493 if (0x800u & psr) { 1494 vol |= PCCARD_VCC_3V; 1495 } 1496 1497 return vol; 1498 } 1499 1500 STATIC int 1501 cbbprint(void *aux, const char *pcic) 1502 { 1503 #if 0 1504 struct cbslot_attach_args *cba = aux; 1505 1506 if (cba->cba_slot >= 0) { 1507 aprint_normal(" slot %d", cba->cba_slot); 1508 } 1509 #endif 1510 return UNCONF; 1511 } 1512 1513 /* 1514 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1515 * This function enables and disables the card 1516 */ 1517 STATIC int 1518 pccbb_cardenable(struct pccbb_softc *sc, int function) 1519 { 1520 u_int32_t command = 1521 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1522 1523 DPRINTF(("pccbb_cardenable:")); 1524 switch (function) { 1525 case CARDBUS_IO_ENABLE: 1526 command |= PCI_COMMAND_IO_ENABLE; 1527 break; 1528 case CARDBUS_IO_DISABLE: 1529 command &= ~PCI_COMMAND_IO_ENABLE; 1530 break; 1531 case CARDBUS_MEM_ENABLE: 1532 command |= PCI_COMMAND_MEM_ENABLE; 1533 break; 1534 case CARDBUS_MEM_DISABLE: 1535 command &= ~PCI_COMMAND_MEM_ENABLE; 1536 break; 1537 case CARDBUS_BM_ENABLE: 1538 command |= PCI_COMMAND_MASTER_ENABLE; 1539 break; 1540 case CARDBUS_BM_DISABLE: 1541 command &= ~PCI_COMMAND_MASTER_ENABLE; 1542 break; 1543 default: 1544 return 0; 1545 } 1546 1547 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1548 DPRINTF((" command reg 0x%x\n", command)); 1549 return 1; 1550 } 1551 1552 #if !rbus 1553 static int 1554 pccbb_io_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 1555 { 1556 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1557 int basereg; 1558 int limitreg; 1559 1560 if ((win < 0) || (win > 2)) { 1561 #if defined DIAGNOSTIC 1562 printf("cardbus_io_open: window out of range %d\n", win); 1563 #endif 1564 return 0; 1565 } 1566 1567 basereg = win * 8 + PCI_CB_IOBASE0; 1568 limitreg = win * 8 + PCI_CB_IOLIMIT0; 1569 1570 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1571 start, basereg, end, limitreg)); 1572 1573 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1574 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1575 return 1; 1576 } 1577 1578 /* 1579 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1580 */ 1581 static int 1582 pccbb_io_close(cardbus_chipset_tag_t ct, int win) 1583 { 1584 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1585 int basereg; 1586 int limitreg; 1587 1588 if ((win < 0) || (win > 2)) { 1589 #if defined DIAGNOSTIC 1590 printf("cardbus_io_close: window out of range %d\n", win); 1591 #endif 1592 return 0; 1593 } 1594 1595 basereg = win * 8 + PCI_CB_IOBASE0; 1596 limitreg = win * 8 + PCI_CB_IOLIMIT0; 1597 1598 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1599 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1600 return 1; 1601 } 1602 1603 static int 1604 pccbb_mem_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 1605 { 1606 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1607 int basereg; 1608 int limitreg; 1609 1610 if ((win < 0) || (win > 2)) { 1611 #if defined DIAGNOSTIC 1612 printf("cardbus_mem_open: window out of range %d\n", win); 1613 #endif 1614 return 0; 1615 } 1616 1617 basereg = win * 8 + PCI_CB_MEMBASE0; 1618 limitreg = win * 8 + PCI_CB_MEMLIMIT0; 1619 1620 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1621 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1622 return 1; 1623 } 1624 1625 static int 1626 pccbb_mem_close(cardbus_chipset_tag_t ct, int win) 1627 { 1628 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1629 int basereg; 1630 int limitreg; 1631 1632 if ((win < 0) || (win > 2)) { 1633 #if defined DIAGNOSTIC 1634 printf("cardbus_mem_close: window out of range %d\n", win); 1635 #endif 1636 return 0; 1637 } 1638 1639 basereg = win * 8 + PCI_CB_MEMBASE0; 1640 limitreg = win * 8 + PCI_CB_MEMLIMIT0; 1641 1642 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1643 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1644 return 1; 1645 } 1646 #endif 1647 1648 /* 1649 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1650 * int level, 1651 * int (* func)(void *), 1652 * void *arg) 1653 * 1654 * This function registers an interrupt handler at the bridge, in 1655 * order not to call the interrupt handlers of child devices when 1656 * a card-deletion interrupt occurs. 1657 * 1658 * The argument level is not used. 1659 */ 1660 static void * 1661 pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, int level, 1662 int (*func)(void *), void *arg) 1663 { 1664 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1665 1666 return pccbb_intr_establish(sc, level, func, arg); 1667 } 1668 1669 1670 /* 1671 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1672 * void *ih) 1673 * 1674 * This function removes an interrupt handler pointed by ih. 1675 */ 1676 static void 1677 pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih) 1678 { 1679 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1680 1681 pccbb_intr_disestablish(sc, ih); 1682 } 1683 1684 1685 void 1686 pccbb_intr_route(struct pccbb_softc *sc) 1687 { 1688 pcireg_t bcr, cbctrl; 1689 1690 /* initialize bridge intr routing */ 1691 bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1692 bcr &= ~CB_BCR_INTR_IREQ_ENABLE; 1693 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr); 1694 1695 switch (sc->sc_chipset) { 1696 case CB_TI113X: 1697 cbctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1698 /* functional intr enabled */ 1699 cbctrl |= PCI113X_CBCTRL_PCI_INTR; 1700 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, cbctrl); 1701 break; 1702 default: 1703 break; 1704 } 1705 } 1706 1707 /* 1708 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1709 * int irq, 1710 * int level, 1711 * int (* func)(void *), 1712 * void *arg) 1713 * 1714 * This function registers an interrupt handler at the bridge, in 1715 * order not to call the interrupt handlers of child devices when 1716 * a card-deletion interrupt occurs. 1717 * 1718 */ 1719 static void * 1720 pccbb_intr_establish(struct pccbb_softc *sc, int level, 1721 int (*func)(void *), void *arg) 1722 { 1723 struct pccbb_intrhand_list *pil, *newpil; 1724 1725 DPRINTF(("pccbb_intr_establish start. %p\n", LIST_FIRST(&sc->sc_pil))); 1726 1727 if (LIST_EMPTY(&sc->sc_pil)) { 1728 pccbb_intr_route(sc); 1729 } 1730 1731 /* 1732 * Allocate a room for interrupt handler structure. 1733 */ 1734 if (NULL == (newpil = 1735 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1736 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1737 return NULL; 1738 } 1739 1740 newpil->pil_func = func; 1741 newpil->pil_arg = arg; 1742 newpil->pil_icookie = makeiplcookie(level); 1743 1744 if (LIST_EMPTY(&sc->sc_pil)) { 1745 LIST_INSERT_HEAD(&sc->sc_pil, newpil, pil_next); 1746 } else { 1747 for (pil = LIST_FIRST(&sc->sc_pil); 1748 LIST_NEXT(pil, pil_next) != NULL; 1749 pil = LIST_NEXT(pil, pil_next)); 1750 LIST_INSERT_AFTER(pil, newpil, pil_next); 1751 } 1752 1753 DPRINTF(("pccbb_intr_establish add pil. %p\n", 1754 LIST_FIRST(&sc->sc_pil))); 1755 1756 return newpil; 1757 } 1758 1759 /* 1760 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1761 * void *ih) 1762 * 1763 * This function removes an interrupt handler pointed by ih. ih 1764 * should be the value returned by cardbus_intr_establish() or 1765 * NULL. 1766 * 1767 * When ih is NULL, this function will do nothing. 1768 */ 1769 static void 1770 pccbb_intr_disestablish(struct pccbb_softc *sc, void *ih) 1771 { 1772 struct pccbb_intrhand_list *pil; 1773 pcireg_t reg; 1774 1775 DPRINTF(("pccbb_intr_disestablish start. %p\n", 1776 LIST_FIRST(&sc->sc_pil))); 1777 1778 if (ih == NULL) { 1779 /* intr handler is not set */ 1780 DPRINTF(("pccbb_intr_disestablish: no ih\n")); 1781 return; 1782 } 1783 1784 #ifdef DIAGNOSTIC 1785 LIST_FOREACH(pil, &sc->sc_pil, pil_next) { 1786 DPRINTF(("pccbb_intr_disestablish: pil %p\n", pil)); 1787 if (pil == ih) { 1788 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1789 break; 1790 } 1791 } 1792 if (pil == NULL) { 1793 panic("pccbb_intr_disestablish: %s cannot find pil %p", 1794 device_xname(sc->sc_dev), ih); 1795 } 1796 #endif 1797 1798 pil = (struct pccbb_intrhand_list *)ih; 1799 LIST_REMOVE(pil, pil_next); 1800 free(pil, M_DEVBUF); 1801 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1802 1803 if (LIST_EMPTY(&sc->sc_pil)) { 1804 /* No interrupt handlers */ 1805 1806 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1807 1808 /* stop routing PCI intr */ 1809 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1810 reg |= CB_BCR_INTR_IREQ_ENABLE; 1811 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, reg); 1812 1813 switch (sc->sc_chipset) { 1814 case CB_TI113X: 1815 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1816 /* functional intr disabled */ 1817 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1818 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1819 break; 1820 default: 1821 break; 1822 } 1823 } 1824 } 1825 1826 #if defined SHOW_REGS 1827 static void 1828 cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, bus_space_tag_t memt, 1829 bus_space_handle_t memh) 1830 { 1831 int i; 1832 printf("PCI config regs:"); 1833 for (i = 0; i < 0x50; i += 4) { 1834 if (i % 16 == 0) 1835 printf("\n 0x%02x:", i); 1836 printf(" %08x", pci_conf_read(pc, tag, i)); 1837 } 1838 for (i = 0x80; i < 0xb0; i += 4) { 1839 if (i % 16 == 0) 1840 printf("\n 0x%02x:", i); 1841 printf(" %08x", pci_conf_read(pc, tag, i)); 1842 } 1843 1844 if (memh == 0) { 1845 printf("\n"); 1846 return; 1847 } 1848 1849 printf("\nsocket regs:"); 1850 for (i = 0; i <= 0x10; i += 0x04) 1851 printf(" %08x", bus_space_read_4(memt, memh, i)); 1852 printf("\nExCA regs:"); 1853 for (i = 0; i < 0x08; ++i) 1854 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1855 printf("\n"); 1856 return; 1857 } 1858 #endif 1859 1860 /* 1861 * static pcitag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1862 * int busno, int function) 1863 * This is the function to make a tag to access config space of 1864 * a CardBus Card. It works same as pci_conf_read. 1865 */ 1866 static pcitag_t 1867 pccbb_make_tag(cardbus_chipset_tag_t cc, int busno, int function) 1868 { 1869 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1870 1871 return pci_make_tag(sc->sc_pc, busno, 0, function); 1872 } 1873 1874 /* 1875 * pccbb_conf_read 1876 * 1877 * This is the function to read the config space of a CardBus card. 1878 * It works the same as pci_conf_read(9). 1879 */ 1880 static pcireg_t 1881 pccbb_conf_read(cardbus_chipset_tag_t cc, pcitag_t tag, int offset) 1882 { 1883 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1884 pcitag_t brtag = sc->sc_tag; 1885 pcireg_t reg; 1886 1887 /* 1888 * clear cardbus master abort status; it is OK to write without 1889 * reading before because all bits are r/o or w1tc 1890 */ 1891 pci_conf_write(sc->sc_pc, brtag, PCI_CBB_SECSTATUS, 1892 CBB_SECSTATUS_CBMABORT); 1893 reg = pci_conf_read(sc->sc_pc, tag, offset); 1894 /* check cardbus master abort status */ 1895 if (pci_conf_read(sc->sc_pc, brtag, PCI_CBB_SECSTATUS) 1896 & CBB_SECSTATUS_CBMABORT) 1897 return (0xffffffff); 1898 return reg; 1899 } 1900 1901 /* 1902 * pccbb_conf_write 1903 * 1904 * This is the function to write the config space of a CardBus 1905 * card. It works the same as pci_conf_write(9). 1906 */ 1907 static void 1908 pccbb_conf_write(cardbus_chipset_tag_t cc, pcitag_t tag, int reg, pcireg_t val) 1909 { 1910 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1911 1912 pci_conf_write(sc->sc_pc, tag, reg, val); 1913 } 1914 1915 #if 0 1916 STATIC int 1917 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1918 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 1919 int speed, int flags, 1920 bus_space_handle_t * iohp) 1921 #endif 1922 /* 1923 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1924 * bus_addr_t start, bus_size_t size, 1925 * bus_size_t align, 1926 * struct pcmcia_io_handle *pcihp 1927 * 1928 * This function only allocates I/O region for pccard. This function 1929 * never maps the allocated region to pccard I/O area. 1930 * 1931 * XXX: The interface of this function is not very good, I believe. 1932 */ 1933 STATIC int 1934 pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, 1935 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 1936 { 1937 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 1938 bus_addr_t ioaddr; 1939 int flags = 0; 1940 bus_space_tag_t iot; 1941 bus_space_handle_t ioh; 1942 bus_addr_t mask; 1943 #if rbus 1944 rbus_tag_t rb; 1945 #endif 1946 if (align == 0) { 1947 align = size; /* XXX: funny??? */ 1948 } 1949 1950 if (start != 0) { 1951 /* XXX: assume all card decode lower 10 bits by its hardware */ 1952 mask = 0x3ff; 1953 /* enforce to use only masked address */ 1954 start &= mask; 1955 } else { 1956 /* 1957 * calculate mask: 1958 * 1. get the most significant bit of size (call it msb). 1959 * 2. compare msb with the value of size. 1960 * 3. if size is larger, shift msb left once. 1961 * 4. obtain mask value to decrement msb. 1962 */ 1963 bus_size_t size_tmp = size; 1964 int shifts = 0; 1965 1966 mask = 1; 1967 while (size_tmp) { 1968 ++shifts; 1969 size_tmp >>= 1; 1970 } 1971 mask = (1 << shifts); 1972 if (mask < size) { 1973 mask <<= 1; 1974 } 1975 --mask; 1976 } 1977 1978 /* 1979 * Allocate some arbitrary I/O space. 1980 */ 1981 1982 iot = sc->sc_iot; 1983 1984 #if rbus 1985 rb = sc->sc_rbus_iot; 1986 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 1987 return 1; 1988 } 1989 DPRINTF(("pccbb_pcmcia_io_alloc alloc port 0x%lx+0x%lx\n", 1990 (u_long) ioaddr, (u_long) size)); 1991 #else 1992 if (start) { 1993 ioaddr = start; 1994 if (bus_space_map(iot, start, size, 0, &ioh)) { 1995 return 1; 1996 } 1997 DPRINTF(("pccbb_pcmcia_io_alloc map port 0x%lx+0x%lx\n", 1998 (u_long) ioaddr, (u_long) size)); 1999 } else { 2000 flags |= PCMCIA_IO_ALLOCATED; 2001 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 2002 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 2003 size, align, 0, 0, &ioaddr, &ioh)) { 2004 /* No room be able to be get. */ 2005 return 1; 2006 } 2007 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2008 (u_long) ioaddr, (u_long) size)); 2009 } 2010 #endif 2011 2012 pcihp->iot = iot; 2013 pcihp->ioh = ioh; 2014 pcihp->addr = ioaddr; 2015 pcihp->size = size; 2016 pcihp->flags = flags; 2017 2018 return 0; 2019 } 2020 2021 /* 2022 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2023 * struct pcmcia_io_handle *pcihp) 2024 * 2025 * This function only frees I/O region for pccard. 2026 * 2027 * XXX: The interface of this function is not very good, I believe. 2028 */ 2029 void 2030 pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2031 struct pcmcia_io_handle *pcihp) 2032 { 2033 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2034 #if !rbus 2035 bus_space_tag_t iot = pcihp->iot; 2036 #endif 2037 bus_space_handle_t ioh = pcihp->ioh; 2038 bus_size_t size = pcihp->size; 2039 2040 #if rbus 2041 rbus_tag_t rb = sc->sc_rbus_iot; 2042 2043 rbus_space_free(rb, ioh, size, NULL); 2044 #else 2045 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 2046 bus_space_free(iot, ioh, size); 2047 else 2048 bus_space_unmap(iot, ioh, size); 2049 #endif 2050 } 2051 2052 /* 2053 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 2054 * bus_addr_t offset, bus_size_t size, 2055 * struct pcmcia_io_handle *pcihp, 2056 * int *windowp) 2057 * 2058 * This function maps the allocated I/O region to pccard. This function 2059 * never allocates any I/O region for pccard I/O area. I don't 2060 * understand why the original authors of pcmciabus separated alloc and 2061 * map. I believe the two must be unite. 2062 * 2063 * XXX: no wait timing control? 2064 */ 2065 int 2066 pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, bus_addr_t offset, 2067 bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp) 2068 { 2069 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2070 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2071 bus_addr_t ioaddr = pcihp->addr + offset; 2072 int i, win; 2073 #if defined CBB_DEBUG 2074 static const char *width_names[] = { "dynamic", "io8", "io16" }; 2075 #endif 2076 2077 /* Sanity check I/O handle. */ 2078 2079 if (!bus_space_is_equal(sc->sc_iot, pcihp->iot)) { 2080 panic("pccbb_pcmcia_io_map iot is bogus"); 2081 } 2082 2083 /* XXX Sanity check offset/size. */ 2084 2085 win = -1; 2086 for (i = 0; i < PCIC_IO_WINS; i++) { 2087 if ((ph->ioalloc & (1 << i)) == 0) { 2088 win = i; 2089 ph->ioalloc |= (1 << i); 2090 break; 2091 } 2092 } 2093 2094 if (win == -1) { 2095 return 1; 2096 } 2097 2098 *windowp = win; 2099 2100 /* XXX this is pretty gross */ 2101 2102 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2103 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2104 2105 /* XXX wtf is this doing here? */ 2106 2107 #if 0 2108 printf(" port 0x%lx", (u_long) ioaddr); 2109 if (size > 1) { 2110 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2111 } 2112 #endif 2113 2114 ph->io[win].addr = ioaddr; 2115 ph->io[win].size = size; 2116 ph->io[win].width = width; 2117 2118 /* actual dirty register-value changing in the function below. */ 2119 pccbb_pcmcia_do_io_map(sc, win); 2120 2121 return 0; 2122 } 2123 2124 /* 2125 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2126 * 2127 * This function changes register-value to map I/O region for pccard. 2128 */ 2129 static void 2130 pccbb_pcmcia_do_io_map(struct pccbb_softc *sc, int win) 2131 { 2132 static u_int8_t pcic_iowidth[3] = { 2133 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2134 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2135 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2136 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2137 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2138 }; 2139 2140 #define PCIC_SIA_START_LOW 0 2141 #define PCIC_SIA_START_HIGH 1 2142 #define PCIC_SIA_STOP_LOW 2 2143 #define PCIC_SIA_STOP_HIGH 3 2144 2145 int regbase_win = 0x8 + win * 0x04; 2146 u_int8_t ioctl, enable; 2147 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2148 2149 DPRINTF(("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx " 2150 "width %d\n", win, (unsigned long)ph->io[win].addr, 2151 (unsigned long)ph->io[win].size, ph->io[win].width * 8)); 2152 2153 Pcic_write(sc, regbase_win + PCIC_SIA_START_LOW, 2154 ph->io[win].addr & 0xff); 2155 Pcic_write(sc, regbase_win + PCIC_SIA_START_HIGH, 2156 (ph->io[win].addr >> 8) & 0xff); 2157 2158 Pcic_write(sc, regbase_win + PCIC_SIA_STOP_LOW, 2159 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2160 Pcic_write(sc, regbase_win + PCIC_SIA_STOP_HIGH, 2161 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2162 2163 ioctl = Pcic_read(sc, PCIC_IOCTL); 2164 enable = Pcic_read(sc, PCIC_ADDRWIN_ENABLE); 2165 switch (win) { 2166 case 0: 2167 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2168 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2169 PCIC_IOCTL_IO0_DATASIZE_MASK); 2170 ioctl |= pcic_iowidth[ph->io[win].width]; 2171 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2172 break; 2173 case 1: 2174 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2175 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2176 PCIC_IOCTL_IO1_DATASIZE_MASK); 2177 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2178 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2179 break; 2180 } 2181 Pcic_write(sc, PCIC_IOCTL, ioctl); 2182 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, enable); 2183 #if defined(CBB_DEBUG) 2184 { 2185 u_int8_t start_low = 2186 Pcic_read(sc, regbase_win + PCIC_SIA_START_LOW); 2187 u_int8_t start_high = 2188 Pcic_read(sc, regbase_win + PCIC_SIA_START_HIGH); 2189 u_int8_t stop_low = 2190 Pcic_read(sc, regbase_win + PCIC_SIA_STOP_LOW); 2191 u_int8_t stop_high = 2192 Pcic_read(sc, regbase_win + PCIC_SIA_STOP_HIGH); 2193 printf("pccbb_pcmcia_do_io_map start %02x %02x, " 2194 "stop %02x %02x, ioctl %02x enable %02x\n", 2195 start_low, start_high, stop_low, stop_high, ioctl, enable); 2196 } 2197 #endif 2198 } 2199 2200 /* 2201 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2202 * 2203 * This function unmaps I/O region. No return value. 2204 */ 2205 STATIC void 2206 pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t pch, int win) 2207 { 2208 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2209 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2210 int reg; 2211 2212 if (win >= PCIC_IO_WINS || win < 0) { 2213 panic("pccbb_pcmcia_io_unmap: window out of range"); 2214 } 2215 2216 reg = Pcic_read(sc, PCIC_ADDRWIN_ENABLE); 2217 switch (win) { 2218 case 0: 2219 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2220 break; 2221 case 1: 2222 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2223 break; 2224 } 2225 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, reg); 2226 2227 ph->ioalloc &= ~(1 << win); 2228 } 2229 2230 static int 2231 pccbb_pcmcia_wait_ready(struct pccbb_softc *sc) 2232 { 2233 u_int8_t stat; 2234 int i; 2235 2236 /* wait an initial 10ms for quick cards */ 2237 stat = Pcic_read(sc, PCIC_IF_STATUS); 2238 if (stat & PCIC_IF_STATUS_READY) 2239 return (0); 2240 pccbb_pcmcia_delay(sc, 10, "pccwr0"); 2241 for (i = 0; i < 50; i++) { 2242 stat = Pcic_read(sc, PCIC_IF_STATUS); 2243 if (stat & PCIC_IF_STATUS_READY) 2244 return (0); 2245 if ((stat & PCIC_IF_STATUS_CARDDETECT_MASK) != 2246 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2247 return (ENXIO); 2248 /* wait .1s (100ms) each iteration now */ 2249 pccbb_pcmcia_delay(sc, 100, "pccwr1"); 2250 } 2251 2252 printf("pccbb_pcmcia_wait_ready: ready never happened, status=%02x\n", stat); 2253 return (EWOULDBLOCK); 2254 } 2255 2256 /* 2257 * Perform long (msec order) delay. timo is in milliseconds. 2258 */ 2259 static void 2260 pccbb_pcmcia_delay(struct pccbb_softc *sc, int timo, const char *wmesg) 2261 { 2262 #ifdef DIAGNOSTIC 2263 if (timo <= 0) 2264 panic("pccbb_pcmcia_delay: called with timeout %d", timo); 2265 if (!curlwp) 2266 panic("pccbb_pcmcia_delay: called in interrupt context"); 2267 #endif 2268 DPRINTF(("pccbb_pcmcia_delay: \"%s\", sleep %d ms\n", wmesg, timo)); 2269 kpause(wmesg, false, max(mstohz(timo), 1), NULL); 2270 } 2271 2272 /* 2273 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2274 * 2275 * This function enables the card. All information is stored in 2276 * the first argument, pcmcia_chipset_handle_t. 2277 */ 2278 STATIC void 2279 pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2280 { 2281 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2282 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2283 pcireg_t spsr; 2284 int voltage; 2285 int win; 2286 u_int8_t power, intr; 2287 #ifdef DIAGNOSTIC 2288 int reg; 2289 #endif 2290 2291 /* this bit is mostly stolen from pcic_attach_card */ 2292 2293 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2294 2295 /* get card Vcc info */ 2296 spsr = 2297 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2298 CB_SOCKET_STAT); 2299 if (spsr & CB_SOCKET_STAT_5VCARD) { 2300 DPRINTF(("5V card\n")); 2301 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2302 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2303 DPRINTF(("3V card\n")); 2304 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2305 } else { 2306 DPRINTF(("?V card, 0x%x\n", spsr)); /* XXX */ 2307 return; 2308 } 2309 2310 /* disable interrupts; assert RESET */ 2311 intr = Pcic_read(sc, PCIC_INTR); 2312 intr &= PCIC_INTR_ENABLE; 2313 Pcic_write(sc, PCIC_INTR, intr); 2314 2315 /* zero out the address windows */ 2316 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, 0); 2317 2318 /* power down the socket to reset it, clear the card reset pin */ 2319 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2320 2321 /* power off; assert output enable bit */ 2322 power = PCIC_PWRCTL_OE; 2323 Pcic_write(sc, PCIC_PWRCTL, power); 2324 2325 /* power up the socket */ 2326 if (pccbb_power(sc, voltage) == 0) 2327 return; 2328 2329 /* 2330 * Table 4-18 and figure 4-6 of the PC Card specifiction say: 2331 * Vcc Rising Time (Tpr) = 100ms (handled in pccbb_power() above) 2332 * RESET Width (Th (Hi-z RESET)) = 1ms 2333 * RESET Width (Tw (RESET)) = 10us 2334 * 2335 * some machines require some more time to be settled 2336 * for example old toshiba topic bridges! 2337 * (100ms is added here). 2338 */ 2339 pccbb_pcmcia_delay(sc, 200 + 1, "pccen1"); 2340 2341 /* negate RESET */ 2342 intr |= PCIC_INTR_RESET; 2343 Pcic_write(sc, PCIC_INTR, intr); 2344 2345 /* 2346 * RESET Setup Time (Tsu (RESET)) = 20ms 2347 */ 2348 pccbb_pcmcia_delay(sc, 20, "pccen2"); 2349 2350 #ifdef DIAGNOSTIC 2351 reg = Pcic_read(sc, PCIC_IF_STATUS); 2352 if ((reg & PCIC_IF_STATUS_POWERACTIVE) == 0) 2353 printf("pccbb_pcmcia_socket_enable: no power, status=%x\n", reg); 2354 #endif 2355 2356 /* wait for the chip to finish initializing */ 2357 if (pccbb_pcmcia_wait_ready(sc)) { 2358 #ifdef DIAGNOSTIC 2359 printf("pccbb_pcmcia_socket_enable: never became ready\n"); 2360 #endif 2361 /* XXX return a failure status?? */ 2362 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2363 Pcic_write(sc, PCIC_PWRCTL, 0); 2364 return; 2365 } 2366 2367 /* reinstall all the memory and io mappings */ 2368 for (win = 0; win < PCIC_MEM_WINS; ++win) 2369 if (ph->memalloc & (1 << win)) 2370 pccbb_pcmcia_do_mem_map(sc, win); 2371 for (win = 0; win < PCIC_IO_WINS; ++win) 2372 if (ph->ioalloc & (1 << win)) 2373 pccbb_pcmcia_do_io_map(sc, win); 2374 } 2375 2376 /* 2377 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2378 * 2379 * This function disables the card. All information is stored in 2380 * the first argument, pcmcia_chipset_handle_t. 2381 */ 2382 STATIC void 2383 pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t pch) 2384 { 2385 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2386 u_int8_t intr; 2387 2388 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2389 2390 /* disable interrupts; assert RESET */ 2391 intr = Pcic_read(sc, PCIC_INTR); 2392 intr &= PCIC_INTR_ENABLE; 2393 Pcic_write(sc, PCIC_INTR, intr); 2394 2395 /* zero out the address windows */ 2396 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, 0); 2397 2398 /* power down the socket to reset it, clear the card reset pin */ 2399 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2400 2401 /* disable socket: negate output enable bit and power off */ 2402 Pcic_write(sc, PCIC_PWRCTL, 0); 2403 2404 /* 2405 * Vcc Falling Time (Tpf) = 300ms 2406 */ 2407 pccbb_pcmcia_delay(sc, 300, "pccwr1"); 2408 } 2409 2410 STATIC void 2411 pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t pch, int type) 2412 { 2413 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2414 u_int8_t intr; 2415 2416 /* set the card type */ 2417 2418 intr = Pcic_read(sc, PCIC_INTR); 2419 intr &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_CARDTYPE_MASK); 2420 if (type == PCMCIA_IFTYPE_IO) 2421 intr |= PCIC_INTR_CARDTYPE_IO; 2422 else 2423 intr |= PCIC_INTR_CARDTYPE_MEM; 2424 Pcic_write(sc, PCIC_INTR, intr); 2425 2426 DPRINTF(("%s: pccbb_pcmcia_socket_settype type %s %02x\n", 2427 device_xname(sc->sc_dev), 2428 ((type == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2429 } 2430 2431 /* 2432 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2433 * 2434 * This function detects whether a card is in the slot or not. 2435 * If a card is inserted, return 1. Otherwise, return 0. 2436 */ 2437 STATIC int 2438 pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch) 2439 { 2440 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2441 2442 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2443 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2444 } 2445 2446 #if 0 2447 STATIC int 2448 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2449 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2450 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2451 #endif 2452 /* 2453 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2454 * bus_size_t size, 2455 * struct pcmcia_mem_handle *pcmhp) 2456 * 2457 * This function only allocates memory region for pccard. This 2458 * function never maps the allocated region to pccard memory area. 2459 * 2460 * XXX: Why the argument of start address is not in? 2461 */ 2462 STATIC int 2463 pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 2464 struct pcmcia_mem_handle *pcmhp) 2465 { 2466 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2467 bus_space_handle_t memh; 2468 bus_addr_t addr; 2469 bus_size_t sizepg; 2470 #if rbus 2471 rbus_tag_t rb; 2472 #endif 2473 2474 /* Check that the card is still there. */ 2475 if ((Pcic_read(sc, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2476 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2477 return 1; 2478 2479 /* out of sc->memh, allocate as many pages as necessary */ 2480 2481 /* convert size to PCIC pages */ 2482 /* 2483 * This is not enough; when the requested region is on the page 2484 * boundaries, this may calculate wrong result. 2485 */ 2486 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2487 #if 0 2488 if (sizepg > PCIC_MAX_MEM_PAGES) { 2489 return 1; 2490 } 2491 #endif 2492 2493 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2494 return 1; 2495 } 2496 2497 addr = 0; /* XXX gcc -Wuninitialized */ 2498 2499 #if rbus 2500 rb = sc->sc_rbus_memt; 2501 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2502 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2503 &addr, &memh)) { 2504 return 1; 2505 } 2506 #else 2507 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2508 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2509 0, /* boundary */ 2510 0, /* flags */ 2511 &addr, &memh)) { 2512 return 1; 2513 } 2514 #endif 2515 2516 DPRINTF(("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, " 2517 "realsize 0x%lx\n", (unsigned long)addr, (unsigned long)size, 2518 (unsigned long)sizepg * PCIC_MEM_PAGESIZE)); 2519 2520 pcmhp->memt = sc->sc_memt; 2521 pcmhp->memh = memh; 2522 pcmhp->addr = addr; 2523 pcmhp->size = size; 2524 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2525 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2526 pcmhp->mhandle = 0; 2527 /* No offset??? Funny. */ 2528 2529 return 0; 2530 } 2531 2532 /* 2533 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2534 * struct pcmcia_mem_handle *pcmhp) 2535 * 2536 * This function release the memory space allocated by the function 2537 * pccbb_pcmcia_mem_alloc(). 2538 */ 2539 STATIC void 2540 pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2541 struct pcmcia_mem_handle *pcmhp) 2542 { 2543 #if rbus 2544 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2545 2546 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2547 #else 2548 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2549 #endif 2550 } 2551 2552 /* 2553 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2554 * 2555 * This function release the memory space allocated by the function 2556 * pccbb_pcmcia_mem_alloc(). 2557 */ 2558 STATIC void 2559 pccbb_pcmcia_do_mem_map(struct pccbb_softc *sc, int win) 2560 { 2561 int regbase_win; 2562 bus_addr_t phys_addr; 2563 bus_addr_t phys_end; 2564 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2565 2566 #define PCIC_SMM_START_LOW 0 2567 #define PCIC_SMM_START_HIGH 1 2568 #define PCIC_SMM_STOP_LOW 2 2569 #define PCIC_SMM_STOP_HIGH 3 2570 #define PCIC_CMA_LOW 4 2571 #define PCIC_CMA_HIGH 5 2572 2573 u_int8_t start_low, start_high = 0; 2574 u_int8_t stop_low, stop_high; 2575 u_int8_t off_low, off_high; 2576 u_int8_t mem_window; 2577 int reg; 2578 2579 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2580 int mem8 = 2581 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2582 || (kind == PCMCIA_MEM_ATTR); 2583 2584 regbase_win = 0x10 + win * 0x08; 2585 2586 phys_addr = ph->mem[win].addr; 2587 phys_end = phys_addr + ph->mem[win].size; 2588 2589 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2590 (unsigned long)phys_addr, (unsigned long)phys_end, 2591 (unsigned long)ph->mem[win].offset)); 2592 2593 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2594 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2595 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2596 2597 /* bit 19:12 */ 2598 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2599 /* bit 23:20 and bit 7 on */ 2600 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2601 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2602 /* bit 31:24, for 32-bit address */ 2603 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2604 2605 Pcic_write(sc, regbase_win + PCIC_SMM_START_LOW, start_low); 2606 Pcic_write(sc, regbase_win + PCIC_SMM_START_HIGH, start_high); 2607 2608 if (sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2609 Pcic_write(sc, 0x40 + win, mem_window); 2610 } 2611 2612 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2613 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2614 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2615 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2616 2617 Pcic_write(sc, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2618 Pcic_write(sc, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2619 2620 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2621 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2622 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2623 | ((kind == PCMCIA_MEM_ATTR) ? 2624 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2625 2626 Pcic_write(sc, regbase_win + PCIC_CMA_LOW, off_low); 2627 Pcic_write(sc, regbase_win + PCIC_CMA_HIGH, off_high); 2628 2629 reg = Pcic_read(sc, PCIC_ADDRWIN_ENABLE); 2630 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2631 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, reg); 2632 2633 #if defined(CBB_DEBUG) 2634 { 2635 int r1, r2, r3, r4, r5, r6, r7 = 0; 2636 2637 r1 = Pcic_read(sc, regbase_win + PCIC_SMM_START_LOW); 2638 r2 = Pcic_read(sc, regbase_win + PCIC_SMM_START_HIGH); 2639 r3 = Pcic_read(sc, regbase_win + PCIC_SMM_STOP_LOW); 2640 r4 = Pcic_read(sc, regbase_win + PCIC_SMM_STOP_HIGH); 2641 r5 = Pcic_read(sc, regbase_win + PCIC_CMA_LOW); 2642 r6 = Pcic_read(sc, regbase_win + PCIC_CMA_HIGH); 2643 if (sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2644 r7 = Pcic_read(sc, 0x40 + win); 2645 } 2646 2647 printf("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2648 "%02x%02x", win, r1, r2, r3, r4, r5, r6); 2649 if (sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2650 printf(" %02x", r7); 2651 } 2652 printf("\n"); 2653 } 2654 #endif 2655 } 2656 2657 /* 2658 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2659 * bus_addr_t card_addr, bus_size_t size, 2660 * struct pcmcia_mem_handle *pcmhp, 2661 * bus_addr_t *offsetp, int *windowp) 2662 * 2663 * This function maps memory space allocated by the function 2664 * pccbb_pcmcia_mem_alloc(). 2665 */ 2666 STATIC int 2667 pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2668 bus_addr_t card_addr, bus_size_t size, struct pcmcia_mem_handle *pcmhp, 2669 bus_size_t *offsetp, int *windowp) 2670 { 2671 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2672 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2673 bus_addr_t busaddr; 2674 long card_offset; 2675 int win; 2676 2677 /* Check that the card is still there. */ 2678 if ((Pcic_read(sc, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2679 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2680 return 1; 2681 2682 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2683 if ((ph->memalloc & (1 << win)) == 0) { 2684 ph->memalloc |= (1 << win); 2685 break; 2686 } 2687 } 2688 2689 if (win == PCIC_MEM_WINS) { 2690 return 1; 2691 } 2692 2693 *windowp = win; 2694 2695 /* XXX this is pretty gross */ 2696 2697 if (!bus_space_is_equal(sc->sc_memt, pcmhp->memt)) { 2698 panic("pccbb_pcmcia_mem_map memt is bogus"); 2699 } 2700 2701 busaddr = pcmhp->addr; 2702 2703 /* 2704 * compute the address offset to the pcmcia address space for the 2705 * pcic. this is intentionally signed. The masks and shifts below 2706 * will cause TRT to happen in the pcic registers. Deal with making 2707 * sure the address is aligned, and return the alignment offset. 2708 */ 2709 2710 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2711 card_addr -= *offsetp; 2712 2713 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2714 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2715 (u_long) card_addr)); 2716 2717 /* 2718 * include the offset in the size, and decrement size by one, since 2719 * the hw wants start/stop 2720 */ 2721 size += *offsetp - 1; 2722 2723 card_offset = (((long)card_addr) - ((long)busaddr)); 2724 2725 ph->mem[win].addr = busaddr; 2726 ph->mem[win].size = size; 2727 ph->mem[win].offset = card_offset; 2728 ph->mem[win].kind = kind; 2729 2730 pccbb_pcmcia_do_mem_map(sc, win); 2731 2732 return 0; 2733 } 2734 2735 /* 2736 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2737 * int window) 2738 * 2739 * This function unmaps memory space which mapped by the function 2740 * pccbb_pcmcia_mem_map(). 2741 */ 2742 STATIC void 2743 pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, int window) 2744 { 2745 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2746 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2747 int reg; 2748 2749 if (window >= PCIC_MEM_WINS) { 2750 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2751 } 2752 2753 reg = Pcic_read(sc, PCIC_ADDRWIN_ENABLE); 2754 reg &= ~(1 << window); 2755 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, reg); 2756 2757 ph->memalloc &= ~(1 << window); 2758 } 2759 2760 /* 2761 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2762 * struct pcmcia_function *pf, 2763 * int ipl, 2764 * int (*func)(void *), 2765 * void *arg); 2766 * 2767 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2768 */ 2769 STATIC void * 2770 pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2771 struct pcmcia_function *pf, int ipl, int (*func)(void *), void *arg) 2772 { 2773 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2774 2775 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2776 /* what should I do? */ 2777 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2778 DPRINTF(("%s does not provide edge nor pulse " 2779 "interrupt\n", device_xname(sc->sc_dev))); 2780 return NULL; 2781 } 2782 /* 2783 * XXX Noooooo! The interrupt flag must set properly!! 2784 * dumb pcmcia driver!! 2785 */ 2786 } 2787 2788 return pccbb_intr_establish(sc, ipl, func, arg); 2789 } 2790 2791 /* 2792 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2793 * void *ih) 2794 * 2795 * This function disables PC-Card interrupt. 2796 */ 2797 STATIC void 2798 pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 2799 { 2800 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2801 2802 pccbb_intr_disestablish(sc, ih); 2803 } 2804 2805 #if rbus 2806 /* 2807 * static int 2808 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2809 * bus_addr_t addr, bus_size_t size, 2810 * bus_addr_t mask, bus_size_t align, 2811 * int flags, bus_addr_t *addrp; 2812 * bus_space_handle_t *bshp) 2813 * 2814 * This function allocates a portion of memory or io space for 2815 * clients. This function is called from CardBus card drivers. 2816 */ 2817 static int 2818 pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2819 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 2820 int flags, bus_addr_t *addrp, bus_space_handle_t *bshp) 2821 { 2822 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2823 2824 DPRINTF(("pccbb_rbus_cb_space_alloc: addr 0x%lx, size 0x%lx, " 2825 "mask 0x%lx, align 0x%lx\n", (unsigned long)addr, 2826 (unsigned long)size, (unsigned long)mask, (unsigned long)align)); 2827 2828 if (align == 0) { 2829 align = size; 2830 } 2831 2832 if (bus_space_is_equal(rb->rb_bt, sc->sc_memt)) { 2833 if (align < 16) { 2834 return 1; 2835 } 2836 /* 2837 * XXX: align more than 0x1000 to avoid overwrapping 2838 * memory windows for two or more devices. 0x1000 2839 * means memory window's granularity. 2840 * 2841 * Two or more devices should be able to share same 2842 * memory window region. However, overrapping memory 2843 * window is not good because some devices, such as 2844 * 3Com 3C575[BC], have a broken address decoder and 2845 * intrude other's memory region. 2846 */ 2847 if (align < 0x1000) { 2848 align = 0x1000; 2849 } 2850 } else if (bus_space_is_equal(rb->rb_bt, sc->sc_iot)) { 2851 if (align < 4) { 2852 return 1; 2853 } 2854 /* XXX: hack for avoiding ISA image */ 2855 if (mask < 0x0100) { 2856 mask = 0x3ff; 2857 addr = 0x300; 2858 } 2859 2860 } else { 2861 DPRINTF(("pccbb_rbus_cb_space_alloc: Bus space tag 0x%lx is " 2862 "NOT used. io: 0x%lx, mem: 0x%lx\n", 2863 (unsigned long)rb->rb_bt, (unsigned long)sc->sc_iot, 2864 (unsigned long)sc->sc_memt)); 2865 return 1; 2866 /* XXX: panic here? */ 2867 } 2868 2869 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 2870 aprint_normal_dev(sc->sc_dev, "<rbus> no bus space\n"); 2871 return 1; 2872 } 2873 2874 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 2875 2876 return 0; 2877 } 2878 2879 /* 2880 * static int 2881 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 2882 * bus_space_handle_t *bshp, bus_size_t size); 2883 * 2884 * This function is called from CardBus card drivers. 2885 */ 2886 static int 2887 pccbb_rbus_cb_space_free(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2888 bus_space_handle_t bsh, bus_size_t size) 2889 { 2890 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2891 bus_space_tag_t bt = rb->rb_bt; 2892 2893 pccbb_close_win(sc, bt, bsh, size); 2894 2895 if (bus_space_is_equal(bt, sc->sc_memt)) { 2896 } else if (bus_space_is_equal(bt, sc->sc_iot)) { 2897 } else { 2898 return 1; 2899 /* XXX: panic here? */ 2900 } 2901 2902 return rbus_space_free(rb, bsh, size, NULL); 2903 } 2904 #endif /* rbus */ 2905 2906 #if rbus 2907 2908 static int 2909 pccbb_open_win(struct pccbb_softc *sc, bus_space_tag_t bst, bus_addr_t addr, 2910 bus_size_t size, bus_space_handle_t bsh, int flags) 2911 { 2912 struct pccbb_win_chain_head *head; 2913 bus_addr_t align; 2914 2915 head = &sc->sc_iowindow; 2916 align = 0x04; 2917 if (bus_space_is_equal(sc->sc_memt, bst)) { 2918 head = &sc->sc_memwindow; 2919 align = 0x1000; 2920 DPRINTF(("using memory window, 0x%lx 0x%lx 0x%lx\n\n", 2921 (unsigned long)sc->sc_iot, (unsigned long)sc->sc_memt, 2922 (unsigned long)bst)); 2923 } 2924 2925 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 2926 aprint_error_dev(sc->sc_dev, 2927 "pccbb_open_win: %s winlist insert failed\n", 2928 (head == &sc->sc_memwindow) ? "mem" : "io"); 2929 } 2930 pccbb_winset(align, sc, bst); 2931 2932 return 0; 2933 } 2934 2935 static int 2936 pccbb_close_win(struct pccbb_softc *sc, bus_space_tag_t bst, 2937 bus_space_handle_t bsh, bus_size_t size) 2938 { 2939 struct pccbb_win_chain_head *head; 2940 bus_addr_t align; 2941 2942 head = &sc->sc_iowindow; 2943 align = 0x04; 2944 if (bus_space_is_equal(sc->sc_memt, bst)) { 2945 head = &sc->sc_memwindow; 2946 align = 0x1000; 2947 } 2948 2949 if (pccbb_winlist_delete(head, bsh, size)) { 2950 aprint_error_dev(sc->sc_dev, 2951 "pccbb_close_win: %s winlist delete failed\n", 2952 (head == &sc->sc_memwindow) ? "mem" : "io"); 2953 } 2954 pccbb_winset(align, sc, bst); 2955 2956 return 0; 2957 } 2958 2959 static int 2960 pccbb_winlist_insert(struct pccbb_win_chain_head *head, bus_addr_t start, 2961 bus_size_t size, bus_space_handle_t bsh, int flags) 2962 { 2963 struct pccbb_win_chain *chainp, *elem; 2964 2965 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 2966 M_NOWAIT)) == NULL) 2967 return (1); /* fail */ 2968 2969 elem->wc_start = start; 2970 elem->wc_end = start + (size - 1); 2971 elem->wc_handle = bsh; 2972 elem->wc_flags = flags; 2973 2974 TAILQ_FOREACH(chainp, head, wc_list) { 2975 if (chainp->wc_end >= start) 2976 break; 2977 } 2978 if (chainp != NULL) 2979 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 2980 else 2981 TAILQ_INSERT_TAIL(head, elem, wc_list); 2982 return (0); 2983 } 2984 2985 static int 2986 pccbb_winlist_delete(struct pccbb_win_chain_head *head, bus_space_handle_t bsh, 2987 bus_size_t size) 2988 { 2989 struct pccbb_win_chain *chainp; 2990 2991 TAILQ_FOREACH(chainp, head, wc_list) { 2992 if (memcmp(&chainp->wc_handle, &bsh, sizeof(bsh)) == 0) 2993 break; 2994 } 2995 if (chainp == NULL) 2996 return 1; /* fail: no candidate to remove */ 2997 2998 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 2999 printf("pccbb_winlist_delete: window 0x%lx size " 3000 "inconsistent: 0x%lx, 0x%lx\n", 3001 (unsigned long)chainp->wc_start, 3002 (unsigned long)(chainp->wc_end - chainp->wc_start), 3003 (unsigned long)(size - 1)); 3004 return 1; 3005 } 3006 3007 TAILQ_REMOVE(head, chainp, wc_list); 3008 free(chainp, M_DEVBUF); 3009 3010 return 0; 3011 } 3012 3013 static void 3014 pccbb_winset(bus_addr_t align, struct pccbb_softc *sc, bus_space_tag_t bst) 3015 { 3016 pci_chipset_tag_t pc; 3017 pcitag_t tag; 3018 bus_addr_t mask = ~(align - 1); 3019 struct { 3020 pcireg_t win_start; 3021 pcireg_t win_limit; 3022 int win_flags; 3023 } win[2]; 3024 struct pccbb_win_chain *chainp; 3025 int offs; 3026 3027 win[0].win_start = win[1].win_start = 0xffffffff; 3028 win[0].win_limit = win[1].win_limit = 0; 3029 win[0].win_flags = win[1].win_flags = 0; 3030 3031 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3032 offs = PCI_CB_IOBASE0; 3033 if (bus_space_is_equal(sc->sc_memt, bst)) { 3034 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3035 offs = PCI_CB_MEMBASE0; 3036 } 3037 3038 if (chainp != NULL) { 3039 win[0].win_start = chainp->wc_start & mask; 3040 win[0].win_limit = chainp->wc_end & mask; 3041 win[0].win_flags = chainp->wc_flags; 3042 chainp = TAILQ_NEXT(chainp, wc_list); 3043 } 3044 3045 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3046 if (win[1].win_start == 0xffffffff) { 3047 /* window 1 is not used */ 3048 if ((win[0].win_flags == chainp->wc_flags) && 3049 (win[0].win_limit + align >= 3050 (chainp->wc_start & mask))) { 3051 /* concatenate */ 3052 win[0].win_limit = chainp->wc_end & mask; 3053 } else { 3054 /* make new window */ 3055 win[1].win_start = chainp->wc_start & mask; 3056 win[1].win_limit = chainp->wc_end & mask; 3057 win[1].win_flags = chainp->wc_flags; 3058 } 3059 continue; 3060 } 3061 3062 /* Both windows are engaged. */ 3063 if (win[0].win_flags == win[1].win_flags) { 3064 /* same flags */ 3065 if (win[0].win_flags == chainp->wc_flags) { 3066 if (win[1].win_start - (win[0].win_limit + 3067 align) < 3068 (chainp->wc_start & mask) - 3069 ((chainp->wc_end & mask) + align)) { 3070 /* 3071 * merge window 0 and 1, and set win1 3072 * to chainp 3073 */ 3074 win[0].win_limit = win[1].win_limit; 3075 win[1].win_start = 3076 chainp->wc_start & mask; 3077 win[1].win_limit = 3078 chainp->wc_end & mask; 3079 } else { 3080 win[1].win_limit = 3081 chainp->wc_end & mask; 3082 } 3083 } else { 3084 /* different flags */ 3085 3086 /* concatenate win0 and win1 */ 3087 win[0].win_limit = win[1].win_limit; 3088 /* allocate win[1] to new space */ 3089 win[1].win_start = chainp->wc_start & mask; 3090 win[1].win_limit = chainp->wc_end & mask; 3091 win[1].win_flags = chainp->wc_flags; 3092 } 3093 } else { 3094 /* the flags of win[0] and win[1] is different */ 3095 if (win[0].win_flags == chainp->wc_flags) { 3096 win[0].win_limit = chainp->wc_end & mask; 3097 /* 3098 * XXX this creates overlapping windows, so 3099 * what should the poor bridge do if one is 3100 * cachable, and the other is not? 3101 */ 3102 aprint_error_dev(sc->sc_dev, 3103 "overlapping windows\n"); 3104 } else { 3105 win[1].win_limit = chainp->wc_end & mask; 3106 } 3107 } 3108 } 3109 3110 pc = sc->sc_pc; 3111 tag = sc->sc_tag; 3112 pci_conf_write(pc, tag, offs, win[0].win_start); 3113 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3114 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3115 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3116 DPRINTF(("--pccbb_winset: win0 [0x%lx, 0x%lx), win1 [0x%lx, 0x%lx)\n", 3117 (unsigned long)pci_conf_read(pc, tag, offs), 3118 (unsigned long)pci_conf_read(pc, tag, offs + 4) + align, 3119 (unsigned long)pci_conf_read(pc, tag, offs + 8), 3120 (unsigned long)pci_conf_read(pc, tag, offs + 12) + align)); 3121 3122 if (bus_space_is_equal(bst, sc->sc_memt)) { 3123 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BRIDGE_CONTROL_REG); 3124 3125 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 3126 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 3127 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3128 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 3129 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3130 pci_conf_write(pc, tag, PCI_BRIDGE_CONTROL_REG, bcr); 3131 } 3132 } 3133 3134 #endif /* rbus */ 3135 3136 static bool 3137 pccbb_suspend(device_t dv, const pmf_qual_t *qual) 3138 { 3139 struct pccbb_softc *sc = device_private(dv); 3140 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3141 bus_space_handle_t base_memh = sc->sc_base_memh; 3142 pcireg_t reg; 3143 3144 if (sc->sc_pil_intr_enable) 3145 (void)pccbbintr_function(sc); 3146 sc->sc_pil_intr_enable = false; 3147 3148 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3149 /* Disable interrupts. */ 3150 reg &= ~(CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER); 3151 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3152 /* XXX joerg Disable power to the socket? */ 3153 3154 /* XXX flush PCI write */ 3155 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3156 3157 /* reset interrupt */ 3158 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, 3159 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT)); 3160 /* XXX flush PCI write */ 3161 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3162 3163 if (sc->sc_ih != NULL) { 3164 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 3165 sc->sc_ih = NULL; 3166 } 3167 3168 return true; 3169 } 3170 3171 static bool 3172 pccbb_resume(device_t dv, const pmf_qual_t *qual) 3173 { 3174 struct pccbb_softc *sc = device_private(dv); 3175 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3176 bus_space_handle_t base_memh = sc->sc_base_memh; 3177 pcireg_t reg; 3178 3179 pccbb_chipinit(sc); 3180 pccbb_intrinit(sc); 3181 /* setup memory and io space window for CB */ 3182 pccbb_winset(0x1000, sc, sc->sc_memt); 3183 pccbb_winset(0x04, sc, sc->sc_iot); 3184 3185 /* CSC Interrupt: Card detect interrupt on */ 3186 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3187 /* Card detect intr is turned on. */ 3188 reg |= CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; 3189 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3190 /* reset interrupt */ 3191 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3192 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3193 3194 /* 3195 * check for card insertion or removal during suspend period. 3196 * XXX: the code can't cope with card swap (remove then 3197 * insert). how can we detect such situation? 3198 */ 3199 (void)pccbbintr(sc); 3200 3201 sc->sc_pil_intr_enable = true; 3202 3203 return true; 3204 } 3205
Indexes created Wed Oct 15 03:09:54 GMT 2025