pccbb.c revision 1.209
1 /* $NetBSD: pccbb.c,v 1.209 2016/02/17 20:00:15 christos Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: pccbb.c,v 1.209 2016/02/17 20:00:15 christos Exp $"); 30 31 /* 32 #define CBB_DEBUG 33 #define SHOW_REGS 34 */ 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/kernel.h> 39 #include <sys/errno.h> 40 #include <sys/ioctl.h> 41 #include <sys/reboot.h> /* for bootverbose */ 42 #include <sys/syslog.h> 43 #include <sys/device.h> 44 #include <sys/malloc.h> 45 #include <sys/proc.h> 46 47 #include <sys/intr.h> 48 #include <sys/bus.h> 49 50 #include <dev/pci/pcivar.h> 51 #include <dev/pci/pcireg.h> 52 #include <dev/pci/pcidevs.h> 53 54 #include <dev/pci/pccbbreg.h> 55 56 #include <dev/cardbus/cardslotvar.h> 57 58 #include <dev/cardbus/cardbusvar.h> 59 60 #include <dev/pcmcia/pcmciareg.h> 61 #include <dev/pcmcia/pcmciavar.h> 62 63 #include <dev/ic/i82365reg.h> 64 #include <dev/pci/pccbbvar.h> 65 66 #ifndef __NetBSD_Version__ 67 struct cfdriver cbb_cd = { 68 NULL, "cbb", DV_DULL 69 }; 70 #endif 71 72 #ifdef CBB_DEBUG 73 #define DPRINTF(x) printf x 74 #define STATIC 75 #else 76 #define DPRINTF(x) 77 #define STATIC static 78 #endif 79 80 int pccbb_burstup = 1; 81 82 /* 83 * delay_ms() is wait in milliseconds. It should be used instead 84 * of delay() if you want to wait more than 1 ms. 85 */ 86 static inline void 87 delay_ms(int millis, struct pccbb_softc *sc) 88 { 89 if (cold) 90 delay(millis * 1000); 91 else 92 kpause("pccbb", false, mstohz(millis), NULL); 93 } 94 95 int pcicbbmatch(device_t, cfdata_t, void *); 96 void pccbbattach(device_t, device_t, void *); 97 void pccbbchilddet(device_t, device_t); 98 int pccbbdetach(device_t, int); 99 int pccbbintr(void *); 100 static void pci113x_insert(void *); 101 static int pccbbintr_function(struct pccbb_softc *); 102 103 static int pccbb_detect_card(struct pccbb_softc *); 104 105 static void pccbb_pcmcia_write(struct pccbb_softc *, int, u_int8_t); 106 static u_int8_t pccbb_pcmcia_read(struct pccbb_softc *, int); 107 #define Pcic_read(sc, reg) pccbb_pcmcia_read((sc), (reg)) 108 #define Pcic_write(sc, reg, val) pccbb_pcmcia_write((sc), (reg), (val)) 109 110 STATIC int cb_reset(struct pccbb_softc *); 111 STATIC int cb_detect_voltage(struct pccbb_softc *); 112 STATIC int cbbprint(void *, const char *); 113 114 static int cb_chipset(u_int32_t, int *); 115 STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *, 116 struct pcmciabus_attach_args *); 117 118 STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int); 119 STATIC int pccbb_power(struct pccbb_softc *sc, int); 120 STATIC int pccbb_power_ct(cardbus_chipset_tag_t, int); 121 STATIC int pccbb_cardenable(struct pccbb_softc * sc, int function); 122 static void *pccbb_intr_establish(struct pccbb_softc *, 123 int level, int (*ih) (void *), void *sc); 124 static void pccbb_intr_disestablish(struct pccbb_softc *, void *ih); 125 126 static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t, 127 int level, int (*ih) (void *), void *sc); 128 static void pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih); 129 130 static pcitag_t pccbb_make_tag(cardbus_chipset_tag_t, int, int); 131 static pcireg_t pccbb_conf_read(cardbus_chipset_tag_t, pcitag_t, int); 132 static void pccbb_conf_write(cardbus_chipset_tag_t, pcitag_t, int, 133 pcireg_t); 134 static void pccbb_chipinit(struct pccbb_softc *); 135 static void pccbb_intrinit(struct pccbb_softc *); 136 137 STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 138 struct pcmcia_mem_handle *); 139 STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t, 140 struct pcmcia_mem_handle *); 141 STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 142 bus_size_t, struct pcmcia_mem_handle *, bus_size_t *, int *); 143 STATIC void pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t, int); 144 STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 145 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 146 STATIC void pccbb_pcmcia_io_free(pcmcia_chipset_handle_t, 147 struct pcmcia_io_handle *); 148 STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 149 bus_size_t, struct pcmcia_io_handle *, int *); 150 STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t, int); 151 STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t, 152 struct pcmcia_function *, int, int (*)(void *), void *); 153 STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t, void *); 154 STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t); 155 STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t); 156 STATIC void pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t, int); 157 STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch); 158 159 static int pccbb_pcmcia_wait_ready(struct pccbb_softc *); 160 static void pccbb_pcmcia_delay(struct pccbb_softc *, int, const char *); 161 162 static void pccbb_pcmcia_do_io_map(struct pccbb_softc *, int); 163 static void pccbb_pcmcia_do_mem_map(struct pccbb_softc *, int); 164 165 /* bus-space allocation and deallocation functions */ 166 167 static int pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t, rbus_tag_t, 168 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 169 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp); 170 static int pccbb_rbus_cb_space_free(cardbus_chipset_tag_t, rbus_tag_t, 171 bus_space_handle_t, bus_size_t); 172 173 174 175 static int pccbb_open_win(struct pccbb_softc *, bus_space_tag_t, 176 bus_addr_t, bus_size_t, bus_space_handle_t, int flags); 177 static int pccbb_close_win(struct pccbb_softc *, bus_space_tag_t, 178 bus_space_handle_t, bus_size_t); 179 static int pccbb_winlist_insert(struct pccbb_win_chain_head *, bus_addr_t, 180 bus_size_t, bus_space_handle_t, int); 181 static int pccbb_winlist_delete(struct pccbb_win_chain_head *, 182 bus_space_handle_t, bus_size_t); 183 static void pccbb_winset(bus_addr_t align, struct pccbb_softc *, 184 bus_space_tag_t); 185 void pccbb_winlist_show(struct pccbb_win_chain *); 186 187 188 /* for config_defer */ 189 static void pccbb_pci_callback(device_t); 190 191 static bool pccbb_suspend(device_t, const pmf_qual_t *); 192 static bool pccbb_resume(device_t, const pmf_qual_t *); 193 194 #if defined SHOW_REGS 195 static void cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, 196 bus_space_tag_t memt, bus_space_handle_t memh); 197 #endif 198 199 CFATTACH_DECL3_NEW(cbb_pci, sizeof(struct pccbb_softc), 200 pcicbbmatch, pccbbattach, pccbbdetach, NULL, NULL, pccbbchilddet, 201 DVF_DETACH_SHUTDOWN); 202 203 static const struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 204 pccbb_pcmcia_mem_alloc, 205 pccbb_pcmcia_mem_free, 206 pccbb_pcmcia_mem_map, 207 pccbb_pcmcia_mem_unmap, 208 pccbb_pcmcia_io_alloc, 209 pccbb_pcmcia_io_free, 210 pccbb_pcmcia_io_map, 211 pccbb_pcmcia_io_unmap, 212 pccbb_pcmcia_intr_establish, 213 pccbb_pcmcia_intr_disestablish, 214 pccbb_pcmcia_socket_enable, 215 pccbb_pcmcia_socket_disable, 216 pccbb_pcmcia_socket_settype, 217 pccbb_pcmcia_card_detect 218 }; 219 220 static const struct cardbus_functions pccbb_funcs = { 221 pccbb_rbus_cb_space_alloc, 222 pccbb_rbus_cb_space_free, 223 pccbb_cb_intr_establish, 224 pccbb_cb_intr_disestablish, 225 pccbb_ctrl, 226 pccbb_power_ct, 227 pccbb_make_tag, 228 pccbb_conf_read, 229 pccbb_conf_write, 230 }; 231 232 int 233 pcicbbmatch(device_t parent, cfdata_t match, void *aux) 234 { 235 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 236 237 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 238 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 239 PCI_INTERFACE(pa->pa_class) == 0) { 240 return 1; 241 } 242 243 return 0; 244 } 245 246 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 247 | ((prod) << PCI_PRODUCT_SHIFT)) 248 249 const struct yenta_chipinfo { 250 pcireg_t yc_id; /* vendor tag | product tag */ 251 int yc_chiptype; 252 int yc_flags; 253 } yc_chipsets[] = { 254 /* Texas Instruments chips */ 255 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 256 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 257 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 258 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 259 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI125X, 260 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 261 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 262 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 263 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 264 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 265 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 266 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 267 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI125X, 268 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 269 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI125X, 270 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 271 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 272 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 273 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 274 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 275 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI1420, 276 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 277 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI125X, 278 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 279 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 280 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 281 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1510), CB_TI12XX, 282 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 283 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1520), CB_TI12XX, 284 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 285 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4410YENTA), CB_TI12XX, 286 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 287 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4520YENTA), CB_TI12XX, 288 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 289 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI7420YENTA), CB_TI12XX, 290 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 291 292 /* Ricoh chips */ 293 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 294 PCCBB_PCMCIA_MEM_32}, 295 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 296 PCCBB_PCMCIA_MEM_32}, 297 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 298 PCCBB_PCMCIA_MEM_32}, 299 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 300 PCCBB_PCMCIA_MEM_32}, 301 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 302 PCCBB_PCMCIA_MEM_32}, 303 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 304 PCCBB_PCMCIA_MEM_32}, 305 306 /* Toshiba products */ 307 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 308 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 309 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 310 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 311 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 312 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 313 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 314 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 315 316 /* Cirrus Logic products */ 317 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 318 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 319 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 320 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 321 322 /* O2 Micro products */ 323 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6729), 324 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 325 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6730), 326 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 327 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6832), 328 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 329 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6836), 330 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 331 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6872), 332 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 333 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6922), 334 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 335 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6933), 336 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 337 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6972), 338 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 339 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_7223), 340 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 341 342 /* sentinel, or Generic chip */ 343 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 344 }; 345 346 static int 347 cb_chipset(u_int32_t pci_id, int *flagp) 348 { 349 const struct yenta_chipinfo *yc; 350 351 /* Loop over except the last default entry. */ 352 for (yc = yc_chipsets; yc < yc_chipsets + 353 __arraycount(yc_chipsets) - 1; yc++) 354 if (pci_id == yc->yc_id) 355 break; 356 357 if (flagp != NULL) 358 *flagp = yc->yc_flags; 359 360 return (yc->yc_chiptype); 361 } 362 363 void 364 pccbbchilddet(device_t self, device_t child) 365 { 366 struct pccbb_softc *sc = device_private(self); 367 int s; 368 369 KASSERT(sc->sc_csc == device_private(child)); 370 371 s = splbio(); 372 if (sc->sc_csc == device_private(child)) 373 sc->sc_csc = NULL; 374 splx(s); 375 } 376 377 void 378 pccbbattach(device_t parent, device_t self, void *aux) 379 { 380 struct pccbb_softc *sc = device_private(self); 381 struct pci_attach_args *pa = aux; 382 pci_chipset_tag_t pc = pa->pa_pc; 383 pcireg_t reg, sock_base; 384 bus_addr_t sockbase; 385 int flags; 386 387 #ifdef __HAVE_PCCBB_ATTACH_HOOK 388 pccbb_attach_hook(parent, self, pa); 389 #endif 390 391 sc->sc_dev = self; 392 393 mutex_init(&sc->sc_pwr_mtx, MUTEX_DEFAULT, IPL_BIO); 394 cv_init(&sc->sc_pwr_cv, "pccpwr"); 395 396 callout_init(&sc->sc_insert_ch, 0); 397 callout_setfunc(&sc->sc_insert_ch, pci113x_insert, sc); 398 399 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 400 401 pci_aprint_devinfo(pa, NULL); 402 DPRINTF(("(chipflags %x)", flags)); 403 404 TAILQ_INIT(&sc->sc_memwindow); 405 TAILQ_INIT(&sc->sc_iowindow); 406 407 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 408 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 409 410 #if 0 411 printf("pa->pa_memt: %08x vs rbus_mem->rb_bt: %08x\n", 412 pa->pa_memt, sc->sc_rbus_memt->rb_bt); 413 #endif 414 415 sc->sc_flags &= ~CBB_MEMHMAPPED; 416 417 /* 418 * MAP socket registers and ExCA registers on memory-space 419 * When no valid address is set on socket base registers (on pci 420 * config space), get it not polite way. 421 */ 422 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 423 424 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 425 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 426 /* The address must be valid. */ 427 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 428 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, &sc->sc_base_size)) { 429 aprint_error_dev(self, 430 "can't map socket base address 0x%lx\n", 431 (unsigned long)sock_base); 432 /* 433 * I think it's funny: socket base registers must be 434 * mapped on memory space, but ... 435 */ 436 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 437 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 438 &sc->sc_base_size)) { 439 aprint_error_dev(self, 440 "can't map socket base address" 441 " 0x%lx: io mode\n", 442 (unsigned long)sockbase); 443 /* give up... allocate reg space via rbus. */ 444 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 445 } else 446 sc->sc_flags |= CBB_MEMHMAPPED; 447 } else { 448 DPRINTF(("%s: socket base address 0x%lx\n", 449 device_xname(self), 450 (unsigned long)sockbase)); 451 sc->sc_flags |= CBB_MEMHMAPPED; 452 } 453 } 454 455 sc->sc_mem_start = 0; /* XXX */ 456 sc->sc_mem_end = 0xffffffff; /* XXX */ 457 458 /* pccbb_machdep.c end */ 459 460 #if defined CBB_DEBUG 461 { 462 static const char *intrname[] = { "NON", "A", "B", "C", "D" }; 463 aprint_debug_dev(self, "intrpin %s, intrtag %d\n", 464 intrname[pa->pa_intrpin], pa->pa_intrline); 465 } 466 #endif 467 468 /* setup softc */ 469 sc->sc_pc = pc; 470 sc->sc_iot = pa->pa_iot; 471 sc->sc_memt = pa->pa_memt; 472 sc->sc_dmat = pa->pa_dmat; 473 sc->sc_tag = pa->pa_tag; 474 475 memcpy(&sc->sc_pa, pa, sizeof(*pa)); 476 477 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 478 479 /* Disable legacy register mapping. */ 480 switch (sc->sc_chipset) { 481 case CB_RX5C46X: /* fallthrough */ 482 #if 0 483 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 484 case CB_RX5C47X: 485 #endif 486 /* 487 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 488 * cannot be disabled by substituting 0 into PCI_LEGACY 489 * register. Ricoh CardBus bridges have special bits on Bridge 490 * control reg (addr 0x3e on PCI config space). 491 */ 492 reg = pci_conf_read(pc, pa->pa_tag, PCI_BRIDGE_CONTROL_REG); 493 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 494 pci_conf_write(pc, pa->pa_tag, PCI_BRIDGE_CONTROL_REG, reg); 495 break; 496 497 default: 498 /* XXX I don't know proper way to kill legacy I/O. */ 499 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 500 break; 501 } 502 503 if (!pmf_device_register(self, pccbb_suspend, pccbb_resume)) 504 aprint_error_dev(self, "couldn't establish power handler\n"); 505 506 config_defer(self, pccbb_pci_callback); 507 } 508 509 int 510 pccbbdetach(device_t self, int flags) 511 { 512 struct pccbb_softc *sc = device_private(self); 513 pci_chipset_tag_t pc = sc->sc_pa.pa_pc; 514 bus_space_tag_t bmt = sc->sc_base_memt; 515 bus_space_handle_t bmh = sc->sc_base_memh; 516 uint32_t sockmask; 517 int rc; 518 519 if ((rc = config_detach_children(self, flags)) != 0) 520 return rc; 521 522 if (!LIST_EMPTY(&sc->sc_pil)) { 523 panic("%s: interrupt handlers still registered", 524 device_xname(self)); 525 return EBUSY; 526 } 527 528 if (sc->sc_ih != NULL) { 529 pci_intr_disestablish(pc, sc->sc_ih); 530 sc->sc_ih = NULL; 531 } 532 533 /* CSC Interrupt: turn off card detect and power cycle interrupts */ 534 sockmask = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 535 sockmask &= ~(CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | 536 CB_SOCKET_MASK_POWER); 537 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, sockmask); 538 /* reset interrupt */ 539 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 540 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 541 542 switch (sc->sc_flags & (CBB_MEMHMAPPED|CBB_SPECMAPPED)) { 543 case CBB_MEMHMAPPED: 544 bus_space_unmap(bmt, bmh, sc->sc_base_size); 545 break; 546 case CBB_MEMHMAPPED|CBB_SPECMAPPED: 547 #if rbus 548 { 549 rbus_space_free(sc->sc_rbus_memt, bmh, 0x1000, 550 NULL); 551 } 552 #else 553 bus_space_free(bmt, bmh, 0x1000); 554 #endif 555 } 556 sc->sc_flags &= ~(CBB_MEMHMAPPED|CBB_SPECMAPPED); 557 558 if (!TAILQ_EMPTY(&sc->sc_iowindow)) 559 aprint_error_dev(self, "i/o windows not empty\n"); 560 if (!TAILQ_EMPTY(&sc->sc_memwindow)) 561 aprint_error_dev(self, "memory windows not empty\n"); 562 563 callout_halt(&sc->sc_insert_ch, NULL); 564 callout_destroy(&sc->sc_insert_ch); 565 566 mutex_destroy(&sc->sc_pwr_mtx); 567 cv_destroy(&sc->sc_pwr_cv); 568 569 return 0; 570 } 571 572 /* 573 * static void pccbb_pci_callback(device_t self) 574 * 575 * The actual attach routine: get memory space for YENTA register 576 * space, setup YENTA register and route interrupt. 577 * 578 * This function should be deferred because this device may obtain 579 * memory space dynamically. This function must avoid obtaining 580 * memory area which has already kept for another device. 581 */ 582 static void 583 pccbb_pci_callback(device_t self) 584 { 585 struct pccbb_softc *sc = device_private(self); 586 pci_chipset_tag_t pc = sc->sc_pc; 587 bus_addr_t sockbase; 588 struct cbslot_attach_args cba; 589 struct pcmciabus_attach_args paa; 590 struct cardslot_attach_args caa; 591 device_t csc; 592 593 if (!(sc->sc_flags & CBB_MEMHMAPPED)) { 594 /* The socket registers aren't mapped correctly. */ 595 #if rbus 596 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 597 (sc->sc_chipset == CB_RX5C47X 598 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 599 0, &sockbase, &sc->sc_base_memh)) { 600 return; 601 } 602 sc->sc_base_memt = sc->sc_memt; 603 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 604 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 605 device_xname(self), (unsigned long)sockbase, 606 (unsigned long)pci_conf_read(pc, sc->sc_tag, 607 PCI_SOCKBASE))); 608 #else 609 sc->sc_base_memt = sc->sc_memt; 610 #if !defined CBB_PCI_BASE 611 #define CBB_PCI_BASE 0x20000000 612 #endif 613 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 614 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 615 /* cannot allocate memory space */ 616 return; 617 } 618 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 619 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 620 device_xname(self), (unsigned long)sock_base, 621 (unsigned long)pci_conf_read(pc, 622 sc->sc_tag, PCI_SOCKBASE))); 623 #endif 624 sc->sc_flags |= CBB_MEMHMAPPED|CBB_SPECMAPPED; 625 } 626 627 /* clear data structure for child device interrupt handlers */ 628 LIST_INIT(&sc->sc_pil); 629 630 /* bus bridge initialization */ 631 pccbb_chipinit(sc); 632 633 sc->sc_pil_intr_enable = true; 634 635 { 636 u_int32_t sockstat; 637 638 sockstat = bus_space_read_4(sc->sc_base_memt, 639 sc->sc_base_memh, CB_SOCKET_STAT); 640 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 641 sc->sc_flags |= CBB_CARDEXIST; 642 } 643 } 644 645 /* 646 * attach cardbus 647 */ 648 { 649 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 650 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 651 652 /* initialize cbslot_attach */ 653 cba.cba_iot = sc->sc_iot; 654 cba.cba_memt = sc->sc_memt; 655 cba.cba_dmat = sc->sc_dmat; 656 cba.cba_bus = (busreg >> 8) & 0x0ff; 657 cba.cba_cc = (void *)sc; 658 cba.cba_cf = &pccbb_funcs; 659 660 #if rbus 661 cba.cba_rbus_iot = sc->sc_rbus_iot; 662 cba.cba_rbus_memt = sc->sc_rbus_memt; 663 #endif 664 665 cba.cba_cacheline = PCI_CACHELINE(bhlc); 666 cba.cba_max_lattimer = PCI_LATTIMER(bhlc); 667 668 aprint_verbose_dev(self, 669 "cacheline 0x%x lattimer 0x%x\n", 670 cba.cba_cacheline, 671 cba.cba_max_lattimer); 672 aprint_verbose_dev(self, "bhlc 0x%x\n", bhlc); 673 #if defined SHOW_REGS 674 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 675 sc->sc_base_memh); 676 #endif 677 } 678 679 pccbb_pcmcia_attach_setup(sc, &paa); 680 caa.caa_cb_attach = NULL; 681 if (cba.cba_bus == 0) 682 aprint_error_dev(self, 683 "secondary bus number uninitialized; try PCI_BUS_FIXUP\n"); 684 else 685 caa.caa_cb_attach = &cba; 686 caa.caa_16_attach = &paa; 687 688 pccbb_intrinit(sc); 689 690 if (NULL != (csc = config_found_ia(self, "pcmciaslot", &caa, 691 cbbprint))) { 692 DPRINTF(("%s: found cardslot\n", __func__)); 693 sc->sc_csc = device_private(csc); 694 } 695 696 return; 697 } 698 699 700 701 702 703 /* 704 * static void pccbb_chipinit(struct pccbb_softc *sc) 705 * 706 * This function initialize YENTA chip registers listed below: 707 * 1) PCI command reg, 708 * 2) PCI and CardBus latency timer, 709 * 3) route PCI interrupt, 710 * 4) close all memory and io windows. 711 * 5) turn off bus power. 712 * 6) card detect and power cycle interrupts on. 713 * 7) clear interrupt 714 */ 715 static void 716 pccbb_chipinit(struct pccbb_softc *sc) 717 { 718 pci_chipset_tag_t pc = sc->sc_pc; 719 pcitag_t tag = sc->sc_tag; 720 bus_space_tag_t bmt = sc->sc_base_memt; 721 bus_space_handle_t bmh = sc->sc_base_memh; 722 pcireg_t bcr, bhlc, cbctl, csr, lscp, mfunc, mrburst, slotctl, sockctl, 723 sysctrl; 724 725 /* 726 * Set PCI command reg. 727 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 728 */ 729 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 730 /* I believe it is harmless. */ 731 csr |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 732 PCI_COMMAND_MASTER_ENABLE); 733 734 /* All O2 Micro chips have broken parity-error reporting 735 * until proven otherwise. The OZ6933 PCI-CardBus Bridge 736 * is known to have the defect---see PR kern/38698. 737 */ 738 if (sc->sc_chipset != CB_O2MICRO) 739 csr |= PCI_COMMAND_PARITY_ENABLE; 740 741 csr |= PCI_COMMAND_SERR_ENABLE; 742 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 743 744 /* 745 * Set CardBus latency timer. 746 */ 747 lscp = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 748 if (PCI_CB_LATENCY(lscp) < 0x20) { 749 lscp &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 750 lscp |= (0x20 << PCI_CB_LATENCY_SHIFT); 751 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, lscp); 752 } 753 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 754 PCI_CB_LATENCY(lscp), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 755 756 /* 757 * Set PCI latency timer. 758 */ 759 bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG); 760 if (PCI_LATTIMER(bhlc) < 0x10) { 761 bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 762 bhlc |= (0x10 << PCI_LATTIMER_SHIFT); 763 pci_conf_write(pc, tag, PCI_BHLC_REG, bhlc); 764 } 765 DPRINTF(("PCI latency timer 0x%x (%x)\n", 766 PCI_LATTIMER(bhlc), pci_conf_read(pc, tag, PCI_BHLC_REG))); 767 768 769 /* Route functional interrupts to PCI. */ 770 bcr = pci_conf_read(pc, tag, PCI_BRIDGE_CONTROL_REG); 771 bcr |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 772 bcr |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 773 /* assert reset */ 774 bcr |= PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT; 775 /* Set master abort mode to 1, forward SERR# from secondary 776 * to primary, and detect parity errors on secondary. 777 */ 778 bcr |= PCI_BRIDGE_CONTROL_MABRT << PCI_BRIDGE_CONTROL_SHIFT; 779 bcr |= PCI_BRIDGE_CONTROL_SERR << PCI_BRIDGE_CONTROL_SHIFT; 780 bcr |= PCI_BRIDGE_CONTROL_PERE << PCI_BRIDGE_CONTROL_SHIFT; 781 pci_conf_write(pc, tag, PCI_BRIDGE_CONTROL_REG, bcr); 782 783 switch (sc->sc_chipset) { 784 case CB_TI113X: 785 cbctl = pci_conf_read(pc, tag, PCI_CBCTRL); 786 /* This bit is shared, but may read as 0 on some chips, so set 787 it explicitly on both functions. */ 788 cbctl |= PCI113X_CBCTRL_PCI_IRQ_ENA; 789 /* CSC intr enable */ 790 cbctl |= PCI113X_CBCTRL_PCI_CSC; 791 /* functional intr prohibit | prohibit ISA routing */ 792 cbctl &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 793 pci_conf_write(pc, tag, PCI_CBCTRL, cbctl); 794 break; 795 796 case CB_TI1420: 797 sysctrl = pci_conf_read(pc, tag, PCI_SYSCTRL); 798 mrburst = pccbb_burstup 799 ? PCI1420_SYSCTRL_MRBURST : PCI1420_SYSCTRL_MRBURSTDN; 800 if ((sysctrl & PCI1420_SYSCTRL_MRBURST) == mrburst) { 801 printf("%s: %swrite bursts enabled\n", 802 device_xname(sc->sc_dev), 803 pccbb_burstup ? "read/" : ""); 804 } else if (pccbb_burstup) { 805 printf("%s: enabling read/write bursts\n", 806 device_xname(sc->sc_dev)); 807 sysctrl |= PCI1420_SYSCTRL_MRBURST; 808 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 809 } else { 810 printf("%s: disabling read bursts, " 811 "enabling write bursts\n", 812 device_xname(sc->sc_dev)); 813 sysctrl |= PCI1420_SYSCTRL_MRBURSTDN; 814 sysctrl &= ~PCI1420_SYSCTRL_MRBURSTUP; 815 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 816 } 817 /*FALLTHROUGH*/ 818 case CB_TI12XX: 819 /* 820 * Some TI 12xx (and [14][45]xx) based pci cards 821 * sometimes have issues with the MFUNC register not 822 * being initialized due to a bad EEPROM on board. 823 * Laptops that this matters on have this register 824 * properly initialized. 825 * 826 * The TI125X parts have a different register. 827 */ 828 mfunc = pci_conf_read(pc, tag, PCI12XX_MFUNC); 829 if ((mfunc & (PCI12XX_MFUNC_PIN0 | PCI12XX_MFUNC_PIN1)) == 0) { 830 /* Enable PCI interrupt /INTA */ 831 mfunc |= PCI12XX_MFUNC_PIN0_INTA; 832 833 /* XXX this is TI1520 only */ 834 if ((pci_conf_read(pc, tag, PCI_SYSCTRL) & 835 PCI12XX_SYSCTRL_INTRTIE) == 0) 836 /* Enable PCI interrupt /INTB */ 837 mfunc |= PCI12XX_MFUNC_PIN1_INTB; 838 839 pci_conf_write(pc, tag, PCI12XX_MFUNC, mfunc); 840 } 841 /* fallthrough */ 842 843 case CB_TI125X: 844 /* 845 * Disable zoom video. Some machines initialize this 846 * improperly and experience has shown that this helps 847 * prevent strange behavior. 848 */ 849 pci_conf_write(pc, tag, PCI12XX_MMCTRL, 0); 850 851 sysctrl = pci_conf_read(pc, tag, PCI_SYSCTRL); 852 sysctrl |= PCI12XX_SYSCTRL_VCCPROT; 853 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 854 cbctl = pci_conf_read(pc, tag, PCI_CBCTRL); 855 cbctl |= PCI12XX_CBCTRL_CSC; 856 pci_conf_write(pc, tag, PCI_CBCTRL, cbctl); 857 break; 858 859 case CB_TOPIC95B: 860 sockctl = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 861 sockctl |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 862 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, sockctl); 863 slotctl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 864 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 865 device_xname(sc->sc_dev), slotctl)); 866 slotctl |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 867 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 868 slotctl &= ~TOPIC_SLOT_CTRL_SWDETECT; 869 DPRINTF(("0x%x\n", slotctl)); 870 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slotctl); 871 break; 872 873 case CB_TOPIC97: 874 slotctl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 875 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 876 device_xname(sc->sc_dev), slotctl)); 877 slotctl |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 878 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 879 slotctl &= ~TOPIC_SLOT_CTRL_SWDETECT; 880 slotctl |= TOPIC97_SLOT_CTRL_PCIINT; 881 slotctl &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 882 DPRINTF(("0x%x\n", slotctl)); 883 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slotctl); 884 /* make sure to assert LV card support bits */ 885 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 886 0x800 + 0x3e, 887 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 888 0x800 + 0x3e) | 0x03); 889 break; 890 } 891 892 /* Close all memory and I/O windows. */ 893 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 894 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 895 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 896 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 897 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 898 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 899 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 900 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 901 902 /* reset 16-bit pcmcia bus */ 903 bus_space_write_1(bmt, bmh, 0x800 + PCIC_INTR, 904 bus_space_read_1(bmt, bmh, 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 905 906 /* turn off power */ 907 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 908 } 909 910 static void 911 pccbb_intrinit(struct pccbb_softc *sc) 912 { 913 pcireg_t sockmask; 914 const char *intrstr = NULL; 915 pci_intr_handle_t ih; 916 pci_chipset_tag_t pc = sc->sc_pc; 917 bus_space_tag_t bmt = sc->sc_base_memt; 918 bus_space_handle_t bmh = sc->sc_base_memh; 919 char intrbuf[PCI_INTRSTR_LEN]; 920 921 /* Map and establish the interrupt. */ 922 if (pci_intr_map(&sc->sc_pa, &ih)) { 923 aprint_error_dev(sc->sc_dev, "couldn't map interrupt\n"); 924 return; 925 } 926 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 927 928 /* 929 * XXX pccbbintr should be called under the priority lower 930 * than any other hard interrupts. 931 */ 932 KASSERT(sc->sc_ih == NULL); 933 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 934 935 if (sc->sc_ih == NULL) { 936 aprint_error_dev(sc->sc_dev, "couldn't establish interrupt"); 937 if (intrstr != NULL) 938 aprint_error(" at %s\n", intrstr); 939 else 940 aprint_error("\n"); 941 return; 942 } 943 944 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 945 946 /* CSC Interrupt: Card detect and power cycle interrupts on */ 947 sockmask = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 948 sockmask |= CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | 949 CB_SOCKET_MASK_POWER; 950 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, sockmask); 951 /* reset interrupt */ 952 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 953 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 954 } 955 956 /* 957 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 958 * struct pcmciabus_attach_args *paa) 959 * 960 * This function attaches 16-bit PCcard bus. 961 */ 962 STATIC void 963 pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 964 struct pcmciabus_attach_args *paa) 965 { 966 /* 967 * We need to do a few things here: 968 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 969 * setting the IRQ numbers to 0. 970 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 971 * routing of CSC interrupts (e.g. card removal) to PCI while in 972 * PCMCIA mode. We just leave this set all the time. 973 * 3) Enable card insertion/removal interrupts in case the chip also 974 * needs that while in PCMCIA mode. 975 * 4) Clear any pending CSC interrupt. 976 */ 977 Pcic_write(sc, PCIC_INTR, PCIC_INTR_ENABLE); 978 if (sc->sc_chipset == CB_TI113X) { 979 Pcic_write(sc, PCIC_CSC_INTR, 0); 980 } else { 981 Pcic_write(sc, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 982 Pcic_read(sc, PCIC_CSC); 983 } 984 985 /* initialize pcmcia bus attachment */ 986 paa->paa_busname = "pcmcia"; 987 paa->pct = &pccbb_pcmcia_funcs; 988 paa->pch = sc; 989 return; 990 } 991 992 /* 993 * int pccbbintr(arg) 994 * void *arg; 995 * This routine handles the interrupt from Yenta PCI-CardBus bridge 996 * itself. 997 */ 998 int 999 pccbbintr(void *arg) 1000 { 1001 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1002 struct cardslot_softc *csc; 1003 u_int32_t sockevent, sockstate; 1004 bus_space_tag_t memt = sc->sc_base_memt; 1005 bus_space_handle_t memh = sc->sc_base_memh; 1006 1007 if (!device_has_power(sc->sc_dev)) 1008 return 0; 1009 1010 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 1011 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 1012 Pcic_read(sc, PCIC_CSC); 1013 1014 if (sockevent != 0) { 1015 DPRINTF(("%s: enter sockevent %" PRIx32 "\n", 1016 __func__, sockevent)); 1017 } 1018 1019 /* XXX sockevent == CB_SOCKET_EVENT_CSTS|CB_SOCKET_EVENT_POWER 1020 * does occur in the wild. Check for a _POWER event before 1021 * possibly exiting because of an _CSTS event. 1022 */ 1023 if (sockevent & CB_SOCKET_EVENT_POWER) { 1024 DPRINTF(("Powercycling because of socket event\n")); 1025 /* XXX: Does not happen when attaching a 16-bit card */ 1026 mutex_enter(&sc->sc_pwr_mtx); 1027 sc->sc_pwrcycle++; 1028 cv_signal(&sc->sc_pwr_cv); 1029 mutex_exit(&sc->sc_pwr_mtx); 1030 } 1031 1032 /* Sometimes a change of CSTSCHG# accompanies the first 1033 * interrupt from an Atheros WLAN. That generates a 1034 * CB_SOCKET_EVENT_CSTS event on the bridge. The event 1035 * isn't interesting to pccbb(4), so we used to ignore the 1036 * interrupt. Now, let the child devices try to handle 1037 * the interrupt, instead. The Atheros NIC produces 1038 * interrupts more reliably, now: used to be that it would 1039 * only interrupt if the driver avoided powering down the 1040 * NIC's cardslot, and then the NIC would only work after 1041 * it was reset a second time. 1042 */ 1043 if (sockevent == 0 || 1044 (sockevent & ~(CB_SOCKET_EVENT_POWER|CB_SOCKET_EVENT_CD)) != 0) { 1045 /* This intr is not for me: it may be for my child devices. */ 1046 if (sc->sc_pil_intr_enable) { 1047 return pccbbintr_function(sc); 1048 } else { 1049 return 0; 1050 } 1051 } 1052 1053 if (sockevent & CB_SOCKET_EVENT_CD) { 1054 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1055 if (0x00 != (sockstate & CB_SOCKET_STAT_CD)) { 1056 /* A card should be removed. */ 1057 if (sc->sc_flags & CBB_CARDEXIST) { 1058 DPRINTF(("%s: 0x%08x", 1059 device_xname(sc->sc_dev), sockevent)); 1060 DPRINTF((" card removed, 0x%08x\n", sockstate)); 1061 sc->sc_flags &= ~CBB_CARDEXIST; 1062 if ((csc = sc->sc_csc) == NULL) 1063 ; 1064 else if (csc->sc_status & 1065 CARDSLOT_STATUS_CARD_16) { 1066 cardslot_event_throw(csc, 1067 CARDSLOT_EVENT_REMOVAL_16); 1068 } else if (csc->sc_status & 1069 CARDSLOT_STATUS_CARD_CB) { 1070 /* Cardbus intr removed */ 1071 cardslot_event_throw(csc, 1072 CARDSLOT_EVENT_REMOVAL_CB); 1073 } 1074 } else if (sc->sc_flags & CBB_INSERTING) { 1075 sc->sc_flags &= ~CBB_INSERTING; 1076 callout_stop(&sc->sc_insert_ch); 1077 } 1078 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 1079 /* 1080 * The pccbbintr may called from powerdown hook when 1081 * the system resumed, to detect the card 1082 * insertion/removal during suspension. 1083 */ 1084 (sc->sc_flags & CBB_CARDEXIST) == 0) { 1085 if (sc->sc_flags & CBB_INSERTING) { 1086 callout_stop(&sc->sc_insert_ch); 1087 } 1088 callout_schedule(&sc->sc_insert_ch, mstohz(200)); 1089 sc->sc_flags |= CBB_INSERTING; 1090 } 1091 } 1092 1093 return (1); 1094 } 1095 1096 /* 1097 * static int pccbbintr_function(struct pccbb_softc *sc) 1098 * 1099 * This function calls each interrupt handler registered at the 1100 * bridge. The interrupt handlers are called in registered order. 1101 */ 1102 static int 1103 pccbbintr_function(struct pccbb_softc *sc) 1104 { 1105 int retval = 0, val; 1106 struct pccbb_intrhand_list *pil; 1107 int s; 1108 1109 LIST_FOREACH(pil, &sc->sc_pil, pil_next) { 1110 s = splraiseipl(pil->pil_icookie); 1111 val = (*pil->pil_func)(pil->pil_arg); 1112 splx(s); 1113 1114 retval = retval == 1 ? 1 : 1115 retval == 0 ? val : val != 0 ? val : retval; 1116 } 1117 1118 return retval; 1119 } 1120 1121 static void 1122 pci113x_insert(void *arg) 1123 { 1124 struct pccbb_softc *sc = arg; 1125 struct cardslot_softc *csc; 1126 u_int32_t sockevent, sockstate; 1127 1128 if (!(sc->sc_flags & CBB_INSERTING)) { 1129 /* We add a card only under inserting state. */ 1130 return; 1131 } 1132 sc->sc_flags &= ~CBB_INSERTING; 1133 1134 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1135 CB_SOCKET_EVENT); 1136 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1137 CB_SOCKET_STAT); 1138 1139 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1140 #ifdef CBB_DEBUG 1141 DPRINTF(("%s: 0x%08x", device_xname(sc->sc_dev), sockevent)); 1142 #else 1143 __USE(sockevent); 1144 #endif 1145 1146 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1147 sc->sc_flags |= CBB_CARDEXIST; 1148 /* call pccard interrupt handler here */ 1149 if ((csc = sc->sc_csc) == NULL) 1150 ; 1151 else if (sockstate & CB_SOCKET_STAT_16BIT) { 1152 /* 16-bit card found */ 1153 cardslot_event_throw(csc, CARDSLOT_EVENT_INSERTION_16); 1154 } else if (sockstate & CB_SOCKET_STAT_CB) { 1155 /* cardbus card found */ 1156 cardslot_event_throw(csc, CARDSLOT_EVENT_INSERTION_CB); 1157 } else { 1158 /* who are you? */ 1159 } 1160 } else { 1161 callout_schedule(&sc->sc_insert_ch, mstohz(100)); 1162 } 1163 } 1164 1165 #define PCCBB_PCMCIA_OFFSET 0x800 1166 static u_int8_t 1167 pccbb_pcmcia_read(struct pccbb_softc *sc, int reg) 1168 { 1169 bus_space_barrier(sc->sc_base_memt, sc->sc_base_memh, 1170 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1171 1172 return bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 1173 PCCBB_PCMCIA_OFFSET + reg); 1174 } 1175 1176 static void 1177 pccbb_pcmcia_write(struct pccbb_softc *sc, int reg, u_int8_t val) 1178 { 1179 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 1180 PCCBB_PCMCIA_OFFSET + reg, val); 1181 1182 bus_space_barrier(sc->sc_base_memt, sc->sc_base_memh, 1183 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1184 } 1185 1186 /* 1187 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1188 */ 1189 STATIC int 1190 pccbb_ctrl(cardbus_chipset_tag_t ct, int command) 1191 { 1192 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1193 1194 switch (command) { 1195 case CARDBUS_CD: 1196 if (2 == pccbb_detect_card(sc)) { 1197 int retval = 0; 1198 int status = cb_detect_voltage(sc); 1199 if (PCCARD_VCC_5V & status) { 1200 retval |= CARDBUS_5V_CARD; 1201 } 1202 if (PCCARD_VCC_3V & status) { 1203 retval |= CARDBUS_3V_CARD; 1204 } 1205 if (PCCARD_VCC_XV & status) { 1206 retval |= CARDBUS_XV_CARD; 1207 } 1208 if (PCCARD_VCC_YV & status) { 1209 retval |= CARDBUS_YV_CARD; 1210 } 1211 return retval; 1212 } else { 1213 return 0; 1214 } 1215 case CARDBUS_RESET: 1216 return cb_reset(sc); 1217 case CARDBUS_IO_ENABLE: /* fallthrough */ 1218 case CARDBUS_IO_DISABLE: /* fallthrough */ 1219 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1220 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1221 case CARDBUS_BM_ENABLE: /* fallthrough */ 1222 case CARDBUS_BM_DISABLE: /* fallthrough */ 1223 /* XXX: I think we don't need to call this function below. */ 1224 return pccbb_cardenable(sc, command); 1225 } 1226 1227 return 0; 1228 } 1229 1230 STATIC int 1231 pccbb_power_ct(cardbus_chipset_tag_t ct, int command) 1232 { 1233 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1234 1235 return pccbb_power(sc, command); 1236 } 1237 1238 /* 1239 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1240 * This function returns true when it succeeds and returns false when 1241 * it fails. 1242 */ 1243 STATIC int 1244 pccbb_power(struct pccbb_softc *sc, int command) 1245 { 1246 u_int32_t status, osock_ctrl, sock_ctrl, reg_ctrl; 1247 bus_space_tag_t memt = sc->sc_base_memt; 1248 bus_space_handle_t memh = sc->sc_base_memh; 1249 int on = 0, pwrcycle, times; 1250 struct timeval before, after, diff; 1251 1252 DPRINTF(("pccbb_power: %s and %s [0x%x]\n", 1253 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1254 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1255 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1256 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1257 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1258 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1259 "UNKNOWN", 1260 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1261 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1262 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1263 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1264 "UNKNOWN", command)); 1265 1266 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1267 osock_ctrl = sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1268 1269 switch (command & CARDBUS_VCCMASK) { 1270 case CARDBUS_VCC_UC: 1271 break; 1272 case CARDBUS_VCC_5V: 1273 on++; 1274 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1275 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1276 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1277 } else { 1278 aprint_error_dev(sc->sc_dev, 1279 "BAD voltage request: no 5 V card\n"); 1280 return 0; 1281 } 1282 break; 1283 case CARDBUS_VCC_3V: 1284 on++; 1285 if (CB_SOCKET_STAT_3VCARD & status) { 1286 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1287 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1288 } else { 1289 aprint_error_dev(sc->sc_dev, 1290 "BAD voltage request: no 3.3 V card\n"); 1291 return 0; 1292 } 1293 break; 1294 case CARDBUS_VCC_0V: 1295 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1296 break; 1297 default: 1298 return 0; /* power NEVER changed */ 1299 } 1300 1301 switch (command & CARDBUS_VPPMASK) { 1302 case CARDBUS_VPP_UC: 1303 break; 1304 case CARDBUS_VPP_0V: 1305 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1306 break; 1307 case CARDBUS_VPP_VCC: 1308 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1309 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1310 break; 1311 case CARDBUS_VPP_12V: 1312 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1313 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1314 break; 1315 } 1316 aprint_debug_dev(sc->sc_dev, "osock_ctrl %#" PRIx32 1317 " sock_ctrl %#" PRIx32 "\n", osock_ctrl, sock_ctrl); 1318 1319 microtime(&before); 1320 mutex_enter(&sc->sc_pwr_mtx); 1321 pwrcycle = sc->sc_pwrcycle; 1322 1323 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1324 1325 /* 1326 * Wait as long as 200ms for a power-cycle interrupt. If 1327 * interrupts are enabled, but the socket has already 1328 * changed to the desired status, keep waiting for the 1329 * interrupt. "Consuming" the interrupt in this way keeps 1330 * the interrupt from prematurely waking some subsequent 1331 * pccbb_power call. 1332 * 1333 * XXX Not every bridge interrupts on the ->OFF transition. 1334 * XXX That's ok, we will time-out after 200ms. 1335 * 1336 * XXX The power cycle event will never happen when attaching 1337 * XXX a 16-bit card. That's ok, we will time-out after 1338 * XXX 200ms. 1339 */ 1340 for (times = 5; --times >= 0; ) { 1341 if (cold) 1342 DELAY(40 * 1000); 1343 else { 1344 (void)cv_timedwait(&sc->sc_pwr_cv, &sc->sc_pwr_mtx, 1345 mstohz(40)); 1346 if (pwrcycle == sc->sc_pwrcycle) 1347 continue; 1348 } 1349 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1350 if ((status & CB_SOCKET_STAT_PWRCYCLE) != 0 && on) 1351 break; 1352 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0 && !on) 1353 break; 1354 } 1355 mutex_exit(&sc->sc_pwr_mtx); 1356 microtime(&after); 1357 timersub(&after, &before, &diff); 1358 aprint_debug_dev(sc->sc_dev, "wait took%s %lld.%06lds\n", 1359 (on && times < 0) ? " too long" : "", (long long)diff.tv_sec, 1360 (long)diff.tv_usec); 1361 1362 /* 1363 * Ok, wait a bit longer for things to settle. 1364 */ 1365 if (on && sc->sc_chipset == CB_TOPIC95B) 1366 delay_ms(100, sc); 1367 1368 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1369 1370 if (on && sc->sc_chipset != CB_TOPIC95B) { 1371 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0) 1372 aprint_error_dev(sc->sc_dev, "power on failed?\n"); 1373 } 1374 1375 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1376 aprint_error_dev(sc->sc_dev, 1377 "bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1378 sock_ctrl, status); 1379 aprint_error_dev(sc->sc_dev, "disabling socket\n"); 1380 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1381 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1382 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1383 status &= ~CB_SOCKET_STAT_BADVCC; 1384 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, status); 1385 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1386 CB_SOCKET_STAT)); 1387 return 0; 1388 } 1389 1390 if (sc->sc_chipset == CB_TOPIC97) { 1391 reg_ctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL); 1392 reg_ctrl &= ~TOPIC97_REG_CTRL_TESTMODE; 1393 if ((command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V) 1394 reg_ctrl &= ~TOPIC97_REG_CTRL_CLKRUN_ENA; 1395 else 1396 reg_ctrl |= TOPIC97_REG_CTRL_CLKRUN_ENA; 1397 pci_conf_write(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL, reg_ctrl); 1398 } 1399 1400 return 1; /* power changed correctly */ 1401 } 1402 1403 /* 1404 * static int pccbb_detect_card(struct pccbb_softc *sc) 1405 * return value: 0 if no card exists. 1406 * 1 if 16-bit card exists. 1407 * 2 if cardbus card exists. 1408 */ 1409 static int 1410 pccbb_detect_card(struct pccbb_softc *sc) 1411 { 1412 bus_space_handle_t base_memh = sc->sc_base_memh; 1413 bus_space_tag_t base_memt = sc->sc_base_memt; 1414 u_int32_t sockstat = 1415 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1416 int retval = 0; 1417 1418 /* CD1 and CD2 asserted */ 1419 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1420 /* card must be present */ 1421 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1422 /* NOTACARD DEASSERTED */ 1423 if (CB_SOCKET_STAT_CB & sockstat) { 1424 /* CardBus mode */ 1425 retval = 2; 1426 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1427 /* 16-bit mode */ 1428 retval = 1; 1429 } 1430 } 1431 } 1432 return retval; 1433 } 1434 1435 /* 1436 * STATIC int cb_reset(struct pccbb_softc *sc) 1437 * This function resets CardBus card. 1438 */ 1439 STATIC int 1440 cb_reset(struct pccbb_softc *sc) 1441 { 1442 /* 1443 * Reset Assert at least 20 ms 1444 * Some machines request longer duration. 1445 */ 1446 int reset_duration = 1447 (sc->sc_chipset == CB_RX5C47X ? 400 : 50); 1448 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1449 aprint_debug("%s: enter bcr %" PRIx32 "\n", __func__, bcr); 1450 1451 /* Reset bit Assert (bit 6 at 0x3E) */ 1452 bcr |= PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT; 1453 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr); 1454 aprint_debug("%s: wrote bcr %" PRIx32 "\n", __func__, bcr); 1455 delay_ms(reset_duration, sc); 1456 1457 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1458 /* Reset bit Deassert (bit 6 at 0x3E) */ 1459 bcr &= ~(PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT); 1460 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, 1461 bcr); 1462 aprint_debug("%s: wrote bcr %" PRIx32 "\n", __func__, bcr); 1463 delay_ms(reset_duration, sc); 1464 aprint_debug("%s: end of delay\n", __func__); 1465 } 1466 /* No card found on the slot. Keep Reset. */ 1467 return 1; 1468 } 1469 1470 /* 1471 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1472 * This function detect card Voltage. 1473 */ 1474 STATIC int 1475 cb_detect_voltage(struct pccbb_softc *sc) 1476 { 1477 u_int32_t psr; /* socket present-state reg */ 1478 bus_space_tag_t iot = sc->sc_base_memt; 1479 bus_space_handle_t ioh = sc->sc_base_memh; 1480 int vol = PCCARD_VCC_UKN; /* set 0 */ 1481 1482 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1483 1484 if (0x400u & psr) { 1485 vol |= PCCARD_VCC_5V; 1486 } 1487 if (0x800u & psr) { 1488 vol |= PCCARD_VCC_3V; 1489 } 1490 1491 return vol; 1492 } 1493 1494 STATIC int 1495 cbbprint(void *aux, const char *pcic) 1496 { 1497 #if 0 1498 struct cbslot_attach_args *cba = aux; 1499 1500 if (cba->cba_slot >= 0) { 1501 aprint_normal(" slot %d", cba->cba_slot); 1502 } 1503 #endif 1504 return UNCONF; 1505 } 1506 1507 /* 1508 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1509 * This function enables and disables the card 1510 */ 1511 STATIC int 1512 pccbb_cardenable(struct pccbb_softc *sc, int function) 1513 { 1514 u_int32_t command = 1515 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1516 1517 DPRINTF(("pccbb_cardenable:")); 1518 switch (function) { 1519 case CARDBUS_IO_ENABLE: 1520 command |= PCI_COMMAND_IO_ENABLE; 1521 break; 1522 case CARDBUS_IO_DISABLE: 1523 command &= ~PCI_COMMAND_IO_ENABLE; 1524 break; 1525 case CARDBUS_MEM_ENABLE: 1526 command |= PCI_COMMAND_MEM_ENABLE; 1527 break; 1528 case CARDBUS_MEM_DISABLE: 1529 command &= ~PCI_COMMAND_MEM_ENABLE; 1530 break; 1531 case CARDBUS_BM_ENABLE: 1532 command |= PCI_COMMAND_MASTER_ENABLE; 1533 break; 1534 case CARDBUS_BM_DISABLE: 1535 command &= ~PCI_COMMAND_MASTER_ENABLE; 1536 break; 1537 default: 1538 return 0; 1539 } 1540 1541 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1542 DPRINTF((" command reg 0x%x\n", command)); 1543 return 1; 1544 } 1545 1546 #if !rbus 1547 static int 1548 pccbb_io_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 1549 { 1550 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1551 int basereg; 1552 int limitreg; 1553 1554 if ((win < 0) || (win > 2)) { 1555 #if defined DIAGNOSTIC 1556 printf("cardbus_io_open: window out of range %d\n", win); 1557 #endif 1558 return 0; 1559 } 1560 1561 basereg = win * 8 + PCI_CB_IOBASE0; 1562 limitreg = win * 8 + PCI_CB_IOLIMIT0; 1563 1564 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1565 start, basereg, end, limitreg)); 1566 1567 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1568 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1569 return 1; 1570 } 1571 1572 /* 1573 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1574 */ 1575 static int 1576 pccbb_io_close(cardbus_chipset_tag_t ct, int win) 1577 { 1578 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1579 int basereg; 1580 int limitreg; 1581 1582 if ((win < 0) || (win > 2)) { 1583 #if defined DIAGNOSTIC 1584 printf("cardbus_io_close: window out of range %d\n", win); 1585 #endif 1586 return 0; 1587 } 1588 1589 basereg = win * 8 + PCI_CB_IOBASE0; 1590 limitreg = win * 8 + PCI_CB_IOLIMIT0; 1591 1592 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1593 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1594 return 1; 1595 } 1596 1597 static int 1598 pccbb_mem_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 1599 { 1600 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1601 int basereg; 1602 int limitreg; 1603 1604 if ((win < 0) || (win > 2)) { 1605 #if defined DIAGNOSTIC 1606 printf("cardbus_mem_open: window out of range %d\n", win); 1607 #endif 1608 return 0; 1609 } 1610 1611 basereg = win * 8 + PCI_CB_MEMBASE0; 1612 limitreg = win * 8 + PCI_CB_MEMLIMIT0; 1613 1614 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1615 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1616 return 1; 1617 } 1618 1619 static int 1620 pccbb_mem_close(cardbus_chipset_tag_t ct, int win) 1621 { 1622 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1623 int basereg; 1624 int limitreg; 1625 1626 if ((win < 0) || (win > 2)) { 1627 #if defined DIAGNOSTIC 1628 printf("cardbus_mem_close: window out of range %d\n", win); 1629 #endif 1630 return 0; 1631 } 1632 1633 basereg = win * 8 + PCI_CB_MEMBASE0; 1634 limitreg = win * 8 + PCI_CB_MEMLIMIT0; 1635 1636 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1637 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1638 return 1; 1639 } 1640 #endif 1641 1642 /* 1643 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1644 * int level, 1645 * int (* func)(void *), 1646 * void *arg) 1647 * 1648 * This function registers an interrupt handler at the bridge, in 1649 * order not to call the interrupt handlers of child devices when 1650 * a card-deletion interrupt occurs. 1651 * 1652 * The argument level is not used. 1653 */ 1654 static void * 1655 pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, int level, 1656 int (*func)(void *), void *arg) 1657 { 1658 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1659 1660 return pccbb_intr_establish(sc, level, func, arg); 1661 } 1662 1663 1664 /* 1665 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1666 * void *ih) 1667 * 1668 * This function removes an interrupt handler pointed by ih. 1669 */ 1670 static void 1671 pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih) 1672 { 1673 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1674 1675 pccbb_intr_disestablish(sc, ih); 1676 } 1677 1678 1679 void 1680 pccbb_intr_route(struct pccbb_softc *sc) 1681 { 1682 pcireg_t bcr, cbctrl; 1683 1684 /* initialize bridge intr routing */ 1685 bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1686 bcr &= ~CB_BCR_INTR_IREQ_ENABLE; 1687 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr); 1688 1689 switch (sc->sc_chipset) { 1690 case CB_TI113X: 1691 cbctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1692 /* functional intr enabled */ 1693 cbctrl |= PCI113X_CBCTRL_PCI_INTR; 1694 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, cbctrl); 1695 break; 1696 default: 1697 break; 1698 } 1699 } 1700 1701 /* 1702 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1703 * int irq, 1704 * int level, 1705 * int (* func)(void *), 1706 * void *arg) 1707 * 1708 * This function registers an interrupt handler at the bridge, in 1709 * order not to call the interrupt handlers of child devices when 1710 * a card-deletion interrupt occurs. 1711 * 1712 */ 1713 static void * 1714 pccbb_intr_establish(struct pccbb_softc *sc, int level, 1715 int (*func)(void *), void *arg) 1716 { 1717 struct pccbb_intrhand_list *pil, *newpil; 1718 1719 DPRINTF(("pccbb_intr_establish start. %p\n", LIST_FIRST(&sc->sc_pil))); 1720 1721 if (LIST_EMPTY(&sc->sc_pil)) { 1722 pccbb_intr_route(sc); 1723 } 1724 1725 /* 1726 * Allocate a room for interrupt handler structure. 1727 */ 1728 if (NULL == (newpil = 1729 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1730 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1731 return NULL; 1732 } 1733 1734 newpil->pil_func = func; 1735 newpil->pil_arg = arg; 1736 newpil->pil_icookie = makeiplcookie(level); 1737 1738 if (LIST_EMPTY(&sc->sc_pil)) { 1739 LIST_INSERT_HEAD(&sc->sc_pil, newpil, pil_next); 1740 } else { 1741 for (pil = LIST_FIRST(&sc->sc_pil); 1742 LIST_NEXT(pil, pil_next) != NULL; 1743 pil = LIST_NEXT(pil, pil_next)); 1744 LIST_INSERT_AFTER(pil, newpil, pil_next); 1745 } 1746 1747 DPRINTF(("pccbb_intr_establish add pil. %p\n", 1748 LIST_FIRST(&sc->sc_pil))); 1749 1750 return newpil; 1751 } 1752 1753 /* 1754 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1755 * void *ih) 1756 * 1757 * This function removes an interrupt handler pointed by ih. ih 1758 * should be the value returned by cardbus_intr_establish() or 1759 * NULL. 1760 * 1761 * When ih is NULL, this function will do nothing. 1762 */ 1763 static void 1764 pccbb_intr_disestablish(struct pccbb_softc *sc, void *ih) 1765 { 1766 struct pccbb_intrhand_list *pil; 1767 pcireg_t reg; 1768 1769 DPRINTF(("pccbb_intr_disestablish start. %p\n", 1770 LIST_FIRST(&sc->sc_pil))); 1771 1772 if (ih == NULL) { 1773 /* intr handler is not set */ 1774 DPRINTF(("pccbb_intr_disestablish: no ih\n")); 1775 return; 1776 } 1777 1778 #ifdef DIAGNOSTIC 1779 LIST_FOREACH(pil, &sc->sc_pil, pil_next) { 1780 DPRINTF(("pccbb_intr_disestablish: pil %p\n", pil)); 1781 if (pil == ih) { 1782 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1783 break; 1784 } 1785 } 1786 if (pil == NULL) { 1787 panic("pccbb_intr_disestablish: %s cannot find pil %p", 1788 device_xname(sc->sc_dev), ih); 1789 } 1790 #endif 1791 1792 pil = (struct pccbb_intrhand_list *)ih; 1793 LIST_REMOVE(pil, pil_next); 1794 free(pil, M_DEVBUF); 1795 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1796 1797 if (LIST_EMPTY(&sc->sc_pil)) { 1798 /* No interrupt handlers */ 1799 1800 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1801 1802 /* stop routing PCI intr */ 1803 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1804 reg |= CB_BCR_INTR_IREQ_ENABLE; 1805 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, reg); 1806 1807 switch (sc->sc_chipset) { 1808 case CB_TI113X: 1809 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1810 /* functional intr disabled */ 1811 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1812 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1813 break; 1814 default: 1815 break; 1816 } 1817 } 1818 } 1819 1820 #if defined SHOW_REGS 1821 static void 1822 cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, bus_space_tag_t memt, 1823 bus_space_handle_t memh) 1824 { 1825 int i; 1826 printf("PCI config regs:"); 1827 for (i = 0; i < 0x50; i += 4) { 1828 if (i % 16 == 0) 1829 printf("\n 0x%02x:", i); 1830 printf(" %08x", pci_conf_read(pc, tag, i)); 1831 } 1832 for (i = 0x80; i < 0xb0; i += 4) { 1833 if (i % 16 == 0) 1834 printf("\n 0x%02x:", i); 1835 printf(" %08x", pci_conf_read(pc, tag, i)); 1836 } 1837 1838 if (memh == 0) { 1839 printf("\n"); 1840 return; 1841 } 1842 1843 printf("\nsocket regs:"); 1844 for (i = 0; i <= 0x10; i += 0x04) 1845 printf(" %08x", bus_space_read_4(memt, memh, i)); 1846 printf("\nExCA regs:"); 1847 for (i = 0; i < 0x08; ++i) 1848 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1849 printf("\n"); 1850 return; 1851 } 1852 #endif 1853 1854 /* 1855 * static pcitag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1856 * int busno, int function) 1857 * This is the function to make a tag to access config space of 1858 * a CardBus Card. It works same as pci_conf_read. 1859 */ 1860 static pcitag_t 1861 pccbb_make_tag(cardbus_chipset_tag_t cc, int busno, int function) 1862 { 1863 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1864 1865 return pci_make_tag(sc->sc_pc, busno, 0, function); 1866 } 1867 1868 /* 1869 * pccbb_conf_read 1870 * 1871 * This is the function to read the config space of a CardBus card. 1872 * It works the same as pci_conf_read(9). 1873 */ 1874 static pcireg_t 1875 pccbb_conf_read(cardbus_chipset_tag_t cc, pcitag_t tag, int offset) 1876 { 1877 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1878 pcitag_t brtag = sc->sc_tag; 1879 pcireg_t reg; 1880 1881 /* 1882 * clear cardbus master abort status; it is OK to write without 1883 * reading before because all bits are r/o or w1tc 1884 */ 1885 pci_conf_write(sc->sc_pc, brtag, PCI_CBB_SECSTATUS, 1886 CBB_SECSTATUS_CBMABORT); 1887 reg = pci_conf_read(sc->sc_pc, tag, offset); 1888 /* check cardbus master abort status */ 1889 if (pci_conf_read(sc->sc_pc, brtag, PCI_CBB_SECSTATUS) 1890 & CBB_SECSTATUS_CBMABORT) 1891 return (0xffffffff); 1892 return reg; 1893 } 1894 1895 /* 1896 * pccbb_conf_write 1897 * 1898 * This is the function to write the config space of a CardBus 1899 * card. It works the same as pci_conf_write(9). 1900 */ 1901 static void 1902 pccbb_conf_write(cardbus_chipset_tag_t cc, pcitag_t tag, int reg, pcireg_t val) 1903 { 1904 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1905 1906 pci_conf_write(sc->sc_pc, tag, reg, val); 1907 } 1908 1909 #if 0 1910 STATIC int 1911 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1912 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 1913 int speed, int flags, 1914 bus_space_handle_t * iohp) 1915 #endif 1916 /* 1917 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1918 * bus_addr_t start, bus_size_t size, 1919 * bus_size_t align, 1920 * struct pcmcia_io_handle *pcihp 1921 * 1922 * This function only allocates I/O region for pccard. This function 1923 * never maps the allocated region to pccard I/O area. 1924 * 1925 * XXX: The interface of this function is not very good, I believe. 1926 */ 1927 STATIC int 1928 pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, 1929 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 1930 { 1931 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 1932 bus_addr_t ioaddr; 1933 int flags = 0; 1934 bus_space_tag_t iot; 1935 bus_space_handle_t ioh; 1936 bus_addr_t mask; 1937 #if rbus 1938 rbus_tag_t rb; 1939 #endif 1940 if (align == 0) { 1941 align = size; /* XXX: funny??? */ 1942 } 1943 1944 if (start != 0) { 1945 /* XXX: assume all card decode lower 10 bits by its hardware */ 1946 mask = 0x3ff; 1947 /* enforce to use only masked address */ 1948 start &= mask; 1949 } else { 1950 /* 1951 * calculate mask: 1952 * 1. get the most significant bit of size (call it msb). 1953 * 2. compare msb with the value of size. 1954 * 3. if size is larger, shift msb left once. 1955 * 4. obtain mask value to decrement msb. 1956 */ 1957 bus_size_t size_tmp = size; 1958 int shifts = 0; 1959 1960 mask = 1; 1961 while (size_tmp) { 1962 ++shifts; 1963 size_tmp >>= 1; 1964 } 1965 mask = (1 << shifts); 1966 if (mask < size) { 1967 mask <<= 1; 1968 } 1969 --mask; 1970 } 1971 1972 /* 1973 * Allocate some arbitrary I/O space. 1974 */ 1975 1976 iot = sc->sc_iot; 1977 1978 #if rbus 1979 rb = sc->sc_rbus_iot; 1980 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 1981 return 1; 1982 } 1983 DPRINTF(("pccbb_pcmcia_io_alloc alloc port 0x%lx+0x%lx\n", 1984 (u_long) ioaddr, (u_long) size)); 1985 #else 1986 if (start) { 1987 ioaddr = start; 1988 if (bus_space_map(iot, start, size, 0, &ioh)) { 1989 return 1; 1990 } 1991 DPRINTF(("pccbb_pcmcia_io_alloc map port 0x%lx+0x%lx\n", 1992 (u_long) ioaddr, (u_long) size)); 1993 } else { 1994 flags |= PCMCIA_IO_ALLOCATED; 1995 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 1996 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 1997 size, align, 0, 0, &ioaddr, &ioh)) { 1998 /* No room be able to be get. */ 1999 return 1; 2000 } 2001 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2002 (u_long) ioaddr, (u_long) size)); 2003 } 2004 #endif 2005 2006 pcihp->iot = iot; 2007 pcihp->ioh = ioh; 2008 pcihp->addr = ioaddr; 2009 pcihp->size = size; 2010 pcihp->flags = flags; 2011 2012 return 0; 2013 } 2014 2015 /* 2016 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2017 * struct pcmcia_io_handle *pcihp) 2018 * 2019 * This function only frees I/O region for pccard. 2020 * 2021 * XXX: The interface of this function is not very good, I believe. 2022 */ 2023 void 2024 pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2025 struct pcmcia_io_handle *pcihp) 2026 { 2027 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2028 #if !rbus 2029 bus_space_tag_t iot = pcihp->iot; 2030 #endif 2031 bus_space_handle_t ioh = pcihp->ioh; 2032 bus_size_t size = pcihp->size; 2033 2034 #if rbus 2035 rbus_tag_t rb = sc->sc_rbus_iot; 2036 2037 rbus_space_free(rb, ioh, size, NULL); 2038 #else 2039 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 2040 bus_space_free(iot, ioh, size); 2041 else 2042 bus_space_unmap(iot, ioh, size); 2043 #endif 2044 } 2045 2046 /* 2047 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 2048 * bus_addr_t offset, bus_size_t size, 2049 * struct pcmcia_io_handle *pcihp, 2050 * int *windowp) 2051 * 2052 * This function maps the allocated I/O region to pccard. This function 2053 * never allocates any I/O region for pccard I/O area. I don't 2054 * understand why the original authors of pcmciabus separated alloc and 2055 * map. I believe the two must be unite. 2056 * 2057 * XXX: no wait timing control? 2058 */ 2059 int 2060 pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, bus_addr_t offset, 2061 bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp) 2062 { 2063 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2064 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2065 bus_addr_t ioaddr = pcihp->addr + offset; 2066 int i, win; 2067 #if defined CBB_DEBUG 2068 static const char *width_names[] = { "dynamic", "io8", "io16" }; 2069 #endif 2070 2071 /* Sanity check I/O handle. */ 2072 2073 if (!bus_space_is_equal(sc->sc_iot, pcihp->iot)) { 2074 panic("pccbb_pcmcia_io_map iot is bogus"); 2075 } 2076 2077 /* XXX Sanity check offset/size. */ 2078 2079 win = -1; 2080 for (i = 0; i < PCIC_IO_WINS; i++) { 2081 if ((ph->ioalloc & (1 << i)) == 0) { 2082 win = i; 2083 ph->ioalloc |= (1 << i); 2084 break; 2085 } 2086 } 2087 2088 if (win == -1) { 2089 return 1; 2090 } 2091 2092 *windowp = win; 2093 2094 /* XXX this is pretty gross */ 2095 2096 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2097 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2098 2099 /* XXX wtf is this doing here? */ 2100 2101 #if 0 2102 printf(" port 0x%lx", (u_long) ioaddr); 2103 if (size > 1) { 2104 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2105 } 2106 #endif 2107 2108 ph->io[win].addr = ioaddr; 2109 ph->io[win].size = size; 2110 ph->io[win].width = width; 2111 2112 /* actual dirty register-value changing in the function below. */ 2113 pccbb_pcmcia_do_io_map(sc, win); 2114 2115 return 0; 2116 } 2117 2118 /* 2119 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2120 * 2121 * This function changes register-value to map I/O region for pccard. 2122 */ 2123 static void 2124 pccbb_pcmcia_do_io_map(struct pccbb_softc *sc, int win) 2125 { 2126 static u_int8_t pcic_iowidth[3] = { 2127 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2128 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2129 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2130 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2131 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2132 }; 2133 2134 #define PCIC_SIA_START_LOW 0 2135 #define PCIC_SIA_START_HIGH 1 2136 #define PCIC_SIA_STOP_LOW 2 2137 #define PCIC_SIA_STOP_HIGH 3 2138 2139 int regbase_win = 0x8 + win * 0x04; 2140 u_int8_t ioctl, enable; 2141 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2142 2143 DPRINTF(("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx " 2144 "width %d\n", win, (unsigned long)ph->io[win].addr, 2145 (unsigned long)ph->io[win].size, ph->io[win].width * 8)); 2146 2147 Pcic_write(sc, regbase_win + PCIC_SIA_START_LOW, 2148 ph->io[win].addr & 0xff); 2149 Pcic_write(sc, regbase_win + PCIC_SIA_START_HIGH, 2150 (ph->io[win].addr >> 8) & 0xff); 2151 2152 Pcic_write(sc, regbase_win + PCIC_SIA_STOP_LOW, 2153 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2154 Pcic_write(sc, regbase_win + PCIC_SIA_STOP_HIGH, 2155 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2156 2157 ioctl = Pcic_read(sc, PCIC_IOCTL); 2158 enable = Pcic_read(sc, PCIC_ADDRWIN_ENABLE); 2159 switch (win) { 2160 case 0: 2161 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2162 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2163 PCIC_IOCTL_IO0_DATASIZE_MASK); 2164 ioctl |= pcic_iowidth[ph->io[win].width]; 2165 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2166 break; 2167 case 1: 2168 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2169 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2170 PCIC_IOCTL_IO1_DATASIZE_MASK); 2171 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2172 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2173 break; 2174 } 2175 Pcic_write(sc, PCIC_IOCTL, ioctl); 2176 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, enable); 2177 #if defined(CBB_DEBUG) 2178 { 2179 u_int8_t start_low = 2180 Pcic_read(sc, regbase_win + PCIC_SIA_START_LOW); 2181 u_int8_t start_high = 2182 Pcic_read(sc, regbase_win + PCIC_SIA_START_HIGH); 2183 u_int8_t stop_low = 2184 Pcic_read(sc, regbase_win + PCIC_SIA_STOP_LOW); 2185 u_int8_t stop_high = 2186 Pcic_read(sc, regbase_win + PCIC_SIA_STOP_HIGH); 2187 printf("pccbb_pcmcia_do_io_map start %02x %02x, " 2188 "stop %02x %02x, ioctl %02x enable %02x\n", 2189 start_low, start_high, stop_low, stop_high, ioctl, enable); 2190 } 2191 #endif 2192 } 2193 2194 /* 2195 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2196 * 2197 * This function unmaps I/O region. No return value. 2198 */ 2199 STATIC void 2200 pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t pch, int win) 2201 { 2202 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2203 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2204 int reg; 2205 2206 if (win >= PCIC_IO_WINS || win < 0) { 2207 panic("pccbb_pcmcia_io_unmap: window out of range"); 2208 } 2209 2210 reg = Pcic_read(sc, PCIC_ADDRWIN_ENABLE); 2211 switch (win) { 2212 case 0: 2213 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2214 break; 2215 case 1: 2216 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2217 break; 2218 } 2219 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, reg); 2220 2221 ph->ioalloc &= ~(1 << win); 2222 } 2223 2224 static int 2225 pccbb_pcmcia_wait_ready(struct pccbb_softc *sc) 2226 { 2227 u_int8_t stat; 2228 int i; 2229 2230 /* wait an initial 10ms for quick cards */ 2231 stat = Pcic_read(sc, PCIC_IF_STATUS); 2232 if (stat & PCIC_IF_STATUS_READY) 2233 return (0); 2234 pccbb_pcmcia_delay(sc, 10, "pccwr0"); 2235 for (i = 0; i < 50; i++) { 2236 stat = Pcic_read(sc, PCIC_IF_STATUS); 2237 if (stat & PCIC_IF_STATUS_READY) 2238 return (0); 2239 if ((stat & PCIC_IF_STATUS_CARDDETECT_MASK) != 2240 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2241 return (ENXIO); 2242 /* wait .1s (100ms) each iteration now */ 2243 pccbb_pcmcia_delay(sc, 100, "pccwr1"); 2244 } 2245 2246 printf("pccbb_pcmcia_wait_ready: ready never happened, status=%02x\n", stat); 2247 return (EWOULDBLOCK); 2248 } 2249 2250 /* 2251 * Perform long (msec order) delay. timo is in milliseconds. 2252 */ 2253 static void 2254 pccbb_pcmcia_delay(struct pccbb_softc *sc, int timo, const char *wmesg) 2255 { 2256 #ifdef DIAGNOSTIC 2257 if (timo <= 0) 2258 panic("pccbb_pcmcia_delay: called with timeout %d", timo); 2259 if (!curlwp) 2260 panic("pccbb_pcmcia_delay: called in interrupt context"); 2261 #endif 2262 DPRINTF(("pccbb_pcmcia_delay: \"%s\", sleep %d ms\n", wmesg, timo)); 2263 kpause(wmesg, false, max(mstohz(timo), 1), NULL); 2264 } 2265 2266 /* 2267 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2268 * 2269 * This function enables the card. All information is stored in 2270 * the first argument, pcmcia_chipset_handle_t. 2271 */ 2272 STATIC void 2273 pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2274 { 2275 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2276 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2277 pcireg_t spsr; 2278 int voltage; 2279 int win; 2280 u_int8_t power, intr; 2281 #ifdef DIAGNOSTIC 2282 int reg; 2283 #endif 2284 2285 /* this bit is mostly stolen from pcic_attach_card */ 2286 2287 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2288 2289 /* get card Vcc info */ 2290 spsr = 2291 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2292 CB_SOCKET_STAT); 2293 if (spsr & CB_SOCKET_STAT_5VCARD) { 2294 DPRINTF(("5V card\n")); 2295 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2296 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2297 DPRINTF(("3V card\n")); 2298 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2299 } else { 2300 DPRINTF(("?V card, 0x%x\n", spsr)); /* XXX */ 2301 return; 2302 } 2303 2304 /* disable interrupts; assert RESET */ 2305 intr = Pcic_read(sc, PCIC_INTR); 2306 intr &= PCIC_INTR_ENABLE; 2307 Pcic_write(sc, PCIC_INTR, intr); 2308 2309 /* zero out the address windows */ 2310 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, 0); 2311 2312 /* power down the socket to reset it, clear the card reset pin */ 2313 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2314 2315 /* power off; assert output enable bit */ 2316 power = PCIC_PWRCTL_OE; 2317 Pcic_write(sc, PCIC_PWRCTL, power); 2318 2319 /* power up the socket */ 2320 if (pccbb_power(sc, voltage) == 0) 2321 return; 2322 2323 /* 2324 * Table 4-18 and figure 4-6 of the PC Card specifiction say: 2325 * Vcc Rising Time (Tpr) = 100ms (handled in pccbb_power() above) 2326 * RESET Width (Th (Hi-z RESET)) = 1ms 2327 * RESET Width (Tw (RESET)) = 10us 2328 * 2329 * some machines require some more time to be settled 2330 * for example old toshiba topic bridges! 2331 * (100ms is added here). 2332 */ 2333 pccbb_pcmcia_delay(sc, 200 + 1, "pccen1"); 2334 2335 /* negate RESET */ 2336 intr |= PCIC_INTR_RESET; 2337 Pcic_write(sc, PCIC_INTR, intr); 2338 2339 /* 2340 * RESET Setup Time (Tsu (RESET)) = 20ms 2341 */ 2342 pccbb_pcmcia_delay(sc, 20, "pccen2"); 2343 2344 #ifdef DIAGNOSTIC 2345 reg = Pcic_read(sc, PCIC_IF_STATUS); 2346 if ((reg & PCIC_IF_STATUS_POWERACTIVE) == 0) 2347 printf("pccbb_pcmcia_socket_enable: no power, status=%x\n", reg); 2348 #endif 2349 2350 /* wait for the chip to finish initializing */ 2351 if (pccbb_pcmcia_wait_ready(sc)) { 2352 #ifdef DIAGNOSTIC 2353 printf("pccbb_pcmcia_socket_enable: never became ready\n"); 2354 #endif 2355 /* XXX return a failure status?? */ 2356 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2357 Pcic_write(sc, PCIC_PWRCTL, 0); 2358 return; 2359 } 2360 2361 /* reinstall all the memory and io mappings */ 2362 for (win = 0; win < PCIC_MEM_WINS; ++win) 2363 if (ph->memalloc & (1 << win)) 2364 pccbb_pcmcia_do_mem_map(sc, win); 2365 for (win = 0; win < PCIC_IO_WINS; ++win) 2366 if (ph->ioalloc & (1 << win)) 2367 pccbb_pcmcia_do_io_map(sc, win); 2368 } 2369 2370 /* 2371 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2372 * 2373 * This function disables the card. All information is stored in 2374 * the first argument, pcmcia_chipset_handle_t. 2375 */ 2376 STATIC void 2377 pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t pch) 2378 { 2379 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2380 u_int8_t intr; 2381 2382 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2383 2384 /* disable interrupts; assert RESET */ 2385 intr = Pcic_read(sc, PCIC_INTR); 2386 intr &= PCIC_INTR_ENABLE; 2387 Pcic_write(sc, PCIC_INTR, intr); 2388 2389 /* zero out the address windows */ 2390 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, 0); 2391 2392 /* power down the socket to reset it, clear the card reset pin */ 2393 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2394 2395 /* disable socket: negate output enable bit and power off */ 2396 Pcic_write(sc, PCIC_PWRCTL, 0); 2397 2398 /* 2399 * Vcc Falling Time (Tpf) = 300ms 2400 */ 2401 pccbb_pcmcia_delay(sc, 300, "pccwr1"); 2402 } 2403 2404 STATIC void 2405 pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t pch, int type) 2406 { 2407 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2408 u_int8_t intr; 2409 2410 /* set the card type */ 2411 2412 intr = Pcic_read(sc, PCIC_INTR); 2413 intr &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_CARDTYPE_MASK); 2414 if (type == PCMCIA_IFTYPE_IO) 2415 intr |= PCIC_INTR_CARDTYPE_IO; 2416 else 2417 intr |= PCIC_INTR_CARDTYPE_MEM; 2418 Pcic_write(sc, PCIC_INTR, intr); 2419 2420 DPRINTF(("%s: pccbb_pcmcia_socket_settype type %s %02x\n", 2421 device_xname(sc->sc_dev), 2422 ((type == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2423 } 2424 2425 /* 2426 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2427 * 2428 * This function detects whether a card is in the slot or not. 2429 * If a card is inserted, return 1. Otherwise, return 0. 2430 */ 2431 STATIC int 2432 pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch) 2433 { 2434 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2435 2436 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2437 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2438 } 2439 2440 #if 0 2441 STATIC int 2442 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2443 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2444 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2445 #endif 2446 /* 2447 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2448 * bus_size_t size, 2449 * struct pcmcia_mem_handle *pcmhp) 2450 * 2451 * This function only allocates memory region for pccard. This 2452 * function never maps the allocated region to pccard memory area. 2453 * 2454 * XXX: Why the argument of start address is not in? 2455 */ 2456 STATIC int 2457 pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 2458 struct pcmcia_mem_handle *pcmhp) 2459 { 2460 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2461 bus_space_handle_t memh; 2462 bus_addr_t addr; 2463 bus_size_t sizepg; 2464 #if rbus 2465 rbus_tag_t rb; 2466 #endif 2467 2468 /* Check that the card is still there. */ 2469 if ((Pcic_read(sc, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2470 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2471 return 1; 2472 2473 /* out of sc->memh, allocate as many pages as necessary */ 2474 2475 /* convert size to PCIC pages */ 2476 /* 2477 * This is not enough; when the requested region is on the page 2478 * boundaries, this may calculate wrong result. 2479 */ 2480 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2481 #if 0 2482 if (sizepg > PCIC_MAX_MEM_PAGES) { 2483 return 1; 2484 } 2485 #endif 2486 2487 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2488 return 1; 2489 } 2490 2491 addr = 0; /* XXX gcc -Wuninitialized */ 2492 2493 #if rbus 2494 rb = sc->sc_rbus_memt; 2495 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2496 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2497 &addr, &memh)) { 2498 return 1; 2499 } 2500 #else 2501 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2502 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2503 0, /* boundary */ 2504 0, /* flags */ 2505 &addr, &memh)) { 2506 return 1; 2507 } 2508 #endif 2509 2510 DPRINTF(("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, " 2511 "realsize 0x%lx\n", (unsigned long)addr, (unsigned long)size, 2512 (unsigned long)sizepg * PCIC_MEM_PAGESIZE)); 2513 2514 pcmhp->memt = sc->sc_memt; 2515 pcmhp->memh = memh; 2516 pcmhp->addr = addr; 2517 pcmhp->size = size; 2518 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2519 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2520 pcmhp->mhandle = 0; 2521 /* No offset??? Funny. */ 2522 2523 return 0; 2524 } 2525 2526 /* 2527 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2528 * struct pcmcia_mem_handle *pcmhp) 2529 * 2530 * This function release the memory space allocated by the function 2531 * pccbb_pcmcia_mem_alloc(). 2532 */ 2533 STATIC void 2534 pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2535 struct pcmcia_mem_handle *pcmhp) 2536 { 2537 #if rbus 2538 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2539 2540 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2541 #else 2542 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2543 #endif 2544 } 2545 2546 /* 2547 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2548 * 2549 * This function release the memory space allocated by the function 2550 * pccbb_pcmcia_mem_alloc(). 2551 */ 2552 STATIC void 2553 pccbb_pcmcia_do_mem_map(struct pccbb_softc *sc, int win) 2554 { 2555 int regbase_win; 2556 bus_addr_t phys_addr; 2557 bus_addr_t phys_end; 2558 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2559 2560 #define PCIC_SMM_START_LOW 0 2561 #define PCIC_SMM_START_HIGH 1 2562 #define PCIC_SMM_STOP_LOW 2 2563 #define PCIC_SMM_STOP_HIGH 3 2564 #define PCIC_CMA_LOW 4 2565 #define PCIC_CMA_HIGH 5 2566 2567 u_int8_t start_low, start_high = 0; 2568 u_int8_t stop_low, stop_high; 2569 u_int8_t off_low, off_high; 2570 u_int8_t mem_window; 2571 int reg; 2572 2573 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2574 int mem8 = 2575 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2576 || (kind == PCMCIA_MEM_ATTR); 2577 2578 regbase_win = 0x10 + win * 0x08; 2579 2580 phys_addr = ph->mem[win].addr; 2581 phys_end = phys_addr + ph->mem[win].size; 2582 2583 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2584 (unsigned long)phys_addr, (unsigned long)phys_end, 2585 (unsigned long)ph->mem[win].offset)); 2586 2587 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2588 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2589 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2590 2591 /* bit 19:12 */ 2592 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2593 /* bit 23:20 and bit 7 on */ 2594 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2595 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2596 /* bit 31:24, for 32-bit address */ 2597 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2598 2599 Pcic_write(sc, regbase_win + PCIC_SMM_START_LOW, start_low); 2600 Pcic_write(sc, regbase_win + PCIC_SMM_START_HIGH, start_high); 2601 2602 if (sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2603 Pcic_write(sc, 0x40 + win, mem_window); 2604 } 2605 2606 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2607 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2608 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2609 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2610 2611 Pcic_write(sc, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2612 Pcic_write(sc, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2613 2614 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2615 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2616 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2617 | ((kind == PCMCIA_MEM_ATTR) ? 2618 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2619 2620 Pcic_write(sc, regbase_win + PCIC_CMA_LOW, off_low); 2621 Pcic_write(sc, regbase_win + PCIC_CMA_HIGH, off_high); 2622 2623 reg = Pcic_read(sc, PCIC_ADDRWIN_ENABLE); 2624 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2625 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, reg); 2626 2627 #if defined(CBB_DEBUG) 2628 { 2629 int r1, r2, r3, r4, r5, r6, r7 = 0; 2630 2631 r1 = Pcic_read(sc, regbase_win + PCIC_SMM_START_LOW); 2632 r2 = Pcic_read(sc, regbase_win + PCIC_SMM_START_HIGH); 2633 r3 = Pcic_read(sc, regbase_win + PCIC_SMM_STOP_LOW); 2634 r4 = Pcic_read(sc, regbase_win + PCIC_SMM_STOP_HIGH); 2635 r5 = Pcic_read(sc, regbase_win + PCIC_CMA_LOW); 2636 r6 = Pcic_read(sc, regbase_win + PCIC_CMA_HIGH); 2637 if (sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2638 r7 = Pcic_read(sc, 0x40 + win); 2639 } 2640 2641 printf("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2642 "%02x%02x", win, r1, r2, r3, r4, r5, r6); 2643 if (sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2644 printf(" %02x", r7); 2645 } 2646 printf("\n"); 2647 } 2648 #endif 2649 } 2650 2651 /* 2652 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2653 * bus_addr_t card_addr, bus_size_t size, 2654 * struct pcmcia_mem_handle *pcmhp, 2655 * bus_addr_t *offsetp, int *windowp) 2656 * 2657 * This function maps memory space allocated by the function 2658 * pccbb_pcmcia_mem_alloc(). 2659 */ 2660 STATIC int 2661 pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2662 bus_addr_t card_addr, bus_size_t size, struct pcmcia_mem_handle *pcmhp, 2663 bus_size_t *offsetp, int *windowp) 2664 { 2665 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2666 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2667 bus_addr_t busaddr; 2668 long card_offset; 2669 int win; 2670 2671 /* Check that the card is still there. */ 2672 if ((Pcic_read(sc, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2673 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2674 return 1; 2675 2676 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2677 if ((ph->memalloc & (1 << win)) == 0) { 2678 ph->memalloc |= (1 << win); 2679 break; 2680 } 2681 } 2682 2683 if (win == PCIC_MEM_WINS) { 2684 return 1; 2685 } 2686 2687 *windowp = win; 2688 2689 /* XXX this is pretty gross */ 2690 2691 if (!bus_space_is_equal(sc->sc_memt, pcmhp->memt)) { 2692 panic("pccbb_pcmcia_mem_map memt is bogus"); 2693 } 2694 2695 busaddr = pcmhp->addr; 2696 2697 /* 2698 * compute the address offset to the pcmcia address space for the 2699 * pcic. this is intentionally signed. The masks and shifts below 2700 * will cause TRT to happen in the pcic registers. Deal with making 2701 * sure the address is aligned, and return the alignment offset. 2702 */ 2703 2704 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2705 card_addr -= *offsetp; 2706 2707 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2708 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2709 (u_long) card_addr)); 2710 2711 /* 2712 * include the offset in the size, and decrement size by one, since 2713 * the hw wants start/stop 2714 */ 2715 size += *offsetp - 1; 2716 2717 card_offset = (((long)card_addr) - ((long)busaddr)); 2718 2719 ph->mem[win].addr = busaddr; 2720 ph->mem[win].size = size; 2721 ph->mem[win].offset = card_offset; 2722 ph->mem[win].kind = kind; 2723 2724 pccbb_pcmcia_do_mem_map(sc, win); 2725 2726 return 0; 2727 } 2728 2729 /* 2730 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2731 * int window) 2732 * 2733 * This function unmaps memory space which mapped by the function 2734 * pccbb_pcmcia_mem_map(). 2735 */ 2736 STATIC void 2737 pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, int window) 2738 { 2739 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2740 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2741 int reg; 2742 2743 if (window >= PCIC_MEM_WINS) { 2744 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2745 } 2746 2747 reg = Pcic_read(sc, PCIC_ADDRWIN_ENABLE); 2748 reg &= ~(1 << window); 2749 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, reg); 2750 2751 ph->memalloc &= ~(1 << window); 2752 } 2753 2754 /* 2755 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2756 * struct pcmcia_function *pf, 2757 * int ipl, 2758 * int (*func)(void *), 2759 * void *arg); 2760 * 2761 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2762 */ 2763 STATIC void * 2764 pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2765 struct pcmcia_function *pf, int ipl, int (*func)(void *), void *arg) 2766 { 2767 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2768 2769 if (!(pf->cfe->flags & (PCMCIA_CFE_IRQLEVEL|PCMCIA_CFE_IRQPULSE))) { 2770 /* 2771 * XXX Noooooo! The interrupt flag must set properly!! 2772 * dumb pcmcia driver!! 2773 */ 2774 DPRINTF(("%s does not provide edge nor pulse interrupt\n", 2775 device_xname(sc->sc_dev))); 2776 return NULL; 2777 } 2778 2779 return pccbb_intr_establish(sc, ipl, func, arg); 2780 } 2781 2782 /* 2783 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2784 * void *ih) 2785 * 2786 * This function disables PC-Card interrupt. 2787 */ 2788 STATIC void 2789 pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 2790 { 2791 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2792 2793 pccbb_intr_disestablish(sc, ih); 2794 } 2795 2796 #if rbus 2797 /* 2798 * static int 2799 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2800 * bus_addr_t addr, bus_size_t size, 2801 * bus_addr_t mask, bus_size_t align, 2802 * int flags, bus_addr_t *addrp; 2803 * bus_space_handle_t *bshp) 2804 * 2805 * This function allocates a portion of memory or io space for 2806 * clients. This function is called from CardBus card drivers. 2807 */ 2808 static int 2809 pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2810 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 2811 int flags, bus_addr_t *addrp, bus_space_handle_t *bshp) 2812 { 2813 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2814 2815 DPRINTF(("pccbb_rbus_cb_space_alloc: addr 0x%lx, size 0x%lx, " 2816 "mask 0x%lx, align 0x%lx\n", (unsigned long)addr, 2817 (unsigned long)size, (unsigned long)mask, (unsigned long)align)); 2818 2819 if (align == 0) { 2820 align = size; 2821 } 2822 2823 if (bus_space_is_equal(rb->rb_bt, sc->sc_memt)) { 2824 if (align < 16) { 2825 return 1; 2826 } 2827 /* 2828 * XXX: align more than 0x1000 to avoid overwrapping 2829 * memory windows for two or more devices. 0x1000 2830 * means memory window's granularity. 2831 * 2832 * Two or more devices should be able to share same 2833 * memory window region. However, overrapping memory 2834 * window is not good because some devices, such as 2835 * 3Com 3C575[BC], have a broken address decoder and 2836 * intrude other's memory region. 2837 */ 2838 if (align < 0x1000) { 2839 align = 0x1000; 2840 } 2841 } else if (bus_space_is_equal(rb->rb_bt, sc->sc_iot)) { 2842 if (align < 4) { 2843 return 1; 2844 } 2845 /* XXX: hack for avoiding ISA image */ 2846 if (mask < 0x0100) { 2847 mask = 0x3ff; 2848 addr = 0x300; 2849 } 2850 2851 } else { 2852 DPRINTF(("pccbb_rbus_cb_space_alloc: Bus space tag 0x%lx is " 2853 "NOT used. io: 0x%lx, mem: 0x%lx\n", 2854 (unsigned long)rb->rb_bt, (unsigned long)sc->sc_iot, 2855 (unsigned long)sc->sc_memt)); 2856 return 1; 2857 /* XXX: panic here? */ 2858 } 2859 2860 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 2861 aprint_normal_dev(sc->sc_dev, "<rbus> no bus space\n"); 2862 return 1; 2863 } 2864 2865 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 2866 2867 return 0; 2868 } 2869 2870 /* 2871 * static int 2872 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 2873 * bus_space_handle_t *bshp, bus_size_t size); 2874 * 2875 * This function is called from CardBus card drivers. 2876 */ 2877 static int 2878 pccbb_rbus_cb_space_free(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2879 bus_space_handle_t bsh, bus_size_t size) 2880 { 2881 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2882 bus_space_tag_t bt = rb->rb_bt; 2883 2884 pccbb_close_win(sc, bt, bsh, size); 2885 2886 if (bus_space_is_equal(bt, sc->sc_memt)) { 2887 } else if (bus_space_is_equal(bt, sc->sc_iot)) { 2888 } else { 2889 return 1; 2890 /* XXX: panic here? */ 2891 } 2892 2893 return rbus_space_free(rb, bsh, size, NULL); 2894 } 2895 #endif /* rbus */ 2896 2897 #if rbus 2898 2899 static int 2900 pccbb_open_win(struct pccbb_softc *sc, bus_space_tag_t bst, bus_addr_t addr, 2901 bus_size_t size, bus_space_handle_t bsh, int flags) 2902 { 2903 struct pccbb_win_chain_head *head; 2904 bus_addr_t align; 2905 2906 head = &sc->sc_iowindow; 2907 align = 0x04; 2908 if (bus_space_is_equal(sc->sc_memt, bst)) { 2909 head = &sc->sc_memwindow; 2910 align = 0x1000; 2911 DPRINTF(("using memory window, 0x%lx 0x%lx 0x%lx\n\n", 2912 (unsigned long)sc->sc_iot, (unsigned long)sc->sc_memt, 2913 (unsigned long)bst)); 2914 } 2915 2916 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 2917 aprint_error_dev(sc->sc_dev, 2918 "pccbb_open_win: %s winlist insert failed\n", 2919 (head == &sc->sc_memwindow) ? "mem" : "io"); 2920 } 2921 pccbb_winset(align, sc, bst); 2922 2923 return 0; 2924 } 2925 2926 static int 2927 pccbb_close_win(struct pccbb_softc *sc, bus_space_tag_t bst, 2928 bus_space_handle_t bsh, bus_size_t size) 2929 { 2930 struct pccbb_win_chain_head *head; 2931 bus_addr_t align; 2932 2933 head = &sc->sc_iowindow; 2934 align = 0x04; 2935 if (bus_space_is_equal(sc->sc_memt, bst)) { 2936 head = &sc->sc_memwindow; 2937 align = 0x1000; 2938 } 2939 2940 if (pccbb_winlist_delete(head, bsh, size)) { 2941 aprint_error_dev(sc->sc_dev, 2942 "pccbb_close_win: %s winlist delete failed\n", 2943 (head == &sc->sc_memwindow) ? "mem" : "io"); 2944 } 2945 pccbb_winset(align, sc, bst); 2946 2947 return 0; 2948 } 2949 2950 static int 2951 pccbb_winlist_insert(struct pccbb_win_chain_head *head, bus_addr_t start, 2952 bus_size_t size, bus_space_handle_t bsh, int flags) 2953 { 2954 struct pccbb_win_chain *chainp, *elem; 2955 2956 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 2957 M_NOWAIT)) == NULL) 2958 return (1); /* fail */ 2959 2960 elem->wc_start = start; 2961 elem->wc_end = start + (size - 1); 2962 elem->wc_handle = bsh; 2963 elem->wc_flags = flags; 2964 2965 TAILQ_FOREACH(chainp, head, wc_list) { 2966 if (chainp->wc_end >= start) 2967 break; 2968 } 2969 if (chainp != NULL) 2970 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 2971 else 2972 TAILQ_INSERT_TAIL(head, elem, wc_list); 2973 return (0); 2974 } 2975 2976 static int 2977 pccbb_winlist_delete(struct pccbb_win_chain_head *head, bus_space_handle_t bsh, 2978 bus_size_t size) 2979 { 2980 struct pccbb_win_chain *chainp; 2981 2982 TAILQ_FOREACH(chainp, head, wc_list) { 2983 if (memcmp(&chainp->wc_handle, &bsh, sizeof(bsh)) == 0) 2984 break; 2985 } 2986 if (chainp == NULL) 2987 return 1; /* fail: no candidate to remove */ 2988 2989 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 2990 printf("pccbb_winlist_delete: window 0x%lx size " 2991 "inconsistent: 0x%lx, 0x%lx\n", 2992 (unsigned long)chainp->wc_start, 2993 (unsigned long)(chainp->wc_end - chainp->wc_start), 2994 (unsigned long)(size - 1)); 2995 return 1; 2996 } 2997 2998 TAILQ_REMOVE(head, chainp, wc_list); 2999 free(chainp, M_DEVBUF); 3000 3001 return 0; 3002 } 3003 3004 static void 3005 pccbb_winset(bus_addr_t align, struct pccbb_softc *sc, bus_space_tag_t bst) 3006 { 3007 pci_chipset_tag_t pc; 3008 pcitag_t tag; 3009 bus_addr_t mask = ~(align - 1); 3010 struct { 3011 pcireg_t win_start; 3012 pcireg_t win_limit; 3013 int win_flags; 3014 } win[2]; 3015 struct pccbb_win_chain *chainp; 3016 int offs; 3017 3018 win[0].win_start = win[1].win_start = 0xffffffff; 3019 win[0].win_limit = win[1].win_limit = 0; 3020 win[0].win_flags = win[1].win_flags = 0; 3021 3022 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3023 offs = PCI_CB_IOBASE0; 3024 if (bus_space_is_equal(sc->sc_memt, bst)) { 3025 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3026 offs = PCI_CB_MEMBASE0; 3027 } 3028 3029 if (chainp != NULL) { 3030 win[0].win_start = chainp->wc_start & mask; 3031 win[0].win_limit = chainp->wc_end & mask; 3032 win[0].win_flags = chainp->wc_flags; 3033 chainp = TAILQ_NEXT(chainp, wc_list); 3034 } 3035 3036 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3037 if (win[1].win_start == 0xffffffff) { 3038 /* window 1 is not used */ 3039 if ((win[0].win_flags == chainp->wc_flags) && 3040 (win[0].win_limit + align >= 3041 (chainp->wc_start & mask))) { 3042 /* concatenate */ 3043 win[0].win_limit = chainp->wc_end & mask; 3044 } else { 3045 /* make new window */ 3046 win[1].win_start = chainp->wc_start & mask; 3047 win[1].win_limit = chainp->wc_end & mask; 3048 win[1].win_flags = chainp->wc_flags; 3049 } 3050 continue; 3051 } 3052 3053 /* Both windows are engaged. */ 3054 if (win[0].win_flags == win[1].win_flags) { 3055 /* same flags */ 3056 if (win[0].win_flags == chainp->wc_flags) { 3057 if (win[1].win_start - (win[0].win_limit + 3058 align) < 3059 (chainp->wc_start & mask) - 3060 ((chainp->wc_end & mask) + align)) { 3061 /* 3062 * merge window 0 and 1, and set win1 3063 * to chainp 3064 */ 3065 win[0].win_limit = win[1].win_limit; 3066 win[1].win_start = 3067 chainp->wc_start & mask; 3068 win[1].win_limit = 3069 chainp->wc_end & mask; 3070 } else { 3071 win[1].win_limit = 3072 chainp->wc_end & mask; 3073 } 3074 } else { 3075 /* different flags */ 3076 3077 /* concatenate win0 and win1 */ 3078 win[0].win_limit = win[1].win_limit; 3079 /* allocate win[1] to new space */ 3080 win[1].win_start = chainp->wc_start & mask; 3081 win[1].win_limit = chainp->wc_end & mask; 3082 win[1].win_flags = chainp->wc_flags; 3083 } 3084 } else { 3085 /* the flags of win[0] and win[1] is different */ 3086 if (win[0].win_flags == chainp->wc_flags) { 3087 win[0].win_limit = chainp->wc_end & mask; 3088 /* 3089 * XXX this creates overlapping windows, so 3090 * what should the poor bridge do if one is 3091 * cachable, and the other is not? 3092 */ 3093 aprint_error_dev(sc->sc_dev, 3094 "overlapping windows\n"); 3095 } else { 3096 win[1].win_limit = chainp->wc_end & mask; 3097 } 3098 } 3099 } 3100 3101 pc = sc->sc_pc; 3102 tag = sc->sc_tag; 3103 pci_conf_write(pc, tag, offs, win[0].win_start); 3104 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3105 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3106 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3107 DPRINTF(("--pccbb_winset: win0 [0x%lx, 0x%lx), win1 [0x%lx, 0x%lx)\n", 3108 (unsigned long)pci_conf_read(pc, tag, offs), 3109 (unsigned long)pci_conf_read(pc, tag, offs + 4) + align, 3110 (unsigned long)pci_conf_read(pc, tag, offs + 8), 3111 (unsigned long)pci_conf_read(pc, tag, offs + 12) + align)); 3112 3113 if (bus_space_is_equal(bst, sc->sc_memt)) { 3114 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BRIDGE_CONTROL_REG); 3115 3116 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 3117 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 3118 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3119 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 3120 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3121 pci_conf_write(pc, tag, PCI_BRIDGE_CONTROL_REG, bcr); 3122 } 3123 } 3124 3125 #endif /* rbus */ 3126 3127 static bool 3128 pccbb_suspend(device_t dv, const pmf_qual_t *qual) 3129 { 3130 struct pccbb_softc *sc = device_private(dv); 3131 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3132 bus_space_handle_t base_memh = sc->sc_base_memh; 3133 pcireg_t reg; 3134 3135 if (sc->sc_pil_intr_enable) 3136 (void)pccbbintr_function(sc); 3137 sc->sc_pil_intr_enable = false; 3138 3139 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3140 /* Disable interrupts. */ 3141 reg &= ~(CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER); 3142 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3143 /* XXX joerg Disable power to the socket? */ 3144 3145 /* XXX flush PCI write */ 3146 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3147 3148 /* reset interrupt */ 3149 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, 3150 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT)); 3151 /* XXX flush PCI write */ 3152 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3153 3154 if (sc->sc_ih != NULL) { 3155 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 3156 sc->sc_ih = NULL; 3157 } 3158 3159 return true; 3160 } 3161 3162 static bool 3163 pccbb_resume(device_t dv, const pmf_qual_t *qual) 3164 { 3165 struct pccbb_softc *sc = device_private(dv); 3166 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3167 bus_space_handle_t base_memh = sc->sc_base_memh; 3168 pcireg_t reg; 3169 3170 pccbb_chipinit(sc); 3171 pccbb_intrinit(sc); 3172 /* setup memory and io space window for CB */ 3173 pccbb_winset(0x1000, sc, sc->sc_memt); 3174 pccbb_winset(0x04, sc, sc->sc_iot); 3175 3176 /* CSC Interrupt: Card detect interrupt on */ 3177 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3178 /* Card detect intr is turned on. */ 3179 reg |= CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; 3180 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3181 /* reset interrupt */ 3182 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3183 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3184 3185 /* 3186 * check for card insertion or removal during suspend period. 3187 * XXX: the code can't cope with card swap (remove then 3188 * insert). how can we detect such situation? 3189 */ 3190 (void)pccbbintr(sc); 3191 3192 sc->sc_pil_intr_enable = true; 3193 3194 return true; 3195 } 3196
Indexes created Fri Sep 26 08:10:20 GMT 2025