pccbb.c revision 1.211
1 /* $NetBSD: pccbb.c,v 1.211 2017/05/10 02:46:33 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: pccbb.c,v 1.211 2017/05/10 02:46:33 msaitoh Exp $"); 30 31 /* 32 #define CBB_DEBUG 33 #define SHOW_REGS 34 */ 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/kernel.h> 39 #include <sys/errno.h> 40 #include <sys/ioctl.h> 41 #include <sys/reboot.h> /* for bootverbose */ 42 #include <sys/syslog.h> 43 #include <sys/device.h> 44 #include <sys/malloc.h> 45 #include <sys/proc.h> 46 47 #include <sys/intr.h> 48 #include <sys/bus.h> 49 50 #include <dev/pci/pcivar.h> 51 #include <dev/pci/pcireg.h> 52 #include <dev/pci/pcidevs.h> 53 54 #include <dev/pci/pccbbreg.h> 55 56 #include <dev/cardbus/cardslotvar.h> 57 58 #include <dev/cardbus/cardbusvar.h> 59 60 #include <dev/pcmcia/pcmciareg.h> 61 #include <dev/pcmcia/pcmciavar.h> 62 63 #include <dev/ic/i82365reg.h> 64 #include <dev/pci/pccbbvar.h> 65 66 #ifndef __NetBSD_Version__ 67 struct cfdriver cbb_cd = { 68 NULL, "cbb", DV_DULL 69 }; 70 #endif 71 72 #ifdef CBB_DEBUG 73 #define DPRINTF(x) printf x 74 #define STATIC 75 #else 76 #define DPRINTF(x) 77 #define STATIC static 78 #endif 79 80 int pccbb_burstup = 1; 81 82 /* 83 * delay_ms() is wait in milliseconds. It should be used instead 84 * of delay() if you want to wait more than 1 ms. 85 */ 86 static inline void 87 delay_ms(int millis, struct pccbb_softc *sc) 88 { 89 if (cold) 90 delay(millis * 1000); 91 else 92 kpause("pccbb", false, mstohz(millis), NULL); 93 } 94 95 int pcicbbmatch(device_t, cfdata_t, void *); 96 void pccbbattach(device_t, device_t, void *); 97 void pccbbchilddet(device_t, device_t); 98 int pccbbdetach(device_t, int); 99 int pccbbintr(void *); 100 static void pci113x_insert(void *); 101 static int pccbbintr_function(struct pccbb_softc *); 102 103 static int pccbb_detect_card(struct pccbb_softc *); 104 105 static void pccbb_pcmcia_write(struct pccbb_softc *, int, u_int8_t); 106 static u_int8_t pccbb_pcmcia_read(struct pccbb_softc *, int); 107 #define Pcic_read(sc, reg) pccbb_pcmcia_read((sc), (reg)) 108 #define Pcic_write(sc, reg, val) pccbb_pcmcia_write((sc), (reg), (val)) 109 110 STATIC int cb_reset(struct pccbb_softc *); 111 STATIC int cb_detect_voltage(struct pccbb_softc *); 112 STATIC int cbbprint(void *, const char *); 113 114 static int cb_chipset(u_int32_t, int *); 115 STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *, 116 struct pcmciabus_attach_args *); 117 118 STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int); 119 STATIC int pccbb_power(struct pccbb_softc *sc, int); 120 STATIC int pccbb_power_ct(cardbus_chipset_tag_t, int); 121 STATIC int pccbb_cardenable(struct pccbb_softc * sc, int function); 122 static void *pccbb_intr_establish(struct pccbb_softc *, 123 int level, int (*ih) (void *), void *sc); 124 static void pccbb_intr_disestablish(struct pccbb_softc *, void *ih); 125 126 static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t, 127 int level, int (*ih) (void *), void *sc); 128 static void pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih); 129 130 static pcitag_t pccbb_make_tag(cardbus_chipset_tag_t, int, int); 131 static pcireg_t pccbb_conf_read(cardbus_chipset_tag_t, pcitag_t, int); 132 static void pccbb_conf_write(cardbus_chipset_tag_t, pcitag_t, int, 133 pcireg_t); 134 static void pccbb_chipinit(struct pccbb_softc *); 135 static void pccbb_intrinit(struct pccbb_softc *); 136 137 STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 138 struct pcmcia_mem_handle *); 139 STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t, 140 struct pcmcia_mem_handle *); 141 STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 142 bus_size_t, struct pcmcia_mem_handle *, bus_size_t *, int *); 143 STATIC void pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t, int); 144 STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 145 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 146 STATIC void pccbb_pcmcia_io_free(pcmcia_chipset_handle_t, 147 struct pcmcia_io_handle *); 148 STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 149 bus_size_t, struct pcmcia_io_handle *, int *); 150 STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t, int); 151 STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t, 152 struct pcmcia_function *, int, int (*)(void *), void *); 153 STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t, void *); 154 STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t); 155 STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t); 156 STATIC void pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t, int); 157 STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch); 158 159 static int pccbb_pcmcia_wait_ready(struct pccbb_softc *); 160 static void pccbb_pcmcia_delay(struct pccbb_softc *, int, const char *); 161 162 static void pccbb_pcmcia_do_io_map(struct pccbb_softc *, int); 163 static void pccbb_pcmcia_do_mem_map(struct pccbb_softc *, int); 164 165 /* bus-space allocation and deallocation functions */ 166 167 static int pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t, rbus_tag_t, 168 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 169 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp); 170 static int pccbb_rbus_cb_space_free(cardbus_chipset_tag_t, rbus_tag_t, 171 bus_space_handle_t, bus_size_t); 172 173 174 175 static int pccbb_open_win(struct pccbb_softc *, bus_space_tag_t, 176 bus_addr_t, bus_size_t, bus_space_handle_t, int flags); 177 static int pccbb_close_win(struct pccbb_softc *, bus_space_tag_t, 178 bus_space_handle_t, bus_size_t); 179 static int pccbb_winlist_insert(struct pccbb_win_chain_head *, bus_addr_t, 180 bus_size_t, bus_space_handle_t, int); 181 static int pccbb_winlist_delete(struct pccbb_win_chain_head *, 182 bus_space_handle_t, bus_size_t); 183 static void pccbb_winset(bus_addr_t align, struct pccbb_softc *, 184 bus_space_tag_t); 185 void pccbb_winlist_show(struct pccbb_win_chain *); 186 187 188 /* for config_defer */ 189 static void pccbb_pci_callback(device_t); 190 191 static bool pccbb_suspend(device_t, const pmf_qual_t *); 192 static bool pccbb_resume(device_t, const pmf_qual_t *); 193 194 #if defined SHOW_REGS 195 static void cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, 196 bus_space_tag_t memt, bus_space_handle_t memh); 197 #endif 198 199 CFATTACH_DECL3_NEW(cbb_pci, sizeof(struct pccbb_softc), 200 pcicbbmatch, pccbbattach, pccbbdetach, NULL, NULL, pccbbchilddet, 201 DVF_DETACH_SHUTDOWN); 202 203 static const struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 204 pccbb_pcmcia_mem_alloc, 205 pccbb_pcmcia_mem_free, 206 pccbb_pcmcia_mem_map, 207 pccbb_pcmcia_mem_unmap, 208 pccbb_pcmcia_io_alloc, 209 pccbb_pcmcia_io_free, 210 pccbb_pcmcia_io_map, 211 pccbb_pcmcia_io_unmap, 212 pccbb_pcmcia_intr_establish, 213 pccbb_pcmcia_intr_disestablish, 214 pccbb_pcmcia_socket_enable, 215 pccbb_pcmcia_socket_disable, 216 pccbb_pcmcia_socket_settype, 217 pccbb_pcmcia_card_detect 218 }; 219 220 static const struct cardbus_functions pccbb_funcs = { 221 pccbb_rbus_cb_space_alloc, 222 pccbb_rbus_cb_space_free, 223 pccbb_cb_intr_establish, 224 pccbb_cb_intr_disestablish, 225 pccbb_ctrl, 226 pccbb_power_ct, 227 pccbb_make_tag, 228 pccbb_conf_read, 229 pccbb_conf_write, 230 }; 231 232 int 233 pcicbbmatch(device_t parent, cfdata_t match, void *aux) 234 { 235 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 236 237 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 238 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 239 PCI_INTERFACE(pa->pa_class) == 0) { 240 return 1; 241 } 242 243 return 0; 244 } 245 246 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 247 | ((prod) << PCI_PRODUCT_SHIFT)) 248 249 const struct yenta_chipinfo { 250 pcireg_t yc_id; /* vendor tag | product tag */ 251 int yc_chiptype; 252 int yc_flags; 253 } yc_chipsets[] = { 254 /* Texas Instruments chips */ 255 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 256 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 257 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 258 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 259 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI125X, 260 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 261 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 262 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 263 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 264 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 265 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 266 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 267 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI125X, 268 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 269 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI125X, 270 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 271 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 272 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 273 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 274 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 275 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI1420, 276 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 277 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI125X, 278 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 279 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 280 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 281 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1510), CB_TI12XX, 282 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 283 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1520), CB_TI12XX, 284 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 285 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4410YENTA), CB_TI12XX, 286 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 287 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4520YENTA), CB_TI12XX, 288 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 289 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI7420YENTA), CB_TI12XX, 290 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 291 292 /* Ricoh chips */ 293 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 294 PCCBB_PCMCIA_MEM_32}, 295 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 296 PCCBB_PCMCIA_MEM_32}, 297 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 298 PCCBB_PCMCIA_MEM_32}, 299 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 300 PCCBB_PCMCIA_MEM_32}, 301 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 302 PCCBB_PCMCIA_MEM_32}, 303 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 304 PCCBB_PCMCIA_MEM_32}, 305 306 /* Toshiba products */ 307 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 308 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 309 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 310 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 311 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 312 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 313 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 314 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 315 316 /* Cirrus Logic products */ 317 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 318 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 319 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 320 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 321 322 /* O2 Micro products */ 323 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6729), 324 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 325 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6730), 326 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 327 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6832), 328 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 329 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6836), 330 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 331 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6872), 332 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 333 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6922), 334 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 335 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6933), 336 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 337 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6972), 338 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 339 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_7223), 340 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 341 342 /* sentinel, or Generic chip */ 343 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 344 }; 345 346 static int 347 cb_chipset(u_int32_t pci_id, int *flagp) 348 { 349 const struct yenta_chipinfo *yc; 350 351 /* Loop over except the last default entry. */ 352 for (yc = yc_chipsets; yc < yc_chipsets + 353 __arraycount(yc_chipsets) - 1; yc++) 354 if (pci_id == yc->yc_id) 355 break; 356 357 if (flagp != NULL) 358 *flagp = yc->yc_flags; 359 360 return (yc->yc_chiptype); 361 } 362 363 void 364 pccbbchilddet(device_t self, device_t child) 365 { 366 struct pccbb_softc *sc = device_private(self); 367 int s; 368 369 KASSERT(sc->sc_csc == device_private(child)); 370 371 s = splbio(); 372 if (sc->sc_csc == device_private(child)) 373 sc->sc_csc = NULL; 374 splx(s); 375 } 376 377 void 378 pccbbattach(device_t parent, device_t self, void *aux) 379 { 380 struct pccbb_softc *sc = device_private(self); 381 struct pci_attach_args *pa = aux; 382 pci_chipset_tag_t pc = pa->pa_pc; 383 pcireg_t reg, sock_base; 384 bus_addr_t sockbase; 385 int flags; 386 387 #ifdef __HAVE_PCCBB_ATTACH_HOOK 388 pccbb_attach_hook(parent, self, pa); 389 #endif 390 391 sc->sc_dev = self; 392 393 mutex_init(&sc->sc_pwr_mtx, MUTEX_DEFAULT, IPL_BIO); 394 cv_init(&sc->sc_pwr_cv, "pccpwr"); 395 396 callout_init(&sc->sc_insert_ch, 0); 397 callout_setfunc(&sc->sc_insert_ch, pci113x_insert, sc); 398 399 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 400 401 pci_aprint_devinfo(pa, NULL); 402 DPRINTF(("(chipflags %x)", flags)); 403 404 TAILQ_INIT(&sc->sc_memwindow); 405 TAILQ_INIT(&sc->sc_iowindow); 406 407 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 408 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 409 410 #if 0 411 printf("pa->pa_memt: %08x vs rbus_mem->rb_bt: %08x\n", 412 pa->pa_memt, sc->sc_rbus_memt->rb_bt); 413 #endif 414 415 sc->sc_flags &= ~CBB_MEMHMAPPED; 416 417 /* 418 * MAP socket registers and ExCA registers on memory-space 419 * When no valid address is set on socket base registers (on pci 420 * config space), get it not polite way. 421 */ 422 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 423 424 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 425 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 426 /* The address must be valid. */ 427 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 428 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 429 &sc->sc_base_size)) { 430 aprint_error_dev(self, 431 "can't map socket base address 0x%lx\n", 432 (unsigned long)sock_base); 433 /* 434 * I think it's funny: socket base registers must be 435 * mapped on memory space, but ... 436 */ 437 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 438 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 439 &sc->sc_base_size)) { 440 aprint_error_dev(self, 441 "can't map socket base address" 442 " 0x%lx: io mode\n", 443 (unsigned long)sockbase); 444 /* give up... allocate reg space via rbus. */ 445 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 446 } else 447 sc->sc_flags |= CBB_MEMHMAPPED; 448 } else { 449 DPRINTF(("%s: socket base address 0x%lx\n", 450 device_xname(self), 451 (unsigned long)sockbase)); 452 sc->sc_flags |= CBB_MEMHMAPPED; 453 } 454 } 455 456 sc->sc_mem_start = 0; /* XXX */ 457 sc->sc_mem_end = 0xffffffff; /* XXX */ 458 459 /* pccbb_machdep.c end */ 460 461 #if defined CBB_DEBUG 462 { 463 static const char *intrname[] = { "NON", "A", "B", "C", "D" }; 464 aprint_debug_dev(self, "intrpin %s, intrtag %d\n", 465 intrname[pa->pa_intrpin], pa->pa_intrline); 466 } 467 #endif 468 469 /* setup softc */ 470 sc->sc_pc = pc; 471 sc->sc_iot = pa->pa_iot; 472 sc->sc_memt = pa->pa_memt; 473 sc->sc_dmat = pa->pa_dmat; 474 sc->sc_tag = pa->pa_tag; 475 476 memcpy(&sc->sc_pa, pa, sizeof(*pa)); 477 478 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 479 480 /* Disable legacy register mapping. */ 481 switch (sc->sc_chipset) { 482 case CB_RX5C46X: /* fallthrough */ 483 #if 0 484 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 485 case CB_RX5C47X: 486 #endif 487 /* 488 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 489 * cannot be disabled by substituting 0 into PCI_LEGACY 490 * register. Ricoh CardBus bridges have special bits on Bridge 491 * control reg (addr 0x3e on PCI config space). 492 */ 493 reg = pci_conf_read(pc, pa->pa_tag, PCI_BRIDGE_CONTROL_REG); 494 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 495 pci_conf_write(pc, pa->pa_tag, PCI_BRIDGE_CONTROL_REG, reg); 496 break; 497 498 default: 499 /* XXX I don't know proper way to kill legacy I/O. */ 500 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 501 break; 502 } 503 504 if (!pmf_device_register(self, pccbb_suspend, pccbb_resume)) 505 aprint_error_dev(self, "couldn't establish power handler\n"); 506 507 config_defer(self, pccbb_pci_callback); 508 } 509 510 int 511 pccbbdetach(device_t self, int flags) 512 { 513 struct pccbb_softc *sc = device_private(self); 514 pci_chipset_tag_t pc = sc->sc_pa.pa_pc; 515 bus_space_tag_t bmt = sc->sc_base_memt; 516 bus_space_handle_t bmh = sc->sc_base_memh; 517 uint32_t sockmask; 518 int rc; 519 520 if ((rc = config_detach_children(self, flags)) != 0) 521 return rc; 522 523 if (!LIST_EMPTY(&sc->sc_pil)) { 524 panic("%s: interrupt handlers still registered", 525 device_xname(self)); 526 return EBUSY; 527 } 528 529 if (sc->sc_ih != NULL) { 530 pci_intr_disestablish(pc, sc->sc_ih); 531 sc->sc_ih = NULL; 532 } 533 534 /* CSC Interrupt: turn off card detect and power cycle interrupts */ 535 sockmask = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 536 sockmask &= ~(CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | 537 CB_SOCKET_MASK_POWER); 538 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, sockmask); 539 /* reset interrupt */ 540 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 541 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 542 543 switch (sc->sc_flags & (CBB_MEMHMAPPED|CBB_SPECMAPPED)) { 544 case CBB_MEMHMAPPED: 545 bus_space_unmap(bmt, bmh, sc->sc_base_size); 546 break; 547 case CBB_MEMHMAPPED|CBB_SPECMAPPED: 548 #if rbus 549 { 550 rbus_space_free(sc->sc_rbus_memt, bmh, 0x1000, 551 NULL); 552 } 553 #else 554 bus_space_free(bmt, bmh, 0x1000); 555 #endif 556 } 557 sc->sc_flags &= ~(CBB_MEMHMAPPED|CBB_SPECMAPPED); 558 559 if (!TAILQ_EMPTY(&sc->sc_iowindow)) 560 aprint_error_dev(self, "i/o windows not empty\n"); 561 if (!TAILQ_EMPTY(&sc->sc_memwindow)) 562 aprint_error_dev(self, "memory windows not empty\n"); 563 564 callout_halt(&sc->sc_insert_ch, NULL); 565 callout_destroy(&sc->sc_insert_ch); 566 567 mutex_destroy(&sc->sc_pwr_mtx); 568 cv_destroy(&sc->sc_pwr_cv); 569 570 return 0; 571 } 572 573 /* 574 * static void pccbb_pci_callback(device_t self) 575 * 576 * The actual attach routine: get memory space for YENTA register 577 * space, setup YENTA register and route interrupt. 578 * 579 * This function should be deferred because this device may obtain 580 * memory space dynamically. This function must avoid obtaining 581 * memory area which has already kept for another device. 582 */ 583 static void 584 pccbb_pci_callback(device_t self) 585 { 586 struct pccbb_softc *sc = device_private(self); 587 pci_chipset_tag_t pc = sc->sc_pc; 588 bus_addr_t sockbase; 589 struct cbslot_attach_args cba; 590 struct pcmciabus_attach_args paa; 591 struct cardslot_attach_args caa; 592 device_t csc; 593 594 if (!(sc->sc_flags & CBB_MEMHMAPPED)) { 595 /* The socket registers aren't mapped correctly. */ 596 #if rbus 597 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 598 (sc->sc_chipset == CB_RX5C47X 599 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 600 0, &sockbase, &sc->sc_base_memh)) { 601 return; 602 } 603 sc->sc_base_memt = sc->sc_memt; 604 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 605 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 606 device_xname(self), (unsigned long)sockbase, 607 (unsigned long)pci_conf_read(pc, sc->sc_tag, 608 PCI_SOCKBASE))); 609 #else 610 sc->sc_base_memt = sc->sc_memt; 611 #if !defined CBB_PCI_BASE 612 #define CBB_PCI_BASE 0x20000000 613 #endif 614 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 615 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 616 /* cannot allocate memory space */ 617 return; 618 } 619 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 620 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 621 device_xname(self), (unsigned long)sock_base, 622 (unsigned long)pci_conf_read(pc, 623 sc->sc_tag, PCI_SOCKBASE))); 624 #endif 625 sc->sc_flags |= CBB_MEMHMAPPED|CBB_SPECMAPPED; 626 } 627 628 /* clear data structure for child device interrupt handlers */ 629 LIST_INIT(&sc->sc_pil); 630 631 /* bus bridge initialization */ 632 pccbb_chipinit(sc); 633 634 sc->sc_pil_intr_enable = true; 635 636 { 637 u_int32_t sockstat; 638 639 sockstat = bus_space_read_4(sc->sc_base_memt, 640 sc->sc_base_memh, CB_SOCKET_STAT); 641 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 642 sc->sc_flags |= CBB_CARDEXIST; 643 } 644 } 645 646 /* 647 * attach cardbus 648 */ 649 { 650 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 651 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 652 653 /* initialize cbslot_attach */ 654 cba.cba_iot = sc->sc_iot; 655 cba.cba_memt = sc->sc_memt; 656 cba.cba_dmat = sc->sc_dmat; 657 cba.cba_bus = (busreg >> 8) & 0x0ff; 658 cba.cba_cc = (void *)sc; 659 cba.cba_cf = &pccbb_funcs; 660 661 #if rbus 662 cba.cba_rbus_iot = sc->sc_rbus_iot; 663 cba.cba_rbus_memt = sc->sc_rbus_memt; 664 #endif 665 666 cba.cba_cacheline = PCI_CACHELINE(bhlc); 667 cba.cba_max_lattimer = PCI_LATTIMER(bhlc); 668 669 aprint_verbose_dev(self, 670 "cacheline 0x%x lattimer 0x%x\n", 671 cba.cba_cacheline, 672 cba.cba_max_lattimer); 673 aprint_verbose_dev(self, "bhlc 0x%x\n", bhlc); 674 #if defined SHOW_REGS 675 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 676 sc->sc_base_memh); 677 #endif 678 } 679 680 pccbb_pcmcia_attach_setup(sc, &paa); 681 caa.caa_cb_attach = NULL; 682 if (cba.cba_bus == 0) 683 aprint_error_dev(self, 684 "secondary bus number uninitialized; try PCI_BUS_FIXUP\n"); 685 else 686 caa.caa_cb_attach = &cba; 687 caa.caa_16_attach = &paa; 688 689 pccbb_intrinit(sc); 690 691 if (NULL != (csc = config_found_ia(self, "pcmciaslot", &caa, 692 cbbprint))) { 693 DPRINTF(("%s: found cardslot\n", __func__)); 694 sc->sc_csc = device_private(csc); 695 } 696 697 return; 698 } 699 700 701 702 703 704 /* 705 * static void pccbb_chipinit(struct pccbb_softc *sc) 706 * 707 * This function initialize YENTA chip registers listed below: 708 * 1) PCI command reg, 709 * 2) PCI and CardBus latency timer, 710 * 3) route PCI interrupt, 711 * 4) close all memory and io windows. 712 * 5) turn off bus power. 713 * 6) card detect and power cycle interrupts on. 714 * 7) clear interrupt 715 */ 716 static void 717 pccbb_chipinit(struct pccbb_softc *sc) 718 { 719 pci_chipset_tag_t pc = sc->sc_pc; 720 pcitag_t tag = sc->sc_tag; 721 bus_space_tag_t bmt = sc->sc_base_memt; 722 bus_space_handle_t bmh = sc->sc_base_memh; 723 pcireg_t bcr, bhlc, cbctl, csr, lscp, mfunc, mrburst, slotctl, sockctl, 724 sysctrl; 725 726 /* 727 * Set PCI command reg. 728 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 729 */ 730 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 731 /* I believe it is harmless. */ 732 csr |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 733 PCI_COMMAND_MASTER_ENABLE); 734 735 /* All O2 Micro chips have broken parity-error reporting 736 * until proven otherwise. The OZ6933 PCI-CardBus Bridge 737 * is known to have the defect---see PR kern/38698. 738 */ 739 if (sc->sc_chipset != CB_O2MICRO) 740 csr |= PCI_COMMAND_PARITY_ENABLE; 741 742 csr |= PCI_COMMAND_SERR_ENABLE; 743 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 744 745 /* 746 * Set CardBus latency timer. 747 */ 748 lscp = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 749 if (PCI_CB_LATENCY(lscp) < 0x20) { 750 lscp &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 751 lscp |= (0x20 << PCI_CB_LATENCY_SHIFT); 752 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, lscp); 753 } 754 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 755 PCI_CB_LATENCY(lscp), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 756 757 /* 758 * Set PCI latency timer. 759 */ 760 bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG); 761 if (PCI_LATTIMER(bhlc) < 0x10) { 762 bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 763 bhlc |= (0x10 << PCI_LATTIMER_SHIFT); 764 pci_conf_write(pc, tag, PCI_BHLC_REG, bhlc); 765 } 766 DPRINTF(("PCI latency timer 0x%x (%x)\n", 767 PCI_LATTIMER(bhlc), pci_conf_read(pc, tag, PCI_BHLC_REG))); 768 769 770 /* Route functional interrupts to PCI. */ 771 bcr = pci_conf_read(pc, tag, PCI_BRIDGE_CONTROL_REG); 772 bcr |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 773 bcr |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 774 /* assert reset */ 775 bcr |= PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT; 776 /* Set master abort mode to 1, forward SERR# from secondary 777 * to primary, and detect parity errors on secondary. 778 */ 779 bcr |= PCI_BRIDGE_CONTROL_MABRT << PCI_BRIDGE_CONTROL_SHIFT; 780 bcr |= PCI_BRIDGE_CONTROL_SERR << PCI_BRIDGE_CONTROL_SHIFT; 781 bcr |= PCI_BRIDGE_CONTROL_PERE << PCI_BRIDGE_CONTROL_SHIFT; 782 pci_conf_write(pc, tag, PCI_BRIDGE_CONTROL_REG, bcr); 783 784 switch (sc->sc_chipset) { 785 case CB_TI113X: 786 cbctl = pci_conf_read(pc, tag, PCI_CBCTRL); 787 /* This bit is shared, but may read as 0 on some chips, so set 788 it explicitly on both functions. */ 789 cbctl |= PCI113X_CBCTRL_PCI_IRQ_ENA; 790 /* CSC intr enable */ 791 cbctl |= PCI113X_CBCTRL_PCI_CSC; 792 /* functional intr prohibit | prohibit ISA routing */ 793 cbctl &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 794 pci_conf_write(pc, tag, PCI_CBCTRL, cbctl); 795 break; 796 797 case CB_TI1420: 798 sysctrl = pci_conf_read(pc, tag, PCI_SYSCTRL); 799 mrburst = pccbb_burstup 800 ? PCI1420_SYSCTRL_MRBURST : PCI1420_SYSCTRL_MRBURSTDN; 801 if ((sysctrl & PCI1420_SYSCTRL_MRBURST) == mrburst) { 802 printf("%s: %swrite bursts enabled\n", 803 device_xname(sc->sc_dev), 804 pccbb_burstup ? "read/" : ""); 805 } else if (pccbb_burstup) { 806 printf("%s: enabling read/write bursts\n", 807 device_xname(sc->sc_dev)); 808 sysctrl |= PCI1420_SYSCTRL_MRBURST; 809 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 810 } else { 811 printf("%s: disabling read bursts, " 812 "enabling write bursts\n", 813 device_xname(sc->sc_dev)); 814 sysctrl |= PCI1420_SYSCTRL_MRBURSTDN; 815 sysctrl &= ~PCI1420_SYSCTRL_MRBURSTUP; 816 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 817 } 818 /*FALLTHROUGH*/ 819 case CB_TI12XX: 820 /* 821 * Some TI 12xx (and [14][45]xx) based pci cards 822 * sometimes have issues with the MFUNC register not 823 * being initialized due to a bad EEPROM on board. 824 * Laptops that this matters on have this register 825 * properly initialized. 826 * 827 * The TI125X parts have a different register. 828 */ 829 mfunc = pci_conf_read(pc, tag, PCI12XX_MFUNC); 830 if ((mfunc & (PCI12XX_MFUNC_PIN0 | PCI12XX_MFUNC_PIN1)) == 0) { 831 /* Enable PCI interrupt /INTA */ 832 mfunc |= PCI12XX_MFUNC_PIN0_INTA; 833 834 /* XXX this is TI1520 only */ 835 if ((pci_conf_read(pc, tag, PCI_SYSCTRL) & 836 PCI12XX_SYSCTRL_INTRTIE) == 0) 837 /* Enable PCI interrupt /INTB */ 838 mfunc |= PCI12XX_MFUNC_PIN1_INTB; 839 840 pci_conf_write(pc, tag, PCI12XX_MFUNC, mfunc); 841 } 842 /* fallthrough */ 843 844 case CB_TI125X: 845 /* 846 * Disable zoom video. Some machines initialize this 847 * improperly and experience has shown that this helps 848 * prevent strange behavior. 849 */ 850 pci_conf_write(pc, tag, PCI12XX_MMCTRL, 0); 851 852 sysctrl = pci_conf_read(pc, tag, PCI_SYSCTRL); 853 sysctrl |= PCI12XX_SYSCTRL_VCCPROT; 854 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 855 cbctl = pci_conf_read(pc, tag, PCI_CBCTRL); 856 cbctl |= PCI12XX_CBCTRL_CSC; 857 pci_conf_write(pc, tag, PCI_CBCTRL, cbctl); 858 break; 859 860 case CB_TOPIC95B: 861 sockctl = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 862 sockctl |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 863 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, sockctl); 864 slotctl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 865 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 866 device_xname(sc->sc_dev), slotctl)); 867 slotctl |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 868 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 869 slotctl &= ~TOPIC_SLOT_CTRL_SWDETECT; 870 DPRINTF(("0x%x\n", slotctl)); 871 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slotctl); 872 break; 873 874 case CB_TOPIC97: 875 slotctl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 876 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 877 device_xname(sc->sc_dev), slotctl)); 878 slotctl |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 879 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 880 slotctl &= ~TOPIC_SLOT_CTRL_SWDETECT; 881 slotctl |= TOPIC97_SLOT_CTRL_PCIINT; 882 slotctl &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 883 DPRINTF(("0x%x\n", slotctl)); 884 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slotctl); 885 /* make sure to assert LV card support bits */ 886 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 887 0x800 + 0x3e, 888 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 889 0x800 + 0x3e) | 0x03); 890 break; 891 } 892 893 /* Close all memory and I/O windows. */ 894 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 895 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 896 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 897 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 898 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 899 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 900 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 901 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 902 903 /* reset 16-bit pcmcia bus */ 904 bus_space_write_1(bmt, bmh, 0x800 + PCIC_INTR, 905 bus_space_read_1(bmt, bmh, 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 906 907 /* turn off power */ 908 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 909 } 910 911 static void 912 pccbb_intrinit(struct pccbb_softc *sc) 913 { 914 pcireg_t sockmask; 915 const char *intrstr = NULL; 916 pci_intr_handle_t ih; 917 pci_chipset_tag_t pc = sc->sc_pc; 918 bus_space_tag_t bmt = sc->sc_base_memt; 919 bus_space_handle_t bmh = sc->sc_base_memh; 920 char intrbuf[PCI_INTRSTR_LEN]; 921 922 /* Map and establish the interrupt. */ 923 if (pci_intr_map(&sc->sc_pa, &ih)) { 924 aprint_error_dev(sc->sc_dev, "couldn't map interrupt\n"); 925 return; 926 } 927 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 928 929 /* 930 * XXX pccbbintr should be called under the priority lower 931 * than any other hard interrupts. 932 */ 933 KASSERT(sc->sc_ih == NULL); 934 sc->sc_ih = pci_intr_establish_xname(pc, ih, IPL_BIO, pccbbintr, sc, 935 device_xname(sc->sc_dev)); 936 937 if (sc->sc_ih == NULL) { 938 aprint_error_dev(sc->sc_dev, "couldn't establish interrupt"); 939 if (intrstr != NULL) 940 aprint_error(" at %s\n", intrstr); 941 else 942 aprint_error("\n"); 943 return; 944 } 945 946 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 947 948 /* CSC Interrupt: Card detect and power cycle interrupts on */ 949 sockmask = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 950 sockmask |= CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | 951 CB_SOCKET_MASK_POWER; 952 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, sockmask); 953 /* reset interrupt */ 954 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 955 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 956 } 957 958 /* 959 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 960 * struct pcmciabus_attach_args *paa) 961 * 962 * This function attaches 16-bit PCcard bus. 963 */ 964 STATIC void 965 pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 966 struct pcmciabus_attach_args *paa) 967 { 968 /* 969 * We need to do a few things here: 970 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 971 * setting the IRQ numbers to 0. 972 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 973 * routing of CSC interrupts (e.g. card removal) to PCI while in 974 * PCMCIA mode. We just leave this set all the time. 975 * 3) Enable card insertion/removal interrupts in case the chip also 976 * needs that while in PCMCIA mode. 977 * 4) Clear any pending CSC interrupt. 978 */ 979 Pcic_write(sc, PCIC_INTR, PCIC_INTR_ENABLE); 980 if (sc->sc_chipset == CB_TI113X) { 981 Pcic_write(sc, PCIC_CSC_INTR, 0); 982 } else { 983 Pcic_write(sc, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 984 Pcic_read(sc, PCIC_CSC); 985 } 986 987 /* initialize pcmcia bus attachment */ 988 paa->paa_busname = "pcmcia"; 989 paa->pct = &pccbb_pcmcia_funcs; 990 paa->pch = sc; 991 return; 992 } 993 994 /* 995 * int pccbbintr(arg) 996 * void *arg; 997 * This routine handles the interrupt from Yenta PCI-CardBus bridge 998 * itself. 999 */ 1000 int 1001 pccbbintr(void *arg) 1002 { 1003 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1004 struct cardslot_softc *csc; 1005 u_int32_t sockevent, sockstate; 1006 bus_space_tag_t memt = sc->sc_base_memt; 1007 bus_space_handle_t memh = sc->sc_base_memh; 1008 1009 if (!device_has_power(sc->sc_dev)) 1010 return 0; 1011 1012 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 1013 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 1014 Pcic_read(sc, PCIC_CSC); 1015 1016 if (sockevent != 0) { 1017 DPRINTF(("%s: enter sockevent %" PRIx32 "\n", 1018 __func__, sockevent)); 1019 } 1020 1021 /* XXX sockevent == CB_SOCKET_EVENT_CSTS|CB_SOCKET_EVENT_POWER 1022 * does occur in the wild. Check for a _POWER event before 1023 * possibly exiting because of an _CSTS event. 1024 */ 1025 if (sockevent & CB_SOCKET_EVENT_POWER) { 1026 DPRINTF(("Powercycling because of socket event\n")); 1027 /* XXX: Does not happen when attaching a 16-bit card */ 1028 mutex_enter(&sc->sc_pwr_mtx); 1029 sc->sc_pwrcycle++; 1030 cv_signal(&sc->sc_pwr_cv); 1031 mutex_exit(&sc->sc_pwr_mtx); 1032 } 1033 1034 /* Sometimes a change of CSTSCHG# accompanies the first 1035 * interrupt from an Atheros WLAN. That generates a 1036 * CB_SOCKET_EVENT_CSTS event on the bridge. The event 1037 * isn't interesting to pccbb(4), so we used to ignore the 1038 * interrupt. Now, let the child devices try to handle 1039 * the interrupt, instead. The Atheros NIC produces 1040 * interrupts more reliably, now: used to be that it would 1041 * only interrupt if the driver avoided powering down the 1042 * NIC's cardslot, and then the NIC would only work after 1043 * it was reset a second time. 1044 */ 1045 if (sockevent == 0 || 1046 (sockevent & ~(CB_SOCKET_EVENT_POWER|CB_SOCKET_EVENT_CD)) != 0) { 1047 /* This intr is not for me: it may be for my child devices. */ 1048 if (sc->sc_pil_intr_enable) { 1049 return pccbbintr_function(sc); 1050 } else { 1051 return 0; 1052 } 1053 } 1054 1055 if (sockevent & CB_SOCKET_EVENT_CD) { 1056 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1057 if (0x00 != (sockstate & CB_SOCKET_STAT_CD)) { 1058 /* A card should be removed. */ 1059 if (sc->sc_flags & CBB_CARDEXIST) { 1060 DPRINTF(("%s: 0x%08x", 1061 device_xname(sc->sc_dev), sockevent)); 1062 DPRINTF((" card removed, 0x%08x\n", sockstate)); 1063 sc->sc_flags &= ~CBB_CARDEXIST; 1064 if ((csc = sc->sc_csc) == NULL) 1065 ; 1066 else if (csc->sc_status & 1067 CARDSLOT_STATUS_CARD_16) { 1068 cardslot_event_throw(csc, 1069 CARDSLOT_EVENT_REMOVAL_16); 1070 } else if (csc->sc_status & 1071 CARDSLOT_STATUS_CARD_CB) { 1072 /* Cardbus intr removed */ 1073 cardslot_event_throw(csc, 1074 CARDSLOT_EVENT_REMOVAL_CB); 1075 } 1076 } else if (sc->sc_flags & CBB_INSERTING) { 1077 sc->sc_flags &= ~CBB_INSERTING; 1078 callout_stop(&sc->sc_insert_ch); 1079 } 1080 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 1081 /* 1082 * The pccbbintr may called from powerdown hook when 1083 * the system resumed, to detect the card 1084 * insertion/removal during suspension. 1085 */ 1086 (sc->sc_flags & CBB_CARDEXIST) == 0) { 1087 if (sc->sc_flags & CBB_INSERTING) { 1088 callout_stop(&sc->sc_insert_ch); 1089 } 1090 callout_schedule(&sc->sc_insert_ch, mstohz(200)); 1091 sc->sc_flags |= CBB_INSERTING; 1092 } 1093 } 1094 1095 return (1); 1096 } 1097 1098 /* 1099 * static int pccbbintr_function(struct pccbb_softc *sc) 1100 * 1101 * This function calls each interrupt handler registered at the 1102 * bridge. The interrupt handlers are called in registered order. 1103 */ 1104 static int 1105 pccbbintr_function(struct pccbb_softc *sc) 1106 { 1107 int retval = 0, val; 1108 struct pccbb_intrhand_list *pil; 1109 int s; 1110 1111 LIST_FOREACH(pil, &sc->sc_pil, pil_next) { 1112 s = splraiseipl(pil->pil_icookie); 1113 val = (*pil->pil_func)(pil->pil_arg); 1114 splx(s); 1115 1116 retval = retval == 1 ? 1 : 1117 retval == 0 ? val : val != 0 ? val : retval; 1118 } 1119 1120 return retval; 1121 } 1122 1123 static void 1124 pci113x_insert(void *arg) 1125 { 1126 struct pccbb_softc *sc = arg; 1127 struct cardslot_softc *csc; 1128 u_int32_t sockevent, sockstate; 1129 1130 if (!(sc->sc_flags & CBB_INSERTING)) { 1131 /* We add a card only under inserting state. */ 1132 return; 1133 } 1134 sc->sc_flags &= ~CBB_INSERTING; 1135 1136 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1137 CB_SOCKET_EVENT); 1138 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1139 CB_SOCKET_STAT); 1140 1141 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1142 #ifdef CBB_DEBUG 1143 DPRINTF(("%s: 0x%08x", device_xname(sc->sc_dev), sockevent)); 1144 #else 1145 __USE(sockevent); 1146 #endif 1147 1148 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1149 sc->sc_flags |= CBB_CARDEXIST; 1150 /* call pccard interrupt handler here */ 1151 if ((csc = sc->sc_csc) == NULL) 1152 ; 1153 else if (sockstate & CB_SOCKET_STAT_16BIT) { 1154 /* 16-bit card found */ 1155 cardslot_event_throw(csc, CARDSLOT_EVENT_INSERTION_16); 1156 } else if (sockstate & CB_SOCKET_STAT_CB) { 1157 /* cardbus card found */ 1158 cardslot_event_throw(csc, CARDSLOT_EVENT_INSERTION_CB); 1159 } else { 1160 /* who are you? */ 1161 } 1162 } else { 1163 callout_schedule(&sc->sc_insert_ch, mstohz(100)); 1164 } 1165 } 1166 1167 #define PCCBB_PCMCIA_OFFSET 0x800 1168 static u_int8_t 1169 pccbb_pcmcia_read(struct pccbb_softc *sc, int reg) 1170 { 1171 bus_space_barrier(sc->sc_base_memt, sc->sc_base_memh, 1172 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1173 1174 return bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 1175 PCCBB_PCMCIA_OFFSET + reg); 1176 } 1177 1178 static void 1179 pccbb_pcmcia_write(struct pccbb_softc *sc, int reg, u_int8_t val) 1180 { 1181 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 1182 PCCBB_PCMCIA_OFFSET + reg, val); 1183 1184 bus_space_barrier(sc->sc_base_memt, sc->sc_base_memh, 1185 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1186 } 1187 1188 /* 1189 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1190 */ 1191 STATIC int 1192 pccbb_ctrl(cardbus_chipset_tag_t ct, int command) 1193 { 1194 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1195 1196 switch (command) { 1197 case CARDBUS_CD: 1198 if (2 == pccbb_detect_card(sc)) { 1199 int retval = 0; 1200 int status = cb_detect_voltage(sc); 1201 if (PCCARD_VCC_5V & status) { 1202 retval |= CARDBUS_5V_CARD; 1203 } 1204 if (PCCARD_VCC_3V & status) { 1205 retval |= CARDBUS_3V_CARD; 1206 } 1207 if (PCCARD_VCC_XV & status) { 1208 retval |= CARDBUS_XV_CARD; 1209 } 1210 if (PCCARD_VCC_YV & status) { 1211 retval |= CARDBUS_YV_CARD; 1212 } 1213 return retval; 1214 } else { 1215 return 0; 1216 } 1217 case CARDBUS_RESET: 1218 return cb_reset(sc); 1219 case CARDBUS_IO_ENABLE: /* fallthrough */ 1220 case CARDBUS_IO_DISABLE: /* fallthrough */ 1221 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1222 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1223 case CARDBUS_BM_ENABLE: /* fallthrough */ 1224 case CARDBUS_BM_DISABLE: /* fallthrough */ 1225 /* XXX: I think we don't need to call this function below. */ 1226 return pccbb_cardenable(sc, command); 1227 } 1228 1229 return 0; 1230 } 1231 1232 STATIC int 1233 pccbb_power_ct(cardbus_chipset_tag_t ct, int command) 1234 { 1235 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1236 1237 return pccbb_power(sc, command); 1238 } 1239 1240 /* 1241 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1242 * This function returns true when it succeeds and returns false when 1243 * it fails. 1244 */ 1245 STATIC int 1246 pccbb_power(struct pccbb_softc *sc, int command) 1247 { 1248 u_int32_t status, osock_ctrl, sock_ctrl, reg_ctrl; 1249 bus_space_tag_t memt = sc->sc_base_memt; 1250 bus_space_handle_t memh = sc->sc_base_memh; 1251 int on = 0, pwrcycle, times; 1252 struct timeval before, after, diff; 1253 1254 DPRINTF(("pccbb_power: %s and %s [0x%x]\n", 1255 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1256 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1257 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1258 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1259 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1260 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1261 "UNKNOWN", 1262 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1263 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1264 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1265 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1266 "UNKNOWN", command)); 1267 1268 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1269 osock_ctrl = sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1270 1271 switch (command & CARDBUS_VCCMASK) { 1272 case CARDBUS_VCC_UC: 1273 break; 1274 case CARDBUS_VCC_5V: 1275 on++; 1276 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1277 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1278 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1279 } else { 1280 aprint_error_dev(sc->sc_dev, 1281 "BAD voltage request: no 5 V card\n"); 1282 return 0; 1283 } 1284 break; 1285 case CARDBUS_VCC_3V: 1286 on++; 1287 if (CB_SOCKET_STAT_3VCARD & status) { 1288 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1289 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1290 } else { 1291 aprint_error_dev(sc->sc_dev, 1292 "BAD voltage request: no 3.3 V card\n"); 1293 return 0; 1294 } 1295 break; 1296 case CARDBUS_VCC_0V: 1297 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1298 break; 1299 default: 1300 return 0; /* power NEVER changed */ 1301 } 1302 1303 switch (command & CARDBUS_VPPMASK) { 1304 case CARDBUS_VPP_UC: 1305 break; 1306 case CARDBUS_VPP_0V: 1307 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1308 break; 1309 case CARDBUS_VPP_VCC: 1310 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1311 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1312 break; 1313 case CARDBUS_VPP_12V: 1314 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1315 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1316 break; 1317 } 1318 aprint_debug_dev(sc->sc_dev, "osock_ctrl %#" PRIx32 1319 " sock_ctrl %#" PRIx32 "\n", osock_ctrl, sock_ctrl); 1320 1321 microtime(&before); 1322 mutex_enter(&sc->sc_pwr_mtx); 1323 pwrcycle = sc->sc_pwrcycle; 1324 1325 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1326 1327 /* 1328 * Wait as long as 200ms for a power-cycle interrupt. If 1329 * interrupts are enabled, but the socket has already 1330 * changed to the desired status, keep waiting for the 1331 * interrupt. "Consuming" the interrupt in this way keeps 1332 * the interrupt from prematurely waking some subsequent 1333 * pccbb_power call. 1334 * 1335 * XXX Not every bridge interrupts on the ->OFF transition. 1336 * XXX That's ok, we will time-out after 200ms. 1337 * 1338 * XXX The power cycle event will never happen when attaching 1339 * XXX a 16-bit card. That's ok, we will time-out after 1340 * XXX 200ms. 1341 */ 1342 for (times = 5; --times >= 0; ) { 1343 if (cold) 1344 DELAY(40 * 1000); 1345 else { 1346 (void)cv_timedwait(&sc->sc_pwr_cv, &sc->sc_pwr_mtx, 1347 mstohz(40)); 1348 if (pwrcycle == sc->sc_pwrcycle) 1349 continue; 1350 } 1351 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1352 if ((status & CB_SOCKET_STAT_PWRCYCLE) != 0 && on) 1353 break; 1354 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0 && !on) 1355 break; 1356 } 1357 mutex_exit(&sc->sc_pwr_mtx); 1358 microtime(&after); 1359 timersub(&after, &before, &diff); 1360 aprint_debug_dev(sc->sc_dev, "wait took%s %lld.%06lds\n", 1361 (on && times < 0) ? " too long" : "", (long long)diff.tv_sec, 1362 (long)diff.tv_usec); 1363 1364 /* 1365 * Ok, wait a bit longer for things to settle. 1366 */ 1367 if (on && sc->sc_chipset == CB_TOPIC95B) 1368 delay_ms(100, sc); 1369 1370 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1371 1372 if (on && sc->sc_chipset != CB_TOPIC95B) { 1373 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0) 1374 aprint_error_dev(sc->sc_dev, "power on failed?\n"); 1375 } 1376 1377 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1378 aprint_error_dev(sc->sc_dev, 1379 "bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1380 sock_ctrl, status); 1381 aprint_error_dev(sc->sc_dev, "disabling socket\n"); 1382 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1383 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1384 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1385 status &= ~CB_SOCKET_STAT_BADVCC; 1386 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, status); 1387 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1388 CB_SOCKET_STAT)); 1389 return 0; 1390 } 1391 1392 if (sc->sc_chipset == CB_TOPIC97) { 1393 reg_ctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL); 1394 reg_ctrl &= ~TOPIC97_REG_CTRL_TESTMODE; 1395 if ((command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V) 1396 reg_ctrl &= ~TOPIC97_REG_CTRL_CLKRUN_ENA; 1397 else 1398 reg_ctrl |= TOPIC97_REG_CTRL_CLKRUN_ENA; 1399 pci_conf_write(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL, reg_ctrl); 1400 } 1401 1402 return 1; /* power changed correctly */ 1403 } 1404 1405 /* 1406 * static int pccbb_detect_card(struct pccbb_softc *sc) 1407 * return value: 0 if no card exists. 1408 * 1 if 16-bit card exists. 1409 * 2 if cardbus card exists. 1410 */ 1411 static int 1412 pccbb_detect_card(struct pccbb_softc *sc) 1413 { 1414 bus_space_handle_t base_memh = sc->sc_base_memh; 1415 bus_space_tag_t base_memt = sc->sc_base_memt; 1416 u_int32_t sockstat = 1417 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1418 int retval = 0; 1419 1420 /* CD1 and CD2 asserted */ 1421 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1422 /* card must be present */ 1423 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1424 /* NOTACARD DEASSERTED */ 1425 if (CB_SOCKET_STAT_CB & sockstat) { 1426 /* CardBus mode */ 1427 retval = 2; 1428 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1429 /* 16-bit mode */ 1430 retval = 1; 1431 } 1432 } 1433 } 1434 return retval; 1435 } 1436 1437 /* 1438 * STATIC int cb_reset(struct pccbb_softc *sc) 1439 * This function resets CardBus card. 1440 */ 1441 STATIC int 1442 cb_reset(struct pccbb_softc *sc) 1443 { 1444 /* 1445 * Reset Assert at least 20 ms 1446 * Some machines request longer duration. 1447 */ 1448 int reset_duration = 1449 (sc->sc_chipset == CB_RX5C47X ? 400 : 50); 1450 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, 1451 PCI_BRIDGE_CONTROL_REG); 1452 aprint_debug("%s: enter bcr %" PRIx32 "\n", __func__, bcr); 1453 1454 /* Reset bit Assert (bit 6 at 0x3E) */ 1455 bcr |= PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT; 1456 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr); 1457 aprint_debug("%s: wrote bcr %" PRIx32 "\n", __func__, bcr); 1458 delay_ms(reset_duration, sc); 1459 1460 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1461 /* Reset bit Deassert (bit 6 at 0x3E) */ 1462 bcr &= ~(PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT); 1463 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, 1464 bcr); 1465 aprint_debug("%s: wrote bcr %" PRIx32 "\n", __func__, bcr); 1466 delay_ms(reset_duration, sc); 1467 aprint_debug("%s: end of delay\n", __func__); 1468 } 1469 /* No card found on the slot. Keep Reset. */ 1470 return 1; 1471 } 1472 1473 /* 1474 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1475 * This function detect card Voltage. 1476 */ 1477 STATIC int 1478 cb_detect_voltage(struct pccbb_softc *sc) 1479 { 1480 u_int32_t psr; /* socket present-state reg */ 1481 bus_space_tag_t iot = sc->sc_base_memt; 1482 bus_space_handle_t ioh = sc->sc_base_memh; 1483 int vol = PCCARD_VCC_UKN; /* set 0 */ 1484 1485 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1486 1487 if (0x400u & psr) { 1488 vol |= PCCARD_VCC_5V; 1489 } 1490 if (0x800u & psr) { 1491 vol |= PCCARD_VCC_3V; 1492 } 1493 1494 return vol; 1495 } 1496 1497 STATIC int 1498 cbbprint(void *aux, const char *pcic) 1499 { 1500 #if 0 1501 struct cbslot_attach_args *cba = aux; 1502 1503 if (cba->cba_slot >= 0) { 1504 aprint_normal(" slot %d", cba->cba_slot); 1505 } 1506 #endif 1507 return UNCONF; 1508 } 1509 1510 /* 1511 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1512 * This function enables and disables the card 1513 */ 1514 STATIC int 1515 pccbb_cardenable(struct pccbb_softc *sc, int function) 1516 { 1517 u_int32_t command = 1518 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1519 1520 DPRINTF(("pccbb_cardenable:")); 1521 switch (function) { 1522 case CARDBUS_IO_ENABLE: 1523 command |= PCI_COMMAND_IO_ENABLE; 1524 break; 1525 case CARDBUS_IO_DISABLE: 1526 command &= ~PCI_COMMAND_IO_ENABLE; 1527 break; 1528 case CARDBUS_MEM_ENABLE: 1529 command |= PCI_COMMAND_MEM_ENABLE; 1530 break; 1531 case CARDBUS_MEM_DISABLE: 1532 command &= ~PCI_COMMAND_MEM_ENABLE; 1533 break; 1534 case CARDBUS_BM_ENABLE: 1535 command |= PCI_COMMAND_MASTER_ENABLE; 1536 break; 1537 case CARDBUS_BM_DISABLE: 1538 command &= ~PCI_COMMAND_MASTER_ENABLE; 1539 break; 1540 default: 1541 return 0; 1542 } 1543 1544 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1545 DPRINTF((" command reg 0x%x\n", command)); 1546 return 1; 1547 } 1548 1549 #if !rbus 1550 static int 1551 pccbb_io_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 1552 { 1553 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1554 int basereg; 1555 int limitreg; 1556 1557 if ((win < 0) || (win > 2)) { 1558 #if defined DIAGNOSTIC 1559 printf("cardbus_io_open: window out of range %d\n", win); 1560 #endif 1561 return 0; 1562 } 1563 1564 basereg = win * 8 + PCI_CB_IOBASE0; 1565 limitreg = win * 8 + PCI_CB_IOLIMIT0; 1566 1567 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1568 start, basereg, end, limitreg)); 1569 1570 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1571 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1572 return 1; 1573 } 1574 1575 /* 1576 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1577 */ 1578 static int 1579 pccbb_io_close(cardbus_chipset_tag_t ct, int win) 1580 { 1581 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1582 int basereg; 1583 int limitreg; 1584 1585 if ((win < 0) || (win > 2)) { 1586 #if defined DIAGNOSTIC 1587 printf("cardbus_io_close: window out of range %d\n", win); 1588 #endif 1589 return 0; 1590 } 1591 1592 basereg = win * 8 + PCI_CB_IOBASE0; 1593 limitreg = win * 8 + PCI_CB_IOLIMIT0; 1594 1595 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1596 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1597 return 1; 1598 } 1599 1600 static int 1601 pccbb_mem_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 1602 { 1603 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1604 int basereg; 1605 int limitreg; 1606 1607 if ((win < 0) || (win > 2)) { 1608 #if defined DIAGNOSTIC 1609 printf("cardbus_mem_open: window out of range %d\n", win); 1610 #endif 1611 return 0; 1612 } 1613 1614 basereg = win * 8 + PCI_CB_MEMBASE0; 1615 limitreg = win * 8 + PCI_CB_MEMLIMIT0; 1616 1617 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1618 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1619 return 1; 1620 } 1621 1622 static int 1623 pccbb_mem_close(cardbus_chipset_tag_t ct, int win) 1624 { 1625 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1626 int basereg; 1627 int limitreg; 1628 1629 if ((win < 0) || (win > 2)) { 1630 #if defined DIAGNOSTIC 1631 printf("cardbus_mem_close: window out of range %d\n", win); 1632 #endif 1633 return 0; 1634 } 1635 1636 basereg = win * 8 + PCI_CB_MEMBASE0; 1637 limitreg = win * 8 + PCI_CB_MEMLIMIT0; 1638 1639 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1640 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1641 return 1; 1642 } 1643 #endif 1644 1645 /* 1646 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1647 * int level, 1648 * int (* func)(void *), 1649 * void *arg) 1650 * 1651 * This function registers an interrupt handler at the bridge, in 1652 * order not to call the interrupt handlers of child devices when 1653 * a card-deletion interrupt occurs. 1654 * 1655 * The argument level is not used. 1656 */ 1657 static void * 1658 pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, int level, 1659 int (*func)(void *), void *arg) 1660 { 1661 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1662 1663 return pccbb_intr_establish(sc, level, func, arg); 1664 } 1665 1666 1667 /* 1668 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1669 * void *ih) 1670 * 1671 * This function removes an interrupt handler pointed by ih. 1672 */ 1673 static void 1674 pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih) 1675 { 1676 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1677 1678 pccbb_intr_disestablish(sc, ih); 1679 } 1680 1681 1682 void 1683 pccbb_intr_route(struct pccbb_softc *sc) 1684 { 1685 pcireg_t bcr, cbctrl; 1686 1687 /* initialize bridge intr routing */ 1688 bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1689 bcr &= ~CB_BCR_INTR_IREQ_ENABLE; 1690 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr); 1691 1692 switch (sc->sc_chipset) { 1693 case CB_TI113X: 1694 cbctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1695 /* functional intr enabled */ 1696 cbctrl |= PCI113X_CBCTRL_PCI_INTR; 1697 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, cbctrl); 1698 break; 1699 default: 1700 break; 1701 } 1702 } 1703 1704 /* 1705 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1706 * int irq, 1707 * int level, 1708 * int (* func)(void *), 1709 * void *arg) 1710 * 1711 * This function registers an interrupt handler at the bridge, in 1712 * order not to call the interrupt handlers of child devices when 1713 * a card-deletion interrupt occurs. 1714 * 1715 */ 1716 static void * 1717 pccbb_intr_establish(struct pccbb_softc *sc, int level, 1718 int (*func)(void *), void *arg) 1719 { 1720 struct pccbb_intrhand_list *pil, *newpil; 1721 1722 DPRINTF(("pccbb_intr_establish start. %p\n", LIST_FIRST(&sc->sc_pil))); 1723 1724 if (LIST_EMPTY(&sc->sc_pil)) { 1725 pccbb_intr_route(sc); 1726 } 1727 1728 /* 1729 * Allocate a room for interrupt handler structure. 1730 */ 1731 if (NULL == (newpil = 1732 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1733 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1734 return NULL; 1735 } 1736 1737 newpil->pil_func = func; 1738 newpil->pil_arg = arg; 1739 newpil->pil_icookie = makeiplcookie(level); 1740 1741 if (LIST_EMPTY(&sc->sc_pil)) { 1742 LIST_INSERT_HEAD(&sc->sc_pil, newpil, pil_next); 1743 } else { 1744 for (pil = LIST_FIRST(&sc->sc_pil); 1745 LIST_NEXT(pil, pil_next) != NULL; 1746 pil = LIST_NEXT(pil, pil_next)); 1747 LIST_INSERT_AFTER(pil, newpil, pil_next); 1748 } 1749 1750 DPRINTF(("pccbb_intr_establish add pil. %p\n", 1751 LIST_FIRST(&sc->sc_pil))); 1752 1753 return newpil; 1754 } 1755 1756 /* 1757 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1758 * void *ih) 1759 * 1760 * This function removes an interrupt handler pointed by ih. ih 1761 * should be the value returned by cardbus_intr_establish() or 1762 * NULL. 1763 * 1764 * When ih is NULL, this function will do nothing. 1765 */ 1766 static void 1767 pccbb_intr_disestablish(struct pccbb_softc *sc, void *ih) 1768 { 1769 struct pccbb_intrhand_list *pil; 1770 pcireg_t reg; 1771 1772 DPRINTF(("pccbb_intr_disestablish start. %p\n", 1773 LIST_FIRST(&sc->sc_pil))); 1774 1775 if (ih == NULL) { 1776 /* intr handler is not set */ 1777 DPRINTF(("pccbb_intr_disestablish: no ih\n")); 1778 return; 1779 } 1780 1781 #ifdef DIAGNOSTIC 1782 LIST_FOREACH(pil, &sc->sc_pil, pil_next) { 1783 DPRINTF(("pccbb_intr_disestablish: pil %p\n", pil)); 1784 if (pil == ih) { 1785 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1786 break; 1787 } 1788 } 1789 if (pil == NULL) { 1790 panic("pccbb_intr_disestablish: %s cannot find pil %p", 1791 device_xname(sc->sc_dev), ih); 1792 } 1793 #endif 1794 1795 pil = (struct pccbb_intrhand_list *)ih; 1796 LIST_REMOVE(pil, pil_next); 1797 free(pil, M_DEVBUF); 1798 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1799 1800 if (LIST_EMPTY(&sc->sc_pil)) { 1801 /* No interrupt handlers */ 1802 1803 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1804 1805 /* stop routing PCI intr */ 1806 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, 1807 PCI_BRIDGE_CONTROL_REG); 1808 reg |= CB_BCR_INTR_IREQ_ENABLE; 1809 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, 1810 reg); 1811 1812 switch (sc->sc_chipset) { 1813 case CB_TI113X: 1814 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1815 /* functional intr disabled */ 1816 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1817 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1818 break; 1819 default: 1820 break; 1821 } 1822 } 1823 } 1824 1825 #if defined SHOW_REGS 1826 static void 1827 cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, bus_space_tag_t memt, 1828 bus_space_handle_t memh) 1829 { 1830 int i; 1831 printf("PCI config regs:"); 1832 for (i = 0; i < 0x50; i += 4) { 1833 if (i % 16 == 0) 1834 printf("\n 0x%02x:", i); 1835 printf(" %08x", pci_conf_read(pc, tag, i)); 1836 } 1837 for (i = 0x80; i < 0xb0; i += 4) { 1838 if (i % 16 == 0) 1839 printf("\n 0x%02x:", i); 1840 printf(" %08x", pci_conf_read(pc, tag, i)); 1841 } 1842 1843 if (memh == 0) { 1844 printf("\n"); 1845 return; 1846 } 1847 1848 printf("\nsocket regs:"); 1849 for (i = 0; i <= 0x10; i += 0x04) 1850 printf(" %08x", bus_space_read_4(memt, memh, i)); 1851 printf("\nExCA regs:"); 1852 for (i = 0; i < 0x08; ++i) 1853 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1854 printf("\n"); 1855 return; 1856 } 1857 #endif 1858 1859 /* 1860 * static pcitag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1861 * int busno, int function) 1862 * This is the function to make a tag to access config space of 1863 * a CardBus Card. It works same as pci_conf_read. 1864 */ 1865 static pcitag_t 1866 pccbb_make_tag(cardbus_chipset_tag_t cc, int busno, int function) 1867 { 1868 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1869 1870 return pci_make_tag(sc->sc_pc, busno, 0, function); 1871 } 1872 1873 /* 1874 * pccbb_conf_read 1875 * 1876 * This is the function to read the config space of a CardBus card. 1877 * It works the same as pci_conf_read(9). 1878 */ 1879 static pcireg_t 1880 pccbb_conf_read(cardbus_chipset_tag_t cc, pcitag_t tag, int offset) 1881 { 1882 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1883 pcitag_t brtag = sc->sc_tag; 1884 pcireg_t reg; 1885 1886 /* 1887 * clear cardbus master abort status; it is OK to write without 1888 * reading before because all bits are r/o or w1tc 1889 */ 1890 pci_conf_write(sc->sc_pc, brtag, PCI_CBB_SECSTATUS, 1891 CBB_SECSTATUS_CBMABORT); 1892 reg = pci_conf_read(sc->sc_pc, tag, offset); 1893 /* check cardbus master abort status */ 1894 if (pci_conf_read(sc->sc_pc, brtag, PCI_CBB_SECSTATUS) 1895 & CBB_SECSTATUS_CBMABORT) 1896 return (0xffffffff); 1897 return reg; 1898 } 1899 1900 /* 1901 * pccbb_conf_write 1902 * 1903 * This is the function to write the config space of a CardBus 1904 * card. It works the same as pci_conf_write(9). 1905 */ 1906 static void 1907 pccbb_conf_write(cardbus_chipset_tag_t cc, pcitag_t tag, int reg, pcireg_t val) 1908 { 1909 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1910 1911 pci_conf_write(sc->sc_pc, tag, reg, val); 1912 } 1913 1914 #if 0 1915 STATIC int 1916 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1917 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 1918 int speed, int flags, 1919 bus_space_handle_t * iohp) 1920 #endif 1921 /* 1922 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1923 * bus_addr_t start, bus_size_t size, 1924 * bus_size_t align, 1925 * struct pcmcia_io_handle *pcihp 1926 * 1927 * This function only allocates I/O region for pccard. This function 1928 * never maps the allocated region to pccard I/O area. 1929 * 1930 * XXX: The interface of this function is not very good, I believe. 1931 */ 1932 STATIC int 1933 pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, 1934 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 1935 { 1936 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 1937 bus_addr_t ioaddr; 1938 int flags = 0; 1939 bus_space_tag_t iot; 1940 bus_space_handle_t ioh; 1941 bus_addr_t mask; 1942 #if rbus 1943 rbus_tag_t rb; 1944 #endif 1945 if (align == 0) { 1946 align = size; /* XXX: funny??? */ 1947 } 1948 1949 if (start != 0) { 1950 /* XXX: assume all card decode lower 10 bits by its hardware */ 1951 mask = 0x3ff; 1952 /* enforce to use only masked address */ 1953 start &= mask; 1954 } else { 1955 /* 1956 * calculate mask: 1957 * 1. get the most significant bit of size (call it msb). 1958 * 2. compare msb with the value of size. 1959 * 3. if size is larger, shift msb left once. 1960 * 4. obtain mask value to decrement msb. 1961 */ 1962 bus_size_t size_tmp = size; 1963 int shifts = 0; 1964 1965 mask = 1; 1966 while (size_tmp) { 1967 ++shifts; 1968 size_tmp >>= 1; 1969 } 1970 mask = (1 << shifts); 1971 if (mask < size) { 1972 mask <<= 1; 1973 } 1974 --mask; 1975 } 1976 1977 /* 1978 * Allocate some arbitrary I/O space. 1979 */ 1980 1981 iot = sc->sc_iot; 1982 1983 #if rbus 1984 rb = sc->sc_rbus_iot; 1985 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 1986 return 1; 1987 } 1988 DPRINTF(("pccbb_pcmcia_io_alloc alloc port 0x%lx+0x%lx\n", 1989 (u_long) ioaddr, (u_long) size)); 1990 #else 1991 if (start) { 1992 ioaddr = start; 1993 if (bus_space_map(iot, start, size, 0, &ioh)) { 1994 return 1; 1995 } 1996 DPRINTF(("pccbb_pcmcia_io_alloc map port 0x%lx+0x%lx\n", 1997 (u_long) ioaddr, (u_long) size)); 1998 } else { 1999 flags |= PCMCIA_IO_ALLOCATED; 2000 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 2001 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 2002 size, align, 0, 0, &ioaddr, &ioh)) { 2003 /* No room be able to be get. */ 2004 return 1; 2005 } 2006 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2007 (u_long) ioaddr, (u_long) size)); 2008 } 2009 #endif 2010 2011 pcihp->iot = iot; 2012 pcihp->ioh = ioh; 2013 pcihp->addr = ioaddr; 2014 pcihp->size = size; 2015 pcihp->flags = flags; 2016 2017 return 0; 2018 } 2019 2020 /* 2021 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2022 * struct pcmcia_io_handle *pcihp) 2023 * 2024 * This function only frees I/O region for pccard. 2025 * 2026 * XXX: The interface of this function is not very good, I believe. 2027 */ 2028 void 2029 pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2030 struct pcmcia_io_handle *pcihp) 2031 { 2032 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2033 #if !rbus 2034 bus_space_tag_t iot = pcihp->iot; 2035 #endif 2036 bus_space_handle_t ioh = pcihp->ioh; 2037 bus_size_t size = pcihp->size; 2038 2039 #if rbus 2040 rbus_tag_t rb = sc->sc_rbus_iot; 2041 2042 rbus_space_free(rb, ioh, size, NULL); 2043 #else 2044 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 2045 bus_space_free(iot, ioh, size); 2046 else 2047 bus_space_unmap(iot, ioh, size); 2048 #endif 2049 } 2050 2051 /* 2052 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 2053 * bus_addr_t offset, bus_size_t size, 2054 * struct pcmcia_io_handle *pcihp, 2055 * int *windowp) 2056 * 2057 * This function maps the allocated I/O region to pccard. This function 2058 * never allocates any I/O region for pccard I/O area. I don't 2059 * understand why the original authors of pcmciabus separated alloc and 2060 * map. I believe the two must be unite. 2061 * 2062 * XXX: no wait timing control? 2063 */ 2064 int 2065 pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, bus_addr_t offset, 2066 bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp) 2067 { 2068 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2069 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2070 bus_addr_t ioaddr = pcihp->addr + offset; 2071 int i, win; 2072 #if defined CBB_DEBUG 2073 static const char *width_names[] = { "dynamic", "io8", "io16" }; 2074 #endif 2075 2076 /* Sanity check I/O handle. */ 2077 2078 if (!bus_space_is_equal(sc->sc_iot, pcihp->iot)) { 2079 panic("pccbb_pcmcia_io_map iot is bogus"); 2080 } 2081 2082 /* XXX Sanity check offset/size. */ 2083 2084 win = -1; 2085 for (i = 0; i < PCIC_IO_WINS; i++) { 2086 if ((ph->ioalloc & (1 << i)) == 0) { 2087 win = i; 2088 ph->ioalloc |= (1 << i); 2089 break; 2090 } 2091 } 2092 2093 if (win == -1) { 2094 return 1; 2095 } 2096 2097 *windowp = win; 2098 2099 /* XXX this is pretty gross */ 2100 2101 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2102 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2103 2104 /* XXX wtf is this doing here? */ 2105 2106 #if 0 2107 printf(" port 0x%lx", (u_long) ioaddr); 2108 if (size > 1) { 2109 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2110 } 2111 #endif 2112 2113 ph->io[win].addr = ioaddr; 2114 ph->io[win].size = size; 2115 ph->io[win].width = width; 2116 2117 /* actual dirty register-value changing in the function below. */ 2118 pccbb_pcmcia_do_io_map(sc, win); 2119 2120 return 0; 2121 } 2122 2123 /* 2124 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2125 * 2126 * This function changes register-value to map I/O region for pccard. 2127 */ 2128 static void 2129 pccbb_pcmcia_do_io_map(struct pccbb_softc *sc, int win) 2130 { 2131 static u_int8_t pcic_iowidth[3] = { 2132 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2133 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2134 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2135 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2136 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2137 }; 2138 2139 #define PCIC_SIA_START_LOW 0 2140 #define PCIC_SIA_START_HIGH 1 2141 #define PCIC_SIA_STOP_LOW 2 2142 #define PCIC_SIA_STOP_HIGH 3 2143 2144 int regbase_win = 0x8 + win * 0x04; 2145 u_int8_t ioctl, enable; 2146 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2147 2148 DPRINTF(("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx " 2149 "width %d\n", win, (unsigned long)ph->io[win].addr, 2150 (unsigned long)ph->io[win].size, ph->io[win].width * 8)); 2151 2152 Pcic_write(sc, regbase_win + PCIC_SIA_START_LOW, 2153 ph->io[win].addr & 0xff); 2154 Pcic_write(sc, regbase_win + PCIC_SIA_START_HIGH, 2155 (ph->io[win].addr >> 8) & 0xff); 2156 2157 Pcic_write(sc, regbase_win + PCIC_SIA_STOP_LOW, 2158 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2159 Pcic_write(sc, regbase_win + PCIC_SIA_STOP_HIGH, 2160 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2161 2162 ioctl = Pcic_read(sc, PCIC_IOCTL); 2163 enable = Pcic_read(sc, PCIC_ADDRWIN_ENABLE); 2164 switch (win) { 2165 case 0: 2166 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2167 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2168 PCIC_IOCTL_IO0_DATASIZE_MASK); 2169 ioctl |= pcic_iowidth[ph->io[win].width]; 2170 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2171 break; 2172 case 1: 2173 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2174 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2175 PCIC_IOCTL_IO1_DATASIZE_MASK); 2176 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2177 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2178 break; 2179 } 2180 Pcic_write(sc, PCIC_IOCTL, ioctl); 2181 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, enable); 2182 #if defined(CBB_DEBUG) 2183 { 2184 u_int8_t start_low = 2185 Pcic_read(sc, regbase_win + PCIC_SIA_START_LOW); 2186 u_int8_t start_high = 2187 Pcic_read(sc, regbase_win + PCIC_SIA_START_HIGH); 2188 u_int8_t stop_low = 2189 Pcic_read(sc, regbase_win + PCIC_SIA_STOP_LOW); 2190 u_int8_t stop_high = 2191 Pcic_read(sc, regbase_win + PCIC_SIA_STOP_HIGH); 2192 printf("pccbb_pcmcia_do_io_map start %02x %02x, " 2193 "stop %02x %02x, ioctl %02x enable %02x\n", 2194 start_low, start_high, stop_low, stop_high, ioctl, enable); 2195 } 2196 #endif 2197 } 2198 2199 /* 2200 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2201 * 2202 * This function unmaps I/O region. No return value. 2203 */ 2204 STATIC void 2205 pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t pch, int win) 2206 { 2207 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2208 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2209 int reg; 2210 2211 if (win >= PCIC_IO_WINS || win < 0) { 2212 panic("pccbb_pcmcia_io_unmap: window out of range"); 2213 } 2214 2215 reg = Pcic_read(sc, PCIC_ADDRWIN_ENABLE); 2216 switch (win) { 2217 case 0: 2218 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2219 break; 2220 case 1: 2221 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2222 break; 2223 } 2224 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, reg); 2225 2226 ph->ioalloc &= ~(1 << win); 2227 } 2228 2229 static int 2230 pccbb_pcmcia_wait_ready(struct pccbb_softc *sc) 2231 { 2232 u_int8_t stat; 2233 int i; 2234 2235 /* wait an initial 10ms for quick cards */ 2236 stat = Pcic_read(sc, PCIC_IF_STATUS); 2237 if (stat & PCIC_IF_STATUS_READY) 2238 return (0); 2239 pccbb_pcmcia_delay(sc, 10, "pccwr0"); 2240 for (i = 0; i < 50; i++) { 2241 stat = Pcic_read(sc, PCIC_IF_STATUS); 2242 if (stat & PCIC_IF_STATUS_READY) 2243 return (0); 2244 if ((stat & PCIC_IF_STATUS_CARDDETECT_MASK) != 2245 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2246 return (ENXIO); 2247 /* wait .1s (100ms) each iteration now */ 2248 pccbb_pcmcia_delay(sc, 100, "pccwr1"); 2249 } 2250 2251 printf("pccbb_pcmcia_wait_ready: ready never happened, status=%02x\n", 2252 stat); 2253 return (EWOULDBLOCK); 2254 } 2255 2256 /* 2257 * Perform long (msec order) delay. timo is in milliseconds. 2258 */ 2259 static void 2260 pccbb_pcmcia_delay(struct pccbb_softc *sc, int timo, const char *wmesg) 2261 { 2262 #ifdef DIAGNOSTIC 2263 if (timo <= 0) 2264 panic("pccbb_pcmcia_delay: called with timeout %d", timo); 2265 if (!curlwp) 2266 panic("pccbb_pcmcia_delay: called in interrupt context"); 2267 #endif 2268 DPRINTF(("pccbb_pcmcia_delay: \"%s\", sleep %d ms\n", wmesg, timo)); 2269 kpause(wmesg, false, max(mstohz(timo), 1), NULL); 2270 } 2271 2272 /* 2273 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2274 * 2275 * This function enables the card. All information is stored in 2276 * the first argument, pcmcia_chipset_handle_t. 2277 */ 2278 STATIC void 2279 pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2280 { 2281 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2282 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2283 pcireg_t spsr; 2284 int voltage; 2285 int win; 2286 u_int8_t power, intr; 2287 #ifdef DIAGNOSTIC 2288 int reg; 2289 #endif 2290 2291 /* this bit is mostly stolen from pcic_attach_card */ 2292 2293 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2294 2295 /* get card Vcc info */ 2296 spsr = 2297 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2298 CB_SOCKET_STAT); 2299 if (spsr & CB_SOCKET_STAT_5VCARD) { 2300 DPRINTF(("5V card\n")); 2301 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2302 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2303 DPRINTF(("3V card\n")); 2304 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2305 } else { 2306 DPRINTF(("?V card, 0x%x\n", spsr)); /* XXX */ 2307 return; 2308 } 2309 2310 /* disable interrupts; assert RESET */ 2311 intr = Pcic_read(sc, PCIC_INTR); 2312 intr &= PCIC_INTR_ENABLE; 2313 Pcic_write(sc, PCIC_INTR, intr); 2314 2315 /* zero out the address windows */ 2316 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, 0); 2317 2318 /* power down the socket to reset it, clear the card reset pin */ 2319 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2320 2321 /* power off; assert output enable bit */ 2322 power = PCIC_PWRCTL_OE; 2323 Pcic_write(sc, PCIC_PWRCTL, power); 2324 2325 /* power up the socket */ 2326 if (pccbb_power(sc, voltage) == 0) 2327 return; 2328 2329 /* 2330 * Table 4-18 and figure 4-6 of the PC Card specifiction say: 2331 * Vcc Rising Time (Tpr) = 100ms (handled in pccbb_power() above) 2332 * RESET Width (Th (Hi-z RESET)) = 1ms 2333 * RESET Width (Tw (RESET)) = 10us 2334 * 2335 * some machines require some more time to be settled 2336 * for example old toshiba topic bridges! 2337 * (100ms is added here). 2338 */ 2339 pccbb_pcmcia_delay(sc, 200 + 1, "pccen1"); 2340 2341 /* negate RESET */ 2342 intr |= PCIC_INTR_RESET; 2343 Pcic_write(sc, PCIC_INTR, intr); 2344 2345 /* 2346 * RESET Setup Time (Tsu (RESET)) = 20ms 2347 */ 2348 pccbb_pcmcia_delay(sc, 20, "pccen2"); 2349 2350 #ifdef DIAGNOSTIC 2351 reg = Pcic_read(sc, PCIC_IF_STATUS); 2352 if ((reg & PCIC_IF_STATUS_POWERACTIVE) == 0) 2353 printf("pccbb_pcmcia_socket_enable: no power, status=%x\n", 2354 reg); 2355 #endif 2356 2357 /* wait for the chip to finish initializing */ 2358 if (pccbb_pcmcia_wait_ready(sc)) { 2359 #ifdef DIAGNOSTIC 2360 printf("pccbb_pcmcia_socket_enable: never became ready\n"); 2361 #endif 2362 /* XXX return a failure status?? */ 2363 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2364 Pcic_write(sc, PCIC_PWRCTL, 0); 2365 return; 2366 } 2367 2368 /* reinstall all the memory and io mappings */ 2369 for (win = 0; win < PCIC_MEM_WINS; ++win) 2370 if (ph->memalloc & (1 << win)) 2371 pccbb_pcmcia_do_mem_map(sc, win); 2372 for (win = 0; win < PCIC_IO_WINS; ++win) 2373 if (ph->ioalloc & (1 << win)) 2374 pccbb_pcmcia_do_io_map(sc, win); 2375 } 2376 2377 /* 2378 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2379 * 2380 * This function disables the card. All information is stored in 2381 * the first argument, pcmcia_chipset_handle_t. 2382 */ 2383 STATIC void 2384 pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t pch) 2385 { 2386 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2387 u_int8_t intr; 2388 2389 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2390 2391 /* disable interrupts; assert RESET */ 2392 intr = Pcic_read(sc, PCIC_INTR); 2393 intr &= PCIC_INTR_ENABLE; 2394 Pcic_write(sc, PCIC_INTR, intr); 2395 2396 /* zero out the address windows */ 2397 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, 0); 2398 2399 /* power down the socket to reset it, clear the card reset pin */ 2400 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2401 2402 /* disable socket: negate output enable bit and power off */ 2403 Pcic_write(sc, PCIC_PWRCTL, 0); 2404 2405 /* 2406 * Vcc Falling Time (Tpf) = 300ms 2407 */ 2408 pccbb_pcmcia_delay(sc, 300, "pccwr1"); 2409 } 2410 2411 STATIC void 2412 pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t pch, int type) 2413 { 2414 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2415 u_int8_t intr; 2416 2417 /* set the card type */ 2418 2419 intr = Pcic_read(sc, PCIC_INTR); 2420 intr &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_CARDTYPE_MASK); 2421 if (type == PCMCIA_IFTYPE_IO) 2422 intr |= PCIC_INTR_CARDTYPE_IO; 2423 else 2424 intr |= PCIC_INTR_CARDTYPE_MEM; 2425 Pcic_write(sc, PCIC_INTR, intr); 2426 2427 DPRINTF(("%s: pccbb_pcmcia_socket_settype type %s %02x\n", 2428 device_xname(sc->sc_dev), 2429 ((type == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2430 } 2431 2432 /* 2433 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2434 * 2435 * This function detects whether a card is in the slot or not. 2436 * If a card is inserted, return 1. Otherwise, return 0. 2437 */ 2438 STATIC int 2439 pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch) 2440 { 2441 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2442 2443 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2444 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2445 } 2446 2447 #if 0 2448 STATIC int 2449 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2450 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2451 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2452 #endif 2453 /* 2454 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2455 * bus_size_t size, 2456 * struct pcmcia_mem_handle *pcmhp) 2457 * 2458 * This function only allocates memory region for pccard. This 2459 * function never maps the allocated region to pccard memory area. 2460 * 2461 * XXX: Why the argument of start address is not in? 2462 */ 2463 STATIC int 2464 pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 2465 struct pcmcia_mem_handle *pcmhp) 2466 { 2467 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2468 bus_space_handle_t memh; 2469 bus_addr_t addr; 2470 bus_size_t sizepg; 2471 #if rbus 2472 rbus_tag_t rb; 2473 #endif 2474 2475 /* Check that the card is still there. */ 2476 if ((Pcic_read(sc, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2477 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2478 return 1; 2479 2480 /* out of sc->memh, allocate as many pages as necessary */ 2481 2482 /* convert size to PCIC pages */ 2483 /* 2484 * This is not enough; when the requested region is on the page 2485 * boundaries, this may calculate wrong result. 2486 */ 2487 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2488 #if 0 2489 if (sizepg > PCIC_MAX_MEM_PAGES) { 2490 return 1; 2491 } 2492 #endif 2493 2494 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2495 return 1; 2496 } 2497 2498 addr = 0; /* XXX gcc -Wuninitialized */ 2499 2500 #if rbus 2501 rb = sc->sc_rbus_memt; 2502 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2503 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2504 &addr, &memh)) { 2505 return 1; 2506 } 2507 #else 2508 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2509 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2510 0, /* boundary */ 2511 0, /* flags */ 2512 &addr, &memh)) { 2513 return 1; 2514 } 2515 #endif 2516 2517 DPRINTF(("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, " 2518 "realsize 0x%lx\n", (unsigned long)addr, (unsigned long)size, 2519 (unsigned long)sizepg * PCIC_MEM_PAGESIZE)); 2520 2521 pcmhp->memt = sc->sc_memt; 2522 pcmhp->memh = memh; 2523 pcmhp->addr = addr; 2524 pcmhp->size = size; 2525 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2526 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2527 pcmhp->mhandle = 0; 2528 /* No offset??? Funny. */ 2529 2530 return 0; 2531 } 2532 2533 /* 2534 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2535 * struct pcmcia_mem_handle *pcmhp) 2536 * 2537 * This function release the memory space allocated by the function 2538 * pccbb_pcmcia_mem_alloc(). 2539 */ 2540 STATIC void 2541 pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2542 struct pcmcia_mem_handle *pcmhp) 2543 { 2544 #if rbus 2545 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2546 2547 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2548 #else 2549 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2550 #endif 2551 } 2552 2553 /* 2554 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2555 * 2556 * This function release the memory space allocated by the function 2557 * pccbb_pcmcia_mem_alloc(). 2558 */ 2559 STATIC void 2560 pccbb_pcmcia_do_mem_map(struct pccbb_softc *sc, int win) 2561 { 2562 int regbase_win; 2563 bus_addr_t phys_addr; 2564 bus_addr_t phys_end; 2565 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2566 2567 #define PCIC_SMM_START_LOW 0 2568 #define PCIC_SMM_START_HIGH 1 2569 #define PCIC_SMM_STOP_LOW 2 2570 #define PCIC_SMM_STOP_HIGH 3 2571 #define PCIC_CMA_LOW 4 2572 #define PCIC_CMA_HIGH 5 2573 2574 u_int8_t start_low, start_high = 0; 2575 u_int8_t stop_low, stop_high; 2576 u_int8_t off_low, off_high; 2577 u_int8_t mem_window; 2578 int reg; 2579 2580 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2581 int mem8 = 2582 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2583 || (kind == PCMCIA_MEM_ATTR); 2584 2585 regbase_win = 0x10 + win * 0x08; 2586 2587 phys_addr = ph->mem[win].addr; 2588 phys_end = phys_addr + ph->mem[win].size; 2589 2590 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2591 (unsigned long)phys_addr, (unsigned long)phys_end, 2592 (unsigned long)ph->mem[win].offset)); 2593 2594 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2595 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2596 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2597 2598 /* bit 19:12 */ 2599 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2600 /* bit 23:20 and bit 7 on */ 2601 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2602 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2603 /* bit 31:24, for 32-bit address */ 2604 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2605 2606 Pcic_write(sc, regbase_win + PCIC_SMM_START_LOW, start_low); 2607 Pcic_write(sc, regbase_win + PCIC_SMM_START_HIGH, start_high); 2608 2609 if (sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2610 Pcic_write(sc, 0x40 + win, mem_window); 2611 } 2612 2613 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2614 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2615 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2616 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2617 2618 Pcic_write(sc, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2619 Pcic_write(sc, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2620 2621 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2622 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2623 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2624 | ((kind == PCMCIA_MEM_ATTR) ? 2625 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2626 2627 Pcic_write(sc, regbase_win + PCIC_CMA_LOW, off_low); 2628 Pcic_write(sc, regbase_win + PCIC_CMA_HIGH, off_high); 2629 2630 reg = Pcic_read(sc, PCIC_ADDRWIN_ENABLE); 2631 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2632 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, reg); 2633 2634 #if defined(CBB_DEBUG) 2635 { 2636 int r1, r2, r3, r4, r5, r6, r7 = 0; 2637 2638 r1 = Pcic_read(sc, regbase_win + PCIC_SMM_START_LOW); 2639 r2 = Pcic_read(sc, regbase_win + PCIC_SMM_START_HIGH); 2640 r3 = Pcic_read(sc, regbase_win + PCIC_SMM_STOP_LOW); 2641 r4 = Pcic_read(sc, regbase_win + PCIC_SMM_STOP_HIGH); 2642 r5 = Pcic_read(sc, regbase_win + PCIC_CMA_LOW); 2643 r6 = Pcic_read(sc, regbase_win + PCIC_CMA_HIGH); 2644 if (sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2645 r7 = Pcic_read(sc, 0x40 + win); 2646 } 2647 2648 printf("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2649 "%02x%02x", win, r1, r2, r3, r4, r5, r6); 2650 if (sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2651 printf(" %02x", r7); 2652 } 2653 printf("\n"); 2654 } 2655 #endif 2656 } 2657 2658 /* 2659 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2660 * bus_addr_t card_addr, bus_size_t size, 2661 * struct pcmcia_mem_handle *pcmhp, 2662 * bus_addr_t *offsetp, int *windowp) 2663 * 2664 * This function maps memory space allocated by the function 2665 * pccbb_pcmcia_mem_alloc(). 2666 */ 2667 STATIC int 2668 pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2669 bus_addr_t card_addr, bus_size_t size, struct pcmcia_mem_handle *pcmhp, 2670 bus_size_t *offsetp, int *windowp) 2671 { 2672 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2673 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2674 bus_addr_t busaddr; 2675 long card_offset; 2676 int win; 2677 2678 /* Check that the card is still there. */ 2679 if ((Pcic_read(sc, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2680 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2681 return 1; 2682 2683 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2684 if ((ph->memalloc & (1 << win)) == 0) { 2685 ph->memalloc |= (1 << win); 2686 break; 2687 } 2688 } 2689 2690 if (win == PCIC_MEM_WINS) { 2691 return 1; 2692 } 2693 2694 *windowp = win; 2695 2696 /* XXX this is pretty gross */ 2697 2698 if (!bus_space_is_equal(sc->sc_memt, pcmhp->memt)) { 2699 panic("pccbb_pcmcia_mem_map memt is bogus"); 2700 } 2701 2702 busaddr = pcmhp->addr; 2703 2704 /* 2705 * compute the address offset to the pcmcia address space for the 2706 * pcic. this is intentionally signed. The masks and shifts below 2707 * will cause TRT to happen in the pcic registers. Deal with making 2708 * sure the address is aligned, and return the alignment offset. 2709 */ 2710 2711 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2712 card_addr -= *offsetp; 2713 2714 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2715 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2716 (u_long) card_addr)); 2717 2718 /* 2719 * include the offset in the size, and decrement size by one, since 2720 * the hw wants start/stop 2721 */ 2722 size += *offsetp - 1; 2723 2724 card_offset = (((long)card_addr) - ((long)busaddr)); 2725 2726 ph->mem[win].addr = busaddr; 2727 ph->mem[win].size = size; 2728 ph->mem[win].offset = card_offset; 2729 ph->mem[win].kind = kind; 2730 2731 pccbb_pcmcia_do_mem_map(sc, win); 2732 2733 return 0; 2734 } 2735 2736 /* 2737 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2738 * int window) 2739 * 2740 * This function unmaps memory space which mapped by the function 2741 * pccbb_pcmcia_mem_map(). 2742 */ 2743 STATIC void 2744 pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, int window) 2745 { 2746 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2747 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2748 int reg; 2749 2750 if (window >= PCIC_MEM_WINS) { 2751 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2752 } 2753 2754 reg = Pcic_read(sc, PCIC_ADDRWIN_ENABLE); 2755 reg &= ~(1 << window); 2756 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, reg); 2757 2758 ph->memalloc &= ~(1 << window); 2759 } 2760 2761 /* 2762 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2763 * struct pcmcia_function *pf, 2764 * int ipl, 2765 * int (*func)(void *), 2766 * void *arg); 2767 * 2768 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2769 */ 2770 STATIC void * 2771 pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2772 struct pcmcia_function *pf, int ipl, int (*func)(void *), void *arg) 2773 { 2774 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2775 2776 if (!(pf->cfe->flags & (PCMCIA_CFE_IRQLEVEL|PCMCIA_CFE_IRQPULSE))) { 2777 /* 2778 * XXX Noooooo! The interrupt flag must set properly!! 2779 * dumb pcmcia driver!! 2780 */ 2781 DPRINTF(("%s does not provide edge nor pulse interrupt\n", 2782 device_xname(sc->sc_dev))); 2783 return NULL; 2784 } 2785 2786 return pccbb_intr_establish(sc, ipl, func, arg); 2787 } 2788 2789 /* 2790 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2791 * void *ih) 2792 * 2793 * This function disables PC-Card interrupt. 2794 */ 2795 STATIC void 2796 pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 2797 { 2798 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2799 2800 pccbb_intr_disestablish(sc, ih); 2801 } 2802 2803 #if rbus 2804 /* 2805 * static int 2806 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2807 * bus_addr_t addr, bus_size_t size, 2808 * bus_addr_t mask, bus_size_t align, 2809 * int flags, bus_addr_t *addrp; 2810 * bus_space_handle_t *bshp) 2811 * 2812 * This function allocates a portion of memory or io space for 2813 * clients. This function is called from CardBus card drivers. 2814 */ 2815 static int 2816 pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2817 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 2818 int flags, bus_addr_t *addrp, bus_space_handle_t *bshp) 2819 { 2820 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2821 2822 DPRINTF(("pccbb_rbus_cb_space_alloc: addr 0x%lx, size 0x%lx, " 2823 "mask 0x%lx, align 0x%lx\n", (unsigned long)addr, 2824 (unsigned long)size, (unsigned long)mask, (unsigned long)align)); 2825 2826 if (align == 0) { 2827 align = size; 2828 } 2829 2830 if (bus_space_is_equal(rb->rb_bt, sc->sc_memt)) { 2831 if (align < 16) { 2832 return 1; 2833 } 2834 /* 2835 * XXX: align more than 0x1000 to avoid overwrapping 2836 * memory windows for two or more devices. 0x1000 2837 * means memory window's granularity. 2838 * 2839 * Two or more devices should be able to share same 2840 * memory window region. However, overrapping memory 2841 * window is not good because some devices, such as 2842 * 3Com 3C575[BC], have a broken address decoder and 2843 * intrude other's memory region. 2844 */ 2845 if (align < 0x1000) { 2846 align = 0x1000; 2847 } 2848 } else if (bus_space_is_equal(rb->rb_bt, sc->sc_iot)) { 2849 if (align < 4) { 2850 return 1; 2851 } 2852 /* XXX: hack for avoiding ISA image */ 2853 if (mask < 0x0100) { 2854 mask = 0x3ff; 2855 addr = 0x300; 2856 } 2857 2858 } else { 2859 DPRINTF(("pccbb_rbus_cb_space_alloc: Bus space tag 0x%lx is " 2860 "NOT used. io: 0x%lx, mem: 0x%lx\n", 2861 (unsigned long)rb->rb_bt, (unsigned long)sc->sc_iot, 2862 (unsigned long)sc->sc_memt)); 2863 return 1; 2864 /* XXX: panic here? */ 2865 } 2866 2867 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 2868 aprint_normal_dev(sc->sc_dev, "<rbus> no bus space\n"); 2869 return 1; 2870 } 2871 2872 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 2873 2874 return 0; 2875 } 2876 2877 /* 2878 * static int 2879 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 2880 * bus_space_handle_t *bshp, bus_size_t size); 2881 * 2882 * This function is called from CardBus card drivers. 2883 */ 2884 static int 2885 pccbb_rbus_cb_space_free(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2886 bus_space_handle_t bsh, bus_size_t size) 2887 { 2888 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2889 bus_space_tag_t bt = rb->rb_bt; 2890 2891 pccbb_close_win(sc, bt, bsh, size); 2892 2893 if (bus_space_is_equal(bt, sc->sc_memt)) { 2894 } else if (bus_space_is_equal(bt, sc->sc_iot)) { 2895 } else { 2896 return 1; 2897 /* XXX: panic here? */ 2898 } 2899 2900 return rbus_space_free(rb, bsh, size, NULL); 2901 } 2902 #endif /* rbus */ 2903 2904 #if rbus 2905 2906 static int 2907 pccbb_open_win(struct pccbb_softc *sc, bus_space_tag_t bst, bus_addr_t addr, 2908 bus_size_t size, bus_space_handle_t bsh, int flags) 2909 { 2910 struct pccbb_win_chain_head *head; 2911 bus_addr_t align; 2912 2913 head = &sc->sc_iowindow; 2914 align = 0x04; 2915 if (bus_space_is_equal(sc->sc_memt, bst)) { 2916 head = &sc->sc_memwindow; 2917 align = 0x1000; 2918 DPRINTF(("using memory window, 0x%lx 0x%lx 0x%lx\n\n", 2919 (unsigned long)sc->sc_iot, (unsigned long)sc->sc_memt, 2920 (unsigned long)bst)); 2921 } 2922 2923 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 2924 aprint_error_dev(sc->sc_dev, 2925 "pccbb_open_win: %s winlist insert failed\n", 2926 (head == &sc->sc_memwindow) ? "mem" : "io"); 2927 } 2928 pccbb_winset(align, sc, bst); 2929 2930 return 0; 2931 } 2932 2933 static int 2934 pccbb_close_win(struct pccbb_softc *sc, bus_space_tag_t bst, 2935 bus_space_handle_t bsh, bus_size_t size) 2936 { 2937 struct pccbb_win_chain_head *head; 2938 bus_addr_t align; 2939 2940 head = &sc->sc_iowindow; 2941 align = 0x04; 2942 if (bus_space_is_equal(sc->sc_memt, bst)) { 2943 head = &sc->sc_memwindow; 2944 align = 0x1000; 2945 } 2946 2947 if (pccbb_winlist_delete(head, bsh, size)) { 2948 aprint_error_dev(sc->sc_dev, 2949 "pccbb_close_win: %s winlist delete failed\n", 2950 (head == &sc->sc_memwindow) ? "mem" : "io"); 2951 } 2952 pccbb_winset(align, sc, bst); 2953 2954 return 0; 2955 } 2956 2957 static int 2958 pccbb_winlist_insert(struct pccbb_win_chain_head *head, bus_addr_t start, 2959 bus_size_t size, bus_space_handle_t bsh, int flags) 2960 { 2961 struct pccbb_win_chain *chainp, *elem; 2962 2963 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 2964 M_NOWAIT)) == NULL) 2965 return (1); /* fail */ 2966 2967 elem->wc_start = start; 2968 elem->wc_end = start + (size - 1); 2969 elem->wc_handle = bsh; 2970 elem->wc_flags = flags; 2971 2972 TAILQ_FOREACH(chainp, head, wc_list) { 2973 if (chainp->wc_end >= start) 2974 break; 2975 } 2976 if (chainp != NULL) 2977 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 2978 else 2979 TAILQ_INSERT_TAIL(head, elem, wc_list); 2980 return (0); 2981 } 2982 2983 static int 2984 pccbb_winlist_delete(struct pccbb_win_chain_head *head, bus_space_handle_t bsh, 2985 bus_size_t size) 2986 { 2987 struct pccbb_win_chain *chainp; 2988 2989 TAILQ_FOREACH(chainp, head, wc_list) { 2990 if (memcmp(&chainp->wc_handle, &bsh, sizeof(bsh)) == 0) 2991 break; 2992 } 2993 if (chainp == NULL) 2994 return 1; /* fail: no candidate to remove */ 2995 2996 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 2997 printf("pccbb_winlist_delete: window 0x%lx size " 2998 "inconsistent: 0x%lx, 0x%lx\n", 2999 (unsigned long)chainp->wc_start, 3000 (unsigned long)(chainp->wc_end - chainp->wc_start), 3001 (unsigned long)(size - 1)); 3002 return 1; 3003 } 3004 3005 TAILQ_REMOVE(head, chainp, wc_list); 3006 free(chainp, M_DEVBUF); 3007 3008 return 0; 3009 } 3010 3011 static void 3012 pccbb_winset(bus_addr_t align, struct pccbb_softc *sc, bus_space_tag_t bst) 3013 { 3014 pci_chipset_tag_t pc; 3015 pcitag_t tag; 3016 bus_addr_t mask = ~(align - 1); 3017 struct { 3018 pcireg_t win_start; 3019 pcireg_t win_limit; 3020 int win_flags; 3021 } win[2]; 3022 struct pccbb_win_chain *chainp; 3023 int offs; 3024 3025 win[0].win_start = win[1].win_start = 0xffffffff; 3026 win[0].win_limit = win[1].win_limit = 0; 3027 win[0].win_flags = win[1].win_flags = 0; 3028 3029 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3030 offs = PCI_CB_IOBASE0; 3031 if (bus_space_is_equal(sc->sc_memt, bst)) { 3032 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3033 offs = PCI_CB_MEMBASE0; 3034 } 3035 3036 if (chainp != NULL) { 3037 win[0].win_start = chainp->wc_start & mask; 3038 win[0].win_limit = chainp->wc_end & mask; 3039 win[0].win_flags = chainp->wc_flags; 3040 chainp = TAILQ_NEXT(chainp, wc_list); 3041 } 3042 3043 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3044 if (win[1].win_start == 0xffffffff) { 3045 /* window 1 is not used */ 3046 if ((win[0].win_flags == chainp->wc_flags) && 3047 (win[0].win_limit + align >= 3048 (chainp->wc_start & mask))) { 3049 /* concatenate */ 3050 win[0].win_limit = chainp->wc_end & mask; 3051 } else { 3052 /* make new window */ 3053 win[1].win_start = chainp->wc_start & mask; 3054 win[1].win_limit = chainp->wc_end & mask; 3055 win[1].win_flags = chainp->wc_flags; 3056 } 3057 continue; 3058 } 3059 3060 /* Both windows are engaged. */ 3061 if (win[0].win_flags == win[1].win_flags) { 3062 /* same flags */ 3063 if (win[0].win_flags == chainp->wc_flags) { 3064 if (win[1].win_start - (win[0].win_limit + 3065 align) < 3066 (chainp->wc_start & mask) - 3067 ((chainp->wc_end & mask) + align)) { 3068 /* 3069 * merge window 0 and 1, and set win1 3070 * to chainp 3071 */ 3072 win[0].win_limit = win[1].win_limit; 3073 win[1].win_start = 3074 chainp->wc_start & mask; 3075 win[1].win_limit = 3076 chainp->wc_end & mask; 3077 } else { 3078 win[1].win_limit = 3079 chainp->wc_end & mask; 3080 } 3081 } else { 3082 /* different flags */ 3083 3084 /* concatenate win0 and win1 */ 3085 win[0].win_limit = win[1].win_limit; 3086 /* allocate win[1] to new space */ 3087 win[1].win_start = chainp->wc_start & mask; 3088 win[1].win_limit = chainp->wc_end & mask; 3089 win[1].win_flags = chainp->wc_flags; 3090 } 3091 } else { 3092 /* the flags of win[0] and win[1] is different */ 3093 if (win[0].win_flags == chainp->wc_flags) { 3094 win[0].win_limit = chainp->wc_end & mask; 3095 /* 3096 * XXX this creates overlapping windows, so 3097 * what should the poor bridge do if one is 3098 * cachable, and the other is not? 3099 */ 3100 aprint_error_dev(sc->sc_dev, 3101 "overlapping windows\n"); 3102 } else { 3103 win[1].win_limit = chainp->wc_end & mask; 3104 } 3105 } 3106 } 3107 3108 pc = sc->sc_pc; 3109 tag = sc->sc_tag; 3110 pci_conf_write(pc, tag, offs, win[0].win_start); 3111 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3112 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3113 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3114 DPRINTF(("--pccbb_winset: win0 [0x%lx, 0x%lx), win1 [0x%lx, 0x%lx)\n", 3115 (unsigned long)pci_conf_read(pc, tag, offs), 3116 (unsigned long)pci_conf_read(pc, tag, offs + 4) + align, 3117 (unsigned long)pci_conf_read(pc, tag, offs + 8), 3118 (unsigned long)pci_conf_read(pc, tag, offs + 12) + align)); 3119 3120 if (bus_space_is_equal(bst, sc->sc_memt)) { 3121 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BRIDGE_CONTROL_REG); 3122 3123 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 3124 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 3125 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3126 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 3127 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3128 pci_conf_write(pc, tag, PCI_BRIDGE_CONTROL_REG, bcr); 3129 } 3130 } 3131 3132 #endif /* rbus */ 3133 3134 static bool 3135 pccbb_suspend(device_t dv, const pmf_qual_t *qual) 3136 { 3137 struct pccbb_softc *sc = device_private(dv); 3138 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3139 bus_space_handle_t base_memh = sc->sc_base_memh; 3140 pcireg_t reg; 3141 3142 if (sc->sc_pil_intr_enable) 3143 (void)pccbbintr_function(sc); 3144 sc->sc_pil_intr_enable = false; 3145 3146 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3147 /* Disable interrupts. */ 3148 reg &= ~(CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER); 3149 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3150 /* XXX joerg Disable power to the socket? */ 3151 3152 /* XXX flush PCI write */ 3153 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3154 3155 /* reset interrupt */ 3156 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, 3157 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT)); 3158 /* XXX flush PCI write */ 3159 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3160 3161 if (sc->sc_ih != NULL) { 3162 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 3163 sc->sc_ih = NULL; 3164 } 3165 3166 return true; 3167 } 3168 3169 static bool 3170 pccbb_resume(device_t dv, const pmf_qual_t *qual) 3171 { 3172 struct pccbb_softc *sc = device_private(dv); 3173 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3174 bus_space_handle_t base_memh = sc->sc_base_memh; 3175 pcireg_t reg; 3176 3177 pccbb_chipinit(sc); 3178 pccbb_intrinit(sc); 3179 /* setup memory and io space window for CB */ 3180 pccbb_winset(0x1000, sc, sc->sc_memt); 3181 pccbb_winset(0x04, sc, sc->sc_iot); 3182 3183 /* CSC Interrupt: Card detect interrupt on */ 3184 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3185 /* Card detect intr is turned on. */ 3186 reg |= CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; 3187 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3188 /* reset interrupt */ 3189 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3190 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3191 3192 /* 3193 * check for card insertion or removal during suspend period. 3194 * XXX: the code can't cope with card swap (remove then 3195 * insert). how can we detect such situation? 3196 */ 3197 (void)pccbbintr(sc); 3198 3199 sc->sc_pil_intr_enable = true; 3200 3201 return true; 3202 } 3203
Indexes created Fri Sep 26 08:10:20 GMT 2025