pccbb.c revision 1.216
1 /* $NetBSD: pccbb.c,v 1.216 2021/04/24 23:36:57 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: pccbb.c,v 1.216 2021/04/24 23:36:57 thorpej Exp $"); 30 31 /* 32 #define CBB_DEBUG 33 #define SHOW_REGS 34 */ 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/kernel.h> 39 #include <sys/errno.h> 40 #include <sys/ioctl.h> 41 #include <sys/reboot.h> /* for bootverbose */ 42 #include <sys/syslog.h> 43 #include <sys/device.h> 44 #include <sys/malloc.h> 45 #include <sys/proc.h> 46 47 #include <sys/intr.h> 48 #include <sys/bus.h> 49 50 #include <dev/pci/pcivar.h> 51 #include <dev/pci/pcireg.h> 52 #include <dev/pci/pcidevs.h> 53 54 #include <dev/pci/pccbbreg.h> 55 56 #include <dev/cardbus/cardslotvar.h> 57 #include <dev/cardbus/cardbusvar.h> 58 59 #include <dev/pcmcia/pcmciareg.h> 60 #include <dev/pcmcia/pcmciavar.h> 61 62 #include <dev/ic/i82365reg.h> 63 #include <dev/pci/pccbbvar.h> 64 65 #ifndef __NetBSD_Version__ 66 struct cfdriver cbb_cd = { 67 NULL, "cbb", DV_DULL 68 }; 69 #endif 70 71 #ifdef CBB_DEBUG 72 #define DPRINTF(x) printf x 73 #define STATIC 74 #else 75 #define DPRINTF(x) 76 #define STATIC static 77 #endif 78 79 int pccbb_burstup = 1; 80 81 /* 82 * delay_ms() is wait in milliseconds. It should be used instead 83 * of delay() if you want to wait more than 1 ms. 84 */ 85 static inline void 86 delay_ms(int millis, struct pccbb_softc *sc) 87 { 88 if (cold) 89 delay(millis * 1000); 90 else 91 kpause("pccbb", false, mstohz(millis), NULL); 92 } 93 94 int pcicbbmatch(device_t, cfdata_t, void *); 95 void pccbbattach(device_t, device_t, void *); 96 void pccbbchilddet(device_t, device_t); 97 int pccbbdetach(device_t, int); 98 int pccbbintr(void *); 99 static void pci113x_insert(void *); 100 static int pccbbintr_function(struct pccbb_softc *); 101 102 static int pccbb_detect_card(struct pccbb_softc *); 103 104 static void pccbb_pcmcia_write(struct pccbb_softc *, int, uint8_t); 105 static uint8_t pccbb_pcmcia_read(struct pccbb_softc *, int); 106 #define Pcic_read(sc, reg) pccbb_pcmcia_read((sc), (reg)) 107 #define Pcic_write(sc, reg, val) pccbb_pcmcia_write((sc), (reg), (val)) 108 109 STATIC int cb_reset(struct pccbb_softc *); 110 STATIC int cb_detect_voltage(struct pccbb_softc *); 111 STATIC int cbbprint(void *, const char *); 112 113 static int cb_chipset(uint32_t, int *); 114 STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *, 115 struct pcmciabus_attach_args *); 116 117 STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int); 118 STATIC int pccbb_power(struct pccbb_softc *, int); 119 STATIC int pccbb_power_ct(cardbus_chipset_tag_t, int); 120 STATIC int pccbb_cardenable(struct pccbb_softc *, int); 121 static void *pccbb_intr_establish(struct pccbb_softc *, 122 int, int (*ih) (void *), void *); 123 static void pccbb_intr_disestablish(struct pccbb_softc *, void *); 124 125 static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t, 126 int, int (*ih) (void *), void *); 127 static void pccbb_cb_intr_disestablish(cardbus_chipset_tag_t, void *); 128 129 static pcitag_t pccbb_make_tag(cardbus_chipset_tag_t, int, int); 130 static pcireg_t pccbb_conf_read(cardbus_chipset_tag_t, pcitag_t, int); 131 static void pccbb_conf_write(cardbus_chipset_tag_t, pcitag_t, int, pcireg_t); 132 static void pccbb_chipinit(struct pccbb_softc *); 133 static void pccbb_intrinit(struct pccbb_softc *); 134 135 STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 136 struct pcmcia_mem_handle *); 137 STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t, 138 struct pcmcia_mem_handle *); 139 STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 140 bus_size_t, struct pcmcia_mem_handle *, bus_size_t *, int *); 141 STATIC void pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t, int); 142 STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 143 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 144 STATIC void pccbb_pcmcia_io_free(pcmcia_chipset_handle_t, 145 struct pcmcia_io_handle *); 146 STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 147 bus_size_t, struct pcmcia_io_handle *, int *); 148 STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t, int); 149 STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t, 150 struct pcmcia_function *, int, int (*)(void *), void *); 151 STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t, void *); 152 STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t); 153 STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t); 154 STATIC void pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t, int); 155 STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t); 156 157 static int pccbb_pcmcia_wait_ready(struct pccbb_softc *); 158 static void pccbb_pcmcia_delay(struct pccbb_softc *, int, const char *); 159 160 static void pccbb_pcmcia_do_io_map(struct pccbb_softc *, int); 161 static void pccbb_pcmcia_do_mem_map(struct pccbb_softc *, int); 162 163 /* bus-space allocation and deallocation functions */ 164 165 static int pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t, rbus_tag_t, 166 bus_addr_t, bus_size_t, bus_addr_t, bus_size_t, 167 int, bus_addr_t *, bus_space_handle_t *); 168 static int pccbb_rbus_cb_space_free(cardbus_chipset_tag_t, rbus_tag_t, 169 bus_space_handle_t, bus_size_t); 170 171 172 173 static int pccbb_open_win(struct pccbb_softc *, bus_space_tag_t, 174 bus_addr_t, bus_size_t, bus_space_handle_t, int); 175 static int pccbb_close_win(struct pccbb_softc *, bus_space_tag_t, 176 bus_space_handle_t, bus_size_t); 177 static int pccbb_winlist_insert(struct pccbb_win_chain_head *, bus_addr_t, 178 bus_size_t, bus_space_handle_t, int); 179 static int pccbb_winlist_delete(struct pccbb_win_chain_head *, 180 bus_space_handle_t, bus_size_t); 181 static void pccbb_winset(bus_addr_t, struct pccbb_softc *, bus_space_tag_t); 182 void pccbb_winlist_show(struct pccbb_win_chain *); 183 184 185 /* for config_defer */ 186 static void pccbb_pci_callback(device_t); 187 188 static bool pccbb_suspend(device_t, const pmf_qual_t *); 189 static bool pccbb_resume(device_t, const pmf_qual_t *); 190 191 #if defined SHOW_REGS 192 static void cb_show_regs(pci_chipset_tag_t, pcitag_t, 193 bus_space_tag_t, bus_space_handle_t); 194 #endif 195 196 CFATTACH_DECL3_NEW(cbb_pci, sizeof(struct pccbb_softc), 197 pcicbbmatch, pccbbattach, pccbbdetach, NULL, NULL, pccbbchilddet, 198 DVF_DETACH_SHUTDOWN); 199 200 static const struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 201 pccbb_pcmcia_mem_alloc, 202 pccbb_pcmcia_mem_free, 203 pccbb_pcmcia_mem_map, 204 pccbb_pcmcia_mem_unmap, 205 pccbb_pcmcia_io_alloc, 206 pccbb_pcmcia_io_free, 207 pccbb_pcmcia_io_map, 208 pccbb_pcmcia_io_unmap, 209 pccbb_pcmcia_intr_establish, 210 pccbb_pcmcia_intr_disestablish, 211 pccbb_pcmcia_socket_enable, 212 pccbb_pcmcia_socket_disable, 213 pccbb_pcmcia_socket_settype, 214 pccbb_pcmcia_card_detect 215 }; 216 217 static const struct cardbus_functions pccbb_funcs = { 218 pccbb_rbus_cb_space_alloc, 219 pccbb_rbus_cb_space_free, 220 pccbb_cb_intr_establish, 221 pccbb_cb_intr_disestablish, 222 pccbb_ctrl, 223 pccbb_power_ct, 224 pccbb_make_tag, 225 pccbb_conf_read, 226 pccbb_conf_write, 227 }; 228 229 int 230 pcicbbmatch(device_t parent, cfdata_t match, void *aux) 231 { 232 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 233 234 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 235 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 236 PCI_INTERFACE(pa->pa_class) == 0) { 237 return 1; 238 } 239 240 return 0; 241 } 242 243 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 244 | ((prod) << PCI_PRODUCT_SHIFT)) 245 246 const struct yenta_chipinfo { 247 pcireg_t yc_id; /* vendor tag | product tag */ 248 int yc_chiptype; 249 int yc_flags; 250 } yc_chipsets[] = { 251 /* Texas Instruments chips */ 252 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 253 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 254 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 255 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 256 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI125X, 257 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 258 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 259 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 260 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 261 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 262 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 263 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 264 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI125X, 265 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 266 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI125X, 267 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 268 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 269 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 270 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 271 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 272 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI1420, 273 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 274 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI125X, 275 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 276 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 277 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 278 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1510), CB_TI12XX, 279 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 280 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1520), CB_TI12XX, 281 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 282 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4410YENTA), CB_TI12XX, 283 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 284 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4520YENTA), CB_TI12XX, 285 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 286 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI7420YENTA), CB_TI12XX, 287 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 288 289 /* Ricoh chips */ 290 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 291 PCCBB_PCMCIA_MEM_32}, 292 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 293 PCCBB_PCMCIA_MEM_32}, 294 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 295 PCCBB_PCMCIA_MEM_32}, 296 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 297 PCCBB_PCMCIA_MEM_32}, 298 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 299 PCCBB_PCMCIA_MEM_32}, 300 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 301 PCCBB_PCMCIA_MEM_32}, 302 303 /* Toshiba products */ 304 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 305 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 306 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 307 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 308 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 309 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 310 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 311 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 312 313 /* Cirrus Logic products */ 314 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 315 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 316 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 317 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 318 319 /* O2 Micro products */ 320 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6729), 321 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 322 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6730), 323 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 324 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6832), 325 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 326 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6836), 327 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 328 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6872), 329 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 330 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6922), 331 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 332 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6933), 333 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 334 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6972), 335 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 336 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_7223), 337 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 338 339 /* sentinel, or Generic chip */ 340 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 341 }; 342 343 static int 344 cb_chipset(uint32_t pci_id, int *flagp) 345 { 346 const struct yenta_chipinfo *yc; 347 348 /* Loop over except the last default entry. */ 349 for (yc = yc_chipsets; yc < yc_chipsets + 350 __arraycount(yc_chipsets) - 1; yc++) 351 if (pci_id == yc->yc_id) 352 break; 353 354 if (flagp != NULL) 355 *flagp = yc->yc_flags; 356 357 return yc->yc_chiptype; 358 } 359 360 void 361 pccbbchilddet(device_t self, device_t child) 362 { 363 struct pccbb_softc *sc = device_private(self); 364 int s; 365 366 KASSERT(sc->sc_csc == device_private(child)); 367 368 s = splbio(); 369 if (sc->sc_csc == device_private(child)) 370 sc->sc_csc = NULL; 371 splx(s); 372 } 373 374 void 375 pccbbattach(device_t parent, device_t self, void *aux) 376 { 377 struct pccbb_softc *sc = device_private(self); 378 struct pci_attach_args *pa = aux; 379 pci_chipset_tag_t pc = pa->pa_pc; 380 pcireg_t reg, sock_base; 381 bus_addr_t sockbase; 382 int flags; 383 384 #ifdef __HAVE_PCCBB_ATTACH_HOOK 385 pccbb_attach_hook(parent, self, pa); 386 #endif 387 388 sc->sc_dev = self; 389 390 mutex_init(&sc->sc_pwr_mtx, MUTEX_DEFAULT, IPL_BIO); 391 cv_init(&sc->sc_pwr_cv, "pccpwr"); 392 393 callout_init(&sc->sc_insert_ch, 0); 394 callout_setfunc(&sc->sc_insert_ch, pci113x_insert, sc); 395 396 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 397 398 pci_aprint_devinfo(pa, NULL); 399 DPRINTF(("(chipflags %x)", flags)); 400 401 TAILQ_INIT(&sc->sc_memwindow); 402 TAILQ_INIT(&sc->sc_iowindow); 403 404 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 405 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 406 407 #if 0 408 printf("pa->pa_memt: %08x vs rbus_mem->rb_bt: %08x\n", 409 pa->pa_memt, sc->sc_rbus_memt->rb_bt); 410 #endif 411 412 sc->sc_flags &= ~CBB_MEMHMAPPED; 413 414 /* 415 * MAP socket registers and ExCA registers on memory-space 416 * When no valid address is set on socket base registers (on pci 417 * config space), get it not polite way. 418 */ 419 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 420 421 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 422 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 423 /* The address must be valid. */ 424 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 425 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 426 &sc->sc_base_size)) { 427 aprint_error_dev(self, 428 "can't map socket base address 0x%lx\n", 429 (unsigned long)sock_base); 430 /* 431 * I think it's funny: socket base registers must be 432 * mapped on memory space, but ... 433 */ 434 if (pci_mapreg_map(pa, PCI_SOCKBASE, 435 PCI_MAPREG_TYPE_IO, 0, &sc->sc_base_memt, 436 &sc->sc_base_memh, &sockbase, &sc->sc_base_size)) { 437 aprint_error_dev(self, 438 "can't map socket base address" 439 " 0x%lx: io mode\n", 440 (unsigned long)sockbase); 441 /* give up... allocate reg space via rbus. */ 442 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 443 } else 444 sc->sc_flags |= CBB_MEMHMAPPED; 445 } else { 446 DPRINTF(("%s: socket base address 0x%lx\n", 447 device_xname(self), (unsigned long)sockbase)); 448 sc->sc_flags |= CBB_MEMHMAPPED; 449 } 450 } 451 452 sc->sc_mem_start = 0; /* XXX */ 453 sc->sc_mem_end = 0xffffffff; /* XXX */ 454 455 /* pccbb_machdep.c end */ 456 457 #if defined CBB_DEBUG 458 { 459 static const char *intrname[] = { "NON", "A", "B", "C", "D" }; 460 aprint_debug_dev(self, "intrpin %s, intrtag %d\n", 461 intrname[pa->pa_intrpin], pa->pa_intrline); 462 } 463 #endif 464 465 /* setup softc */ 466 sc->sc_pc = pc; 467 sc->sc_iot = pa->pa_iot; 468 sc->sc_memt = pa->pa_memt; 469 sc->sc_dmat = pa->pa_dmat; 470 sc->sc_tag = pa->pa_tag; 471 472 memcpy(&sc->sc_pa, pa, sizeof(*pa)); 473 474 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 475 476 /* Disable legacy register mapping. */ 477 switch (sc->sc_chipset) { 478 case CB_RX5C46X: /* fallthrough */ 479 #if 0 480 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 481 case CB_RX5C47X: 482 #endif 483 /* 484 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 485 * cannot be disabled by substituting 0 into PCI_LEGACY 486 * register. Ricoh CardBus bridges have special bits on Bridge 487 * control reg (addr 0x3e on PCI config space). 488 */ 489 reg = pci_conf_read(pc, pa->pa_tag, PCI_BRIDGE_CONTROL_REG); 490 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 491 pci_conf_write(pc, pa->pa_tag, PCI_BRIDGE_CONTROL_REG, reg); 492 break; 493 494 default: 495 /* XXX I don't know proper way to kill legacy I/O. */ 496 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 497 break; 498 } 499 500 if (!pmf_device_register(self, pccbb_suspend, pccbb_resume)) 501 aprint_error_dev(self, "couldn't establish power handler\n"); 502 503 config_defer(self, pccbb_pci_callback); 504 } 505 506 int 507 pccbbdetach(device_t self, int flags) 508 { 509 struct pccbb_softc *sc = device_private(self); 510 pci_chipset_tag_t pc = sc->sc_pa.pa_pc; 511 bus_space_tag_t bmt = sc->sc_base_memt; 512 bus_space_handle_t bmh = sc->sc_base_memh; 513 uint32_t sockmask; 514 int rc; 515 516 if ((rc = config_detach_children(self, flags)) != 0) 517 return rc; 518 519 if (!LIST_EMPTY(&sc->sc_pil)) { 520 panic("%s: interrupt handlers still registered", 521 device_xname(self)); 522 return EBUSY; 523 } 524 525 if (sc->sc_ih != NULL) { 526 pci_intr_disestablish(pc, sc->sc_ih); 527 sc->sc_ih = NULL; 528 } 529 530 /* CSC Interrupt: turn off card detect and power cycle interrupts */ 531 sockmask = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 532 sockmask &= ~(CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | 533 CB_SOCKET_MASK_POWER); 534 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, sockmask); 535 /* reset interrupt */ 536 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 537 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 538 539 switch (sc->sc_flags & (CBB_MEMHMAPPED|CBB_SPECMAPPED)) { 540 case CBB_MEMHMAPPED: 541 bus_space_unmap(bmt, bmh, sc->sc_base_size); 542 break; 543 case CBB_MEMHMAPPED|CBB_SPECMAPPED: 544 #if rbus 545 { 546 rbus_space_free(sc->sc_rbus_memt, bmh, 0x1000, NULL); 547 } 548 #else 549 bus_space_free(bmt, bmh, 0x1000); 550 #endif 551 } 552 sc->sc_flags &= ~(CBB_MEMHMAPPED|CBB_SPECMAPPED); 553 554 if (!TAILQ_EMPTY(&sc->sc_iowindow)) 555 aprint_error_dev(self, "i/o windows not empty\n"); 556 if (!TAILQ_EMPTY(&sc->sc_memwindow)) 557 aprint_error_dev(self, "memory windows not empty\n"); 558 559 callout_halt(&sc->sc_insert_ch, NULL); 560 callout_destroy(&sc->sc_insert_ch); 561 562 mutex_destroy(&sc->sc_pwr_mtx); 563 cv_destroy(&sc->sc_pwr_cv); 564 565 return 0; 566 } 567 568 /* 569 * static void pccbb_pci_callback(device_t self) 570 * 571 * The actual attach routine: get memory space for YENTA register 572 * space, setup YENTA register and route interrupt. 573 * 574 * This function should be deferred because this device may obtain 575 * memory space dynamically. This function must avoid obtaining 576 * memory area which has already kept for another device. 577 */ 578 static void 579 pccbb_pci_callback(device_t self) 580 { 581 struct pccbb_softc *sc = device_private(self); 582 pci_chipset_tag_t pc = sc->sc_pc; 583 bus_addr_t sockbase; 584 struct cbslot_attach_args cba; 585 struct pcmciabus_attach_args paa; 586 struct cardslot_attach_args caa; 587 device_t csc; 588 589 if (!(sc->sc_flags & CBB_MEMHMAPPED)) { 590 /* The socket registers aren't mapped correctly. */ 591 #if rbus 592 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 593 (sc->sc_chipset == CB_RX5C47X 594 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 595 0, &sockbase, &sc->sc_base_memh)) { 596 return; 597 } 598 sc->sc_base_memt = sc->sc_memt; 599 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 600 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 601 device_xname(self), (unsigned long)sockbase, 602 (unsigned long)pci_conf_read(pc, sc->sc_tag, 603 PCI_SOCKBASE))); 604 #else 605 sc->sc_base_memt = sc->sc_memt; 606 #if !defined CBB_PCI_BASE 607 #define CBB_PCI_BASE 0x20000000 608 #endif 609 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 610 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 611 /* cannot allocate memory space */ 612 return; 613 } 614 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 615 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 616 device_xname(self), (unsigned long)sock_base, 617 (unsigned long)pci_conf_read(pc, 618 sc->sc_tag, PCI_SOCKBASE))); 619 #endif 620 sc->sc_flags |= CBB_MEMHMAPPED|CBB_SPECMAPPED; 621 } 622 623 /* clear data structure for child device interrupt handlers */ 624 LIST_INIT(&sc->sc_pil); 625 626 /* bus bridge initialization */ 627 pccbb_chipinit(sc); 628 629 sc->sc_pil_intr_enable = true; 630 631 { 632 uint32_t sockstat; 633 634 sockstat = bus_space_read_4(sc->sc_base_memt, 635 sc->sc_base_memh, CB_SOCKET_STAT); 636 if (0 == (sockstat & CB_SOCKET_STAT_CD)) 637 sc->sc_flags |= CBB_CARDEXIST; 638 } 639 640 /* 641 * attach cardbus 642 */ 643 { 644 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 645 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 646 647 /* initialize cbslot_attach */ 648 cba.cba_iot = sc->sc_iot; 649 cba.cba_memt = sc->sc_memt; 650 cba.cba_dmat = sc->sc_dmat; 651 cba.cba_bus = (busreg >> 8) & 0x0ff; 652 cba.cba_cc = (void *)sc; 653 cba.cba_cf = &pccbb_funcs; 654 655 #if rbus 656 cba.cba_rbus_iot = sc->sc_rbus_iot; 657 cba.cba_rbus_memt = sc->sc_rbus_memt; 658 #endif 659 660 cba.cba_cacheline = PCI_CACHELINE(bhlc); 661 cba.cba_max_lattimer = PCI_LATTIMER(bhlc); 662 663 aprint_verbose_dev(self, "cacheline 0x%x lattimer 0x%x\n", 664 cba.cba_cacheline, cba.cba_max_lattimer); 665 aprint_verbose_dev(self, "bhlc 0x%x\n", bhlc); 666 #if defined SHOW_REGS 667 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 668 sc->sc_base_memh); 669 #endif 670 } 671 672 pccbb_pcmcia_attach_setup(sc, &paa); 673 caa.caa_cb_attach = NULL; 674 if (cba.cba_bus == 0) 675 aprint_error_dev(self, 676 "secondary bus number uninitialized; try PCI_BUS_FIXUP\n"); 677 else 678 caa.caa_cb_attach = &cba; 679 caa.caa_16_attach = &paa; 680 681 pccbb_intrinit(sc); 682 683 if (NULL != (csc = config_found(self, &caa, cbbprint, 684 CFARG_IATTR, "pcmciaslot", 685 CFARG_EOL))) { 686 DPRINTF(("%s: found cardslot\n", __func__)); 687 sc->sc_csc = device_private(csc); 688 } 689 690 return; 691 } 692 693 694 695 696 697 /* 698 * static void pccbb_chipinit(struct pccbb_softc *sc) 699 * 700 * This function initialize YENTA chip registers listed below: 701 * 1) PCI command reg, 702 * 2) PCI and CardBus latency timer, 703 * 3) route PCI interrupt, 704 * 4) close all memory and io windows. 705 * 5) turn off bus power. 706 * 6) card detect and power cycle interrupts on. 707 * 7) clear interrupt 708 */ 709 static void 710 pccbb_chipinit(struct pccbb_softc *sc) 711 { 712 pci_chipset_tag_t pc = sc->sc_pc; 713 pcitag_t tag = sc->sc_tag; 714 bus_space_tag_t bmt = sc->sc_base_memt; 715 bus_space_handle_t bmh = sc->sc_base_memh; 716 pcireg_t bcr, bhlc, cbctl, csr, lscp, mfunc, mrburst, slotctl, sockctl, 717 sysctrl; 718 719 /* 720 * Set PCI command reg. 721 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 722 */ 723 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 724 /* I believe it is harmless. */ 725 csr |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 726 PCI_COMMAND_MASTER_ENABLE); 727 728 /* All O2 Micro chips have broken parity-error reporting 729 * until proven otherwise. The OZ6933 PCI-CardBus Bridge 730 * is known to have the defect---see PR kern/38698. 731 */ 732 if (sc->sc_chipset != CB_O2MICRO) 733 csr |= PCI_COMMAND_PARITY_ENABLE; 734 735 csr |= PCI_COMMAND_SERR_ENABLE; 736 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 737 738 /* 739 * Set CardBus latency timer. 740 */ 741 lscp = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 742 if (PCI_CB_LATENCY(lscp) < 0x20) { 743 lscp &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 744 lscp |= (0x20 << PCI_CB_LATENCY_SHIFT); 745 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, lscp); 746 } 747 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 748 PCI_CB_LATENCY(lscp), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 749 750 /* 751 * Set PCI latency timer. 752 */ 753 bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG); 754 if (PCI_LATTIMER(bhlc) < 0x10) { 755 bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 756 bhlc |= (0x10 << PCI_LATTIMER_SHIFT); 757 pci_conf_write(pc, tag, PCI_BHLC_REG, bhlc); 758 } 759 DPRINTF(("PCI latency timer 0x%x (%x)\n", 760 PCI_LATTIMER(bhlc), pci_conf_read(pc, tag, PCI_BHLC_REG))); 761 762 763 /* Route functional interrupts to PCI. */ 764 bcr = pci_conf_read(pc, tag, PCI_BRIDGE_CONTROL_REG); 765 bcr |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 766 bcr |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 767 /* assert reset */ 768 bcr |= PCI_BRIDGE_CONTROL_SECBR; 769 /* Set master abort mode to 1, forward SERR# from secondary 770 * to primary, and detect parity errors on secondary. 771 */ 772 bcr |= PCI_BRIDGE_CONTROL_MABRT; 773 bcr |= PCI_BRIDGE_CONTROL_SERR; 774 bcr |= PCI_BRIDGE_CONTROL_PERE; 775 pci_conf_write(pc, tag, PCI_BRIDGE_CONTROL_REG, bcr); 776 777 switch (sc->sc_chipset) { 778 case CB_TI113X: 779 cbctl = pci_conf_read(pc, tag, PCI_CBCTRL); 780 /* This bit is shared, but may read as 0 on some chips, so set 781 it explicitly on both functions. */ 782 cbctl |= PCI113X_CBCTRL_PCI_IRQ_ENA; 783 /* CSC intr enable */ 784 cbctl |= PCI113X_CBCTRL_PCI_CSC; 785 /* functional intr prohibit | prohibit ISA routing */ 786 cbctl &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 787 pci_conf_write(pc, tag, PCI_CBCTRL, cbctl); 788 break; 789 790 case CB_TI1420: 791 sysctrl = pci_conf_read(pc, tag, PCI_SYSCTRL); 792 mrburst = pccbb_burstup 793 ? PCI1420_SYSCTRL_MRBURST : PCI1420_SYSCTRL_MRBURSTDN; 794 if ((sysctrl & PCI1420_SYSCTRL_MRBURST) == mrburst) { 795 printf("%s: %swrite bursts enabled\n", 796 device_xname(sc->sc_dev), 797 pccbb_burstup ? "read/" : ""); 798 } else if (pccbb_burstup) { 799 printf("%s: enabling read/write bursts\n", 800 device_xname(sc->sc_dev)); 801 sysctrl |= PCI1420_SYSCTRL_MRBURST; 802 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 803 } else { 804 printf("%s: disabling read bursts, " 805 "enabling write bursts\n", 806 device_xname(sc->sc_dev)); 807 sysctrl |= PCI1420_SYSCTRL_MRBURSTDN; 808 sysctrl &= ~PCI1420_SYSCTRL_MRBURSTUP; 809 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 810 } 811 /*FALLTHROUGH*/ 812 case CB_TI12XX: 813 /* 814 * Some TI 12xx (and [14][45]xx) based pci cards 815 * sometimes have issues with the MFUNC register not 816 * being initialized due to a bad EEPROM on board. 817 * Laptops that this matters on have this register 818 * properly initialized. 819 * 820 * The TI125X parts have a different register. 821 */ 822 mfunc = pci_conf_read(pc, tag, PCI12XX_MFUNC); 823 if ((mfunc & (PCI12XX_MFUNC_PIN0 | PCI12XX_MFUNC_PIN1)) == 0) { 824 /* Enable PCI interrupt /INTA */ 825 mfunc |= PCI12XX_MFUNC_PIN0_INTA; 826 827 /* XXX this is TI1520 only */ 828 if ((pci_conf_read(pc, tag, PCI_SYSCTRL) & 829 PCI12XX_SYSCTRL_INTRTIE) == 0) 830 /* Enable PCI interrupt /INTB */ 831 mfunc |= PCI12XX_MFUNC_PIN1_INTB; 832 833 pci_conf_write(pc, tag, PCI12XX_MFUNC, mfunc); 834 } 835 /* fallthrough */ 836 837 case CB_TI125X: 838 /* 839 * Disable zoom video. Some machines initialize this 840 * improperly and experience has shown that this helps 841 * prevent strange behavior. 842 */ 843 pci_conf_write(pc, tag, PCI12XX_MMCTRL, 0); 844 845 sysctrl = pci_conf_read(pc, tag, PCI_SYSCTRL); 846 sysctrl |= PCI12XX_SYSCTRL_VCCPROT; 847 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 848 cbctl = pci_conf_read(pc, tag, PCI_CBCTRL); 849 cbctl |= PCI12XX_CBCTRL_CSC; 850 pci_conf_write(pc, tag, PCI_CBCTRL, cbctl); 851 break; 852 853 case CB_TOPIC95B: 854 sockctl = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 855 sockctl |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 856 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, sockctl); 857 slotctl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 858 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 859 device_xname(sc->sc_dev), slotctl)); 860 slotctl |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 861 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 862 slotctl &= ~TOPIC_SLOT_CTRL_SWDETECT; 863 DPRINTF(("0x%x\n", slotctl)); 864 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slotctl); 865 break; 866 867 case CB_TOPIC97: 868 slotctl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 869 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 870 device_xname(sc->sc_dev), slotctl)); 871 slotctl |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 872 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 873 slotctl &= ~TOPIC_SLOT_CTRL_SWDETECT; 874 slotctl |= TOPIC97_SLOT_CTRL_PCIINT; 875 slotctl &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 876 DPRINTF(("0x%x\n", slotctl)); 877 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slotctl); 878 /* make sure to assert LV card support bits */ 879 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 880 0x800 + 0x3e, 881 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 882 0x800 + 0x3e) | 0x03); 883 break; 884 } 885 886 /* Close all memory and I/O windows. */ 887 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 888 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 889 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 890 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 891 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 892 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 893 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 894 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 895 896 /* reset 16-bit pcmcia bus */ 897 bus_space_write_1(bmt, bmh, 0x800 + PCIC_INTR, 898 bus_space_read_1(bmt, bmh, 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 899 900 /* turn off power */ 901 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 902 } 903 904 static void 905 pccbb_intrinit(struct pccbb_softc *sc) 906 { 907 pcireg_t sockmask; 908 const char *intrstr = NULL; 909 pci_intr_handle_t ih; 910 pci_chipset_tag_t pc = sc->sc_pc; 911 bus_space_tag_t bmt = sc->sc_base_memt; 912 bus_space_handle_t bmh = sc->sc_base_memh; 913 char intrbuf[PCI_INTRSTR_LEN]; 914 915 /* Map and establish the interrupt. */ 916 if (pci_intr_map(&sc->sc_pa, &ih)) { 917 aprint_error_dev(sc->sc_dev, "couldn't map interrupt\n"); 918 return; 919 } 920 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 921 922 /* 923 * XXX pccbbintr should be called under the priority lower 924 * than any other hard interrupts. 925 */ 926 KASSERT(sc->sc_ih == NULL); 927 sc->sc_ih = pci_intr_establish_xname(pc, ih, IPL_BIO, pccbbintr, sc, 928 device_xname(sc->sc_dev)); 929 930 if (sc->sc_ih == NULL) { 931 aprint_error_dev(sc->sc_dev, "couldn't establish interrupt"); 932 if (intrstr != NULL) 933 aprint_error(" at %s\n", intrstr); 934 else 935 aprint_error("\n"); 936 return; 937 } 938 939 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 940 941 /* CSC Interrupt: Card detect and power cycle interrupts on */ 942 sockmask = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 943 sockmask |= CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | 944 CB_SOCKET_MASK_POWER; 945 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, sockmask); 946 /* reset interrupt */ 947 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 948 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 949 } 950 951 /* 952 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 953 * struct pcmciabus_attach_args *paa) 954 * 955 * This function attaches 16-bit PCcard bus. 956 */ 957 STATIC void 958 pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 959 struct pcmciabus_attach_args *paa) 960 { 961 /* 962 * We need to do a few things here: 963 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 964 * setting the IRQ numbers to 0. 965 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 966 * routing of CSC interrupts (e.g. card removal) to PCI while in 967 * PCMCIA mode. We just leave this set all the time. 968 * 3) Enable card insertion/removal interrupts in case the chip also 969 * needs that while in PCMCIA mode. 970 * 4) Clear any pending CSC interrupt. 971 */ 972 Pcic_write(sc, PCIC_INTR, PCIC_INTR_ENABLE); 973 if (sc->sc_chipset == CB_TI113X) { 974 Pcic_write(sc, PCIC_CSC_INTR, 0); 975 } else { 976 Pcic_write(sc, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 977 Pcic_read(sc, PCIC_CSC); 978 } 979 980 /* initialize pcmcia bus attachment */ 981 paa->paa_busname = "pcmcia"; 982 paa->pct = &pccbb_pcmcia_funcs; 983 paa->pch = sc; 984 return; 985 } 986 987 /* 988 * int pccbbintr(arg) 989 * void *arg; 990 * This routine handles the interrupt from Yenta PCI-CardBus bridge 991 * itself. 992 */ 993 int 994 pccbbintr(void *arg) 995 { 996 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 997 struct cardslot_softc *csc; 998 uint32_t sockevent, sockstate; 999 bus_space_tag_t memt = sc->sc_base_memt; 1000 bus_space_handle_t memh = sc->sc_base_memh; 1001 1002 if (!device_has_power(sc->sc_dev)) 1003 return 0; 1004 1005 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 1006 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 1007 Pcic_read(sc, PCIC_CSC); 1008 1009 if (sockevent != 0) { 1010 DPRINTF(("%s: enter sockevent %" PRIx32 "\n", 1011 __func__, sockevent)); 1012 } 1013 1014 /* XXX sockevent == CB_SOCKET_EVENT_CSTS|CB_SOCKET_EVENT_POWER 1015 * does occur in the wild. Check for a _POWER event before 1016 * possibly exiting because of an _CSTS event. 1017 */ 1018 if (sockevent & CB_SOCKET_EVENT_POWER) { 1019 DPRINTF(("Powercycling because of socket event\n")); 1020 /* XXX: Does not happen when attaching a 16-bit card */ 1021 mutex_enter(&sc->sc_pwr_mtx); 1022 sc->sc_pwrcycle++; 1023 cv_signal(&sc->sc_pwr_cv); 1024 mutex_exit(&sc->sc_pwr_mtx); 1025 } 1026 1027 /* Sometimes a change of CSTSCHG# accompanies the first 1028 * interrupt from an Atheros WLAN. That generates a 1029 * CB_SOCKET_EVENT_CSTS event on the bridge. The event 1030 * isn't interesting to pccbb(4), so we used to ignore the 1031 * interrupt. Now, let the child devices try to handle 1032 * the interrupt, instead. The Atheros NIC produces 1033 * interrupts more reliably, now: used to be that it would 1034 * only interrupt if the driver avoided powering down the 1035 * NIC's cardslot, and then the NIC would only work after 1036 * it was reset a second time. 1037 */ 1038 if (sockevent == 0 || 1039 (sockevent & ~(CB_SOCKET_EVENT_POWER|CB_SOCKET_EVENT_CD)) != 0) { 1040 /* This intr is not for me: it may be for my child devices. */ 1041 if (sc->sc_pil_intr_enable) { 1042 return pccbbintr_function(sc); 1043 } else { 1044 return 0; 1045 } 1046 } 1047 1048 if (sockevent & CB_SOCKET_EVENT_CD) { 1049 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1050 if (0x00 != (sockstate & CB_SOCKET_STAT_CD)) { 1051 /* A card should be removed. */ 1052 if (sc->sc_flags & CBB_CARDEXIST) { 1053 DPRINTF(("%s: 0x%08x", 1054 device_xname(sc->sc_dev), sockevent)); 1055 DPRINTF((" card removed, 0x%08x\n", sockstate)); 1056 sc->sc_flags &= ~CBB_CARDEXIST; 1057 if ((csc = sc->sc_csc) == NULL) 1058 ; 1059 else if (csc->sc_status & 1060 CARDSLOT_STATUS_CARD_16) { 1061 cardslot_event_throw(csc, 1062 CARDSLOT_EVENT_REMOVAL_16); 1063 } else if (csc->sc_status & 1064 CARDSLOT_STATUS_CARD_CB) { 1065 /* Cardbus intr removed */ 1066 cardslot_event_throw(csc, 1067 CARDSLOT_EVENT_REMOVAL_CB); 1068 } 1069 } else if (sc->sc_flags & CBB_INSERTING) { 1070 sc->sc_flags &= ~CBB_INSERTING; 1071 callout_stop(&sc->sc_insert_ch); 1072 } 1073 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 1074 /* 1075 * The pccbbintr may called from powerdown hook when 1076 * the system resumed, to detect the card 1077 * insertion/removal during suspension. 1078 */ 1079 (sc->sc_flags & CBB_CARDEXIST) == 0) { 1080 if (sc->sc_flags & CBB_INSERTING) { 1081 callout_stop(&sc->sc_insert_ch); 1082 } 1083 callout_schedule(&sc->sc_insert_ch, mstohz(200)); 1084 sc->sc_flags |= CBB_INSERTING; 1085 } 1086 } 1087 1088 return 1; 1089 } 1090 1091 /* 1092 * static int pccbbintr_function(struct pccbb_softc *sc) 1093 * 1094 * This function calls each interrupt handler registered at the 1095 * bridge. The interrupt handlers are called in registered order. 1096 */ 1097 static int 1098 pccbbintr_function(struct pccbb_softc *sc) 1099 { 1100 int retval = 0, val; 1101 struct pccbb_intrhand_list *pil; 1102 int s; 1103 1104 LIST_FOREACH(pil, &sc->sc_pil, pil_next) { 1105 s = splraiseipl(pil->pil_icookie); 1106 val = (*pil->pil_func)(pil->pil_arg); 1107 splx(s); 1108 1109 retval = retval == 1 ? 1 : 1110 retval == 0 ? val : val != 0 ? val : retval; 1111 } 1112 1113 return retval; 1114 } 1115 1116 static void 1117 pci113x_insert(void *arg) 1118 { 1119 struct pccbb_softc *sc = arg; 1120 struct cardslot_softc *csc; 1121 uint32_t sockevent, sockstate; 1122 1123 if (!(sc->sc_flags & CBB_INSERTING)) { 1124 /* We add a card only under inserting state. */ 1125 return; 1126 } 1127 sc->sc_flags &= ~CBB_INSERTING; 1128 1129 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1130 CB_SOCKET_EVENT); 1131 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1132 CB_SOCKET_STAT); 1133 1134 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1135 #ifdef CBB_DEBUG 1136 DPRINTF(("%s: 0x%08x", device_xname(sc->sc_dev), sockevent)); 1137 #else 1138 __USE(sockevent); 1139 #endif 1140 1141 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1142 sc->sc_flags |= CBB_CARDEXIST; 1143 /* call pccard interrupt handler here */ 1144 if ((csc = sc->sc_csc) == NULL) 1145 ; 1146 else if (sockstate & CB_SOCKET_STAT_16BIT) { 1147 /* 16-bit card found */ 1148 cardslot_event_throw(csc, CARDSLOT_EVENT_INSERTION_16); 1149 } else if (sockstate & CB_SOCKET_STAT_CB) { 1150 /* cardbus card found */ 1151 cardslot_event_throw(csc, CARDSLOT_EVENT_INSERTION_CB); 1152 } else { 1153 /* who are you? */ 1154 } 1155 } else 1156 callout_schedule(&sc->sc_insert_ch, mstohz(100)); 1157 } 1158 1159 #define PCCBB_PCMCIA_OFFSET 0x800 1160 static uint8_t 1161 pccbb_pcmcia_read(struct pccbb_softc *sc, int reg) 1162 { 1163 bus_space_barrier(sc->sc_base_memt, sc->sc_base_memh, 1164 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1165 1166 return bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 1167 PCCBB_PCMCIA_OFFSET + reg); 1168 } 1169 1170 static void 1171 pccbb_pcmcia_write(struct pccbb_softc *sc, int reg, uint8_t val) 1172 { 1173 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 1174 PCCBB_PCMCIA_OFFSET + reg, val); 1175 1176 bus_space_barrier(sc->sc_base_memt, sc->sc_base_memh, 1177 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1178 } 1179 1180 /* 1181 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1182 */ 1183 STATIC int 1184 pccbb_ctrl(cardbus_chipset_tag_t ct, int command) 1185 { 1186 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1187 1188 switch (command) { 1189 case CARDBUS_CD: 1190 if (2 == pccbb_detect_card(sc)) { 1191 int retval = 0; 1192 int status = cb_detect_voltage(sc); 1193 if (PCCARD_VCC_5V & status) { 1194 retval |= CARDBUS_5V_CARD; 1195 } 1196 if (PCCARD_VCC_3V & status) { 1197 retval |= CARDBUS_3V_CARD; 1198 } 1199 if (PCCARD_VCC_XV & status) { 1200 retval |= CARDBUS_XV_CARD; 1201 } 1202 if (PCCARD_VCC_YV & status) { 1203 retval |= CARDBUS_YV_CARD; 1204 } 1205 return retval; 1206 } else { 1207 return 0; 1208 } 1209 case CARDBUS_RESET: 1210 return cb_reset(sc); 1211 case CARDBUS_IO_ENABLE: /* fallthrough */ 1212 case CARDBUS_IO_DISABLE: /* fallthrough */ 1213 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1214 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1215 case CARDBUS_BM_ENABLE: /* fallthrough */ 1216 case CARDBUS_BM_DISABLE: /* fallthrough */ 1217 /* XXX: I think we don't need to call this function below. */ 1218 return pccbb_cardenable(sc, command); 1219 } 1220 1221 return 0; 1222 } 1223 1224 STATIC int 1225 pccbb_power_ct(cardbus_chipset_tag_t ct, int command) 1226 { 1227 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1228 1229 return pccbb_power(sc, command); 1230 } 1231 1232 /* 1233 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1234 * This function returns true when it succeeds and returns false when 1235 * it fails. 1236 */ 1237 STATIC int 1238 pccbb_power(struct pccbb_softc *sc, int command) 1239 { 1240 uint32_t status, osock_ctrl, sock_ctrl, reg_ctrl; 1241 bus_space_tag_t memt = sc->sc_base_memt; 1242 bus_space_handle_t memh = sc->sc_base_memh; 1243 int on = 0, pwrcycle, times; 1244 struct timeval before, after, diff; 1245 1246 DPRINTF(("pccbb_power: %s and %s [0x%x]\n", 1247 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1248 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1249 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1250 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1251 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1252 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1253 "UNKNOWN", 1254 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1255 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1256 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1257 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1258 "UNKNOWN", command)); 1259 1260 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1261 osock_ctrl = sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1262 1263 switch (command & CARDBUS_VCCMASK) { 1264 case CARDBUS_VCC_UC: 1265 break; 1266 case CARDBUS_VCC_5V: 1267 on++; 1268 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1269 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1270 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1271 } else { 1272 aprint_error_dev(sc->sc_dev, 1273 "BAD voltage request: no 5 V card\n"); 1274 return 0; 1275 } 1276 break; 1277 case CARDBUS_VCC_3V: 1278 on++; 1279 if (CB_SOCKET_STAT_3VCARD & status) { 1280 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1281 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1282 } else { 1283 aprint_error_dev(sc->sc_dev, 1284 "BAD voltage request: no 3.3 V card\n"); 1285 return 0; 1286 } 1287 break; 1288 case CARDBUS_VCC_0V: 1289 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1290 break; 1291 default: 1292 return 0; /* power NEVER changed */ 1293 } 1294 1295 switch (command & CARDBUS_VPPMASK) { 1296 case CARDBUS_VPP_UC: 1297 break; 1298 case CARDBUS_VPP_0V: 1299 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1300 break; 1301 case CARDBUS_VPP_VCC: 1302 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1303 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1304 break; 1305 case CARDBUS_VPP_12V: 1306 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1307 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1308 break; 1309 } 1310 aprint_debug_dev(sc->sc_dev, "osock_ctrl %#" PRIx32 1311 " sock_ctrl %#" PRIx32 "\n", osock_ctrl, sock_ctrl); 1312 1313 microtime(&before); 1314 mutex_enter(&sc->sc_pwr_mtx); 1315 pwrcycle = sc->sc_pwrcycle; 1316 1317 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1318 1319 /* 1320 * Wait as long as 200ms for a power-cycle interrupt. If 1321 * interrupts are enabled, but the socket has already 1322 * changed to the desired status, keep waiting for the 1323 * interrupt. "Consuming" the interrupt in this way keeps 1324 * the interrupt from prematurely waking some subsequent 1325 * pccbb_power call. 1326 * 1327 * XXX Not every bridge interrupts on the ->OFF transition. 1328 * XXX That's ok, we will time-out after 200ms. 1329 * 1330 * XXX The power cycle event will never happen when attaching 1331 * XXX a 16-bit card. That's ok, we will time-out after 1332 * XXX 200ms. 1333 */ 1334 for (times = 5; --times >= 0; ) { 1335 if (cold) 1336 DELAY(40 * 1000); 1337 else { 1338 (void)cv_timedwait(&sc->sc_pwr_cv, &sc->sc_pwr_mtx, 1339 mstohz(40)); 1340 if (pwrcycle == sc->sc_pwrcycle) 1341 continue; 1342 } 1343 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1344 if ((status & CB_SOCKET_STAT_PWRCYCLE) != 0 && on) 1345 break; 1346 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0 && !on) 1347 break; 1348 } 1349 mutex_exit(&sc->sc_pwr_mtx); 1350 microtime(&after); 1351 timersub(&after, &before, &diff); 1352 aprint_debug_dev(sc->sc_dev, "wait took%s %lld.%06lds\n", 1353 (on && times < 0) ? " too long" : "", (long long)diff.tv_sec, 1354 (long)diff.tv_usec); 1355 1356 /* 1357 * Ok, wait a bit longer for things to settle. 1358 */ 1359 if (on && sc->sc_chipset == CB_TOPIC95B) 1360 delay_ms(100, sc); 1361 1362 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1363 1364 if (on && sc->sc_chipset != CB_TOPIC95B) { 1365 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0) 1366 aprint_error_dev(sc->sc_dev, "power on failed?\n"); 1367 } 1368 1369 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1370 aprint_error_dev(sc->sc_dev, 1371 "bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1372 sock_ctrl, status); 1373 aprint_error_dev(sc->sc_dev, "disabling socket\n"); 1374 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1375 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1376 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1377 status &= ~CB_SOCKET_STAT_BADVCC; 1378 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, status); 1379 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1380 CB_SOCKET_STAT)); 1381 return 0; 1382 } 1383 1384 if (sc->sc_chipset == CB_TOPIC97) { 1385 reg_ctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL); 1386 reg_ctrl &= ~TOPIC97_REG_CTRL_TESTMODE; 1387 if ((command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V) 1388 reg_ctrl &= ~TOPIC97_REG_CTRL_CLKRUN_ENA; 1389 else 1390 reg_ctrl |= TOPIC97_REG_CTRL_CLKRUN_ENA; 1391 pci_conf_write(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL, reg_ctrl); 1392 } 1393 1394 return 1; /* power changed correctly */ 1395 } 1396 1397 /* 1398 * static int pccbb_detect_card(struct pccbb_softc *sc) 1399 * return value: 0 if no card exists. 1400 * 1 if 16-bit card exists. 1401 * 2 if cardbus card exists. 1402 */ 1403 static int 1404 pccbb_detect_card(struct pccbb_softc *sc) 1405 { 1406 bus_space_handle_t base_memh = sc->sc_base_memh; 1407 bus_space_tag_t base_memt = sc->sc_base_memt; 1408 uint32_t sockstat = 1409 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1410 int retval = 0; 1411 1412 /* CD1 and CD2 asserted */ 1413 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1414 /* card must be present */ 1415 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1416 /* NOTACARD DEASSERTED */ 1417 if (CB_SOCKET_STAT_CB & sockstat) { 1418 /* CardBus mode */ 1419 retval = 2; 1420 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1421 /* 16-bit mode */ 1422 retval = 1; 1423 } 1424 } 1425 } 1426 return retval; 1427 } 1428 1429 /* 1430 * STATIC int cb_reset(struct pccbb_softc *sc) 1431 * This function resets CardBus card. 1432 */ 1433 STATIC int 1434 cb_reset(struct pccbb_softc *sc) 1435 { 1436 /* 1437 * Reset Assert at least 20 ms 1438 * Some machines request longer duration. 1439 */ 1440 int reset_duration = 1441 (sc->sc_chipset == CB_RX5C47X ? 400 : 50); 1442 uint32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, 1443 PCI_BRIDGE_CONTROL_REG); 1444 aprint_debug("%s: enter bcr %" PRIx32 "\n", __func__, bcr); 1445 1446 /* Reset bit Assert (bit 6 at 0x3E) */ 1447 bcr |= PCI_BRIDGE_CONTROL_SECBR; 1448 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr); 1449 aprint_debug("%s: wrote bcr %" PRIx32 "\n", __func__, bcr); 1450 delay_ms(reset_duration, sc); 1451 1452 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1453 /* Reset bit Deassert (bit 6 at 0x3E) */ 1454 bcr &= ~(PCI_BRIDGE_CONTROL_SECBR); 1455 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, 1456 bcr); 1457 aprint_debug("%s: wrote bcr %" PRIx32 "\n", __func__, bcr); 1458 delay_ms(reset_duration, sc); 1459 aprint_debug("%s: end of delay\n", __func__); 1460 } 1461 /* No card found on the slot. Keep Reset. */ 1462 return 1; 1463 } 1464 1465 /* 1466 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1467 * This function detect card Voltage. 1468 */ 1469 STATIC int 1470 cb_detect_voltage(struct pccbb_softc *sc) 1471 { 1472 uint32_t psr; /* socket present-state reg */ 1473 bus_space_tag_t iot = sc->sc_base_memt; 1474 bus_space_handle_t ioh = sc->sc_base_memh; 1475 int vol = PCCARD_VCC_UKN; /* set 0 */ 1476 1477 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1478 1479 if (0x400u & psr) 1480 vol |= PCCARD_VCC_5V; 1481 1482 if (0x800u & psr) 1483 vol |= PCCARD_VCC_3V; 1484 1485 return vol; 1486 } 1487 1488 STATIC int 1489 cbbprint(void *aux, const char *pcic) 1490 { 1491 #if 0 1492 struct cbslot_attach_args *cba = aux; 1493 1494 if (cba->cba_slot >= 0) 1495 aprint_normal(" slot %d", cba->cba_slot); 1496 #endif 1497 return UNCONF; 1498 } 1499 1500 /* 1501 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1502 * This function enables and disables the card 1503 */ 1504 STATIC int 1505 pccbb_cardenable(struct pccbb_softc *sc, int function) 1506 { 1507 uint32_t command = 1508 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1509 1510 DPRINTF(("pccbb_cardenable:")); 1511 switch (function) { 1512 case CARDBUS_IO_ENABLE: 1513 command |= PCI_COMMAND_IO_ENABLE; 1514 break; 1515 case CARDBUS_IO_DISABLE: 1516 command &= ~PCI_COMMAND_IO_ENABLE; 1517 break; 1518 case CARDBUS_MEM_ENABLE: 1519 command |= PCI_COMMAND_MEM_ENABLE; 1520 break; 1521 case CARDBUS_MEM_DISABLE: 1522 command &= ~PCI_COMMAND_MEM_ENABLE; 1523 break; 1524 case CARDBUS_BM_ENABLE: 1525 command |= PCI_COMMAND_MASTER_ENABLE; 1526 break; 1527 case CARDBUS_BM_DISABLE: 1528 command &= ~PCI_COMMAND_MASTER_ENABLE; 1529 break; 1530 default: 1531 return 0; 1532 } 1533 1534 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1535 DPRINTF((" command reg 0x%x\n", command)); 1536 return 1; 1537 } 1538 1539 #if !rbus 1540 static int 1541 pccbb_io_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 1542 { 1543 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1544 int basereg; 1545 int limitreg; 1546 1547 if ((win < 0) || (win > 2)) { 1548 #if defined DIAGNOSTIC 1549 printf("cardbus_io_open: window out of range %d\n", win); 1550 #endif 1551 return 0; 1552 } 1553 1554 basereg = win * 8 + PCI_CB_IOBASE0; 1555 limitreg = win * 8 + PCI_CB_IOLIMIT0; 1556 1557 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1558 start, basereg, end, limitreg)); 1559 1560 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1561 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1562 return 1; 1563 } 1564 1565 /* 1566 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1567 */ 1568 static int 1569 pccbb_io_close(cardbus_chipset_tag_t ct, int win) 1570 { 1571 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1572 int basereg; 1573 int limitreg; 1574 1575 if ((win < 0) || (win > 2)) { 1576 #if defined DIAGNOSTIC 1577 printf("cardbus_io_close: window out of range %d\n", win); 1578 #endif 1579 return 0; 1580 } 1581 1582 basereg = win * 8 + PCI_CB_IOBASE0; 1583 limitreg = win * 8 + PCI_CB_IOLIMIT0; 1584 1585 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1586 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1587 return 1; 1588 } 1589 1590 static int 1591 pccbb_mem_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 1592 { 1593 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1594 int basereg; 1595 int limitreg; 1596 1597 if ((win < 0) || (win > 2)) { 1598 #if defined DIAGNOSTIC 1599 printf("cardbus_mem_open: window out of range %d\n", win); 1600 #endif 1601 return 0; 1602 } 1603 1604 basereg = win * 8 + PCI_CB_MEMBASE0; 1605 limitreg = win * 8 + PCI_CB_MEMLIMIT0; 1606 1607 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1608 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1609 return 1; 1610 } 1611 1612 static int 1613 pccbb_mem_close(cardbus_chipset_tag_t ct, int win) 1614 { 1615 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1616 int basereg; 1617 int limitreg; 1618 1619 if ((win < 0) || (win > 2)) { 1620 #if defined DIAGNOSTIC 1621 printf("cardbus_mem_close: window out of range %d\n", win); 1622 #endif 1623 return 0; 1624 } 1625 1626 basereg = win * 8 + PCI_CB_MEMBASE0; 1627 limitreg = win * 8 + PCI_CB_MEMLIMIT0; 1628 1629 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1630 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1631 return 1; 1632 } 1633 #endif 1634 1635 /* 1636 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1637 * int level, 1638 * int (* func)(void *), 1639 * void *arg) 1640 * 1641 * This function registers an interrupt handler at the bridge, in 1642 * order not to call the interrupt handlers of child devices when 1643 * a card-deletion interrupt occurs. 1644 * 1645 * The argument level is not used. 1646 */ 1647 static void * 1648 pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, int level, 1649 int (*func)(void *), void *arg) 1650 { 1651 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1652 1653 return pccbb_intr_establish(sc, level, func, arg); 1654 } 1655 1656 1657 /* 1658 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1659 * void *ih) 1660 * 1661 * This function removes an interrupt handler pointed by ih. 1662 */ 1663 static void 1664 pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih) 1665 { 1666 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1667 1668 pccbb_intr_disestablish(sc, ih); 1669 } 1670 1671 1672 void 1673 pccbb_intr_route(struct pccbb_softc *sc) 1674 { 1675 pcireg_t bcr, cbctrl; 1676 1677 /* initialize bridge intr routing */ 1678 bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1679 bcr &= ~CB_BCR_INTR_IREQ_ENABLE; 1680 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr); 1681 1682 switch (sc->sc_chipset) { 1683 case CB_TI113X: 1684 cbctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1685 /* functional intr enabled */ 1686 cbctrl |= PCI113X_CBCTRL_PCI_INTR; 1687 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, cbctrl); 1688 break; 1689 default: 1690 break; 1691 } 1692 } 1693 1694 /* 1695 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1696 * int irq, 1697 * int level, 1698 * int (* func)(void *), 1699 * void *arg) 1700 * 1701 * This function registers an interrupt handler at the bridge, in 1702 * order not to call the interrupt handlers of child devices when 1703 * a card-deletion interrupt occurs. 1704 * 1705 */ 1706 static void * 1707 pccbb_intr_establish(struct pccbb_softc *sc, int level, 1708 int (*func)(void *), void *arg) 1709 { 1710 struct pccbb_intrhand_list *pil, *newpil; 1711 1712 DPRINTF(("pccbb_intr_establish start. %p\n", LIST_FIRST(&sc->sc_pil))); 1713 1714 if (LIST_EMPTY(&sc->sc_pil)) 1715 pccbb_intr_route(sc); 1716 1717 /* 1718 * Allocate a room for interrupt handler structure. 1719 */ 1720 if (NULL == (newpil = 1721 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1722 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1723 return NULL; 1724 } 1725 1726 newpil->pil_func = func; 1727 newpil->pil_arg = arg; 1728 newpil->pil_icookie = makeiplcookie(level); 1729 1730 if (LIST_EMPTY(&sc->sc_pil)) { 1731 LIST_INSERT_HEAD(&sc->sc_pil, newpil, pil_next); 1732 } else { 1733 for (pil = LIST_FIRST(&sc->sc_pil); 1734 LIST_NEXT(pil, pil_next) != NULL; 1735 pil = LIST_NEXT(pil, pil_next)); 1736 LIST_INSERT_AFTER(pil, newpil, pil_next); 1737 } 1738 1739 DPRINTF(("pccbb_intr_establish add pil. %p\n", 1740 LIST_FIRST(&sc->sc_pil))); 1741 1742 return newpil; 1743 } 1744 1745 /* 1746 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1747 * void *ih) 1748 * 1749 * This function removes an interrupt handler pointed by ih. ih 1750 * should be the value returned by cardbus_intr_establish() or 1751 * NULL. 1752 * 1753 * When ih is NULL, this function will do nothing. 1754 */ 1755 static void 1756 pccbb_intr_disestablish(struct pccbb_softc *sc, void *ih) 1757 { 1758 struct pccbb_intrhand_list *pil; 1759 pcireg_t reg; 1760 1761 DPRINTF(("pccbb_intr_disestablish start. %p\n", 1762 LIST_FIRST(&sc->sc_pil))); 1763 1764 if (ih == NULL) { 1765 /* intr handler is not set */ 1766 DPRINTF(("pccbb_intr_disestablish: no ih\n")); 1767 return; 1768 } 1769 1770 #ifdef DIAGNOSTIC 1771 LIST_FOREACH(pil, &sc->sc_pil, pil_next) { 1772 DPRINTF(("pccbb_intr_disestablish: pil %p\n", pil)); 1773 if (pil == ih) { 1774 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1775 break; 1776 } 1777 } 1778 if (pil == NULL) { 1779 panic("pccbb_intr_disestablish: %s cannot find pil %p", 1780 device_xname(sc->sc_dev), ih); 1781 } 1782 #endif 1783 1784 pil = (struct pccbb_intrhand_list *)ih; 1785 LIST_REMOVE(pil, pil_next); 1786 free(pil, M_DEVBUF); 1787 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1788 1789 if (LIST_EMPTY(&sc->sc_pil)) { 1790 /* No interrupt handlers */ 1791 1792 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1793 1794 /* stop routing PCI intr */ 1795 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, 1796 PCI_BRIDGE_CONTROL_REG); 1797 reg |= CB_BCR_INTR_IREQ_ENABLE; 1798 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, 1799 reg); 1800 1801 switch (sc->sc_chipset) { 1802 case CB_TI113X: 1803 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1804 /* functional intr disabled */ 1805 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1806 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1807 break; 1808 default: 1809 break; 1810 } 1811 } 1812 } 1813 1814 #if defined SHOW_REGS 1815 static void 1816 cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, bus_space_tag_t memt, 1817 bus_space_handle_t memh) 1818 { 1819 int i; 1820 printf("PCI config regs:"); 1821 for (i = 0; i < 0x50; i += 4) { 1822 if (i % 16 == 0) 1823 printf("\n 0x%02x:", i); 1824 printf(" %08x", pci_conf_read(pc, tag, i)); 1825 } 1826 for (i = 0x80; i < 0xb0; i += 4) { 1827 if (i % 16 == 0) 1828 printf("\n 0x%02x:", i); 1829 printf(" %08x", pci_conf_read(pc, tag, i)); 1830 } 1831 1832 if (memh == 0) { 1833 printf("\n"); 1834 return; 1835 } 1836 1837 printf("\nsocket regs:"); 1838 for (i = 0; i <= 0x10; i += 0x04) 1839 printf(" %08x", bus_space_read_4(memt, memh, i)); 1840 printf("\nExCA regs:"); 1841 for (i = 0; i < 0x08; ++i) 1842 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1843 printf("\n"); 1844 return; 1845 } 1846 #endif 1847 1848 /* 1849 * static pcitag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1850 * int busno, int function) 1851 * This is the function to make a tag to access config space of 1852 * a CardBus Card. It works same as pci_conf_read. 1853 */ 1854 static pcitag_t 1855 pccbb_make_tag(cardbus_chipset_tag_t cc, int busno, int function) 1856 { 1857 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1858 1859 return pci_make_tag(sc->sc_pc, busno, 0, function); 1860 } 1861 1862 /* 1863 * pccbb_conf_read 1864 * 1865 * This is the function to read the config space of a CardBus card. 1866 * It works the same as pci_conf_read(9). 1867 */ 1868 static pcireg_t 1869 pccbb_conf_read(cardbus_chipset_tag_t cc, pcitag_t tag, int offset) 1870 { 1871 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1872 pcitag_t brtag = sc->sc_tag; 1873 pcireg_t reg; 1874 1875 /* 1876 * clear cardbus master abort status; it is OK to write without 1877 * reading before because all bits are r/o or w1tc 1878 */ 1879 pci_conf_write(sc->sc_pc, brtag, PCI_CBB_SECSTATUS, 1880 CBB_SECSTATUS_CBMABORT); 1881 reg = pci_conf_read(sc->sc_pc, tag, offset); 1882 /* check cardbus master abort status */ 1883 if (pci_conf_read(sc->sc_pc, brtag, PCI_CBB_SECSTATUS) 1884 & CBB_SECSTATUS_CBMABORT) 1885 return 0xffffffff; 1886 return reg; 1887 } 1888 1889 /* 1890 * pccbb_conf_write 1891 * 1892 * This is the function to write the config space of a CardBus 1893 * card. It works the same as pci_conf_write(9). 1894 */ 1895 static void 1896 pccbb_conf_write(cardbus_chipset_tag_t cc, pcitag_t tag, int reg, pcireg_t val) 1897 { 1898 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1899 1900 pci_conf_write(sc->sc_pc, tag, reg, val); 1901 } 1902 1903 #if 0 1904 STATIC int 1905 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1906 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 1907 int speed, int flags, 1908 bus_space_handle_t * iohp) 1909 #endif 1910 /* 1911 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1912 * bus_addr_t start, bus_size_t size, 1913 * bus_size_t align, 1914 * struct pcmcia_io_handle *pcihp 1915 * 1916 * This function only allocates I/O region for pccard. This function 1917 * never maps the allocated region to pccard I/O area. 1918 * 1919 * XXX: The interface of this function is not very good, I believe. 1920 */ 1921 STATIC int 1922 pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, 1923 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 1924 { 1925 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 1926 bus_addr_t ioaddr; 1927 int flags = 0; 1928 bus_space_tag_t iot; 1929 bus_space_handle_t ioh; 1930 bus_addr_t mask; 1931 #if rbus 1932 rbus_tag_t rb; 1933 #endif 1934 if (align == 0) 1935 align = size; /* XXX: funny??? */ 1936 1937 if (start != 0) { 1938 /* XXX: assume all card decode lower 10 bits by its hardware */ 1939 mask = 0x3ff; 1940 /* enforce to use only masked address */ 1941 start &= mask; 1942 } else { 1943 /* 1944 * calculate mask: 1945 * 1. get the most significant bit of size (call it msb). 1946 * 2. compare msb with the value of size. 1947 * 3. if size is larger, shift msb left once. 1948 * 4. obtain mask value to decrement msb. 1949 */ 1950 bus_size_t size_tmp = size; 1951 int shifts = 0; 1952 1953 mask = 1; 1954 while (size_tmp) { 1955 ++shifts; 1956 size_tmp >>= 1; 1957 } 1958 mask = (1 << shifts); 1959 if (mask < size) { 1960 mask <<= 1; 1961 } 1962 --mask; 1963 } 1964 1965 /* 1966 * Allocate some arbitrary I/O space. 1967 */ 1968 1969 iot = sc->sc_iot; 1970 1971 #if rbus 1972 rb = sc->sc_rbus_iot; 1973 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 1974 return 1; 1975 } 1976 DPRINTF(("pccbb_pcmcia_io_alloc alloc port 0x%lx+0x%lx\n", 1977 (u_long) ioaddr, (u_long) size)); 1978 #else 1979 if (start) { 1980 ioaddr = start; 1981 if (bus_space_map(iot, start, size, 0, &ioh)) { 1982 return 1; 1983 } 1984 DPRINTF(("pccbb_pcmcia_io_alloc map port 0x%lx+0x%lx\n", 1985 (u_long) ioaddr, (u_long) size)); 1986 } else { 1987 flags |= PCMCIA_IO_ALLOCATED; 1988 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 1989 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 1990 size, align, 0, 0, &ioaddr, &ioh)) { 1991 /* No room be able to be get. */ 1992 return 1; 1993 } 1994 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 1995 (u_long) ioaddr, (u_long) size)); 1996 } 1997 #endif 1998 1999 pcihp->iot = iot; 2000 pcihp->ioh = ioh; 2001 pcihp->addr = ioaddr; 2002 pcihp->size = size; 2003 pcihp->flags = flags; 2004 2005 return 0; 2006 } 2007 2008 /* 2009 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2010 * struct pcmcia_io_handle *pcihp) 2011 * 2012 * This function only frees I/O region for pccard. 2013 * 2014 * XXX: The interface of this function is not very good, I believe. 2015 */ 2016 void 2017 pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2018 struct pcmcia_io_handle *pcihp) 2019 { 2020 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2021 #if !rbus 2022 bus_space_tag_t iot = pcihp->iot; 2023 #endif 2024 bus_space_handle_t ioh = pcihp->ioh; 2025 bus_size_t size = pcihp->size; 2026 2027 #if rbus 2028 rbus_tag_t rb = sc->sc_rbus_iot; 2029 2030 rbus_space_free(rb, ioh, size, NULL); 2031 #else 2032 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 2033 bus_space_free(iot, ioh, size); 2034 else 2035 bus_space_unmap(iot, ioh, size); 2036 #endif 2037 } 2038 2039 /* 2040 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 2041 * bus_addr_t offset, bus_size_t size, 2042 * struct pcmcia_io_handle *pcihp, 2043 * int *windowp) 2044 * 2045 * This function maps the allocated I/O region to pccard. This function 2046 * never allocates any I/O region for pccard I/O area. I don't 2047 * understand why the original authors of pcmciabus separated alloc and 2048 * map. I believe the two must be unite. 2049 * 2050 * XXX: no wait timing control? 2051 */ 2052 int 2053 pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, bus_addr_t offset, 2054 bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp) 2055 { 2056 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2057 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2058 bus_addr_t ioaddr = pcihp->addr + offset; 2059 int i, win; 2060 #if defined CBB_DEBUG 2061 static const char *width_names[] = { "dynamic", "io8", "io16" }; 2062 #endif 2063 2064 /* Sanity check I/O handle. */ 2065 2066 if (!bus_space_is_equal(sc->sc_iot, pcihp->iot)) 2067 panic("pccbb_pcmcia_io_map iot is bogus"); 2068 2069 /* XXX Sanity check offset/size. */ 2070 2071 win = -1; 2072 for (i = 0; i < PCIC_IO_WINS; i++) { 2073 if ((ph->ioalloc & (1 << i)) == 0) { 2074 win = i; 2075 ph->ioalloc |= (1 << i); 2076 break; 2077 } 2078 } 2079 2080 if (win == -1) 2081 return 1; 2082 2083 *windowp = win; 2084 2085 /* XXX this is pretty gross */ 2086 2087 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2088 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2089 2090 /* XXX wtf is this doing here? */ 2091 2092 #if 0 2093 printf(" port 0x%lx", (u_long) ioaddr); 2094 if (size > 1) 2095 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2096 #endif 2097 2098 ph->io[win].addr = ioaddr; 2099 ph->io[win].size = size; 2100 ph->io[win].width = width; 2101 2102 /* actual dirty register-value changing in the function below. */ 2103 pccbb_pcmcia_do_io_map(sc, win); 2104 2105 return 0; 2106 } 2107 2108 /* 2109 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2110 * 2111 * This function changes register-value to map I/O region for pccard. 2112 */ 2113 static void 2114 pccbb_pcmcia_do_io_map(struct pccbb_softc *sc, int win) 2115 { 2116 static uint8_t pcic_iowidth[3] = { 2117 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2118 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2119 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2120 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2121 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2122 }; 2123 2124 #define PCIC_SIA_START_LOW 0 2125 #define PCIC_SIA_START_HIGH 1 2126 #define PCIC_SIA_STOP_LOW 2 2127 #define PCIC_SIA_STOP_HIGH 3 2128 2129 int regbase_win = 0x8 + win * 0x04; 2130 uint8_t ioctl, enable; 2131 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2132 2133 DPRINTF(("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx " 2134 "width %d\n", win, (unsigned long)ph->io[win].addr, 2135 (unsigned long)ph->io[win].size, ph->io[win].width * 8)); 2136 2137 Pcic_write(sc, regbase_win + PCIC_SIA_START_LOW, 2138 ph->io[win].addr & 0xff); 2139 Pcic_write(sc, regbase_win + PCIC_SIA_START_HIGH, 2140 (ph->io[win].addr >> 8) & 0xff); 2141 2142 Pcic_write(sc, regbase_win + PCIC_SIA_STOP_LOW, 2143 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2144 Pcic_write(sc, regbase_win + PCIC_SIA_STOP_HIGH, 2145 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2146 2147 ioctl = Pcic_read(sc, PCIC_IOCTL); 2148 enable = Pcic_read(sc, PCIC_ADDRWIN_ENABLE); 2149 switch (win) { 2150 case 0: 2151 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2152 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2153 PCIC_IOCTL_IO0_DATASIZE_MASK); 2154 ioctl |= pcic_iowidth[ph->io[win].width]; 2155 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2156 break; 2157 case 1: 2158 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2159 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2160 PCIC_IOCTL_IO1_DATASIZE_MASK); 2161 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2162 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2163 break; 2164 } 2165 Pcic_write(sc, PCIC_IOCTL, ioctl); 2166 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, enable); 2167 #if defined(CBB_DEBUG) 2168 { 2169 uint8_t start_low = 2170 Pcic_read(sc, regbase_win + PCIC_SIA_START_LOW); 2171 uint8_t start_high = 2172 Pcic_read(sc, regbase_win + PCIC_SIA_START_HIGH); 2173 uint8_t stop_low = 2174 Pcic_read(sc, regbase_win + PCIC_SIA_STOP_LOW); 2175 uint8_t stop_high = 2176 Pcic_read(sc, regbase_win + PCIC_SIA_STOP_HIGH); 2177 printf("pccbb_pcmcia_do_io_map start %02x %02x, " 2178 "stop %02x %02x, ioctl %02x enable %02x\n", 2179 start_low, start_high, stop_low, stop_high, ioctl, enable); 2180 } 2181 #endif 2182 } 2183 2184 /* 2185 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2186 * 2187 * This function unmaps I/O region. No return value. 2188 */ 2189 STATIC void 2190 pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t pch, int win) 2191 { 2192 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2193 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2194 int reg; 2195 2196 if (win >= PCIC_IO_WINS || win < 0) 2197 panic("pccbb_pcmcia_io_unmap: window out of range"); 2198 2199 reg = Pcic_read(sc, PCIC_ADDRWIN_ENABLE); 2200 switch (win) { 2201 case 0: 2202 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2203 break; 2204 case 1: 2205 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2206 break; 2207 } 2208 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, reg); 2209 2210 ph->ioalloc &= ~(1 << win); 2211 } 2212 2213 static int 2214 pccbb_pcmcia_wait_ready(struct pccbb_softc *sc) 2215 { 2216 uint8_t stat; 2217 int i; 2218 2219 /* wait an initial 10ms for quick cards */ 2220 stat = Pcic_read(sc, PCIC_IF_STATUS); 2221 if (stat & PCIC_IF_STATUS_READY) 2222 return 0; 2223 pccbb_pcmcia_delay(sc, 10, "pccwr0"); 2224 for (i = 0; i < 50; i++) { 2225 stat = Pcic_read(sc, PCIC_IF_STATUS); 2226 if (stat & PCIC_IF_STATUS_READY) 2227 return 0; 2228 if ((stat & PCIC_IF_STATUS_CARDDETECT_MASK) != 2229 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2230 return ENXIO; 2231 /* wait .1s (100ms) each iteration now */ 2232 pccbb_pcmcia_delay(sc, 100, "pccwr1"); 2233 } 2234 2235 printf("pccbb_pcmcia_wait_ready: ready never happened, status=%02x\n", 2236 stat); 2237 return EWOULDBLOCK; 2238 } 2239 2240 /* 2241 * Perform long (msec order) delay. timo is in milliseconds. 2242 */ 2243 static void 2244 pccbb_pcmcia_delay(struct pccbb_softc *sc, int timo, const char *wmesg) 2245 { 2246 #ifdef DIAGNOSTIC 2247 if (timo <= 0) 2248 panic("pccbb_pcmcia_delay: called with timeout %d", timo); 2249 if (!curlwp) 2250 panic("pccbb_pcmcia_delay: called in interrupt context"); 2251 #endif 2252 DPRINTF(("pccbb_pcmcia_delay: \"%s\", sleep %d ms\n", wmesg, timo)); 2253 kpause(wmesg, false, uimax(mstohz(timo), 1), NULL); 2254 } 2255 2256 /* 2257 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2258 * 2259 * This function enables the card. All information is stored in 2260 * the first argument, pcmcia_chipset_handle_t. 2261 */ 2262 STATIC void 2263 pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2264 { 2265 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2266 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2267 pcireg_t spsr; 2268 int voltage; 2269 int win; 2270 uint8_t power, intr; 2271 #ifdef DIAGNOSTIC 2272 int reg; 2273 #endif 2274 2275 /* this bit is mostly stolen from pcic_attach_card */ 2276 2277 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2278 2279 /* get card Vcc info */ 2280 spsr = 2281 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2282 CB_SOCKET_STAT); 2283 if (spsr & CB_SOCKET_STAT_5VCARD) { 2284 DPRINTF(("5V card\n")); 2285 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2286 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2287 DPRINTF(("3V card\n")); 2288 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2289 } else { 2290 DPRINTF(("?V card, 0x%x\n", spsr)); /* XXX */ 2291 return; 2292 } 2293 2294 /* disable interrupts; assert RESET */ 2295 intr = Pcic_read(sc, PCIC_INTR); 2296 intr &= PCIC_INTR_ENABLE; 2297 Pcic_write(sc, PCIC_INTR, intr); 2298 2299 /* zero out the address windows */ 2300 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, 0); 2301 2302 /* power down the socket to reset it, clear the card reset pin */ 2303 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2304 2305 /* power off; assert output enable bit */ 2306 power = PCIC_PWRCTL_OE; 2307 Pcic_write(sc, PCIC_PWRCTL, power); 2308 2309 /* power up the socket */ 2310 if (pccbb_power(sc, voltage) == 0) 2311 return; 2312 2313 /* 2314 * Table 4-18 and figure 4-6 of the PC Card specifiction say: 2315 * Vcc Rising Time (Tpr) = 100ms (handled in pccbb_power() above) 2316 * RESET Width (Th (Hi-z RESET)) = 1ms 2317 * RESET Width (Tw (RESET)) = 10us 2318 * 2319 * some machines require some more time to be settled 2320 * for example old toshiba topic bridges! 2321 * (100ms is added here). 2322 */ 2323 pccbb_pcmcia_delay(sc, 200 + 1, "pccen1"); 2324 2325 /* negate RESET */ 2326 intr |= PCIC_INTR_RESET; 2327 Pcic_write(sc, PCIC_INTR, intr); 2328 2329 /* 2330 * RESET Setup Time (Tsu (RESET)) = 20ms 2331 */ 2332 pccbb_pcmcia_delay(sc, 20, "pccen2"); 2333 2334 #ifdef DIAGNOSTIC 2335 reg = Pcic_read(sc, PCIC_IF_STATUS); 2336 if ((reg & PCIC_IF_STATUS_POWERACTIVE) == 0) 2337 printf("pccbb_pcmcia_socket_enable: no power, status=%x\n", 2338 reg); 2339 #endif 2340 2341 /* wait for the chip to finish initializing */ 2342 if (pccbb_pcmcia_wait_ready(sc)) { 2343 #ifdef DIAGNOSTIC 2344 printf("pccbb_pcmcia_socket_enable: never became ready\n"); 2345 #endif 2346 /* XXX return a failure status?? */ 2347 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2348 Pcic_write(sc, PCIC_PWRCTL, 0); 2349 return; 2350 } 2351 2352 /* reinstall all the memory and io mappings */ 2353 for (win = 0; win < PCIC_MEM_WINS; ++win) 2354 if (ph->memalloc & (1 << win)) 2355 pccbb_pcmcia_do_mem_map(sc, win); 2356 for (win = 0; win < PCIC_IO_WINS; ++win) 2357 if (ph->ioalloc & (1 << win)) 2358 pccbb_pcmcia_do_io_map(sc, win); 2359 } 2360 2361 /* 2362 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2363 * 2364 * This function disables the card. All information is stored in 2365 * the first argument, pcmcia_chipset_handle_t. 2366 */ 2367 STATIC void 2368 pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t pch) 2369 { 2370 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2371 uint8_t intr; 2372 2373 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2374 2375 /* disable interrupts; assert RESET */ 2376 intr = Pcic_read(sc, PCIC_INTR); 2377 intr &= PCIC_INTR_ENABLE; 2378 Pcic_write(sc, PCIC_INTR, intr); 2379 2380 /* zero out the address windows */ 2381 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, 0); 2382 2383 /* power down the socket to reset it, clear the card reset pin */ 2384 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2385 2386 /* disable socket: negate output enable bit and power off */ 2387 Pcic_write(sc, PCIC_PWRCTL, 0); 2388 2389 /* 2390 * Vcc Falling Time (Tpf) = 300ms 2391 */ 2392 pccbb_pcmcia_delay(sc, 300, "pccwr1"); 2393 } 2394 2395 STATIC void 2396 pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t pch, int type) 2397 { 2398 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2399 uint8_t intr; 2400 2401 /* set the card type */ 2402 2403 intr = Pcic_read(sc, PCIC_INTR); 2404 intr &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_CARDTYPE_MASK); 2405 if (type == PCMCIA_IFTYPE_IO) 2406 intr |= PCIC_INTR_CARDTYPE_IO; 2407 else 2408 intr |= PCIC_INTR_CARDTYPE_MEM; 2409 Pcic_write(sc, PCIC_INTR, intr); 2410 2411 DPRINTF(("%s: pccbb_pcmcia_socket_settype type %s %02x\n", 2412 device_xname(sc->sc_dev), 2413 ((type == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2414 } 2415 2416 /* 2417 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2418 * 2419 * This function detects whether a card is in the slot or not. 2420 * If a card is inserted, return 1. Otherwise, return 0. 2421 */ 2422 STATIC int 2423 pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch) 2424 { 2425 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2426 2427 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2428 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2429 } 2430 2431 #if 0 2432 STATIC int 2433 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2434 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2435 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2436 #endif 2437 /* 2438 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2439 * bus_size_t size, 2440 * struct pcmcia_mem_handle *pcmhp) 2441 * 2442 * This function only allocates memory region for pccard. This 2443 * function never maps the allocated region to pccard memory area. 2444 * 2445 * XXX: Why the argument of start address is not in? 2446 */ 2447 STATIC int 2448 pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 2449 struct pcmcia_mem_handle *pcmhp) 2450 { 2451 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2452 bus_space_handle_t memh; 2453 bus_addr_t addr; 2454 bus_size_t sizepg; 2455 #if rbus 2456 rbus_tag_t rb; 2457 #endif 2458 2459 /* Check that the card is still there. */ 2460 if ((Pcic_read(sc, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2461 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2462 return 1; 2463 2464 /* out of sc->memh, allocate as many pages as necessary */ 2465 2466 /* convert size to PCIC pages */ 2467 /* 2468 * This is not enough; when the requested region is on the page 2469 * boundaries, this may calculate wrong result. 2470 */ 2471 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2472 #if 0 2473 if (sizepg > PCIC_MAX_MEM_PAGES) 2474 return 1; 2475 #endif 2476 2477 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) 2478 return 1; 2479 2480 addr = 0; /* XXX gcc -Wuninitialized */ 2481 2482 #if rbus 2483 rb = sc->sc_rbus_memt; 2484 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2485 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2486 &addr, &memh)) { 2487 return 1; 2488 } 2489 #else 2490 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2491 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2492 0, /* boundary */ 2493 0, /* flags */ 2494 &addr, &memh)) { 2495 return 1; 2496 } 2497 #endif 2498 2499 DPRINTF(("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, " 2500 "realsize 0x%lx\n", (unsigned long)addr, (unsigned long)size, 2501 (unsigned long)sizepg * PCIC_MEM_PAGESIZE)); 2502 2503 pcmhp->memt = sc->sc_memt; 2504 pcmhp->memh = memh; 2505 pcmhp->addr = addr; 2506 pcmhp->size = size; 2507 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2508 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2509 pcmhp->mhandle = 0; 2510 /* No offset??? Funny. */ 2511 2512 return 0; 2513 } 2514 2515 /* 2516 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2517 * struct pcmcia_mem_handle *pcmhp) 2518 * 2519 * This function release the memory space allocated by the function 2520 * pccbb_pcmcia_mem_alloc(). 2521 */ 2522 STATIC void 2523 pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2524 struct pcmcia_mem_handle *pcmhp) 2525 { 2526 #if rbus 2527 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2528 2529 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2530 #else 2531 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2532 #endif 2533 } 2534 2535 /* 2536 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2537 * 2538 * This function release the memory space allocated by the function 2539 * pccbb_pcmcia_mem_alloc(). 2540 */ 2541 STATIC void 2542 pccbb_pcmcia_do_mem_map(struct pccbb_softc *sc, int win) 2543 { 2544 int regbase_win; 2545 bus_addr_t phys_addr; 2546 bus_addr_t phys_end; 2547 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2548 2549 #define PCIC_SMM_START_LOW 0 2550 #define PCIC_SMM_START_HIGH 1 2551 #define PCIC_SMM_STOP_LOW 2 2552 #define PCIC_SMM_STOP_HIGH 3 2553 #define PCIC_CMA_LOW 4 2554 #define PCIC_CMA_HIGH 5 2555 2556 uint8_t start_low, start_high = 0; 2557 uint8_t stop_low, stop_high; 2558 uint8_t off_low, off_high; 2559 uint8_t mem_window; 2560 int reg; 2561 2562 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2563 int mem8 = 2564 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2565 || (kind == PCMCIA_MEM_ATTR); 2566 2567 regbase_win = 0x10 + win * 0x08; 2568 2569 phys_addr = ph->mem[win].addr; 2570 phys_end = phys_addr + ph->mem[win].size; 2571 2572 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2573 (unsigned long)phys_addr, (unsigned long)phys_end, 2574 (unsigned long)ph->mem[win].offset)); 2575 2576 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2577 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2578 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2579 2580 /* bit 19:12 */ 2581 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2582 /* bit 23:20 and bit 7 on */ 2583 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2584 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2585 /* bit 31:24, for 32-bit address */ 2586 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2587 2588 Pcic_write(sc, regbase_win + PCIC_SMM_START_LOW, start_low); 2589 Pcic_write(sc, regbase_win + PCIC_SMM_START_HIGH, start_high); 2590 2591 if (sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2592 Pcic_write(sc, 0x40 + win, mem_window); 2593 } 2594 2595 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2596 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2597 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2598 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2599 2600 Pcic_write(sc, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2601 Pcic_write(sc, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2602 2603 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2604 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2605 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2606 | ((kind == PCMCIA_MEM_ATTR) ? 2607 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2608 2609 Pcic_write(sc, regbase_win + PCIC_CMA_LOW, off_low); 2610 Pcic_write(sc, regbase_win + PCIC_CMA_HIGH, off_high); 2611 2612 reg = Pcic_read(sc, PCIC_ADDRWIN_ENABLE); 2613 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2614 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, reg); 2615 2616 #if defined(CBB_DEBUG) 2617 { 2618 int r1, r2, r3, r4, r5, r6, r7 = 0; 2619 2620 r1 = Pcic_read(sc, regbase_win + PCIC_SMM_START_LOW); 2621 r2 = Pcic_read(sc, regbase_win + PCIC_SMM_START_HIGH); 2622 r3 = Pcic_read(sc, regbase_win + PCIC_SMM_STOP_LOW); 2623 r4 = Pcic_read(sc, regbase_win + PCIC_SMM_STOP_HIGH); 2624 r5 = Pcic_read(sc, regbase_win + PCIC_CMA_LOW); 2625 r6 = Pcic_read(sc, regbase_win + PCIC_CMA_HIGH); 2626 if (sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2627 r7 = Pcic_read(sc, 0x40 + win); 2628 } 2629 2630 printf("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2631 "%02x%02x", win, r1, r2, r3, r4, r5, r6); 2632 if (sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2633 printf(" %02x", r7); 2634 } 2635 printf("\n"); 2636 } 2637 #endif 2638 } 2639 2640 /* 2641 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2642 * bus_addr_t card_addr, bus_size_t size, 2643 * struct pcmcia_mem_handle *pcmhp, 2644 * bus_addr_t *offsetp, int *windowp) 2645 * 2646 * This function maps memory space allocated by the function 2647 * pccbb_pcmcia_mem_alloc(). 2648 */ 2649 STATIC int 2650 pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2651 bus_addr_t card_addr, bus_size_t size, struct pcmcia_mem_handle *pcmhp, 2652 bus_size_t *offsetp, int *windowp) 2653 { 2654 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2655 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2656 bus_addr_t busaddr; 2657 long card_offset; 2658 int win; 2659 2660 /* Check that the card is still there. */ 2661 if ((Pcic_read(sc, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2662 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2663 return 1; 2664 2665 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2666 if ((ph->memalloc & (1 << win)) == 0) { 2667 ph->memalloc |= (1 << win); 2668 break; 2669 } 2670 } 2671 2672 if (win == PCIC_MEM_WINS) 2673 return 1; 2674 2675 *windowp = win; 2676 2677 /* XXX this is pretty gross */ 2678 2679 if (!bus_space_is_equal(sc->sc_memt, pcmhp->memt)) { 2680 panic("pccbb_pcmcia_mem_map memt is bogus"); 2681 } 2682 2683 busaddr = pcmhp->addr; 2684 2685 /* 2686 * compute the address offset to the pcmcia address space for the 2687 * pcic. this is intentionally signed. The masks and shifts below 2688 * will cause TRT to happen in the pcic registers. Deal with making 2689 * sure the address is aligned, and return the alignment offset. 2690 */ 2691 2692 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2693 card_addr -= *offsetp; 2694 2695 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2696 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2697 (u_long) card_addr)); 2698 2699 /* 2700 * include the offset in the size, and decrement size by one, since 2701 * the hw wants start/stop 2702 */ 2703 size += *offsetp - 1; 2704 2705 card_offset = (((long)card_addr) - ((long)busaddr)); 2706 2707 ph->mem[win].addr = busaddr; 2708 ph->mem[win].size = size; 2709 ph->mem[win].offset = card_offset; 2710 ph->mem[win].kind = kind; 2711 2712 pccbb_pcmcia_do_mem_map(sc, win); 2713 2714 return 0; 2715 } 2716 2717 /* 2718 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2719 * int window) 2720 * 2721 * This function unmaps memory space which mapped by the function 2722 * pccbb_pcmcia_mem_map(). 2723 */ 2724 STATIC void 2725 pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, int window) 2726 { 2727 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2728 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2729 int reg; 2730 2731 if (window >= PCIC_MEM_WINS) 2732 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2733 2734 reg = Pcic_read(sc, PCIC_ADDRWIN_ENABLE); 2735 reg &= ~(1 << window); 2736 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, reg); 2737 2738 ph->memalloc &= ~(1 << window); 2739 } 2740 2741 /* 2742 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2743 * struct pcmcia_function *pf, 2744 * int ipl, 2745 * int (*func)(void *), 2746 * void *arg); 2747 * 2748 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2749 */ 2750 STATIC void * 2751 pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2752 struct pcmcia_function *pf, int ipl, int (*func)(void *), void *arg) 2753 { 2754 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2755 2756 if (!(pf->cfe->flags & (PCMCIA_CFE_IRQLEVEL|PCMCIA_CFE_IRQPULSE))) { 2757 /* 2758 * XXX Noooooo! The interrupt flag must set properly!! 2759 * dumb pcmcia driver!! 2760 */ 2761 DPRINTF(("%s does not provide edge nor pulse interrupt\n", 2762 device_xname(sc->sc_dev))); 2763 return NULL; 2764 } 2765 2766 return pccbb_intr_establish(sc, ipl, func, arg); 2767 } 2768 2769 /* 2770 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2771 * void *ih) 2772 * 2773 * This function disables PC-Card interrupt. 2774 */ 2775 STATIC void 2776 pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 2777 { 2778 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2779 2780 pccbb_intr_disestablish(sc, ih); 2781 } 2782 2783 #if rbus 2784 /* 2785 * static int 2786 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2787 * bus_addr_t addr, bus_size_t size, 2788 * bus_addr_t mask, bus_size_t align, 2789 * int flags, bus_addr_t *addrp; 2790 * bus_space_handle_t *bshp) 2791 * 2792 * This function allocates a portion of memory or io space for 2793 * clients. This function is called from CardBus card drivers. 2794 */ 2795 static int 2796 pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2797 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 2798 int flags, bus_addr_t *addrp, bus_space_handle_t *bshp) 2799 { 2800 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2801 2802 DPRINTF(("pccbb_rbus_cb_space_alloc: addr 0x%lx, size 0x%lx, " 2803 "mask 0x%lx, align 0x%lx\n", (unsigned long)addr, 2804 (unsigned long)size, (unsigned long)mask, (unsigned long)align)); 2805 2806 if (align == 0) 2807 align = size; 2808 2809 if (bus_space_is_equal(rb->rb_bt, sc->sc_memt)) { 2810 if (align < 16) { 2811 return 1; 2812 } 2813 /* 2814 * XXX: align more than 0x1000 to avoid overwrapping 2815 * memory windows for two or more devices. 0x1000 2816 * means memory window's granularity. 2817 * 2818 * Two or more devices should be able to share same 2819 * memory window region. However, overrapping memory 2820 * window is not good because some devices, such as 2821 * 3Com 3C575[BC], have a broken address decoder and 2822 * intrude other's memory region. 2823 */ 2824 if (align < 0x1000) { 2825 align = 0x1000; 2826 } 2827 } else if (bus_space_is_equal(rb->rb_bt, sc->sc_iot)) { 2828 if (align < 4) { 2829 return 1; 2830 } 2831 /* XXX: hack for avoiding ISA image */ 2832 if (mask < 0x0100) { 2833 mask = 0x3ff; 2834 addr = 0x300; 2835 } 2836 2837 } else { 2838 DPRINTF(("pccbb_rbus_cb_space_alloc: Bus space tag 0x%lx is " 2839 "NOT used. io: 0x%lx, mem: 0x%lx\n", 2840 (unsigned long)rb->rb_bt, (unsigned long)sc->sc_iot, 2841 (unsigned long)sc->sc_memt)); 2842 return 1; 2843 /* XXX: panic here? */ 2844 } 2845 2846 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 2847 aprint_normal_dev(sc->sc_dev, "<rbus> no bus space\n"); 2848 return 1; 2849 } 2850 2851 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 2852 2853 return 0; 2854 } 2855 2856 /* 2857 * static int 2858 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 2859 * bus_space_handle_t *bshp, bus_size_t size); 2860 * 2861 * This function is called from CardBus card drivers. 2862 */ 2863 static int 2864 pccbb_rbus_cb_space_free(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2865 bus_space_handle_t bsh, bus_size_t size) 2866 { 2867 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2868 bus_space_tag_t bt = rb->rb_bt; 2869 2870 pccbb_close_win(sc, bt, bsh, size); 2871 2872 if (bus_space_is_equal(bt, sc->sc_memt)) { 2873 } else if (bus_space_is_equal(bt, sc->sc_iot)) { 2874 } else { 2875 return 1; 2876 /* XXX: panic here? */ 2877 } 2878 2879 return rbus_space_free(rb, bsh, size, NULL); 2880 } 2881 #endif /* rbus */ 2882 2883 #if rbus 2884 2885 static int 2886 pccbb_open_win(struct pccbb_softc *sc, bus_space_tag_t bst, bus_addr_t addr, 2887 bus_size_t size, bus_space_handle_t bsh, int flags) 2888 { 2889 struct pccbb_win_chain_head *head; 2890 bus_addr_t align; 2891 2892 head = &sc->sc_iowindow; 2893 align = 0x04; 2894 if (bus_space_is_equal(sc->sc_memt, bst)) { 2895 head = &sc->sc_memwindow; 2896 align = 0x1000; 2897 DPRINTF(("using memory window, 0x%lx 0x%lx 0x%lx\n\n", 2898 (unsigned long)sc->sc_iot, (unsigned long)sc->sc_memt, 2899 (unsigned long)bst)); 2900 } 2901 2902 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 2903 aprint_error_dev(sc->sc_dev, 2904 "pccbb_open_win: %s winlist insert failed\n", 2905 (head == &sc->sc_memwindow) ? "mem" : "io"); 2906 } 2907 pccbb_winset(align, sc, bst); 2908 2909 return 0; 2910 } 2911 2912 static int 2913 pccbb_close_win(struct pccbb_softc *sc, bus_space_tag_t bst, 2914 bus_space_handle_t bsh, bus_size_t size) 2915 { 2916 struct pccbb_win_chain_head *head; 2917 bus_addr_t align; 2918 2919 head = &sc->sc_iowindow; 2920 align = 0x04; 2921 if (bus_space_is_equal(sc->sc_memt, bst)) { 2922 head = &sc->sc_memwindow; 2923 align = 0x1000; 2924 } 2925 2926 if (pccbb_winlist_delete(head, bsh, size)) { 2927 aprint_error_dev(sc->sc_dev, 2928 "pccbb_close_win: %s winlist delete failed\n", 2929 (head == &sc->sc_memwindow) ? "mem" : "io"); 2930 } 2931 pccbb_winset(align, sc, bst); 2932 2933 return 0; 2934 } 2935 2936 static int 2937 pccbb_winlist_insert(struct pccbb_win_chain_head *head, bus_addr_t start, 2938 bus_size_t size, bus_space_handle_t bsh, int flags) 2939 { 2940 struct pccbb_win_chain *chainp, *elem; 2941 2942 elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 2943 M_WAITOK); 2944 elem->wc_start = start; 2945 elem->wc_end = start + (size - 1); 2946 elem->wc_handle = bsh; 2947 elem->wc_flags = flags; 2948 2949 TAILQ_FOREACH(chainp, head, wc_list) { 2950 if (chainp->wc_end >= start) 2951 break; 2952 } 2953 if (chainp != NULL) 2954 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 2955 else 2956 TAILQ_INSERT_TAIL(head, elem, wc_list); 2957 return 0; 2958 } 2959 2960 static int 2961 pccbb_winlist_delete(struct pccbb_win_chain_head *head, bus_space_handle_t bsh, 2962 bus_size_t size) 2963 { 2964 struct pccbb_win_chain *chainp; 2965 2966 TAILQ_FOREACH(chainp, head, wc_list) { 2967 if (memcmp(&chainp->wc_handle, &bsh, sizeof(bsh)) == 0) 2968 break; 2969 } 2970 if (chainp == NULL) 2971 return 1; /* fail: no candidate to remove */ 2972 2973 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 2974 printf("pccbb_winlist_delete: window 0x%lx size " 2975 "inconsistent: 0x%lx, 0x%lx\n", 2976 (unsigned long)chainp->wc_start, 2977 (unsigned long)(chainp->wc_end - chainp->wc_start), 2978 (unsigned long)(size - 1)); 2979 return 1; 2980 } 2981 2982 TAILQ_REMOVE(head, chainp, wc_list); 2983 free(chainp, M_DEVBUF); 2984 2985 return 0; 2986 } 2987 2988 static void 2989 pccbb_winset(bus_addr_t align, struct pccbb_softc *sc, bus_space_tag_t bst) 2990 { 2991 pci_chipset_tag_t pc; 2992 pcitag_t tag; 2993 bus_addr_t mask = ~(align - 1); 2994 struct { 2995 pcireg_t win_start; 2996 pcireg_t win_limit; 2997 int win_flags; 2998 } win[2]; 2999 struct pccbb_win_chain *chainp; 3000 int offs; 3001 3002 win[0].win_start = win[1].win_start = 0xffffffff; 3003 win[0].win_limit = win[1].win_limit = 0; 3004 win[0].win_flags = win[1].win_flags = 0; 3005 3006 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3007 offs = PCI_CB_IOBASE0; 3008 if (bus_space_is_equal(sc->sc_memt, bst)) { 3009 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3010 offs = PCI_CB_MEMBASE0; 3011 } 3012 3013 if (chainp != NULL) { 3014 win[0].win_start = chainp->wc_start & mask; 3015 win[0].win_limit = chainp->wc_end & mask; 3016 win[0].win_flags = chainp->wc_flags; 3017 chainp = TAILQ_NEXT(chainp, wc_list); 3018 } 3019 3020 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3021 if (win[1].win_start == 0xffffffff) { 3022 /* window 1 is not used */ 3023 if ((win[0].win_flags == chainp->wc_flags) && 3024 (win[0].win_limit + align >= 3025 (chainp->wc_start & mask))) { 3026 /* concatenate */ 3027 win[0].win_limit = chainp->wc_end & mask; 3028 } else { 3029 /* make new window */ 3030 win[1].win_start = chainp->wc_start & mask; 3031 win[1].win_limit = chainp->wc_end & mask; 3032 win[1].win_flags = chainp->wc_flags; 3033 } 3034 continue; 3035 } 3036 3037 /* Both windows are engaged. */ 3038 if (win[0].win_flags == win[1].win_flags) { 3039 /* same flags */ 3040 if (win[0].win_flags == chainp->wc_flags) { 3041 if (win[1].win_start - (win[0].win_limit + 3042 align) < 3043 (chainp->wc_start & mask) - 3044 ((chainp->wc_end & mask) + align)) { 3045 /* 3046 * merge window 0 and 1, and set win1 3047 * to chainp 3048 */ 3049 win[0].win_limit = win[1].win_limit; 3050 win[1].win_start = 3051 chainp->wc_start & mask; 3052 win[1].win_limit = 3053 chainp->wc_end & mask; 3054 } else { 3055 win[1].win_limit = 3056 chainp->wc_end & mask; 3057 } 3058 } else { 3059 /* different flags */ 3060 3061 /* concatenate win0 and win1 */ 3062 win[0].win_limit = win[1].win_limit; 3063 /* allocate win[1] to new space */ 3064 win[1].win_start = chainp->wc_start & mask; 3065 win[1].win_limit = chainp->wc_end & mask; 3066 win[1].win_flags = chainp->wc_flags; 3067 } 3068 } else { 3069 /* the flags of win[0] and win[1] is different */ 3070 if (win[0].win_flags == chainp->wc_flags) { 3071 win[0].win_limit = chainp->wc_end & mask; 3072 /* 3073 * XXX this creates overlapping windows, so 3074 * what should the poor bridge do if one is 3075 * cachable, and the other is not? 3076 */ 3077 aprint_error_dev(sc->sc_dev, 3078 "overlapping windows\n"); 3079 } else { 3080 win[1].win_limit = chainp->wc_end & mask; 3081 } 3082 } 3083 } 3084 3085 pc = sc->sc_pc; 3086 tag = sc->sc_tag; 3087 pci_conf_write(pc, tag, offs, win[0].win_start); 3088 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3089 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3090 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3091 DPRINTF(("--pccbb_winset: win0 [0x%lx, 0x%lx), win1 [0x%lx, 0x%lx)\n", 3092 (unsigned long)pci_conf_read(pc, tag, offs), 3093 (unsigned long)pci_conf_read(pc, tag, offs + 4) + align, 3094 (unsigned long)pci_conf_read(pc, tag, offs + 8), 3095 (unsigned long)pci_conf_read(pc, tag, offs + 12) + align)); 3096 3097 if (bus_space_is_equal(bst, sc->sc_memt)) { 3098 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BRIDGE_CONTROL_REG); 3099 3100 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 3101 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 3102 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3103 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 3104 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3105 pci_conf_write(pc, tag, PCI_BRIDGE_CONTROL_REG, bcr); 3106 } 3107 } 3108 3109 #endif /* rbus */ 3110 3111 static bool 3112 pccbb_suspend(device_t dv, const pmf_qual_t *qual) 3113 { 3114 struct pccbb_softc *sc = device_private(dv); 3115 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3116 bus_space_handle_t base_memh = sc->sc_base_memh; 3117 pcireg_t reg; 3118 3119 if (sc->sc_pil_intr_enable) 3120 (void)pccbbintr_function(sc); 3121 sc->sc_pil_intr_enable = false; 3122 3123 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3124 /* Disable interrupts. */ 3125 reg &= ~(CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER); 3126 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3127 /* XXX joerg Disable power to the socket? */ 3128 3129 /* XXX flush PCI write */ 3130 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3131 3132 /* reset interrupt */ 3133 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, 3134 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT)); 3135 /* XXX flush PCI write */ 3136 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3137 3138 if (sc->sc_ih != NULL) { 3139 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 3140 sc->sc_ih = NULL; 3141 } 3142 3143 return true; 3144 } 3145 3146 static bool 3147 pccbb_resume(device_t dv, const pmf_qual_t *qual) 3148 { 3149 struct pccbb_softc *sc = device_private(dv); 3150 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3151 bus_space_handle_t base_memh = sc->sc_base_memh; 3152 pcireg_t reg; 3153 3154 pccbb_chipinit(sc); 3155 pccbb_intrinit(sc); 3156 /* setup memory and io space window for CB */ 3157 pccbb_winset(0x1000, sc, sc->sc_memt); 3158 pccbb_winset(0x04, sc, sc->sc_iot); 3159 3160 /* CSC Interrupt: Card detect interrupt on */ 3161 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3162 /* Card detect intr is turned on. */ 3163 reg |= CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; 3164 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3165 /* reset interrupt */ 3166 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3167 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3168 3169 /* 3170 * check for card insertion or removal during suspend period. 3171 * XXX: the code can't cope with card swap (remove then 3172 * insert). how can we detect such situation? 3173 */ 3174 (void)pccbbintr(sc); 3175 3176 sc->sc_pil_intr_enable = true; 3177 3178 return true; 3179 } 3180
Indexes created Sun Sep 28 16:09:52 GMT 2025