pccbb.c revision 1.22
1 /* $NetBSD: pccbb.c,v 1.22 2000/02/05 18:20:08 chopps Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 #define CBB_DEBUG 35 #define SHOW_REGS 36 #define PCCBB_PCMCIA_POLL 37 */ 38 /* #define CBB_DEBUG */ 39 40 /* 41 #define CB_PCMCIA_POLL 42 #define CB_PCMCIA_POLL_ONLY 43 #define LEVEL2 44 */ 45 46 #include <sys/types.h> 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/kernel.h> 50 #include <sys/errno.h> 51 #include <sys/ioctl.h> 52 #include <sys/syslog.h> 53 #include <sys/device.h> 54 #include <sys/malloc.h> 55 56 #include <machine/intr.h> 57 #include <machine/bus.h> 58 59 #include <dev/pci/pcivar.h> 60 #include <dev/pci/pcireg.h> 61 #include <dev/pci/pcidevs.h> 62 63 #include <dev/pci/pccbbreg.h> 64 65 #include <dev/cardbus/cardslotvar.h> 66 67 #include <dev/cardbus/cardbusvar.h> 68 69 #include <dev/pcmcia/pcmciareg.h> 70 #include <dev/pcmcia/pcmciavar.h> 71 72 #include <dev/ic/i82365reg.h> 73 #include <dev/ic/i82365var.h> 74 #include <dev/pci/pccbbvar.h> 75 76 #include "locators.h" 77 78 #ifndef __NetBSD_Version__ 79 struct cfdriver cbb_cd = { 80 NULL, "cbb", DV_DULL 81 }; 82 #endif 83 84 #if defined CBB_DEBUG 85 #define DPRINTF(x) printf x 86 #define STATIC 87 #else 88 #define DPRINTF(x) 89 #define STATIC static 90 #endif 91 92 #ifdef __BROKEN_INDIRECT_CONFIG 93 int pcicbbmatch __P((struct device *, void *, void *)); 94 #else 95 int pcicbbmatch __P((struct device *, struct cfdata *, void *)); 96 #endif 97 void pccbbattach __P((struct device *, struct device *, void *)); 98 int pccbbintr __P((void *)); 99 static void pci113x_insert __P((void *)); 100 static int pccbbintr_function __P((struct pccbb_softc *)); 101 102 static int pccbb_detect_card __P((struct pccbb_softc *)); 103 104 static void pccbb_pcmcia_write __P((struct pcic_handle *, int, u_int8_t)); 105 static u_int8_t pccbb_pcmcia_read __P((struct pcic_handle *, int)); 106 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 107 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 108 109 STATIC int cb_reset __P((struct pccbb_softc *)); 110 STATIC int cb_detect_voltage __P((struct pccbb_softc *)); 111 STATIC int cbbprint __P((void *, const char *)); 112 113 static int cb_chipset __P((u_int32_t, int *)); 114 STATIC void pccbb_pcmcia_attach_setup __P((struct pccbb_softc *, 115 struct pcmciabus_attach_args *)); 116 #if 0 117 STATIC void pccbb_pcmcia_attach_card __P((struct pcic_handle *)); 118 STATIC void pccbb_pcmcia_detach_card __P((struct pcic_handle *, int)); 119 STATIC void pccbb_pcmcia_deactivate_card __P((struct pcic_handle *)); 120 #endif 121 122 STATIC int pccbb_ctrl __P((cardbus_chipset_tag_t, int)); 123 STATIC int pccbb_power __P((cardbus_chipset_tag_t, int)); 124 STATIC int pccbb_cardenable __P((struct pccbb_softc * sc, int function)); 125 #if !rbus 126 static int pccbb_io_open __P((cardbus_chipset_tag_t, int, u_int32_t, 127 u_int32_t)); 128 static int pccbb_io_close __P((cardbus_chipset_tag_t, int)); 129 static int pccbb_mem_open __P((cardbus_chipset_tag_t, int, u_int32_t, 130 u_int32_t)); 131 static int pccbb_mem_close __P((cardbus_chipset_tag_t, int)); 132 #endif /* !rbus */ 133 static void *pccbb_intr_establish __P((cardbus_chipset_tag_t, int irq, 134 int level, int (*ih) (void *), void *sc)); 135 static void pccbb_intr_disestablish __P((cardbus_chipset_tag_t ct, void *ih)); 136 137 static cardbustag_t pccbb_make_tag __P((cardbus_chipset_tag_t, int, int, int)); 138 static void pccbb_free_tag __P((cardbus_chipset_tag_t, cardbustag_t)); 139 static cardbusreg_t pccbb_conf_read __P((cardbus_chipset_tag_t, cardbustag_t, 140 int)); 141 static void pccbb_conf_write __P((cardbus_chipset_tag_t, cardbustag_t, int, 142 cardbusreg_t)); 143 static void pccbb_chipinit __P((struct pccbb_softc *)); 144 145 STATIC int pccbb_pcmcia_mem_alloc __P((pcmcia_chipset_handle_t, bus_size_t, 146 struct pcmcia_mem_handle *)); 147 STATIC void pccbb_pcmcia_mem_free __P((pcmcia_chipset_handle_t, 148 struct pcmcia_mem_handle *)); 149 STATIC int pccbb_pcmcia_mem_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 150 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *)); 151 STATIC void pccbb_pcmcia_mem_unmap __P((pcmcia_chipset_handle_t, int)); 152 STATIC int pccbb_pcmcia_io_alloc __P((pcmcia_chipset_handle_t, bus_addr_t, 153 bus_size_t, bus_size_t, struct pcmcia_io_handle *)); 154 STATIC void pccbb_pcmcia_io_free __P((pcmcia_chipset_handle_t, 155 struct pcmcia_io_handle *)); 156 STATIC int pccbb_pcmcia_io_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 157 bus_size_t, struct pcmcia_io_handle *, int *)); 158 STATIC void pccbb_pcmcia_io_unmap __P((pcmcia_chipset_handle_t, int)); 159 STATIC void *pccbb_pcmcia_intr_establish __P((pcmcia_chipset_handle_t, 160 struct pcmcia_function *, int, int (*)(void *), void *)); 161 STATIC void pccbb_pcmcia_intr_disestablish __P((pcmcia_chipset_handle_t, 162 void *)); 163 STATIC void pccbb_pcmcia_socket_enable __P((pcmcia_chipset_handle_t)); 164 STATIC void pccbb_pcmcia_socket_disable __P((pcmcia_chipset_handle_t)); 165 STATIC int pccbb_pcmcia_card_detect __P((pcmcia_chipset_handle_t pch)); 166 167 static void pccbb_pcmcia_do_io_map __P((struct pcic_handle *, int)); 168 static void pccbb_pcmcia_wait_ready __P((struct pcic_handle *)); 169 static void pccbb_pcmcia_do_mem_map __P((struct pcic_handle *, int)); 170 171 /* bus-space allocation and disallocation functions */ 172 #if rbus 173 174 static int pccbb_rbus_cb_space_alloc __P((cardbus_chipset_tag_t, rbus_tag_t, 175 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 176 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp)); 177 static int pccbb_rbus_cb_space_free __P((cardbus_chipset_tag_t, rbus_tag_t, 178 bus_space_handle_t, bus_size_t)); 179 180 #endif /* rbus */ 181 182 #if rbus 183 184 static int pccbb_open_win __P((struct pccbb_softc *, bus_space_tag_t, 185 bus_addr_t, bus_size_t, bus_space_handle_t, int flags)); 186 static int pccbb_close_win __P((struct pccbb_softc *, bus_space_tag_t, 187 bus_space_handle_t, bus_size_t)); 188 static int pccbb_winlist_insert __P((struct pccbb_win_chain **, bus_addr_t, 189 bus_size_t, bus_space_handle_t, int)); 190 static int pccbb_winlist_delete __P((struct pccbb_win_chain **, 191 bus_space_handle_t, bus_size_t)); 192 static void pccbb_winset __P((bus_addr_t align, struct pccbb_softc *, 193 bus_space_tag_t)); 194 void pccbb_winlist_show(struct pccbb_win_chain *); 195 196 #endif /* rbus */ 197 198 /* for config_defer */ 199 static void pccbb_pci_callback __P((struct device *)); 200 201 #if defined SHOW_REGS 202 static void cb_show_regs __P((pci_chipset_tag_t pc, pcitag_t tag, 203 bus_space_tag_t memt, bus_space_handle_t memh)); 204 #endif 205 206 struct cfattach cbb_pci_ca = { 207 sizeof(struct pccbb_softc), pcicbbmatch, pccbbattach 208 }; 209 210 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 211 pccbb_pcmcia_mem_alloc, 212 pccbb_pcmcia_mem_free, 213 pccbb_pcmcia_mem_map, 214 pccbb_pcmcia_mem_unmap, 215 pccbb_pcmcia_io_alloc, 216 pccbb_pcmcia_io_free, 217 pccbb_pcmcia_io_map, 218 pccbb_pcmcia_io_unmap, 219 pccbb_pcmcia_intr_establish, 220 pccbb_pcmcia_intr_disestablish, 221 pccbb_pcmcia_socket_enable, 222 pccbb_pcmcia_socket_disable, 223 pccbb_pcmcia_card_detect 224 }; 225 226 #if rbus 227 static struct cardbus_functions pccbb_funcs = { 228 pccbb_rbus_cb_space_alloc, 229 pccbb_rbus_cb_space_free, 230 pccbb_intr_establish, 231 pccbb_intr_disestablish, 232 pccbb_ctrl, 233 pccbb_power, 234 pccbb_make_tag, 235 pccbb_free_tag, 236 pccbb_conf_read, 237 pccbb_conf_write, 238 }; 239 #else 240 static struct cardbus_functions pccbb_funcs = { 241 pccbb_ctrl, 242 pccbb_power, 243 pccbb_mem_open, 244 pccbb_mem_close, 245 pccbb_io_open, 246 pccbb_io_close, 247 pccbb_intr_establish, 248 pccbb_intr_disestablish, 249 pccbb_make_tag, 250 pccbb_conf_read, 251 pccbb_conf_write, 252 }; 253 #endif 254 255 int 256 pcicbbmatch(parent, match, aux) 257 struct device *parent; 258 #ifdef __BROKEN_INDIRECT_CONFIG 259 void *match; 260 #else 261 struct cfdata *match; 262 #endif 263 void *aux; 264 { 265 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 266 267 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 268 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 269 PCI_INTERFACE(pa->pa_class) == 0) { 270 return 1; 271 } 272 273 return 0; 274 } 275 276 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 277 | ((prod) << PCI_PRODUCT_SHIFT)) 278 279 struct yenta_chipinfo { 280 pcireg_t yc_id; /* vendor tag | product tag */ 281 int yc_chiptype; 282 int yc_flags; 283 } yc_chipsets[] = { 284 /* Texas Instruments chips */ 285 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 286 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 287 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 288 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 289 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI12XX, 290 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 291 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 292 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 293 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 294 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 295 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 296 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 297 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI12XX, 298 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 299 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI12XX, 300 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 301 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 302 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 303 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 304 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 305 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI12XX, 306 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 307 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 308 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 309 310 /* Ricoh chips */ 311 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 312 PCCBB_PCMCIA_MEM_32}, 313 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 314 PCCBB_PCMCIA_MEM_32}, 315 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 316 PCCBB_PCMCIA_MEM_32}, 317 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 318 PCCBB_PCMCIA_MEM_32}, 319 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 320 PCCBB_PCMCIA_MEM_32}, 321 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 322 PCCBB_PCMCIA_MEM_32}, 323 324 /* Toshiba products */ 325 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 326 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 327 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 328 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 329 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 330 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 331 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 332 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 333 334 /* Cirrus Logic products */ 335 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 336 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 337 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 338 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 339 340 /* sentinel, or Generic chip */ 341 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 342 }; 343 344 static int 345 cb_chipset(pci_id, flagp) 346 u_int32_t pci_id; 347 int *flagp; 348 { 349 int loopend = sizeof(yc_chipsets) / sizeof(yc_chipsets[0]); 350 struct yenta_chipinfo *ycp, *ycend; 351 352 ycend = yc_chipsets + loopend; 353 354 for (ycp = yc_chipsets; ycp < ycend && pci_id != ycp->yc_id; ++ycp); 355 356 if (ycp == ycend) { 357 /* not found -- point at sentinel */ 358 ycp = yc_chipsets + loopend - 1; 359 } 360 361 if (flagp != NULL) { 362 *flagp = ycp->yc_flags; 363 } 364 365 return ycp->yc_chiptype; 366 } 367 368 static void 369 pccbb_shutdown(void *arg) 370 { 371 struct pccbb_softc *sc = arg; 372 pcireg_t command; 373 374 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 375 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 376 0); 377 378 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 379 380 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 381 PCI_COMMAND_MASTER_ENABLE); 382 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 383 384 } 385 386 void 387 pccbbattach(parent, self, aux) 388 struct device *parent; 389 struct device *self; 390 void *aux; 391 { 392 struct pccbb_softc *sc = (void *)self; 393 struct pci_attach_args *pa = aux; 394 pci_chipset_tag_t pc = pa->pa_pc; 395 pcireg_t sock_base, busreg; 396 bus_addr_t sockbase; 397 char devinfo[256]; 398 int flags; 399 400 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 401 402 pci_devinfo(pa->pa_id, 0, 0, devinfo); 403 printf(": %s (rev. 0x%02x)", devinfo, PCI_REVISION(pa->pa_class)); 404 #ifdef CBB_DEBUG 405 printf(" (chipflags %x)", flags); 406 #endif 407 printf("\n"); 408 409 #if rbus 410 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 411 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 412 #endif /* rbus */ 413 414 sc->sc_base_memh = 0; 415 416 /* 417 * MAP socket registers and ExCA registers on memory-space 418 * When no valid address is set on socket base registers (on pci 419 * config space), get it not polite way. 420 */ 421 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 422 423 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 424 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 425 /* The address must be valid. */ 426 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 427 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL)) { 428 printf("%s: can't map socket base address 0x%x\n", 429 sc->sc_dev.dv_xname, sock_base); 430 /* 431 * I think it's funny: socket base registers must be 432 * mapped on memory space, but ... 433 */ 434 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 435 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 436 NULL)) { 437 printf("%s: can't map socket base address" 438 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 439 sockbase); 440 /* give up... allocate reg space via rbus. */ 441 sc->sc_base_memh = 0; 442 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 443 } 444 } else { 445 DPRINTF(("%s: socket base address 0x%lx\n", 446 sc->sc_dev.dv_xname, sockbase)); 447 } 448 } 449 450 sc->sc_mem_start = 0; /* XXX */ 451 sc->sc_mem_end = 0xffffffff; /* XXX */ 452 453 /* 454 * When interrupt isn't routed correctly, give up probing cbb and do 455 * not kill pcic-compatible port. 456 */ 457 if ((0 == pa->pa_intrline) || (255 == pa->pa_intrline)) { 458 printf(" Do not use %s because of intr unconfig.\n", 459 sc->sc_dev.dv_xname); 460 return; 461 } 462 463 /* 464 * When bus number isn't set correctly, give up using 32-bit CardBus 465 * mode. 466 */ 467 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 468 #if notyet 469 if (((busreg >> 8) & 0xff) == 0) { 470 printf 471 (" CardBus on %s will not be configured, because of bus no unconfig.\n", 472 sc->sc_dev.dv_xname); 473 flags |= PCCBB_PCMCIA_16BITONLY; 474 } 475 #endif 476 477 /* pccbb_machdep.c end */ 478 479 #if defined CBB_DEBUG 480 { 481 static char *intrname[5] = { "NON", "A", "B", "C", "D" }; 482 printf(" intrpin %s, intrtag %d\n", intrname[pa->pa_intrpin], 483 pa->pa_intrline); 484 } 485 #endif 486 487 /* setup softc */ 488 sc->sc_pc = pc; 489 sc->sc_iot = pa->pa_iot; 490 sc->sc_memt = pa->pa_memt; 491 sc->sc_dmat = pa->pa_dmat; 492 sc->sc_tag = pa->pa_tag; 493 sc->sc_function = pa->pa_function; 494 495 sc->sc_intrline = pa->pa_intrline; 496 sc->sc_intrtag = pa->pa_intrtag; 497 sc->sc_intrpin = pa->pa_intrpin; 498 499 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 500 501 shutdownhook_establish(pccbb_shutdown, sc); 502 503 #if __NetBSD_Version__ > 103060000 504 config_defer(self, pccbb_pci_callback); 505 #else 506 pccbb_pci_callback(self); 507 #endif 508 } 509 510 static void 511 pccbb_pci_callback(self) 512 struct device *self; 513 { 514 struct pccbb_softc *sc = (void *)self; 515 pci_chipset_tag_t pc = sc->sc_pc; 516 bus_space_tag_t base_memt; 517 bus_space_handle_t base_memh; 518 u_int32_t maskreg; 519 pci_intr_handle_t ih; 520 const char *intrstr = NULL; 521 bus_addr_t sockbase; 522 struct cbslot_attach_args cba; 523 struct pcmciabus_attach_args paa; 524 struct cardslot_attach_args caa; 525 struct cardslot_softc *csc; 526 527 if (0 == sc->sc_base_memh) { 528 /* The socket registers aren't mapped correctly. */ 529 #if rbus 530 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 531 (sc->sc_chipset == CB_RX5C47X 532 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 533 0, &sockbase, &sc->sc_base_memh)) { 534 return; 535 } 536 sc->sc_base_memt = sc->sc_memt; 537 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 538 DPRINTF(("%s: CardBus resister address 0x%lx -> 0x%x\n", 539 sc->sc_dev.dv_xname, sockbase, pci_conf_read(pc, sc->sc_tag, 540 PCI_SOCKBASE))); 541 #else 542 sc->sc_base_memt = sc->sc_memt; 543 #if !defined CBB_PCI_BASE 544 #define CBB_PCI_BASE 0x20000000 545 #endif 546 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 547 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 548 /* cannot allocate memory space */ 549 return; 550 } 551 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 552 DPRINTF(("%s: CardBus resister address 0x%x -> 0x%x\n", 553 sc->sc_dev.dv_xname, sock_base, pci_conf_read(pc, 554 sc->sc_tag, PCI_SOCKBASE))); 555 #endif 556 } 557 558 /* bus bridge initialisation */ 559 pccbb_chipinit(sc); 560 561 base_memt = sc->sc_base_memt; /* socket regs memory tag */ 562 base_memh = sc->sc_base_memh; /* socket regs memory handle */ 563 564 /* CSC Interrupt: Card detect interrupt on */ 565 maskreg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 566 maskreg |= CB_SOCKET_MASK_CD; /* Card detect intr is turned on. */ 567 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, maskreg); 568 /* reset interrupt */ 569 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, 570 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT)); 571 572 /* Map and establish the interrupt. */ 573 if (pci_intr_map(pc, sc->sc_intrtag, sc->sc_intrpin, 574 sc->sc_intrline, &ih)) { 575 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 576 return; 577 } 578 intrstr = pci_intr_string(pc, ih); 579 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 580 581 if (sc->sc_ih == NULL) { 582 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 583 if (intrstr != NULL) { 584 printf(" at %s", intrstr); 585 } 586 printf("\n"); 587 return; 588 } 589 590 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 591 592 { 593 u_int32_t sockstat = 594 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 595 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 596 sc->sc_flags |= CBB_CARDEXIST; 597 } 598 } 599 600 /* 601 * attach cardbus 602 */ 603 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 604 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 605 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 606 607 /* initialise cbslot_attach */ 608 cba.cba_busname = "cardbus"; 609 cba.cba_iot = sc->sc_iot; 610 cba.cba_memt = sc->sc_memt; 611 cba.cba_dmat = sc->sc_dmat; 612 cba.cba_function = 0; 613 cba.cba_bus = (busreg >> 8) & 0x0ff; 614 cba.cba_cc = (void *)sc; 615 cba.cba_cf = &pccbb_funcs; 616 cba.cba_intrline = sc->sc_intrline; 617 618 #if rbus 619 cba.cba_rbus_iot = sc->sc_rbus_iot; 620 cba.cba_rbus_memt = sc->sc_rbus_memt; 621 #endif 622 623 cba.cba_cacheline = PCI_CACHELINE(bhlc); 624 cba.cba_lattimer = PCI_CB_LATENCY(busreg); 625 626 printf("%s: cacheline 0x%x lattimer 0x%x\n", 627 sc->sc_dev.dv_xname, cba.cba_cacheline, cba.cba_lattimer); 628 printf("%s: bhlc 0x%x lscp 0x%x\n", sc->sc_dev.dv_xname, bhlc, 629 busreg); 630 #if defined SHOW_REGS 631 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 632 sc->sc_base_memh); 633 #endif 634 } 635 636 pccbb_pcmcia_attach_setup(sc, &paa); 637 caa.caa_cb_attach = NULL; 638 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 639 caa.caa_cb_attach = &cba; 640 } 641 caa.caa_16_attach = &paa; 642 caa.caa_ph = &sc->sc_pcmcia_h; 643 644 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 645 DPRINTF(("pccbbattach: found cardslot\n")); 646 sc->sc_csc = csc; 647 } 648 649 return; 650 } 651 652 static void 653 pccbb_chipinit(sc) 654 struct pccbb_softc *sc; 655 { 656 pci_chipset_tag_t pc = sc->sc_pc; 657 pcitag_t tag = sc->sc_tag; 658 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 659 bus_space_handle_t base_memh = sc->sc_base_memh; 660 pcireg_t cbctrl; 661 662 /* 663 * Set PCI command reg. 664 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 665 */ 666 { 667 pcireg_t command = 668 pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 669 670 /* I believe it is harmless. */ 671 command |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 672 PCI_COMMAND_MASTER_ENABLE); 673 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, command); 674 } 675 676 /* 677 * Set CardBus latency timer 678 */ 679 { 680 pcireg_t pci_lscp = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 681 if (PCI_CB_LATENCY(pci_lscp) < 0x20) { 682 pci_lscp &= 683 ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 684 pci_lscp |= (0x20 << PCI_CB_LATENCY_SHIFT); 685 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, pci_lscp); 686 } 687 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 688 PCI_CB_LATENCY(pci_lscp), pci_conf_read(pc, tag, 689 PCI_CB_LSCP_REG))); 690 } 691 692 /* 693 * Set PCI latency timer 694 */ 695 { 696 pcireg_t pci_bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG); 697 if (PCI_LATTIMER(pci_bhlc) < 0x10) { 698 pci_bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 699 pci_bhlc |= (0x10 << PCI_LATTIMER_SHIFT); 700 pci_conf_write(pc, tag, PCI_BHLC_REG, pci_bhlc); 701 } 702 DPRINTF(("PCI latency timer 0x%x (%x)\n", 703 PCI_LATTIMER(pci_bhlc), pci_conf_read(pc, tag, 704 PCI_BHLC_REG))); 705 } 706 707 /* disable Legacy IO */ 708 709 switch (sc->sc_chipset) { 710 case CB_RX5C46X: /* fallthrogh */ 711 #if 0 712 case CB_RX5C47X: 713 #endif 714 /* 715 * The legacy pcic io-port on Ricoh CardBus bridges cannot be 716 * disabled by substituting 0 into PCI_LEGACY register. Ricoh 717 * CardBus bridges have special bits on Bridge control reg (addr 718 * 0x3e on PCI config space). 719 */ 720 { 721 pcireg_t bcri = pci_conf_read(pc, tag, PCI_BCR_INTR); 722 bcri &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 723 pci_conf_write(pc, tag, PCI_BCR_INTR, bcri); 724 } 725 break; 726 default: 727 /* XXX: I don't know proper way to kill Legacy IO properly. */ 728 pci_conf_write(pc, tag, PCI_LEGACY, 0x0); 729 break; 730 } 731 732 /* 733 * Interrupt routing: use PCI interrupt 734 */ 735 { 736 u_int32_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 737 bcr &= ~CB_BCR_INTR_IREQ_ENABLE; /* use PCI Intr */ 738 bcr |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 739 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 740 } 741 742 if (CB_TI113X == sc->sc_chipset) { 743 cbctrl = pci_conf_read(pc, tag, PCI_CBCTRL); 744 if (0 == sc->sc_function) { 745 cbctrl |= PCI113X_CBCTRL_PCI_IRQ_ENA; 746 } 747 /* XXX: bug in PCI113X */ 748 cbctrl |= PCI113X_CBCTRL_PCI_IRQ_ENA; 749 /* CSC intr enable */ 750 cbctrl |= PCI113X_CBCTRL_PCI_CSC; 751 /* functional intr prohibit */ 752 cbctrl &= ~PCI113X_CBCTRL_PCI_INTR; 753 /* prohibit ISA routing */ 754 cbctrl &= ~PCI113X_CBCTRL_INT_MASK; 755 pci_conf_write(pc, tag, PCI_CBCTRL, cbctrl); 756 757 /* 758 * set ExCA regs: PCI113X required to be set bit 4 at Interrupt 759 * and General Register, which is IRQ Enable Register, and 760 * clear bit 3:0 to zero in order to route CSC interrupt to 761 * PCI interrupt pin. 762 */ 763 bus_space_write_1(base_memt, base_memh, 0x0803, 0x10); 764 /* set ExCA regs: prohibit all pcmcia-style CSC intr. */ 765 bus_space_write_1(base_memt, base_memh, 0x0805, 0x00); 766 #if 1 767 DPRINTF(("ExCA regs:")); 768 DPRINTF((" 0x803: %02x", bus_space_read_1(base_memt, base_memh, 769 0x803))); 770 DPRINTF((" 0x805: %02x", bus_space_read_1(base_memt, base_memh, 771 0x805))); 772 DPRINTF((" 0x81e: %02x\n", bus_space_read_1(base_memt, 773 base_memh, 0x81e))); 774 #endif 775 } else if (sc->sc_chipset == CB_TI12XX) { 776 cbctrl = pci_conf_read(pc, tag, PCI_CBCTRL); 777 cbctrl &= ~PCI12XX_CBCTRL_INT_MASK; /* intr routing reset */ 778 pci_conf_write(pc, tag, PCI_CBCTRL, cbctrl); 779 /* 780 * set ExCA regs: PCI12XX required to be set bit 4 at Interrupt 781 * and General Register, which is IRQ Enable Register, and clear 782 * bit 3:0 to zero in order to route CSC interrupt to PCI 783 * interrupt pin. 784 */ 785 bus_space_write_1(base_memt, base_memh, 0x0803, 0x10); 786 /* set ExCA regs: prohibit all pcmcia-style CSC intr. */ 787 bus_space_write_1(base_memt, base_memh, 0x0805, 0x00); 788 } else if (sc->sc_chipset == CB_TOPIC95B) { 789 cardbusreg_t sock_ctrl, slot_ctrl; 790 791 sock_ctrl = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 792 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, 793 sock_ctrl | TOPIC_SOCKET_CTRL_SCR_IRQSEL); 794 795 slot_ctrl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 796 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 797 sc->sc_dev.dv_xname, slot_ctrl)); 798 slot_ctrl |= 799 (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 800 TOPIC_SLOT_CTRL_ID_LOCK); 801 slot_ctrl |= TOPIC_SLOT_CTRL_CARDBUS; 802 slot_ctrl &= ~TOPIC_SLOT_CTRL_SWDETECT; 803 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slot_ctrl); 804 DPRINTF(("0x%x\n", slot_ctrl)); 805 } 806 807 /* close all memory and io windows */ 808 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 809 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 810 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 811 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 812 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 813 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 814 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 815 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 816 817 return; 818 } 819 820 /* 821 * attach pccard bus 822 */ 823 STATIC void 824 pccbb_pcmcia_attach_setup(sc, paa) 825 struct pccbb_softc *sc; 826 struct pcmciabus_attach_args *paa; 827 { 828 struct pcic_handle *ph = &sc->sc_pcmcia_h; 829 #if rbus 830 rbus_tag_t rb; 831 #endif 832 833 /* initialise pcmcia part in pccbb_softc */ 834 ph->ph_parent = (struct device *)sc; 835 ph->sock = sc->sc_function; 836 ph->flags = 0; 837 ph->shutdown = 0; 838 ph->ih_irq = sc->sc_intrline; 839 ph->ph_bus_t = sc->sc_base_memt; 840 ph->ph_bus_h = sc->sc_base_memh; 841 ph->ph_read = pccbb_pcmcia_read; 842 ph->ph_write = pccbb_pcmcia_write; 843 sc->sc_pct = &pccbb_pcmcia_funcs; 844 845 Pcic_write(ph, PCIC_CSC_INTR, 0); 846 Pcic_read(ph, PCIC_CSC); 847 848 /* initialise pcmcia bus attachment */ 849 paa->paa_busname = "pcmcia"; 850 paa->pct = sc->sc_pct; 851 paa->pch = ph; 852 paa->iobase = 0; /* I don't use them */ 853 paa->iosize = 0; 854 #if rbus 855 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 856 paa->iobase = rb->rb_start + rb->rb_offset; 857 paa->iosize = rb->rb_end - rb->rb_start; 858 #endif 859 860 return; 861 } 862 863 #if 0 864 STATIC void 865 pccbb_pcmcia_attach_card(ph) 866 struct pcic_handle *ph; 867 { 868 if (ph->flags & PCIC_FLAG_CARDP) { 869 panic("pccbb_pcmcia_attach_card: already attached"); 870 } 871 872 /* call the MI attach function */ 873 pcmcia_card_attach(ph->pcmcia); 874 875 ph->flags |= PCIC_FLAG_CARDP; 876 } 877 878 STATIC void 879 pccbb_pcmcia_detach_card(ph, flags) 880 struct pcic_handle *ph; 881 int flags; 882 { 883 if (!(ph->flags & PCIC_FLAG_CARDP)) { 884 panic("pccbb_pcmcia_detach_card: already detached"); 885 } 886 887 ph->flags &= ~PCIC_FLAG_CARDP; 888 889 /* call the MI detach function */ 890 pcmcia_card_detach(ph->pcmcia, flags); 891 } 892 #endif 893 894 /* 895 * int pccbbintr(arg) 896 * void *arg; 897 * This routine handles the interrupt from Yenta PCI-CardBus bridge 898 * itself. 899 */ 900 int 901 pccbbintr(arg) 902 void *arg; 903 { 904 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 905 u_int32_t sockevent; 906 bus_space_tag_t memt = sc->sc_base_memt; 907 bus_space_handle_t memh = sc->sc_base_memh; 908 u_int32_t sockstate; 909 910 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 911 if (0 == sockevent) { 912 /* This intr is not for me: it may be for my child devices. */ 913 return pccbbintr_function(sc); 914 } else { 915 /* reset bit */ 916 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 917 } 918 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 919 920 if (sockevent & CB_SOCKET_EVENT_CD) { 921 if (CB_SOCKET_STAT_CD == (sockstate & CB_SOCKET_STAT_CD)) { 922 /* A card should be removed. */ 923 if (sc->sc_flags & CBB_CARDEXIST) { 924 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 925 sockevent)); 926 DPRINTF((" card removed, 0x%08x\n", sockstate)); 927 sc->sc_flags &= ~CBB_CARDEXIST; 928 if (sc-> 929 sc_csc->sc_status & CARDSLOT_STATUS_CARD_16) 930 { 931 #if 0 932 struct pcic_handle *ph = 933 &sc->sc_pcmcia_h; 934 935 pcmcia_card_deactivate(ph->pcmcia); 936 pccbb_pcmcia_socket_disable(ph); 937 pccbb_pcmcia_detach_card(ph, 938 DETACH_FORCE); 939 #endif 940 cardslot_event_throw(sc->sc_csc, 941 CARDSLOT_EVENT_REMOVAL_16); 942 } else if (sc-> 943 sc_csc->sc_status & CARDSLOT_STATUS_CARD_CB) 944 { 945 /* Cardbus intr removed */ 946 cardslot_event_throw(sc->sc_csc, 947 CARDSLOT_EVENT_REMOVAL_CB); 948 } 949 } 950 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD)) { 951 if (sc->sc_flags & CBB_INSERTING) { 952 untimeout(pci113x_insert, sc); 953 } 954 timeout(pci113x_insert, sc, hz / 10); 955 sc->sc_flags |= CBB_INSERTING; 956 } 957 } else { 958 DPRINTF(("%s: sockevent = %b\n", 959 sc->sc_dev.dv_xname, sockevent, PCCBB_SOCKEVENT_BITS)); 960 DPRINTF(("%s: sockstate = %b\n", 961 sc->sc_dev.dv_xname, sockstate, PCCBB_SOCKSTATE_BITS)); 962 } 963 964 return 1; 965 } 966 967 /* 968 * static int pccbbintr_function(struct pccbb_softc *sc) 969 * 970 * This function calls each interrupt handler registered at the 971 * bridge. The interrupt handlers are called in registerd order. 972 */ 973 static int 974 pccbbintr_function(sc) 975 struct pccbb_softc *sc; 976 { 977 int retval = 0, val; 978 struct pccbb_intrhand_list *pil; 979 980 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 981 val = (*pil->pil_func) (pil->pil_arg); 982 retval = retval == 1 ? 1 : 983 retval == 0 ? val : val != 0 ? val : retval; 984 } 985 986 return retval; 987 } 988 989 static void 990 pci113x_insert(arg) 991 void *arg; 992 { 993 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 994 u_int32_t sockevent, sockstate; 995 996 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 997 CB_SOCKET_EVENT); 998 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 999 CB_SOCKET_STAT); 1000 1001 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1002 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1003 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1004 sc->sc_flags |= CBB_CARDEXIST; 1005 /* call pccard intterupt handler here */ 1006 if (sockstate & CB_SOCKET_STAT_16BIT) { 1007 /* 16-bit card found */ 1008 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1009 cardslot_event_throw(sc->sc_csc, 1010 CARDSLOT_EVENT_INSERTION_16); 1011 } else if (sockstate & CB_SOCKET_STAT_CB) { 1012 /* cardbus card fuond */ 1013 /* cardbus_attach_card(sc->sc_csc); */ 1014 cardslot_event_throw(sc->sc_csc, 1015 CARDSLOT_EVENT_INSERTION_CB); 1016 } else { 1017 /* who are you? */ 1018 } 1019 } else { 1020 timeout(pci113x_insert, sc, hz / 10); 1021 } 1022 } 1023 1024 #define PCCBB_PCMCIA_OFFSET 0x800 1025 static u_int8_t 1026 pccbb_pcmcia_read(ph, reg) 1027 struct pcic_handle *ph; 1028 int reg; 1029 { 1030 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1031 PCCBB_PCMCIA_OFFSET + reg); 1032 } 1033 1034 static void 1035 pccbb_pcmcia_write(ph, reg, val) 1036 struct pcic_handle *ph; 1037 int reg; 1038 u_int8_t val; 1039 { 1040 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1041 val); 1042 } 1043 1044 /* 1045 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1046 */ 1047 STATIC int 1048 pccbb_ctrl(ct, command) 1049 cardbus_chipset_tag_t ct; 1050 int command; 1051 { 1052 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1053 1054 switch (command) { 1055 case CARDBUS_CD: 1056 if (2 == pccbb_detect_card(sc)) { 1057 int retval = 0; 1058 int status = cb_detect_voltage(sc); 1059 if (PCCARD_VCC_5V & status) { 1060 retval |= CARDBUS_5V_CARD; 1061 } 1062 if (PCCARD_VCC_3V & status) { 1063 retval |= CARDBUS_3V_CARD; 1064 } 1065 if (PCCARD_VCC_XV & status) { 1066 retval |= CARDBUS_XV_CARD; 1067 } 1068 if (PCCARD_VCC_YV & status) { 1069 retval |= CARDBUS_YV_CARD; 1070 } 1071 return retval; 1072 } else { 1073 return 0; 1074 } 1075 break; 1076 case CARDBUS_RESET: 1077 return cb_reset(sc); 1078 break; 1079 case CARDBUS_IO_ENABLE: /* fallthrough */ 1080 case CARDBUS_IO_DISABLE: /* fallthrough */ 1081 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1082 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1083 case CARDBUS_BM_ENABLE: /* fallthrough */ 1084 case CARDBUS_BM_DISABLE: /* fallthrough */ 1085 return pccbb_cardenable(sc, command); 1086 break; 1087 } 1088 1089 return 0; 1090 } 1091 1092 /* 1093 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1094 * This function returns true when it succeeds and returns false when 1095 * it fails. 1096 */ 1097 STATIC int 1098 pccbb_power(ct, command) 1099 cardbus_chipset_tag_t ct; 1100 int command; 1101 { 1102 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1103 1104 u_int32_t status, sock_ctrl; 1105 bus_space_tag_t memt = sc->sc_base_memt; 1106 bus_space_handle_t memh = sc->sc_base_memh; 1107 1108 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1109 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1110 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1111 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1112 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1113 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1114 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1115 "UNKNOWN", 1116 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1117 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1118 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1119 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1120 "UNKNOWN", command)); 1121 1122 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1123 sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1124 1125 switch (command & CARDBUS_VCCMASK) { 1126 case CARDBUS_VCC_UC: 1127 break; 1128 case CARDBUS_VCC_5V: 1129 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1130 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1131 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1132 } else { 1133 printf("%s: BAD voltage request: no 5 V card\n", 1134 sc->sc_dev.dv_xname); 1135 } 1136 break; 1137 case CARDBUS_VCC_3V: 1138 if (CB_SOCKET_STAT_3VCARD & status) { 1139 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1140 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1141 } else { 1142 printf("%s: BAD voltage request: no 3.3 V card\n", 1143 sc->sc_dev.dv_xname); 1144 } 1145 break; 1146 case CARDBUS_VCC_0V: 1147 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1148 break; 1149 default: 1150 return 0; /* power NEVER changed */ 1151 break; 1152 } 1153 1154 switch (command & CARDBUS_VPPMASK) { 1155 case CARDBUS_VPP_UC: 1156 break; 1157 case CARDBUS_VPP_0V: 1158 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1159 break; 1160 case CARDBUS_VPP_VCC: 1161 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1162 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1163 break; 1164 case CARDBUS_VPP_12V: 1165 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1166 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1167 break; 1168 } 1169 1170 #if 0 1171 DPRINTF(("sock_ctrl: %x\n", sock_ctrl)); 1172 #endif 1173 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1174 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1175 1176 delay(20 * 1000); /* wait 20 ms: Vcc setup time */ 1177 /* 1178 * XXX delay 200 ms: though the standard defines that the Vcc set-up 1179 * time is 20 ms, some PC-Card bridge requires longer duration. 1180 */ 1181 delay(200 * 1000); 1182 1183 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1184 printf 1185 ("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1186 sc->sc_dev.dv_xname, sock_ctrl, status); 1187 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1188 (command & CARDBUS_VCCMASK) == 1189 CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : (command & 1190 CARDBUS_VCCMASK) == 1191 CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : (command & 1192 CARDBUS_VCCMASK) == 1193 CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : (command & 1194 CARDBUS_VCCMASK) == 1195 CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : (command & 1196 CARDBUS_VCCMASK) == 1197 CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : (command & 1198 CARDBUS_VCCMASK) == 1199 CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : "UNKNOWN", 1200 (command & CARDBUS_VPPMASK) == 1201 CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : (command & 1202 CARDBUS_VPPMASK) == 1203 CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : (command & 1204 CARDBUS_VPPMASK) == 1205 CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : (command & 1206 CARDBUS_VPPMASK) == 1207 CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : "UNKNOWN", command)); 1208 #if 0 1209 if (command == (CARDBUS_VCC_0V | CARDBUS_VPP_0V)) { 1210 u_int32_t force = 1211 bus_space_read_4(memt, memh, CB_SOCKET_FORCE); 1212 /* Reset Bad Vcc request */ 1213 force &= ~CB_SOCKET_FORCE_BADVCC; 1214 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, force); 1215 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1216 CB_SOCKET_STAT)); 1217 return 1; 1218 } 1219 #endif 1220 return 0; 1221 } 1222 return 1; /* power changed correctly */ 1223 } 1224 1225 #if defined CB_PCMCIA_POLL 1226 struct cb_poll_str { 1227 void *arg; 1228 int (*func) __P((void *)); 1229 int level; 1230 pccard_chipset_tag_t ct; 1231 int count; 1232 }; 1233 1234 static struct cb_poll_str cb_poll[10]; 1235 static int cb_poll_n = 0; 1236 1237 static void cb_pcmcia_poll __P((void *arg)); 1238 1239 static void 1240 cb_pcmcia_poll(arg) 1241 void *arg; 1242 { 1243 struct cb_poll_str *poll = arg; 1244 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1245 struct pccbb_softc *sc = psc->cpc_parent; 1246 int s; 1247 u_int32_t spsr; /* socket present-state reg */ 1248 1249 timeout(cb_pcmcia_poll, arg, hz / 10); 1250 switch (poll->level) { 1251 case IPL_NET: 1252 s = splnet(); 1253 break; 1254 case IPL_BIO: 1255 s = splbio(); 1256 break; 1257 case IPL_TTY: /* fallthrough */ 1258 default: 1259 s = spltty(); 1260 break; 1261 } 1262 1263 spsr = 1264 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1265 CB_SOCKET_STAT); 1266 1267 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1268 if (!(spsr & 0x40)) { /* CINT low */ 1269 #else 1270 if (1) { 1271 #endif 1272 if ((*poll->func) (poll->arg) == 1) { 1273 ++poll->count; 1274 printf("intr: reported from poller, 0x%x\n", spsr); 1275 #if defined LEVEL2 1276 } else { 1277 printf("intr: miss! 0x%x\n", spsr); 1278 #endif 1279 } 1280 } 1281 splx(s); 1282 } 1283 #endif /* defined CB_PCMCIA_POLL */ 1284 1285 /* 1286 * static int pccbb_detect_card(struct pccbb_softc *sc) 1287 * return value: 0 if no card exists. 1288 * 1 if 16-bit card exists. 1289 * 2 if cardbus card exists. 1290 */ 1291 static int 1292 pccbb_detect_card(sc) 1293 struct pccbb_softc *sc; 1294 { 1295 bus_space_handle_t base_memh = sc->sc_base_memh; 1296 bus_space_tag_t base_memt = sc->sc_base_memt; 1297 u_int32_t sockstat = 1298 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1299 int retval = 0; 1300 1301 /* CD1 and CD2 asserted */ 1302 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1303 /* card must be present */ 1304 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1305 /* NOTACARD DEASSERTED */ 1306 if (CB_SOCKET_STAT_CB & sockstat) { 1307 /* CardBus mode */ 1308 retval = 2; 1309 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1310 /* 16-bit mode */ 1311 retval = 1; 1312 } 1313 } 1314 } 1315 return retval; 1316 } 1317 1318 /* 1319 * STATIC int cb_reset(struct pccbb_softc *sc) 1320 * This function resets CardBus card. 1321 */ 1322 STATIC int 1323 cb_reset(sc) 1324 struct pccbb_softc *sc; 1325 { 1326 /* 1327 * Reset Assert at least 20 ms 1328 * Some machines request longer duration. 1329 */ 1330 int reset_duration = 1331 (sc->sc_chipset == CB_RX5C47X ? 400 * 1000 : 40 * 1000); 1332 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1333 1334 bcr |= (0x40 << 16); /* Reset bit Assert (bit 6 at 0x3E) */ 1335 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1336 delay(reset_duration); 1337 1338 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1339 bcr &= ~(0x40 << 16); /* Reset bit Deassert (bit 6 at 0x3E) */ 1340 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1341 delay(reset_duration); 1342 } 1343 /* No card found on the slot. Keep Reset. */ 1344 return 1; 1345 } 1346 1347 /* 1348 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1349 * This function detect card Voltage. 1350 */ 1351 STATIC int 1352 cb_detect_voltage(sc) 1353 struct pccbb_softc *sc; 1354 { 1355 u_int32_t psr; /* socket present-state reg */ 1356 bus_space_tag_t iot = sc->sc_base_memt; 1357 bus_space_handle_t ioh = sc->sc_base_memh; 1358 int vol = PCCARD_VCC_UKN; /* set 0 */ 1359 1360 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1361 1362 if (0x400u & psr) { 1363 vol |= PCCARD_VCC_5V; 1364 } 1365 if (0x800u & psr) { 1366 vol |= PCCARD_VCC_3V; 1367 } 1368 1369 return vol; 1370 } 1371 1372 STATIC int 1373 cbbprint(aux, pcic) 1374 void *aux; 1375 const char *pcic; 1376 { 1377 /* 1378 struct cbslot_attach_args *cba = aux; 1379 1380 if (cba->cba_slot >= 0) { 1381 printf(" slot %d", cba->cba_slot); 1382 } 1383 */ 1384 return UNCONF; 1385 } 1386 1387 /* 1388 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1389 * This function enables and disables the card 1390 */ 1391 STATIC int 1392 pccbb_cardenable(sc, function) 1393 struct pccbb_softc *sc; 1394 int function; 1395 { 1396 u_int32_t command = 1397 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1398 1399 DPRINTF(("pccbb_cardenable:")); 1400 switch (function) { 1401 case CARDBUS_IO_ENABLE: 1402 command |= PCI_COMMAND_IO_ENABLE; 1403 break; 1404 case CARDBUS_IO_DISABLE: 1405 command &= ~PCI_COMMAND_IO_ENABLE; 1406 break; 1407 case CARDBUS_MEM_ENABLE: 1408 command |= PCI_COMMAND_MEM_ENABLE; 1409 break; 1410 case CARDBUS_MEM_DISABLE: 1411 command &= ~PCI_COMMAND_MEM_ENABLE; 1412 break; 1413 case CARDBUS_BM_ENABLE: 1414 command |= PCI_COMMAND_MASTER_ENABLE; 1415 break; 1416 case CARDBUS_BM_DISABLE: 1417 command &= ~PCI_COMMAND_MASTER_ENABLE; 1418 break; 1419 default: 1420 return 0; 1421 } 1422 1423 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1424 DPRINTF((" command reg 0x%x\n", command)); 1425 return 1; 1426 } 1427 1428 #if !rbus 1429 /* 1430 * int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1431 */ 1432 static int 1433 pccbb_io_open(ct, win, start, end) 1434 cardbus_chipset_tag_t ct; 1435 int win; 1436 u_int32_t start, end; 1437 { 1438 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1439 int basereg; 1440 int limitreg; 1441 1442 if ((win < 0) || (win > 2)) { 1443 #if defined DIAGNOSTIC 1444 printf("cardbus_io_open: window out of range %d\n", win); 1445 #endif 1446 return 0; 1447 } 1448 1449 basereg = win * 8 + 0x2c; 1450 limitreg = win * 8 + 0x30; 1451 1452 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1453 start, basereg, end, limitreg)); 1454 1455 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1456 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1457 return 1; 1458 } 1459 1460 /* 1461 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1462 */ 1463 static int 1464 pccbb_io_close(ct, win) 1465 cardbus_chipset_tag_t ct; 1466 int win; 1467 { 1468 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1469 int basereg; 1470 int limitreg; 1471 1472 if ((win < 0) || (win > 2)) { 1473 #if defined DIAGNOSTIC 1474 printf("cardbus_io_close: window out of range %d\n", win); 1475 #endif 1476 return 0; 1477 } 1478 1479 basereg = win * 8 + 0x2c; 1480 limitreg = win * 8 + 0x30; 1481 1482 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1483 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1484 return 1; 1485 } 1486 1487 /* 1488 * int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1489 */ 1490 static int 1491 pccbb_mem_open(ct, win, start, end) 1492 cardbus_chipset_tag_t ct; 1493 int win; 1494 u_int32_t start, end; 1495 { 1496 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1497 int basereg; 1498 int limitreg; 1499 1500 if ((win < 0) || (win > 2)) { 1501 #if defined DIAGNOSTIC 1502 printf("cardbus_mem_open: window out of range %d\n", win); 1503 #endif 1504 return 0; 1505 } 1506 1507 basereg = win * 8 + 0x1c; 1508 limitreg = win * 8 + 0x20; 1509 1510 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1511 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1512 return 1; 1513 } 1514 1515 /* 1516 * int pccbb_mem_close(cardbus_chipset_tag_t, int) 1517 */ 1518 static int 1519 pccbb_mem_close(ct, win) 1520 cardbus_chipset_tag_t ct; 1521 int win; 1522 { 1523 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1524 int basereg; 1525 int limitreg; 1526 1527 if ((win < 0) || (win > 2)) { 1528 #if defined DIAGNOSTIC 1529 printf("cardbus_mem_close: window out of range %d\n", win); 1530 #endif 1531 return 0; 1532 } 1533 1534 basereg = win * 8 + 0x1c; 1535 limitreg = win * 8 + 0x20; 1536 1537 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1538 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1539 return 1; 1540 } 1541 #endif 1542 1543 /* 1544 * static void *pccbb_intr_establish(cardbus_chipset_tag_t ct, 1545 * int irq, 1546 * int level, 1547 * int (* func) __P((void *)), 1548 * void *arg) 1549 * 1550 * This function registers an interrupt handler at the bridge, in 1551 * order not to call the interrput handlers of child devices when 1552 * a card-deletion interrput occurs. 1553 * 1554 * The arguments irq and level are not used. 1555 */ 1556 static void * 1557 pccbb_intr_establish(ct, irq, level, func, arg) 1558 cardbus_chipset_tag_t ct; 1559 int irq, level; 1560 int (*func) __P((void *)); 1561 void *arg; 1562 { 1563 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1564 struct pccbb_intrhand_list *pil, *newpil; 1565 1566 if (sc->sc_pil == NULL) { 1567 /* initialise bridge intr routing */ 1568 1569 switch (sc->sc_chipset) { 1570 case CB_TI113X: 1571 { 1572 pcireg_t cbctrl = 1573 pci_conf_read(sc->sc_pc, sc->sc_tag, 1574 PCI_CBCTRL); 1575 /* functional intr enabled */ 1576 cbctrl |= PCI113X_CBCTRL_PCI_INTR; 1577 pci_conf_write(sc->sc_pc, sc->sc_tag, 1578 PCI_CBCTRL, cbctrl); 1579 break; 1580 } 1581 default: 1582 break; 1583 } 1584 } 1585 1586 /* 1587 * Allocate a room for interrut handler structure. 1588 */ 1589 if (NULL == (newpil = 1590 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1591 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1592 return NULL; 1593 } 1594 1595 newpil->pil_func = func; 1596 newpil->pil_arg = arg; 1597 newpil->pil_next = NULL; 1598 1599 if (sc->sc_pil == NULL) { 1600 sc->sc_pil = newpil; 1601 } else { 1602 for (pil = sc->sc_pil; pil->pil_next != NULL; 1603 pil = pil->pil_next); 1604 pil->pil_next = newpil; 1605 } 1606 1607 return newpil; 1608 } 1609 1610 /* 1611 * static void *pccbb_intr_disestablish(cardbus_chipset_tag_t ct, 1612 * void *ih) 1613 * 1614 * This function removes an interrupt handler pointed by ih. 1615 */ 1616 static void 1617 pccbb_intr_disestablish(ct, ih) 1618 cardbus_chipset_tag_t ct; 1619 void *ih; 1620 { 1621 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1622 struct pccbb_intrhand_list *pil, **pil_prev; 1623 1624 pil_prev = &sc->sc_pil; 1625 1626 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 1627 if (pil == ih) { 1628 *pil_prev = pil->pil_next; 1629 free(pil, M_DEVBUF); 1630 break; 1631 } 1632 pil_prev = &pil->pil_next; 1633 } 1634 1635 if (sc->sc_pil == NULL) { 1636 /* No interrupt handlers */ 1637 1638 switch (sc->sc_chipset) { 1639 case CB_TI113X: 1640 { 1641 pcireg_t cbctrl = 1642 pci_conf_read(sc->sc_pc, sc->sc_tag, 1643 PCI_CBCTRL); 1644 /* functional intr disabled */ 1645 cbctrl &= ~PCI113X_CBCTRL_PCI_INTR; 1646 pci_conf_write(sc->sc_pc, sc->sc_tag, 1647 PCI_CBCTRL, cbctrl); 1648 break; 1649 } 1650 default: 1651 break; 1652 } 1653 } 1654 } 1655 1656 #if defined SHOW_REGS 1657 static void 1658 cb_show_regs(pc, tag, memt, memh) 1659 pci_chipset_tag_t pc; 1660 pcitag_t tag; 1661 bus_space_tag_t memt; 1662 bus_space_handle_t memh; 1663 { 1664 int i; 1665 printf("PCI config regs:"); 1666 for (i = 0; i < 0x50; i += 4) { 1667 if (i % 16 == 0) { 1668 printf("\n 0x%02x:", i); 1669 } 1670 printf(" %08x", pci_conf_read(pc, tag, i)); 1671 } 1672 for (i = 0x80; i < 0xb0; i += 4) { 1673 if (i % 16 == 0) { 1674 printf("\n 0x%02x:", i); 1675 } 1676 printf(" %08x", pci_conf_read(pc, tag, i)); 1677 } 1678 1679 if (memh == 0) { 1680 printf("\n"); 1681 return; 1682 } 1683 1684 printf("\nsocket regs:"); 1685 for (i = 0; i <= 0x10; i += 0x04) { 1686 printf(" %08x", bus_space_read_4(memt, memh, i)); 1687 } 1688 printf("\nExCA regs:"); 1689 for (i = 0; i < 0x08; ++i) { 1690 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1691 } 1692 printf("\n"); 1693 return; 1694 } 1695 #endif 1696 1697 /* 1698 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1699 * int busno, int devno, int function) 1700 * This is the function to make a tag to access config space of 1701 * a CardBus Card. It works same as pci_conf_read. 1702 */ 1703 static cardbustag_t 1704 pccbb_make_tag(cc, busno, devno, function) 1705 cardbus_chipset_tag_t cc; 1706 int busno, devno, function; 1707 { 1708 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1709 1710 return pci_make_tag(sc->sc_pc, busno, devno, function); 1711 } 1712 1713 static void 1714 pccbb_free_tag(cc, tag) 1715 cardbus_chipset_tag_t cc; 1716 cardbustag_t tag; 1717 { 1718 } 1719 1720 /* 1721 * static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t cc, 1722 * cardbustag_t tag, int offset) 1723 * This is the function to read the config space of a CardBus Card. 1724 * It works same as pci_conf_read. 1725 */ 1726 static cardbusreg_t 1727 pccbb_conf_read(cc, tag, offset) 1728 cardbus_chipset_tag_t cc; 1729 cardbustag_t tag; 1730 int offset; /* register offset */ 1731 { 1732 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1733 1734 return pci_conf_read(sc->sc_pc, tag, offset); 1735 } 1736 1737 /* 1738 * static void pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, 1739 * int offs, cardbusreg_t val) 1740 * This is the function to write the config space of a CardBus Card. 1741 * It works same as pci_conf_write. 1742 */ 1743 static void 1744 pccbb_conf_write(cc, tag, reg, val) 1745 cardbus_chipset_tag_t cc; 1746 cardbustag_t tag; 1747 int reg; /* register offset */ 1748 cardbusreg_t val; 1749 { 1750 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1751 1752 pci_conf_write(sc->sc_pc, tag, reg, val); 1753 } 1754 1755 #if 0 1756 STATIC int 1757 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1758 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 1759 int speed, int flags, 1760 bus_space_handle_t * iohp) 1761 #endif 1762 /* 1763 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1764 * bus_addr_t start, bus_size_t size, 1765 * bus_size_t align, 1766 * struct pcmcia_io_handle *pcihp 1767 * 1768 * This function only allocates I/O region for pccard. This function 1769 * never maps the allcated region to pccard I/O area. 1770 * 1771 * XXX: The interface of this function is not very good, I believe. 1772 */ 1773 STATIC int 1774 pccbb_pcmcia_io_alloc(pch, start, size, align, pcihp) 1775 pcmcia_chipset_handle_t pch; 1776 bus_addr_t start; /* start address */ 1777 bus_size_t size; 1778 bus_size_t align; 1779 struct pcmcia_io_handle *pcihp; 1780 { 1781 struct pcic_handle *ph = (struct pcic_handle *)pch; 1782 bus_addr_t ioaddr; 1783 int flags = 0; 1784 bus_space_tag_t iot; 1785 bus_space_handle_t ioh; 1786 #if rbus 1787 rbus_tag_t rb; 1788 #endif 1789 if (align == 0) { 1790 align = size; /* XXX: funny??? */ 1791 } 1792 1793 /* 1794 * Allocate some arbitrary I/O space. 1795 */ 1796 1797 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 1798 1799 #if rbus 1800 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 1801 /* XXX: I assume all card decode lower 10 bits by its hardware */ 1802 if (rbus_space_alloc(rb, start, size, 0x3ff, align, 0, &ioaddr, &ioh)) { 1803 return 1; 1804 } 1805 #else 1806 if (start) { 1807 ioaddr = start; 1808 if (bus_space_map(iot, start, size, 0, &ioh)) { 1809 return 1; 1810 } 1811 DPRINTF(("pccbb_pcmcia_io_alloc map port %lx+%lx\n", 1812 (u_long) ioaddr, (u_long) size)); 1813 } else { 1814 flags |= PCMCIA_IO_ALLOCATED; 1815 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 1816 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 1817 size, align, 0, 0, &ioaddr, &ioh)) { 1818 /* No room be able to be get. */ 1819 return 1; 1820 } 1821 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 1822 (u_long) ioaddr, (u_long) size)); 1823 } 1824 #endif 1825 1826 pcihp->iot = iot; 1827 pcihp->ioh = ioh; 1828 pcihp->addr = ioaddr; 1829 pcihp->size = size; 1830 pcihp->flags = flags; 1831 1832 return 0; 1833 } 1834 1835 /* 1836 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 1837 * struct pcmcia_io_handle *pcihp) 1838 * 1839 * This function only frees I/O region for pccard. 1840 * 1841 * XXX: The interface of this function is not very good, I believe. 1842 */ 1843 void 1844 pccbb_pcmcia_io_free(pch, pcihp) 1845 pcmcia_chipset_handle_t pch; 1846 struct pcmcia_io_handle *pcihp; 1847 { 1848 #if !rbus 1849 bus_space_tag_t iot = pcihp->iot; 1850 #endif 1851 bus_space_handle_t ioh = pcihp->ioh; 1852 bus_size_t size = pcihp->size; 1853 1854 #if rbus 1855 struct pccbb_softc *sc = 1856 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 1857 rbus_tag_t rb = sc->sc_rbus_iot; 1858 1859 rbus_space_free(rb, ioh, size, NULL); 1860 #else 1861 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 1862 bus_space_free(iot, ioh, size); 1863 else 1864 bus_space_unmap(iot, ioh, size); 1865 #endif 1866 } 1867 1868 /* 1869 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 1870 * bus_addr_t offset, bus_size_t size, 1871 * struct pcmcia_io_handle *pcihp, 1872 * int *windowp) 1873 * 1874 * This function maps the allocated I/O region to pccard. This function 1875 * never allocates any I/O region for pccard I/O area. I don't 1876 * understand why the original authors of pcmciabus separated alloc and 1877 * map. I believe the two must be unite. 1878 * 1879 * XXX: no wait timing control? 1880 */ 1881 int 1882 pccbb_pcmcia_io_map(pch, width, offset, size, pcihp, windowp) 1883 pcmcia_chipset_handle_t pch; 1884 int width; 1885 bus_addr_t offset; 1886 bus_size_t size; 1887 struct pcmcia_io_handle *pcihp; 1888 int *windowp; 1889 { 1890 struct pcic_handle *ph = (struct pcic_handle *)pch; 1891 bus_addr_t ioaddr = pcihp->addr + offset; 1892 int i, win; 1893 #if defined CBB_DEBUG 1894 static char *width_names[] = { "dynamic", "io8", "io16" }; 1895 #endif 1896 1897 /* Sanity check I/O handle. */ 1898 1899 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 1900 panic("pccbb_pcmcia_io_map iot is bogus"); 1901 } 1902 1903 /* XXX Sanity check offset/size. */ 1904 1905 win = -1; 1906 for (i = 0; i < PCIC_IO_WINS; i++) { 1907 if ((ph->ioalloc & (1 << i)) == 0) { 1908 win = i; 1909 ph->ioalloc |= (1 << i); 1910 break; 1911 } 1912 } 1913 1914 if (win == -1) { 1915 return 1; 1916 } 1917 1918 *windowp = win; 1919 1920 /* XXX this is pretty gross */ 1921 1922 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 1923 win, width_names[width], (u_long) ioaddr, (u_long) size)); 1924 1925 /* XXX wtf is this doing here? */ 1926 1927 #if 0 1928 printf(" port 0x%lx", (u_long) ioaddr); 1929 if (size > 1) { 1930 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 1931 } 1932 #endif 1933 1934 ph->io[win].addr = ioaddr; 1935 ph->io[win].size = size; 1936 ph->io[win].width = width; 1937 1938 /* actual dirty register-value changing in the function below. */ 1939 pccbb_pcmcia_do_io_map(ph, win); 1940 1941 return 0; 1942 } 1943 1944 /* 1945 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 1946 * 1947 * This function changes register-value to map I/O region for pccard. 1948 */ 1949 static void 1950 pccbb_pcmcia_do_io_map(ph, win) 1951 struct pcic_handle *ph; 1952 int win; 1953 { 1954 static u_int8_t pcic_iowidth[3] = { 1955 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 1956 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 1957 PCIC_IOCTL_IO0_DATASIZE_8BIT, 1958 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 1959 PCIC_IOCTL_IO0_DATASIZE_16BIT, 1960 }; 1961 1962 #define PCIC_SIA_START_LOW 0 1963 #define PCIC_SIA_START_HIGH 1 1964 #define PCIC_SIA_STOP_LOW 2 1965 #define PCIC_SIA_STOP_HIGH 3 1966 1967 int regbase_win = 0x8 + win * 0x04; 1968 u_int8_t ioctl, enable; 1969 1970 DPRINTF( 1971 ("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx width %d\n", 1972 win, (long)ph->io[win].addr, (long)ph->io[win].size, 1973 ph->io[win].width * 8)); 1974 1975 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 1976 ph->io[win].addr & 0xff); 1977 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 1978 (ph->io[win].addr >> 8) & 0xff); 1979 1980 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 1981 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 1982 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 1983 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 1984 1985 ioctl = Pcic_read(ph, PCIC_IOCTL); 1986 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 1987 switch (win) { 1988 case 0: 1989 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 1990 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 1991 PCIC_IOCTL_IO0_DATASIZE_MASK); 1992 ioctl |= pcic_iowidth[ph->io[win].width]; 1993 enable |= PCIC_ADDRWIN_ENABLE_IO0; 1994 break; 1995 case 1: 1996 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 1997 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 1998 PCIC_IOCTL_IO1_DATASIZE_MASK); 1999 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2000 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2001 break; 2002 } 2003 Pcic_write(ph, PCIC_IOCTL, ioctl); 2004 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2005 #if defined CBB_DEBUG 2006 { 2007 u_int8_t start_low = 2008 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2009 u_int8_t start_high = 2010 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2011 u_int8_t stop_low = 2012 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2013 u_int8_t stop_high = 2014 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2015 printf 2016 (" start %02x %02x, stop %02x %02x, ioctl %02x enable %02x\n", 2017 start_low, start_high, stop_low, stop_high, ioctl, enable); 2018 } 2019 #endif 2020 } 2021 2022 /* 2023 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2024 * 2025 * This function unmapss I/O region. No return value. 2026 */ 2027 STATIC void 2028 pccbb_pcmcia_io_unmap(pch, win) 2029 pcmcia_chipset_handle_t pch; 2030 int win; 2031 { 2032 struct pcic_handle *ph = (struct pcic_handle *)pch; 2033 int reg; 2034 2035 if (win >= PCIC_IO_WINS || win < 0) { 2036 panic("pccbb_pcmcia_io_unmap: window out of range"); 2037 } 2038 2039 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2040 switch (win) { 2041 case 0: 2042 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2043 break; 2044 case 1: 2045 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2046 break; 2047 } 2048 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2049 2050 ph->ioalloc &= ~(1 << win); 2051 } 2052 2053 /* 2054 * static void pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 2055 * 2056 * This function enables the card. All information is stored in 2057 * the first argument, pcmcia_chipset_handle_t. 2058 */ 2059 static void 2060 pccbb_pcmcia_wait_ready(ph) 2061 struct pcic_handle *ph; 2062 { 2063 int i; 2064 2065 DPRINTF(("pccbb_pcmcia_wait_ready: status 0x%02x\n", 2066 Pcic_read(ph, PCIC_IF_STATUS))); 2067 2068 for (i = 0; i < 10000; i++) { 2069 if (Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) { 2070 return; 2071 } 2072 delay(500); 2073 #ifdef CBB_DEBUG 2074 if ((i > 5000) && (i % 100 == 99)) 2075 printf("."); 2076 #endif 2077 } 2078 2079 #ifdef DIAGNOSTIC 2080 printf("pcic_wait_ready: ready never happened, status = %02x\n", 2081 Pcic_read(ph, PCIC_IF_STATUS)); 2082 #endif 2083 } 2084 2085 /* 2086 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2087 * 2088 * This function enables the card. All information is stored in 2089 * the first argument, pcmcia_chipset_handle_t. 2090 */ 2091 STATIC void 2092 pccbb_pcmcia_socket_enable(pch) 2093 pcmcia_chipset_handle_t pch; 2094 { 2095 struct pcic_handle *ph = (struct pcic_handle *)pch; 2096 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2097 int cardtype, win; 2098 u_int8_t power, intr; 2099 pcireg_t spsr; 2100 int voltage; 2101 #define PCIC_INTR_PCI PCIC_INTR_ENABLE 2102 2103 /* this bit is mostly stolen from pcic_attach_card */ 2104 2105 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2106 2107 /* get card Vcc info */ 2108 2109 spsr = 2110 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2111 CB_SOCKET_STAT); 2112 if (spsr & CB_SOCKET_STAT_5VCARD) { 2113 DPRINTF(("5V card\n")); 2114 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2115 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2116 DPRINTF(("3V card\n")); 2117 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2118 } else { 2119 printf("?V card, 0x%x\n", spsr); /* XXX */ 2120 return; 2121 } 2122 2123 /* assert reset bit */ 2124 intr = Pcic_read(ph, PCIC_INTR); 2125 intr &= ~(PCIC_INTR_RESET | PCIC_INTR_ENABLE | PCIC_INTR_CARDTYPE_MASK); 2126 Pcic_write(ph, PCIC_INTR, intr); 2127 2128 /* disable socket i/o: negate output enable bit */ 2129 2130 power = Pcic_read(ph, PCIC_PWRCTL); 2131 power &= ~PCIC_PWRCTL_OE; 2132 Pcic_write(ph, PCIC_PWRCTL, power); 2133 2134 /* power down the socket to reset it, clear the card reset pin */ 2135 2136 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2137 2138 /* 2139 * wait 200ms until power fails (Tpf). Then, wait 100ms since 2140 * we are changing Vcc (Toff). 2141 */ 2142 /* delay(300*1000); too much */ 2143 2144 /* power up the socket */ 2145 pccbb_power(sc, voltage); 2146 2147 /* 2148 * wait 100ms until power raise (Tpr) and 20ms to become 2149 * stable (Tsu(Vcc)). 2150 * 2151 * some machines require some more time to be settled 2152 * (another 200ms is added here). 2153 */ 2154 /* delay((100 + 20 + 200)*1000); too much */ 2155 2156 power = Pcic_read(ph, PCIC_PWRCTL); 2157 power |= PCIC_PWRCTL_OE; 2158 Pcic_write(ph, PCIC_PWRCTL, power); 2159 2160 /* 2161 * hold RESET at least 10us. 2162 */ 2163 delay(10); 2164 delay(2 * 1000); /* XXX: TI1130 requires it. */ 2165 delay(20 * 1000); /* XXX: TI1130 requires it. */ 2166 2167 /* clear the reset flag */ 2168 2169 intr |= PCIC_INTR_RESET; 2170 Pcic_write(ph, PCIC_INTR, intr); 2171 2172 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 2173 2174 delay(20000); 2175 2176 /* wait for the chip to finish initializing */ 2177 2178 pccbb_pcmcia_wait_ready(ph); 2179 2180 /* zero out the address windows */ 2181 2182 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2183 2184 /* set the card type */ 2185 2186 cardtype = pcmcia_card_gettype(ph->pcmcia); 2187 2188 intr |= PCIC_INTR_PCI; 2189 intr |= ((cardtype == PCMCIA_IFTYPE_IO) ? 2190 PCIC_INTR_CARDTYPE_IO : PCIC_INTR_CARDTYPE_MEM); 2191 Pcic_write(ph, PCIC_INTR, intr); 2192 2193 DPRINTF(("%s: pccbb_pcmcia_socket_enable %02x cardtype %s %02x\n", 2194 ph->ph_parent->dv_xname, ph->sock, 2195 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2196 2197 /* reinstall all the memory and io mappings */ 2198 2199 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2200 if (ph->memalloc & (1 << win)) { 2201 pccbb_pcmcia_do_mem_map(ph, win); 2202 } 2203 } 2204 2205 for (win = 0; win < PCIC_IO_WINS; ++win) { 2206 if (ph->ioalloc & (1 << win)) { 2207 pccbb_pcmcia_do_io_map(ph, win); 2208 } 2209 } 2210 } 2211 2212 /* 2213 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2214 * 2215 * This function disables the card. All information is stored in 2216 * the first argument, pcmcia_chipset_handle_t. 2217 */ 2218 STATIC void 2219 pccbb_pcmcia_socket_disable(pch) 2220 pcmcia_chipset_handle_t pch; 2221 { 2222 struct pcic_handle *ph = (struct pcic_handle *)pch; 2223 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2224 u_int8_t power, intr; 2225 2226 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2227 2228 /* reset signal asserting... */ 2229 2230 intr = Pcic_read(ph, PCIC_INTR); 2231 intr &= ~(PCIC_INTR_RESET | PCIC_INTR_ENABLE | PCIC_INTR_CARDTYPE_MASK); 2232 Pcic_write(ph, PCIC_INTR, intr); 2233 delay(2 * 1000); 2234 2235 /* power down the socket */ 2236 power = Pcic_read(ph, PCIC_PWRCTL); 2237 power &= ~PCIC_PWRCTL_OE; 2238 Pcic_write(ph, PCIC_PWRCTL, power); 2239 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2240 /* 2241 * wait 300ms until power fails (Tpf). 2242 */ 2243 delay(300 * 1000); 2244 } 2245 2246 /* 2247 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2248 * 2249 * This function detects whether a card is in the slot or not. 2250 * If a card is inserted, return 1. Otherwise, return 0. 2251 */ 2252 STATIC int 2253 pccbb_pcmcia_card_detect(pch) 2254 pcmcia_chipset_handle_t pch; 2255 { 2256 struct pcic_handle *ph = (struct pcic_handle *)pch; 2257 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2258 2259 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2260 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2261 } 2262 2263 #if 0 2264 STATIC int 2265 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2266 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2267 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2268 #endif 2269 /* 2270 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2271 * bus_size_t size, 2272 * struct pcmcia_mem_handle *pcmhp) 2273 * 2274 * This function only allocates memory region for pccard. This 2275 * function never maps the allcated region to pccard memory area. 2276 * 2277 * XXX: Why the argument of start address is not in? 2278 */ 2279 STATIC int 2280 pccbb_pcmcia_mem_alloc(pch, size, pcmhp) 2281 pcmcia_chipset_handle_t pch; 2282 bus_size_t size; 2283 struct pcmcia_mem_handle *pcmhp; 2284 { 2285 struct pcic_handle *ph = (struct pcic_handle *)pch; 2286 bus_space_handle_t memh; 2287 bus_addr_t addr; 2288 bus_size_t sizepg; 2289 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2290 #if rbus 2291 rbus_tag_t rb; 2292 #endif 2293 2294 /* out of sc->memh, allocate as many pages as necessary */ 2295 2296 /* convert size to PCIC pages */ 2297 /* 2298 * This is not enough; when the requested region is on the page 2299 * boundaries, this may calculate wrong result. 2300 */ 2301 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2302 #if 0 2303 if (sizepg > PCIC_MAX_MEM_PAGES) { 2304 return 1; 2305 } 2306 #endif 2307 2308 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2309 return 1; 2310 } 2311 2312 addr = 0; /* XXX gcc -Wuninitialized */ 2313 2314 #if rbus 2315 rb = sc->sc_rbus_memt; 2316 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2317 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2318 &addr, &memh)) { 2319 return 1; 2320 } 2321 #else 2322 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2323 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2324 0, /* boundary */ 2325 0, /* flags */ 2326 &addr, &memh)) { 2327 return 1; 2328 } 2329 #endif 2330 2331 DPRINTF( 2332 ("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, realsize 0x%lx\n", 2333 addr, size, sizepg * PCIC_MEM_PAGESIZE)); 2334 2335 pcmhp->memt = sc->sc_memt; 2336 pcmhp->memh = memh; 2337 pcmhp->addr = addr; 2338 pcmhp->size = size; 2339 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2340 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2341 pcmhp->mhandle = 0; 2342 /* No offset??? Funny. */ 2343 2344 return 0; 2345 } 2346 2347 /* 2348 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2349 * struct pcmcia_mem_handle *pcmhp) 2350 * 2351 * This function release the memory space allocated by the fuction 2352 * pccbb_pcmcia_mem_alloc(). 2353 */ 2354 STATIC void 2355 pccbb_pcmcia_mem_free(pch, pcmhp) 2356 pcmcia_chipset_handle_t pch; 2357 struct pcmcia_mem_handle *pcmhp; 2358 { 2359 #if rbus 2360 struct pcic_handle *ph = (struct pcic_handle *)pch; 2361 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2362 2363 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2364 #else 2365 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2366 #endif 2367 } 2368 2369 /* 2370 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2371 * 2372 * This function release the memory space allocated by the fuction 2373 * pccbb_pcmcia_mem_alloc(). 2374 */ 2375 STATIC void 2376 pccbb_pcmcia_do_mem_map(ph, win) 2377 struct pcic_handle *ph; 2378 int win; 2379 { 2380 int regbase_win; 2381 bus_addr_t phys_addr; 2382 bus_addr_t phys_end; 2383 2384 #define PCIC_SMM_START_LOW 0 2385 #define PCIC_SMM_START_HIGH 1 2386 #define PCIC_SMM_STOP_LOW 2 2387 #define PCIC_SMM_STOP_HIGH 3 2388 #define PCIC_CMA_LOW 4 2389 #define PCIC_CMA_HIGH 5 2390 2391 u_int8_t start_low, start_high = 0; 2392 u_int8_t stop_low, stop_high; 2393 u_int8_t off_low, off_high; 2394 u_int8_t mem_window; 2395 int reg; 2396 2397 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2398 int mem8 = 2399 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8; 2400 2401 regbase_win = 0x10 + win * 0x08; 2402 2403 phys_addr = ph->mem[win].addr; 2404 phys_end = phys_addr + ph->mem[win].size; 2405 2406 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2407 phys_addr, phys_end, ph->mem[win].offset)); 2408 2409 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2410 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2411 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2412 2413 /* bit 19:12 */ 2414 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2415 /* bit 23:20 and bit 7 on */ 2416 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2417 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2418 /* bit 31:24, for 32-bit address */ 2419 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2420 2421 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2422 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2423 2424 if (((struct pccbb_softc *)ph-> 2425 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2426 Pcic_write(ph, 0x40 + win, mem_window); 2427 } 2428 2429 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2430 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2431 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2432 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2433 2434 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2435 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2436 2437 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2438 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2439 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2440 | ((kind == PCMCIA_MEM_ATTR) ? 2441 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2442 2443 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2444 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2445 2446 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2447 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2448 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2449 2450 #if defined CBB_DEBUG 2451 { 2452 int r1, r2, r3, r4, r5, r6, r7 = 0; 2453 2454 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2455 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2456 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2457 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2458 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2459 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2460 if (((struct pccbb_softc *)(ph-> 2461 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2462 r7 = Pcic_read(ph, 0x40 + win); 2463 } 2464 2465 DPRINTF(("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2466 "%02x%02x", win, r1, r2, r3, r4, r5, r6)); 2467 if (((struct pccbb_softc *)(ph-> 2468 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2469 DPRINTF((" %02x", r7)); 2470 } 2471 DPRINTF(("\n")); 2472 } 2473 #endif 2474 } 2475 2476 /* 2477 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2478 * bus_addr_t card_addr, bus_size_t size, 2479 * struct pcmcia_mem_handle *pcmhp, 2480 * bus_addr_t *offsetp, int *windowp) 2481 * 2482 * This function maps memory space allocated by the fuction 2483 * pccbb_pcmcia_mem_alloc(). 2484 */ 2485 STATIC int 2486 pccbb_pcmcia_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 2487 pcmcia_chipset_handle_t pch; 2488 int kind; 2489 bus_addr_t card_addr; 2490 bus_size_t size; 2491 struct pcmcia_mem_handle *pcmhp; 2492 bus_addr_t *offsetp; 2493 int *windowp; 2494 { 2495 struct pcic_handle *ph = (struct pcic_handle *)pch; 2496 bus_addr_t busaddr; 2497 long card_offset; 2498 int win; 2499 2500 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2501 if ((ph->memalloc & (1 << win)) == 0) { 2502 ph->memalloc |= (1 << win); 2503 break; 2504 } 2505 } 2506 2507 if (win == PCIC_MEM_WINS) { 2508 return 1; 2509 } 2510 2511 *windowp = win; 2512 2513 /* XXX this is pretty gross */ 2514 2515 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2516 panic("pccbb_pcmcia_mem_map memt is bogus"); 2517 } 2518 2519 busaddr = pcmhp->addr; 2520 2521 /* 2522 * compute the address offset to the pcmcia address space for the 2523 * pcic. this is intentionally signed. The masks and shifts below 2524 * will cause TRT to happen in the pcic registers. Deal with making 2525 * sure the address is aligned, and return the alignment offset. 2526 */ 2527 2528 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2529 card_addr -= *offsetp; 2530 2531 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2532 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2533 (u_long) card_addr)); 2534 2535 /* 2536 * include the offset in the size, and decrement size by one, since 2537 * the hw wants start/stop 2538 */ 2539 size += *offsetp - 1; 2540 2541 card_offset = (((long)card_addr) - ((long)busaddr)); 2542 2543 ph->mem[win].addr = busaddr; 2544 ph->mem[win].size = size; 2545 ph->mem[win].offset = card_offset; 2546 ph->mem[win].kind = kind; 2547 2548 pccbb_pcmcia_do_mem_map(ph, win); 2549 2550 return 0; 2551 } 2552 2553 /* 2554 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2555 * int window) 2556 * 2557 * This function unmaps memory space which mapped by the fuction 2558 * pccbb_pcmcia_mem_map(). 2559 */ 2560 STATIC void 2561 pccbb_pcmcia_mem_unmap(pch, window) 2562 pcmcia_chipset_handle_t pch; 2563 int window; 2564 { 2565 struct pcic_handle *ph = (struct pcic_handle *)pch; 2566 int reg; 2567 2568 if (window >= PCIC_MEM_WINS) { 2569 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2570 } 2571 2572 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2573 reg &= ~(1 << window); 2574 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2575 2576 ph->memalloc &= ~(1 << window); 2577 } 2578 2579 #if defined PCCBB_PCMCIA_POLL 2580 struct pccbb_poll_str { 2581 void *arg; 2582 int (*func) __P((void *)); 2583 int level; 2584 struct pcic_handle *ph; 2585 int count; 2586 int num; 2587 }; 2588 2589 static struct pccbb_poll_str pccbb_poll[10]; 2590 static int pccbb_poll_n = 0; 2591 2592 static void pccbb_pcmcia_poll __P((void *arg)); 2593 2594 static void 2595 pccbb_pcmcia_poll(arg) 2596 void *arg; 2597 { 2598 struct pccbb_poll_str *poll = arg; 2599 struct pcic_handle *ph = poll->ph; 2600 struct pccbb_softc *sc = ph->sc; 2601 int s; 2602 u_int32_t spsr; /* socket present-state reg */ 2603 2604 timeout(pccbb_pcmcia_poll, arg, hz * 2); 2605 switch (poll->level) { 2606 case IPL_NET: 2607 s = splnet(); 2608 break; 2609 case IPL_BIO: 2610 s = splbio(); 2611 break; 2612 case IPL_TTY: /* fallthrough */ 2613 default: 2614 s = spltty(); 2615 break; 2616 } 2617 2618 spsr = 2619 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2620 CB_SOCKET_STAT); 2621 2622 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2623 if (!(spsr & 0x40)) /* CINT low */ 2624 #else 2625 if (1) 2626 #endif 2627 { 2628 if ((*poll->func) (poll->arg) > 0) { 2629 ++poll->count; 2630 // printf("intr: reported from poller, 0x%x\n", spsr); 2631 #if defined LEVEL2 2632 } else { 2633 printf("intr: miss! 0x%x\n", spsr); 2634 #endif 2635 } 2636 } 2637 splx(s); 2638 } 2639 #endif /* defined CB_PCMCIA_POLL */ 2640 2641 /* 2642 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2643 * struct pcmcia_function *pf, 2644 * int ipl, 2645 * int (*func)(void *), 2646 * void *arg); 2647 * 2648 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2649 */ 2650 STATIC void * 2651 pccbb_pcmcia_intr_establish(pch, pf, ipl, func, arg) 2652 pcmcia_chipset_handle_t pch; 2653 struct pcmcia_function *pf; 2654 int ipl; 2655 int (*func) __P((void *)); 2656 void *arg; 2657 { 2658 struct pcic_handle *ph = (struct pcic_handle *)pch; 2659 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2660 pci_intr_handle_t handle; 2661 void *ih; 2662 2663 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2664 /* what should I do? */ 2665 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2666 DPRINTF( 2667 ("%s does not provide edge nor pulse interrupt\n", 2668 sc->sc_dev.dv_xname)); 2669 return NULL; 2670 } 2671 /* 2672 * XXX Noooooo! The interrupt flag must set properly!! 2673 * dumb pcmcia driver!! 2674 */ 2675 } 2676 2677 if (pci_intr_map(sc->sc_pc, sc->sc_intrtag, sc->sc_intrpin, 2678 sc->sc_intrline, &handle)) { 2679 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 2680 return NULL; 2681 } 2682 DPRINTF(("pccbb_pcmcia_intr_establish: line %d, handle %d\n", 2683 sc->sc_intrline, handle)); 2684 2685 if (NULL != (ih = 2686 pci_intr_establish(sc->sc_pc, handle, ipl, func, arg))) { 2687 u_int32_t cbctrl; 2688 2689 if ((CB_TI113X == sc->sc_chipset)) { 2690 cbctrl = 2691 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 2692 /* PCI functional intr req */ 2693 cbctrl |= PCI113X_CBCTRL_PCI_INTR; 2694 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, 2695 cbctrl); 2696 } 2697 } 2698 #if defined PCCBB_PCMCIA_POLL 2699 if (pccbb_poll_n < 10) { 2700 pccbb_poll[pccbb_poll_n].arg = arg; 2701 pccbb_poll[pccbb_poll_n].func = func; 2702 pccbb_poll[pccbb_poll_n].level = ipl; 2703 pccbb_poll[pccbb_poll_n].count = 0; 2704 pccbb_poll[pccbb_poll_n].num = pccbb_poll_n; 2705 pccbb_poll[pccbb_poll_n].ph = ph; 2706 timeout(pccbb_pcmcia_poll, &pccbb_poll[pccbb_poll_n++], hz * 2); 2707 printf("polling set\n"); 2708 } 2709 #endif 2710 #if defined SHOW_REGS 2711 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, sc->sc_base_memh); 2712 #endif 2713 2714 return ih; 2715 } 2716 2717 /* 2718 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2719 * void *ih) 2720 * 2721 * This function disables PC-Card interrupt. 2722 */ 2723 STATIC void 2724 pccbb_pcmcia_intr_disestablish(pch, ih) 2725 pcmcia_chipset_handle_t pch; 2726 void *ih; 2727 { 2728 struct pcic_handle *ph = (struct pcic_handle *)pch; 2729 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2730 2731 pci_intr_disestablish(sc->sc_pc, ih); 2732 } 2733 2734 #if rbus 2735 /* 2736 * static int 2737 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2738 * bus_addr_t addr, bus_size_t size, 2739 * bus_addr_t mask, bus_size_t align, 2740 * int flags, bus_addr_t *addrp; 2741 * bus_space_handle_t *bshp) 2742 * 2743 * This function allocates a portion of memory or io space for 2744 * clients. This function is called from CardBus card drivers. 2745 */ 2746 static int 2747 pccbb_rbus_cb_space_alloc(ct, rb, addr, size, mask, align, flags, addrp, bshp) 2748 cardbus_chipset_tag_t ct; 2749 rbus_tag_t rb; 2750 bus_addr_t addr; 2751 bus_size_t size; 2752 bus_addr_t mask; 2753 bus_size_t align; 2754 int flags; 2755 bus_addr_t *addrp; 2756 bus_space_handle_t *bshp; 2757 { 2758 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2759 2760 DPRINTF( 2761 ("pccbb_rbus_cb_space_alloc: adr %lx, size %lx, mask %lx, align %lx\n", 2762 addr, size, mask, align)); 2763 2764 if (align == 0) { 2765 align = size; 2766 } 2767 2768 if (rb->rb_bt == sc->sc_memt) { 2769 if (align < 16) { 2770 return 1; 2771 } 2772 } else if (rb->rb_bt == sc->sc_iot) { 2773 if (align < 4) { 2774 return 1; 2775 } 2776 } else { 2777 DPRINTF( 2778 ("pccbb_rbus_cb_space_alloc: Bus space tag %x is NOT used.\n", 2779 rb->rb_bt)); 2780 return 1; 2781 /* XXX: panic here? */ 2782 } 2783 2784 /* XXX: hack for avoiding ISA image */ 2785 if (mask < 0x3ff) { 2786 mask = 0x3ff; 2787 addr = 0x300; 2788 } 2789 2790 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 2791 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 2792 return 1; 2793 } 2794 2795 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 2796 2797 return 0; 2798 } 2799 2800 /* 2801 * static int 2802 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 2803 * bus_space_handle_t *bshp, bus_size_t size); 2804 * 2805 * This function is called from CardBus card drivers. 2806 */ 2807 static int 2808 pccbb_rbus_cb_space_free(ct, rb, bsh, size) 2809 cardbus_chipset_tag_t ct; 2810 rbus_tag_t rb; 2811 bus_space_handle_t bsh; 2812 bus_size_t size; 2813 { 2814 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2815 bus_space_tag_t bt = rb->rb_bt; 2816 2817 pccbb_close_win(sc, bt, bsh, size); 2818 2819 if (bt == sc->sc_memt) { 2820 } else if (bt == sc->sc_iot) { 2821 } else { 2822 return 1; 2823 /* XXX: panic here? */ 2824 } 2825 2826 return rbus_space_free(rb, bsh, size, NULL); 2827 } 2828 #endif /* rbus */ 2829 2830 #if rbus 2831 2832 static int 2833 pccbb_open_win(sc, bst, addr, size, bsh, flags) 2834 struct pccbb_softc *sc; 2835 bus_space_tag_t bst; 2836 bus_addr_t addr; 2837 bus_size_t size; 2838 bus_space_handle_t bsh; 2839 int flags; 2840 { 2841 struct pccbb_win_chain **top; 2842 bus_addr_t align; 2843 2844 top = &sc->sc_iowindow; 2845 align = 0x04; 2846 if (sc->sc_memt == bst) { 2847 top = &sc->sc_memwindow; 2848 align = 0x1000; 2849 DPRINTF(("using memory window, %x %x %x\n\n", 2850 sc->sc_iot, sc->sc_memt, bst)); 2851 } 2852 2853 if (pccbb_winlist_insert(top, addr, size, bsh, flags)) { 2854 printf("winlist insert fails:\n"); 2855 } 2856 pccbb_winset(align, sc, bst); 2857 2858 return 0; 2859 } 2860 2861 static int 2862 pccbb_close_win(sc, bst, bsh, size) 2863 struct pccbb_softc *sc; 2864 bus_space_tag_t bst; 2865 bus_space_handle_t bsh; 2866 bus_size_t size; 2867 { 2868 struct pccbb_win_chain **top; 2869 bus_addr_t align; 2870 2871 top = &sc->sc_iowindow; 2872 align = 0x04; 2873 if (sc->sc_memt == bst) { 2874 top = &sc->sc_memwindow; 2875 align = 0x1000; 2876 } 2877 2878 if (pccbb_winlist_delete(top, bsh, size)) { 2879 printf("winlist delete fails:\n"); 2880 } 2881 pccbb_winset(align, sc, bst); 2882 2883 return 0; 2884 } 2885 2886 static int 2887 pccbb_winlist_insert(top, start, size, bsh, flags) 2888 struct pccbb_win_chain **top; 2889 bus_addr_t start; 2890 bus_size_t size; 2891 bus_space_handle_t bsh; 2892 int flags; 2893 { 2894 struct pccbb_win_chain *chainp = *top; 2895 struct pccbb_win_chain *before = *top; 2896 struct pccbb_win_chain *elem; 2897 2898 if (*top == NULL) { 2899 if (NULL == (elem = 2900 (struct pccbb_win_chain *)malloc(sizeof(struct 2901 pccbb_win_chain), M_DEVBUF, M_NOWAIT))) { 2902 return 1; /* fail */ 2903 } 2904 2905 elem->wc_start = start; 2906 elem->wc_end = start + size - 1; 2907 elem->wc_handle = bsh; 2908 elem->wc_flags = flags; 2909 2910 *top = elem; 2911 elem->wc_next = NULL; 2912 return 0; 2913 } 2914 2915 for (; chainp && chainp->wc_start <= start; chainp = chainp->wc_next) { 2916 before = chainp; 2917 } 2918 2919 if (chainp != NULL) { 2920 if (chainp->wc_start < start + size) { 2921 printf("fatal! 0x%lx 0x%lx\n", chainp->wc_start, 2922 start + size); 2923 return 1; 2924 } 2925 } 2926 if ((before != *top) && (before->wc_end >= start)) { 2927 printf("fatal!! 0x%lx 0x%lx\n", before->wc_end, start); 2928 return 1; 2929 } 2930 2931 if (NULL == (elem = 2932 (struct pccbb_win_chain *)malloc(sizeof(struct pccbb_win_chain), 2933 M_DEVBUF, M_NOWAIT))) { 2934 return 1; /* fail */ 2935 } 2936 2937 elem->wc_start = start; 2938 elem->wc_end = start + size - 1; 2939 elem->wc_handle = bsh; 2940 elem->wc_flags = flags; 2941 2942 elem->wc_next = chainp; 2943 if (chainp == *top) { 2944 *top = elem; 2945 } else { 2946 before->wc_next = elem; 2947 } 2948 return 0; 2949 } 2950 2951 static int 2952 pccbb_winlist_delete(top, bsh, size) 2953 struct pccbb_win_chain **top; 2954 bus_space_handle_t bsh; 2955 bus_size_t size; 2956 { 2957 struct pccbb_win_chain *chainp = *top; 2958 struct pccbb_win_chain **before = top; 2959 2960 for (; chainp && chainp->wc_handle != bsh; chainp = chainp->wc_next) { 2961 before = &chainp->wc_next; 2962 } 2963 2964 if (chainp == NULL) { 2965 return 1; /* fail: no candidate to remove */ 2966 } 2967 2968 if (chainp->wc_end - chainp->wc_start != size - 1) { 2969 printf("fatal!!! 0x%lx\n", chainp->wc_start); 2970 return 1; /* fail: no candidate to remove */ 2971 } 2972 2973 *before = chainp->wc_next; 2974 free(chainp, M_DEVBUF); 2975 2976 return 0; 2977 } 2978 2979 static void 2980 pccbb_winset(align, sc, bst) 2981 bus_addr_t align; 2982 struct pccbb_softc *sc; 2983 bus_space_tag_t bst; 2984 { 2985 pci_chipset_tag_t pc; 2986 pcitag_t tag; 2987 bus_addr_t mask = ~(align - 1); 2988 struct { 2989 cardbusreg_t win_start; 2990 cardbusreg_t win_limit; 2991 int win_flags; 2992 } win[2]; 2993 struct pccbb_win_chain *chainp; 2994 int offs; 2995 2996 win[0].win_start = 0xffffffff; 2997 win[0].win_limit = 0; 2998 win[1].win_start = 0xffffffff; 2999 win[1].win_limit = 0; 3000 3001 chainp = sc->sc_iowindow; 3002 offs = 0x2c; 3003 if (sc->sc_memt == bst) { 3004 chainp = sc->sc_memwindow; 3005 offs = 0x1c; 3006 } 3007 3008 if (chainp) { 3009 win[0].win_start = chainp->wc_start & mask; 3010 win[0].win_limit = chainp->wc_end & mask; 3011 win[0].win_flags = chainp->wc_flags; 3012 chainp = chainp->wc_next; 3013 } 3014 3015 for (; chainp; chainp = chainp->wc_next) { 3016 if (win[1].win_start == 0xffffffff) { 3017 /* window 1 is not used */ 3018 if ((win[0].win_flags == chainp->wc_flags) && 3019 (win[0].win_limit + align >= 3020 (chainp->wc_start & mask))) { 3021 /* concatinate */ 3022 win[0].win_limit = chainp->wc_end & mask; 3023 } else { 3024 /* make new window */ 3025 win[1].win_start = chainp->wc_start & mask; 3026 win[1].win_limit = chainp->wc_end & mask; 3027 win[1].win_flags = chainp->wc_flags; 3028 } 3029 continue; 3030 } 3031 3032 /* Both windows are engagad. */ 3033 if (win[0].win_flags == win[1].win_flags) { 3034 /* same flags */ 3035 if (win[0].win_flags == chainp->wc_flags) { 3036 if (win[1].win_start - (win[0].win_limit + 3037 align) < 3038 (chainp->wc_start & mask) - 3039 ((chainp->wc_end & mask) + align)) { 3040 /* 3041 * merge window 0 and 1, and set win1 3042 * to chainp 3043 */ 3044 win[0].win_limit = win[1].win_limit; 3045 win[1].win_start = 3046 chainp->wc_start & mask; 3047 win[1].win_limit = 3048 chainp->wc_end & mask; 3049 } else { 3050 win[1].win_limit = 3051 chainp->wc_end & mask; 3052 } 3053 } else { 3054 /* different flags */ 3055 3056 /* concatinate win0 and win1 */ 3057 win[0].win_limit = win[1].win_limit; 3058 /* allocate win[1] to new space */ 3059 win[1].win_start = chainp->wc_start & mask; 3060 win[1].win_limit = chainp->wc_end & mask; 3061 win[1].win_flags = chainp->wc_flags; 3062 } 3063 } else { 3064 /* the flags of win[0] and win[1] is different */ 3065 if (win[0].win_flags == chainp->wc_flags) { 3066 win[0].win_limit = chainp->wc_end & mask; 3067 /* 3068 * XXX this creates overlapping windows, so 3069 * what should the poor bridge do if one is 3070 * cachable, and the other is not? 3071 */ 3072 printf("%s: overlapping windows\n", 3073 sc->sc_dev.dv_xname); 3074 } else { 3075 win[1].win_limit = chainp->wc_end & mask; 3076 } 3077 } 3078 } 3079 3080 pc = sc->sc_pc; 3081 tag = sc->sc_tag; 3082 pci_conf_write(pc, tag, offs, win[0].win_start); 3083 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3084 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3085 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3086 DPRINTF(("--pccbb_winset: win0 [%x, %lx), win1 [%x, %lx)\n", 3087 pci_conf_read(pc, tag, offs), 3088 pci_conf_read(pc, tag, offs + 4) + align, 3089 pci_conf_read(pc, tag, offs + 8), 3090 pci_conf_read(pc, tag, offs + 12) + align)); 3091 3092 if (bst == sc->sc_memt) { 3093 if (win[0].win_flags & PCCBB_MEM_CACHABLE) { 3094 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3095 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3096 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3097 } 3098 if (win[1].win_flags & PCCBB_MEM_CACHABLE) { 3099 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3100 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3101 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3102 } 3103 } 3104 } 3105 3106 #endif /* rbus */ 3107
Indexes created Fri Sep 26 08:10:20 GMT 2025