pccbb.c revision 1.23
1 /* $NetBSD: pccbb.c,v 1.23 2000/02/06 08:14:13 cgd Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 #define CBB_DEBUG 35 #define SHOW_REGS 36 #define PCCBB_PCMCIA_POLL 37 */ 38 /* #define CBB_DEBUG */ 39 40 /* 41 #define CB_PCMCIA_POLL 42 #define CB_PCMCIA_POLL_ONLY 43 #define LEVEL2 44 */ 45 46 #include <sys/types.h> 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/kernel.h> 50 #include <sys/errno.h> 51 #include <sys/ioctl.h> 52 #include <sys/syslog.h> 53 #include <sys/device.h> 54 #include <sys/malloc.h> 55 56 #include <machine/intr.h> 57 #include <machine/bus.h> 58 59 #include <dev/pci/pcivar.h> 60 #include <dev/pci/pcireg.h> 61 #include <dev/pci/pcidevs.h> 62 63 #include <dev/pci/pccbbreg.h> 64 65 #include <dev/cardbus/cardslotvar.h> 66 67 #include <dev/cardbus/cardbusvar.h> 68 69 #include <dev/pcmcia/pcmciareg.h> 70 #include <dev/pcmcia/pcmciavar.h> 71 72 #include <dev/ic/i82365reg.h> 73 #include <dev/ic/i82365var.h> 74 #include <dev/pci/pccbbvar.h> 75 76 #include "locators.h" 77 78 #ifndef __NetBSD_Version__ 79 struct cfdriver cbb_cd = { 80 NULL, "cbb", DV_DULL 81 }; 82 #endif 83 84 #if defined CBB_DEBUG 85 #define DPRINTF(x) printf x 86 #define STATIC 87 #else 88 #define DPRINTF(x) 89 #define STATIC static 90 #endif 91 92 #ifdef __BROKEN_INDIRECT_CONFIG 93 int pcicbbmatch __P((struct device *, void *, void *)); 94 #else 95 int pcicbbmatch __P((struct device *, struct cfdata *, void *)); 96 #endif 97 void pccbbattach __P((struct device *, struct device *, void *)); 98 int pccbbintr __P((void *)); 99 static void pci113x_insert __P((void *)); 100 static int pccbbintr_function __P((struct pccbb_softc *)); 101 102 static int pccbb_detect_card __P((struct pccbb_softc *)); 103 104 static void pccbb_pcmcia_write __P((struct pcic_handle *, int, u_int8_t)); 105 static u_int8_t pccbb_pcmcia_read __P((struct pcic_handle *, int)); 106 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 107 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 108 109 STATIC int cb_reset __P((struct pccbb_softc *)); 110 STATIC int cb_detect_voltage __P((struct pccbb_softc *)); 111 STATIC int cbbprint __P((void *, const char *)); 112 113 static int cb_chipset __P((u_int32_t, int *)); 114 STATIC void pccbb_pcmcia_attach_setup __P((struct pccbb_softc *, 115 struct pcmciabus_attach_args *)); 116 #if 0 117 STATIC void pccbb_pcmcia_attach_card __P((struct pcic_handle *)); 118 STATIC void pccbb_pcmcia_detach_card __P((struct pcic_handle *, int)); 119 STATIC void pccbb_pcmcia_deactivate_card __P((struct pcic_handle *)); 120 #endif 121 122 STATIC int pccbb_ctrl __P((cardbus_chipset_tag_t, int)); 123 STATIC int pccbb_power __P((cardbus_chipset_tag_t, int)); 124 STATIC int pccbb_cardenable __P((struct pccbb_softc * sc, int function)); 125 #if !rbus 126 static int pccbb_io_open __P((cardbus_chipset_tag_t, int, u_int32_t, 127 u_int32_t)); 128 static int pccbb_io_close __P((cardbus_chipset_tag_t, int)); 129 static int pccbb_mem_open __P((cardbus_chipset_tag_t, int, u_int32_t, 130 u_int32_t)); 131 static int pccbb_mem_close __P((cardbus_chipset_tag_t, int)); 132 #endif /* !rbus */ 133 static void *pccbb_intr_establish __P((cardbus_chipset_tag_t, int irq, 134 int level, int (*ih) (void *), void *sc)); 135 static void pccbb_intr_disestablish __P((cardbus_chipset_tag_t ct, void *ih)); 136 137 static cardbustag_t pccbb_make_tag __P((cardbus_chipset_tag_t, int, int, int)); 138 static void pccbb_free_tag __P((cardbus_chipset_tag_t, cardbustag_t)); 139 static cardbusreg_t pccbb_conf_read __P((cardbus_chipset_tag_t, cardbustag_t, 140 int)); 141 static void pccbb_conf_write __P((cardbus_chipset_tag_t, cardbustag_t, int, 142 cardbusreg_t)); 143 static void pccbb_chipinit __P((struct pccbb_softc *)); 144 145 STATIC int pccbb_pcmcia_mem_alloc __P((pcmcia_chipset_handle_t, bus_size_t, 146 struct pcmcia_mem_handle *)); 147 STATIC void pccbb_pcmcia_mem_free __P((pcmcia_chipset_handle_t, 148 struct pcmcia_mem_handle *)); 149 STATIC int pccbb_pcmcia_mem_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 150 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *)); 151 STATIC void pccbb_pcmcia_mem_unmap __P((pcmcia_chipset_handle_t, int)); 152 STATIC int pccbb_pcmcia_io_alloc __P((pcmcia_chipset_handle_t, bus_addr_t, 153 bus_size_t, bus_size_t, struct pcmcia_io_handle *)); 154 STATIC void pccbb_pcmcia_io_free __P((pcmcia_chipset_handle_t, 155 struct pcmcia_io_handle *)); 156 STATIC int pccbb_pcmcia_io_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 157 bus_size_t, struct pcmcia_io_handle *, int *)); 158 STATIC void pccbb_pcmcia_io_unmap __P((pcmcia_chipset_handle_t, int)); 159 STATIC void *pccbb_pcmcia_intr_establish __P((pcmcia_chipset_handle_t, 160 struct pcmcia_function *, int, int (*)(void *), void *)); 161 STATIC void pccbb_pcmcia_intr_disestablish __P((pcmcia_chipset_handle_t, 162 void *)); 163 STATIC void pccbb_pcmcia_socket_enable __P((pcmcia_chipset_handle_t)); 164 STATIC void pccbb_pcmcia_socket_disable __P((pcmcia_chipset_handle_t)); 165 STATIC int pccbb_pcmcia_card_detect __P((pcmcia_chipset_handle_t pch)); 166 167 static void pccbb_pcmcia_do_io_map __P((struct pcic_handle *, int)); 168 static void pccbb_pcmcia_wait_ready __P((struct pcic_handle *)); 169 static void pccbb_pcmcia_do_mem_map __P((struct pcic_handle *, int)); 170 171 /* bus-space allocation and disallocation functions */ 172 #if rbus 173 174 static int pccbb_rbus_cb_space_alloc __P((cardbus_chipset_tag_t, rbus_tag_t, 175 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 176 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp)); 177 static int pccbb_rbus_cb_space_free __P((cardbus_chipset_tag_t, rbus_tag_t, 178 bus_space_handle_t, bus_size_t)); 179 180 #endif /* rbus */ 181 182 #if rbus 183 184 static int pccbb_open_win __P((struct pccbb_softc *, bus_space_tag_t, 185 bus_addr_t, bus_size_t, bus_space_handle_t, int flags)); 186 static int pccbb_close_win __P((struct pccbb_softc *, bus_space_tag_t, 187 bus_space_handle_t, bus_size_t)); 188 static int pccbb_winlist_insert __P((struct pccbb_win_chain **, bus_addr_t, 189 bus_size_t, bus_space_handle_t, int)); 190 static int pccbb_winlist_delete __P((struct pccbb_win_chain **, 191 bus_space_handle_t, bus_size_t)); 192 static void pccbb_winset __P((bus_addr_t align, struct pccbb_softc *, 193 bus_space_tag_t)); 194 void pccbb_winlist_show(struct pccbb_win_chain *); 195 196 #endif /* rbus */ 197 198 /* for config_defer */ 199 static void pccbb_pci_callback __P((struct device *)); 200 201 #if defined SHOW_REGS 202 static void cb_show_regs __P((pci_chipset_tag_t pc, pcitag_t tag, 203 bus_space_tag_t memt, bus_space_handle_t memh)); 204 #endif 205 206 struct cfattach cbb_pci_ca = { 207 sizeof(struct pccbb_softc), pcicbbmatch, pccbbattach 208 }; 209 210 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 211 pccbb_pcmcia_mem_alloc, 212 pccbb_pcmcia_mem_free, 213 pccbb_pcmcia_mem_map, 214 pccbb_pcmcia_mem_unmap, 215 pccbb_pcmcia_io_alloc, 216 pccbb_pcmcia_io_free, 217 pccbb_pcmcia_io_map, 218 pccbb_pcmcia_io_unmap, 219 pccbb_pcmcia_intr_establish, 220 pccbb_pcmcia_intr_disestablish, 221 pccbb_pcmcia_socket_enable, 222 pccbb_pcmcia_socket_disable, 223 pccbb_pcmcia_card_detect 224 }; 225 226 #if rbus 227 static struct cardbus_functions pccbb_funcs = { 228 pccbb_rbus_cb_space_alloc, 229 pccbb_rbus_cb_space_free, 230 pccbb_intr_establish, 231 pccbb_intr_disestablish, 232 pccbb_ctrl, 233 pccbb_power, 234 pccbb_make_tag, 235 pccbb_free_tag, 236 pccbb_conf_read, 237 pccbb_conf_write, 238 }; 239 #else 240 static struct cardbus_functions pccbb_funcs = { 241 pccbb_ctrl, 242 pccbb_power, 243 pccbb_mem_open, 244 pccbb_mem_close, 245 pccbb_io_open, 246 pccbb_io_close, 247 pccbb_intr_establish, 248 pccbb_intr_disestablish, 249 pccbb_make_tag, 250 pccbb_conf_read, 251 pccbb_conf_write, 252 }; 253 #endif 254 255 int 256 pcicbbmatch(parent, match, aux) 257 struct device *parent; 258 #ifdef __BROKEN_INDIRECT_CONFIG 259 void *match; 260 #else 261 struct cfdata *match; 262 #endif 263 void *aux; 264 { 265 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 266 267 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 268 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 269 PCI_INTERFACE(pa->pa_class) == 0) { 270 return 1; 271 } 272 273 return 0; 274 } 275 276 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 277 | ((prod) << PCI_PRODUCT_SHIFT)) 278 279 struct yenta_chipinfo { 280 pcireg_t yc_id; /* vendor tag | product tag */ 281 int yc_chiptype; 282 int yc_flags; 283 } yc_chipsets[] = { 284 /* Texas Instruments chips */ 285 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 286 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 287 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 288 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 289 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI12XX, 290 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 291 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 292 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 293 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 294 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 295 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 296 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 297 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI12XX, 298 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 299 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI12XX, 300 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 301 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 302 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 303 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 304 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 305 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI12XX, 306 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 307 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 308 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 309 310 /* Ricoh chips */ 311 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 312 PCCBB_PCMCIA_MEM_32}, 313 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 314 PCCBB_PCMCIA_MEM_32}, 315 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 316 PCCBB_PCMCIA_MEM_32}, 317 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 318 PCCBB_PCMCIA_MEM_32}, 319 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 320 PCCBB_PCMCIA_MEM_32}, 321 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 322 PCCBB_PCMCIA_MEM_32}, 323 324 /* Toshiba products */ 325 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 326 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 327 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 328 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 329 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 330 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 331 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 332 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 333 334 /* Cirrus Logic products */ 335 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 336 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 337 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 338 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 339 340 /* sentinel, or Generic chip */ 341 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 342 }; 343 344 static int 345 cb_chipset(pci_id, flagp) 346 u_int32_t pci_id; 347 int *flagp; 348 { 349 int loopend = sizeof(yc_chipsets) / sizeof(yc_chipsets[0]); 350 struct yenta_chipinfo *ycp, *ycend; 351 352 ycend = yc_chipsets + loopend; 353 354 for (ycp = yc_chipsets; ycp < ycend && pci_id != ycp->yc_id; ++ycp); 355 356 if (ycp == ycend) { 357 /* not found -- point at sentinel */ 358 ycp = yc_chipsets + loopend - 1; 359 } 360 361 if (flagp != NULL) { 362 *flagp = ycp->yc_flags; 363 } 364 365 return ycp->yc_chiptype; 366 } 367 368 static void 369 pccbb_shutdown(void *arg) 370 { 371 struct pccbb_softc *sc = arg; 372 pcireg_t command; 373 374 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 375 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 376 0); 377 378 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 379 380 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 381 PCI_COMMAND_MASTER_ENABLE); 382 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 383 384 } 385 386 void 387 pccbbattach(parent, self, aux) 388 struct device *parent; 389 struct device *self; 390 void *aux; 391 { 392 struct pccbb_softc *sc = (void *)self; 393 struct pci_attach_args *pa = aux; 394 pci_chipset_tag_t pc = pa->pa_pc; 395 pcireg_t sock_base, busreg; 396 bus_addr_t sockbase; 397 char devinfo[256]; 398 int flags; 399 400 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 401 402 pci_devinfo(pa->pa_id, 0, 0, devinfo); 403 printf(": %s (rev. 0x%02x)", devinfo, PCI_REVISION(pa->pa_class)); 404 #ifdef CBB_DEBUG 405 printf(" (chipflags %x)", flags); 406 #endif 407 printf("\n"); 408 409 #if rbus 410 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 411 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 412 #endif /* rbus */ 413 414 sc->sc_base_memh = 0; 415 416 /* 417 * MAP socket registers and ExCA registers on memory-space 418 * When no valid address is set on socket base registers (on pci 419 * config space), get it not polite way. 420 */ 421 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 422 423 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 424 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 425 /* The address must be valid. */ 426 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 427 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL)) { 428 printf("%s: can't map socket base address 0x%x\n", 429 sc->sc_dev.dv_xname, sock_base); 430 /* 431 * I think it's funny: socket base registers must be 432 * mapped on memory space, but ... 433 */ 434 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 435 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 436 NULL)) { 437 printf("%s: can't map socket base address" 438 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 439 sockbase); 440 /* give up... allocate reg space via rbus. */ 441 sc->sc_base_memh = 0; 442 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 443 } 444 } else { 445 DPRINTF(("%s: socket base address 0x%lx\n", 446 sc->sc_dev.dv_xname, sockbase)); 447 } 448 } 449 450 sc->sc_mem_start = 0; /* XXX */ 451 sc->sc_mem_end = 0xffffffff; /* XXX */ 452 453 /* 454 * When interrupt isn't routed correctly, give up probing cbb and do 455 * not kill pcic-compatible port. 456 */ 457 if ((0 == pa->pa_intrline) || (255 == pa->pa_intrline)) { 458 printf("%s: NOT USED because of unconfigured interrupt\n", 459 sc->sc_dev.dv_xname); 460 return; 461 } 462 463 /* 464 * When bus number isn't set correctly, give up using 32-bit CardBus 465 * mode. 466 */ 467 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 468 #if notyet 469 if (((busreg >> 8) & 0xff) == 0) { 470 printf("%s: CardBus support disabled because of unconfigured bus number\n", 471 sc->sc_dev.dv_xname); 472 flags |= PCCBB_PCMCIA_16BITONLY; 473 } 474 #endif 475 476 /* pccbb_machdep.c end */ 477 478 #if defined CBB_DEBUG 479 { 480 static char *intrname[5] = { "NON", "A", "B", "C", "D" }; 481 printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname, 482 intrname[pa->pa_intrpin], pa->pa_intrline); 483 } 484 #endif 485 486 /* setup softc */ 487 sc->sc_pc = pc; 488 sc->sc_iot = pa->pa_iot; 489 sc->sc_memt = pa->pa_memt; 490 sc->sc_dmat = pa->pa_dmat; 491 sc->sc_tag = pa->pa_tag; 492 sc->sc_function = pa->pa_function; 493 494 sc->sc_intrline = pa->pa_intrline; 495 sc->sc_intrtag = pa->pa_intrtag; 496 sc->sc_intrpin = pa->pa_intrpin; 497 498 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 499 500 shutdownhook_establish(pccbb_shutdown, sc); 501 502 #if __NetBSD_Version__ > 103060000 503 config_defer(self, pccbb_pci_callback); 504 #else 505 pccbb_pci_callback(self); 506 #endif 507 } 508 509 static void 510 pccbb_pci_callback(self) 511 struct device *self; 512 { 513 struct pccbb_softc *sc = (void *)self; 514 pci_chipset_tag_t pc = sc->sc_pc; 515 bus_space_tag_t base_memt; 516 bus_space_handle_t base_memh; 517 u_int32_t maskreg; 518 pci_intr_handle_t ih; 519 const char *intrstr = NULL; 520 bus_addr_t sockbase; 521 struct cbslot_attach_args cba; 522 struct pcmciabus_attach_args paa; 523 struct cardslot_attach_args caa; 524 struct cardslot_softc *csc; 525 526 if (0 == sc->sc_base_memh) { 527 /* The socket registers aren't mapped correctly. */ 528 #if rbus 529 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 530 (sc->sc_chipset == CB_RX5C47X 531 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 532 0, &sockbase, &sc->sc_base_memh)) { 533 return; 534 } 535 sc->sc_base_memt = sc->sc_memt; 536 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 537 DPRINTF(("%s: CardBus resister address 0x%lx -> 0x%x\n", 538 sc->sc_dev.dv_xname, sockbase, pci_conf_read(pc, sc->sc_tag, 539 PCI_SOCKBASE))); 540 #else 541 sc->sc_base_memt = sc->sc_memt; 542 #if !defined CBB_PCI_BASE 543 #define CBB_PCI_BASE 0x20000000 544 #endif 545 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 546 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 547 /* cannot allocate memory space */ 548 return; 549 } 550 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 551 DPRINTF(("%s: CardBus resister address 0x%x -> 0x%x\n", 552 sc->sc_dev.dv_xname, sock_base, pci_conf_read(pc, 553 sc->sc_tag, PCI_SOCKBASE))); 554 #endif 555 } 556 557 /* bus bridge initialisation */ 558 pccbb_chipinit(sc); 559 560 base_memt = sc->sc_base_memt; /* socket regs memory tag */ 561 base_memh = sc->sc_base_memh; /* socket regs memory handle */ 562 563 /* CSC Interrupt: Card detect interrupt on */ 564 maskreg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 565 maskreg |= CB_SOCKET_MASK_CD; /* Card detect intr is turned on. */ 566 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, maskreg); 567 /* reset interrupt */ 568 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, 569 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT)); 570 571 /* Map and establish the interrupt. */ 572 if (pci_intr_map(pc, sc->sc_intrtag, sc->sc_intrpin, 573 sc->sc_intrline, &ih)) { 574 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 575 return; 576 } 577 intrstr = pci_intr_string(pc, ih); 578 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 579 580 if (sc->sc_ih == NULL) { 581 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 582 if (intrstr != NULL) { 583 printf(" at %s", intrstr); 584 } 585 printf("\n"); 586 return; 587 } 588 589 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 590 591 { 592 u_int32_t sockstat = 593 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 594 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 595 sc->sc_flags |= CBB_CARDEXIST; 596 } 597 } 598 599 /* 600 * attach cardbus 601 */ 602 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 603 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 604 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 605 606 /* initialise cbslot_attach */ 607 cba.cba_busname = "cardbus"; 608 cba.cba_iot = sc->sc_iot; 609 cba.cba_memt = sc->sc_memt; 610 cba.cba_dmat = sc->sc_dmat; 611 cba.cba_function = 0; 612 cba.cba_bus = (busreg >> 8) & 0x0ff; 613 cba.cba_cc = (void *)sc; 614 cba.cba_cf = &pccbb_funcs; 615 cba.cba_intrline = sc->sc_intrline; 616 617 #if rbus 618 cba.cba_rbus_iot = sc->sc_rbus_iot; 619 cba.cba_rbus_memt = sc->sc_rbus_memt; 620 #endif 621 622 cba.cba_cacheline = PCI_CACHELINE(bhlc); 623 cba.cba_lattimer = PCI_CB_LATENCY(busreg); 624 625 printf("%s: cacheline 0x%x lattimer 0x%x\n", 626 sc->sc_dev.dv_xname, cba.cba_cacheline, cba.cba_lattimer); 627 printf("%s: bhlc 0x%x lscp 0x%x\n", sc->sc_dev.dv_xname, bhlc, 628 busreg); 629 #if defined SHOW_REGS 630 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 631 sc->sc_base_memh); 632 #endif 633 } 634 635 pccbb_pcmcia_attach_setup(sc, &paa); 636 caa.caa_cb_attach = NULL; 637 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 638 caa.caa_cb_attach = &cba; 639 } 640 caa.caa_16_attach = &paa; 641 caa.caa_ph = &sc->sc_pcmcia_h; 642 643 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 644 DPRINTF(("pccbbattach: found cardslot\n")); 645 sc->sc_csc = csc; 646 } 647 648 return; 649 } 650 651 static void 652 pccbb_chipinit(sc) 653 struct pccbb_softc *sc; 654 { 655 pci_chipset_tag_t pc = sc->sc_pc; 656 pcitag_t tag = sc->sc_tag; 657 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 658 bus_space_handle_t base_memh = sc->sc_base_memh; 659 pcireg_t cbctrl; 660 661 /* 662 * Set PCI command reg. 663 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 664 */ 665 { 666 pcireg_t command = 667 pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 668 669 /* I believe it is harmless. */ 670 command |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 671 PCI_COMMAND_MASTER_ENABLE); 672 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, command); 673 } 674 675 /* 676 * Set CardBus latency timer 677 */ 678 { 679 pcireg_t pci_lscp = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 680 if (PCI_CB_LATENCY(pci_lscp) < 0x20) { 681 pci_lscp &= 682 ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 683 pci_lscp |= (0x20 << PCI_CB_LATENCY_SHIFT); 684 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, pci_lscp); 685 } 686 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 687 PCI_CB_LATENCY(pci_lscp), pci_conf_read(pc, tag, 688 PCI_CB_LSCP_REG))); 689 } 690 691 /* 692 * Set PCI latency timer 693 */ 694 { 695 pcireg_t pci_bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG); 696 if (PCI_LATTIMER(pci_bhlc) < 0x10) { 697 pci_bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 698 pci_bhlc |= (0x10 << PCI_LATTIMER_SHIFT); 699 pci_conf_write(pc, tag, PCI_BHLC_REG, pci_bhlc); 700 } 701 DPRINTF(("PCI latency timer 0x%x (%x)\n", 702 PCI_LATTIMER(pci_bhlc), pci_conf_read(pc, tag, 703 PCI_BHLC_REG))); 704 } 705 706 /* disable Legacy IO */ 707 708 switch (sc->sc_chipset) { 709 case CB_RX5C46X: /* fallthrogh */ 710 #if 0 711 case CB_RX5C47X: 712 #endif 713 /* 714 * The legacy pcic io-port on Ricoh CardBus bridges cannot be 715 * disabled by substituting 0 into PCI_LEGACY register. Ricoh 716 * CardBus bridges have special bits on Bridge control reg (addr 717 * 0x3e on PCI config space). 718 */ 719 { 720 pcireg_t bcri = pci_conf_read(pc, tag, PCI_BCR_INTR); 721 bcri &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 722 pci_conf_write(pc, tag, PCI_BCR_INTR, bcri); 723 } 724 break; 725 default: 726 /* XXX: I don't know proper way to kill Legacy IO properly. */ 727 pci_conf_write(pc, tag, PCI_LEGACY, 0x0); 728 break; 729 } 730 731 /* 732 * Interrupt routing: use PCI interrupt 733 */ 734 { 735 u_int32_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 736 bcr &= ~CB_BCR_INTR_IREQ_ENABLE; /* use PCI Intr */ 737 bcr |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 738 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 739 } 740 741 if (CB_TI113X == sc->sc_chipset) { 742 cbctrl = pci_conf_read(pc, tag, PCI_CBCTRL); 743 if (0 == sc->sc_function) { 744 cbctrl |= PCI113X_CBCTRL_PCI_IRQ_ENA; 745 } 746 /* XXX: bug in PCI113X */ 747 cbctrl |= PCI113X_CBCTRL_PCI_IRQ_ENA; 748 /* CSC intr enable */ 749 cbctrl |= PCI113X_CBCTRL_PCI_CSC; 750 /* functional intr prohibit */ 751 cbctrl &= ~PCI113X_CBCTRL_PCI_INTR; 752 /* prohibit ISA routing */ 753 cbctrl &= ~PCI113X_CBCTRL_INT_MASK; 754 pci_conf_write(pc, tag, PCI_CBCTRL, cbctrl); 755 756 /* 757 * set ExCA regs: PCI113X required to be set bit 4 at Interrupt 758 * and General Register, which is IRQ Enable Register, and 759 * clear bit 3:0 to zero in order to route CSC interrupt to 760 * PCI interrupt pin. 761 */ 762 bus_space_write_1(base_memt, base_memh, 0x0803, 0x10); 763 /* set ExCA regs: prohibit all pcmcia-style CSC intr. */ 764 bus_space_write_1(base_memt, base_memh, 0x0805, 0x00); 765 #if 1 766 DPRINTF(("ExCA regs:")); 767 DPRINTF((" 0x803: %02x", bus_space_read_1(base_memt, base_memh, 768 0x803))); 769 DPRINTF((" 0x805: %02x", bus_space_read_1(base_memt, base_memh, 770 0x805))); 771 DPRINTF((" 0x81e: %02x\n", bus_space_read_1(base_memt, 772 base_memh, 0x81e))); 773 #endif 774 } else if (sc->sc_chipset == CB_TI12XX) { 775 cbctrl = pci_conf_read(pc, tag, PCI_CBCTRL); 776 cbctrl &= ~PCI12XX_CBCTRL_INT_MASK; /* intr routing reset */ 777 pci_conf_write(pc, tag, PCI_CBCTRL, cbctrl); 778 /* 779 * set ExCA regs: PCI12XX required to be set bit 4 at Interrupt 780 * and General Register, which is IRQ Enable Register, and clear 781 * bit 3:0 to zero in order to route CSC interrupt to PCI 782 * interrupt pin. 783 */ 784 bus_space_write_1(base_memt, base_memh, 0x0803, 0x10); 785 /* set ExCA regs: prohibit all pcmcia-style CSC intr. */ 786 bus_space_write_1(base_memt, base_memh, 0x0805, 0x00); 787 } else if (sc->sc_chipset == CB_TOPIC95B) { 788 cardbusreg_t sock_ctrl, slot_ctrl; 789 790 sock_ctrl = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 791 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, 792 sock_ctrl | TOPIC_SOCKET_CTRL_SCR_IRQSEL); 793 794 slot_ctrl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 795 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 796 sc->sc_dev.dv_xname, slot_ctrl)); 797 slot_ctrl |= 798 (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 799 TOPIC_SLOT_CTRL_ID_LOCK); 800 slot_ctrl |= TOPIC_SLOT_CTRL_CARDBUS; 801 slot_ctrl &= ~TOPIC_SLOT_CTRL_SWDETECT; 802 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slot_ctrl); 803 DPRINTF(("0x%x\n", slot_ctrl)); 804 } 805 806 /* close all memory and io windows */ 807 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 808 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 809 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 810 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 811 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 812 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 813 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 814 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 815 816 return; 817 } 818 819 /* 820 * attach pccard bus 821 */ 822 STATIC void 823 pccbb_pcmcia_attach_setup(sc, paa) 824 struct pccbb_softc *sc; 825 struct pcmciabus_attach_args *paa; 826 { 827 struct pcic_handle *ph = &sc->sc_pcmcia_h; 828 #if rbus 829 rbus_tag_t rb; 830 #endif 831 832 /* initialise pcmcia part in pccbb_softc */ 833 ph->ph_parent = (struct device *)sc; 834 ph->sock = sc->sc_function; 835 ph->flags = 0; 836 ph->shutdown = 0; 837 ph->ih_irq = sc->sc_intrline; 838 ph->ph_bus_t = sc->sc_base_memt; 839 ph->ph_bus_h = sc->sc_base_memh; 840 ph->ph_read = pccbb_pcmcia_read; 841 ph->ph_write = pccbb_pcmcia_write; 842 sc->sc_pct = &pccbb_pcmcia_funcs; 843 844 Pcic_write(ph, PCIC_CSC_INTR, 0); 845 Pcic_read(ph, PCIC_CSC); 846 847 /* initialise pcmcia bus attachment */ 848 paa->paa_busname = "pcmcia"; 849 paa->pct = sc->sc_pct; 850 paa->pch = ph; 851 paa->iobase = 0; /* I don't use them */ 852 paa->iosize = 0; 853 #if rbus 854 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 855 paa->iobase = rb->rb_start + rb->rb_offset; 856 paa->iosize = rb->rb_end - rb->rb_start; 857 #endif 858 859 return; 860 } 861 862 #if 0 863 STATIC void 864 pccbb_pcmcia_attach_card(ph) 865 struct pcic_handle *ph; 866 { 867 if (ph->flags & PCIC_FLAG_CARDP) { 868 panic("pccbb_pcmcia_attach_card: already attached"); 869 } 870 871 /* call the MI attach function */ 872 pcmcia_card_attach(ph->pcmcia); 873 874 ph->flags |= PCIC_FLAG_CARDP; 875 } 876 877 STATIC void 878 pccbb_pcmcia_detach_card(ph, flags) 879 struct pcic_handle *ph; 880 int flags; 881 { 882 if (!(ph->flags & PCIC_FLAG_CARDP)) { 883 panic("pccbb_pcmcia_detach_card: already detached"); 884 } 885 886 ph->flags &= ~PCIC_FLAG_CARDP; 887 888 /* call the MI detach function */ 889 pcmcia_card_detach(ph->pcmcia, flags); 890 } 891 #endif 892 893 /* 894 * int pccbbintr(arg) 895 * void *arg; 896 * This routine handles the interrupt from Yenta PCI-CardBus bridge 897 * itself. 898 */ 899 int 900 pccbbintr(arg) 901 void *arg; 902 { 903 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 904 u_int32_t sockevent; 905 bus_space_tag_t memt = sc->sc_base_memt; 906 bus_space_handle_t memh = sc->sc_base_memh; 907 u_int32_t sockstate; 908 909 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 910 if (0 == sockevent) { 911 /* This intr is not for me: it may be for my child devices. */ 912 return pccbbintr_function(sc); 913 } else { 914 /* reset bit */ 915 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 916 } 917 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 918 919 if (sockevent & CB_SOCKET_EVENT_CD) { 920 if (CB_SOCKET_STAT_CD == (sockstate & CB_SOCKET_STAT_CD)) { 921 /* A card should be removed. */ 922 if (sc->sc_flags & CBB_CARDEXIST) { 923 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 924 sockevent)); 925 DPRINTF((" card removed, 0x%08x\n", sockstate)); 926 sc->sc_flags &= ~CBB_CARDEXIST; 927 if (sc-> 928 sc_csc->sc_status & CARDSLOT_STATUS_CARD_16) 929 { 930 #if 0 931 struct pcic_handle *ph = 932 &sc->sc_pcmcia_h; 933 934 pcmcia_card_deactivate(ph->pcmcia); 935 pccbb_pcmcia_socket_disable(ph); 936 pccbb_pcmcia_detach_card(ph, 937 DETACH_FORCE); 938 #endif 939 cardslot_event_throw(sc->sc_csc, 940 CARDSLOT_EVENT_REMOVAL_16); 941 } else if (sc-> 942 sc_csc->sc_status & CARDSLOT_STATUS_CARD_CB) 943 { 944 /* Cardbus intr removed */ 945 cardslot_event_throw(sc->sc_csc, 946 CARDSLOT_EVENT_REMOVAL_CB); 947 } 948 } 949 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD)) { 950 if (sc->sc_flags & CBB_INSERTING) { 951 untimeout(pci113x_insert, sc); 952 } 953 timeout(pci113x_insert, sc, hz / 10); 954 sc->sc_flags |= CBB_INSERTING; 955 } 956 } else { 957 DPRINTF(("%s: sockevent = %b\n", 958 sc->sc_dev.dv_xname, sockevent, PCCBB_SOCKEVENT_BITS)); 959 DPRINTF(("%s: sockstate = %b\n", 960 sc->sc_dev.dv_xname, sockstate, PCCBB_SOCKSTATE_BITS)); 961 } 962 963 return 1; 964 } 965 966 /* 967 * static int pccbbintr_function(struct pccbb_softc *sc) 968 * 969 * This function calls each interrupt handler registered at the 970 * bridge. The interrupt handlers are called in registerd order. 971 */ 972 static int 973 pccbbintr_function(sc) 974 struct pccbb_softc *sc; 975 { 976 int retval = 0, val; 977 struct pccbb_intrhand_list *pil; 978 979 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 980 val = (*pil->pil_func) (pil->pil_arg); 981 retval = retval == 1 ? 1 : 982 retval == 0 ? val : val != 0 ? val : retval; 983 } 984 985 return retval; 986 } 987 988 static void 989 pci113x_insert(arg) 990 void *arg; 991 { 992 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 993 u_int32_t sockevent, sockstate; 994 995 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 996 CB_SOCKET_EVENT); 997 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 998 CB_SOCKET_STAT); 999 1000 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1001 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1002 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1003 sc->sc_flags |= CBB_CARDEXIST; 1004 /* call pccard intterupt handler here */ 1005 if (sockstate & CB_SOCKET_STAT_16BIT) { 1006 /* 16-bit card found */ 1007 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1008 cardslot_event_throw(sc->sc_csc, 1009 CARDSLOT_EVENT_INSERTION_16); 1010 } else if (sockstate & CB_SOCKET_STAT_CB) { 1011 /* cardbus card fuond */ 1012 /* cardbus_attach_card(sc->sc_csc); */ 1013 cardslot_event_throw(sc->sc_csc, 1014 CARDSLOT_EVENT_INSERTION_CB); 1015 } else { 1016 /* who are you? */ 1017 } 1018 } else { 1019 timeout(pci113x_insert, sc, hz / 10); 1020 } 1021 } 1022 1023 #define PCCBB_PCMCIA_OFFSET 0x800 1024 static u_int8_t 1025 pccbb_pcmcia_read(ph, reg) 1026 struct pcic_handle *ph; 1027 int reg; 1028 { 1029 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1030 PCCBB_PCMCIA_OFFSET + reg); 1031 } 1032 1033 static void 1034 pccbb_pcmcia_write(ph, reg, val) 1035 struct pcic_handle *ph; 1036 int reg; 1037 u_int8_t val; 1038 { 1039 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1040 val); 1041 } 1042 1043 /* 1044 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1045 */ 1046 STATIC int 1047 pccbb_ctrl(ct, command) 1048 cardbus_chipset_tag_t ct; 1049 int command; 1050 { 1051 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1052 1053 switch (command) { 1054 case CARDBUS_CD: 1055 if (2 == pccbb_detect_card(sc)) { 1056 int retval = 0; 1057 int status = cb_detect_voltage(sc); 1058 if (PCCARD_VCC_5V & status) { 1059 retval |= CARDBUS_5V_CARD; 1060 } 1061 if (PCCARD_VCC_3V & status) { 1062 retval |= CARDBUS_3V_CARD; 1063 } 1064 if (PCCARD_VCC_XV & status) { 1065 retval |= CARDBUS_XV_CARD; 1066 } 1067 if (PCCARD_VCC_YV & status) { 1068 retval |= CARDBUS_YV_CARD; 1069 } 1070 return retval; 1071 } else { 1072 return 0; 1073 } 1074 break; 1075 case CARDBUS_RESET: 1076 return cb_reset(sc); 1077 break; 1078 case CARDBUS_IO_ENABLE: /* fallthrough */ 1079 case CARDBUS_IO_DISABLE: /* fallthrough */ 1080 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1081 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1082 case CARDBUS_BM_ENABLE: /* fallthrough */ 1083 case CARDBUS_BM_DISABLE: /* fallthrough */ 1084 return pccbb_cardenable(sc, command); 1085 break; 1086 } 1087 1088 return 0; 1089 } 1090 1091 /* 1092 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1093 * This function returns true when it succeeds and returns false when 1094 * it fails. 1095 */ 1096 STATIC int 1097 pccbb_power(ct, command) 1098 cardbus_chipset_tag_t ct; 1099 int command; 1100 { 1101 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1102 1103 u_int32_t status, sock_ctrl; 1104 bus_space_tag_t memt = sc->sc_base_memt; 1105 bus_space_handle_t memh = sc->sc_base_memh; 1106 1107 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1108 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1109 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1110 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1111 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1112 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1113 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1114 "UNKNOWN", 1115 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1116 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1117 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1118 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1119 "UNKNOWN", command)); 1120 1121 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1122 sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1123 1124 switch (command & CARDBUS_VCCMASK) { 1125 case CARDBUS_VCC_UC: 1126 break; 1127 case CARDBUS_VCC_5V: 1128 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1129 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1130 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1131 } else { 1132 printf("%s: BAD voltage request: no 5 V card\n", 1133 sc->sc_dev.dv_xname); 1134 } 1135 break; 1136 case CARDBUS_VCC_3V: 1137 if (CB_SOCKET_STAT_3VCARD & status) { 1138 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1139 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1140 } else { 1141 printf("%s: BAD voltage request: no 3.3 V card\n", 1142 sc->sc_dev.dv_xname); 1143 } 1144 break; 1145 case CARDBUS_VCC_0V: 1146 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1147 break; 1148 default: 1149 return 0; /* power NEVER changed */ 1150 break; 1151 } 1152 1153 switch (command & CARDBUS_VPPMASK) { 1154 case CARDBUS_VPP_UC: 1155 break; 1156 case CARDBUS_VPP_0V: 1157 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1158 break; 1159 case CARDBUS_VPP_VCC: 1160 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1161 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1162 break; 1163 case CARDBUS_VPP_12V: 1164 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1165 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1166 break; 1167 } 1168 1169 #if 0 1170 DPRINTF(("sock_ctrl: %x\n", sock_ctrl)); 1171 #endif 1172 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1173 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1174 1175 delay(20 * 1000); /* wait 20 ms: Vcc setup time */ 1176 /* 1177 * XXX delay 200 ms: though the standard defines that the Vcc set-up 1178 * time is 20 ms, some PC-Card bridge requires longer duration. 1179 */ 1180 delay(200 * 1000); 1181 1182 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1183 printf 1184 ("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1185 sc->sc_dev.dv_xname, sock_ctrl, status); 1186 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1187 (command & CARDBUS_VCCMASK) == 1188 CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : (command & 1189 CARDBUS_VCCMASK) == 1190 CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : (command & 1191 CARDBUS_VCCMASK) == 1192 CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : (command & 1193 CARDBUS_VCCMASK) == 1194 CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : (command & 1195 CARDBUS_VCCMASK) == 1196 CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : (command & 1197 CARDBUS_VCCMASK) == 1198 CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : "UNKNOWN", 1199 (command & CARDBUS_VPPMASK) == 1200 CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : (command & 1201 CARDBUS_VPPMASK) == 1202 CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : (command & 1203 CARDBUS_VPPMASK) == 1204 CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : (command & 1205 CARDBUS_VPPMASK) == 1206 CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : "UNKNOWN", command)); 1207 #if 0 1208 if (command == (CARDBUS_VCC_0V | CARDBUS_VPP_0V)) { 1209 u_int32_t force = 1210 bus_space_read_4(memt, memh, CB_SOCKET_FORCE); 1211 /* Reset Bad Vcc request */ 1212 force &= ~CB_SOCKET_FORCE_BADVCC; 1213 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, force); 1214 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1215 CB_SOCKET_STAT)); 1216 return 1; 1217 } 1218 #endif 1219 return 0; 1220 } 1221 return 1; /* power changed correctly */ 1222 } 1223 1224 #if defined CB_PCMCIA_POLL 1225 struct cb_poll_str { 1226 void *arg; 1227 int (*func) __P((void *)); 1228 int level; 1229 pccard_chipset_tag_t ct; 1230 int count; 1231 }; 1232 1233 static struct cb_poll_str cb_poll[10]; 1234 static int cb_poll_n = 0; 1235 1236 static void cb_pcmcia_poll __P((void *arg)); 1237 1238 static void 1239 cb_pcmcia_poll(arg) 1240 void *arg; 1241 { 1242 struct cb_poll_str *poll = arg; 1243 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1244 struct pccbb_softc *sc = psc->cpc_parent; 1245 int s; 1246 u_int32_t spsr; /* socket present-state reg */ 1247 1248 timeout(cb_pcmcia_poll, arg, hz / 10); 1249 switch (poll->level) { 1250 case IPL_NET: 1251 s = splnet(); 1252 break; 1253 case IPL_BIO: 1254 s = splbio(); 1255 break; 1256 case IPL_TTY: /* fallthrough */ 1257 default: 1258 s = spltty(); 1259 break; 1260 } 1261 1262 spsr = 1263 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1264 CB_SOCKET_STAT); 1265 1266 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1267 if (!(spsr & 0x40)) { /* CINT low */ 1268 #else 1269 if (1) { 1270 #endif 1271 if ((*poll->func) (poll->arg) == 1) { 1272 ++poll->count; 1273 printf("intr: reported from poller, 0x%x\n", spsr); 1274 #if defined LEVEL2 1275 } else { 1276 printf("intr: miss! 0x%x\n", spsr); 1277 #endif 1278 } 1279 } 1280 splx(s); 1281 } 1282 #endif /* defined CB_PCMCIA_POLL */ 1283 1284 /* 1285 * static int pccbb_detect_card(struct pccbb_softc *sc) 1286 * return value: 0 if no card exists. 1287 * 1 if 16-bit card exists. 1288 * 2 if cardbus card exists. 1289 */ 1290 static int 1291 pccbb_detect_card(sc) 1292 struct pccbb_softc *sc; 1293 { 1294 bus_space_handle_t base_memh = sc->sc_base_memh; 1295 bus_space_tag_t base_memt = sc->sc_base_memt; 1296 u_int32_t sockstat = 1297 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1298 int retval = 0; 1299 1300 /* CD1 and CD2 asserted */ 1301 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1302 /* card must be present */ 1303 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1304 /* NOTACARD DEASSERTED */ 1305 if (CB_SOCKET_STAT_CB & sockstat) { 1306 /* CardBus mode */ 1307 retval = 2; 1308 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1309 /* 16-bit mode */ 1310 retval = 1; 1311 } 1312 } 1313 } 1314 return retval; 1315 } 1316 1317 /* 1318 * STATIC int cb_reset(struct pccbb_softc *sc) 1319 * This function resets CardBus card. 1320 */ 1321 STATIC int 1322 cb_reset(sc) 1323 struct pccbb_softc *sc; 1324 { 1325 /* 1326 * Reset Assert at least 20 ms 1327 * Some machines request longer duration. 1328 */ 1329 int reset_duration = 1330 (sc->sc_chipset == CB_RX5C47X ? 400 * 1000 : 40 * 1000); 1331 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1332 1333 bcr |= (0x40 << 16); /* Reset bit Assert (bit 6 at 0x3E) */ 1334 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1335 delay(reset_duration); 1336 1337 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1338 bcr &= ~(0x40 << 16); /* Reset bit Deassert (bit 6 at 0x3E) */ 1339 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1340 delay(reset_duration); 1341 } 1342 /* No card found on the slot. Keep Reset. */ 1343 return 1; 1344 } 1345 1346 /* 1347 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1348 * This function detect card Voltage. 1349 */ 1350 STATIC int 1351 cb_detect_voltage(sc) 1352 struct pccbb_softc *sc; 1353 { 1354 u_int32_t psr; /* socket present-state reg */ 1355 bus_space_tag_t iot = sc->sc_base_memt; 1356 bus_space_handle_t ioh = sc->sc_base_memh; 1357 int vol = PCCARD_VCC_UKN; /* set 0 */ 1358 1359 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1360 1361 if (0x400u & psr) { 1362 vol |= PCCARD_VCC_5V; 1363 } 1364 if (0x800u & psr) { 1365 vol |= PCCARD_VCC_3V; 1366 } 1367 1368 return vol; 1369 } 1370 1371 STATIC int 1372 cbbprint(aux, pcic) 1373 void *aux; 1374 const char *pcic; 1375 { 1376 /* 1377 struct cbslot_attach_args *cba = aux; 1378 1379 if (cba->cba_slot >= 0) { 1380 printf(" slot %d", cba->cba_slot); 1381 } 1382 */ 1383 return UNCONF; 1384 } 1385 1386 /* 1387 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1388 * This function enables and disables the card 1389 */ 1390 STATIC int 1391 pccbb_cardenable(sc, function) 1392 struct pccbb_softc *sc; 1393 int function; 1394 { 1395 u_int32_t command = 1396 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1397 1398 DPRINTF(("pccbb_cardenable:")); 1399 switch (function) { 1400 case CARDBUS_IO_ENABLE: 1401 command |= PCI_COMMAND_IO_ENABLE; 1402 break; 1403 case CARDBUS_IO_DISABLE: 1404 command &= ~PCI_COMMAND_IO_ENABLE; 1405 break; 1406 case CARDBUS_MEM_ENABLE: 1407 command |= PCI_COMMAND_MEM_ENABLE; 1408 break; 1409 case CARDBUS_MEM_DISABLE: 1410 command &= ~PCI_COMMAND_MEM_ENABLE; 1411 break; 1412 case CARDBUS_BM_ENABLE: 1413 command |= PCI_COMMAND_MASTER_ENABLE; 1414 break; 1415 case CARDBUS_BM_DISABLE: 1416 command &= ~PCI_COMMAND_MASTER_ENABLE; 1417 break; 1418 default: 1419 return 0; 1420 } 1421 1422 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1423 DPRINTF((" command reg 0x%x\n", command)); 1424 return 1; 1425 } 1426 1427 #if !rbus 1428 /* 1429 * int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1430 */ 1431 static int 1432 pccbb_io_open(ct, win, start, end) 1433 cardbus_chipset_tag_t ct; 1434 int win; 1435 u_int32_t start, end; 1436 { 1437 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1438 int basereg; 1439 int limitreg; 1440 1441 if ((win < 0) || (win > 2)) { 1442 #if defined DIAGNOSTIC 1443 printf("cardbus_io_open: window out of range %d\n", win); 1444 #endif 1445 return 0; 1446 } 1447 1448 basereg = win * 8 + 0x2c; 1449 limitreg = win * 8 + 0x30; 1450 1451 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1452 start, basereg, end, limitreg)); 1453 1454 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1455 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1456 return 1; 1457 } 1458 1459 /* 1460 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1461 */ 1462 static int 1463 pccbb_io_close(ct, win) 1464 cardbus_chipset_tag_t ct; 1465 int win; 1466 { 1467 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1468 int basereg; 1469 int limitreg; 1470 1471 if ((win < 0) || (win > 2)) { 1472 #if defined DIAGNOSTIC 1473 printf("cardbus_io_close: window out of range %d\n", win); 1474 #endif 1475 return 0; 1476 } 1477 1478 basereg = win * 8 + 0x2c; 1479 limitreg = win * 8 + 0x30; 1480 1481 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1482 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1483 return 1; 1484 } 1485 1486 /* 1487 * int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1488 */ 1489 static int 1490 pccbb_mem_open(ct, win, start, end) 1491 cardbus_chipset_tag_t ct; 1492 int win; 1493 u_int32_t start, end; 1494 { 1495 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1496 int basereg; 1497 int limitreg; 1498 1499 if ((win < 0) || (win > 2)) { 1500 #if defined DIAGNOSTIC 1501 printf("cardbus_mem_open: window out of range %d\n", win); 1502 #endif 1503 return 0; 1504 } 1505 1506 basereg = win * 8 + 0x1c; 1507 limitreg = win * 8 + 0x20; 1508 1509 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1510 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1511 return 1; 1512 } 1513 1514 /* 1515 * int pccbb_mem_close(cardbus_chipset_tag_t, int) 1516 */ 1517 static int 1518 pccbb_mem_close(ct, win) 1519 cardbus_chipset_tag_t ct; 1520 int win; 1521 { 1522 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1523 int basereg; 1524 int limitreg; 1525 1526 if ((win < 0) || (win > 2)) { 1527 #if defined DIAGNOSTIC 1528 printf("cardbus_mem_close: window out of range %d\n", win); 1529 #endif 1530 return 0; 1531 } 1532 1533 basereg = win * 8 + 0x1c; 1534 limitreg = win * 8 + 0x20; 1535 1536 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1537 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1538 return 1; 1539 } 1540 #endif 1541 1542 /* 1543 * static void *pccbb_intr_establish(cardbus_chipset_tag_t ct, 1544 * int irq, 1545 * int level, 1546 * int (* func) __P((void *)), 1547 * void *arg) 1548 * 1549 * This function registers an interrupt handler at the bridge, in 1550 * order not to call the interrput handlers of child devices when 1551 * a card-deletion interrput occurs. 1552 * 1553 * The arguments irq and level are not used. 1554 */ 1555 static void * 1556 pccbb_intr_establish(ct, irq, level, func, arg) 1557 cardbus_chipset_tag_t ct; 1558 int irq, level; 1559 int (*func) __P((void *)); 1560 void *arg; 1561 { 1562 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1563 struct pccbb_intrhand_list *pil, *newpil; 1564 1565 if (sc->sc_pil == NULL) { 1566 /* initialise bridge intr routing */ 1567 1568 switch (sc->sc_chipset) { 1569 case CB_TI113X: 1570 { 1571 pcireg_t cbctrl = 1572 pci_conf_read(sc->sc_pc, sc->sc_tag, 1573 PCI_CBCTRL); 1574 /* functional intr enabled */ 1575 cbctrl |= PCI113X_CBCTRL_PCI_INTR; 1576 pci_conf_write(sc->sc_pc, sc->sc_tag, 1577 PCI_CBCTRL, cbctrl); 1578 break; 1579 } 1580 default: 1581 break; 1582 } 1583 } 1584 1585 /* 1586 * Allocate a room for interrut handler structure. 1587 */ 1588 if (NULL == (newpil = 1589 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1590 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1591 return NULL; 1592 } 1593 1594 newpil->pil_func = func; 1595 newpil->pil_arg = arg; 1596 newpil->pil_next = NULL; 1597 1598 if (sc->sc_pil == NULL) { 1599 sc->sc_pil = newpil; 1600 } else { 1601 for (pil = sc->sc_pil; pil->pil_next != NULL; 1602 pil = pil->pil_next); 1603 pil->pil_next = newpil; 1604 } 1605 1606 return newpil; 1607 } 1608 1609 /* 1610 * static void *pccbb_intr_disestablish(cardbus_chipset_tag_t ct, 1611 * void *ih) 1612 * 1613 * This function removes an interrupt handler pointed by ih. 1614 */ 1615 static void 1616 pccbb_intr_disestablish(ct, ih) 1617 cardbus_chipset_tag_t ct; 1618 void *ih; 1619 { 1620 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1621 struct pccbb_intrhand_list *pil, **pil_prev; 1622 1623 pil_prev = &sc->sc_pil; 1624 1625 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 1626 if (pil == ih) { 1627 *pil_prev = pil->pil_next; 1628 free(pil, M_DEVBUF); 1629 break; 1630 } 1631 pil_prev = &pil->pil_next; 1632 } 1633 1634 if (sc->sc_pil == NULL) { 1635 /* No interrupt handlers */ 1636 1637 switch (sc->sc_chipset) { 1638 case CB_TI113X: 1639 { 1640 pcireg_t cbctrl = 1641 pci_conf_read(sc->sc_pc, sc->sc_tag, 1642 PCI_CBCTRL); 1643 /* functional intr disabled */ 1644 cbctrl &= ~PCI113X_CBCTRL_PCI_INTR; 1645 pci_conf_write(sc->sc_pc, sc->sc_tag, 1646 PCI_CBCTRL, cbctrl); 1647 break; 1648 } 1649 default: 1650 break; 1651 } 1652 } 1653 } 1654 1655 #if defined SHOW_REGS 1656 static void 1657 cb_show_regs(pc, tag, memt, memh) 1658 pci_chipset_tag_t pc; 1659 pcitag_t tag; 1660 bus_space_tag_t memt; 1661 bus_space_handle_t memh; 1662 { 1663 int i; 1664 printf("PCI config regs:"); 1665 for (i = 0; i < 0x50; i += 4) { 1666 if (i % 16 == 0) { 1667 printf("\n 0x%02x:", i); 1668 } 1669 printf(" %08x", pci_conf_read(pc, tag, i)); 1670 } 1671 for (i = 0x80; i < 0xb0; i += 4) { 1672 if (i % 16 == 0) { 1673 printf("\n 0x%02x:", i); 1674 } 1675 printf(" %08x", pci_conf_read(pc, tag, i)); 1676 } 1677 1678 if (memh == 0) { 1679 printf("\n"); 1680 return; 1681 } 1682 1683 printf("\nsocket regs:"); 1684 for (i = 0; i <= 0x10; i += 0x04) { 1685 printf(" %08x", bus_space_read_4(memt, memh, i)); 1686 } 1687 printf("\nExCA regs:"); 1688 for (i = 0; i < 0x08; ++i) { 1689 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1690 } 1691 printf("\n"); 1692 return; 1693 } 1694 #endif 1695 1696 /* 1697 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1698 * int busno, int devno, int function) 1699 * This is the function to make a tag to access config space of 1700 * a CardBus Card. It works same as pci_conf_read. 1701 */ 1702 static cardbustag_t 1703 pccbb_make_tag(cc, busno, devno, function) 1704 cardbus_chipset_tag_t cc; 1705 int busno, devno, function; 1706 { 1707 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1708 1709 return pci_make_tag(sc->sc_pc, busno, devno, function); 1710 } 1711 1712 static void 1713 pccbb_free_tag(cc, tag) 1714 cardbus_chipset_tag_t cc; 1715 cardbustag_t tag; 1716 { 1717 } 1718 1719 /* 1720 * static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t cc, 1721 * cardbustag_t tag, int offset) 1722 * This is the function to read the config space of a CardBus Card. 1723 * It works same as pci_conf_read. 1724 */ 1725 static cardbusreg_t 1726 pccbb_conf_read(cc, tag, offset) 1727 cardbus_chipset_tag_t cc; 1728 cardbustag_t tag; 1729 int offset; /* register offset */ 1730 { 1731 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1732 1733 return pci_conf_read(sc->sc_pc, tag, offset); 1734 } 1735 1736 /* 1737 * static void pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, 1738 * int offs, cardbusreg_t val) 1739 * This is the function to write the config space of a CardBus Card. 1740 * It works same as pci_conf_write. 1741 */ 1742 static void 1743 pccbb_conf_write(cc, tag, reg, val) 1744 cardbus_chipset_tag_t cc; 1745 cardbustag_t tag; 1746 int reg; /* register offset */ 1747 cardbusreg_t val; 1748 { 1749 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1750 1751 pci_conf_write(sc->sc_pc, tag, reg, val); 1752 } 1753 1754 #if 0 1755 STATIC int 1756 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1757 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 1758 int speed, int flags, 1759 bus_space_handle_t * iohp) 1760 #endif 1761 /* 1762 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1763 * bus_addr_t start, bus_size_t size, 1764 * bus_size_t align, 1765 * struct pcmcia_io_handle *pcihp 1766 * 1767 * This function only allocates I/O region for pccard. This function 1768 * never maps the allcated region to pccard I/O area. 1769 * 1770 * XXX: The interface of this function is not very good, I believe. 1771 */ 1772 STATIC int 1773 pccbb_pcmcia_io_alloc(pch, start, size, align, pcihp) 1774 pcmcia_chipset_handle_t pch; 1775 bus_addr_t start; /* start address */ 1776 bus_size_t size; 1777 bus_size_t align; 1778 struct pcmcia_io_handle *pcihp; 1779 { 1780 struct pcic_handle *ph = (struct pcic_handle *)pch; 1781 bus_addr_t ioaddr; 1782 int flags = 0; 1783 bus_space_tag_t iot; 1784 bus_space_handle_t ioh; 1785 #if rbus 1786 rbus_tag_t rb; 1787 #endif 1788 if (align == 0) { 1789 align = size; /* XXX: funny??? */ 1790 } 1791 1792 /* 1793 * Allocate some arbitrary I/O space. 1794 */ 1795 1796 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 1797 1798 #if rbus 1799 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 1800 /* XXX: I assume all card decode lower 10 bits by its hardware */ 1801 if (rbus_space_alloc(rb, start, size, 0x3ff, align, 0, &ioaddr, &ioh)) { 1802 return 1; 1803 } 1804 #else 1805 if (start) { 1806 ioaddr = start; 1807 if (bus_space_map(iot, start, size, 0, &ioh)) { 1808 return 1; 1809 } 1810 DPRINTF(("pccbb_pcmcia_io_alloc map port %lx+%lx\n", 1811 (u_long) ioaddr, (u_long) size)); 1812 } else { 1813 flags |= PCMCIA_IO_ALLOCATED; 1814 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 1815 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 1816 size, align, 0, 0, &ioaddr, &ioh)) { 1817 /* No room be able to be get. */ 1818 return 1; 1819 } 1820 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 1821 (u_long) ioaddr, (u_long) size)); 1822 } 1823 #endif 1824 1825 pcihp->iot = iot; 1826 pcihp->ioh = ioh; 1827 pcihp->addr = ioaddr; 1828 pcihp->size = size; 1829 pcihp->flags = flags; 1830 1831 return 0; 1832 } 1833 1834 /* 1835 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 1836 * struct pcmcia_io_handle *pcihp) 1837 * 1838 * This function only frees I/O region for pccard. 1839 * 1840 * XXX: The interface of this function is not very good, I believe. 1841 */ 1842 void 1843 pccbb_pcmcia_io_free(pch, pcihp) 1844 pcmcia_chipset_handle_t pch; 1845 struct pcmcia_io_handle *pcihp; 1846 { 1847 #if !rbus 1848 bus_space_tag_t iot = pcihp->iot; 1849 #endif 1850 bus_space_handle_t ioh = pcihp->ioh; 1851 bus_size_t size = pcihp->size; 1852 1853 #if rbus 1854 struct pccbb_softc *sc = 1855 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 1856 rbus_tag_t rb = sc->sc_rbus_iot; 1857 1858 rbus_space_free(rb, ioh, size, NULL); 1859 #else 1860 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 1861 bus_space_free(iot, ioh, size); 1862 else 1863 bus_space_unmap(iot, ioh, size); 1864 #endif 1865 } 1866 1867 /* 1868 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 1869 * bus_addr_t offset, bus_size_t size, 1870 * struct pcmcia_io_handle *pcihp, 1871 * int *windowp) 1872 * 1873 * This function maps the allocated I/O region to pccard. This function 1874 * never allocates any I/O region for pccard I/O area. I don't 1875 * understand why the original authors of pcmciabus separated alloc and 1876 * map. I believe the two must be unite. 1877 * 1878 * XXX: no wait timing control? 1879 */ 1880 int 1881 pccbb_pcmcia_io_map(pch, width, offset, size, pcihp, windowp) 1882 pcmcia_chipset_handle_t pch; 1883 int width; 1884 bus_addr_t offset; 1885 bus_size_t size; 1886 struct pcmcia_io_handle *pcihp; 1887 int *windowp; 1888 { 1889 struct pcic_handle *ph = (struct pcic_handle *)pch; 1890 bus_addr_t ioaddr = pcihp->addr + offset; 1891 int i, win; 1892 #if defined CBB_DEBUG 1893 static char *width_names[] = { "dynamic", "io8", "io16" }; 1894 #endif 1895 1896 /* Sanity check I/O handle. */ 1897 1898 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 1899 panic("pccbb_pcmcia_io_map iot is bogus"); 1900 } 1901 1902 /* XXX Sanity check offset/size. */ 1903 1904 win = -1; 1905 for (i = 0; i < PCIC_IO_WINS; i++) { 1906 if ((ph->ioalloc & (1 << i)) == 0) { 1907 win = i; 1908 ph->ioalloc |= (1 << i); 1909 break; 1910 } 1911 } 1912 1913 if (win == -1) { 1914 return 1; 1915 } 1916 1917 *windowp = win; 1918 1919 /* XXX this is pretty gross */ 1920 1921 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 1922 win, width_names[width], (u_long) ioaddr, (u_long) size)); 1923 1924 /* XXX wtf is this doing here? */ 1925 1926 #if 0 1927 printf(" port 0x%lx", (u_long) ioaddr); 1928 if (size > 1) { 1929 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 1930 } 1931 #endif 1932 1933 ph->io[win].addr = ioaddr; 1934 ph->io[win].size = size; 1935 ph->io[win].width = width; 1936 1937 /* actual dirty register-value changing in the function below. */ 1938 pccbb_pcmcia_do_io_map(ph, win); 1939 1940 return 0; 1941 } 1942 1943 /* 1944 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 1945 * 1946 * This function changes register-value to map I/O region for pccard. 1947 */ 1948 static void 1949 pccbb_pcmcia_do_io_map(ph, win) 1950 struct pcic_handle *ph; 1951 int win; 1952 { 1953 static u_int8_t pcic_iowidth[3] = { 1954 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 1955 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 1956 PCIC_IOCTL_IO0_DATASIZE_8BIT, 1957 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 1958 PCIC_IOCTL_IO0_DATASIZE_16BIT, 1959 }; 1960 1961 #define PCIC_SIA_START_LOW 0 1962 #define PCIC_SIA_START_HIGH 1 1963 #define PCIC_SIA_STOP_LOW 2 1964 #define PCIC_SIA_STOP_HIGH 3 1965 1966 int regbase_win = 0x8 + win * 0x04; 1967 u_int8_t ioctl, enable; 1968 1969 DPRINTF( 1970 ("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx width %d\n", 1971 win, (long)ph->io[win].addr, (long)ph->io[win].size, 1972 ph->io[win].width * 8)); 1973 1974 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 1975 ph->io[win].addr & 0xff); 1976 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 1977 (ph->io[win].addr >> 8) & 0xff); 1978 1979 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 1980 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 1981 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 1982 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 1983 1984 ioctl = Pcic_read(ph, PCIC_IOCTL); 1985 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 1986 switch (win) { 1987 case 0: 1988 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 1989 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 1990 PCIC_IOCTL_IO0_DATASIZE_MASK); 1991 ioctl |= pcic_iowidth[ph->io[win].width]; 1992 enable |= PCIC_ADDRWIN_ENABLE_IO0; 1993 break; 1994 case 1: 1995 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 1996 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 1997 PCIC_IOCTL_IO1_DATASIZE_MASK); 1998 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 1999 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2000 break; 2001 } 2002 Pcic_write(ph, PCIC_IOCTL, ioctl); 2003 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2004 #if defined CBB_DEBUG 2005 { 2006 u_int8_t start_low = 2007 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2008 u_int8_t start_high = 2009 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2010 u_int8_t stop_low = 2011 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2012 u_int8_t stop_high = 2013 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2014 printf 2015 (" start %02x %02x, stop %02x %02x, ioctl %02x enable %02x\n", 2016 start_low, start_high, stop_low, stop_high, ioctl, enable); 2017 } 2018 #endif 2019 } 2020 2021 /* 2022 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2023 * 2024 * This function unmapss I/O region. No return value. 2025 */ 2026 STATIC void 2027 pccbb_pcmcia_io_unmap(pch, win) 2028 pcmcia_chipset_handle_t pch; 2029 int win; 2030 { 2031 struct pcic_handle *ph = (struct pcic_handle *)pch; 2032 int reg; 2033 2034 if (win >= PCIC_IO_WINS || win < 0) { 2035 panic("pccbb_pcmcia_io_unmap: window out of range"); 2036 } 2037 2038 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2039 switch (win) { 2040 case 0: 2041 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2042 break; 2043 case 1: 2044 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2045 break; 2046 } 2047 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2048 2049 ph->ioalloc &= ~(1 << win); 2050 } 2051 2052 /* 2053 * static void pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 2054 * 2055 * This function enables the card. All information is stored in 2056 * the first argument, pcmcia_chipset_handle_t. 2057 */ 2058 static void 2059 pccbb_pcmcia_wait_ready(ph) 2060 struct pcic_handle *ph; 2061 { 2062 int i; 2063 2064 DPRINTF(("pccbb_pcmcia_wait_ready: status 0x%02x\n", 2065 Pcic_read(ph, PCIC_IF_STATUS))); 2066 2067 for (i = 0; i < 10000; i++) { 2068 if (Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) { 2069 return; 2070 } 2071 delay(500); 2072 #ifdef CBB_DEBUG 2073 if ((i > 5000) && (i % 100 == 99)) 2074 printf("."); 2075 #endif 2076 } 2077 2078 #ifdef DIAGNOSTIC 2079 printf("pcic_wait_ready: ready never happened, status = %02x\n", 2080 Pcic_read(ph, PCIC_IF_STATUS)); 2081 #endif 2082 } 2083 2084 /* 2085 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2086 * 2087 * This function enables the card. All information is stored in 2088 * the first argument, pcmcia_chipset_handle_t. 2089 */ 2090 STATIC void 2091 pccbb_pcmcia_socket_enable(pch) 2092 pcmcia_chipset_handle_t pch; 2093 { 2094 struct pcic_handle *ph = (struct pcic_handle *)pch; 2095 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2096 int cardtype, win; 2097 u_int8_t power, intr; 2098 pcireg_t spsr; 2099 int voltage; 2100 #define PCIC_INTR_PCI PCIC_INTR_ENABLE 2101 2102 /* this bit is mostly stolen from pcic_attach_card */ 2103 2104 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2105 2106 /* get card Vcc info */ 2107 2108 spsr = 2109 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2110 CB_SOCKET_STAT); 2111 if (spsr & CB_SOCKET_STAT_5VCARD) { 2112 DPRINTF(("5V card\n")); 2113 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2114 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2115 DPRINTF(("3V card\n")); 2116 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2117 } else { 2118 printf("?V card, 0x%x\n", spsr); /* XXX */ 2119 return; 2120 } 2121 2122 /* assert reset bit */ 2123 intr = Pcic_read(ph, PCIC_INTR); 2124 intr &= ~(PCIC_INTR_RESET | PCIC_INTR_ENABLE | PCIC_INTR_CARDTYPE_MASK); 2125 Pcic_write(ph, PCIC_INTR, intr); 2126 2127 /* disable socket i/o: negate output enable bit */ 2128 2129 power = Pcic_read(ph, PCIC_PWRCTL); 2130 power &= ~PCIC_PWRCTL_OE; 2131 Pcic_write(ph, PCIC_PWRCTL, power); 2132 2133 /* power down the socket to reset it, clear the card reset pin */ 2134 2135 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2136 2137 /* 2138 * wait 200ms until power fails (Tpf). Then, wait 100ms since 2139 * we are changing Vcc (Toff). 2140 */ 2141 /* delay(300*1000); too much */ 2142 2143 /* power up the socket */ 2144 pccbb_power(sc, voltage); 2145 2146 /* 2147 * wait 100ms until power raise (Tpr) and 20ms to become 2148 * stable (Tsu(Vcc)). 2149 * 2150 * some machines require some more time to be settled 2151 * (another 200ms is added here). 2152 */ 2153 /* delay((100 + 20 + 200)*1000); too much */ 2154 2155 power = Pcic_read(ph, PCIC_PWRCTL); 2156 power |= PCIC_PWRCTL_OE; 2157 Pcic_write(ph, PCIC_PWRCTL, power); 2158 2159 /* 2160 * hold RESET at least 10us. 2161 */ 2162 delay(10); 2163 delay(2 * 1000); /* XXX: TI1130 requires it. */ 2164 delay(20 * 1000); /* XXX: TI1130 requires it. */ 2165 2166 /* clear the reset flag */ 2167 2168 intr |= PCIC_INTR_RESET; 2169 Pcic_write(ph, PCIC_INTR, intr); 2170 2171 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 2172 2173 delay(20000); 2174 2175 /* wait for the chip to finish initializing */ 2176 2177 pccbb_pcmcia_wait_ready(ph); 2178 2179 /* zero out the address windows */ 2180 2181 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2182 2183 /* set the card type */ 2184 2185 cardtype = pcmcia_card_gettype(ph->pcmcia); 2186 2187 intr |= PCIC_INTR_PCI; 2188 intr |= ((cardtype == PCMCIA_IFTYPE_IO) ? 2189 PCIC_INTR_CARDTYPE_IO : PCIC_INTR_CARDTYPE_MEM); 2190 Pcic_write(ph, PCIC_INTR, intr); 2191 2192 DPRINTF(("%s: pccbb_pcmcia_socket_enable %02x cardtype %s %02x\n", 2193 ph->ph_parent->dv_xname, ph->sock, 2194 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2195 2196 /* reinstall all the memory and io mappings */ 2197 2198 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2199 if (ph->memalloc & (1 << win)) { 2200 pccbb_pcmcia_do_mem_map(ph, win); 2201 } 2202 } 2203 2204 for (win = 0; win < PCIC_IO_WINS; ++win) { 2205 if (ph->ioalloc & (1 << win)) { 2206 pccbb_pcmcia_do_io_map(ph, win); 2207 } 2208 } 2209 } 2210 2211 /* 2212 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2213 * 2214 * This function disables the card. All information is stored in 2215 * the first argument, pcmcia_chipset_handle_t. 2216 */ 2217 STATIC void 2218 pccbb_pcmcia_socket_disable(pch) 2219 pcmcia_chipset_handle_t pch; 2220 { 2221 struct pcic_handle *ph = (struct pcic_handle *)pch; 2222 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2223 u_int8_t power, intr; 2224 2225 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2226 2227 /* reset signal asserting... */ 2228 2229 intr = Pcic_read(ph, PCIC_INTR); 2230 intr &= ~(PCIC_INTR_RESET | PCIC_INTR_ENABLE | PCIC_INTR_CARDTYPE_MASK); 2231 Pcic_write(ph, PCIC_INTR, intr); 2232 delay(2 * 1000); 2233 2234 /* power down the socket */ 2235 power = Pcic_read(ph, PCIC_PWRCTL); 2236 power &= ~PCIC_PWRCTL_OE; 2237 Pcic_write(ph, PCIC_PWRCTL, power); 2238 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2239 /* 2240 * wait 300ms until power fails (Tpf). 2241 */ 2242 delay(300 * 1000); 2243 } 2244 2245 /* 2246 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2247 * 2248 * This function detects whether a card is in the slot or not. 2249 * If a card is inserted, return 1. Otherwise, return 0. 2250 */ 2251 STATIC int 2252 pccbb_pcmcia_card_detect(pch) 2253 pcmcia_chipset_handle_t pch; 2254 { 2255 struct pcic_handle *ph = (struct pcic_handle *)pch; 2256 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2257 2258 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2259 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2260 } 2261 2262 #if 0 2263 STATIC int 2264 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2265 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2266 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2267 #endif 2268 /* 2269 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2270 * bus_size_t size, 2271 * struct pcmcia_mem_handle *pcmhp) 2272 * 2273 * This function only allocates memory region for pccard. This 2274 * function never maps the allcated region to pccard memory area. 2275 * 2276 * XXX: Why the argument of start address is not in? 2277 */ 2278 STATIC int 2279 pccbb_pcmcia_mem_alloc(pch, size, pcmhp) 2280 pcmcia_chipset_handle_t pch; 2281 bus_size_t size; 2282 struct pcmcia_mem_handle *pcmhp; 2283 { 2284 struct pcic_handle *ph = (struct pcic_handle *)pch; 2285 bus_space_handle_t memh; 2286 bus_addr_t addr; 2287 bus_size_t sizepg; 2288 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2289 #if rbus 2290 rbus_tag_t rb; 2291 #endif 2292 2293 /* out of sc->memh, allocate as many pages as necessary */ 2294 2295 /* convert size to PCIC pages */ 2296 /* 2297 * This is not enough; when the requested region is on the page 2298 * boundaries, this may calculate wrong result. 2299 */ 2300 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2301 #if 0 2302 if (sizepg > PCIC_MAX_MEM_PAGES) { 2303 return 1; 2304 } 2305 #endif 2306 2307 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2308 return 1; 2309 } 2310 2311 addr = 0; /* XXX gcc -Wuninitialized */ 2312 2313 #if rbus 2314 rb = sc->sc_rbus_memt; 2315 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2316 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2317 &addr, &memh)) { 2318 return 1; 2319 } 2320 #else 2321 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2322 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2323 0, /* boundary */ 2324 0, /* flags */ 2325 &addr, &memh)) { 2326 return 1; 2327 } 2328 #endif 2329 2330 DPRINTF( 2331 ("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, realsize 0x%lx\n", 2332 addr, size, sizepg * PCIC_MEM_PAGESIZE)); 2333 2334 pcmhp->memt = sc->sc_memt; 2335 pcmhp->memh = memh; 2336 pcmhp->addr = addr; 2337 pcmhp->size = size; 2338 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2339 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2340 pcmhp->mhandle = 0; 2341 /* No offset??? Funny. */ 2342 2343 return 0; 2344 } 2345 2346 /* 2347 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2348 * struct pcmcia_mem_handle *pcmhp) 2349 * 2350 * This function release the memory space allocated by the fuction 2351 * pccbb_pcmcia_mem_alloc(). 2352 */ 2353 STATIC void 2354 pccbb_pcmcia_mem_free(pch, pcmhp) 2355 pcmcia_chipset_handle_t pch; 2356 struct pcmcia_mem_handle *pcmhp; 2357 { 2358 #if rbus 2359 struct pcic_handle *ph = (struct pcic_handle *)pch; 2360 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2361 2362 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2363 #else 2364 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2365 #endif 2366 } 2367 2368 /* 2369 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2370 * 2371 * This function release the memory space allocated by the fuction 2372 * pccbb_pcmcia_mem_alloc(). 2373 */ 2374 STATIC void 2375 pccbb_pcmcia_do_mem_map(ph, win) 2376 struct pcic_handle *ph; 2377 int win; 2378 { 2379 int regbase_win; 2380 bus_addr_t phys_addr; 2381 bus_addr_t phys_end; 2382 2383 #define PCIC_SMM_START_LOW 0 2384 #define PCIC_SMM_START_HIGH 1 2385 #define PCIC_SMM_STOP_LOW 2 2386 #define PCIC_SMM_STOP_HIGH 3 2387 #define PCIC_CMA_LOW 4 2388 #define PCIC_CMA_HIGH 5 2389 2390 u_int8_t start_low, start_high = 0; 2391 u_int8_t stop_low, stop_high; 2392 u_int8_t off_low, off_high; 2393 u_int8_t mem_window; 2394 int reg; 2395 2396 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2397 int mem8 = 2398 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8; 2399 2400 regbase_win = 0x10 + win * 0x08; 2401 2402 phys_addr = ph->mem[win].addr; 2403 phys_end = phys_addr + ph->mem[win].size; 2404 2405 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2406 phys_addr, phys_end, ph->mem[win].offset)); 2407 2408 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2409 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2410 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2411 2412 /* bit 19:12 */ 2413 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2414 /* bit 23:20 and bit 7 on */ 2415 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2416 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2417 /* bit 31:24, for 32-bit address */ 2418 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2419 2420 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2421 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2422 2423 if (((struct pccbb_softc *)ph-> 2424 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2425 Pcic_write(ph, 0x40 + win, mem_window); 2426 } 2427 2428 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2429 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2430 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2431 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2432 2433 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2434 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2435 2436 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2437 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2438 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2439 | ((kind == PCMCIA_MEM_ATTR) ? 2440 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2441 2442 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2443 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2444 2445 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2446 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2447 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2448 2449 #if defined CBB_DEBUG 2450 { 2451 int r1, r2, r3, r4, r5, r6, r7 = 0; 2452 2453 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2454 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2455 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2456 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2457 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2458 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2459 if (((struct pccbb_softc *)(ph-> 2460 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2461 r7 = Pcic_read(ph, 0x40 + win); 2462 } 2463 2464 DPRINTF(("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2465 "%02x%02x", win, r1, r2, r3, r4, r5, r6)); 2466 if (((struct pccbb_softc *)(ph-> 2467 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2468 DPRINTF((" %02x", r7)); 2469 } 2470 DPRINTF(("\n")); 2471 } 2472 #endif 2473 } 2474 2475 /* 2476 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2477 * bus_addr_t card_addr, bus_size_t size, 2478 * struct pcmcia_mem_handle *pcmhp, 2479 * bus_addr_t *offsetp, int *windowp) 2480 * 2481 * This function maps memory space allocated by the fuction 2482 * pccbb_pcmcia_mem_alloc(). 2483 */ 2484 STATIC int 2485 pccbb_pcmcia_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 2486 pcmcia_chipset_handle_t pch; 2487 int kind; 2488 bus_addr_t card_addr; 2489 bus_size_t size; 2490 struct pcmcia_mem_handle *pcmhp; 2491 bus_addr_t *offsetp; 2492 int *windowp; 2493 { 2494 struct pcic_handle *ph = (struct pcic_handle *)pch; 2495 bus_addr_t busaddr; 2496 long card_offset; 2497 int win; 2498 2499 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2500 if ((ph->memalloc & (1 << win)) == 0) { 2501 ph->memalloc |= (1 << win); 2502 break; 2503 } 2504 } 2505 2506 if (win == PCIC_MEM_WINS) { 2507 return 1; 2508 } 2509 2510 *windowp = win; 2511 2512 /* XXX this is pretty gross */ 2513 2514 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2515 panic("pccbb_pcmcia_mem_map memt is bogus"); 2516 } 2517 2518 busaddr = pcmhp->addr; 2519 2520 /* 2521 * compute the address offset to the pcmcia address space for the 2522 * pcic. this is intentionally signed. The masks and shifts below 2523 * will cause TRT to happen in the pcic registers. Deal with making 2524 * sure the address is aligned, and return the alignment offset. 2525 */ 2526 2527 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2528 card_addr -= *offsetp; 2529 2530 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2531 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2532 (u_long) card_addr)); 2533 2534 /* 2535 * include the offset in the size, and decrement size by one, since 2536 * the hw wants start/stop 2537 */ 2538 size += *offsetp - 1; 2539 2540 card_offset = (((long)card_addr) - ((long)busaddr)); 2541 2542 ph->mem[win].addr = busaddr; 2543 ph->mem[win].size = size; 2544 ph->mem[win].offset = card_offset; 2545 ph->mem[win].kind = kind; 2546 2547 pccbb_pcmcia_do_mem_map(ph, win); 2548 2549 return 0; 2550 } 2551 2552 /* 2553 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2554 * int window) 2555 * 2556 * This function unmaps memory space which mapped by the fuction 2557 * pccbb_pcmcia_mem_map(). 2558 */ 2559 STATIC void 2560 pccbb_pcmcia_mem_unmap(pch, window) 2561 pcmcia_chipset_handle_t pch; 2562 int window; 2563 { 2564 struct pcic_handle *ph = (struct pcic_handle *)pch; 2565 int reg; 2566 2567 if (window >= PCIC_MEM_WINS) { 2568 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2569 } 2570 2571 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2572 reg &= ~(1 << window); 2573 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2574 2575 ph->memalloc &= ~(1 << window); 2576 } 2577 2578 #if defined PCCBB_PCMCIA_POLL 2579 struct pccbb_poll_str { 2580 void *arg; 2581 int (*func) __P((void *)); 2582 int level; 2583 struct pcic_handle *ph; 2584 int count; 2585 int num; 2586 }; 2587 2588 static struct pccbb_poll_str pccbb_poll[10]; 2589 static int pccbb_poll_n = 0; 2590 2591 static void pccbb_pcmcia_poll __P((void *arg)); 2592 2593 static void 2594 pccbb_pcmcia_poll(arg) 2595 void *arg; 2596 { 2597 struct pccbb_poll_str *poll = arg; 2598 struct pcic_handle *ph = poll->ph; 2599 struct pccbb_softc *sc = ph->sc; 2600 int s; 2601 u_int32_t spsr; /* socket present-state reg */ 2602 2603 timeout(pccbb_pcmcia_poll, arg, hz * 2); 2604 switch (poll->level) { 2605 case IPL_NET: 2606 s = splnet(); 2607 break; 2608 case IPL_BIO: 2609 s = splbio(); 2610 break; 2611 case IPL_TTY: /* fallthrough */ 2612 default: 2613 s = spltty(); 2614 break; 2615 } 2616 2617 spsr = 2618 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2619 CB_SOCKET_STAT); 2620 2621 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2622 if (!(spsr & 0x40)) /* CINT low */ 2623 #else 2624 if (1) 2625 #endif 2626 { 2627 if ((*poll->func) (poll->arg) > 0) { 2628 ++poll->count; 2629 // printf("intr: reported from poller, 0x%x\n", spsr); 2630 #if defined LEVEL2 2631 } else { 2632 printf("intr: miss! 0x%x\n", spsr); 2633 #endif 2634 } 2635 } 2636 splx(s); 2637 } 2638 #endif /* defined CB_PCMCIA_POLL */ 2639 2640 /* 2641 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2642 * struct pcmcia_function *pf, 2643 * int ipl, 2644 * int (*func)(void *), 2645 * void *arg); 2646 * 2647 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2648 */ 2649 STATIC void * 2650 pccbb_pcmcia_intr_establish(pch, pf, ipl, func, arg) 2651 pcmcia_chipset_handle_t pch; 2652 struct pcmcia_function *pf; 2653 int ipl; 2654 int (*func) __P((void *)); 2655 void *arg; 2656 { 2657 struct pcic_handle *ph = (struct pcic_handle *)pch; 2658 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2659 pci_intr_handle_t handle; 2660 void *ih; 2661 2662 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2663 /* what should I do? */ 2664 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2665 DPRINTF( 2666 ("%s does not provide edge nor pulse interrupt\n", 2667 sc->sc_dev.dv_xname)); 2668 return NULL; 2669 } 2670 /* 2671 * XXX Noooooo! The interrupt flag must set properly!! 2672 * dumb pcmcia driver!! 2673 */ 2674 } 2675 2676 if (pci_intr_map(sc->sc_pc, sc->sc_intrtag, sc->sc_intrpin, 2677 sc->sc_intrline, &handle)) { 2678 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 2679 return NULL; 2680 } 2681 DPRINTF(("pccbb_pcmcia_intr_establish: line %d, handle %d\n", 2682 sc->sc_intrline, handle)); 2683 2684 if (NULL != (ih = 2685 pci_intr_establish(sc->sc_pc, handle, ipl, func, arg))) { 2686 u_int32_t cbctrl; 2687 2688 if ((CB_TI113X == sc->sc_chipset)) { 2689 cbctrl = 2690 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 2691 /* PCI functional intr req */ 2692 cbctrl |= PCI113X_CBCTRL_PCI_INTR; 2693 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, 2694 cbctrl); 2695 } 2696 } 2697 #if defined PCCBB_PCMCIA_POLL 2698 if (pccbb_poll_n < 10) { 2699 pccbb_poll[pccbb_poll_n].arg = arg; 2700 pccbb_poll[pccbb_poll_n].func = func; 2701 pccbb_poll[pccbb_poll_n].level = ipl; 2702 pccbb_poll[pccbb_poll_n].count = 0; 2703 pccbb_poll[pccbb_poll_n].num = pccbb_poll_n; 2704 pccbb_poll[pccbb_poll_n].ph = ph; 2705 timeout(pccbb_pcmcia_poll, &pccbb_poll[pccbb_poll_n++], hz * 2); 2706 printf("polling set\n"); 2707 } 2708 #endif 2709 #if defined SHOW_REGS 2710 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, sc->sc_base_memh); 2711 #endif 2712 2713 return ih; 2714 } 2715 2716 /* 2717 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2718 * void *ih) 2719 * 2720 * This function disables PC-Card interrupt. 2721 */ 2722 STATIC void 2723 pccbb_pcmcia_intr_disestablish(pch, ih) 2724 pcmcia_chipset_handle_t pch; 2725 void *ih; 2726 { 2727 struct pcic_handle *ph = (struct pcic_handle *)pch; 2728 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2729 2730 pci_intr_disestablish(sc->sc_pc, ih); 2731 } 2732 2733 #if rbus 2734 /* 2735 * static int 2736 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2737 * bus_addr_t addr, bus_size_t size, 2738 * bus_addr_t mask, bus_size_t align, 2739 * int flags, bus_addr_t *addrp; 2740 * bus_space_handle_t *bshp) 2741 * 2742 * This function allocates a portion of memory or io space for 2743 * clients. This function is called from CardBus card drivers. 2744 */ 2745 static int 2746 pccbb_rbus_cb_space_alloc(ct, rb, addr, size, mask, align, flags, addrp, bshp) 2747 cardbus_chipset_tag_t ct; 2748 rbus_tag_t rb; 2749 bus_addr_t addr; 2750 bus_size_t size; 2751 bus_addr_t mask; 2752 bus_size_t align; 2753 int flags; 2754 bus_addr_t *addrp; 2755 bus_space_handle_t *bshp; 2756 { 2757 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2758 2759 DPRINTF( 2760 ("pccbb_rbus_cb_space_alloc: adr %lx, size %lx, mask %lx, align %lx\n", 2761 addr, size, mask, align)); 2762 2763 if (align == 0) { 2764 align = size; 2765 } 2766 2767 if (rb->rb_bt == sc->sc_memt) { 2768 if (align < 16) { 2769 return 1; 2770 } 2771 } else if (rb->rb_bt == sc->sc_iot) { 2772 if (align < 4) { 2773 return 1; 2774 } 2775 } else { 2776 DPRINTF( 2777 ("pccbb_rbus_cb_space_alloc: Bus space tag %x is NOT used.\n", 2778 rb->rb_bt)); 2779 return 1; 2780 /* XXX: panic here? */ 2781 } 2782 2783 /* XXX: hack for avoiding ISA image */ 2784 if (mask < 0x3ff) { 2785 mask = 0x3ff; 2786 addr = 0x300; 2787 } 2788 2789 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 2790 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 2791 return 1; 2792 } 2793 2794 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 2795 2796 return 0; 2797 } 2798 2799 /* 2800 * static int 2801 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 2802 * bus_space_handle_t *bshp, bus_size_t size); 2803 * 2804 * This function is called from CardBus card drivers. 2805 */ 2806 static int 2807 pccbb_rbus_cb_space_free(ct, rb, bsh, size) 2808 cardbus_chipset_tag_t ct; 2809 rbus_tag_t rb; 2810 bus_space_handle_t bsh; 2811 bus_size_t size; 2812 { 2813 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2814 bus_space_tag_t bt = rb->rb_bt; 2815 2816 pccbb_close_win(sc, bt, bsh, size); 2817 2818 if (bt == sc->sc_memt) { 2819 } else if (bt == sc->sc_iot) { 2820 } else { 2821 return 1; 2822 /* XXX: panic here? */ 2823 } 2824 2825 return rbus_space_free(rb, bsh, size, NULL); 2826 } 2827 #endif /* rbus */ 2828 2829 #if rbus 2830 2831 static int 2832 pccbb_open_win(sc, bst, addr, size, bsh, flags) 2833 struct pccbb_softc *sc; 2834 bus_space_tag_t bst; 2835 bus_addr_t addr; 2836 bus_size_t size; 2837 bus_space_handle_t bsh; 2838 int flags; 2839 { 2840 struct pccbb_win_chain **top; 2841 bus_addr_t align; 2842 2843 top = &sc->sc_iowindow; 2844 align = 0x04; 2845 if (sc->sc_memt == bst) { 2846 top = &sc->sc_memwindow; 2847 align = 0x1000; 2848 DPRINTF(("using memory window, %x %x %x\n\n", 2849 sc->sc_iot, sc->sc_memt, bst)); 2850 } 2851 2852 if (pccbb_winlist_insert(top, addr, size, bsh, flags)) { 2853 printf("winlist insert fails:\n"); 2854 } 2855 pccbb_winset(align, sc, bst); 2856 2857 return 0; 2858 } 2859 2860 static int 2861 pccbb_close_win(sc, bst, bsh, size) 2862 struct pccbb_softc *sc; 2863 bus_space_tag_t bst; 2864 bus_space_handle_t bsh; 2865 bus_size_t size; 2866 { 2867 struct pccbb_win_chain **top; 2868 bus_addr_t align; 2869 2870 top = &sc->sc_iowindow; 2871 align = 0x04; 2872 if (sc->sc_memt == bst) { 2873 top = &sc->sc_memwindow; 2874 align = 0x1000; 2875 } 2876 2877 if (pccbb_winlist_delete(top, bsh, size)) { 2878 printf("winlist delete fails:\n"); 2879 } 2880 pccbb_winset(align, sc, bst); 2881 2882 return 0; 2883 } 2884 2885 static int 2886 pccbb_winlist_insert(top, start, size, bsh, flags) 2887 struct pccbb_win_chain **top; 2888 bus_addr_t start; 2889 bus_size_t size; 2890 bus_space_handle_t bsh; 2891 int flags; 2892 { 2893 struct pccbb_win_chain *chainp = *top; 2894 struct pccbb_win_chain *before = *top; 2895 struct pccbb_win_chain *elem; 2896 2897 if (*top == NULL) { 2898 if (NULL == (elem = 2899 (struct pccbb_win_chain *)malloc(sizeof(struct 2900 pccbb_win_chain), M_DEVBUF, M_NOWAIT))) { 2901 return 1; /* fail */ 2902 } 2903 2904 elem->wc_start = start; 2905 elem->wc_end = start + size - 1; 2906 elem->wc_handle = bsh; 2907 elem->wc_flags = flags; 2908 2909 *top = elem; 2910 elem->wc_next = NULL; 2911 return 0; 2912 } 2913 2914 for (; chainp && chainp->wc_start <= start; chainp = chainp->wc_next) { 2915 before = chainp; 2916 } 2917 2918 if (chainp != NULL) { 2919 if (chainp->wc_start < start + size) { 2920 printf("fatal! 0x%lx 0x%lx\n", chainp->wc_start, 2921 start + size); 2922 return 1; 2923 } 2924 } 2925 if ((before != *top) && (before->wc_end >= start)) { 2926 printf("fatal!! 0x%lx 0x%lx\n", before->wc_end, start); 2927 return 1; 2928 } 2929 2930 if (NULL == (elem = 2931 (struct pccbb_win_chain *)malloc(sizeof(struct pccbb_win_chain), 2932 M_DEVBUF, M_NOWAIT))) { 2933 return 1; /* fail */ 2934 } 2935 2936 elem->wc_start = start; 2937 elem->wc_end = start + size - 1; 2938 elem->wc_handle = bsh; 2939 elem->wc_flags = flags; 2940 2941 elem->wc_next = chainp; 2942 if (chainp == *top) { 2943 *top = elem; 2944 } else { 2945 before->wc_next = elem; 2946 } 2947 return 0; 2948 } 2949 2950 static int 2951 pccbb_winlist_delete(top, bsh, size) 2952 struct pccbb_win_chain **top; 2953 bus_space_handle_t bsh; 2954 bus_size_t size; 2955 { 2956 struct pccbb_win_chain *chainp = *top; 2957 struct pccbb_win_chain **before = top; 2958 2959 for (; chainp && chainp->wc_handle != bsh; chainp = chainp->wc_next) { 2960 before = &chainp->wc_next; 2961 } 2962 2963 if (chainp == NULL) { 2964 return 1; /* fail: no candidate to remove */ 2965 } 2966 2967 if (chainp->wc_end - chainp->wc_start != size - 1) { 2968 printf("fatal!!! 0x%lx\n", chainp->wc_start); 2969 return 1; /* fail: no candidate to remove */ 2970 } 2971 2972 *before = chainp->wc_next; 2973 free(chainp, M_DEVBUF); 2974 2975 return 0; 2976 } 2977 2978 static void 2979 pccbb_winset(align, sc, bst) 2980 bus_addr_t align; 2981 struct pccbb_softc *sc; 2982 bus_space_tag_t bst; 2983 { 2984 pci_chipset_tag_t pc; 2985 pcitag_t tag; 2986 bus_addr_t mask = ~(align - 1); 2987 struct { 2988 cardbusreg_t win_start; 2989 cardbusreg_t win_limit; 2990 int win_flags; 2991 } win[2]; 2992 struct pccbb_win_chain *chainp; 2993 int offs; 2994 2995 win[0].win_start = 0xffffffff; 2996 win[0].win_limit = 0; 2997 win[1].win_start = 0xffffffff; 2998 win[1].win_limit = 0; 2999 3000 chainp = sc->sc_iowindow; 3001 offs = 0x2c; 3002 if (sc->sc_memt == bst) { 3003 chainp = sc->sc_memwindow; 3004 offs = 0x1c; 3005 } 3006 3007 if (chainp) { 3008 win[0].win_start = chainp->wc_start & mask; 3009 win[0].win_limit = chainp->wc_end & mask; 3010 win[0].win_flags = chainp->wc_flags; 3011 chainp = chainp->wc_next; 3012 } 3013 3014 for (; chainp; chainp = chainp->wc_next) { 3015 if (win[1].win_start == 0xffffffff) { 3016 /* window 1 is not used */ 3017 if ((win[0].win_flags == chainp->wc_flags) && 3018 (win[0].win_limit + align >= 3019 (chainp->wc_start & mask))) { 3020 /* concatinate */ 3021 win[0].win_limit = chainp->wc_end & mask; 3022 } else { 3023 /* make new window */ 3024 win[1].win_start = chainp->wc_start & mask; 3025 win[1].win_limit = chainp->wc_end & mask; 3026 win[1].win_flags = chainp->wc_flags; 3027 } 3028 continue; 3029 } 3030 3031 /* Both windows are engagad. */ 3032 if (win[0].win_flags == win[1].win_flags) { 3033 /* same flags */ 3034 if (win[0].win_flags == chainp->wc_flags) { 3035 if (win[1].win_start - (win[0].win_limit + 3036 align) < 3037 (chainp->wc_start & mask) - 3038 ((chainp->wc_end & mask) + align)) { 3039 /* 3040 * merge window 0 and 1, and set win1 3041 * to chainp 3042 */ 3043 win[0].win_limit = win[1].win_limit; 3044 win[1].win_start = 3045 chainp->wc_start & mask; 3046 win[1].win_limit = 3047 chainp->wc_end & mask; 3048 } else { 3049 win[1].win_limit = 3050 chainp->wc_end & mask; 3051 } 3052 } else { 3053 /* different flags */ 3054 3055 /* concatinate win0 and win1 */ 3056 win[0].win_limit = win[1].win_limit; 3057 /* allocate win[1] to new space */ 3058 win[1].win_start = chainp->wc_start & mask; 3059 win[1].win_limit = chainp->wc_end & mask; 3060 win[1].win_flags = chainp->wc_flags; 3061 } 3062 } else { 3063 /* the flags of win[0] and win[1] is different */ 3064 if (win[0].win_flags == chainp->wc_flags) { 3065 win[0].win_limit = chainp->wc_end & mask; 3066 /* 3067 * XXX this creates overlapping windows, so 3068 * what should the poor bridge do if one is 3069 * cachable, and the other is not? 3070 */ 3071 printf("%s: overlapping windows\n", 3072 sc->sc_dev.dv_xname); 3073 } else { 3074 win[1].win_limit = chainp->wc_end & mask; 3075 } 3076 } 3077 } 3078 3079 pc = sc->sc_pc; 3080 tag = sc->sc_tag; 3081 pci_conf_write(pc, tag, offs, win[0].win_start); 3082 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3083 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3084 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3085 DPRINTF(("--pccbb_winset: win0 [%x, %lx), win1 [%x, %lx)\n", 3086 pci_conf_read(pc, tag, offs), 3087 pci_conf_read(pc, tag, offs + 4) + align, 3088 pci_conf_read(pc, tag, offs + 8), 3089 pci_conf_read(pc, tag, offs + 12) + align)); 3090 3091 if (bst == sc->sc_memt) { 3092 if (win[0].win_flags & PCCBB_MEM_CACHABLE) { 3093 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3094 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3095 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3096 } 3097 if (win[1].win_flags & PCCBB_MEM_CACHABLE) { 3098 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3099 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3100 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3101 } 3102 } 3103 } 3104 3105 #endif /* rbus */ 3106
Indexes created Fri Sep 26 08:10:20 GMT 2025