pccbb.c revision 1.25
1 /* $NetBSD: pccbb.c,v 1.25 2000/02/22 02:35:26 enami Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 #define CBB_DEBUG 35 #define SHOW_REGS 36 #define PCCBB_PCMCIA_POLL 37 */ 38 /* #define CBB_DEBUG */ 39 40 /* 41 #define CB_PCMCIA_POLL 42 #define CB_PCMCIA_POLL_ONLY 43 #define LEVEL2 44 */ 45 46 #include <sys/types.h> 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/kernel.h> 50 #include <sys/errno.h> 51 #include <sys/ioctl.h> 52 #include <sys/syslog.h> 53 #include <sys/device.h> 54 #include <sys/malloc.h> 55 56 #include <machine/intr.h> 57 #include <machine/bus.h> 58 59 #include <dev/pci/pcivar.h> 60 #include <dev/pci/pcireg.h> 61 #include <dev/pci/pcidevs.h> 62 63 #include <dev/pci/pccbbreg.h> 64 65 #include <dev/cardbus/cardslotvar.h> 66 67 #include <dev/cardbus/cardbusvar.h> 68 69 #include <dev/pcmcia/pcmciareg.h> 70 #include <dev/pcmcia/pcmciavar.h> 71 72 #include <dev/ic/i82365reg.h> 73 #include <dev/ic/i82365var.h> 74 #include <dev/pci/pccbbvar.h> 75 76 #include "locators.h" 77 78 #ifndef __NetBSD_Version__ 79 struct cfdriver cbb_cd = { 80 NULL, "cbb", DV_DULL 81 }; 82 #endif 83 84 #if defined CBB_DEBUG 85 #define DPRINTF(x) printf x 86 #define STATIC 87 #else 88 #define DPRINTF(x) 89 #define STATIC static 90 #endif 91 92 #ifdef __BROKEN_INDIRECT_CONFIG 93 int pcicbbmatch __P((struct device *, void *, void *)); 94 #else 95 int pcicbbmatch __P((struct device *, struct cfdata *, void *)); 96 #endif 97 void pccbbattach __P((struct device *, struct device *, void *)); 98 int pccbbintr __P((void *)); 99 static void pci113x_insert __P((void *)); 100 static int pccbbintr_function __P((struct pccbb_softc *)); 101 102 static int pccbb_detect_card __P((struct pccbb_softc *)); 103 104 static void pccbb_pcmcia_write __P((struct pcic_handle *, int, u_int8_t)); 105 static u_int8_t pccbb_pcmcia_read __P((struct pcic_handle *, int)); 106 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 107 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 108 109 STATIC int cb_reset __P((struct pccbb_softc *)); 110 STATIC int cb_detect_voltage __P((struct pccbb_softc *)); 111 STATIC int cbbprint __P((void *, const char *)); 112 113 static int cb_chipset __P((u_int32_t, int *)); 114 STATIC void pccbb_pcmcia_attach_setup __P((struct pccbb_softc *, 115 struct pcmciabus_attach_args *)); 116 #if 0 117 STATIC void pccbb_pcmcia_attach_card __P((struct pcic_handle *)); 118 STATIC void pccbb_pcmcia_detach_card __P((struct pcic_handle *, int)); 119 STATIC void pccbb_pcmcia_deactivate_card __P((struct pcic_handle *)); 120 #endif 121 122 STATIC int pccbb_ctrl __P((cardbus_chipset_tag_t, int)); 123 STATIC int pccbb_power __P((cardbus_chipset_tag_t, int)); 124 STATIC int pccbb_cardenable __P((struct pccbb_softc * sc, int function)); 125 #if !rbus 126 static int pccbb_io_open __P((cardbus_chipset_tag_t, int, u_int32_t, 127 u_int32_t)); 128 static int pccbb_io_close __P((cardbus_chipset_tag_t, int)); 129 static int pccbb_mem_open __P((cardbus_chipset_tag_t, int, u_int32_t, 130 u_int32_t)); 131 static int pccbb_mem_close __P((cardbus_chipset_tag_t, int)); 132 #endif /* !rbus */ 133 static void *pccbb_intr_establish __P((cardbus_chipset_tag_t, int irq, 134 int level, int (*ih) (void *), void *sc)); 135 static void pccbb_intr_disestablish __P((cardbus_chipset_tag_t ct, void *ih)); 136 137 static cardbustag_t pccbb_make_tag __P((cardbus_chipset_tag_t, int, int, int)); 138 static void pccbb_free_tag __P((cardbus_chipset_tag_t, cardbustag_t)); 139 static cardbusreg_t pccbb_conf_read __P((cardbus_chipset_tag_t, cardbustag_t, 140 int)); 141 static void pccbb_conf_write __P((cardbus_chipset_tag_t, cardbustag_t, int, 142 cardbusreg_t)); 143 static void pccbb_chipinit __P((struct pccbb_softc *)); 144 145 STATIC int pccbb_pcmcia_mem_alloc __P((pcmcia_chipset_handle_t, bus_size_t, 146 struct pcmcia_mem_handle *)); 147 STATIC void pccbb_pcmcia_mem_free __P((pcmcia_chipset_handle_t, 148 struct pcmcia_mem_handle *)); 149 STATIC int pccbb_pcmcia_mem_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 150 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *)); 151 STATIC void pccbb_pcmcia_mem_unmap __P((pcmcia_chipset_handle_t, int)); 152 STATIC int pccbb_pcmcia_io_alloc __P((pcmcia_chipset_handle_t, bus_addr_t, 153 bus_size_t, bus_size_t, struct pcmcia_io_handle *)); 154 STATIC void pccbb_pcmcia_io_free __P((pcmcia_chipset_handle_t, 155 struct pcmcia_io_handle *)); 156 STATIC int pccbb_pcmcia_io_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 157 bus_size_t, struct pcmcia_io_handle *, int *)); 158 STATIC void pccbb_pcmcia_io_unmap __P((pcmcia_chipset_handle_t, int)); 159 STATIC void *pccbb_pcmcia_intr_establish __P((pcmcia_chipset_handle_t, 160 struct pcmcia_function *, int, int (*)(void *), void *)); 161 STATIC void pccbb_pcmcia_intr_disestablish __P((pcmcia_chipset_handle_t, 162 void *)); 163 STATIC void pccbb_pcmcia_socket_enable __P((pcmcia_chipset_handle_t)); 164 STATIC void pccbb_pcmcia_socket_disable __P((pcmcia_chipset_handle_t)); 165 STATIC int pccbb_pcmcia_card_detect __P((pcmcia_chipset_handle_t pch)); 166 167 static void pccbb_pcmcia_do_io_map __P((struct pcic_handle *, int)); 168 static void pccbb_pcmcia_wait_ready __P((struct pcic_handle *)); 169 static void pccbb_pcmcia_do_mem_map __P((struct pcic_handle *, int)); 170 static void pccbb_powerhook __P((int, void *)); 171 172 /* bus-space allocation and disallocation functions */ 173 #if rbus 174 175 static int pccbb_rbus_cb_space_alloc __P((cardbus_chipset_tag_t, rbus_tag_t, 176 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 177 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp)); 178 static int pccbb_rbus_cb_space_free __P((cardbus_chipset_tag_t, rbus_tag_t, 179 bus_space_handle_t, bus_size_t)); 180 181 #endif /* rbus */ 182 183 #if rbus 184 185 static int pccbb_open_win __P((struct pccbb_softc *, bus_space_tag_t, 186 bus_addr_t, bus_size_t, bus_space_handle_t, int flags)); 187 static int pccbb_close_win __P((struct pccbb_softc *, bus_space_tag_t, 188 bus_space_handle_t, bus_size_t)); 189 static int pccbb_winlist_insert __P((struct pccbb_win_chain **, bus_addr_t, 190 bus_size_t, bus_space_handle_t, int)); 191 static int pccbb_winlist_delete __P((struct pccbb_win_chain **, 192 bus_space_handle_t, bus_size_t)); 193 static void pccbb_winset __P((bus_addr_t align, struct pccbb_softc *, 194 bus_space_tag_t)); 195 void pccbb_winlist_show(struct pccbb_win_chain *); 196 197 #endif /* rbus */ 198 199 /* for config_defer */ 200 static void pccbb_pci_callback __P((struct device *)); 201 202 #if defined SHOW_REGS 203 static void cb_show_regs __P((pci_chipset_tag_t pc, pcitag_t tag, 204 bus_space_tag_t memt, bus_space_handle_t memh)); 205 #endif 206 207 struct cfattach cbb_pci_ca = { 208 sizeof(struct pccbb_softc), pcicbbmatch, pccbbattach 209 }; 210 211 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 212 pccbb_pcmcia_mem_alloc, 213 pccbb_pcmcia_mem_free, 214 pccbb_pcmcia_mem_map, 215 pccbb_pcmcia_mem_unmap, 216 pccbb_pcmcia_io_alloc, 217 pccbb_pcmcia_io_free, 218 pccbb_pcmcia_io_map, 219 pccbb_pcmcia_io_unmap, 220 pccbb_pcmcia_intr_establish, 221 pccbb_pcmcia_intr_disestablish, 222 pccbb_pcmcia_socket_enable, 223 pccbb_pcmcia_socket_disable, 224 pccbb_pcmcia_card_detect 225 }; 226 227 #if rbus 228 static struct cardbus_functions pccbb_funcs = { 229 pccbb_rbus_cb_space_alloc, 230 pccbb_rbus_cb_space_free, 231 pccbb_intr_establish, 232 pccbb_intr_disestablish, 233 pccbb_ctrl, 234 pccbb_power, 235 pccbb_make_tag, 236 pccbb_free_tag, 237 pccbb_conf_read, 238 pccbb_conf_write, 239 }; 240 #else 241 static struct cardbus_functions pccbb_funcs = { 242 pccbb_ctrl, 243 pccbb_power, 244 pccbb_mem_open, 245 pccbb_mem_close, 246 pccbb_io_open, 247 pccbb_io_close, 248 pccbb_intr_establish, 249 pccbb_intr_disestablish, 250 pccbb_make_tag, 251 pccbb_conf_read, 252 pccbb_conf_write, 253 }; 254 #endif 255 256 int 257 pcicbbmatch(parent, match, aux) 258 struct device *parent; 259 #ifdef __BROKEN_INDIRECT_CONFIG 260 void *match; 261 #else 262 struct cfdata *match; 263 #endif 264 void *aux; 265 { 266 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 267 268 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 269 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 270 PCI_INTERFACE(pa->pa_class) == 0) { 271 return 1; 272 } 273 274 return 0; 275 } 276 277 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 278 | ((prod) << PCI_PRODUCT_SHIFT)) 279 280 struct yenta_chipinfo { 281 pcireg_t yc_id; /* vendor tag | product tag */ 282 int yc_chiptype; 283 int yc_flags; 284 } yc_chipsets[] = { 285 /* Texas Instruments chips */ 286 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 287 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 288 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 289 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 290 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI12XX, 291 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 292 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 293 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 294 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 295 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 296 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 297 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 298 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI12XX, 299 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 300 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI12XX, 301 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 302 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 303 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 304 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 305 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 306 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI12XX, 307 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 308 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 309 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 310 311 /* Ricoh chips */ 312 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 313 PCCBB_PCMCIA_MEM_32}, 314 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 315 PCCBB_PCMCIA_MEM_32}, 316 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 317 PCCBB_PCMCIA_MEM_32}, 318 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 319 PCCBB_PCMCIA_MEM_32}, 320 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 321 PCCBB_PCMCIA_MEM_32}, 322 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 323 PCCBB_PCMCIA_MEM_32}, 324 325 /* Toshiba products */ 326 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 327 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 328 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 329 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 330 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 331 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 332 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 333 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 334 335 /* Cirrus Logic products */ 336 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 337 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 338 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 339 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 340 341 /* sentinel, or Generic chip */ 342 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 343 }; 344 345 static int 346 cb_chipset(pci_id, flagp) 347 u_int32_t pci_id; 348 int *flagp; 349 { 350 int loopend = sizeof(yc_chipsets) / sizeof(yc_chipsets[0]); 351 struct yenta_chipinfo *ycp, *ycend; 352 353 ycend = yc_chipsets + loopend; 354 355 for (ycp = yc_chipsets; ycp < ycend && pci_id != ycp->yc_id; ++ycp); 356 357 if (ycp == ycend) { 358 /* not found -- point at sentinel */ 359 ycp = yc_chipsets + loopend - 1; 360 } 361 362 if (flagp != NULL) { 363 *flagp = ycp->yc_flags; 364 } 365 366 return ycp->yc_chiptype; 367 } 368 369 static void 370 pccbb_shutdown(void *arg) 371 { 372 struct pccbb_softc *sc = arg; 373 pcireg_t command; 374 375 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 376 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 377 0); 378 379 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 380 381 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 382 PCI_COMMAND_MASTER_ENABLE); 383 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 384 385 } 386 387 void 388 pccbbattach(parent, self, aux) 389 struct device *parent; 390 struct device *self; 391 void *aux; 392 { 393 struct pccbb_softc *sc = (void *)self; 394 struct pci_attach_args *pa = aux; 395 pci_chipset_tag_t pc = pa->pa_pc; 396 pcireg_t sock_base, busreg; 397 bus_addr_t sockbase; 398 char devinfo[256]; 399 int flags; 400 401 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 402 403 pci_devinfo(pa->pa_id, 0, 0, devinfo); 404 printf(": %s (rev. 0x%02x)", devinfo, PCI_REVISION(pa->pa_class)); 405 #ifdef CBB_DEBUG 406 printf(" (chipflags %x)", flags); 407 #endif 408 printf("\n"); 409 410 #if rbus 411 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 412 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 413 #endif /* rbus */ 414 415 sc->sc_base_memh = 0; 416 417 /* 418 * MAP socket registers and ExCA registers on memory-space 419 * When no valid address is set on socket base registers (on pci 420 * config space), get it not polite way. 421 */ 422 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 423 424 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 425 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 426 /* The address must be valid. */ 427 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 428 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL)) { 429 printf("%s: can't map socket base address 0x%x\n", 430 sc->sc_dev.dv_xname, sock_base); 431 /* 432 * I think it's funny: socket base registers must be 433 * mapped on memory space, but ... 434 */ 435 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 436 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 437 NULL)) { 438 printf("%s: can't map socket base address" 439 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 440 sockbase); 441 /* give up... allocate reg space via rbus. */ 442 sc->sc_base_memh = 0; 443 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 444 } 445 } else { 446 DPRINTF(("%s: socket base address 0x%lx\n", 447 sc->sc_dev.dv_xname, sockbase)); 448 } 449 } 450 451 sc->sc_mem_start = 0; /* XXX */ 452 sc->sc_mem_end = 0xffffffff; /* XXX */ 453 454 /* 455 * When interrupt isn't routed correctly, give up probing cbb and do 456 * not kill pcic-compatible port. 457 */ 458 if ((0 == pa->pa_intrline) || (255 == pa->pa_intrline)) { 459 printf("%s: NOT USED because of unconfigured interrupt\n", 460 sc->sc_dev.dv_xname); 461 return; 462 } 463 464 /* 465 * When bus number isn't set correctly, give up using 32-bit CardBus 466 * mode. 467 */ 468 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 469 #if notyet 470 if (((busreg >> 8) & 0xff) == 0) { 471 printf("%s: CardBus support disabled because of unconfigured bus number\n", 472 sc->sc_dev.dv_xname); 473 flags |= PCCBB_PCMCIA_16BITONLY; 474 } 475 #endif 476 477 /* pccbb_machdep.c end */ 478 479 #if defined CBB_DEBUG 480 { 481 static char *intrname[5] = { "NON", "A", "B", "C", "D" }; 482 printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname, 483 intrname[pa->pa_intrpin], pa->pa_intrline); 484 } 485 #endif 486 487 /* setup softc */ 488 sc->sc_pc = pc; 489 sc->sc_iot = pa->pa_iot; 490 sc->sc_memt = pa->pa_memt; 491 sc->sc_dmat = pa->pa_dmat; 492 sc->sc_tag = pa->pa_tag; 493 sc->sc_function = pa->pa_function; 494 495 sc->sc_intrline = pa->pa_intrline; 496 sc->sc_intrtag = pa->pa_intrtag; 497 sc->sc_intrpin = pa->pa_intrpin; 498 499 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 500 501 shutdownhook_establish(pccbb_shutdown, sc); 502 503 #if __NetBSD_Version__ > 103060000 504 config_defer(self, pccbb_pci_callback); 505 #else 506 pccbb_pci_callback(self); 507 #endif 508 } 509 510 static void 511 pccbb_pci_callback(self) 512 struct device *self; 513 { 514 struct pccbb_softc *sc = (void *)self; 515 pci_chipset_tag_t pc = sc->sc_pc; 516 bus_space_tag_t base_memt; 517 bus_space_handle_t base_memh; 518 u_int32_t maskreg; 519 pci_intr_handle_t ih; 520 const char *intrstr = NULL; 521 bus_addr_t sockbase; 522 struct cbslot_attach_args cba; 523 struct pcmciabus_attach_args paa; 524 struct cardslot_attach_args caa; 525 struct cardslot_softc *csc; 526 527 if (0 == sc->sc_base_memh) { 528 /* The socket registers aren't mapped correctly. */ 529 #if rbus 530 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 531 (sc->sc_chipset == CB_RX5C47X 532 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 533 0, &sockbase, &sc->sc_base_memh)) { 534 return; 535 } 536 sc->sc_base_memt = sc->sc_memt; 537 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 538 DPRINTF(("%s: CardBus resister address 0x%lx -> 0x%x\n", 539 sc->sc_dev.dv_xname, sockbase, pci_conf_read(pc, sc->sc_tag, 540 PCI_SOCKBASE))); 541 #else 542 sc->sc_base_memt = sc->sc_memt; 543 #if !defined CBB_PCI_BASE 544 #define CBB_PCI_BASE 0x20000000 545 #endif 546 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 547 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 548 /* cannot allocate memory space */ 549 return; 550 } 551 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 552 DPRINTF(("%s: CardBus resister address 0x%x -> 0x%x\n", 553 sc->sc_dev.dv_xname, sock_base, pci_conf_read(pc, 554 sc->sc_tag, PCI_SOCKBASE))); 555 #endif 556 } 557 558 /* bus bridge initialisation */ 559 pccbb_chipinit(sc); 560 561 base_memt = sc->sc_base_memt; /* socket regs memory tag */ 562 base_memh = sc->sc_base_memh; /* socket regs memory handle */ 563 564 /* CSC Interrupt: Card detect interrupt on */ 565 maskreg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 566 maskreg |= CB_SOCKET_MASK_CD; /* Card detect intr is turned on. */ 567 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, maskreg); 568 /* reset interrupt */ 569 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, 570 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT)); 571 572 /* Map and establish the interrupt. */ 573 if (pci_intr_map(pc, sc->sc_intrtag, sc->sc_intrpin, 574 sc->sc_intrline, &ih)) { 575 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 576 return; 577 } 578 intrstr = pci_intr_string(pc, ih); 579 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 580 581 if (sc->sc_ih == NULL) { 582 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 583 if (intrstr != NULL) { 584 printf(" at %s", intrstr); 585 } 586 printf("\n"); 587 return; 588 } 589 590 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 591 powerhook_establish(pccbb_powerhook, sc); 592 593 { 594 u_int32_t sockstat = 595 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 596 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 597 sc->sc_flags |= CBB_CARDEXIST; 598 } 599 } 600 601 /* 602 * attach cardbus 603 */ 604 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 605 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 606 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 607 608 /* initialise cbslot_attach */ 609 cba.cba_busname = "cardbus"; 610 cba.cba_iot = sc->sc_iot; 611 cba.cba_memt = sc->sc_memt; 612 cba.cba_dmat = sc->sc_dmat; 613 cba.cba_function = 0; 614 cba.cba_bus = (busreg >> 8) & 0x0ff; 615 cba.cba_cc = (void *)sc; 616 cba.cba_cf = &pccbb_funcs; 617 cba.cba_intrline = sc->sc_intrline; 618 619 #if rbus 620 cba.cba_rbus_iot = sc->sc_rbus_iot; 621 cba.cba_rbus_memt = sc->sc_rbus_memt; 622 #endif 623 624 cba.cba_cacheline = PCI_CACHELINE(bhlc); 625 cba.cba_lattimer = PCI_CB_LATENCY(busreg); 626 627 printf("%s: cacheline 0x%x lattimer 0x%x\n", 628 sc->sc_dev.dv_xname, cba.cba_cacheline, cba.cba_lattimer); 629 printf("%s: bhlc 0x%x lscp 0x%x\n", sc->sc_dev.dv_xname, bhlc, 630 busreg); 631 #if defined SHOW_REGS 632 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 633 sc->sc_base_memh); 634 #endif 635 } 636 637 pccbb_pcmcia_attach_setup(sc, &paa); 638 caa.caa_cb_attach = NULL; 639 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 640 caa.caa_cb_attach = &cba; 641 } 642 caa.caa_16_attach = &paa; 643 caa.caa_ph = &sc->sc_pcmcia_h; 644 645 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 646 DPRINTF(("pccbbattach: found cardslot\n")); 647 sc->sc_csc = csc; 648 } 649 650 return; 651 } 652 653 static void 654 pccbb_chipinit(sc) 655 struct pccbb_softc *sc; 656 { 657 pci_chipset_tag_t pc = sc->sc_pc; 658 pcitag_t tag = sc->sc_tag; 659 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 660 bus_space_handle_t base_memh = sc->sc_base_memh; 661 pcireg_t cbctrl; 662 663 /* 664 * Set PCI command reg. 665 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 666 */ 667 { 668 pcireg_t command = 669 pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 670 671 /* I believe it is harmless. */ 672 command |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 673 PCI_COMMAND_MASTER_ENABLE); 674 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, command); 675 } 676 677 /* 678 * Set CardBus latency timer 679 */ 680 { 681 pcireg_t pci_lscp = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 682 if (PCI_CB_LATENCY(pci_lscp) < 0x20) { 683 pci_lscp &= 684 ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 685 pci_lscp |= (0x20 << PCI_CB_LATENCY_SHIFT); 686 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, pci_lscp); 687 } 688 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 689 PCI_CB_LATENCY(pci_lscp), pci_conf_read(pc, tag, 690 PCI_CB_LSCP_REG))); 691 } 692 693 /* 694 * Set PCI latency timer 695 */ 696 { 697 pcireg_t pci_bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG); 698 if (PCI_LATTIMER(pci_bhlc) < 0x10) { 699 pci_bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 700 pci_bhlc |= (0x10 << PCI_LATTIMER_SHIFT); 701 pci_conf_write(pc, tag, PCI_BHLC_REG, pci_bhlc); 702 } 703 DPRINTF(("PCI latency timer 0x%x (%x)\n", 704 PCI_LATTIMER(pci_bhlc), pci_conf_read(pc, tag, 705 PCI_BHLC_REG))); 706 } 707 708 /* disable Legacy IO */ 709 710 switch (sc->sc_chipset) { 711 case CB_RX5C46X: /* fallthrogh */ 712 #if 0 713 case CB_RX5C47X: 714 #endif 715 /* 716 * The legacy pcic io-port on Ricoh CardBus bridges cannot be 717 * disabled by substituting 0 into PCI_LEGACY register. Ricoh 718 * CardBus bridges have special bits on Bridge control reg (addr 719 * 0x3e on PCI config space). 720 */ 721 { 722 pcireg_t bcri = pci_conf_read(pc, tag, PCI_BCR_INTR); 723 bcri &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 724 pci_conf_write(pc, tag, PCI_BCR_INTR, bcri); 725 } 726 break; 727 default: 728 /* XXX: I don't know proper way to kill Legacy IO properly. */ 729 pci_conf_write(pc, tag, PCI_LEGACY, 0x0); 730 break; 731 } 732 733 /* 734 * Interrupt routing: use PCI interrupt 735 */ 736 { 737 u_int32_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 738 bcr &= ~CB_BCR_INTR_IREQ_ENABLE; /* use PCI Intr */ 739 bcr |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 740 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 741 } 742 743 if (CB_TI113X == sc->sc_chipset) { 744 cbctrl = pci_conf_read(pc, tag, PCI_CBCTRL); 745 if (0 == sc->sc_function) { 746 cbctrl |= PCI113X_CBCTRL_PCI_IRQ_ENA; 747 } 748 /* XXX: bug in PCI113X */ 749 cbctrl |= PCI113X_CBCTRL_PCI_IRQ_ENA; 750 /* CSC intr enable */ 751 cbctrl |= PCI113X_CBCTRL_PCI_CSC; 752 /* functional intr prohibit */ 753 cbctrl &= ~PCI113X_CBCTRL_PCI_INTR; 754 /* prohibit ISA routing */ 755 cbctrl &= ~PCI113X_CBCTRL_INT_MASK; 756 pci_conf_write(pc, tag, PCI_CBCTRL, cbctrl); 757 758 /* 759 * set ExCA regs: PCI113X required to be set bit 4 at Interrupt 760 * and General Register, which is IRQ Enable Register, and 761 * clear bit 3:0 to zero in order to route CSC interrupt to 762 * PCI interrupt pin. 763 */ 764 bus_space_write_1(base_memt, base_memh, 0x0803, 0x10); 765 /* set ExCA regs: prohibit all pcmcia-style CSC intr. */ 766 bus_space_write_1(base_memt, base_memh, 0x0805, 0x00); 767 #if 1 768 DPRINTF(("ExCA regs:")); 769 DPRINTF((" 0x803: %02x", bus_space_read_1(base_memt, base_memh, 770 0x803))); 771 DPRINTF((" 0x805: %02x", bus_space_read_1(base_memt, base_memh, 772 0x805))); 773 DPRINTF((" 0x81e: %02x\n", bus_space_read_1(base_memt, 774 base_memh, 0x81e))); 775 #endif 776 } else if (sc->sc_chipset == CB_TI12XX) { 777 cbctrl = pci_conf_read(pc, tag, PCI_CBCTRL); 778 cbctrl &= ~PCI12XX_CBCTRL_INT_MASK; /* intr routing reset */ 779 pci_conf_write(pc, tag, PCI_CBCTRL, cbctrl); 780 /* 781 * set ExCA regs: PCI12XX required to be set bit 4 at Interrupt 782 * and General Register, which is IRQ Enable Register, and clear 783 * bit 3:0 to zero in order to route CSC interrupt to PCI 784 * interrupt pin. 785 */ 786 bus_space_write_1(base_memt, base_memh, 0x0803, 0x10); 787 /* set ExCA regs: prohibit all pcmcia-style CSC intr. */ 788 bus_space_write_1(base_memt, base_memh, 0x0805, 0x00); 789 } else if (sc->sc_chipset == CB_TOPIC95B) { 790 cardbusreg_t sock_ctrl, slot_ctrl; 791 792 sock_ctrl = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 793 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, 794 sock_ctrl | TOPIC_SOCKET_CTRL_SCR_IRQSEL); 795 796 slot_ctrl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 797 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 798 sc->sc_dev.dv_xname, slot_ctrl)); 799 slot_ctrl |= 800 (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 801 TOPIC_SLOT_CTRL_ID_LOCK); 802 slot_ctrl |= TOPIC_SLOT_CTRL_CARDBUS; 803 slot_ctrl &= ~TOPIC_SLOT_CTRL_SWDETECT; 804 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slot_ctrl); 805 DPRINTF(("0x%x\n", slot_ctrl)); 806 } 807 808 /* close all memory and io windows */ 809 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 810 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 811 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 812 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 813 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 814 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 815 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 816 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 817 818 return; 819 } 820 821 /* 822 * attach pccard bus 823 */ 824 STATIC void 825 pccbb_pcmcia_attach_setup(sc, paa) 826 struct pccbb_softc *sc; 827 struct pcmciabus_attach_args *paa; 828 { 829 struct pcic_handle *ph = &sc->sc_pcmcia_h; 830 #if rbus 831 rbus_tag_t rb; 832 #endif 833 834 /* initialise pcmcia part in pccbb_softc */ 835 ph->ph_parent = (struct device *)sc; 836 ph->sock = sc->sc_function; 837 ph->flags = 0; 838 ph->shutdown = 0; 839 ph->ih_irq = sc->sc_intrline; 840 ph->ph_bus_t = sc->sc_base_memt; 841 ph->ph_bus_h = sc->sc_base_memh; 842 ph->ph_read = pccbb_pcmcia_read; 843 ph->ph_write = pccbb_pcmcia_write; 844 sc->sc_pct = &pccbb_pcmcia_funcs; 845 846 Pcic_write(ph, PCIC_CSC_INTR, 0); 847 Pcic_read(ph, PCIC_CSC); 848 849 /* initialise pcmcia bus attachment */ 850 paa->paa_busname = "pcmcia"; 851 paa->pct = sc->sc_pct; 852 paa->pch = ph; 853 paa->iobase = 0; /* I don't use them */ 854 paa->iosize = 0; 855 #if rbus 856 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 857 paa->iobase = rb->rb_start + rb->rb_offset; 858 paa->iosize = rb->rb_end - rb->rb_start; 859 #endif 860 861 return; 862 } 863 864 #if 0 865 STATIC void 866 pccbb_pcmcia_attach_card(ph) 867 struct pcic_handle *ph; 868 { 869 if (ph->flags & PCIC_FLAG_CARDP) { 870 panic("pccbb_pcmcia_attach_card: already attached"); 871 } 872 873 /* call the MI attach function */ 874 pcmcia_card_attach(ph->pcmcia); 875 876 ph->flags |= PCIC_FLAG_CARDP; 877 } 878 879 STATIC void 880 pccbb_pcmcia_detach_card(ph, flags) 881 struct pcic_handle *ph; 882 int flags; 883 { 884 if (!(ph->flags & PCIC_FLAG_CARDP)) { 885 panic("pccbb_pcmcia_detach_card: already detached"); 886 } 887 888 ph->flags &= ~PCIC_FLAG_CARDP; 889 890 /* call the MI detach function */ 891 pcmcia_card_detach(ph->pcmcia, flags); 892 } 893 #endif 894 895 /* 896 * int pccbbintr(arg) 897 * void *arg; 898 * This routine handles the interrupt from Yenta PCI-CardBus bridge 899 * itself. 900 */ 901 int 902 pccbbintr(arg) 903 void *arg; 904 { 905 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 906 u_int32_t sockevent; 907 bus_space_tag_t memt = sc->sc_base_memt; 908 bus_space_handle_t memh = sc->sc_base_memh; 909 u_int32_t sockstate; 910 911 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 912 if (0 == sockevent) { 913 /* This intr is not for me: it may be for my child devices. */ 914 return pccbbintr_function(sc); 915 } else { 916 /* reset bit */ 917 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 918 } 919 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 920 921 if (sockevent & CB_SOCKET_EVENT_CD) { 922 if (CB_SOCKET_STAT_CD == (sockstate & CB_SOCKET_STAT_CD)) { 923 /* A card should be removed. */ 924 if (sc->sc_flags & CBB_CARDEXIST) { 925 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 926 sockevent)); 927 DPRINTF((" card removed, 0x%08x\n", sockstate)); 928 sc->sc_flags &= ~CBB_CARDEXIST; 929 if (sc-> 930 sc_csc->sc_status & CARDSLOT_STATUS_CARD_16) 931 { 932 #if 0 933 struct pcic_handle *ph = 934 &sc->sc_pcmcia_h; 935 936 pcmcia_card_deactivate(ph->pcmcia); 937 pccbb_pcmcia_socket_disable(ph); 938 pccbb_pcmcia_detach_card(ph, 939 DETACH_FORCE); 940 #endif 941 cardslot_event_throw(sc->sc_csc, 942 CARDSLOT_EVENT_REMOVAL_16); 943 } else if (sc-> 944 sc_csc->sc_status & CARDSLOT_STATUS_CARD_CB) 945 { 946 /* Cardbus intr removed */ 947 cardslot_event_throw(sc->sc_csc, 948 CARDSLOT_EVENT_REMOVAL_CB); 949 } 950 } 951 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD)) { 952 if (sc->sc_flags & CBB_INSERTING) { 953 untimeout(pci113x_insert, sc); 954 } 955 timeout(pci113x_insert, sc, hz / 10); 956 sc->sc_flags |= CBB_INSERTING; 957 } 958 } else { 959 DPRINTF(("%s: sockevent = %b\n", 960 sc->sc_dev.dv_xname, sockevent, PCCBB_SOCKEVENT_BITS)); 961 DPRINTF(("%s: sockstate = %b\n", 962 sc->sc_dev.dv_xname, sockstate, PCCBB_SOCKSTATE_BITS)); 963 } 964 965 return 1; 966 } 967 968 /* 969 * static int pccbbintr_function(struct pccbb_softc *sc) 970 * 971 * This function calls each interrupt handler registered at the 972 * bridge. The interrupt handlers are called in registerd order. 973 */ 974 static int 975 pccbbintr_function(sc) 976 struct pccbb_softc *sc; 977 { 978 int retval = 0, val; 979 struct pccbb_intrhand_list *pil; 980 981 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 982 val = (*pil->pil_func) (pil->pil_arg); 983 retval = retval == 1 ? 1 : 984 retval == 0 ? val : val != 0 ? val : retval; 985 } 986 987 return retval; 988 } 989 990 static void 991 pci113x_insert(arg) 992 void *arg; 993 { 994 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 995 u_int32_t sockevent, sockstate; 996 997 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 998 CB_SOCKET_EVENT); 999 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1000 CB_SOCKET_STAT); 1001 1002 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1003 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1004 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1005 sc->sc_flags |= CBB_CARDEXIST; 1006 /* call pccard intterupt handler here */ 1007 if (sockstate & CB_SOCKET_STAT_16BIT) { 1008 /* 16-bit card found */ 1009 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1010 cardslot_event_throw(sc->sc_csc, 1011 CARDSLOT_EVENT_INSERTION_16); 1012 } else if (sockstate & CB_SOCKET_STAT_CB) { 1013 /* cardbus card fuond */ 1014 /* cardbus_attach_card(sc->sc_csc); */ 1015 cardslot_event_throw(sc->sc_csc, 1016 CARDSLOT_EVENT_INSERTION_CB); 1017 } else { 1018 /* who are you? */ 1019 } 1020 } else { 1021 timeout(pci113x_insert, sc, hz / 10); 1022 } 1023 } 1024 1025 #define PCCBB_PCMCIA_OFFSET 0x800 1026 static u_int8_t 1027 pccbb_pcmcia_read(ph, reg) 1028 struct pcic_handle *ph; 1029 int reg; 1030 { 1031 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1032 PCCBB_PCMCIA_OFFSET + reg); 1033 } 1034 1035 static void 1036 pccbb_pcmcia_write(ph, reg, val) 1037 struct pcic_handle *ph; 1038 int reg; 1039 u_int8_t val; 1040 { 1041 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1042 val); 1043 } 1044 1045 /* 1046 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1047 */ 1048 STATIC int 1049 pccbb_ctrl(ct, command) 1050 cardbus_chipset_tag_t ct; 1051 int command; 1052 { 1053 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1054 1055 switch (command) { 1056 case CARDBUS_CD: 1057 if (2 == pccbb_detect_card(sc)) { 1058 int retval = 0; 1059 int status = cb_detect_voltage(sc); 1060 if (PCCARD_VCC_5V & status) { 1061 retval |= CARDBUS_5V_CARD; 1062 } 1063 if (PCCARD_VCC_3V & status) { 1064 retval |= CARDBUS_3V_CARD; 1065 } 1066 if (PCCARD_VCC_XV & status) { 1067 retval |= CARDBUS_XV_CARD; 1068 } 1069 if (PCCARD_VCC_YV & status) { 1070 retval |= CARDBUS_YV_CARD; 1071 } 1072 return retval; 1073 } else { 1074 return 0; 1075 } 1076 break; 1077 case CARDBUS_RESET: 1078 return cb_reset(sc); 1079 break; 1080 case CARDBUS_IO_ENABLE: /* fallthrough */ 1081 case CARDBUS_IO_DISABLE: /* fallthrough */ 1082 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1083 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1084 case CARDBUS_BM_ENABLE: /* fallthrough */ 1085 case CARDBUS_BM_DISABLE: /* fallthrough */ 1086 return pccbb_cardenable(sc, command); 1087 break; 1088 } 1089 1090 return 0; 1091 } 1092 1093 /* 1094 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1095 * This function returns true when it succeeds and returns false when 1096 * it fails. 1097 */ 1098 STATIC int 1099 pccbb_power(ct, command) 1100 cardbus_chipset_tag_t ct; 1101 int command; 1102 { 1103 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1104 1105 u_int32_t status, sock_ctrl; 1106 bus_space_tag_t memt = sc->sc_base_memt; 1107 bus_space_handle_t memh = sc->sc_base_memh; 1108 1109 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1110 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1111 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1112 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1113 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1114 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1115 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1116 "UNKNOWN", 1117 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1118 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1119 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1120 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1121 "UNKNOWN", command)); 1122 1123 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1124 sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1125 1126 switch (command & CARDBUS_VCCMASK) { 1127 case CARDBUS_VCC_UC: 1128 break; 1129 case CARDBUS_VCC_5V: 1130 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1131 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1132 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1133 } else { 1134 printf("%s: BAD voltage request: no 5 V card\n", 1135 sc->sc_dev.dv_xname); 1136 } 1137 break; 1138 case CARDBUS_VCC_3V: 1139 if (CB_SOCKET_STAT_3VCARD & status) { 1140 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1141 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1142 } else { 1143 printf("%s: BAD voltage request: no 3.3 V card\n", 1144 sc->sc_dev.dv_xname); 1145 } 1146 break; 1147 case CARDBUS_VCC_0V: 1148 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1149 break; 1150 default: 1151 return 0; /* power NEVER changed */ 1152 break; 1153 } 1154 1155 switch (command & CARDBUS_VPPMASK) { 1156 case CARDBUS_VPP_UC: 1157 break; 1158 case CARDBUS_VPP_0V: 1159 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1160 break; 1161 case CARDBUS_VPP_VCC: 1162 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1163 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1164 break; 1165 case CARDBUS_VPP_12V: 1166 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1167 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1168 break; 1169 } 1170 1171 #if 0 1172 DPRINTF(("sock_ctrl: %x\n", sock_ctrl)); 1173 #endif 1174 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1175 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1176 1177 delay(20 * 1000); /* wait 20 ms: Vcc setup time */ 1178 /* 1179 * XXX delay 200 ms: though the standard defines that the Vcc set-up 1180 * time is 20 ms, some PC-Card bridge requires longer duration. 1181 */ 1182 delay(200 * 1000); 1183 1184 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1185 printf 1186 ("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1187 sc->sc_dev.dv_xname, sock_ctrl, status); 1188 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1189 (command & CARDBUS_VCCMASK) == 1190 CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : (command & 1191 CARDBUS_VCCMASK) == 1192 CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : (command & 1193 CARDBUS_VCCMASK) == 1194 CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : (command & 1195 CARDBUS_VCCMASK) == 1196 CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : (command & 1197 CARDBUS_VCCMASK) == 1198 CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : (command & 1199 CARDBUS_VCCMASK) == 1200 CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : "UNKNOWN", 1201 (command & CARDBUS_VPPMASK) == 1202 CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : (command & 1203 CARDBUS_VPPMASK) == 1204 CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : (command & 1205 CARDBUS_VPPMASK) == 1206 CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : (command & 1207 CARDBUS_VPPMASK) == 1208 CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : "UNKNOWN", command)); 1209 #if 0 1210 if (command == (CARDBUS_VCC_0V | CARDBUS_VPP_0V)) { 1211 u_int32_t force = 1212 bus_space_read_4(memt, memh, CB_SOCKET_FORCE); 1213 /* Reset Bad Vcc request */ 1214 force &= ~CB_SOCKET_FORCE_BADVCC; 1215 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, force); 1216 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1217 CB_SOCKET_STAT)); 1218 return 1; 1219 } 1220 #endif 1221 return 0; 1222 } 1223 return 1; /* power changed correctly */ 1224 } 1225 1226 #if defined CB_PCMCIA_POLL 1227 struct cb_poll_str { 1228 void *arg; 1229 int (*func) __P((void *)); 1230 int level; 1231 pccard_chipset_tag_t ct; 1232 int count; 1233 }; 1234 1235 static struct cb_poll_str cb_poll[10]; 1236 static int cb_poll_n = 0; 1237 1238 static void cb_pcmcia_poll __P((void *arg)); 1239 1240 static void 1241 cb_pcmcia_poll(arg) 1242 void *arg; 1243 { 1244 struct cb_poll_str *poll = arg; 1245 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1246 struct pccbb_softc *sc = psc->cpc_parent; 1247 int s; 1248 u_int32_t spsr; /* socket present-state reg */ 1249 1250 timeout(cb_pcmcia_poll, arg, hz / 10); 1251 switch (poll->level) { 1252 case IPL_NET: 1253 s = splnet(); 1254 break; 1255 case IPL_BIO: 1256 s = splbio(); 1257 break; 1258 case IPL_TTY: /* fallthrough */ 1259 default: 1260 s = spltty(); 1261 break; 1262 } 1263 1264 spsr = 1265 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1266 CB_SOCKET_STAT); 1267 1268 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1269 if (!(spsr & 0x40)) { /* CINT low */ 1270 #else 1271 if (1) { 1272 #endif 1273 if ((*poll->func) (poll->arg) == 1) { 1274 ++poll->count; 1275 printf("intr: reported from poller, 0x%x\n", spsr); 1276 #if defined LEVEL2 1277 } else { 1278 printf("intr: miss! 0x%x\n", spsr); 1279 #endif 1280 } 1281 } 1282 splx(s); 1283 } 1284 #endif /* defined CB_PCMCIA_POLL */ 1285 1286 /* 1287 * static int pccbb_detect_card(struct pccbb_softc *sc) 1288 * return value: 0 if no card exists. 1289 * 1 if 16-bit card exists. 1290 * 2 if cardbus card exists. 1291 */ 1292 static int 1293 pccbb_detect_card(sc) 1294 struct pccbb_softc *sc; 1295 { 1296 bus_space_handle_t base_memh = sc->sc_base_memh; 1297 bus_space_tag_t base_memt = sc->sc_base_memt; 1298 u_int32_t sockstat = 1299 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1300 int retval = 0; 1301 1302 /* CD1 and CD2 asserted */ 1303 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1304 /* card must be present */ 1305 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1306 /* NOTACARD DEASSERTED */ 1307 if (CB_SOCKET_STAT_CB & sockstat) { 1308 /* CardBus mode */ 1309 retval = 2; 1310 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1311 /* 16-bit mode */ 1312 retval = 1; 1313 } 1314 } 1315 } 1316 return retval; 1317 } 1318 1319 /* 1320 * STATIC int cb_reset(struct pccbb_softc *sc) 1321 * This function resets CardBus card. 1322 */ 1323 STATIC int 1324 cb_reset(sc) 1325 struct pccbb_softc *sc; 1326 { 1327 /* 1328 * Reset Assert at least 20 ms 1329 * Some machines request longer duration. 1330 */ 1331 int reset_duration = 1332 (sc->sc_chipset == CB_RX5C47X ? 400 * 1000 : 40 * 1000); 1333 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1334 1335 bcr |= (0x40 << 16); /* Reset bit Assert (bit 6 at 0x3E) */ 1336 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1337 delay(reset_duration); 1338 1339 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1340 bcr &= ~(0x40 << 16); /* Reset bit Deassert (bit 6 at 0x3E) */ 1341 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1342 delay(reset_duration); 1343 } 1344 /* No card found on the slot. Keep Reset. */ 1345 return 1; 1346 } 1347 1348 /* 1349 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1350 * This function detect card Voltage. 1351 */ 1352 STATIC int 1353 cb_detect_voltage(sc) 1354 struct pccbb_softc *sc; 1355 { 1356 u_int32_t psr; /* socket present-state reg */ 1357 bus_space_tag_t iot = sc->sc_base_memt; 1358 bus_space_handle_t ioh = sc->sc_base_memh; 1359 int vol = PCCARD_VCC_UKN; /* set 0 */ 1360 1361 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1362 1363 if (0x400u & psr) { 1364 vol |= PCCARD_VCC_5V; 1365 } 1366 if (0x800u & psr) { 1367 vol |= PCCARD_VCC_3V; 1368 } 1369 1370 return vol; 1371 } 1372 1373 STATIC int 1374 cbbprint(aux, pcic) 1375 void *aux; 1376 const char *pcic; 1377 { 1378 /* 1379 struct cbslot_attach_args *cba = aux; 1380 1381 if (cba->cba_slot >= 0) { 1382 printf(" slot %d", cba->cba_slot); 1383 } 1384 */ 1385 return UNCONF; 1386 } 1387 1388 /* 1389 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1390 * This function enables and disables the card 1391 */ 1392 STATIC int 1393 pccbb_cardenable(sc, function) 1394 struct pccbb_softc *sc; 1395 int function; 1396 { 1397 u_int32_t command = 1398 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1399 1400 DPRINTF(("pccbb_cardenable:")); 1401 switch (function) { 1402 case CARDBUS_IO_ENABLE: 1403 command |= PCI_COMMAND_IO_ENABLE; 1404 break; 1405 case CARDBUS_IO_DISABLE: 1406 command &= ~PCI_COMMAND_IO_ENABLE; 1407 break; 1408 case CARDBUS_MEM_ENABLE: 1409 command |= PCI_COMMAND_MEM_ENABLE; 1410 break; 1411 case CARDBUS_MEM_DISABLE: 1412 command &= ~PCI_COMMAND_MEM_ENABLE; 1413 break; 1414 case CARDBUS_BM_ENABLE: 1415 command |= PCI_COMMAND_MASTER_ENABLE; 1416 break; 1417 case CARDBUS_BM_DISABLE: 1418 command &= ~PCI_COMMAND_MASTER_ENABLE; 1419 break; 1420 default: 1421 return 0; 1422 } 1423 1424 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1425 DPRINTF((" command reg 0x%x\n", command)); 1426 return 1; 1427 } 1428 1429 #if !rbus 1430 /* 1431 * int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1432 */ 1433 static int 1434 pccbb_io_open(ct, win, start, end) 1435 cardbus_chipset_tag_t ct; 1436 int win; 1437 u_int32_t start, end; 1438 { 1439 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1440 int basereg; 1441 int limitreg; 1442 1443 if ((win < 0) || (win > 2)) { 1444 #if defined DIAGNOSTIC 1445 printf("cardbus_io_open: window out of range %d\n", win); 1446 #endif 1447 return 0; 1448 } 1449 1450 basereg = win * 8 + 0x2c; 1451 limitreg = win * 8 + 0x30; 1452 1453 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1454 start, basereg, end, limitreg)); 1455 1456 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1457 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1458 return 1; 1459 } 1460 1461 /* 1462 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1463 */ 1464 static int 1465 pccbb_io_close(ct, win) 1466 cardbus_chipset_tag_t ct; 1467 int win; 1468 { 1469 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1470 int basereg; 1471 int limitreg; 1472 1473 if ((win < 0) || (win > 2)) { 1474 #if defined DIAGNOSTIC 1475 printf("cardbus_io_close: window out of range %d\n", win); 1476 #endif 1477 return 0; 1478 } 1479 1480 basereg = win * 8 + 0x2c; 1481 limitreg = win * 8 + 0x30; 1482 1483 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1484 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1485 return 1; 1486 } 1487 1488 /* 1489 * int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1490 */ 1491 static int 1492 pccbb_mem_open(ct, win, start, end) 1493 cardbus_chipset_tag_t ct; 1494 int win; 1495 u_int32_t start, end; 1496 { 1497 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1498 int basereg; 1499 int limitreg; 1500 1501 if ((win < 0) || (win > 2)) { 1502 #if defined DIAGNOSTIC 1503 printf("cardbus_mem_open: window out of range %d\n", win); 1504 #endif 1505 return 0; 1506 } 1507 1508 basereg = win * 8 + 0x1c; 1509 limitreg = win * 8 + 0x20; 1510 1511 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1512 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1513 return 1; 1514 } 1515 1516 /* 1517 * int pccbb_mem_close(cardbus_chipset_tag_t, int) 1518 */ 1519 static int 1520 pccbb_mem_close(ct, win) 1521 cardbus_chipset_tag_t ct; 1522 int win; 1523 { 1524 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1525 int basereg; 1526 int limitreg; 1527 1528 if ((win < 0) || (win > 2)) { 1529 #if defined DIAGNOSTIC 1530 printf("cardbus_mem_close: window out of range %d\n", win); 1531 #endif 1532 return 0; 1533 } 1534 1535 basereg = win * 8 + 0x1c; 1536 limitreg = win * 8 + 0x20; 1537 1538 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1539 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1540 return 1; 1541 } 1542 #endif 1543 1544 /* 1545 * static void *pccbb_intr_establish(cardbus_chipset_tag_t ct, 1546 * int irq, 1547 * int level, 1548 * int (* func) __P((void *)), 1549 * void *arg) 1550 * 1551 * This function registers an interrupt handler at the bridge, in 1552 * order not to call the interrput handlers of child devices when 1553 * a card-deletion interrput occurs. 1554 * 1555 * The arguments irq and level are not used. 1556 */ 1557 static void * 1558 pccbb_intr_establish(ct, irq, level, func, arg) 1559 cardbus_chipset_tag_t ct; 1560 int irq, level; 1561 int (*func) __P((void *)); 1562 void *arg; 1563 { 1564 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1565 struct pccbb_intrhand_list *pil, *newpil; 1566 1567 if (sc->sc_pil == NULL) { 1568 /* initialise bridge intr routing */ 1569 1570 switch (sc->sc_chipset) { 1571 case CB_TI113X: 1572 { 1573 pcireg_t cbctrl = 1574 pci_conf_read(sc->sc_pc, sc->sc_tag, 1575 PCI_CBCTRL); 1576 /* functional intr enabled */ 1577 cbctrl |= PCI113X_CBCTRL_PCI_INTR; 1578 pci_conf_write(sc->sc_pc, sc->sc_tag, 1579 PCI_CBCTRL, cbctrl); 1580 break; 1581 } 1582 default: 1583 break; 1584 } 1585 } 1586 1587 /* 1588 * Allocate a room for interrut handler structure. 1589 */ 1590 if (NULL == (newpil = 1591 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1592 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1593 return NULL; 1594 } 1595 1596 newpil->pil_func = func; 1597 newpil->pil_arg = arg; 1598 newpil->pil_next = NULL; 1599 1600 if (sc->sc_pil == NULL) { 1601 sc->sc_pil = newpil; 1602 } else { 1603 for (pil = sc->sc_pil; pil->pil_next != NULL; 1604 pil = pil->pil_next); 1605 pil->pil_next = newpil; 1606 } 1607 1608 return newpil; 1609 } 1610 1611 /* 1612 * static void *pccbb_intr_disestablish(cardbus_chipset_tag_t ct, 1613 * void *ih) 1614 * 1615 * This function removes an interrupt handler pointed by ih. 1616 */ 1617 static void 1618 pccbb_intr_disestablish(ct, ih) 1619 cardbus_chipset_tag_t ct; 1620 void *ih; 1621 { 1622 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1623 struct pccbb_intrhand_list *pil, **pil_prev; 1624 1625 pil_prev = &sc->sc_pil; 1626 1627 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 1628 if (pil == ih) { 1629 *pil_prev = pil->pil_next; 1630 free(pil, M_DEVBUF); 1631 break; 1632 } 1633 pil_prev = &pil->pil_next; 1634 } 1635 1636 if (sc->sc_pil == NULL) { 1637 /* No interrupt handlers */ 1638 1639 switch (sc->sc_chipset) { 1640 case CB_TI113X: 1641 { 1642 pcireg_t cbctrl = 1643 pci_conf_read(sc->sc_pc, sc->sc_tag, 1644 PCI_CBCTRL); 1645 /* functional intr disabled */ 1646 cbctrl &= ~PCI113X_CBCTRL_PCI_INTR; 1647 pci_conf_write(sc->sc_pc, sc->sc_tag, 1648 PCI_CBCTRL, cbctrl); 1649 break; 1650 } 1651 default: 1652 break; 1653 } 1654 } 1655 } 1656 1657 #if defined SHOW_REGS 1658 static void 1659 cb_show_regs(pc, tag, memt, memh) 1660 pci_chipset_tag_t pc; 1661 pcitag_t tag; 1662 bus_space_tag_t memt; 1663 bus_space_handle_t memh; 1664 { 1665 int i; 1666 printf("PCI config regs:"); 1667 for (i = 0; i < 0x50; i += 4) { 1668 if (i % 16 == 0) { 1669 printf("\n 0x%02x:", i); 1670 } 1671 printf(" %08x", pci_conf_read(pc, tag, i)); 1672 } 1673 for (i = 0x80; i < 0xb0; i += 4) { 1674 if (i % 16 == 0) { 1675 printf("\n 0x%02x:", i); 1676 } 1677 printf(" %08x", pci_conf_read(pc, tag, i)); 1678 } 1679 1680 if (memh == 0) { 1681 printf("\n"); 1682 return; 1683 } 1684 1685 printf("\nsocket regs:"); 1686 for (i = 0; i <= 0x10; i += 0x04) { 1687 printf(" %08x", bus_space_read_4(memt, memh, i)); 1688 } 1689 printf("\nExCA regs:"); 1690 for (i = 0; i < 0x08; ++i) { 1691 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1692 } 1693 printf("\n"); 1694 return; 1695 } 1696 #endif 1697 1698 /* 1699 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1700 * int busno, int devno, int function) 1701 * This is the function to make a tag to access config space of 1702 * a CardBus Card. It works same as pci_conf_read. 1703 */ 1704 static cardbustag_t 1705 pccbb_make_tag(cc, busno, devno, function) 1706 cardbus_chipset_tag_t cc; 1707 int busno, devno, function; 1708 { 1709 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1710 1711 return pci_make_tag(sc->sc_pc, busno, devno, function); 1712 } 1713 1714 static void 1715 pccbb_free_tag(cc, tag) 1716 cardbus_chipset_tag_t cc; 1717 cardbustag_t tag; 1718 { 1719 } 1720 1721 /* 1722 * static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t cc, 1723 * cardbustag_t tag, int offset) 1724 * This is the function to read the config space of a CardBus Card. 1725 * It works same as pci_conf_read. 1726 */ 1727 static cardbusreg_t 1728 pccbb_conf_read(cc, tag, offset) 1729 cardbus_chipset_tag_t cc; 1730 cardbustag_t tag; 1731 int offset; /* register offset */ 1732 { 1733 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1734 1735 return pci_conf_read(sc->sc_pc, tag, offset); 1736 } 1737 1738 /* 1739 * static void pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, 1740 * int offs, cardbusreg_t val) 1741 * This is the function to write the config space of a CardBus Card. 1742 * It works same as pci_conf_write. 1743 */ 1744 static void 1745 pccbb_conf_write(cc, tag, reg, val) 1746 cardbus_chipset_tag_t cc; 1747 cardbustag_t tag; 1748 int reg; /* register offset */ 1749 cardbusreg_t val; 1750 { 1751 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1752 1753 pci_conf_write(sc->sc_pc, tag, reg, val); 1754 } 1755 1756 #if 0 1757 STATIC int 1758 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1759 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 1760 int speed, int flags, 1761 bus_space_handle_t * iohp) 1762 #endif 1763 /* 1764 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1765 * bus_addr_t start, bus_size_t size, 1766 * bus_size_t align, 1767 * struct pcmcia_io_handle *pcihp 1768 * 1769 * This function only allocates I/O region for pccard. This function 1770 * never maps the allcated region to pccard I/O area. 1771 * 1772 * XXX: The interface of this function is not very good, I believe. 1773 */ 1774 STATIC int 1775 pccbb_pcmcia_io_alloc(pch, start, size, align, pcihp) 1776 pcmcia_chipset_handle_t pch; 1777 bus_addr_t start; /* start address */ 1778 bus_size_t size; 1779 bus_size_t align; 1780 struct pcmcia_io_handle *pcihp; 1781 { 1782 struct pcic_handle *ph = (struct pcic_handle *)pch; 1783 bus_addr_t ioaddr; 1784 int flags = 0; 1785 bus_space_tag_t iot; 1786 bus_space_handle_t ioh; 1787 #if rbus 1788 rbus_tag_t rb; 1789 #endif 1790 if (align == 0) { 1791 align = size; /* XXX: funny??? */ 1792 } 1793 1794 /* 1795 * Allocate some arbitrary I/O space. 1796 */ 1797 1798 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 1799 1800 #if rbus 1801 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 1802 /* XXX: I assume all card decode lower 10 bits by its hardware */ 1803 if (rbus_space_alloc(rb, start, size, 0x3ff, align, 0, &ioaddr, &ioh)) { 1804 return 1; 1805 } 1806 #else 1807 if (start) { 1808 ioaddr = start; 1809 if (bus_space_map(iot, start, size, 0, &ioh)) { 1810 return 1; 1811 } 1812 DPRINTF(("pccbb_pcmcia_io_alloc map port %lx+%lx\n", 1813 (u_long) ioaddr, (u_long) size)); 1814 } else { 1815 flags |= PCMCIA_IO_ALLOCATED; 1816 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 1817 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 1818 size, align, 0, 0, &ioaddr, &ioh)) { 1819 /* No room be able to be get. */ 1820 return 1; 1821 } 1822 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 1823 (u_long) ioaddr, (u_long) size)); 1824 } 1825 #endif 1826 1827 pcihp->iot = iot; 1828 pcihp->ioh = ioh; 1829 pcihp->addr = ioaddr; 1830 pcihp->size = size; 1831 pcihp->flags = flags; 1832 1833 return 0; 1834 } 1835 1836 /* 1837 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 1838 * struct pcmcia_io_handle *pcihp) 1839 * 1840 * This function only frees I/O region for pccard. 1841 * 1842 * XXX: The interface of this function is not very good, I believe. 1843 */ 1844 void 1845 pccbb_pcmcia_io_free(pch, pcihp) 1846 pcmcia_chipset_handle_t pch; 1847 struct pcmcia_io_handle *pcihp; 1848 { 1849 #if !rbus 1850 bus_space_tag_t iot = pcihp->iot; 1851 #endif 1852 bus_space_handle_t ioh = pcihp->ioh; 1853 bus_size_t size = pcihp->size; 1854 1855 #if rbus 1856 struct pccbb_softc *sc = 1857 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 1858 rbus_tag_t rb = sc->sc_rbus_iot; 1859 1860 rbus_space_free(rb, ioh, size, NULL); 1861 #else 1862 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 1863 bus_space_free(iot, ioh, size); 1864 else 1865 bus_space_unmap(iot, ioh, size); 1866 #endif 1867 } 1868 1869 /* 1870 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 1871 * bus_addr_t offset, bus_size_t size, 1872 * struct pcmcia_io_handle *pcihp, 1873 * int *windowp) 1874 * 1875 * This function maps the allocated I/O region to pccard. This function 1876 * never allocates any I/O region for pccard I/O area. I don't 1877 * understand why the original authors of pcmciabus separated alloc and 1878 * map. I believe the two must be unite. 1879 * 1880 * XXX: no wait timing control? 1881 */ 1882 int 1883 pccbb_pcmcia_io_map(pch, width, offset, size, pcihp, windowp) 1884 pcmcia_chipset_handle_t pch; 1885 int width; 1886 bus_addr_t offset; 1887 bus_size_t size; 1888 struct pcmcia_io_handle *pcihp; 1889 int *windowp; 1890 { 1891 struct pcic_handle *ph = (struct pcic_handle *)pch; 1892 bus_addr_t ioaddr = pcihp->addr + offset; 1893 int i, win; 1894 #if defined CBB_DEBUG 1895 static char *width_names[] = { "dynamic", "io8", "io16" }; 1896 #endif 1897 1898 /* Sanity check I/O handle. */ 1899 1900 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 1901 panic("pccbb_pcmcia_io_map iot is bogus"); 1902 } 1903 1904 /* XXX Sanity check offset/size. */ 1905 1906 win = -1; 1907 for (i = 0; i < PCIC_IO_WINS; i++) { 1908 if ((ph->ioalloc & (1 << i)) == 0) { 1909 win = i; 1910 ph->ioalloc |= (1 << i); 1911 break; 1912 } 1913 } 1914 1915 if (win == -1) { 1916 return 1; 1917 } 1918 1919 *windowp = win; 1920 1921 /* XXX this is pretty gross */ 1922 1923 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 1924 win, width_names[width], (u_long) ioaddr, (u_long) size)); 1925 1926 /* XXX wtf is this doing here? */ 1927 1928 #if 0 1929 printf(" port 0x%lx", (u_long) ioaddr); 1930 if (size > 1) { 1931 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 1932 } 1933 #endif 1934 1935 ph->io[win].addr = ioaddr; 1936 ph->io[win].size = size; 1937 ph->io[win].width = width; 1938 1939 /* actual dirty register-value changing in the function below. */ 1940 pccbb_pcmcia_do_io_map(ph, win); 1941 1942 return 0; 1943 } 1944 1945 /* 1946 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 1947 * 1948 * This function changes register-value to map I/O region for pccard. 1949 */ 1950 static void 1951 pccbb_pcmcia_do_io_map(ph, win) 1952 struct pcic_handle *ph; 1953 int win; 1954 { 1955 static u_int8_t pcic_iowidth[3] = { 1956 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 1957 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 1958 PCIC_IOCTL_IO0_DATASIZE_8BIT, 1959 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 1960 PCIC_IOCTL_IO0_DATASIZE_16BIT, 1961 }; 1962 1963 #define PCIC_SIA_START_LOW 0 1964 #define PCIC_SIA_START_HIGH 1 1965 #define PCIC_SIA_STOP_LOW 2 1966 #define PCIC_SIA_STOP_HIGH 3 1967 1968 int regbase_win = 0x8 + win * 0x04; 1969 u_int8_t ioctl, enable; 1970 1971 DPRINTF( 1972 ("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx width %d\n", 1973 win, (long)ph->io[win].addr, (long)ph->io[win].size, 1974 ph->io[win].width * 8)); 1975 1976 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 1977 ph->io[win].addr & 0xff); 1978 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 1979 (ph->io[win].addr >> 8) & 0xff); 1980 1981 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 1982 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 1983 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 1984 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 1985 1986 ioctl = Pcic_read(ph, PCIC_IOCTL); 1987 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 1988 switch (win) { 1989 case 0: 1990 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 1991 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 1992 PCIC_IOCTL_IO0_DATASIZE_MASK); 1993 ioctl |= pcic_iowidth[ph->io[win].width]; 1994 enable |= PCIC_ADDRWIN_ENABLE_IO0; 1995 break; 1996 case 1: 1997 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 1998 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 1999 PCIC_IOCTL_IO1_DATASIZE_MASK); 2000 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2001 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2002 break; 2003 } 2004 Pcic_write(ph, PCIC_IOCTL, ioctl); 2005 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2006 #if defined CBB_DEBUG 2007 { 2008 u_int8_t start_low = 2009 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2010 u_int8_t start_high = 2011 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2012 u_int8_t stop_low = 2013 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2014 u_int8_t stop_high = 2015 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2016 printf 2017 (" start %02x %02x, stop %02x %02x, ioctl %02x enable %02x\n", 2018 start_low, start_high, stop_low, stop_high, ioctl, enable); 2019 } 2020 #endif 2021 } 2022 2023 /* 2024 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2025 * 2026 * This function unmapss I/O region. No return value. 2027 */ 2028 STATIC void 2029 pccbb_pcmcia_io_unmap(pch, win) 2030 pcmcia_chipset_handle_t pch; 2031 int win; 2032 { 2033 struct pcic_handle *ph = (struct pcic_handle *)pch; 2034 int reg; 2035 2036 if (win >= PCIC_IO_WINS || win < 0) { 2037 panic("pccbb_pcmcia_io_unmap: window out of range"); 2038 } 2039 2040 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2041 switch (win) { 2042 case 0: 2043 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2044 break; 2045 case 1: 2046 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2047 break; 2048 } 2049 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2050 2051 ph->ioalloc &= ~(1 << win); 2052 } 2053 2054 /* 2055 * static void pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 2056 * 2057 * This function enables the card. All information is stored in 2058 * the first argument, pcmcia_chipset_handle_t. 2059 */ 2060 static void 2061 pccbb_pcmcia_wait_ready(ph) 2062 struct pcic_handle *ph; 2063 { 2064 int i; 2065 2066 DPRINTF(("pccbb_pcmcia_wait_ready: status 0x%02x\n", 2067 Pcic_read(ph, PCIC_IF_STATUS))); 2068 2069 for (i = 0; i < 10000; i++) { 2070 if (Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) { 2071 return; 2072 } 2073 delay(500); 2074 #ifdef CBB_DEBUG 2075 if ((i > 5000) && (i % 100 == 99)) 2076 printf("."); 2077 #endif 2078 } 2079 2080 #ifdef DIAGNOSTIC 2081 printf("pcic_wait_ready: ready never happened, status = %02x\n", 2082 Pcic_read(ph, PCIC_IF_STATUS)); 2083 #endif 2084 } 2085 2086 /* 2087 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2088 * 2089 * This function enables the card. All information is stored in 2090 * the first argument, pcmcia_chipset_handle_t. 2091 */ 2092 STATIC void 2093 pccbb_pcmcia_socket_enable(pch) 2094 pcmcia_chipset_handle_t pch; 2095 { 2096 struct pcic_handle *ph = (struct pcic_handle *)pch; 2097 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2098 int cardtype, win; 2099 u_int8_t power, intr; 2100 pcireg_t spsr; 2101 int voltage; 2102 #define PCIC_INTR_PCI PCIC_INTR_ENABLE 2103 2104 /* this bit is mostly stolen from pcic_attach_card */ 2105 2106 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2107 2108 /* get card Vcc info */ 2109 2110 spsr = 2111 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2112 CB_SOCKET_STAT); 2113 if (spsr & CB_SOCKET_STAT_5VCARD) { 2114 DPRINTF(("5V card\n")); 2115 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2116 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2117 DPRINTF(("3V card\n")); 2118 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2119 } else { 2120 printf("?V card, 0x%x\n", spsr); /* XXX */ 2121 return; 2122 } 2123 2124 /* assert reset bit */ 2125 intr = Pcic_read(ph, PCIC_INTR); 2126 intr &= ~(PCIC_INTR_RESET | PCIC_INTR_ENABLE | PCIC_INTR_CARDTYPE_MASK); 2127 Pcic_write(ph, PCIC_INTR, intr); 2128 2129 /* disable socket i/o: negate output enable bit */ 2130 2131 power = Pcic_read(ph, PCIC_PWRCTL); 2132 power &= ~PCIC_PWRCTL_OE; 2133 Pcic_write(ph, PCIC_PWRCTL, power); 2134 2135 /* power down the socket to reset it, clear the card reset pin */ 2136 2137 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2138 2139 /* 2140 * wait 200ms until power fails (Tpf). Then, wait 100ms since 2141 * we are changing Vcc (Toff). 2142 */ 2143 /* delay(300*1000); too much */ 2144 2145 /* power up the socket */ 2146 pccbb_power(sc, voltage); 2147 2148 /* 2149 * wait 100ms until power raise (Tpr) and 20ms to become 2150 * stable (Tsu(Vcc)). 2151 * 2152 * some machines require some more time to be settled 2153 * (another 200ms is added here). 2154 */ 2155 /* delay((100 + 20 + 200)*1000); too much */ 2156 2157 power = Pcic_read(ph, PCIC_PWRCTL); 2158 power |= PCIC_PWRCTL_OE; 2159 Pcic_write(ph, PCIC_PWRCTL, power); 2160 2161 /* 2162 * hold RESET at least 10us. 2163 */ 2164 delay(10); 2165 delay(2 * 1000); /* XXX: TI1130 requires it. */ 2166 delay(20 * 1000); /* XXX: TI1130 requires it. */ 2167 2168 /* clear the reset flag */ 2169 2170 intr |= PCIC_INTR_RESET; 2171 Pcic_write(ph, PCIC_INTR, intr); 2172 2173 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 2174 2175 delay(20000); 2176 2177 /* wait for the chip to finish initializing */ 2178 2179 pccbb_pcmcia_wait_ready(ph); 2180 2181 /* zero out the address windows */ 2182 2183 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2184 2185 /* set the card type */ 2186 2187 cardtype = pcmcia_card_gettype(ph->pcmcia); 2188 2189 intr |= PCIC_INTR_PCI; 2190 intr |= ((cardtype == PCMCIA_IFTYPE_IO) ? 2191 PCIC_INTR_CARDTYPE_IO : PCIC_INTR_CARDTYPE_MEM); 2192 Pcic_write(ph, PCIC_INTR, intr); 2193 2194 DPRINTF(("%s: pccbb_pcmcia_socket_enable %02x cardtype %s %02x\n", 2195 ph->ph_parent->dv_xname, ph->sock, 2196 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2197 2198 /* reinstall all the memory and io mappings */ 2199 2200 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2201 if (ph->memalloc & (1 << win)) { 2202 pccbb_pcmcia_do_mem_map(ph, win); 2203 } 2204 } 2205 2206 for (win = 0; win < PCIC_IO_WINS; ++win) { 2207 if (ph->ioalloc & (1 << win)) { 2208 pccbb_pcmcia_do_io_map(ph, win); 2209 } 2210 } 2211 } 2212 2213 /* 2214 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2215 * 2216 * This function disables the card. All information is stored in 2217 * the first argument, pcmcia_chipset_handle_t. 2218 */ 2219 STATIC void 2220 pccbb_pcmcia_socket_disable(pch) 2221 pcmcia_chipset_handle_t pch; 2222 { 2223 struct pcic_handle *ph = (struct pcic_handle *)pch; 2224 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2225 u_int8_t power, intr; 2226 2227 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2228 2229 /* reset signal asserting... */ 2230 2231 intr = Pcic_read(ph, PCIC_INTR); 2232 intr &= ~(PCIC_INTR_RESET | PCIC_INTR_ENABLE | PCIC_INTR_CARDTYPE_MASK); 2233 Pcic_write(ph, PCIC_INTR, intr); 2234 delay(2 * 1000); 2235 2236 /* power down the socket */ 2237 power = Pcic_read(ph, PCIC_PWRCTL); 2238 power &= ~PCIC_PWRCTL_OE; 2239 Pcic_write(ph, PCIC_PWRCTL, power); 2240 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2241 /* 2242 * wait 300ms until power fails (Tpf). 2243 */ 2244 delay(300 * 1000); 2245 } 2246 2247 /* 2248 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2249 * 2250 * This function detects whether a card is in the slot or not. 2251 * If a card is inserted, return 1. Otherwise, return 0. 2252 */ 2253 STATIC int 2254 pccbb_pcmcia_card_detect(pch) 2255 pcmcia_chipset_handle_t pch; 2256 { 2257 struct pcic_handle *ph = (struct pcic_handle *)pch; 2258 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2259 2260 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2261 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2262 } 2263 2264 #if 0 2265 STATIC int 2266 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2267 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2268 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2269 #endif 2270 /* 2271 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2272 * bus_size_t size, 2273 * struct pcmcia_mem_handle *pcmhp) 2274 * 2275 * This function only allocates memory region for pccard. This 2276 * function never maps the allcated region to pccard memory area. 2277 * 2278 * XXX: Why the argument of start address is not in? 2279 */ 2280 STATIC int 2281 pccbb_pcmcia_mem_alloc(pch, size, pcmhp) 2282 pcmcia_chipset_handle_t pch; 2283 bus_size_t size; 2284 struct pcmcia_mem_handle *pcmhp; 2285 { 2286 struct pcic_handle *ph = (struct pcic_handle *)pch; 2287 bus_space_handle_t memh; 2288 bus_addr_t addr; 2289 bus_size_t sizepg; 2290 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2291 #if rbus 2292 rbus_tag_t rb; 2293 #endif 2294 2295 /* out of sc->memh, allocate as many pages as necessary */ 2296 2297 /* convert size to PCIC pages */ 2298 /* 2299 * This is not enough; when the requested region is on the page 2300 * boundaries, this may calculate wrong result. 2301 */ 2302 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2303 #if 0 2304 if (sizepg > PCIC_MAX_MEM_PAGES) { 2305 return 1; 2306 } 2307 #endif 2308 2309 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2310 return 1; 2311 } 2312 2313 addr = 0; /* XXX gcc -Wuninitialized */ 2314 2315 #if rbus 2316 rb = sc->sc_rbus_memt; 2317 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2318 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2319 &addr, &memh)) { 2320 return 1; 2321 } 2322 #else 2323 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2324 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2325 0, /* boundary */ 2326 0, /* flags */ 2327 &addr, &memh)) { 2328 return 1; 2329 } 2330 #endif 2331 2332 DPRINTF( 2333 ("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, realsize 0x%lx\n", 2334 addr, size, sizepg * PCIC_MEM_PAGESIZE)); 2335 2336 pcmhp->memt = sc->sc_memt; 2337 pcmhp->memh = memh; 2338 pcmhp->addr = addr; 2339 pcmhp->size = size; 2340 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2341 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2342 pcmhp->mhandle = 0; 2343 /* No offset??? Funny. */ 2344 2345 return 0; 2346 } 2347 2348 /* 2349 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2350 * struct pcmcia_mem_handle *pcmhp) 2351 * 2352 * This function release the memory space allocated by the fuction 2353 * pccbb_pcmcia_mem_alloc(). 2354 */ 2355 STATIC void 2356 pccbb_pcmcia_mem_free(pch, pcmhp) 2357 pcmcia_chipset_handle_t pch; 2358 struct pcmcia_mem_handle *pcmhp; 2359 { 2360 #if rbus 2361 struct pcic_handle *ph = (struct pcic_handle *)pch; 2362 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2363 2364 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2365 #else 2366 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2367 #endif 2368 } 2369 2370 /* 2371 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2372 * 2373 * This function release the memory space allocated by the fuction 2374 * pccbb_pcmcia_mem_alloc(). 2375 */ 2376 STATIC void 2377 pccbb_pcmcia_do_mem_map(ph, win) 2378 struct pcic_handle *ph; 2379 int win; 2380 { 2381 int regbase_win; 2382 bus_addr_t phys_addr; 2383 bus_addr_t phys_end; 2384 2385 #define PCIC_SMM_START_LOW 0 2386 #define PCIC_SMM_START_HIGH 1 2387 #define PCIC_SMM_STOP_LOW 2 2388 #define PCIC_SMM_STOP_HIGH 3 2389 #define PCIC_CMA_LOW 4 2390 #define PCIC_CMA_HIGH 5 2391 2392 u_int8_t start_low, start_high = 0; 2393 u_int8_t stop_low, stop_high; 2394 u_int8_t off_low, off_high; 2395 u_int8_t mem_window; 2396 int reg; 2397 2398 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2399 int mem8 = 2400 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2401 || (kind == PCMCIA_MEM_ATTR); 2402 2403 regbase_win = 0x10 + win * 0x08; 2404 2405 phys_addr = ph->mem[win].addr; 2406 phys_end = phys_addr + ph->mem[win].size; 2407 2408 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2409 phys_addr, phys_end, ph->mem[win].offset)); 2410 2411 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2412 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2413 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2414 2415 /* bit 19:12 */ 2416 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2417 /* bit 23:20 and bit 7 on */ 2418 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2419 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2420 /* bit 31:24, for 32-bit address */ 2421 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2422 2423 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2424 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2425 2426 if (((struct pccbb_softc *)ph-> 2427 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2428 Pcic_write(ph, 0x40 + win, mem_window); 2429 } 2430 2431 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2432 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2433 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2434 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2435 2436 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2437 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2438 2439 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2440 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2441 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2442 | ((kind == PCMCIA_MEM_ATTR) ? 2443 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2444 2445 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2446 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2447 2448 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2449 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2450 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2451 2452 #if defined CBB_DEBUG 2453 { 2454 int r1, r2, r3, r4, r5, r6, r7 = 0; 2455 2456 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2457 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2458 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2459 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2460 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2461 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2462 if (((struct pccbb_softc *)(ph-> 2463 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2464 r7 = Pcic_read(ph, 0x40 + win); 2465 } 2466 2467 DPRINTF(("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2468 "%02x%02x", win, r1, r2, r3, r4, r5, r6)); 2469 if (((struct pccbb_softc *)(ph-> 2470 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2471 DPRINTF((" %02x", r7)); 2472 } 2473 DPRINTF(("\n")); 2474 } 2475 #endif 2476 } 2477 2478 /* 2479 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2480 * bus_addr_t card_addr, bus_size_t size, 2481 * struct pcmcia_mem_handle *pcmhp, 2482 * bus_addr_t *offsetp, int *windowp) 2483 * 2484 * This function maps memory space allocated by the fuction 2485 * pccbb_pcmcia_mem_alloc(). 2486 */ 2487 STATIC int 2488 pccbb_pcmcia_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 2489 pcmcia_chipset_handle_t pch; 2490 int kind; 2491 bus_addr_t card_addr; 2492 bus_size_t size; 2493 struct pcmcia_mem_handle *pcmhp; 2494 bus_addr_t *offsetp; 2495 int *windowp; 2496 { 2497 struct pcic_handle *ph = (struct pcic_handle *)pch; 2498 bus_addr_t busaddr; 2499 long card_offset; 2500 int win; 2501 2502 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2503 if ((ph->memalloc & (1 << win)) == 0) { 2504 ph->memalloc |= (1 << win); 2505 break; 2506 } 2507 } 2508 2509 if (win == PCIC_MEM_WINS) { 2510 return 1; 2511 } 2512 2513 *windowp = win; 2514 2515 /* XXX this is pretty gross */ 2516 2517 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2518 panic("pccbb_pcmcia_mem_map memt is bogus"); 2519 } 2520 2521 busaddr = pcmhp->addr; 2522 2523 /* 2524 * compute the address offset to the pcmcia address space for the 2525 * pcic. this is intentionally signed. The masks and shifts below 2526 * will cause TRT to happen in the pcic registers. Deal with making 2527 * sure the address is aligned, and return the alignment offset. 2528 */ 2529 2530 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2531 card_addr -= *offsetp; 2532 2533 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2534 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2535 (u_long) card_addr)); 2536 2537 /* 2538 * include the offset in the size, and decrement size by one, since 2539 * the hw wants start/stop 2540 */ 2541 size += *offsetp - 1; 2542 2543 card_offset = (((long)card_addr) - ((long)busaddr)); 2544 2545 ph->mem[win].addr = busaddr; 2546 ph->mem[win].size = size; 2547 ph->mem[win].offset = card_offset; 2548 ph->mem[win].kind = kind; 2549 2550 pccbb_pcmcia_do_mem_map(ph, win); 2551 2552 return 0; 2553 } 2554 2555 /* 2556 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2557 * int window) 2558 * 2559 * This function unmaps memory space which mapped by the fuction 2560 * pccbb_pcmcia_mem_map(). 2561 */ 2562 STATIC void 2563 pccbb_pcmcia_mem_unmap(pch, window) 2564 pcmcia_chipset_handle_t pch; 2565 int window; 2566 { 2567 struct pcic_handle *ph = (struct pcic_handle *)pch; 2568 int reg; 2569 2570 if (window >= PCIC_MEM_WINS) { 2571 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2572 } 2573 2574 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2575 reg &= ~(1 << window); 2576 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2577 2578 ph->memalloc &= ~(1 << window); 2579 } 2580 2581 #if defined PCCBB_PCMCIA_POLL 2582 struct pccbb_poll_str { 2583 void *arg; 2584 int (*func) __P((void *)); 2585 int level; 2586 struct pcic_handle *ph; 2587 int count; 2588 int num; 2589 }; 2590 2591 static struct pccbb_poll_str pccbb_poll[10]; 2592 static int pccbb_poll_n = 0; 2593 2594 static void pccbb_pcmcia_poll __P((void *arg)); 2595 2596 static void 2597 pccbb_pcmcia_poll(arg) 2598 void *arg; 2599 { 2600 struct pccbb_poll_str *poll = arg; 2601 struct pcic_handle *ph = poll->ph; 2602 struct pccbb_softc *sc = ph->sc; 2603 int s; 2604 u_int32_t spsr; /* socket present-state reg */ 2605 2606 timeout(pccbb_pcmcia_poll, arg, hz * 2); 2607 switch (poll->level) { 2608 case IPL_NET: 2609 s = splnet(); 2610 break; 2611 case IPL_BIO: 2612 s = splbio(); 2613 break; 2614 case IPL_TTY: /* fallthrough */ 2615 default: 2616 s = spltty(); 2617 break; 2618 } 2619 2620 spsr = 2621 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2622 CB_SOCKET_STAT); 2623 2624 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2625 if (!(spsr & 0x40)) /* CINT low */ 2626 #else 2627 if (1) 2628 #endif 2629 { 2630 if ((*poll->func) (poll->arg) > 0) { 2631 ++poll->count; 2632 // printf("intr: reported from poller, 0x%x\n", spsr); 2633 #if defined LEVEL2 2634 } else { 2635 printf("intr: miss! 0x%x\n", spsr); 2636 #endif 2637 } 2638 } 2639 splx(s); 2640 } 2641 #endif /* defined CB_PCMCIA_POLL */ 2642 2643 /* 2644 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2645 * struct pcmcia_function *pf, 2646 * int ipl, 2647 * int (*func)(void *), 2648 * void *arg); 2649 * 2650 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2651 */ 2652 STATIC void * 2653 pccbb_pcmcia_intr_establish(pch, pf, ipl, func, arg) 2654 pcmcia_chipset_handle_t pch; 2655 struct pcmcia_function *pf; 2656 int ipl; 2657 int (*func) __P((void *)); 2658 void *arg; 2659 { 2660 struct pcic_handle *ph = (struct pcic_handle *)pch; 2661 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2662 pci_intr_handle_t handle; 2663 void *ih; 2664 2665 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2666 /* what should I do? */ 2667 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2668 DPRINTF( 2669 ("%s does not provide edge nor pulse interrupt\n", 2670 sc->sc_dev.dv_xname)); 2671 return NULL; 2672 } 2673 /* 2674 * XXX Noooooo! The interrupt flag must set properly!! 2675 * dumb pcmcia driver!! 2676 */ 2677 } 2678 2679 if (pci_intr_map(sc->sc_pc, sc->sc_intrtag, sc->sc_intrpin, 2680 sc->sc_intrline, &handle)) { 2681 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 2682 return NULL; 2683 } 2684 DPRINTF(("pccbb_pcmcia_intr_establish: line %d, handle %d\n", 2685 sc->sc_intrline, handle)); 2686 2687 if (NULL != (ih = 2688 pci_intr_establish(sc->sc_pc, handle, ipl, func, arg))) { 2689 u_int32_t cbctrl; 2690 2691 if ((CB_TI113X == sc->sc_chipset)) { 2692 cbctrl = 2693 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 2694 /* PCI functional intr req */ 2695 cbctrl |= PCI113X_CBCTRL_PCI_INTR; 2696 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, 2697 cbctrl); 2698 } 2699 } 2700 #if defined PCCBB_PCMCIA_POLL 2701 if (pccbb_poll_n < 10) { 2702 pccbb_poll[pccbb_poll_n].arg = arg; 2703 pccbb_poll[pccbb_poll_n].func = func; 2704 pccbb_poll[pccbb_poll_n].level = ipl; 2705 pccbb_poll[pccbb_poll_n].count = 0; 2706 pccbb_poll[pccbb_poll_n].num = pccbb_poll_n; 2707 pccbb_poll[pccbb_poll_n].ph = ph; 2708 timeout(pccbb_pcmcia_poll, &pccbb_poll[pccbb_poll_n++], hz * 2); 2709 printf("polling set\n"); 2710 } 2711 #endif 2712 #if defined SHOW_REGS 2713 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, sc->sc_base_memh); 2714 #endif 2715 2716 return ih; 2717 } 2718 2719 /* 2720 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2721 * void *ih) 2722 * 2723 * This function disables PC-Card interrupt. 2724 */ 2725 STATIC void 2726 pccbb_pcmcia_intr_disestablish(pch, ih) 2727 pcmcia_chipset_handle_t pch; 2728 void *ih; 2729 { 2730 struct pcic_handle *ph = (struct pcic_handle *)pch; 2731 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2732 2733 pci_intr_disestablish(sc->sc_pc, ih); 2734 } 2735 2736 #if rbus 2737 /* 2738 * static int 2739 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2740 * bus_addr_t addr, bus_size_t size, 2741 * bus_addr_t mask, bus_size_t align, 2742 * int flags, bus_addr_t *addrp; 2743 * bus_space_handle_t *bshp) 2744 * 2745 * This function allocates a portion of memory or io space for 2746 * clients. This function is called from CardBus card drivers. 2747 */ 2748 static int 2749 pccbb_rbus_cb_space_alloc(ct, rb, addr, size, mask, align, flags, addrp, bshp) 2750 cardbus_chipset_tag_t ct; 2751 rbus_tag_t rb; 2752 bus_addr_t addr; 2753 bus_size_t size; 2754 bus_addr_t mask; 2755 bus_size_t align; 2756 int flags; 2757 bus_addr_t *addrp; 2758 bus_space_handle_t *bshp; 2759 { 2760 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2761 2762 DPRINTF( 2763 ("pccbb_rbus_cb_space_alloc: adr %lx, size %lx, mask %lx, align %lx\n", 2764 addr, size, mask, align)); 2765 2766 if (align == 0) { 2767 align = size; 2768 } 2769 2770 if (rb->rb_bt == sc->sc_memt) { 2771 if (align < 16) { 2772 return 1; 2773 } 2774 } else if (rb->rb_bt == sc->sc_iot) { 2775 if (align < 4) { 2776 return 1; 2777 } 2778 } else { 2779 DPRINTF( 2780 ("pccbb_rbus_cb_space_alloc: Bus space tag %x is NOT used.\n", 2781 rb->rb_bt)); 2782 return 1; 2783 /* XXX: panic here? */ 2784 } 2785 2786 /* XXX: hack for avoiding ISA image */ 2787 if (mask < 0x3ff) { 2788 mask = 0x3ff; 2789 addr = 0x300; 2790 } 2791 2792 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 2793 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 2794 return 1; 2795 } 2796 2797 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 2798 2799 return 0; 2800 } 2801 2802 /* 2803 * static int 2804 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 2805 * bus_space_handle_t *bshp, bus_size_t size); 2806 * 2807 * This function is called from CardBus card drivers. 2808 */ 2809 static int 2810 pccbb_rbus_cb_space_free(ct, rb, bsh, size) 2811 cardbus_chipset_tag_t ct; 2812 rbus_tag_t rb; 2813 bus_space_handle_t bsh; 2814 bus_size_t size; 2815 { 2816 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2817 bus_space_tag_t bt = rb->rb_bt; 2818 2819 pccbb_close_win(sc, bt, bsh, size); 2820 2821 if (bt == sc->sc_memt) { 2822 } else if (bt == sc->sc_iot) { 2823 } else { 2824 return 1; 2825 /* XXX: panic here? */ 2826 } 2827 2828 return rbus_space_free(rb, bsh, size, NULL); 2829 } 2830 #endif /* rbus */ 2831 2832 #if rbus 2833 2834 static int 2835 pccbb_open_win(sc, bst, addr, size, bsh, flags) 2836 struct pccbb_softc *sc; 2837 bus_space_tag_t bst; 2838 bus_addr_t addr; 2839 bus_size_t size; 2840 bus_space_handle_t bsh; 2841 int flags; 2842 { 2843 struct pccbb_win_chain **top; 2844 bus_addr_t align; 2845 2846 top = &sc->sc_iowindow; 2847 align = 0x04; 2848 if (sc->sc_memt == bst) { 2849 top = &sc->sc_memwindow; 2850 align = 0x1000; 2851 DPRINTF(("using memory window, %x %x %x\n\n", 2852 sc->sc_iot, sc->sc_memt, bst)); 2853 } 2854 2855 if (pccbb_winlist_insert(top, addr, size, bsh, flags)) { 2856 printf("winlist insert fails:\n"); 2857 } 2858 pccbb_winset(align, sc, bst); 2859 2860 return 0; 2861 } 2862 2863 static int 2864 pccbb_close_win(sc, bst, bsh, size) 2865 struct pccbb_softc *sc; 2866 bus_space_tag_t bst; 2867 bus_space_handle_t bsh; 2868 bus_size_t size; 2869 { 2870 struct pccbb_win_chain **top; 2871 bus_addr_t align; 2872 2873 top = &sc->sc_iowindow; 2874 align = 0x04; 2875 if (sc->sc_memt == bst) { 2876 top = &sc->sc_memwindow; 2877 align = 0x1000; 2878 } 2879 2880 if (pccbb_winlist_delete(top, bsh, size)) { 2881 printf("winlist delete fails:\n"); 2882 } 2883 pccbb_winset(align, sc, bst); 2884 2885 return 0; 2886 } 2887 2888 static int 2889 pccbb_winlist_insert(top, start, size, bsh, flags) 2890 struct pccbb_win_chain **top; 2891 bus_addr_t start; 2892 bus_size_t size; 2893 bus_space_handle_t bsh; 2894 int flags; 2895 { 2896 struct pccbb_win_chain *chainp = *top; 2897 struct pccbb_win_chain *before = *top; 2898 struct pccbb_win_chain *elem; 2899 2900 if (*top == NULL) { 2901 if (NULL == (elem = 2902 (struct pccbb_win_chain *)malloc(sizeof(struct 2903 pccbb_win_chain), M_DEVBUF, M_NOWAIT))) { 2904 return 1; /* fail */ 2905 } 2906 2907 elem->wc_start = start; 2908 elem->wc_end = start + size - 1; 2909 elem->wc_handle = bsh; 2910 elem->wc_flags = flags; 2911 2912 *top = elem; 2913 elem->wc_next = NULL; 2914 return 0; 2915 } 2916 2917 for (; chainp && chainp->wc_start <= start; chainp = chainp->wc_next) { 2918 before = chainp; 2919 } 2920 2921 if (chainp != NULL) { 2922 if (chainp->wc_start < start + size) { 2923 printf("fatal! 0x%lx 0x%lx\n", chainp->wc_start, 2924 start + size); 2925 return 1; 2926 } 2927 } 2928 if ((before != *top) && (before->wc_end >= start)) { 2929 printf("fatal!! 0x%lx 0x%lx\n", before->wc_end, start); 2930 return 1; 2931 } 2932 2933 if (NULL == (elem = 2934 (struct pccbb_win_chain *)malloc(sizeof(struct pccbb_win_chain), 2935 M_DEVBUF, M_NOWAIT))) { 2936 return 1; /* fail */ 2937 } 2938 2939 elem->wc_start = start; 2940 elem->wc_end = start + size - 1; 2941 elem->wc_handle = bsh; 2942 elem->wc_flags = flags; 2943 2944 elem->wc_next = chainp; 2945 if (chainp == *top) { 2946 *top = elem; 2947 } else { 2948 before->wc_next = elem; 2949 } 2950 return 0; 2951 } 2952 2953 static int 2954 pccbb_winlist_delete(top, bsh, size) 2955 struct pccbb_win_chain **top; 2956 bus_space_handle_t bsh; 2957 bus_size_t size; 2958 { 2959 struct pccbb_win_chain *chainp = *top; 2960 struct pccbb_win_chain **before = top; 2961 2962 for (; chainp && chainp->wc_handle != bsh; chainp = chainp->wc_next) { 2963 before = &chainp->wc_next; 2964 } 2965 2966 if (chainp == NULL) { 2967 return 1; /* fail: no candidate to remove */ 2968 } 2969 2970 if (chainp->wc_end - chainp->wc_start != size - 1) { 2971 printf("fatal!!! 0x%lx\n", chainp->wc_start); 2972 return 1; /* fail: no candidate to remove */ 2973 } 2974 2975 *before = chainp->wc_next; 2976 free(chainp, M_DEVBUF); 2977 2978 return 0; 2979 } 2980 2981 static void 2982 pccbb_winset(align, sc, bst) 2983 bus_addr_t align; 2984 struct pccbb_softc *sc; 2985 bus_space_tag_t bst; 2986 { 2987 pci_chipset_tag_t pc; 2988 pcitag_t tag; 2989 bus_addr_t mask = ~(align - 1); 2990 struct { 2991 cardbusreg_t win_start; 2992 cardbusreg_t win_limit; 2993 int win_flags; 2994 } win[2]; 2995 struct pccbb_win_chain *chainp; 2996 int offs; 2997 2998 win[0].win_start = 0xffffffff; 2999 win[0].win_limit = 0; 3000 win[1].win_start = 0xffffffff; 3001 win[1].win_limit = 0; 3002 3003 chainp = sc->sc_iowindow; 3004 offs = 0x2c; 3005 if (sc->sc_memt == bst) { 3006 chainp = sc->sc_memwindow; 3007 offs = 0x1c; 3008 } 3009 3010 if (chainp) { 3011 win[0].win_start = chainp->wc_start & mask; 3012 win[0].win_limit = chainp->wc_end & mask; 3013 win[0].win_flags = chainp->wc_flags; 3014 chainp = chainp->wc_next; 3015 } 3016 3017 for (; chainp; chainp = chainp->wc_next) { 3018 if (win[1].win_start == 0xffffffff) { 3019 /* window 1 is not used */ 3020 if ((win[0].win_flags == chainp->wc_flags) && 3021 (win[0].win_limit + align >= 3022 (chainp->wc_start & mask))) { 3023 /* concatinate */ 3024 win[0].win_limit = chainp->wc_end & mask; 3025 } else { 3026 /* make new window */ 3027 win[1].win_start = chainp->wc_start & mask; 3028 win[1].win_limit = chainp->wc_end & mask; 3029 win[1].win_flags = chainp->wc_flags; 3030 } 3031 continue; 3032 } 3033 3034 /* Both windows are engagad. */ 3035 if (win[0].win_flags == win[1].win_flags) { 3036 /* same flags */ 3037 if (win[0].win_flags == chainp->wc_flags) { 3038 if (win[1].win_start - (win[0].win_limit + 3039 align) < 3040 (chainp->wc_start & mask) - 3041 ((chainp->wc_end & mask) + align)) { 3042 /* 3043 * merge window 0 and 1, and set win1 3044 * to chainp 3045 */ 3046 win[0].win_limit = win[1].win_limit; 3047 win[1].win_start = 3048 chainp->wc_start & mask; 3049 win[1].win_limit = 3050 chainp->wc_end & mask; 3051 } else { 3052 win[1].win_limit = 3053 chainp->wc_end & mask; 3054 } 3055 } else { 3056 /* different flags */ 3057 3058 /* concatinate win0 and win1 */ 3059 win[0].win_limit = win[1].win_limit; 3060 /* allocate win[1] to new space */ 3061 win[1].win_start = chainp->wc_start & mask; 3062 win[1].win_limit = chainp->wc_end & mask; 3063 win[1].win_flags = chainp->wc_flags; 3064 } 3065 } else { 3066 /* the flags of win[0] and win[1] is different */ 3067 if (win[0].win_flags == chainp->wc_flags) { 3068 win[0].win_limit = chainp->wc_end & mask; 3069 /* 3070 * XXX this creates overlapping windows, so 3071 * what should the poor bridge do if one is 3072 * cachable, and the other is not? 3073 */ 3074 printf("%s: overlapping windows\n", 3075 sc->sc_dev.dv_xname); 3076 } else { 3077 win[1].win_limit = chainp->wc_end & mask; 3078 } 3079 } 3080 } 3081 3082 pc = sc->sc_pc; 3083 tag = sc->sc_tag; 3084 pci_conf_write(pc, tag, offs, win[0].win_start); 3085 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3086 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3087 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3088 DPRINTF(("--pccbb_winset: win0 [%x, %lx), win1 [%x, %lx)\n", 3089 pci_conf_read(pc, tag, offs), 3090 pci_conf_read(pc, tag, offs + 4) + align, 3091 pci_conf_read(pc, tag, offs + 8), 3092 pci_conf_read(pc, tag, offs + 12) + align)); 3093 3094 if (bst == sc->sc_memt) { 3095 if (win[0].win_flags & PCCBB_MEM_CACHABLE) { 3096 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3097 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3098 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3099 } 3100 if (win[1].win_flags & PCCBB_MEM_CACHABLE) { 3101 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3102 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3103 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3104 } 3105 } 3106 } 3107 3108 #endif /* rbus */ 3109 3110 static void 3111 pccbb_powerhook(why, arg) 3112 int why; 3113 void *arg; 3114 { 3115 struct pccbb_softc *sc = arg; 3116 u_int32_t reg; 3117 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3118 bus_space_handle_t base_memh = sc->sc_base_memh; 3119 3120 DPRINTF(("%s: power: why %d\n", sc->sc_dev.dv_xname, why)); 3121 3122 if (why == PWR_RESUME) { 3123 /* CSC Interrupt: Card detect interrupt on */ 3124 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3125 /* Card detect intr is turned on. */ 3126 reg |= CB_SOCKET_MASK_CD; 3127 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3128 /* reset interrupt */ 3129 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3130 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3131 3132 /* 3133 * check for card insertion or removal during suspend period. 3134 * XXX: the code can't cope with card swap (remove then insert). 3135 * how can we detect such situation? 3136 */ 3137 if (why == PWR_RESUME) 3138 (void)pccbbintr(sc); 3139 } 3140 } 3141
Indexes created Thu Sep 25 16:09:42 GMT 2025