pccbb.c revision 1.26
1 /* $NetBSD: pccbb.c,v 1.26 2000/02/23 07:28:54 haya Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 #define CBB_DEBUG 35 #define SHOW_REGS 36 #define PCCBB_PCMCIA_POLL 37 */ 38 /* #define CBB_DEBUG */ 39 40 /* 41 #define CB_PCMCIA_POLL 42 #define CB_PCMCIA_POLL_ONLY 43 #define LEVEL2 44 */ 45 46 #include <sys/types.h> 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/kernel.h> 50 #include <sys/errno.h> 51 #include <sys/ioctl.h> 52 #include <sys/syslog.h> 53 #include <sys/device.h> 54 #include <sys/malloc.h> 55 56 #include <machine/intr.h> 57 #include <machine/bus.h> 58 59 #include <dev/pci/pcivar.h> 60 #include <dev/pci/pcireg.h> 61 #include <dev/pci/pcidevs.h> 62 63 #include <dev/pci/pccbbreg.h> 64 65 #include <dev/cardbus/cardslotvar.h> 66 67 #include <dev/cardbus/cardbusvar.h> 68 69 #include <dev/pcmcia/pcmciareg.h> 70 #include <dev/pcmcia/pcmciavar.h> 71 72 #include <dev/ic/i82365reg.h> 73 #include <dev/ic/i82365var.h> 74 #include <dev/pci/pccbbvar.h> 75 76 #include "locators.h" 77 78 #ifndef __NetBSD_Version__ 79 struct cfdriver cbb_cd = { 80 NULL, "cbb", DV_DULL 81 }; 82 #endif 83 84 #if defined CBB_DEBUG 85 #define DPRINTF(x) printf x 86 #define STATIC 87 #else 88 #define DPRINTF(x) 89 #define STATIC static 90 #endif 91 92 #ifdef __BROKEN_INDIRECT_CONFIG 93 int pcicbbmatch __P((struct device *, void *, void *)); 94 #else 95 int pcicbbmatch __P((struct device *, struct cfdata *, void *)); 96 #endif 97 void pccbbattach __P((struct device *, struct device *, void *)); 98 int pccbbintr __P((void *)); 99 static void pci113x_insert __P((void *)); 100 static int pccbbintr_function __P((struct pccbb_softc *)); 101 102 static int pccbb_detect_card __P((struct pccbb_softc *)); 103 104 static void pccbb_pcmcia_write __P((struct pcic_handle *, int, u_int8_t)); 105 static u_int8_t pccbb_pcmcia_read __P((struct pcic_handle *, int)); 106 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 107 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 108 109 STATIC int cb_reset __P((struct pccbb_softc *)); 110 STATIC int cb_detect_voltage __P((struct pccbb_softc *)); 111 STATIC int cbbprint __P((void *, const char *)); 112 113 static int cb_chipset __P((u_int32_t, int *)); 114 STATIC void pccbb_pcmcia_attach_setup __P((struct pccbb_softc *, 115 struct pcmciabus_attach_args *)); 116 #if 0 117 STATIC void pccbb_pcmcia_attach_card __P((struct pcic_handle *)); 118 STATIC void pccbb_pcmcia_detach_card __P((struct pcic_handle *, int)); 119 STATIC void pccbb_pcmcia_deactivate_card __P((struct pcic_handle *)); 120 #endif 121 122 STATIC int pccbb_ctrl __P((cardbus_chipset_tag_t, int)); 123 STATIC int pccbb_power __P((cardbus_chipset_tag_t, int)); 124 STATIC int pccbb_cardenable __P((struct pccbb_softc * sc, int function)); 125 #if !rbus 126 static int pccbb_io_open __P((cardbus_chipset_tag_t, int, u_int32_t, 127 u_int32_t)); 128 static int pccbb_io_close __P((cardbus_chipset_tag_t, int)); 129 static int pccbb_mem_open __P((cardbus_chipset_tag_t, int, u_int32_t, 130 u_int32_t)); 131 static int pccbb_mem_close __P((cardbus_chipset_tag_t, int)); 132 #endif /* !rbus */ 133 static void *pccbb_intr_establish __P((struct pccbb_softc *, int irq, 134 int level, int (*ih) (void *), void *sc)); 135 static void pccbb_intr_disestablish __P((struct pccbb_softc *, void *ih)); 136 137 static void *pccbb_cb_intr_establish __P((cardbus_chipset_tag_t, int irq, 138 int level, int (*ih) (void *), void *sc)); 139 static void pccbb_cb_intr_disestablish __P((cardbus_chipset_tag_t ct, void *ih)); 140 141 static cardbustag_t pccbb_make_tag __P((cardbus_chipset_tag_t, int, int, int)); 142 static void pccbb_free_tag __P((cardbus_chipset_tag_t, cardbustag_t)); 143 static cardbusreg_t pccbb_conf_read __P((cardbus_chipset_tag_t, cardbustag_t, 144 int)); 145 static void pccbb_conf_write __P((cardbus_chipset_tag_t, cardbustag_t, int, 146 cardbusreg_t)); 147 static void pccbb_chipinit __P((struct pccbb_softc *)); 148 149 STATIC int pccbb_pcmcia_mem_alloc __P((pcmcia_chipset_handle_t, bus_size_t, 150 struct pcmcia_mem_handle *)); 151 STATIC void pccbb_pcmcia_mem_free __P((pcmcia_chipset_handle_t, 152 struct pcmcia_mem_handle *)); 153 STATIC int pccbb_pcmcia_mem_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 154 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *)); 155 STATIC void pccbb_pcmcia_mem_unmap __P((pcmcia_chipset_handle_t, int)); 156 STATIC int pccbb_pcmcia_io_alloc __P((pcmcia_chipset_handle_t, bus_addr_t, 157 bus_size_t, bus_size_t, struct pcmcia_io_handle *)); 158 STATIC void pccbb_pcmcia_io_free __P((pcmcia_chipset_handle_t, 159 struct pcmcia_io_handle *)); 160 STATIC int pccbb_pcmcia_io_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 161 bus_size_t, struct pcmcia_io_handle *, int *)); 162 STATIC void pccbb_pcmcia_io_unmap __P((pcmcia_chipset_handle_t, int)); 163 STATIC void *pccbb_pcmcia_intr_establish __P((pcmcia_chipset_handle_t, 164 struct pcmcia_function *, int, int (*)(void *), void *)); 165 STATIC void pccbb_pcmcia_intr_disestablish __P((pcmcia_chipset_handle_t, 166 void *)); 167 STATIC void pccbb_pcmcia_socket_enable __P((pcmcia_chipset_handle_t)); 168 STATIC void pccbb_pcmcia_socket_disable __P((pcmcia_chipset_handle_t)); 169 STATIC int pccbb_pcmcia_card_detect __P((pcmcia_chipset_handle_t pch)); 170 171 static void pccbb_pcmcia_do_io_map __P((struct pcic_handle *, int)); 172 static void pccbb_pcmcia_wait_ready __P((struct pcic_handle *)); 173 static void pccbb_pcmcia_do_mem_map __P((struct pcic_handle *, int)); 174 static void pccbb_powerhook __P((int, void *)); 175 176 /* bus-space allocation and disallocation functions */ 177 #if rbus 178 179 static int pccbb_rbus_cb_space_alloc __P((cardbus_chipset_tag_t, rbus_tag_t, 180 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 181 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp)); 182 static int pccbb_rbus_cb_space_free __P((cardbus_chipset_tag_t, rbus_tag_t, 183 bus_space_handle_t, bus_size_t)); 184 185 #endif /* rbus */ 186 187 #if rbus 188 189 static int pccbb_open_win __P((struct pccbb_softc *, bus_space_tag_t, 190 bus_addr_t, bus_size_t, bus_space_handle_t, int flags)); 191 static int pccbb_close_win __P((struct pccbb_softc *, bus_space_tag_t, 192 bus_space_handle_t, bus_size_t)); 193 static int pccbb_winlist_insert __P((struct pccbb_win_chain **, bus_addr_t, 194 bus_size_t, bus_space_handle_t, int)); 195 static int pccbb_winlist_delete __P((struct pccbb_win_chain **, 196 bus_space_handle_t, bus_size_t)); 197 static void pccbb_winset __P((bus_addr_t align, struct pccbb_softc *, 198 bus_space_tag_t)); 199 void pccbb_winlist_show(struct pccbb_win_chain *); 200 201 #endif /* rbus */ 202 203 /* for config_defer */ 204 static void pccbb_pci_callback __P((struct device *)); 205 206 #if defined SHOW_REGS 207 static void cb_show_regs __P((pci_chipset_tag_t pc, pcitag_t tag, 208 bus_space_tag_t memt, bus_space_handle_t memh)); 209 #endif 210 211 struct cfattach cbb_pci_ca = { 212 sizeof(struct pccbb_softc), pcicbbmatch, pccbbattach 213 }; 214 215 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 216 pccbb_pcmcia_mem_alloc, 217 pccbb_pcmcia_mem_free, 218 pccbb_pcmcia_mem_map, 219 pccbb_pcmcia_mem_unmap, 220 pccbb_pcmcia_io_alloc, 221 pccbb_pcmcia_io_free, 222 pccbb_pcmcia_io_map, 223 pccbb_pcmcia_io_unmap, 224 pccbb_pcmcia_intr_establish, 225 pccbb_pcmcia_intr_disestablish, 226 pccbb_pcmcia_socket_enable, 227 pccbb_pcmcia_socket_disable, 228 pccbb_pcmcia_card_detect 229 }; 230 231 #if rbus 232 static struct cardbus_functions pccbb_funcs = { 233 pccbb_rbus_cb_space_alloc, 234 pccbb_rbus_cb_space_free, 235 pccbb_cb_intr_establish, 236 pccbb_cb_intr_disestablish, 237 pccbb_ctrl, 238 pccbb_power, 239 pccbb_make_tag, 240 pccbb_free_tag, 241 pccbb_conf_read, 242 pccbb_conf_write, 243 }; 244 #else 245 static struct cardbus_functions pccbb_funcs = { 246 pccbb_ctrl, 247 pccbb_power, 248 pccbb_mem_open, 249 pccbb_mem_close, 250 pccbb_io_open, 251 pccbb_io_close, 252 pccbb_cb_intr_establish, 253 pccbb_cb_intr_disestablish, 254 pccbb_make_tag, 255 pccbb_conf_read, 256 pccbb_conf_write, 257 }; 258 #endif 259 260 int 261 pcicbbmatch(parent, match, aux) 262 struct device *parent; 263 #ifdef __BROKEN_INDIRECT_CONFIG 264 void *match; 265 #else 266 struct cfdata *match; 267 #endif 268 void *aux; 269 { 270 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 271 272 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 273 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 274 PCI_INTERFACE(pa->pa_class) == 0) { 275 return 1; 276 } 277 278 return 0; 279 } 280 281 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 282 | ((prod) << PCI_PRODUCT_SHIFT)) 283 284 struct yenta_chipinfo { 285 pcireg_t yc_id; /* vendor tag | product tag */ 286 int yc_chiptype; 287 int yc_flags; 288 } yc_chipsets[] = { 289 /* Texas Instruments chips */ 290 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 291 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 292 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 293 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 294 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI12XX, 295 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 296 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 297 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 298 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 299 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 300 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 301 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 302 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI12XX, 303 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 304 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI12XX, 305 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 306 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 307 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 308 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 309 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 310 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI12XX, 311 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 312 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 313 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 314 315 /* Ricoh chips */ 316 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 317 PCCBB_PCMCIA_MEM_32}, 318 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 319 PCCBB_PCMCIA_MEM_32}, 320 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 321 PCCBB_PCMCIA_MEM_32}, 322 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 323 PCCBB_PCMCIA_MEM_32}, 324 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 325 PCCBB_PCMCIA_MEM_32}, 326 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 327 PCCBB_PCMCIA_MEM_32}, 328 329 /* Toshiba products */ 330 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 331 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 332 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 333 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 334 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 335 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 336 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 337 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 338 339 /* Cirrus Logic products */ 340 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 341 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 342 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 343 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 344 345 /* sentinel, or Generic chip */ 346 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 347 }; 348 349 static int 350 cb_chipset(pci_id, flagp) 351 u_int32_t pci_id; 352 int *flagp; 353 { 354 int loopend = sizeof(yc_chipsets) / sizeof(yc_chipsets[0]); 355 struct yenta_chipinfo *ycp, *ycend; 356 357 ycend = yc_chipsets + loopend; 358 359 for (ycp = yc_chipsets; ycp < ycend && pci_id != ycp->yc_id; ++ycp); 360 361 if (ycp == ycend) { 362 /* not found -- point at sentinel */ 363 ycp = yc_chipsets + loopend - 1; 364 } 365 366 if (flagp != NULL) { 367 *flagp = ycp->yc_flags; 368 } 369 370 return ycp->yc_chiptype; 371 } 372 373 static void 374 pccbb_shutdown(void *arg) 375 { 376 struct pccbb_softc *sc = arg; 377 pcireg_t command; 378 379 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 380 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 381 0); 382 383 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 384 385 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 386 PCI_COMMAND_MASTER_ENABLE); 387 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 388 389 } 390 391 void 392 pccbbattach(parent, self, aux) 393 struct device *parent; 394 struct device *self; 395 void *aux; 396 { 397 struct pccbb_softc *sc = (void *)self; 398 struct pci_attach_args *pa = aux; 399 pci_chipset_tag_t pc = pa->pa_pc; 400 pcireg_t sock_base, busreg; 401 bus_addr_t sockbase; 402 char devinfo[256]; 403 int flags; 404 405 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 406 407 pci_devinfo(pa->pa_id, 0, 0, devinfo); 408 printf(": %s (rev. 0x%02x)", devinfo, PCI_REVISION(pa->pa_class)); 409 #ifdef CBB_DEBUG 410 printf(" (chipflags %x)", flags); 411 #endif 412 printf("\n"); 413 414 #if rbus 415 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 416 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 417 #endif /* rbus */ 418 419 sc->sc_base_memh = 0; 420 421 /* 422 * MAP socket registers and ExCA registers on memory-space 423 * When no valid address is set on socket base registers (on pci 424 * config space), get it not polite way. 425 */ 426 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 427 428 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 429 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 430 /* The address must be valid. */ 431 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 432 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL)) { 433 printf("%s: can't map socket base address 0x%x\n", 434 sc->sc_dev.dv_xname, sock_base); 435 /* 436 * I think it's funny: socket base registers must be 437 * mapped on memory space, but ... 438 */ 439 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 440 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 441 NULL)) { 442 printf("%s: can't map socket base address" 443 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 444 sockbase); 445 /* give up... allocate reg space via rbus. */ 446 sc->sc_base_memh = 0; 447 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 448 } 449 } else { 450 DPRINTF(("%s: socket base address 0x%lx\n", 451 sc->sc_dev.dv_xname, sockbase)); 452 } 453 } 454 455 sc->sc_mem_start = 0; /* XXX */ 456 sc->sc_mem_end = 0xffffffff; /* XXX */ 457 458 /* 459 * When interrupt isn't routed correctly, give up probing cbb and do 460 * not kill pcic-compatible port. 461 */ 462 if ((0 == pa->pa_intrline) || (255 == pa->pa_intrline)) { 463 printf("%s: NOT USED because of unconfigured interrupt\n", 464 sc->sc_dev.dv_xname); 465 return; 466 } 467 468 /* 469 * When bus number isn't set correctly, give up using 32-bit CardBus 470 * mode. 471 */ 472 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 473 #if notyet 474 if (((busreg >> 8) & 0xff) == 0) { 475 printf("%s: CardBus support disabled because of unconfigured bus number\n", 476 sc->sc_dev.dv_xname); 477 flags |= PCCBB_PCMCIA_16BITONLY; 478 } 479 #endif 480 481 /* pccbb_machdep.c end */ 482 483 #if defined CBB_DEBUG 484 { 485 static char *intrname[5] = { "NON", "A", "B", "C", "D" }; 486 printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname, 487 intrname[pa->pa_intrpin], pa->pa_intrline); 488 } 489 #endif 490 491 /* setup softc */ 492 sc->sc_pc = pc; 493 sc->sc_iot = pa->pa_iot; 494 sc->sc_memt = pa->pa_memt; 495 sc->sc_dmat = pa->pa_dmat; 496 sc->sc_tag = pa->pa_tag; 497 sc->sc_function = pa->pa_function; 498 499 sc->sc_intrline = pa->pa_intrline; 500 sc->sc_intrtag = pa->pa_intrtag; 501 sc->sc_intrpin = pa->pa_intrpin; 502 503 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 504 505 shutdownhook_establish(pccbb_shutdown, sc); 506 507 #if __NetBSD_Version__ > 103060000 508 config_defer(self, pccbb_pci_callback); 509 #else 510 pccbb_pci_callback(self); 511 #endif 512 } 513 514 515 516 517 /* 518 * static void pccbb_pci_callback(struct device *self) 519 * 520 * The actual attach routine: get memory space for YENTA register 521 * space, setup YENTA register and route interrupt. 522 * 523 * This function should be deferred because this device may obtain 524 * memory space dynamically. This function must avoid obtaining 525 * memory area which has already kept for another device. Also, 526 * this function MUST be done before ISA attach process because this 527 * function kills pcic compatible port used by ISA pcic. 528 */ 529 static void 530 pccbb_pci_callback(self) 531 struct device *self; 532 { 533 struct pccbb_softc *sc = (void *)self; 534 pci_chipset_tag_t pc = sc->sc_pc; 535 bus_space_tag_t base_memt; 536 bus_space_handle_t base_memh; 537 u_int32_t maskreg; 538 pci_intr_handle_t ih; 539 const char *intrstr = NULL; 540 bus_addr_t sockbase; 541 struct cbslot_attach_args cba; 542 struct pcmciabus_attach_args paa; 543 struct cardslot_attach_args caa; 544 struct cardslot_softc *csc; 545 546 if (0 == sc->sc_base_memh) { 547 /* The socket registers aren't mapped correctly. */ 548 #if rbus 549 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 550 (sc->sc_chipset == CB_RX5C47X 551 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 552 0, &sockbase, &sc->sc_base_memh)) { 553 return; 554 } 555 sc->sc_base_memt = sc->sc_memt; 556 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 557 DPRINTF(("%s: CardBus resister address 0x%lx -> 0x%x\n", 558 sc->sc_dev.dv_xname, sockbase, pci_conf_read(pc, sc->sc_tag, 559 PCI_SOCKBASE))); 560 #else 561 sc->sc_base_memt = sc->sc_memt; 562 #if !defined CBB_PCI_BASE 563 #define CBB_PCI_BASE 0x20000000 564 #endif 565 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 566 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 567 /* cannot allocate memory space */ 568 return; 569 } 570 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 571 DPRINTF(("%s: CardBus resister address 0x%x -> 0x%x\n", 572 sc->sc_dev.dv_xname, sock_base, pci_conf_read(pc, 573 sc->sc_tag, PCI_SOCKBASE))); 574 #endif 575 } 576 577 /* bus bridge initialisation */ 578 pccbb_chipinit(sc); 579 580 base_memt = sc->sc_base_memt; /* socket regs memory tag */ 581 base_memh = sc->sc_base_memh; /* socket regs memory handle */ 582 583 /* CSC Interrupt: Card detect interrupt on */ 584 maskreg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 585 maskreg |= CB_SOCKET_MASK_CD; /* Card detect intr is turned on. */ 586 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, maskreg); 587 /* reset interrupt */ 588 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, 589 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT)); 590 591 /* Map and establish the interrupt. */ 592 if (pci_intr_map(pc, sc->sc_intrtag, sc->sc_intrpin, 593 sc->sc_intrline, &ih)) { 594 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 595 return; 596 } 597 intrstr = pci_intr_string(pc, ih); 598 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 599 600 if (sc->sc_ih == NULL) { 601 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 602 if (intrstr != NULL) { 603 printf(" at %s", intrstr); 604 } 605 printf("\n"); 606 return; 607 } 608 609 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 610 powerhook_establish(pccbb_powerhook, sc); 611 612 { 613 u_int32_t sockstat = 614 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 615 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 616 sc->sc_flags |= CBB_CARDEXIST; 617 } 618 } 619 620 /* 621 * attach cardbus 622 */ 623 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 624 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 625 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 626 627 /* initialise cbslot_attach */ 628 cba.cba_busname = "cardbus"; 629 cba.cba_iot = sc->sc_iot; 630 cba.cba_memt = sc->sc_memt; 631 cba.cba_dmat = sc->sc_dmat; 632 cba.cba_function = 0; 633 cba.cba_bus = (busreg >> 8) & 0x0ff; 634 cba.cba_cc = (void *)sc; 635 cba.cba_cf = &pccbb_funcs; 636 cba.cba_intrline = sc->sc_intrline; 637 638 #if rbus 639 cba.cba_rbus_iot = sc->sc_rbus_iot; 640 cba.cba_rbus_memt = sc->sc_rbus_memt; 641 #endif 642 643 cba.cba_cacheline = PCI_CACHELINE(bhlc); 644 cba.cba_lattimer = PCI_CB_LATENCY(busreg); 645 646 printf("%s: cacheline 0x%x lattimer 0x%x\n", 647 sc->sc_dev.dv_xname, cba.cba_cacheline, cba.cba_lattimer); 648 printf("%s: bhlc 0x%x lscp 0x%x\n", sc->sc_dev.dv_xname, bhlc, 649 busreg); 650 #if defined SHOW_REGS 651 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 652 sc->sc_base_memh); 653 #endif 654 } 655 656 pccbb_pcmcia_attach_setup(sc, &paa); 657 caa.caa_cb_attach = NULL; 658 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 659 caa.caa_cb_attach = &cba; 660 } 661 caa.caa_16_attach = &paa; 662 caa.caa_ph = &sc->sc_pcmcia_h; 663 664 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 665 DPRINTF(("pccbbattach: found cardslot\n")); 666 sc->sc_csc = csc; 667 } 668 669 return; 670 } 671 672 673 674 675 676 /* 677 * static void pccbb_chipinit(struct pccbb_softc *sc) 678 * 679 * This function initialise YENTA chip registers listed below: 680 * 1) PCI command reg, 681 * 2) PCI and CardBus latency timer, 682 * 3) disable legacy (PCIC-compatible) io, 683 * 4) route PCI interrupt, 684 * 5) close all memory and io windows. 685 */ 686 static void 687 pccbb_chipinit(sc) 688 struct pccbb_softc *sc; 689 { 690 pci_chipset_tag_t pc = sc->sc_pc; 691 pcitag_t tag = sc->sc_tag; 692 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 693 bus_space_handle_t base_memh = sc->sc_base_memh; 694 pcireg_t cbctrl; 695 696 /* 697 * Set PCI command reg. 698 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 699 */ 700 { 701 pcireg_t command = 702 pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 703 704 /* I believe it is harmless. */ 705 command |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 706 PCI_COMMAND_MASTER_ENABLE); 707 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, command); 708 } 709 710 /* 711 * Set CardBus latency timer 712 */ 713 { 714 pcireg_t pci_lscp = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 715 if (PCI_CB_LATENCY(pci_lscp) < 0x20) { 716 pci_lscp &= 717 ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 718 pci_lscp |= (0x20 << PCI_CB_LATENCY_SHIFT); 719 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, pci_lscp); 720 } 721 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 722 PCI_CB_LATENCY(pci_lscp), pci_conf_read(pc, tag, 723 PCI_CB_LSCP_REG))); 724 } 725 726 /* 727 * Set PCI latency timer 728 */ 729 { 730 pcireg_t pci_bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG); 731 if (PCI_LATTIMER(pci_bhlc) < 0x10) { 732 pci_bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 733 pci_bhlc |= (0x10 << PCI_LATTIMER_SHIFT); 734 pci_conf_write(pc, tag, PCI_BHLC_REG, pci_bhlc); 735 } 736 DPRINTF(("PCI latency timer 0x%x (%x)\n", 737 PCI_LATTIMER(pci_bhlc), pci_conf_read(pc, tag, 738 PCI_BHLC_REG))); 739 } 740 741 /* disable Legacy IO */ 742 743 switch (sc->sc_chipset) { 744 case CB_RX5C46X: /* fallthrogh */ 745 #if 0 746 case CB_RX5C47X: 747 #endif 748 /* 749 * The legacy pcic io-port on Ricoh CardBus bridges cannot be 750 * disabled by substituting 0 into PCI_LEGACY register. Ricoh 751 * CardBus bridges have special bits on Bridge control reg (addr 752 * 0x3e on PCI config space). 753 */ 754 { 755 pcireg_t bcri = pci_conf_read(pc, tag, PCI_BCR_INTR); 756 bcri &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 757 pci_conf_write(pc, tag, PCI_BCR_INTR, bcri); 758 } 759 break; 760 default: 761 /* XXX: I don't know proper way to kill Legacy IO properly. */ 762 pci_conf_write(pc, tag, PCI_LEGACY, 0x0); 763 break; 764 } 765 766 /* 767 * Interrupt routing: use PCI interrupt 768 */ 769 { 770 u_int32_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 771 bcr &= ~CB_BCR_INTR_IREQ_ENABLE; /* use PCI Intr */ 772 bcr |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 773 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 774 } 775 776 if (CB_TI113X == sc->sc_chipset) { 777 cbctrl = pci_conf_read(pc, tag, PCI_CBCTRL); 778 if (0 == sc->sc_function) { 779 cbctrl |= PCI113X_CBCTRL_PCI_IRQ_ENA; 780 } 781 /* XXX: bug in PCI113X */ 782 cbctrl |= PCI113X_CBCTRL_PCI_IRQ_ENA; 783 /* CSC intr enable */ 784 cbctrl |= PCI113X_CBCTRL_PCI_CSC; 785 /* functional intr prohibit */ 786 cbctrl &= ~PCI113X_CBCTRL_PCI_INTR; 787 /* prohibit ISA routing */ 788 cbctrl &= ~PCI113X_CBCTRL_INT_MASK; 789 pci_conf_write(pc, tag, PCI_CBCTRL, cbctrl); 790 791 /* 792 * set ExCA regs: PCI113X required to be set bit 4 at Interrupt 793 * and General Register, which is IRQ Enable Register, and 794 * clear bit 3:0 to zero in order to route CSC interrupt to 795 * PCI interrupt pin. 796 */ 797 bus_space_write_1(base_memt, base_memh, 0x0803, 0x10); 798 /* set ExCA regs: prohibit all pcmcia-style CSC intr. */ 799 bus_space_write_1(base_memt, base_memh, 0x0805, 0x00); 800 #if 1 801 DPRINTF(("ExCA regs:")); 802 DPRINTF((" 0x803: %02x", bus_space_read_1(base_memt, base_memh, 803 0x803))); 804 DPRINTF((" 0x805: %02x", bus_space_read_1(base_memt, base_memh, 805 0x805))); 806 DPRINTF((" 0x81e: %02x\n", bus_space_read_1(base_memt, 807 base_memh, 0x81e))); 808 #endif 809 } else if (sc->sc_chipset == CB_TI12XX) { 810 cbctrl = pci_conf_read(pc, tag, PCI_CBCTRL); 811 cbctrl &= ~PCI12XX_CBCTRL_INT_MASK; /* intr routing reset */ 812 pci_conf_write(pc, tag, PCI_CBCTRL, cbctrl); 813 /* 814 * set ExCA regs: PCI12XX required to be set bit 4 at 815 * Interrupt and General Register, which is IRQ Enable 816 * Register, and clear bit 3:0 to zero in order to 817 * route CSC interrupt to PCI interrupt pin. 818 */ 819 bus_space_write_1(base_memt, base_memh, 0x0803, 0x10); 820 /* set ExCA regs: prohibit all pcmcia-style CSC intr. */ 821 bus_space_write_1(base_memt, base_memh, 0x0805, 0x00); 822 } else if (sc->sc_chipset == CB_TOPIC95B) { 823 cardbusreg_t sock_ctrl, slot_ctrl; 824 825 sock_ctrl = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 826 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, 827 sock_ctrl | TOPIC_SOCKET_CTRL_SCR_IRQSEL); 828 829 slot_ctrl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 830 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 831 sc->sc_dev.dv_xname, slot_ctrl)); 832 slot_ctrl |= 833 (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 834 TOPIC_SLOT_CTRL_ID_LOCK); 835 slot_ctrl |= TOPIC_SLOT_CTRL_CARDBUS; 836 slot_ctrl &= ~TOPIC_SLOT_CTRL_SWDETECT; 837 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slot_ctrl); 838 DPRINTF(("0x%x\n", slot_ctrl)); 839 } 840 841 /* close all memory and io windows */ 842 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 843 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 844 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 845 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 846 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 847 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 848 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 849 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 850 851 return; 852 } 853 854 855 856 857 /* 858 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 859 * struct pcmciabus_attach_args *paa) 860 * 861 * This function attaches 16-bit PCcard bus. 862 */ 863 STATIC void 864 pccbb_pcmcia_attach_setup(sc, paa) 865 struct pccbb_softc *sc; 866 struct pcmciabus_attach_args *paa; 867 { 868 struct pcic_handle *ph = &sc->sc_pcmcia_h; 869 #if rbus 870 rbus_tag_t rb; 871 #endif 872 873 /* initialise pcmcia part in pccbb_softc */ 874 ph->ph_parent = (struct device *)sc; 875 ph->sock = sc->sc_function; 876 ph->flags = 0; 877 ph->shutdown = 0; 878 ph->ih_irq = sc->sc_intrline; 879 ph->ph_bus_t = sc->sc_base_memt; 880 ph->ph_bus_h = sc->sc_base_memh; 881 ph->ph_read = pccbb_pcmcia_read; 882 ph->ph_write = pccbb_pcmcia_write; 883 sc->sc_pct = &pccbb_pcmcia_funcs; 884 885 Pcic_write(ph, PCIC_CSC_INTR, 0); 886 Pcic_read(ph, PCIC_CSC); 887 888 /* initialise pcmcia bus attachment */ 889 paa->paa_busname = "pcmcia"; 890 paa->pct = sc->sc_pct; 891 paa->pch = ph; 892 paa->iobase = 0; /* I don't use them */ 893 paa->iosize = 0; 894 #if rbus 895 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 896 paa->iobase = rb->rb_start + rb->rb_offset; 897 paa->iosize = rb->rb_end - rb->rb_start; 898 #endif 899 900 return; 901 } 902 903 #if 0 904 STATIC void 905 pccbb_pcmcia_attach_card(ph) 906 struct pcic_handle *ph; 907 { 908 if (ph->flags & PCIC_FLAG_CARDP) { 909 panic("pccbb_pcmcia_attach_card: already attached"); 910 } 911 912 /* call the MI attach function */ 913 pcmcia_card_attach(ph->pcmcia); 914 915 ph->flags |= PCIC_FLAG_CARDP; 916 } 917 918 STATIC void 919 pccbb_pcmcia_detach_card(ph, flags) 920 struct pcic_handle *ph; 921 int flags; 922 { 923 if (!(ph->flags & PCIC_FLAG_CARDP)) { 924 panic("pccbb_pcmcia_detach_card: already detached"); 925 } 926 927 ph->flags &= ~PCIC_FLAG_CARDP; 928 929 /* call the MI detach function */ 930 pcmcia_card_detach(ph->pcmcia, flags); 931 } 932 #endif 933 934 /* 935 * int pccbbintr(arg) 936 * void *arg; 937 * This routine handles the interrupt from Yenta PCI-CardBus bridge 938 * itself. 939 */ 940 int 941 pccbbintr(arg) 942 void *arg; 943 { 944 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 945 u_int32_t sockevent; 946 bus_space_tag_t memt = sc->sc_base_memt; 947 bus_space_handle_t memh = sc->sc_base_memh; 948 u_int32_t sockstate; 949 950 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 951 if (0 == sockevent) { 952 /* This intr is not for me: it may be for my child devices. */ 953 return pccbbintr_function(sc); 954 } else { 955 /* reset bit */ 956 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 957 } 958 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 959 960 if (sockevent & CB_SOCKET_EVENT_CD) { 961 if (CB_SOCKET_STAT_CD == (sockstate & CB_SOCKET_STAT_CD)) { 962 /* A card should be removed. */ 963 if (sc->sc_flags & CBB_CARDEXIST) { 964 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 965 sockevent)); 966 DPRINTF((" card removed, 0x%08x\n", sockstate)); 967 sc->sc_flags &= ~CBB_CARDEXIST; 968 if (sc-> 969 sc_csc->sc_status & CARDSLOT_STATUS_CARD_16) 970 { 971 #if 0 972 struct pcic_handle *ph = 973 &sc->sc_pcmcia_h; 974 975 pcmcia_card_deactivate(ph->pcmcia); 976 pccbb_pcmcia_socket_disable(ph); 977 pccbb_pcmcia_detach_card(ph, 978 DETACH_FORCE); 979 #endif 980 cardslot_event_throw(sc->sc_csc, 981 CARDSLOT_EVENT_REMOVAL_16); 982 } else if (sc-> 983 sc_csc->sc_status & CARDSLOT_STATUS_CARD_CB) 984 { 985 /* Cardbus intr removed */ 986 cardslot_event_throw(sc->sc_csc, 987 CARDSLOT_EVENT_REMOVAL_CB); 988 } 989 } 990 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD)) { 991 if (sc->sc_flags & CBB_INSERTING) { 992 untimeout(pci113x_insert, sc); 993 } 994 timeout(pci113x_insert, sc, hz / 10); 995 sc->sc_flags |= CBB_INSERTING; 996 } 997 } else { 998 DPRINTF(("%s: sockevent = %b\n", 999 sc->sc_dev.dv_xname, sockevent, PCCBB_SOCKEVENT_BITS)); 1000 DPRINTF(("%s: sockstate = %b\n", 1001 sc->sc_dev.dv_xname, sockstate, PCCBB_SOCKSTATE_BITS)); 1002 } 1003 1004 return 1; 1005 } 1006 1007 /* 1008 * static int pccbbintr_function(struct pccbb_softc *sc) 1009 * 1010 * This function calls each interrupt handler registered at the 1011 * bridge. The interrupt handlers are called in registerd order. 1012 */ 1013 static int 1014 pccbbintr_function(sc) 1015 struct pccbb_softc *sc; 1016 { 1017 int retval = 0, val; 1018 struct pccbb_intrhand_list *pil; 1019 1020 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 1021 val = (*pil->pil_func) (pil->pil_arg); 1022 retval = retval == 1 ? 1 : 1023 retval == 0 ? val : val != 0 ? val : retval; 1024 } 1025 1026 return retval; 1027 } 1028 1029 static void 1030 pci113x_insert(arg) 1031 void *arg; 1032 { 1033 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1034 u_int32_t sockevent, sockstate; 1035 1036 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1037 CB_SOCKET_EVENT); 1038 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1039 CB_SOCKET_STAT); 1040 1041 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1042 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1043 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1044 sc->sc_flags |= CBB_CARDEXIST; 1045 /* call pccard intterupt handler here */ 1046 if (sockstate & CB_SOCKET_STAT_16BIT) { 1047 /* 16-bit card found */ 1048 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1049 cardslot_event_throw(sc->sc_csc, 1050 CARDSLOT_EVENT_INSERTION_16); 1051 } else if (sockstate & CB_SOCKET_STAT_CB) { 1052 /* cardbus card fuond */ 1053 /* cardbus_attach_card(sc->sc_csc); */ 1054 cardslot_event_throw(sc->sc_csc, 1055 CARDSLOT_EVENT_INSERTION_CB); 1056 } else { 1057 /* who are you? */ 1058 } 1059 } else { 1060 timeout(pci113x_insert, sc, hz / 10); 1061 } 1062 } 1063 1064 #define PCCBB_PCMCIA_OFFSET 0x800 1065 static u_int8_t 1066 pccbb_pcmcia_read(ph, reg) 1067 struct pcic_handle *ph; 1068 int reg; 1069 { 1070 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1071 PCCBB_PCMCIA_OFFSET + reg); 1072 } 1073 1074 static void 1075 pccbb_pcmcia_write(ph, reg, val) 1076 struct pcic_handle *ph; 1077 int reg; 1078 u_int8_t val; 1079 { 1080 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1081 val); 1082 } 1083 1084 /* 1085 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1086 */ 1087 STATIC int 1088 pccbb_ctrl(ct, command) 1089 cardbus_chipset_tag_t ct; 1090 int command; 1091 { 1092 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1093 1094 switch (command) { 1095 case CARDBUS_CD: 1096 if (2 == pccbb_detect_card(sc)) { 1097 int retval = 0; 1098 int status = cb_detect_voltage(sc); 1099 if (PCCARD_VCC_5V & status) { 1100 retval |= CARDBUS_5V_CARD; 1101 } 1102 if (PCCARD_VCC_3V & status) { 1103 retval |= CARDBUS_3V_CARD; 1104 } 1105 if (PCCARD_VCC_XV & status) { 1106 retval |= CARDBUS_XV_CARD; 1107 } 1108 if (PCCARD_VCC_YV & status) { 1109 retval |= CARDBUS_YV_CARD; 1110 } 1111 return retval; 1112 } else { 1113 return 0; 1114 } 1115 break; 1116 case CARDBUS_RESET: 1117 return cb_reset(sc); 1118 break; 1119 case CARDBUS_IO_ENABLE: /* fallthrough */ 1120 case CARDBUS_IO_DISABLE: /* fallthrough */ 1121 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1122 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1123 case CARDBUS_BM_ENABLE: /* fallthrough */ 1124 case CARDBUS_BM_DISABLE: /* fallthrough */ 1125 return pccbb_cardenable(sc, command); 1126 break; 1127 } 1128 1129 return 0; 1130 } 1131 1132 /* 1133 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1134 * This function returns true when it succeeds and returns false when 1135 * it fails. 1136 */ 1137 STATIC int 1138 pccbb_power(ct, command) 1139 cardbus_chipset_tag_t ct; 1140 int command; 1141 { 1142 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1143 1144 u_int32_t status, sock_ctrl; 1145 bus_space_tag_t memt = sc->sc_base_memt; 1146 bus_space_handle_t memh = sc->sc_base_memh; 1147 1148 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1149 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1150 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1151 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1152 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1153 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1154 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1155 "UNKNOWN", 1156 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1157 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1158 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1159 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1160 "UNKNOWN", command)); 1161 1162 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1163 sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1164 1165 switch (command & CARDBUS_VCCMASK) { 1166 case CARDBUS_VCC_UC: 1167 break; 1168 case CARDBUS_VCC_5V: 1169 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1170 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1171 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1172 } else { 1173 printf("%s: BAD voltage request: no 5 V card\n", 1174 sc->sc_dev.dv_xname); 1175 } 1176 break; 1177 case CARDBUS_VCC_3V: 1178 if (CB_SOCKET_STAT_3VCARD & status) { 1179 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1180 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1181 } else { 1182 printf("%s: BAD voltage request: no 3.3 V card\n", 1183 sc->sc_dev.dv_xname); 1184 } 1185 break; 1186 case CARDBUS_VCC_0V: 1187 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1188 break; 1189 default: 1190 return 0; /* power NEVER changed */ 1191 break; 1192 } 1193 1194 switch (command & CARDBUS_VPPMASK) { 1195 case CARDBUS_VPP_UC: 1196 break; 1197 case CARDBUS_VPP_0V: 1198 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1199 break; 1200 case CARDBUS_VPP_VCC: 1201 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1202 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1203 break; 1204 case CARDBUS_VPP_12V: 1205 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1206 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1207 break; 1208 } 1209 1210 #if 0 1211 DPRINTF(("sock_ctrl: %x\n", sock_ctrl)); 1212 #endif 1213 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1214 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1215 1216 delay(20 * 1000); /* wait 20 ms: Vcc setup time */ 1217 /* 1218 * XXX delay 200 ms: though the standard defines that the Vcc set-up 1219 * time is 20 ms, some PC-Card bridge requires longer duration. 1220 */ 1221 delay(200 * 1000); 1222 1223 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1224 printf 1225 ("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1226 sc->sc_dev.dv_xname, sock_ctrl, status); 1227 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1228 (command & CARDBUS_VCCMASK) == 1229 CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : (command & 1230 CARDBUS_VCCMASK) == 1231 CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : (command & 1232 CARDBUS_VCCMASK) == 1233 CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : (command & 1234 CARDBUS_VCCMASK) == 1235 CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : (command & 1236 CARDBUS_VCCMASK) == 1237 CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : (command & 1238 CARDBUS_VCCMASK) == 1239 CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : "UNKNOWN", 1240 (command & CARDBUS_VPPMASK) == 1241 CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : (command & 1242 CARDBUS_VPPMASK) == 1243 CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : (command & 1244 CARDBUS_VPPMASK) == 1245 CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : (command & 1246 CARDBUS_VPPMASK) == 1247 CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : "UNKNOWN", command)); 1248 #if 0 1249 if (command == (CARDBUS_VCC_0V | CARDBUS_VPP_0V)) { 1250 u_int32_t force = 1251 bus_space_read_4(memt, memh, CB_SOCKET_FORCE); 1252 /* Reset Bad Vcc request */ 1253 force &= ~CB_SOCKET_FORCE_BADVCC; 1254 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, force); 1255 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1256 CB_SOCKET_STAT)); 1257 return 1; 1258 } 1259 #endif 1260 return 0; 1261 } 1262 return 1; /* power changed correctly */ 1263 } 1264 1265 #if defined CB_PCMCIA_POLL 1266 struct cb_poll_str { 1267 void *arg; 1268 int (*func) __P((void *)); 1269 int level; 1270 pccard_chipset_tag_t ct; 1271 int count; 1272 }; 1273 1274 static struct cb_poll_str cb_poll[10]; 1275 static int cb_poll_n = 0; 1276 1277 static void cb_pcmcia_poll __P((void *arg)); 1278 1279 static void 1280 cb_pcmcia_poll(arg) 1281 void *arg; 1282 { 1283 struct cb_poll_str *poll = arg; 1284 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1285 struct pccbb_softc *sc = psc->cpc_parent; 1286 int s; 1287 u_int32_t spsr; /* socket present-state reg */ 1288 1289 timeout(cb_pcmcia_poll, arg, hz / 10); 1290 switch (poll->level) { 1291 case IPL_NET: 1292 s = splnet(); 1293 break; 1294 case IPL_BIO: 1295 s = splbio(); 1296 break; 1297 case IPL_TTY: /* fallthrough */ 1298 default: 1299 s = spltty(); 1300 break; 1301 } 1302 1303 spsr = 1304 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1305 CB_SOCKET_STAT); 1306 1307 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1308 if (!(spsr & 0x40)) { /* CINT low */ 1309 #else 1310 if (1) { 1311 #endif 1312 if ((*poll->func) (poll->arg) == 1) { 1313 ++poll->count; 1314 printf("intr: reported from poller, 0x%x\n", spsr); 1315 #if defined LEVEL2 1316 } else { 1317 printf("intr: miss! 0x%x\n", spsr); 1318 #endif 1319 } 1320 } 1321 splx(s); 1322 } 1323 #endif /* defined CB_PCMCIA_POLL */ 1324 1325 /* 1326 * static int pccbb_detect_card(struct pccbb_softc *sc) 1327 * return value: 0 if no card exists. 1328 * 1 if 16-bit card exists. 1329 * 2 if cardbus card exists. 1330 */ 1331 static int 1332 pccbb_detect_card(sc) 1333 struct pccbb_softc *sc; 1334 { 1335 bus_space_handle_t base_memh = sc->sc_base_memh; 1336 bus_space_tag_t base_memt = sc->sc_base_memt; 1337 u_int32_t sockstat = 1338 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1339 int retval = 0; 1340 1341 /* CD1 and CD2 asserted */ 1342 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1343 /* card must be present */ 1344 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1345 /* NOTACARD DEASSERTED */ 1346 if (CB_SOCKET_STAT_CB & sockstat) { 1347 /* CardBus mode */ 1348 retval = 2; 1349 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1350 /* 16-bit mode */ 1351 retval = 1; 1352 } 1353 } 1354 } 1355 return retval; 1356 } 1357 1358 /* 1359 * STATIC int cb_reset(struct pccbb_softc *sc) 1360 * This function resets CardBus card. 1361 */ 1362 STATIC int 1363 cb_reset(sc) 1364 struct pccbb_softc *sc; 1365 { 1366 /* 1367 * Reset Assert at least 20 ms 1368 * Some machines request longer duration. 1369 */ 1370 int reset_duration = 1371 (sc->sc_chipset == CB_RX5C47X ? 400 * 1000 : 40 * 1000); 1372 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1373 1374 bcr |= (0x40 << 16); /* Reset bit Assert (bit 6 at 0x3E) */ 1375 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1376 delay(reset_duration); 1377 1378 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1379 bcr &= ~(0x40 << 16); /* Reset bit Deassert (bit 6 at 0x3E) */ 1380 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1381 delay(reset_duration); 1382 } 1383 /* No card found on the slot. Keep Reset. */ 1384 return 1; 1385 } 1386 1387 /* 1388 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1389 * This function detect card Voltage. 1390 */ 1391 STATIC int 1392 cb_detect_voltage(sc) 1393 struct pccbb_softc *sc; 1394 { 1395 u_int32_t psr; /* socket present-state reg */ 1396 bus_space_tag_t iot = sc->sc_base_memt; 1397 bus_space_handle_t ioh = sc->sc_base_memh; 1398 int vol = PCCARD_VCC_UKN; /* set 0 */ 1399 1400 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1401 1402 if (0x400u & psr) { 1403 vol |= PCCARD_VCC_5V; 1404 } 1405 if (0x800u & psr) { 1406 vol |= PCCARD_VCC_3V; 1407 } 1408 1409 return vol; 1410 } 1411 1412 STATIC int 1413 cbbprint(aux, pcic) 1414 void *aux; 1415 const char *pcic; 1416 { 1417 /* 1418 struct cbslot_attach_args *cba = aux; 1419 1420 if (cba->cba_slot >= 0) { 1421 printf(" slot %d", cba->cba_slot); 1422 } 1423 */ 1424 return UNCONF; 1425 } 1426 1427 /* 1428 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1429 * This function enables and disables the card 1430 */ 1431 STATIC int 1432 pccbb_cardenable(sc, function) 1433 struct pccbb_softc *sc; 1434 int function; 1435 { 1436 u_int32_t command = 1437 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1438 1439 DPRINTF(("pccbb_cardenable:")); 1440 switch (function) { 1441 case CARDBUS_IO_ENABLE: 1442 command |= PCI_COMMAND_IO_ENABLE; 1443 break; 1444 case CARDBUS_IO_DISABLE: 1445 command &= ~PCI_COMMAND_IO_ENABLE; 1446 break; 1447 case CARDBUS_MEM_ENABLE: 1448 command |= PCI_COMMAND_MEM_ENABLE; 1449 break; 1450 case CARDBUS_MEM_DISABLE: 1451 command &= ~PCI_COMMAND_MEM_ENABLE; 1452 break; 1453 case CARDBUS_BM_ENABLE: 1454 command |= PCI_COMMAND_MASTER_ENABLE; 1455 break; 1456 case CARDBUS_BM_DISABLE: 1457 command &= ~PCI_COMMAND_MASTER_ENABLE; 1458 break; 1459 default: 1460 return 0; 1461 } 1462 1463 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1464 DPRINTF((" command reg 0x%x\n", command)); 1465 return 1; 1466 } 1467 1468 #if !rbus 1469 /* 1470 * int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1471 */ 1472 static int 1473 pccbb_io_open(ct, win, start, end) 1474 cardbus_chipset_tag_t ct; 1475 int win; 1476 u_int32_t start, end; 1477 { 1478 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1479 int basereg; 1480 int limitreg; 1481 1482 if ((win < 0) || (win > 2)) { 1483 #if defined DIAGNOSTIC 1484 printf("cardbus_io_open: window out of range %d\n", win); 1485 #endif 1486 return 0; 1487 } 1488 1489 basereg = win * 8 + 0x2c; 1490 limitreg = win * 8 + 0x30; 1491 1492 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1493 start, basereg, end, limitreg)); 1494 1495 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1496 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1497 return 1; 1498 } 1499 1500 /* 1501 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1502 */ 1503 static int 1504 pccbb_io_close(ct, win) 1505 cardbus_chipset_tag_t ct; 1506 int win; 1507 { 1508 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1509 int basereg; 1510 int limitreg; 1511 1512 if ((win < 0) || (win > 2)) { 1513 #if defined DIAGNOSTIC 1514 printf("cardbus_io_close: window out of range %d\n", win); 1515 #endif 1516 return 0; 1517 } 1518 1519 basereg = win * 8 + 0x2c; 1520 limitreg = win * 8 + 0x30; 1521 1522 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1523 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1524 return 1; 1525 } 1526 1527 /* 1528 * int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1529 */ 1530 static int 1531 pccbb_mem_open(ct, win, start, end) 1532 cardbus_chipset_tag_t ct; 1533 int win; 1534 u_int32_t start, end; 1535 { 1536 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1537 int basereg; 1538 int limitreg; 1539 1540 if ((win < 0) || (win > 2)) { 1541 #if defined DIAGNOSTIC 1542 printf("cardbus_mem_open: window out of range %d\n", win); 1543 #endif 1544 return 0; 1545 } 1546 1547 basereg = win * 8 + 0x1c; 1548 limitreg = win * 8 + 0x20; 1549 1550 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1551 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1552 return 1; 1553 } 1554 1555 /* 1556 * int pccbb_mem_close(cardbus_chipset_tag_t, int) 1557 */ 1558 static int 1559 pccbb_mem_close(ct, win) 1560 cardbus_chipset_tag_t ct; 1561 int win; 1562 { 1563 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1564 int basereg; 1565 int limitreg; 1566 1567 if ((win < 0) || (win > 2)) { 1568 #if defined DIAGNOSTIC 1569 printf("cardbus_mem_close: window out of range %d\n", win); 1570 #endif 1571 return 0; 1572 } 1573 1574 basereg = win * 8 + 0x1c; 1575 limitreg = win * 8 + 0x20; 1576 1577 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1578 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1579 return 1; 1580 } 1581 #endif 1582 1583 /* 1584 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1585 * int irq, 1586 * int level, 1587 * int (* func) __P((void *)), 1588 * void *arg) 1589 * 1590 * This function registers an interrupt handler at the bridge, in 1591 * order not to call the interrput handlers of child devices when 1592 * a card-deletion interrput occurs. 1593 * 1594 * The arguments irq and level are not used. 1595 */ 1596 static void * 1597 pccbb_cb_intr_establish(ct, irq, level, func, arg) 1598 cardbus_chipset_tag_t ct; 1599 int irq, level; 1600 int (*func) __P((void *)); 1601 void *arg; 1602 { 1603 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1604 1605 return pccbb_intr_establish(sc, irq, level, func, arg); 1606 } 1607 1608 1609 /* 1610 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1611 * void *ih) 1612 * 1613 * This function removes an interrupt handler pointed by ih. 1614 */ 1615 static void 1616 pccbb_cb_intr_disestablish(ct, ih) 1617 cardbus_chipset_tag_t ct; 1618 void *ih; 1619 { 1620 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1621 1622 pccbb_intr_disestablish(sc, ih); 1623 } 1624 1625 1626 /* 1627 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1628 * int irq, 1629 * int level, 1630 * int (* func) __P((void *)), 1631 * void *arg) 1632 * 1633 * This function registers an interrupt handler at the bridge, in 1634 * order not to call the interrput handlers of child devices when 1635 * a card-deletion interrput occurs. 1636 * 1637 * The arguments irq and level are not used. 1638 */ 1639 static void * 1640 pccbb_intr_establish(sc, irq, level, func, arg) 1641 struct pccbb_softc *sc; 1642 int irq, level; 1643 int (*func) __P((void *)); 1644 void *arg; 1645 { 1646 struct pccbb_intrhand_list *pil, *newpil; 1647 1648 DPRINTF(("pccbb_intr_establish start. %p\n", sc->sc_pil)); 1649 1650 if (sc->sc_pil == NULL) { 1651 /* initialise bridge intr routing */ 1652 1653 switch (sc->sc_chipset) { 1654 case CB_TI113X: 1655 { 1656 pcireg_t cbctrl = 1657 pci_conf_read(sc->sc_pc, sc->sc_tag, 1658 PCI_CBCTRL); 1659 /* functional intr enabled */ 1660 cbctrl |= PCI113X_CBCTRL_PCI_INTR; 1661 pci_conf_write(sc->sc_pc, sc->sc_tag, 1662 PCI_CBCTRL, cbctrl); 1663 break; 1664 } 1665 default: 1666 break; 1667 } 1668 } 1669 1670 /* 1671 * Allocate a room for interrut handler structure. 1672 */ 1673 if (NULL == (newpil = 1674 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1675 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1676 return NULL; 1677 } 1678 1679 newpil->pil_func = func; 1680 newpil->pil_arg = arg; 1681 newpil->pil_next = NULL; 1682 1683 if (sc->sc_pil == NULL) { 1684 sc->sc_pil = newpil; 1685 } else { 1686 for (pil = sc->sc_pil; pil->pil_next != NULL; 1687 pil = pil->pil_next); 1688 pil->pil_next = newpil; 1689 } 1690 1691 DPRINTF(("pccbb_intr_establish add pil. %p\n", sc->sc_pil)); 1692 1693 return newpil; 1694 } 1695 1696 /* 1697 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1698 * void *ih) 1699 * 1700 * This function removes an interrupt handler pointed by ih. 1701 */ 1702 static void 1703 pccbb_intr_disestablish(sc, ih) 1704 struct pccbb_softc *sc; 1705 void *ih; 1706 { 1707 struct pccbb_intrhand_list *pil, **pil_prev; 1708 1709 DPRINTF(("pccbb_intr_disestablish start. %p\n", sc->sc_pil)); 1710 1711 pil_prev = &sc->sc_pil; 1712 1713 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 1714 if (pil == ih) { 1715 *pil_prev = pil->pil_next; 1716 free(pil, M_DEVBUF); 1717 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1718 break; 1719 } 1720 pil_prev = &pil->pil_next; 1721 } 1722 1723 if (sc->sc_pil == NULL) { 1724 /* No interrupt handlers */ 1725 1726 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1727 1728 switch (sc->sc_chipset) { 1729 case CB_TI113X: 1730 { 1731 pcireg_t cbctrl = 1732 pci_conf_read(sc->sc_pc, sc->sc_tag, 1733 PCI_CBCTRL); 1734 /* functional intr disabled */ 1735 cbctrl &= ~PCI113X_CBCTRL_PCI_INTR; 1736 pci_conf_write(sc->sc_pc, sc->sc_tag, 1737 PCI_CBCTRL, cbctrl); 1738 break; 1739 } 1740 default: 1741 break; 1742 } 1743 } 1744 } 1745 1746 #if defined SHOW_REGS 1747 static void 1748 cb_show_regs(pc, tag, memt, memh) 1749 pci_chipset_tag_t pc; 1750 pcitag_t tag; 1751 bus_space_tag_t memt; 1752 bus_space_handle_t memh; 1753 { 1754 int i; 1755 printf("PCI config regs:"); 1756 for (i = 0; i < 0x50; i += 4) { 1757 if (i % 16 == 0) { 1758 printf("\n 0x%02x:", i); 1759 } 1760 printf(" %08x", pci_conf_read(pc, tag, i)); 1761 } 1762 for (i = 0x80; i < 0xb0; i += 4) { 1763 if (i % 16 == 0) { 1764 printf("\n 0x%02x:", i); 1765 } 1766 printf(" %08x", pci_conf_read(pc, tag, i)); 1767 } 1768 1769 if (memh == 0) { 1770 printf("\n"); 1771 return; 1772 } 1773 1774 printf("\nsocket regs:"); 1775 for (i = 0; i <= 0x10; i += 0x04) { 1776 printf(" %08x", bus_space_read_4(memt, memh, i)); 1777 } 1778 printf("\nExCA regs:"); 1779 for (i = 0; i < 0x08; ++i) { 1780 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1781 } 1782 printf("\n"); 1783 return; 1784 } 1785 #endif 1786 1787 /* 1788 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1789 * int busno, int devno, int function) 1790 * This is the function to make a tag to access config space of 1791 * a CardBus Card. It works same as pci_conf_read. 1792 */ 1793 static cardbustag_t 1794 pccbb_make_tag(cc, busno, devno, function) 1795 cardbus_chipset_tag_t cc; 1796 int busno, devno, function; 1797 { 1798 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1799 1800 return pci_make_tag(sc->sc_pc, busno, devno, function); 1801 } 1802 1803 static void 1804 pccbb_free_tag(cc, tag) 1805 cardbus_chipset_tag_t cc; 1806 cardbustag_t tag; 1807 { 1808 } 1809 1810 /* 1811 * static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t cc, 1812 * cardbustag_t tag, int offset) 1813 * This is the function to read the config space of a CardBus Card. 1814 * It works same as pci_conf_read. 1815 */ 1816 static cardbusreg_t 1817 pccbb_conf_read(cc, tag, offset) 1818 cardbus_chipset_tag_t cc; 1819 cardbustag_t tag; 1820 int offset; /* register offset */ 1821 { 1822 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1823 1824 return pci_conf_read(sc->sc_pc, tag, offset); 1825 } 1826 1827 /* 1828 * static void pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, 1829 * int offs, cardbusreg_t val) 1830 * This is the function to write the config space of a CardBus Card. 1831 * It works same as pci_conf_write. 1832 */ 1833 static void 1834 pccbb_conf_write(cc, tag, reg, val) 1835 cardbus_chipset_tag_t cc; 1836 cardbustag_t tag; 1837 int reg; /* register offset */ 1838 cardbusreg_t val; 1839 { 1840 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1841 1842 pci_conf_write(sc->sc_pc, tag, reg, val); 1843 } 1844 1845 #if 0 1846 STATIC int 1847 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1848 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 1849 int speed, int flags, 1850 bus_space_handle_t * iohp) 1851 #endif 1852 /* 1853 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1854 * bus_addr_t start, bus_size_t size, 1855 * bus_size_t align, 1856 * struct pcmcia_io_handle *pcihp 1857 * 1858 * This function only allocates I/O region for pccard. This function 1859 * never maps the allcated region to pccard I/O area. 1860 * 1861 * XXX: The interface of this function is not very good, I believe. 1862 */ 1863 STATIC int 1864 pccbb_pcmcia_io_alloc(pch, start, size, align, pcihp) 1865 pcmcia_chipset_handle_t pch; 1866 bus_addr_t start; /* start address */ 1867 bus_size_t size; 1868 bus_size_t align; 1869 struct pcmcia_io_handle *pcihp; 1870 { 1871 struct pcic_handle *ph = (struct pcic_handle *)pch; 1872 bus_addr_t ioaddr; 1873 int flags = 0; 1874 bus_space_tag_t iot; 1875 bus_space_handle_t ioh; 1876 #if rbus 1877 rbus_tag_t rb; 1878 #endif 1879 if (align == 0) { 1880 align = size; /* XXX: funny??? */ 1881 } 1882 1883 /* 1884 * Allocate some arbitrary I/O space. 1885 */ 1886 1887 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 1888 1889 #if rbus 1890 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 1891 /* XXX: I assume all card decode lower 10 bits by its hardware */ 1892 if (rbus_space_alloc(rb, start, size, 0x3ff, align, 0, &ioaddr, &ioh)) { 1893 return 1; 1894 } 1895 #else 1896 if (start) { 1897 ioaddr = start; 1898 if (bus_space_map(iot, start, size, 0, &ioh)) { 1899 return 1; 1900 } 1901 DPRINTF(("pccbb_pcmcia_io_alloc map port %lx+%lx\n", 1902 (u_long) ioaddr, (u_long) size)); 1903 } else { 1904 flags |= PCMCIA_IO_ALLOCATED; 1905 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 1906 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 1907 size, align, 0, 0, &ioaddr, &ioh)) { 1908 /* No room be able to be get. */ 1909 return 1; 1910 } 1911 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 1912 (u_long) ioaddr, (u_long) size)); 1913 } 1914 #endif 1915 1916 pcihp->iot = iot; 1917 pcihp->ioh = ioh; 1918 pcihp->addr = ioaddr; 1919 pcihp->size = size; 1920 pcihp->flags = flags; 1921 1922 return 0; 1923 } 1924 1925 /* 1926 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 1927 * struct pcmcia_io_handle *pcihp) 1928 * 1929 * This function only frees I/O region for pccard. 1930 * 1931 * XXX: The interface of this function is not very good, I believe. 1932 */ 1933 void 1934 pccbb_pcmcia_io_free(pch, pcihp) 1935 pcmcia_chipset_handle_t pch; 1936 struct pcmcia_io_handle *pcihp; 1937 { 1938 #if !rbus 1939 bus_space_tag_t iot = pcihp->iot; 1940 #endif 1941 bus_space_handle_t ioh = pcihp->ioh; 1942 bus_size_t size = pcihp->size; 1943 1944 #if rbus 1945 struct pccbb_softc *sc = 1946 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 1947 rbus_tag_t rb = sc->sc_rbus_iot; 1948 1949 rbus_space_free(rb, ioh, size, NULL); 1950 #else 1951 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 1952 bus_space_free(iot, ioh, size); 1953 else 1954 bus_space_unmap(iot, ioh, size); 1955 #endif 1956 } 1957 1958 /* 1959 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 1960 * bus_addr_t offset, bus_size_t size, 1961 * struct pcmcia_io_handle *pcihp, 1962 * int *windowp) 1963 * 1964 * This function maps the allocated I/O region to pccard. This function 1965 * never allocates any I/O region for pccard I/O area. I don't 1966 * understand why the original authors of pcmciabus separated alloc and 1967 * map. I believe the two must be unite. 1968 * 1969 * XXX: no wait timing control? 1970 */ 1971 int 1972 pccbb_pcmcia_io_map(pch, width, offset, size, pcihp, windowp) 1973 pcmcia_chipset_handle_t pch; 1974 int width; 1975 bus_addr_t offset; 1976 bus_size_t size; 1977 struct pcmcia_io_handle *pcihp; 1978 int *windowp; 1979 { 1980 struct pcic_handle *ph = (struct pcic_handle *)pch; 1981 bus_addr_t ioaddr = pcihp->addr + offset; 1982 int i, win; 1983 #if defined CBB_DEBUG 1984 static char *width_names[] = { "dynamic", "io8", "io16" }; 1985 #endif 1986 1987 /* Sanity check I/O handle. */ 1988 1989 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 1990 panic("pccbb_pcmcia_io_map iot is bogus"); 1991 } 1992 1993 /* XXX Sanity check offset/size. */ 1994 1995 win = -1; 1996 for (i = 0; i < PCIC_IO_WINS; i++) { 1997 if ((ph->ioalloc & (1 << i)) == 0) { 1998 win = i; 1999 ph->ioalloc |= (1 << i); 2000 break; 2001 } 2002 } 2003 2004 if (win == -1) { 2005 return 1; 2006 } 2007 2008 *windowp = win; 2009 2010 /* XXX this is pretty gross */ 2011 2012 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2013 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2014 2015 /* XXX wtf is this doing here? */ 2016 2017 #if 0 2018 printf(" port 0x%lx", (u_long) ioaddr); 2019 if (size > 1) { 2020 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2021 } 2022 #endif 2023 2024 ph->io[win].addr = ioaddr; 2025 ph->io[win].size = size; 2026 ph->io[win].width = width; 2027 2028 /* actual dirty register-value changing in the function below. */ 2029 pccbb_pcmcia_do_io_map(ph, win); 2030 2031 return 0; 2032 } 2033 2034 /* 2035 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2036 * 2037 * This function changes register-value to map I/O region for pccard. 2038 */ 2039 static void 2040 pccbb_pcmcia_do_io_map(ph, win) 2041 struct pcic_handle *ph; 2042 int win; 2043 { 2044 static u_int8_t pcic_iowidth[3] = { 2045 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2046 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2047 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2048 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2049 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2050 }; 2051 2052 #define PCIC_SIA_START_LOW 0 2053 #define PCIC_SIA_START_HIGH 1 2054 #define PCIC_SIA_STOP_LOW 2 2055 #define PCIC_SIA_STOP_HIGH 3 2056 2057 int regbase_win = 0x8 + win * 0x04; 2058 u_int8_t ioctl, enable; 2059 2060 DPRINTF( 2061 ("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx width %d\n", 2062 win, (long)ph->io[win].addr, (long)ph->io[win].size, 2063 ph->io[win].width * 8)); 2064 2065 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2066 ph->io[win].addr & 0xff); 2067 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2068 (ph->io[win].addr >> 8) & 0xff); 2069 2070 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2071 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2072 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2073 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2074 2075 ioctl = Pcic_read(ph, PCIC_IOCTL); 2076 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2077 switch (win) { 2078 case 0: 2079 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2080 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2081 PCIC_IOCTL_IO0_DATASIZE_MASK); 2082 ioctl |= pcic_iowidth[ph->io[win].width]; 2083 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2084 break; 2085 case 1: 2086 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2087 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2088 PCIC_IOCTL_IO1_DATASIZE_MASK); 2089 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2090 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2091 break; 2092 } 2093 Pcic_write(ph, PCIC_IOCTL, ioctl); 2094 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2095 #if defined CBB_DEBUG 2096 { 2097 u_int8_t start_low = 2098 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2099 u_int8_t start_high = 2100 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2101 u_int8_t stop_low = 2102 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2103 u_int8_t stop_high = 2104 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2105 printf 2106 (" start %02x %02x, stop %02x %02x, ioctl %02x enable %02x\n", 2107 start_low, start_high, stop_low, stop_high, ioctl, enable); 2108 } 2109 #endif 2110 } 2111 2112 /* 2113 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2114 * 2115 * This function unmapss I/O region. No return value. 2116 */ 2117 STATIC void 2118 pccbb_pcmcia_io_unmap(pch, win) 2119 pcmcia_chipset_handle_t pch; 2120 int win; 2121 { 2122 struct pcic_handle *ph = (struct pcic_handle *)pch; 2123 int reg; 2124 2125 if (win >= PCIC_IO_WINS || win < 0) { 2126 panic("pccbb_pcmcia_io_unmap: window out of range"); 2127 } 2128 2129 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2130 switch (win) { 2131 case 0: 2132 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2133 break; 2134 case 1: 2135 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2136 break; 2137 } 2138 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2139 2140 ph->ioalloc &= ~(1 << win); 2141 } 2142 2143 /* 2144 * static void pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 2145 * 2146 * This function enables the card. All information is stored in 2147 * the first argument, pcmcia_chipset_handle_t. 2148 */ 2149 static void 2150 pccbb_pcmcia_wait_ready(ph) 2151 struct pcic_handle *ph; 2152 { 2153 int i; 2154 2155 DPRINTF(("pccbb_pcmcia_wait_ready: status 0x%02x\n", 2156 Pcic_read(ph, PCIC_IF_STATUS))); 2157 2158 for (i = 0; i < 10000; i++) { 2159 if (Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) { 2160 return; 2161 } 2162 delay(500); 2163 #ifdef CBB_DEBUG 2164 if ((i > 5000) && (i % 100 == 99)) 2165 printf("."); 2166 #endif 2167 } 2168 2169 #ifdef DIAGNOSTIC 2170 printf("pcic_wait_ready: ready never happened, status = %02x\n", 2171 Pcic_read(ph, PCIC_IF_STATUS)); 2172 #endif 2173 } 2174 2175 /* 2176 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2177 * 2178 * This function enables the card. All information is stored in 2179 * the first argument, pcmcia_chipset_handle_t. 2180 */ 2181 STATIC void 2182 pccbb_pcmcia_socket_enable(pch) 2183 pcmcia_chipset_handle_t pch; 2184 { 2185 struct pcic_handle *ph = (struct pcic_handle *)pch; 2186 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2187 int cardtype, win; 2188 u_int8_t power, intr; 2189 pcireg_t spsr; 2190 int voltage; 2191 #define PCIC_INTR_PCI PCIC_INTR_ENABLE 2192 2193 /* this bit is mostly stolen from pcic_attach_card */ 2194 2195 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2196 2197 /* get card Vcc info */ 2198 2199 spsr = 2200 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2201 CB_SOCKET_STAT); 2202 if (spsr & CB_SOCKET_STAT_5VCARD) { 2203 DPRINTF(("5V card\n")); 2204 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2205 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2206 DPRINTF(("3V card\n")); 2207 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2208 } else { 2209 printf("?V card, 0x%x\n", spsr); /* XXX */ 2210 return; 2211 } 2212 2213 /* assert reset bit */ 2214 intr = Pcic_read(ph, PCIC_INTR); 2215 intr &= ~(PCIC_INTR_RESET | PCIC_INTR_ENABLE | PCIC_INTR_CARDTYPE_MASK); 2216 Pcic_write(ph, PCIC_INTR, intr); 2217 2218 /* disable socket i/o: negate output enable bit */ 2219 2220 power = Pcic_read(ph, PCIC_PWRCTL); 2221 power &= ~PCIC_PWRCTL_OE; 2222 Pcic_write(ph, PCIC_PWRCTL, power); 2223 2224 /* power down the socket to reset it, clear the card reset pin */ 2225 2226 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2227 2228 /* 2229 * wait 200ms until power fails (Tpf). Then, wait 100ms since 2230 * we are changing Vcc (Toff). 2231 */ 2232 /* delay(300*1000); too much */ 2233 2234 /* power up the socket */ 2235 pccbb_power(sc, voltage); 2236 2237 /* 2238 * wait 100ms until power raise (Tpr) and 20ms to become 2239 * stable (Tsu(Vcc)). 2240 * 2241 * some machines require some more time to be settled 2242 * (another 200ms is added here). 2243 */ 2244 /* delay((100 + 20 + 200)*1000); too much */ 2245 2246 power = Pcic_read(ph, PCIC_PWRCTL); 2247 power |= PCIC_PWRCTL_OE; 2248 Pcic_write(ph, PCIC_PWRCTL, power); 2249 2250 /* 2251 * hold RESET at least 10us. 2252 */ 2253 delay(10); 2254 delay(2 * 1000); /* XXX: TI1130 requires it. */ 2255 delay(20 * 1000); /* XXX: TI1130 requires it. */ 2256 2257 /* clear the reset flag */ 2258 2259 intr |= PCIC_INTR_RESET; 2260 Pcic_write(ph, PCIC_INTR, intr); 2261 2262 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 2263 2264 delay(20000); 2265 2266 /* wait for the chip to finish initializing */ 2267 2268 pccbb_pcmcia_wait_ready(ph); 2269 2270 /* zero out the address windows */ 2271 2272 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2273 2274 /* set the card type */ 2275 2276 cardtype = pcmcia_card_gettype(ph->pcmcia); 2277 2278 intr |= PCIC_INTR_PCI; 2279 intr |= ((cardtype == PCMCIA_IFTYPE_IO) ? 2280 PCIC_INTR_CARDTYPE_IO : PCIC_INTR_CARDTYPE_MEM); 2281 Pcic_write(ph, PCIC_INTR, intr); 2282 2283 DPRINTF(("%s: pccbb_pcmcia_socket_enable %02x cardtype %s %02x\n", 2284 ph->ph_parent->dv_xname, ph->sock, 2285 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2286 2287 /* reinstall all the memory and io mappings */ 2288 2289 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2290 if (ph->memalloc & (1 << win)) { 2291 pccbb_pcmcia_do_mem_map(ph, win); 2292 } 2293 } 2294 2295 for (win = 0; win < PCIC_IO_WINS; ++win) { 2296 if (ph->ioalloc & (1 << win)) { 2297 pccbb_pcmcia_do_io_map(ph, win); 2298 } 2299 } 2300 } 2301 2302 /* 2303 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2304 * 2305 * This function disables the card. All information is stored in 2306 * the first argument, pcmcia_chipset_handle_t. 2307 */ 2308 STATIC void 2309 pccbb_pcmcia_socket_disable(pch) 2310 pcmcia_chipset_handle_t pch; 2311 { 2312 struct pcic_handle *ph = (struct pcic_handle *)pch; 2313 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2314 u_int8_t power, intr; 2315 2316 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2317 2318 /* reset signal asserting... */ 2319 2320 intr = Pcic_read(ph, PCIC_INTR); 2321 intr &= ~(PCIC_INTR_RESET | PCIC_INTR_ENABLE | PCIC_INTR_CARDTYPE_MASK); 2322 Pcic_write(ph, PCIC_INTR, intr); 2323 delay(2 * 1000); 2324 2325 /* power down the socket */ 2326 power = Pcic_read(ph, PCIC_PWRCTL); 2327 power &= ~PCIC_PWRCTL_OE; 2328 Pcic_write(ph, PCIC_PWRCTL, power); 2329 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2330 /* 2331 * wait 300ms until power fails (Tpf). 2332 */ 2333 delay(300 * 1000); 2334 } 2335 2336 /* 2337 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2338 * 2339 * This function detects whether a card is in the slot or not. 2340 * If a card is inserted, return 1. Otherwise, return 0. 2341 */ 2342 STATIC int 2343 pccbb_pcmcia_card_detect(pch) 2344 pcmcia_chipset_handle_t pch; 2345 { 2346 struct pcic_handle *ph = (struct pcic_handle *)pch; 2347 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2348 2349 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2350 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2351 } 2352 2353 #if 0 2354 STATIC int 2355 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2356 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2357 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2358 #endif 2359 /* 2360 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2361 * bus_size_t size, 2362 * struct pcmcia_mem_handle *pcmhp) 2363 * 2364 * This function only allocates memory region for pccard. This 2365 * function never maps the allcated region to pccard memory area. 2366 * 2367 * XXX: Why the argument of start address is not in? 2368 */ 2369 STATIC int 2370 pccbb_pcmcia_mem_alloc(pch, size, pcmhp) 2371 pcmcia_chipset_handle_t pch; 2372 bus_size_t size; 2373 struct pcmcia_mem_handle *pcmhp; 2374 { 2375 struct pcic_handle *ph = (struct pcic_handle *)pch; 2376 bus_space_handle_t memh; 2377 bus_addr_t addr; 2378 bus_size_t sizepg; 2379 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2380 #if rbus 2381 rbus_tag_t rb; 2382 #endif 2383 2384 /* out of sc->memh, allocate as many pages as necessary */ 2385 2386 /* convert size to PCIC pages */ 2387 /* 2388 * This is not enough; when the requested region is on the page 2389 * boundaries, this may calculate wrong result. 2390 */ 2391 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2392 #if 0 2393 if (sizepg > PCIC_MAX_MEM_PAGES) { 2394 return 1; 2395 } 2396 #endif 2397 2398 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2399 return 1; 2400 } 2401 2402 addr = 0; /* XXX gcc -Wuninitialized */ 2403 2404 #if rbus 2405 rb = sc->sc_rbus_memt; 2406 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2407 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2408 &addr, &memh)) { 2409 return 1; 2410 } 2411 #else 2412 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2413 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2414 0, /* boundary */ 2415 0, /* flags */ 2416 &addr, &memh)) { 2417 return 1; 2418 } 2419 #endif 2420 2421 DPRINTF( 2422 ("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, realsize 0x%lx\n", 2423 addr, size, sizepg * PCIC_MEM_PAGESIZE)); 2424 2425 pcmhp->memt = sc->sc_memt; 2426 pcmhp->memh = memh; 2427 pcmhp->addr = addr; 2428 pcmhp->size = size; 2429 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2430 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2431 pcmhp->mhandle = 0; 2432 /* No offset??? Funny. */ 2433 2434 return 0; 2435 } 2436 2437 /* 2438 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2439 * struct pcmcia_mem_handle *pcmhp) 2440 * 2441 * This function release the memory space allocated by the fuction 2442 * pccbb_pcmcia_mem_alloc(). 2443 */ 2444 STATIC void 2445 pccbb_pcmcia_mem_free(pch, pcmhp) 2446 pcmcia_chipset_handle_t pch; 2447 struct pcmcia_mem_handle *pcmhp; 2448 { 2449 #if rbus 2450 struct pcic_handle *ph = (struct pcic_handle *)pch; 2451 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2452 2453 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2454 #else 2455 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2456 #endif 2457 } 2458 2459 /* 2460 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2461 * 2462 * This function release the memory space allocated by the fuction 2463 * pccbb_pcmcia_mem_alloc(). 2464 */ 2465 STATIC void 2466 pccbb_pcmcia_do_mem_map(ph, win) 2467 struct pcic_handle *ph; 2468 int win; 2469 { 2470 int regbase_win; 2471 bus_addr_t phys_addr; 2472 bus_addr_t phys_end; 2473 2474 #define PCIC_SMM_START_LOW 0 2475 #define PCIC_SMM_START_HIGH 1 2476 #define PCIC_SMM_STOP_LOW 2 2477 #define PCIC_SMM_STOP_HIGH 3 2478 #define PCIC_CMA_LOW 4 2479 #define PCIC_CMA_HIGH 5 2480 2481 u_int8_t start_low, start_high = 0; 2482 u_int8_t stop_low, stop_high; 2483 u_int8_t off_low, off_high; 2484 u_int8_t mem_window; 2485 int reg; 2486 2487 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2488 int mem8 = 2489 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2490 || (kind == PCMCIA_MEM_ATTR); 2491 2492 regbase_win = 0x10 + win * 0x08; 2493 2494 phys_addr = ph->mem[win].addr; 2495 phys_end = phys_addr + ph->mem[win].size; 2496 2497 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2498 phys_addr, phys_end, ph->mem[win].offset)); 2499 2500 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2501 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2502 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2503 2504 /* bit 19:12 */ 2505 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2506 /* bit 23:20 and bit 7 on */ 2507 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2508 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2509 /* bit 31:24, for 32-bit address */ 2510 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2511 2512 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2513 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2514 2515 if (((struct pccbb_softc *)ph-> 2516 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2517 Pcic_write(ph, 0x40 + win, mem_window); 2518 } 2519 2520 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2521 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2522 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2523 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2524 2525 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2526 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2527 2528 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2529 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2530 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2531 | ((kind == PCMCIA_MEM_ATTR) ? 2532 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2533 2534 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2535 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2536 2537 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2538 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2539 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2540 2541 #if defined CBB_DEBUG 2542 { 2543 int r1, r2, r3, r4, r5, r6, r7 = 0; 2544 2545 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2546 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2547 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2548 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2549 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2550 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2551 if (((struct pccbb_softc *)(ph-> 2552 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2553 r7 = Pcic_read(ph, 0x40 + win); 2554 } 2555 2556 DPRINTF(("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2557 "%02x%02x", win, r1, r2, r3, r4, r5, r6)); 2558 if (((struct pccbb_softc *)(ph-> 2559 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2560 DPRINTF((" %02x", r7)); 2561 } 2562 DPRINTF(("\n")); 2563 } 2564 #endif 2565 } 2566 2567 /* 2568 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2569 * bus_addr_t card_addr, bus_size_t size, 2570 * struct pcmcia_mem_handle *pcmhp, 2571 * bus_addr_t *offsetp, int *windowp) 2572 * 2573 * This function maps memory space allocated by the fuction 2574 * pccbb_pcmcia_mem_alloc(). 2575 */ 2576 STATIC int 2577 pccbb_pcmcia_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 2578 pcmcia_chipset_handle_t pch; 2579 int kind; 2580 bus_addr_t card_addr; 2581 bus_size_t size; 2582 struct pcmcia_mem_handle *pcmhp; 2583 bus_addr_t *offsetp; 2584 int *windowp; 2585 { 2586 struct pcic_handle *ph = (struct pcic_handle *)pch; 2587 bus_addr_t busaddr; 2588 long card_offset; 2589 int win; 2590 2591 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2592 if ((ph->memalloc & (1 << win)) == 0) { 2593 ph->memalloc |= (1 << win); 2594 break; 2595 } 2596 } 2597 2598 if (win == PCIC_MEM_WINS) { 2599 return 1; 2600 } 2601 2602 *windowp = win; 2603 2604 /* XXX this is pretty gross */ 2605 2606 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2607 panic("pccbb_pcmcia_mem_map memt is bogus"); 2608 } 2609 2610 busaddr = pcmhp->addr; 2611 2612 /* 2613 * compute the address offset to the pcmcia address space for the 2614 * pcic. this is intentionally signed. The masks and shifts below 2615 * will cause TRT to happen in the pcic registers. Deal with making 2616 * sure the address is aligned, and return the alignment offset. 2617 */ 2618 2619 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2620 card_addr -= *offsetp; 2621 2622 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2623 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2624 (u_long) card_addr)); 2625 2626 /* 2627 * include the offset in the size, and decrement size by one, since 2628 * the hw wants start/stop 2629 */ 2630 size += *offsetp - 1; 2631 2632 card_offset = (((long)card_addr) - ((long)busaddr)); 2633 2634 ph->mem[win].addr = busaddr; 2635 ph->mem[win].size = size; 2636 ph->mem[win].offset = card_offset; 2637 ph->mem[win].kind = kind; 2638 2639 pccbb_pcmcia_do_mem_map(ph, win); 2640 2641 return 0; 2642 } 2643 2644 /* 2645 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2646 * int window) 2647 * 2648 * This function unmaps memory space which mapped by the fuction 2649 * pccbb_pcmcia_mem_map(). 2650 */ 2651 STATIC void 2652 pccbb_pcmcia_mem_unmap(pch, window) 2653 pcmcia_chipset_handle_t pch; 2654 int window; 2655 { 2656 struct pcic_handle *ph = (struct pcic_handle *)pch; 2657 int reg; 2658 2659 if (window >= PCIC_MEM_WINS) { 2660 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2661 } 2662 2663 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2664 reg &= ~(1 << window); 2665 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2666 2667 ph->memalloc &= ~(1 << window); 2668 } 2669 2670 #if defined PCCBB_PCMCIA_POLL 2671 struct pccbb_poll_str { 2672 void *arg; 2673 int (*func) __P((void *)); 2674 int level; 2675 struct pcic_handle *ph; 2676 int count; 2677 int num; 2678 }; 2679 2680 static struct pccbb_poll_str pccbb_poll[10]; 2681 static int pccbb_poll_n = 0; 2682 2683 static void pccbb_pcmcia_poll __P((void *arg)); 2684 2685 static void 2686 pccbb_pcmcia_poll(arg) 2687 void *arg; 2688 { 2689 struct pccbb_poll_str *poll = arg; 2690 struct pcic_handle *ph = poll->ph; 2691 struct pccbb_softc *sc = ph->sc; 2692 int s; 2693 u_int32_t spsr; /* socket present-state reg */ 2694 2695 timeout(pccbb_pcmcia_poll, arg, hz * 2); 2696 switch (poll->level) { 2697 case IPL_NET: 2698 s = splnet(); 2699 break; 2700 case IPL_BIO: 2701 s = splbio(); 2702 break; 2703 case IPL_TTY: /* fallthrough */ 2704 default: 2705 s = spltty(); 2706 break; 2707 } 2708 2709 spsr = 2710 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2711 CB_SOCKET_STAT); 2712 2713 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2714 if (!(spsr & 0x40)) /* CINT low */ 2715 #else 2716 if (1) 2717 #endif 2718 { 2719 if ((*poll->func) (poll->arg) > 0) { 2720 ++poll->count; 2721 // printf("intr: reported from poller, 0x%x\n", spsr); 2722 #if defined LEVEL2 2723 } else { 2724 printf("intr: miss! 0x%x\n", spsr); 2725 #endif 2726 } 2727 } 2728 splx(s); 2729 } 2730 #endif /* defined CB_PCMCIA_POLL */ 2731 2732 /* 2733 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2734 * struct pcmcia_function *pf, 2735 * int ipl, 2736 * int (*func)(void *), 2737 * void *arg); 2738 * 2739 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2740 */ 2741 STATIC void * 2742 pccbb_pcmcia_intr_establish(pch, pf, ipl, func, arg) 2743 pcmcia_chipset_handle_t pch; 2744 struct pcmcia_function *pf; 2745 int ipl; 2746 int (*func) __P((void *)); 2747 void *arg; 2748 { 2749 struct pcic_handle *ph = (struct pcic_handle *)pch; 2750 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2751 2752 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2753 /* what should I do? */ 2754 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2755 DPRINTF( 2756 ("%s does not provide edge nor pulse interrupt\n", 2757 sc->sc_dev.dv_xname)); 2758 return NULL; 2759 } 2760 /* 2761 * XXX Noooooo! The interrupt flag must set properly!! 2762 * dumb pcmcia driver!! 2763 */ 2764 } 2765 2766 return pccbb_intr_establish(sc, IST_LEVEL, ipl, func, arg); 2767 } 2768 2769 /* 2770 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2771 * void *ih) 2772 * 2773 * This function disables PC-Card interrupt. 2774 */ 2775 STATIC void 2776 pccbb_pcmcia_intr_disestablish(pch, ih) 2777 pcmcia_chipset_handle_t pch; 2778 void *ih; 2779 { 2780 struct pcic_handle *ph = (struct pcic_handle *)pch; 2781 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2782 2783 pccbb_intr_disestablish(sc, ih); 2784 } 2785 2786 #if rbus 2787 /* 2788 * static int 2789 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2790 * bus_addr_t addr, bus_size_t size, 2791 * bus_addr_t mask, bus_size_t align, 2792 * int flags, bus_addr_t *addrp; 2793 * bus_space_handle_t *bshp) 2794 * 2795 * This function allocates a portion of memory or io space for 2796 * clients. This function is called from CardBus card drivers. 2797 */ 2798 static int 2799 pccbb_rbus_cb_space_alloc(ct, rb, addr, size, mask, align, flags, addrp, bshp) 2800 cardbus_chipset_tag_t ct; 2801 rbus_tag_t rb; 2802 bus_addr_t addr; 2803 bus_size_t size; 2804 bus_addr_t mask; 2805 bus_size_t align; 2806 int flags; 2807 bus_addr_t *addrp; 2808 bus_space_handle_t *bshp; 2809 { 2810 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2811 2812 DPRINTF( 2813 ("pccbb_rbus_cb_space_alloc: adr %lx, size %lx, mask %lx, align %lx\n", 2814 addr, size, mask, align)); 2815 2816 if (align == 0) { 2817 align = size; 2818 } 2819 2820 if (rb->rb_bt == sc->sc_memt) { 2821 if (align < 16) { 2822 return 1; 2823 } 2824 } else if (rb->rb_bt == sc->sc_iot) { 2825 if (align < 4) { 2826 return 1; 2827 } 2828 } else { 2829 DPRINTF( 2830 ("pccbb_rbus_cb_space_alloc: Bus space tag %x is NOT used.\n", 2831 rb->rb_bt)); 2832 return 1; 2833 /* XXX: panic here? */ 2834 } 2835 2836 /* XXX: hack for avoiding ISA image */ 2837 if (mask < 0x3ff) { 2838 mask = 0x3ff; 2839 addr = 0x300; 2840 } 2841 2842 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 2843 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 2844 return 1; 2845 } 2846 2847 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 2848 2849 return 0; 2850 } 2851 2852 /* 2853 * static int 2854 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 2855 * bus_space_handle_t *bshp, bus_size_t size); 2856 * 2857 * This function is called from CardBus card drivers. 2858 */ 2859 static int 2860 pccbb_rbus_cb_space_free(ct, rb, bsh, size) 2861 cardbus_chipset_tag_t ct; 2862 rbus_tag_t rb; 2863 bus_space_handle_t bsh; 2864 bus_size_t size; 2865 { 2866 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2867 bus_space_tag_t bt = rb->rb_bt; 2868 2869 pccbb_close_win(sc, bt, bsh, size); 2870 2871 if (bt == sc->sc_memt) { 2872 } else if (bt == sc->sc_iot) { 2873 } else { 2874 return 1; 2875 /* XXX: panic here? */ 2876 } 2877 2878 return rbus_space_free(rb, bsh, size, NULL); 2879 } 2880 #endif /* rbus */ 2881 2882 #if rbus 2883 2884 static int 2885 pccbb_open_win(sc, bst, addr, size, bsh, flags) 2886 struct pccbb_softc *sc; 2887 bus_space_tag_t bst; 2888 bus_addr_t addr; 2889 bus_size_t size; 2890 bus_space_handle_t bsh; 2891 int flags; 2892 { 2893 struct pccbb_win_chain **top; 2894 bus_addr_t align; 2895 2896 top = &sc->sc_iowindow; 2897 align = 0x04; 2898 if (sc->sc_memt == bst) { 2899 top = &sc->sc_memwindow; 2900 align = 0x1000; 2901 DPRINTF(("using memory window, %x %x %x\n\n", 2902 sc->sc_iot, sc->sc_memt, bst)); 2903 } 2904 2905 if (pccbb_winlist_insert(top, addr, size, bsh, flags)) { 2906 printf("winlist insert fails:\n"); 2907 } 2908 pccbb_winset(align, sc, bst); 2909 2910 return 0; 2911 } 2912 2913 static int 2914 pccbb_close_win(sc, bst, bsh, size) 2915 struct pccbb_softc *sc; 2916 bus_space_tag_t bst; 2917 bus_space_handle_t bsh; 2918 bus_size_t size; 2919 { 2920 struct pccbb_win_chain **top; 2921 bus_addr_t align; 2922 2923 top = &sc->sc_iowindow; 2924 align = 0x04; 2925 if (sc->sc_memt == bst) { 2926 top = &sc->sc_memwindow; 2927 align = 0x1000; 2928 } 2929 2930 if (pccbb_winlist_delete(top, bsh, size)) { 2931 printf("winlist delete fails:\n"); 2932 } 2933 pccbb_winset(align, sc, bst); 2934 2935 return 0; 2936 } 2937 2938 static int 2939 pccbb_winlist_insert(top, start, size, bsh, flags) 2940 struct pccbb_win_chain **top; 2941 bus_addr_t start; 2942 bus_size_t size; 2943 bus_space_handle_t bsh; 2944 int flags; 2945 { 2946 struct pccbb_win_chain *chainp = *top; 2947 struct pccbb_win_chain *before = *top; 2948 struct pccbb_win_chain *elem; 2949 2950 if (*top == NULL) { 2951 if (NULL == (elem = 2952 (struct pccbb_win_chain *)malloc(sizeof(struct 2953 pccbb_win_chain), M_DEVBUF, M_NOWAIT))) { 2954 return 1; /* fail */ 2955 } 2956 2957 elem->wc_start = start; 2958 elem->wc_end = start + size - 1; 2959 elem->wc_handle = bsh; 2960 elem->wc_flags = flags; 2961 2962 *top = elem; 2963 elem->wc_next = NULL; 2964 return 0; 2965 } 2966 2967 for (; chainp && chainp->wc_start <= start; chainp = chainp->wc_next) { 2968 before = chainp; 2969 } 2970 2971 if (chainp != NULL) { 2972 if (chainp->wc_start < start + size) { 2973 printf("fatal! 0x%lx 0x%lx\n", chainp->wc_start, 2974 start + size); 2975 return 1; 2976 } 2977 } 2978 if ((before != *top) && (before->wc_end >= start)) { 2979 printf("fatal!! 0x%lx 0x%lx\n", before->wc_end, start); 2980 return 1; 2981 } 2982 2983 if (NULL == (elem = 2984 (struct pccbb_win_chain *)malloc(sizeof(struct pccbb_win_chain), 2985 M_DEVBUF, M_NOWAIT))) { 2986 return 1; /* fail */ 2987 } 2988 2989 elem->wc_start = start; 2990 elem->wc_end = start + size - 1; 2991 elem->wc_handle = bsh; 2992 elem->wc_flags = flags; 2993 2994 elem->wc_next = chainp; 2995 if (chainp == *top) { 2996 *top = elem; 2997 } else { 2998 before->wc_next = elem; 2999 } 3000 return 0; 3001 } 3002 3003 static int 3004 pccbb_winlist_delete(top, bsh, size) 3005 struct pccbb_win_chain **top; 3006 bus_space_handle_t bsh; 3007 bus_size_t size; 3008 { 3009 struct pccbb_win_chain *chainp = *top; 3010 struct pccbb_win_chain **before = top; 3011 3012 for (; chainp && chainp->wc_handle != bsh; chainp = chainp->wc_next) { 3013 before = &chainp->wc_next; 3014 } 3015 3016 if (chainp == NULL) { 3017 return 1; /* fail: no candidate to remove */ 3018 } 3019 3020 if (chainp->wc_end - chainp->wc_start != size - 1) { 3021 printf("fatal!!! 0x%lx\n", chainp->wc_start); 3022 return 1; /* fail: no candidate to remove */ 3023 } 3024 3025 *before = chainp->wc_next; 3026 free(chainp, M_DEVBUF); 3027 3028 return 0; 3029 } 3030 3031 static void 3032 pccbb_winset(align, sc, bst) 3033 bus_addr_t align; 3034 struct pccbb_softc *sc; 3035 bus_space_tag_t bst; 3036 { 3037 pci_chipset_tag_t pc; 3038 pcitag_t tag; 3039 bus_addr_t mask = ~(align - 1); 3040 struct { 3041 cardbusreg_t win_start; 3042 cardbusreg_t win_limit; 3043 int win_flags; 3044 } win[2]; 3045 struct pccbb_win_chain *chainp; 3046 int offs; 3047 3048 win[0].win_start = 0xffffffff; 3049 win[0].win_limit = 0; 3050 win[1].win_start = 0xffffffff; 3051 win[1].win_limit = 0; 3052 3053 chainp = sc->sc_iowindow; 3054 offs = 0x2c; 3055 if (sc->sc_memt == bst) { 3056 chainp = sc->sc_memwindow; 3057 offs = 0x1c; 3058 } 3059 3060 if (chainp) { 3061 win[0].win_start = chainp->wc_start & mask; 3062 win[0].win_limit = chainp->wc_end & mask; 3063 win[0].win_flags = chainp->wc_flags; 3064 chainp = chainp->wc_next; 3065 } 3066 3067 for (; chainp; chainp = chainp->wc_next) { 3068 if (win[1].win_start == 0xffffffff) { 3069 /* window 1 is not used */ 3070 if ((win[0].win_flags == chainp->wc_flags) && 3071 (win[0].win_limit + align >= 3072 (chainp->wc_start & mask))) { 3073 /* concatinate */ 3074 win[0].win_limit = chainp->wc_end & mask; 3075 } else { 3076 /* make new window */ 3077 win[1].win_start = chainp->wc_start & mask; 3078 win[1].win_limit = chainp->wc_end & mask; 3079 win[1].win_flags = chainp->wc_flags; 3080 } 3081 continue; 3082 } 3083 3084 /* Both windows are engagad. */ 3085 if (win[0].win_flags == win[1].win_flags) { 3086 /* same flags */ 3087 if (win[0].win_flags == chainp->wc_flags) { 3088 if (win[1].win_start - (win[0].win_limit + 3089 align) < 3090 (chainp->wc_start & mask) - 3091 ((chainp->wc_end & mask) + align)) { 3092 /* 3093 * merge window 0 and 1, and set win1 3094 * to chainp 3095 */ 3096 win[0].win_limit = win[1].win_limit; 3097 win[1].win_start = 3098 chainp->wc_start & mask; 3099 win[1].win_limit = 3100 chainp->wc_end & mask; 3101 } else { 3102 win[1].win_limit = 3103 chainp->wc_end & mask; 3104 } 3105 } else { 3106 /* different flags */ 3107 3108 /* concatinate win0 and win1 */ 3109 win[0].win_limit = win[1].win_limit; 3110 /* allocate win[1] to new space */ 3111 win[1].win_start = chainp->wc_start & mask; 3112 win[1].win_limit = chainp->wc_end & mask; 3113 win[1].win_flags = chainp->wc_flags; 3114 } 3115 } else { 3116 /* the flags of win[0] and win[1] is different */ 3117 if (win[0].win_flags == chainp->wc_flags) { 3118 win[0].win_limit = chainp->wc_end & mask; 3119 /* 3120 * XXX this creates overlapping windows, so 3121 * what should the poor bridge do if one is 3122 * cachable, and the other is not? 3123 */ 3124 printf("%s: overlapping windows\n", 3125 sc->sc_dev.dv_xname); 3126 } else { 3127 win[1].win_limit = chainp->wc_end & mask; 3128 } 3129 } 3130 } 3131 3132 pc = sc->sc_pc; 3133 tag = sc->sc_tag; 3134 pci_conf_write(pc, tag, offs, win[0].win_start); 3135 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3136 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3137 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3138 DPRINTF(("--pccbb_winset: win0 [%x, %lx), win1 [%x, %lx)\n", 3139 pci_conf_read(pc, tag, offs), 3140 pci_conf_read(pc, tag, offs + 4) + align, 3141 pci_conf_read(pc, tag, offs + 8), 3142 pci_conf_read(pc, tag, offs + 12) + align)); 3143 3144 if (bst == sc->sc_memt) { 3145 if (win[0].win_flags & PCCBB_MEM_CACHABLE) { 3146 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3147 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3148 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3149 } 3150 if (win[1].win_flags & PCCBB_MEM_CACHABLE) { 3151 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3152 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3153 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3154 } 3155 } 3156 } 3157 3158 #endif /* rbus */ 3159 3160 static void 3161 pccbb_powerhook(why, arg) 3162 int why; 3163 void *arg; 3164 { 3165 struct pccbb_softc *sc = arg; 3166 u_int32_t reg; 3167 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3168 bus_space_handle_t base_memh = sc->sc_base_memh; 3169 3170 DPRINTF(("%s: power: why %d\n", sc->sc_dev.dv_xname, why)); 3171 3172 if (why == PWR_RESUME) { 3173 /* CSC Interrupt: Card detect interrupt on */ 3174 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3175 /* Card detect intr is turned on. */ 3176 reg |= CB_SOCKET_MASK_CD; 3177 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3178 /* reset interrupt */ 3179 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3180 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3181 3182 /* 3183 * check for card insertion or removal during suspend period. 3184 * XXX: the code can't cope with card swap (remove then insert). 3185 * how can we detect such situation? 3186 */ 3187 if (why == PWR_RESUME) 3188 (void)pccbbintr(sc); 3189 } 3190 } 3191
Indexes created Thu Sep 25 16:09:42 GMT 2025