pccbb.c revision 1.28
1 /* $NetBSD: pccbb.c,v 1.28 2000/03/10 11:08:49 haya Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 #define CBB_DEBUG 35 #define SHOW_REGS 36 #define PCCBB_PCMCIA_POLL 37 */ 38 /* #define CBB_DEBUG */ 39 40 /* 41 #define CB_PCMCIA_POLL 42 #define CB_PCMCIA_POLL_ONLY 43 #define LEVEL2 44 */ 45 46 #include <sys/types.h> 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/kernel.h> 50 #include <sys/errno.h> 51 #include <sys/ioctl.h> 52 #include <sys/syslog.h> 53 #include <sys/device.h> 54 #include <sys/malloc.h> 55 56 #include <machine/intr.h> 57 #include <machine/bus.h> 58 59 #include <dev/pci/pcivar.h> 60 #include <dev/pci/pcireg.h> 61 #include <dev/pci/pcidevs.h> 62 63 #include <dev/pci/pccbbreg.h> 64 65 #include <dev/cardbus/cardslotvar.h> 66 67 #include <dev/cardbus/cardbusvar.h> 68 69 #include <dev/pcmcia/pcmciareg.h> 70 #include <dev/pcmcia/pcmciavar.h> 71 72 #include <dev/ic/i82365reg.h> 73 #include <dev/ic/i82365var.h> 74 #include <dev/pci/pccbbvar.h> 75 76 #include "locators.h" 77 78 #ifndef __NetBSD_Version__ 79 struct cfdriver cbb_cd = { 80 NULL, "cbb", DV_DULL 81 }; 82 #endif 83 84 #if defined CBB_DEBUG 85 #define DPRINTF(x) printf x 86 #define STATIC 87 #else 88 #define DPRINTF(x) 89 #define STATIC static 90 #endif 91 92 #ifdef __BROKEN_INDIRECT_CONFIG 93 int pcicbbmatch __P((struct device *, void *, void *)); 94 #else 95 int pcicbbmatch __P((struct device *, struct cfdata *, void *)); 96 #endif 97 void pccbbattach __P((struct device *, struct device *, void *)); 98 int pccbbintr __P((void *)); 99 static void pci113x_insert __P((void *)); 100 static int pccbbintr_function __P((struct pccbb_softc *)); 101 102 static int pccbb_detect_card __P((struct pccbb_softc *)); 103 104 static void pccbb_pcmcia_write __P((struct pcic_handle *, int, u_int8_t)); 105 static u_int8_t pccbb_pcmcia_read __P((struct pcic_handle *, int)); 106 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 107 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 108 109 STATIC int cb_reset __P((struct pccbb_softc *)); 110 STATIC int cb_detect_voltage __P((struct pccbb_softc *)); 111 STATIC int cbbprint __P((void *, const char *)); 112 113 static int cb_chipset __P((u_int32_t, int *)); 114 STATIC void pccbb_pcmcia_attach_setup __P((struct pccbb_softc *, 115 struct pcmciabus_attach_args *)); 116 #if 0 117 STATIC void pccbb_pcmcia_attach_card __P((struct pcic_handle *)); 118 STATIC void pccbb_pcmcia_detach_card __P((struct pcic_handle *, int)); 119 STATIC void pccbb_pcmcia_deactivate_card __P((struct pcic_handle *)); 120 #endif 121 122 STATIC int pccbb_ctrl __P((cardbus_chipset_tag_t, int)); 123 STATIC int pccbb_power __P((cardbus_chipset_tag_t, int)); 124 STATIC int pccbb_cardenable __P((struct pccbb_softc * sc, int function)); 125 #if !rbus 126 static int pccbb_io_open __P((cardbus_chipset_tag_t, int, u_int32_t, 127 u_int32_t)); 128 static int pccbb_io_close __P((cardbus_chipset_tag_t, int)); 129 static int pccbb_mem_open __P((cardbus_chipset_tag_t, int, u_int32_t, 130 u_int32_t)); 131 static int pccbb_mem_close __P((cardbus_chipset_tag_t, int)); 132 #endif /* !rbus */ 133 static void *pccbb_intr_establish __P((struct pccbb_softc *, int irq, 134 int level, int (*ih) (void *), void *sc)); 135 static void pccbb_intr_disestablish __P((struct pccbb_softc *, void *ih)); 136 137 static void *pccbb_cb_intr_establish __P((cardbus_chipset_tag_t, int irq, 138 int level, int (*ih) (void *), void *sc)); 139 static void pccbb_cb_intr_disestablish __P((cardbus_chipset_tag_t ct, void *ih)); 140 141 static cardbustag_t pccbb_make_tag __P((cardbus_chipset_tag_t, int, int, int)); 142 static void pccbb_free_tag __P((cardbus_chipset_tag_t, cardbustag_t)); 143 static cardbusreg_t pccbb_conf_read __P((cardbus_chipset_tag_t, cardbustag_t, 144 int)); 145 static void pccbb_conf_write __P((cardbus_chipset_tag_t, cardbustag_t, int, 146 cardbusreg_t)); 147 static void pccbb_chipinit __P((struct pccbb_softc *)); 148 149 STATIC int pccbb_pcmcia_mem_alloc __P((pcmcia_chipset_handle_t, bus_size_t, 150 struct pcmcia_mem_handle *)); 151 STATIC void pccbb_pcmcia_mem_free __P((pcmcia_chipset_handle_t, 152 struct pcmcia_mem_handle *)); 153 STATIC int pccbb_pcmcia_mem_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 154 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *)); 155 STATIC void pccbb_pcmcia_mem_unmap __P((pcmcia_chipset_handle_t, int)); 156 STATIC int pccbb_pcmcia_io_alloc __P((pcmcia_chipset_handle_t, bus_addr_t, 157 bus_size_t, bus_size_t, struct pcmcia_io_handle *)); 158 STATIC void pccbb_pcmcia_io_free __P((pcmcia_chipset_handle_t, 159 struct pcmcia_io_handle *)); 160 STATIC int pccbb_pcmcia_io_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 161 bus_size_t, struct pcmcia_io_handle *, int *)); 162 STATIC void pccbb_pcmcia_io_unmap __P((pcmcia_chipset_handle_t, int)); 163 STATIC void *pccbb_pcmcia_intr_establish __P((pcmcia_chipset_handle_t, 164 struct pcmcia_function *, int, int (*)(void *), void *)); 165 STATIC void pccbb_pcmcia_intr_disestablish __P((pcmcia_chipset_handle_t, 166 void *)); 167 STATIC void pccbb_pcmcia_socket_enable __P((pcmcia_chipset_handle_t)); 168 STATIC void pccbb_pcmcia_socket_disable __P((pcmcia_chipset_handle_t)); 169 STATIC int pccbb_pcmcia_card_detect __P((pcmcia_chipset_handle_t pch)); 170 171 static void pccbb_pcmcia_do_io_map __P((struct pcic_handle *, int)); 172 static void pccbb_pcmcia_wait_ready __P((struct pcic_handle *)); 173 static void pccbb_pcmcia_do_mem_map __P((struct pcic_handle *, int)); 174 static void pccbb_powerhook __P((int, void *)); 175 176 /* bus-space allocation and disallocation functions */ 177 #if rbus 178 179 static int pccbb_rbus_cb_space_alloc __P((cardbus_chipset_tag_t, rbus_tag_t, 180 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 181 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp)); 182 static int pccbb_rbus_cb_space_free __P((cardbus_chipset_tag_t, rbus_tag_t, 183 bus_space_handle_t, bus_size_t)); 184 185 #endif /* rbus */ 186 187 #if rbus 188 189 static int pccbb_open_win __P((struct pccbb_softc *, bus_space_tag_t, 190 bus_addr_t, bus_size_t, bus_space_handle_t, int flags)); 191 static int pccbb_close_win __P((struct pccbb_softc *, bus_space_tag_t, 192 bus_space_handle_t, bus_size_t)); 193 static int pccbb_winlist_insert __P((struct pccbb_win_chain_head *, bus_addr_t, 194 bus_size_t, bus_space_handle_t, int)); 195 static int pccbb_winlist_delete __P((struct pccbb_win_chain_head *, 196 bus_space_handle_t, bus_size_t)); 197 static void pccbb_winset __P((bus_addr_t align, struct pccbb_softc *, 198 bus_space_tag_t)); 199 void pccbb_winlist_show(struct pccbb_win_chain *); 200 201 #endif /* rbus */ 202 203 /* for config_defer */ 204 static void pccbb_pci_callback __P((struct device *)); 205 206 #if defined SHOW_REGS 207 static void cb_show_regs __P((pci_chipset_tag_t pc, pcitag_t tag, 208 bus_space_tag_t memt, bus_space_handle_t memh)); 209 #endif 210 211 struct cfattach cbb_pci_ca = { 212 sizeof(struct pccbb_softc), pcicbbmatch, pccbbattach 213 }; 214 215 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 216 pccbb_pcmcia_mem_alloc, 217 pccbb_pcmcia_mem_free, 218 pccbb_pcmcia_mem_map, 219 pccbb_pcmcia_mem_unmap, 220 pccbb_pcmcia_io_alloc, 221 pccbb_pcmcia_io_free, 222 pccbb_pcmcia_io_map, 223 pccbb_pcmcia_io_unmap, 224 pccbb_pcmcia_intr_establish, 225 pccbb_pcmcia_intr_disestablish, 226 pccbb_pcmcia_socket_enable, 227 pccbb_pcmcia_socket_disable, 228 pccbb_pcmcia_card_detect 229 }; 230 231 #if rbus 232 static struct cardbus_functions pccbb_funcs = { 233 pccbb_rbus_cb_space_alloc, 234 pccbb_rbus_cb_space_free, 235 pccbb_cb_intr_establish, 236 pccbb_cb_intr_disestablish, 237 pccbb_ctrl, 238 pccbb_power, 239 pccbb_make_tag, 240 pccbb_free_tag, 241 pccbb_conf_read, 242 pccbb_conf_write, 243 }; 244 #else 245 static struct cardbus_functions pccbb_funcs = { 246 pccbb_ctrl, 247 pccbb_power, 248 pccbb_mem_open, 249 pccbb_mem_close, 250 pccbb_io_open, 251 pccbb_io_close, 252 pccbb_cb_intr_establish, 253 pccbb_cb_intr_disestablish, 254 pccbb_make_tag, 255 pccbb_conf_read, 256 pccbb_conf_write, 257 }; 258 #endif 259 260 int 261 pcicbbmatch(parent, match, aux) 262 struct device *parent; 263 #ifdef __BROKEN_INDIRECT_CONFIG 264 void *match; 265 #else 266 struct cfdata *match; 267 #endif 268 void *aux; 269 { 270 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 271 272 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 273 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 274 PCI_INTERFACE(pa->pa_class) == 0) { 275 return 1; 276 } 277 278 return 0; 279 } 280 281 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 282 | ((prod) << PCI_PRODUCT_SHIFT)) 283 284 struct yenta_chipinfo { 285 pcireg_t yc_id; /* vendor tag | product tag */ 286 int yc_chiptype; 287 int yc_flags; 288 } yc_chipsets[] = { 289 /* Texas Instruments chips */ 290 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 291 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 292 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 293 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 294 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI12XX, 295 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 296 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 297 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 298 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 299 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 300 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 301 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 302 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI12XX, 303 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 304 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI12XX, 305 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 306 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 307 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 308 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 309 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 310 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI12XX, 311 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 312 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 313 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 314 315 /* Ricoh chips */ 316 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 317 PCCBB_PCMCIA_MEM_32}, 318 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 319 PCCBB_PCMCIA_MEM_32}, 320 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 321 PCCBB_PCMCIA_MEM_32}, 322 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 323 PCCBB_PCMCIA_MEM_32}, 324 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 325 PCCBB_PCMCIA_MEM_32}, 326 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 327 PCCBB_PCMCIA_MEM_32}, 328 329 /* Toshiba products */ 330 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 331 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 332 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 333 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 334 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 335 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 336 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 337 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 338 339 /* Cirrus Logic products */ 340 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 341 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 342 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 343 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 344 345 /* sentinel, or Generic chip */ 346 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 347 }; 348 349 static int 350 cb_chipset(pci_id, flagp) 351 u_int32_t pci_id; 352 int *flagp; 353 { 354 int loopend = sizeof(yc_chipsets) / sizeof(yc_chipsets[0]); 355 struct yenta_chipinfo *ycp, *ycend; 356 357 ycend = yc_chipsets + loopend; 358 359 for (ycp = yc_chipsets; ycp < ycend && pci_id != ycp->yc_id; ++ycp); 360 361 if (ycp == ycend) { 362 /* not found -- point at sentinel */ 363 ycp = yc_chipsets + loopend - 1; 364 } 365 366 if (flagp != NULL) { 367 *flagp = ycp->yc_flags; 368 } 369 370 return ycp->yc_chiptype; 371 } 372 373 #if notyet 374 static void 375 pccbb_shutdown(void *arg) 376 { 377 struct pccbb_softc *sc = arg; 378 pcireg_t command; 379 380 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 381 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 382 0); 383 384 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 385 386 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 387 PCI_COMMAND_MASTER_ENABLE); 388 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 389 390 } 391 #endif 392 393 void 394 pccbbattach(parent, self, aux) 395 struct device *parent; 396 struct device *self; 397 void *aux; 398 { 399 struct pccbb_softc *sc = (void *)self; 400 struct pci_attach_args *pa = aux; 401 pci_chipset_tag_t pc = pa->pa_pc; 402 pcireg_t sock_base, busreg; 403 bus_addr_t sockbase; 404 char devinfo[256]; 405 int flags; 406 407 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 408 409 pci_devinfo(pa->pa_id, 0, 0, devinfo); 410 printf(": %s (rev. 0x%02x)", devinfo, PCI_REVISION(pa->pa_class)); 411 #ifdef CBB_DEBUG 412 printf(" (chipflags %x)", flags); 413 #endif 414 printf("\n"); 415 416 TAILQ_INIT(&sc->sc_memwindow); 417 TAILQ_INIT(&sc->sc_iowindow); 418 419 #if rbus 420 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 421 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 422 #endif /* rbus */ 423 424 sc->sc_base_memh = 0; 425 426 /* 427 * MAP socket registers and ExCA registers on memory-space 428 * When no valid address is set on socket base registers (on pci 429 * config space), get it not polite way. 430 */ 431 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 432 433 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 434 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 435 /* The address must be valid. */ 436 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 437 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL)) { 438 printf("%s: can't map socket base address 0x%x\n", 439 sc->sc_dev.dv_xname, sock_base); 440 /* 441 * I think it's funny: socket base registers must be 442 * mapped on memory space, but ... 443 */ 444 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 445 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 446 NULL)) { 447 printf("%s: can't map socket base address" 448 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 449 sockbase); 450 /* give up... allocate reg space via rbus. */ 451 sc->sc_base_memh = 0; 452 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 453 } 454 } else { 455 DPRINTF(("%s: socket base address 0x%lx\n", 456 sc->sc_dev.dv_xname, sockbase)); 457 } 458 } 459 460 sc->sc_mem_start = 0; /* XXX */ 461 sc->sc_mem_end = 0xffffffff; /* XXX */ 462 463 /* 464 * When interrupt isn't routed correctly, give up probing cbb and do 465 * not kill pcic-compatible port. 466 */ 467 if ((0 == pa->pa_intrline) || (255 == pa->pa_intrline)) { 468 printf("%s: NOT USED because of unconfigured interrupt\n", 469 sc->sc_dev.dv_xname); 470 return; 471 } 472 473 /* 474 * When bus number isn't set correctly, give up using 32-bit CardBus 475 * mode. 476 */ 477 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 478 #if notyet 479 if (((busreg >> 8) & 0xff) == 0) { 480 printf("%s: CardBus support disabled because of unconfigured bus number\n", 481 sc->sc_dev.dv_xname); 482 flags |= PCCBB_PCMCIA_16BITONLY; 483 } 484 #endif 485 486 /* pccbb_machdep.c end */ 487 488 #if defined CBB_DEBUG 489 { 490 static char *intrname[5] = { "NON", "A", "B", "C", "D" }; 491 printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname, 492 intrname[pa->pa_intrpin], pa->pa_intrline); 493 } 494 #endif 495 496 /* setup softc */ 497 sc->sc_pc = pc; 498 sc->sc_iot = pa->pa_iot; 499 sc->sc_memt = pa->pa_memt; 500 sc->sc_dmat = pa->pa_dmat; 501 sc->sc_tag = pa->pa_tag; 502 sc->sc_function = pa->pa_function; 503 504 sc->sc_intrline = pa->pa_intrline; 505 sc->sc_intrtag = pa->pa_intrtag; 506 sc->sc_intrpin = pa->pa_intrpin; 507 508 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 509 510 #if notyet 511 shutdownhook_establish(pccbb_shutdown, sc); 512 #endif 513 514 #if __NetBSD_Version__ > 103060000 515 config_defer(self, pccbb_pci_callback); 516 #else 517 pccbb_pci_callback(self); 518 #endif 519 } 520 521 522 523 524 /* 525 * static void pccbb_pci_callback(struct device *self) 526 * 527 * The actual attach routine: get memory space for YENTA register 528 * space, setup YENTA register and route interrupt. 529 * 530 * This function should be deferred because this device may obtain 531 * memory space dynamically. This function must avoid obtaining 532 * memory area which has already kept for another device. Also, 533 * this function MUST be done before ISA attach process because this 534 * function kills pcic compatible port used by ISA pcic. 535 */ 536 static void 537 pccbb_pci_callback(self) 538 struct device *self; 539 { 540 struct pccbb_softc *sc = (void *)self; 541 pci_chipset_tag_t pc = sc->sc_pc; 542 bus_space_tag_t base_memt; 543 bus_space_handle_t base_memh; 544 u_int32_t maskreg; 545 pci_intr_handle_t ih; 546 const char *intrstr = NULL; 547 bus_addr_t sockbase; 548 struct cbslot_attach_args cba; 549 struct pcmciabus_attach_args paa; 550 struct cardslot_attach_args caa; 551 struct cardslot_softc *csc; 552 553 if (0 == sc->sc_base_memh) { 554 /* The socket registers aren't mapped correctly. */ 555 #if rbus 556 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 557 (sc->sc_chipset == CB_RX5C47X 558 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 559 0, &sockbase, &sc->sc_base_memh)) { 560 return; 561 } 562 sc->sc_base_memt = sc->sc_memt; 563 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 564 DPRINTF(("%s: CardBus resister address 0x%lx -> 0x%x\n", 565 sc->sc_dev.dv_xname, sockbase, pci_conf_read(pc, sc->sc_tag, 566 PCI_SOCKBASE))); 567 #else 568 sc->sc_base_memt = sc->sc_memt; 569 #if !defined CBB_PCI_BASE 570 #define CBB_PCI_BASE 0x20000000 571 #endif 572 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 573 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 574 /* cannot allocate memory space */ 575 return; 576 } 577 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 578 DPRINTF(("%s: CardBus resister address 0x%x -> 0x%x\n", 579 sc->sc_dev.dv_xname, sock_base, pci_conf_read(pc, 580 sc->sc_tag, PCI_SOCKBASE))); 581 #endif 582 } 583 584 /* bus bridge initialisation */ 585 pccbb_chipinit(sc); 586 587 base_memt = sc->sc_base_memt; /* socket regs memory tag */ 588 base_memh = sc->sc_base_memh; /* socket regs memory handle */ 589 590 /* CSC Interrupt: Card detect interrupt on */ 591 maskreg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 592 maskreg |= CB_SOCKET_MASK_CD; /* Card detect intr is turned on. */ 593 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, maskreg); 594 /* reset interrupt */ 595 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, 596 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT)); 597 598 599 /* clear data structure for child device interrupt handlers */ 600 sc->sc_pil = NULL; 601 sc->sc_pil_intr_enable = 1; 602 603 /* Map and establish the interrupt. */ 604 if (pci_intr_map(pc, sc->sc_intrtag, sc->sc_intrpin, 605 sc->sc_intrline, &ih)) { 606 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 607 return; 608 } 609 intrstr = pci_intr_string(pc, ih); 610 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 611 612 if (sc->sc_ih == NULL) { 613 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 614 if (intrstr != NULL) { 615 printf(" at %s", intrstr); 616 } 617 printf("\n"); 618 return; 619 } 620 621 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 622 powerhook_establish(pccbb_powerhook, sc); 623 624 { 625 u_int32_t sockstat = 626 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 627 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 628 sc->sc_flags |= CBB_CARDEXIST; 629 } 630 } 631 632 /* 633 * attach cardbus 634 */ 635 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 636 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 637 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 638 639 /* initialise cbslot_attach */ 640 cba.cba_busname = "cardbus"; 641 cba.cba_iot = sc->sc_iot; 642 cba.cba_memt = sc->sc_memt; 643 cba.cba_dmat = sc->sc_dmat; 644 cba.cba_bus = (busreg >> 8) & 0x0ff; 645 cba.cba_cc = (void *)sc; 646 cba.cba_cf = &pccbb_funcs; 647 cba.cba_intrline = sc->sc_intrline; 648 649 #if rbus 650 cba.cba_rbus_iot = sc->sc_rbus_iot; 651 cba.cba_rbus_memt = sc->sc_rbus_memt; 652 #endif 653 654 cba.cba_cacheline = PCI_CACHELINE(bhlc); 655 cba.cba_lattimer = PCI_CB_LATENCY(busreg); 656 657 printf("%s: cacheline 0x%x lattimer 0x%x\n", 658 sc->sc_dev.dv_xname, cba.cba_cacheline, cba.cba_lattimer); 659 printf("%s: bhlc 0x%x lscp 0x%x\n", sc->sc_dev.dv_xname, bhlc, 660 busreg); 661 #if defined SHOW_REGS 662 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 663 sc->sc_base_memh); 664 #endif 665 } 666 667 pccbb_pcmcia_attach_setup(sc, &paa); 668 caa.caa_cb_attach = NULL; 669 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 670 caa.caa_cb_attach = &cba; 671 } 672 caa.caa_16_attach = &paa; 673 caa.caa_ph = &sc->sc_pcmcia_h; 674 675 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 676 DPRINTF(("pccbbattach: found cardslot\n")); 677 sc->sc_csc = csc; 678 } 679 680 return; 681 } 682 683 684 685 686 687 /* 688 * static void pccbb_chipinit(struct pccbb_softc *sc) 689 * 690 * This function initialise YENTA chip registers listed below: 691 * 1) PCI command reg, 692 * 2) PCI and CardBus latency timer, 693 * 3) disable legacy (PCIC-compatible) io, 694 * 4) route PCI interrupt, 695 * 5) close all memory and io windows. 696 */ 697 static void 698 pccbb_chipinit(sc) 699 struct pccbb_softc *sc; 700 { 701 pci_chipset_tag_t pc = sc->sc_pc; 702 pcitag_t tag = sc->sc_tag; 703 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 704 bus_space_handle_t base_memh = sc->sc_base_memh; 705 pcireg_t cbctrl; 706 707 /* 708 * Set PCI command reg. 709 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 710 */ 711 { 712 pcireg_t command = 713 pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 714 715 /* I believe it is harmless. */ 716 command |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 717 PCI_COMMAND_MASTER_ENABLE); 718 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, command); 719 } 720 721 /* 722 * Set CardBus latency timer 723 */ 724 { 725 pcireg_t pci_lscp = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 726 if (PCI_CB_LATENCY(pci_lscp) < 0x20) { 727 pci_lscp &= 728 ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 729 pci_lscp |= (0x20 << PCI_CB_LATENCY_SHIFT); 730 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, pci_lscp); 731 } 732 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 733 PCI_CB_LATENCY(pci_lscp), pci_conf_read(pc, tag, 734 PCI_CB_LSCP_REG))); 735 } 736 737 /* 738 * Set PCI latency timer 739 */ 740 { 741 pcireg_t pci_bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG); 742 if (PCI_LATTIMER(pci_bhlc) < 0x10) { 743 pci_bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 744 pci_bhlc |= (0x10 << PCI_LATTIMER_SHIFT); 745 pci_conf_write(pc, tag, PCI_BHLC_REG, pci_bhlc); 746 } 747 DPRINTF(("PCI latency timer 0x%x (%x)\n", 748 PCI_LATTIMER(pci_bhlc), pci_conf_read(pc, tag, 749 PCI_BHLC_REG))); 750 } 751 752 /* disable Legacy IO */ 753 754 switch (sc->sc_chipset) { 755 case CB_RX5C46X: /* fallthrogh */ 756 #if 0 757 case CB_RX5C47X: 758 #endif 759 /* 760 * The legacy pcic io-port on Ricoh CardBus bridges cannot be 761 * disabled by substituting 0 into PCI_LEGACY register. Ricoh 762 * CardBus bridges have special bits on Bridge control reg (addr 763 * 0x3e on PCI config space). 764 */ 765 { 766 pcireg_t bcri = pci_conf_read(pc, tag, PCI_BCR_INTR); 767 bcri &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 768 pci_conf_write(pc, tag, PCI_BCR_INTR, bcri); 769 } 770 break; 771 default: 772 /* XXX: I don't know proper way to kill Legacy IO properly. */ 773 pci_conf_write(pc, tag, PCI_LEGACY, 0x0); 774 break; 775 } 776 777 /* 778 * Interrupt routing: use PCI interrupt 779 */ 780 { 781 u_int32_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 782 bcr &= ~CB_BCR_INTR_IREQ_ENABLE; /* use PCI Intr */ 783 bcr |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 784 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 785 } 786 787 if (CB_TI113X == sc->sc_chipset) { 788 cbctrl = pci_conf_read(pc, tag, PCI_CBCTRL); 789 if (0 == sc->sc_function) { 790 cbctrl |= PCI113X_CBCTRL_PCI_IRQ_ENA; 791 } 792 /* XXX: bug in PCI113X */ 793 cbctrl |= PCI113X_CBCTRL_PCI_IRQ_ENA; 794 /* CSC intr enable */ 795 cbctrl |= PCI113X_CBCTRL_PCI_CSC; 796 /* functional intr prohibit */ 797 cbctrl &= ~PCI113X_CBCTRL_PCI_INTR; 798 /* prohibit ISA routing */ 799 cbctrl &= ~PCI113X_CBCTRL_INT_MASK; 800 pci_conf_write(pc, tag, PCI_CBCTRL, cbctrl); 801 802 /* 803 * set ExCA regs: PCI113X required to be set bit 4 at Interrupt 804 * and General Register, which is IRQ Enable Register, and 805 * clear bit 3:0 to zero in order to route CSC interrupt to 806 * PCI interrupt pin. 807 */ 808 bus_space_write_1(base_memt, base_memh, 0x0803, 0x10); 809 /* set ExCA regs: prohibit all pcmcia-style CSC intr. */ 810 bus_space_write_1(base_memt, base_memh, 0x0805, 0x00); 811 #if 1 812 DPRINTF(("ExCA regs:")); 813 DPRINTF((" 0x803: %02x", bus_space_read_1(base_memt, base_memh, 814 0x803))); 815 DPRINTF((" 0x805: %02x", bus_space_read_1(base_memt, base_memh, 816 0x805))); 817 DPRINTF((" 0x81e: %02x\n", bus_space_read_1(base_memt, 818 base_memh, 0x81e))); 819 #endif 820 } else if (sc->sc_chipset == CB_TI12XX) { 821 cbctrl = pci_conf_read(pc, tag, PCI_CBCTRL); 822 cbctrl &= ~PCI12XX_CBCTRL_INT_MASK; /* intr routing reset */ 823 pci_conf_write(pc, tag, PCI_CBCTRL, cbctrl); 824 /* 825 * set ExCA regs: PCI12XX required to be set bit 4 at 826 * Interrupt and General Register, which is IRQ Enable 827 * Register, and clear bit 3:0 to zero in order to 828 * route CSC interrupt to PCI interrupt pin. 829 */ 830 bus_space_write_1(base_memt, base_memh, 0x0803, 0x10); 831 /* set ExCA regs: prohibit all pcmcia-style CSC intr. */ 832 bus_space_write_1(base_memt, base_memh, 0x0805, 0x00); 833 } else if (sc->sc_chipset == CB_TOPIC95B) { 834 cardbusreg_t sock_ctrl, slot_ctrl; 835 836 sock_ctrl = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 837 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, 838 sock_ctrl | TOPIC_SOCKET_CTRL_SCR_IRQSEL); 839 840 slot_ctrl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 841 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 842 sc->sc_dev.dv_xname, slot_ctrl)); 843 slot_ctrl |= 844 (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 845 TOPIC_SLOT_CTRL_ID_LOCK); 846 slot_ctrl |= TOPIC_SLOT_CTRL_CARDBUS; 847 slot_ctrl &= ~TOPIC_SLOT_CTRL_SWDETECT; 848 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slot_ctrl); 849 DPRINTF(("0x%x\n", slot_ctrl)); 850 } 851 852 /* close all memory and io windows */ 853 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 854 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 855 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 856 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 857 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 858 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 859 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 860 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 861 862 return; 863 } 864 865 866 867 868 /* 869 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 870 * struct pcmciabus_attach_args *paa) 871 * 872 * This function attaches 16-bit PCcard bus. 873 */ 874 STATIC void 875 pccbb_pcmcia_attach_setup(sc, paa) 876 struct pccbb_softc *sc; 877 struct pcmciabus_attach_args *paa; 878 { 879 struct pcic_handle *ph = &sc->sc_pcmcia_h; 880 #if rbus 881 rbus_tag_t rb; 882 #endif 883 884 /* initialise pcmcia part in pccbb_softc */ 885 ph->ph_parent = (struct device *)sc; 886 ph->sock = sc->sc_function; 887 ph->flags = 0; 888 ph->shutdown = 0; 889 ph->ih_irq = sc->sc_intrline; 890 ph->ph_bus_t = sc->sc_base_memt; 891 ph->ph_bus_h = sc->sc_base_memh; 892 ph->ph_read = pccbb_pcmcia_read; 893 ph->ph_write = pccbb_pcmcia_write; 894 sc->sc_pct = &pccbb_pcmcia_funcs; 895 896 Pcic_write(ph, PCIC_CSC_INTR, 0); 897 Pcic_read(ph, PCIC_CSC); 898 899 /* initialise pcmcia bus attachment */ 900 paa->paa_busname = "pcmcia"; 901 paa->pct = sc->sc_pct; 902 paa->pch = ph; 903 paa->iobase = 0; /* I don't use them */ 904 paa->iosize = 0; 905 #if rbus 906 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 907 paa->iobase = rb->rb_start + rb->rb_offset; 908 paa->iosize = rb->rb_end - rb->rb_start; 909 #endif 910 911 return; 912 } 913 914 #if 0 915 STATIC void 916 pccbb_pcmcia_attach_card(ph) 917 struct pcic_handle *ph; 918 { 919 if (ph->flags & PCIC_FLAG_CARDP) { 920 panic("pccbb_pcmcia_attach_card: already attached"); 921 } 922 923 /* call the MI attach function */ 924 pcmcia_card_attach(ph->pcmcia); 925 926 ph->flags |= PCIC_FLAG_CARDP; 927 } 928 929 STATIC void 930 pccbb_pcmcia_detach_card(ph, flags) 931 struct pcic_handle *ph; 932 int flags; 933 { 934 if (!(ph->flags & PCIC_FLAG_CARDP)) { 935 panic("pccbb_pcmcia_detach_card: already detached"); 936 } 937 938 ph->flags &= ~PCIC_FLAG_CARDP; 939 940 /* call the MI detach function */ 941 pcmcia_card_detach(ph->pcmcia, flags); 942 } 943 #endif 944 945 /* 946 * int pccbbintr(arg) 947 * void *arg; 948 * This routine handles the interrupt from Yenta PCI-CardBus bridge 949 * itself. 950 */ 951 int 952 pccbbintr(arg) 953 void *arg; 954 { 955 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 956 u_int32_t sockevent; 957 bus_space_tag_t memt = sc->sc_base_memt; 958 bus_space_handle_t memh = sc->sc_base_memh; 959 u_int32_t sockstate; 960 961 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 962 if (0 == sockevent) { 963 /* This intr is not for me: it may be for my child devices. */ 964 if (sc->sc_pil_intr_enable) { 965 return pccbbintr_function(sc); 966 } else { 967 return 0; 968 } 969 } 970 971 /* reset bit */ 972 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 973 974 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 975 976 if (sockevent & CB_SOCKET_EVENT_CD) { 977 if (CB_SOCKET_STAT_CD == (sockstate & CB_SOCKET_STAT_CD)) { 978 /* A card should be removed. */ 979 if (sc->sc_flags & CBB_CARDEXIST) { 980 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 981 sockevent)); 982 DPRINTF((" card removed, 0x%08x\n", sockstate)); 983 sc->sc_flags &= ~CBB_CARDEXIST; 984 if (sc-> 985 sc_csc->sc_status & CARDSLOT_STATUS_CARD_16) 986 { 987 #if 0 988 struct pcic_handle *ph = 989 &sc->sc_pcmcia_h; 990 991 pcmcia_card_deactivate(ph->pcmcia); 992 pccbb_pcmcia_socket_disable(ph); 993 pccbb_pcmcia_detach_card(ph, 994 DETACH_FORCE); 995 #endif 996 cardslot_event_throw(sc->sc_csc, 997 CARDSLOT_EVENT_REMOVAL_16); 998 } else if (sc-> 999 sc_csc->sc_status & CARDSLOT_STATUS_CARD_CB) 1000 { 1001 /* Cardbus intr removed */ 1002 cardslot_event_throw(sc->sc_csc, 1003 CARDSLOT_EVENT_REMOVAL_CB); 1004 } 1005 } 1006 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD)) { 1007 if (sc->sc_flags & CBB_INSERTING) { 1008 untimeout(pci113x_insert, sc); 1009 } 1010 timeout(pci113x_insert, sc, hz / 10); 1011 sc->sc_flags |= CBB_INSERTING; 1012 } 1013 } else { 1014 DPRINTF(("%s: sockevent = %b\n", 1015 sc->sc_dev.dv_xname, sockevent, PCCBB_SOCKEVENT_BITS)); 1016 DPRINTF(("%s: sockstate = %b\n", 1017 sc->sc_dev.dv_xname, sockstate, PCCBB_SOCKSTATE_BITS)); 1018 } 1019 1020 return 1; 1021 } 1022 1023 /* 1024 * static int pccbbintr_function(struct pccbb_softc *sc) 1025 * 1026 * This function calls each interrupt handler registered at the 1027 * bridge. The interrupt handlers are called in registerd order. 1028 */ 1029 static int 1030 pccbbintr_function(sc) 1031 struct pccbb_softc *sc; 1032 { 1033 int retval = 0, val; 1034 struct pccbb_intrhand_list *pil; 1035 1036 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 1037 val = (*pil->pil_func) (pil->pil_arg); 1038 retval = retval == 1 ? 1 : 1039 retval == 0 ? val : val != 0 ? val : retval; 1040 } 1041 1042 return retval; 1043 } 1044 1045 static void 1046 pci113x_insert(arg) 1047 void *arg; 1048 { 1049 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1050 u_int32_t sockevent, sockstate; 1051 1052 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1053 CB_SOCKET_EVENT); 1054 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1055 CB_SOCKET_STAT); 1056 1057 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1058 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1059 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1060 sc->sc_flags |= CBB_CARDEXIST; 1061 /* call pccard intterupt handler here */ 1062 if (sockstate & CB_SOCKET_STAT_16BIT) { 1063 /* 16-bit card found */ 1064 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1065 cardslot_event_throw(sc->sc_csc, 1066 CARDSLOT_EVENT_INSERTION_16); 1067 } else if (sockstate & CB_SOCKET_STAT_CB) { 1068 /* cardbus card fuond */ 1069 /* cardbus_attach_card(sc->sc_csc); */ 1070 cardslot_event_throw(sc->sc_csc, 1071 CARDSLOT_EVENT_INSERTION_CB); 1072 } else { 1073 /* who are you? */ 1074 } 1075 } else { 1076 timeout(pci113x_insert, sc, hz / 10); 1077 } 1078 } 1079 1080 #define PCCBB_PCMCIA_OFFSET 0x800 1081 static u_int8_t 1082 pccbb_pcmcia_read(ph, reg) 1083 struct pcic_handle *ph; 1084 int reg; 1085 { 1086 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1087 PCCBB_PCMCIA_OFFSET + reg); 1088 } 1089 1090 static void 1091 pccbb_pcmcia_write(ph, reg, val) 1092 struct pcic_handle *ph; 1093 int reg; 1094 u_int8_t val; 1095 { 1096 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1097 val); 1098 } 1099 1100 /* 1101 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1102 */ 1103 STATIC int 1104 pccbb_ctrl(ct, command) 1105 cardbus_chipset_tag_t ct; 1106 int command; 1107 { 1108 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1109 1110 switch (command) { 1111 case CARDBUS_CD: 1112 if (2 == pccbb_detect_card(sc)) { 1113 int retval = 0; 1114 int status = cb_detect_voltage(sc); 1115 if (PCCARD_VCC_5V & status) { 1116 retval |= CARDBUS_5V_CARD; 1117 } 1118 if (PCCARD_VCC_3V & status) { 1119 retval |= CARDBUS_3V_CARD; 1120 } 1121 if (PCCARD_VCC_XV & status) { 1122 retval |= CARDBUS_XV_CARD; 1123 } 1124 if (PCCARD_VCC_YV & status) { 1125 retval |= CARDBUS_YV_CARD; 1126 } 1127 return retval; 1128 } else { 1129 return 0; 1130 } 1131 break; 1132 case CARDBUS_RESET: 1133 return cb_reset(sc); 1134 break; 1135 case CARDBUS_IO_ENABLE: /* fallthrough */ 1136 case CARDBUS_IO_DISABLE: /* fallthrough */ 1137 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1138 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1139 case CARDBUS_BM_ENABLE: /* fallthrough */ 1140 case CARDBUS_BM_DISABLE: /* fallthrough */ 1141 return pccbb_cardenable(sc, command); 1142 break; 1143 } 1144 1145 return 0; 1146 } 1147 1148 /* 1149 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1150 * This function returns true when it succeeds and returns false when 1151 * it fails. 1152 */ 1153 STATIC int 1154 pccbb_power(ct, command) 1155 cardbus_chipset_tag_t ct; 1156 int command; 1157 { 1158 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1159 1160 u_int32_t status, sock_ctrl; 1161 bus_space_tag_t memt = sc->sc_base_memt; 1162 bus_space_handle_t memh = sc->sc_base_memh; 1163 1164 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1165 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1166 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1167 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1168 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1169 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1170 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1171 "UNKNOWN", 1172 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1173 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1174 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1175 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1176 "UNKNOWN", command)); 1177 1178 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1179 sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1180 1181 switch (command & CARDBUS_VCCMASK) { 1182 case CARDBUS_VCC_UC: 1183 break; 1184 case CARDBUS_VCC_5V: 1185 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1186 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1187 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1188 } else { 1189 printf("%s: BAD voltage request: no 5 V card\n", 1190 sc->sc_dev.dv_xname); 1191 } 1192 break; 1193 case CARDBUS_VCC_3V: 1194 if (CB_SOCKET_STAT_3VCARD & status) { 1195 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1196 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1197 } else { 1198 printf("%s: BAD voltage request: no 3.3 V card\n", 1199 sc->sc_dev.dv_xname); 1200 } 1201 break; 1202 case CARDBUS_VCC_0V: 1203 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1204 break; 1205 default: 1206 return 0; /* power NEVER changed */ 1207 break; 1208 } 1209 1210 switch (command & CARDBUS_VPPMASK) { 1211 case CARDBUS_VPP_UC: 1212 break; 1213 case CARDBUS_VPP_0V: 1214 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1215 break; 1216 case CARDBUS_VPP_VCC: 1217 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1218 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1219 break; 1220 case CARDBUS_VPP_12V: 1221 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1222 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1223 break; 1224 } 1225 1226 #if 0 1227 DPRINTF(("sock_ctrl: %x\n", sock_ctrl)); 1228 #endif 1229 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1230 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1231 1232 delay(20 * 1000); /* wait 20 ms: Vcc setup time */ 1233 /* 1234 * XXX delay 200 ms: though the standard defines that the Vcc set-up 1235 * time is 20 ms, some PC-Card bridge requires longer duration. 1236 */ 1237 delay(200 * 1000); 1238 1239 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1240 printf 1241 ("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1242 sc->sc_dev.dv_xname, sock_ctrl, status); 1243 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1244 (command & CARDBUS_VCCMASK) == 1245 CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : (command & 1246 CARDBUS_VCCMASK) == 1247 CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : (command & 1248 CARDBUS_VCCMASK) == 1249 CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : (command & 1250 CARDBUS_VCCMASK) == 1251 CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : (command & 1252 CARDBUS_VCCMASK) == 1253 CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : (command & 1254 CARDBUS_VCCMASK) == 1255 CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : "UNKNOWN", 1256 (command & CARDBUS_VPPMASK) == 1257 CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : (command & 1258 CARDBUS_VPPMASK) == 1259 CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : (command & 1260 CARDBUS_VPPMASK) == 1261 CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : (command & 1262 CARDBUS_VPPMASK) == 1263 CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : "UNKNOWN", command)); 1264 #if 0 1265 if (command == (CARDBUS_VCC_0V | CARDBUS_VPP_0V)) { 1266 u_int32_t force = 1267 bus_space_read_4(memt, memh, CB_SOCKET_FORCE); 1268 /* Reset Bad Vcc request */ 1269 force &= ~CB_SOCKET_FORCE_BADVCC; 1270 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, force); 1271 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1272 CB_SOCKET_STAT)); 1273 return 1; 1274 } 1275 #endif 1276 return 0; 1277 } 1278 return 1; /* power changed correctly */ 1279 } 1280 1281 #if defined CB_PCMCIA_POLL 1282 struct cb_poll_str { 1283 void *arg; 1284 int (*func) __P((void *)); 1285 int level; 1286 pccard_chipset_tag_t ct; 1287 int count; 1288 }; 1289 1290 static struct cb_poll_str cb_poll[10]; 1291 static int cb_poll_n = 0; 1292 1293 static void cb_pcmcia_poll __P((void *arg)); 1294 1295 static void 1296 cb_pcmcia_poll(arg) 1297 void *arg; 1298 { 1299 struct cb_poll_str *poll = arg; 1300 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1301 struct pccbb_softc *sc = psc->cpc_parent; 1302 int s; 1303 u_int32_t spsr; /* socket present-state reg */ 1304 1305 timeout(cb_pcmcia_poll, arg, hz / 10); 1306 switch (poll->level) { 1307 case IPL_NET: 1308 s = splnet(); 1309 break; 1310 case IPL_BIO: 1311 s = splbio(); 1312 break; 1313 case IPL_TTY: /* fallthrough */ 1314 default: 1315 s = spltty(); 1316 break; 1317 } 1318 1319 spsr = 1320 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1321 CB_SOCKET_STAT); 1322 1323 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1324 if (!(spsr & 0x40)) { /* CINT low */ 1325 #else 1326 if (1) { 1327 #endif 1328 if ((*poll->func) (poll->arg) == 1) { 1329 ++poll->count; 1330 printf("intr: reported from poller, 0x%x\n", spsr); 1331 #if defined LEVEL2 1332 } else { 1333 printf("intr: miss! 0x%x\n", spsr); 1334 #endif 1335 } 1336 } 1337 splx(s); 1338 } 1339 #endif /* defined CB_PCMCIA_POLL */ 1340 1341 /* 1342 * static int pccbb_detect_card(struct pccbb_softc *sc) 1343 * return value: 0 if no card exists. 1344 * 1 if 16-bit card exists. 1345 * 2 if cardbus card exists. 1346 */ 1347 static int 1348 pccbb_detect_card(sc) 1349 struct pccbb_softc *sc; 1350 { 1351 bus_space_handle_t base_memh = sc->sc_base_memh; 1352 bus_space_tag_t base_memt = sc->sc_base_memt; 1353 u_int32_t sockstat = 1354 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1355 int retval = 0; 1356 1357 /* CD1 and CD2 asserted */ 1358 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1359 /* card must be present */ 1360 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1361 /* NOTACARD DEASSERTED */ 1362 if (CB_SOCKET_STAT_CB & sockstat) { 1363 /* CardBus mode */ 1364 retval = 2; 1365 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1366 /* 16-bit mode */ 1367 retval = 1; 1368 } 1369 } 1370 } 1371 return retval; 1372 } 1373 1374 /* 1375 * STATIC int cb_reset(struct pccbb_softc *sc) 1376 * This function resets CardBus card. 1377 */ 1378 STATIC int 1379 cb_reset(sc) 1380 struct pccbb_softc *sc; 1381 { 1382 /* 1383 * Reset Assert at least 20 ms 1384 * Some machines request longer duration. 1385 */ 1386 int reset_duration = 1387 (sc->sc_chipset == CB_RX5C47X ? 400 * 1000 : 40 * 1000); 1388 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1389 1390 bcr |= (0x40 << 16); /* Reset bit Assert (bit 6 at 0x3E) */ 1391 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1392 delay(reset_duration); 1393 1394 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1395 bcr &= ~(0x40 << 16); /* Reset bit Deassert (bit 6 at 0x3E) */ 1396 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1397 delay(reset_duration); 1398 } 1399 /* No card found on the slot. Keep Reset. */ 1400 return 1; 1401 } 1402 1403 /* 1404 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1405 * This function detect card Voltage. 1406 */ 1407 STATIC int 1408 cb_detect_voltage(sc) 1409 struct pccbb_softc *sc; 1410 { 1411 u_int32_t psr; /* socket present-state reg */ 1412 bus_space_tag_t iot = sc->sc_base_memt; 1413 bus_space_handle_t ioh = sc->sc_base_memh; 1414 int vol = PCCARD_VCC_UKN; /* set 0 */ 1415 1416 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1417 1418 if (0x400u & psr) { 1419 vol |= PCCARD_VCC_5V; 1420 } 1421 if (0x800u & psr) { 1422 vol |= PCCARD_VCC_3V; 1423 } 1424 1425 return vol; 1426 } 1427 1428 STATIC int 1429 cbbprint(aux, pcic) 1430 void *aux; 1431 const char *pcic; 1432 { 1433 /* 1434 struct cbslot_attach_args *cba = aux; 1435 1436 if (cba->cba_slot >= 0) { 1437 printf(" slot %d", cba->cba_slot); 1438 } 1439 */ 1440 return UNCONF; 1441 } 1442 1443 /* 1444 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1445 * This function enables and disables the card 1446 */ 1447 STATIC int 1448 pccbb_cardenable(sc, function) 1449 struct pccbb_softc *sc; 1450 int function; 1451 { 1452 u_int32_t command = 1453 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1454 1455 DPRINTF(("pccbb_cardenable:")); 1456 switch (function) { 1457 case CARDBUS_IO_ENABLE: 1458 command |= PCI_COMMAND_IO_ENABLE; 1459 break; 1460 case CARDBUS_IO_DISABLE: 1461 command &= ~PCI_COMMAND_IO_ENABLE; 1462 break; 1463 case CARDBUS_MEM_ENABLE: 1464 command |= PCI_COMMAND_MEM_ENABLE; 1465 break; 1466 case CARDBUS_MEM_DISABLE: 1467 command &= ~PCI_COMMAND_MEM_ENABLE; 1468 break; 1469 case CARDBUS_BM_ENABLE: 1470 command |= PCI_COMMAND_MASTER_ENABLE; 1471 break; 1472 case CARDBUS_BM_DISABLE: 1473 command &= ~PCI_COMMAND_MASTER_ENABLE; 1474 break; 1475 default: 1476 return 0; 1477 } 1478 1479 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1480 DPRINTF((" command reg 0x%x\n", command)); 1481 return 1; 1482 } 1483 1484 #if !rbus 1485 /* 1486 * int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1487 */ 1488 static int 1489 pccbb_io_open(ct, win, start, end) 1490 cardbus_chipset_tag_t ct; 1491 int win; 1492 u_int32_t start, end; 1493 { 1494 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1495 int basereg; 1496 int limitreg; 1497 1498 if ((win < 0) || (win > 2)) { 1499 #if defined DIAGNOSTIC 1500 printf("cardbus_io_open: window out of range %d\n", win); 1501 #endif 1502 return 0; 1503 } 1504 1505 basereg = win * 8 + 0x2c; 1506 limitreg = win * 8 + 0x30; 1507 1508 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1509 start, basereg, end, limitreg)); 1510 1511 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1512 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1513 return 1; 1514 } 1515 1516 /* 1517 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1518 */ 1519 static int 1520 pccbb_io_close(ct, win) 1521 cardbus_chipset_tag_t ct; 1522 int win; 1523 { 1524 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1525 int basereg; 1526 int limitreg; 1527 1528 if ((win < 0) || (win > 2)) { 1529 #if defined DIAGNOSTIC 1530 printf("cardbus_io_close: window out of range %d\n", win); 1531 #endif 1532 return 0; 1533 } 1534 1535 basereg = win * 8 + 0x2c; 1536 limitreg = win * 8 + 0x30; 1537 1538 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1539 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1540 return 1; 1541 } 1542 1543 /* 1544 * int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1545 */ 1546 static int 1547 pccbb_mem_open(ct, win, start, end) 1548 cardbus_chipset_tag_t ct; 1549 int win; 1550 u_int32_t start, end; 1551 { 1552 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1553 int basereg; 1554 int limitreg; 1555 1556 if ((win < 0) || (win > 2)) { 1557 #if defined DIAGNOSTIC 1558 printf("cardbus_mem_open: window out of range %d\n", win); 1559 #endif 1560 return 0; 1561 } 1562 1563 basereg = win * 8 + 0x1c; 1564 limitreg = win * 8 + 0x20; 1565 1566 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1567 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1568 return 1; 1569 } 1570 1571 /* 1572 * int pccbb_mem_close(cardbus_chipset_tag_t, int) 1573 */ 1574 static int 1575 pccbb_mem_close(ct, win) 1576 cardbus_chipset_tag_t ct; 1577 int win; 1578 { 1579 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1580 int basereg; 1581 int limitreg; 1582 1583 if ((win < 0) || (win > 2)) { 1584 #if defined DIAGNOSTIC 1585 printf("cardbus_mem_close: window out of range %d\n", win); 1586 #endif 1587 return 0; 1588 } 1589 1590 basereg = win * 8 + 0x1c; 1591 limitreg = win * 8 + 0x20; 1592 1593 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1594 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1595 return 1; 1596 } 1597 #endif 1598 1599 /* 1600 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1601 * int irq, 1602 * int level, 1603 * int (* func) __P((void *)), 1604 * void *arg) 1605 * 1606 * This function registers an interrupt handler at the bridge, in 1607 * order not to call the interrput handlers of child devices when 1608 * a card-deletion interrput occurs. 1609 * 1610 * The arguments irq and level are not used. 1611 */ 1612 static void * 1613 pccbb_cb_intr_establish(ct, irq, level, func, arg) 1614 cardbus_chipset_tag_t ct; 1615 int irq, level; 1616 int (*func) __P((void *)); 1617 void *arg; 1618 { 1619 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1620 1621 return pccbb_intr_establish(sc, irq, level, func, arg); 1622 } 1623 1624 1625 /* 1626 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1627 * void *ih) 1628 * 1629 * This function removes an interrupt handler pointed by ih. 1630 */ 1631 static void 1632 pccbb_cb_intr_disestablish(ct, ih) 1633 cardbus_chipset_tag_t ct; 1634 void *ih; 1635 { 1636 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1637 1638 pccbb_intr_disestablish(sc, ih); 1639 } 1640 1641 1642 /* 1643 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1644 * int irq, 1645 * int level, 1646 * int (* func) __P((void *)), 1647 * void *arg) 1648 * 1649 * This function registers an interrupt handler at the bridge, in 1650 * order not to call the interrput handlers of child devices when 1651 * a card-deletion interrput occurs. 1652 * 1653 * The arguments irq and level are not used. 1654 */ 1655 static void * 1656 pccbb_intr_establish(sc, irq, level, func, arg) 1657 struct pccbb_softc *sc; 1658 int irq, level; 1659 int (*func) __P((void *)); 1660 void *arg; 1661 { 1662 struct pccbb_intrhand_list *pil, *newpil; 1663 1664 DPRINTF(("pccbb_intr_establish start. %p\n", sc->sc_pil)); 1665 1666 if (sc->sc_pil == NULL) { 1667 /* initialise bridge intr routing */ 1668 1669 switch (sc->sc_chipset) { 1670 case CB_TI113X: 1671 { 1672 pcireg_t cbctrl = 1673 pci_conf_read(sc->sc_pc, sc->sc_tag, 1674 PCI_CBCTRL); 1675 /* functional intr enabled */ 1676 cbctrl |= PCI113X_CBCTRL_PCI_INTR; 1677 pci_conf_write(sc->sc_pc, sc->sc_tag, 1678 PCI_CBCTRL, cbctrl); 1679 break; 1680 } 1681 default: 1682 break; 1683 } 1684 } 1685 1686 /* 1687 * Allocate a room for interrut handler structure. 1688 */ 1689 if (NULL == (newpil = 1690 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1691 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1692 return NULL; 1693 } 1694 1695 newpil->pil_func = func; 1696 newpil->pil_arg = arg; 1697 newpil->pil_next = NULL; 1698 1699 if (sc->sc_pil == NULL) { 1700 sc->sc_pil = newpil; 1701 } else { 1702 for (pil = sc->sc_pil; pil->pil_next != NULL; 1703 pil = pil->pil_next); 1704 pil->pil_next = newpil; 1705 } 1706 1707 DPRINTF(("pccbb_intr_establish add pil. %p\n", sc->sc_pil)); 1708 1709 return newpil; 1710 } 1711 1712 /* 1713 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1714 * void *ih) 1715 * 1716 * This function removes an interrupt handler pointed by ih. 1717 */ 1718 static void 1719 pccbb_intr_disestablish(sc, ih) 1720 struct pccbb_softc *sc; 1721 void *ih; 1722 { 1723 struct pccbb_intrhand_list *pil, **pil_prev; 1724 1725 DPRINTF(("pccbb_intr_disestablish start. %p\n", sc->sc_pil)); 1726 1727 pil_prev = &sc->sc_pil; 1728 1729 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 1730 if (pil == ih) { 1731 *pil_prev = pil->pil_next; 1732 free(pil, M_DEVBUF); 1733 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1734 break; 1735 } 1736 pil_prev = &pil->pil_next; 1737 } 1738 1739 if (sc->sc_pil == NULL) { 1740 /* No interrupt handlers */ 1741 1742 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1743 1744 switch (sc->sc_chipset) { 1745 case CB_TI113X: 1746 { 1747 pcireg_t cbctrl = 1748 pci_conf_read(sc->sc_pc, sc->sc_tag, 1749 PCI_CBCTRL); 1750 /* functional intr disabled */ 1751 cbctrl &= ~PCI113X_CBCTRL_PCI_INTR; 1752 pci_conf_write(sc->sc_pc, sc->sc_tag, 1753 PCI_CBCTRL, cbctrl); 1754 break; 1755 } 1756 default: 1757 break; 1758 } 1759 } 1760 } 1761 1762 #if defined SHOW_REGS 1763 static void 1764 cb_show_regs(pc, tag, memt, memh) 1765 pci_chipset_tag_t pc; 1766 pcitag_t tag; 1767 bus_space_tag_t memt; 1768 bus_space_handle_t memh; 1769 { 1770 int i; 1771 printf("PCI config regs:"); 1772 for (i = 0; i < 0x50; i += 4) { 1773 if (i % 16 == 0) { 1774 printf("\n 0x%02x:", i); 1775 } 1776 printf(" %08x", pci_conf_read(pc, tag, i)); 1777 } 1778 for (i = 0x80; i < 0xb0; i += 4) { 1779 if (i % 16 == 0) { 1780 printf("\n 0x%02x:", i); 1781 } 1782 printf(" %08x", pci_conf_read(pc, tag, i)); 1783 } 1784 1785 if (memh == 0) { 1786 printf("\n"); 1787 return; 1788 } 1789 1790 printf("\nsocket regs:"); 1791 for (i = 0; i <= 0x10; i += 0x04) { 1792 printf(" %08x", bus_space_read_4(memt, memh, i)); 1793 } 1794 printf("\nExCA regs:"); 1795 for (i = 0; i < 0x08; ++i) { 1796 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1797 } 1798 printf("\n"); 1799 return; 1800 } 1801 #endif 1802 1803 /* 1804 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1805 * int busno, int devno, int function) 1806 * This is the function to make a tag to access config space of 1807 * a CardBus Card. It works same as pci_conf_read. 1808 */ 1809 static cardbustag_t 1810 pccbb_make_tag(cc, busno, devno, function) 1811 cardbus_chipset_tag_t cc; 1812 int busno, devno, function; 1813 { 1814 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1815 1816 return pci_make_tag(sc->sc_pc, busno, devno, function); 1817 } 1818 1819 static void 1820 pccbb_free_tag(cc, tag) 1821 cardbus_chipset_tag_t cc; 1822 cardbustag_t tag; 1823 { 1824 } 1825 1826 /* 1827 * static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t cc, 1828 * cardbustag_t tag, int offset) 1829 * This is the function to read the config space of a CardBus Card. 1830 * It works same as pci_conf_read. 1831 */ 1832 static cardbusreg_t 1833 pccbb_conf_read(cc, tag, offset) 1834 cardbus_chipset_tag_t cc; 1835 cardbustag_t tag; 1836 int offset; /* register offset */ 1837 { 1838 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1839 1840 return pci_conf_read(sc->sc_pc, tag, offset); 1841 } 1842 1843 /* 1844 * static void pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, 1845 * int offs, cardbusreg_t val) 1846 * This is the function to write the config space of a CardBus Card. 1847 * It works same as pci_conf_write. 1848 */ 1849 static void 1850 pccbb_conf_write(cc, tag, reg, val) 1851 cardbus_chipset_tag_t cc; 1852 cardbustag_t tag; 1853 int reg; /* register offset */ 1854 cardbusreg_t val; 1855 { 1856 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1857 1858 pci_conf_write(sc->sc_pc, tag, reg, val); 1859 } 1860 1861 #if 0 1862 STATIC int 1863 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1864 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 1865 int speed, int flags, 1866 bus_space_handle_t * iohp) 1867 #endif 1868 /* 1869 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1870 * bus_addr_t start, bus_size_t size, 1871 * bus_size_t align, 1872 * struct pcmcia_io_handle *pcihp 1873 * 1874 * This function only allocates I/O region for pccard. This function 1875 * never maps the allcated region to pccard I/O area. 1876 * 1877 * XXX: The interface of this function is not very good, I believe. 1878 */ 1879 STATIC int 1880 pccbb_pcmcia_io_alloc(pch, start, size, align, pcihp) 1881 pcmcia_chipset_handle_t pch; 1882 bus_addr_t start; /* start address */ 1883 bus_size_t size; 1884 bus_size_t align; 1885 struct pcmcia_io_handle *pcihp; 1886 { 1887 struct pcic_handle *ph = (struct pcic_handle *)pch; 1888 bus_addr_t ioaddr; 1889 int flags = 0; 1890 bus_space_tag_t iot; 1891 bus_space_handle_t ioh; 1892 #if rbus 1893 rbus_tag_t rb; 1894 #endif 1895 if (align == 0) { 1896 align = size; /* XXX: funny??? */ 1897 } 1898 1899 /* 1900 * Allocate some arbitrary I/O space. 1901 */ 1902 1903 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 1904 1905 #if rbus 1906 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 1907 /* XXX: I assume all card decode lower 10 bits by its hardware */ 1908 if (rbus_space_alloc(rb, start, size, 0x3ff, align, 0, &ioaddr, &ioh)) { 1909 return 1; 1910 } 1911 #else 1912 if (start) { 1913 ioaddr = start; 1914 if (bus_space_map(iot, start, size, 0, &ioh)) { 1915 return 1; 1916 } 1917 DPRINTF(("pccbb_pcmcia_io_alloc map port %lx+%lx\n", 1918 (u_long) ioaddr, (u_long) size)); 1919 } else { 1920 flags |= PCMCIA_IO_ALLOCATED; 1921 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 1922 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 1923 size, align, 0, 0, &ioaddr, &ioh)) { 1924 /* No room be able to be get. */ 1925 return 1; 1926 } 1927 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 1928 (u_long) ioaddr, (u_long) size)); 1929 } 1930 #endif 1931 1932 pcihp->iot = iot; 1933 pcihp->ioh = ioh; 1934 pcihp->addr = ioaddr; 1935 pcihp->size = size; 1936 pcihp->flags = flags; 1937 1938 return 0; 1939 } 1940 1941 /* 1942 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 1943 * struct pcmcia_io_handle *pcihp) 1944 * 1945 * This function only frees I/O region for pccard. 1946 * 1947 * XXX: The interface of this function is not very good, I believe. 1948 */ 1949 void 1950 pccbb_pcmcia_io_free(pch, pcihp) 1951 pcmcia_chipset_handle_t pch; 1952 struct pcmcia_io_handle *pcihp; 1953 { 1954 #if !rbus 1955 bus_space_tag_t iot = pcihp->iot; 1956 #endif 1957 bus_space_handle_t ioh = pcihp->ioh; 1958 bus_size_t size = pcihp->size; 1959 1960 #if rbus 1961 struct pccbb_softc *sc = 1962 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 1963 rbus_tag_t rb = sc->sc_rbus_iot; 1964 1965 rbus_space_free(rb, ioh, size, NULL); 1966 #else 1967 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 1968 bus_space_free(iot, ioh, size); 1969 else 1970 bus_space_unmap(iot, ioh, size); 1971 #endif 1972 } 1973 1974 /* 1975 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 1976 * bus_addr_t offset, bus_size_t size, 1977 * struct pcmcia_io_handle *pcihp, 1978 * int *windowp) 1979 * 1980 * This function maps the allocated I/O region to pccard. This function 1981 * never allocates any I/O region for pccard I/O area. I don't 1982 * understand why the original authors of pcmciabus separated alloc and 1983 * map. I believe the two must be unite. 1984 * 1985 * XXX: no wait timing control? 1986 */ 1987 int 1988 pccbb_pcmcia_io_map(pch, width, offset, size, pcihp, windowp) 1989 pcmcia_chipset_handle_t pch; 1990 int width; 1991 bus_addr_t offset; 1992 bus_size_t size; 1993 struct pcmcia_io_handle *pcihp; 1994 int *windowp; 1995 { 1996 struct pcic_handle *ph = (struct pcic_handle *)pch; 1997 bus_addr_t ioaddr = pcihp->addr + offset; 1998 int i, win; 1999 #if defined CBB_DEBUG 2000 static char *width_names[] = { "dynamic", "io8", "io16" }; 2001 #endif 2002 2003 /* Sanity check I/O handle. */ 2004 2005 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 2006 panic("pccbb_pcmcia_io_map iot is bogus"); 2007 } 2008 2009 /* XXX Sanity check offset/size. */ 2010 2011 win = -1; 2012 for (i = 0; i < PCIC_IO_WINS; i++) { 2013 if ((ph->ioalloc & (1 << i)) == 0) { 2014 win = i; 2015 ph->ioalloc |= (1 << i); 2016 break; 2017 } 2018 } 2019 2020 if (win == -1) { 2021 return 1; 2022 } 2023 2024 *windowp = win; 2025 2026 /* XXX this is pretty gross */ 2027 2028 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2029 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2030 2031 /* XXX wtf is this doing here? */ 2032 2033 #if 0 2034 printf(" port 0x%lx", (u_long) ioaddr); 2035 if (size > 1) { 2036 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2037 } 2038 #endif 2039 2040 ph->io[win].addr = ioaddr; 2041 ph->io[win].size = size; 2042 ph->io[win].width = width; 2043 2044 /* actual dirty register-value changing in the function below. */ 2045 pccbb_pcmcia_do_io_map(ph, win); 2046 2047 return 0; 2048 } 2049 2050 /* 2051 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2052 * 2053 * This function changes register-value to map I/O region for pccard. 2054 */ 2055 static void 2056 pccbb_pcmcia_do_io_map(ph, win) 2057 struct pcic_handle *ph; 2058 int win; 2059 { 2060 static u_int8_t pcic_iowidth[3] = { 2061 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2062 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2063 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2064 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2065 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2066 }; 2067 2068 #define PCIC_SIA_START_LOW 0 2069 #define PCIC_SIA_START_HIGH 1 2070 #define PCIC_SIA_STOP_LOW 2 2071 #define PCIC_SIA_STOP_HIGH 3 2072 2073 int regbase_win = 0x8 + win * 0x04; 2074 u_int8_t ioctl, enable; 2075 2076 DPRINTF( 2077 ("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx width %d\n", 2078 win, (long)ph->io[win].addr, (long)ph->io[win].size, 2079 ph->io[win].width * 8)); 2080 2081 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2082 ph->io[win].addr & 0xff); 2083 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2084 (ph->io[win].addr >> 8) & 0xff); 2085 2086 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2087 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2088 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2089 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2090 2091 ioctl = Pcic_read(ph, PCIC_IOCTL); 2092 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2093 switch (win) { 2094 case 0: 2095 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2096 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2097 PCIC_IOCTL_IO0_DATASIZE_MASK); 2098 ioctl |= pcic_iowidth[ph->io[win].width]; 2099 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2100 break; 2101 case 1: 2102 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2103 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2104 PCIC_IOCTL_IO1_DATASIZE_MASK); 2105 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2106 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2107 break; 2108 } 2109 Pcic_write(ph, PCIC_IOCTL, ioctl); 2110 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2111 #if defined CBB_DEBUG 2112 { 2113 u_int8_t start_low = 2114 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2115 u_int8_t start_high = 2116 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2117 u_int8_t stop_low = 2118 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2119 u_int8_t stop_high = 2120 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2121 printf 2122 (" start %02x %02x, stop %02x %02x, ioctl %02x enable %02x\n", 2123 start_low, start_high, stop_low, stop_high, ioctl, enable); 2124 } 2125 #endif 2126 } 2127 2128 /* 2129 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2130 * 2131 * This function unmapss I/O region. No return value. 2132 */ 2133 STATIC void 2134 pccbb_pcmcia_io_unmap(pch, win) 2135 pcmcia_chipset_handle_t pch; 2136 int win; 2137 { 2138 struct pcic_handle *ph = (struct pcic_handle *)pch; 2139 int reg; 2140 2141 if (win >= PCIC_IO_WINS || win < 0) { 2142 panic("pccbb_pcmcia_io_unmap: window out of range"); 2143 } 2144 2145 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2146 switch (win) { 2147 case 0: 2148 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2149 break; 2150 case 1: 2151 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2152 break; 2153 } 2154 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2155 2156 ph->ioalloc &= ~(1 << win); 2157 } 2158 2159 /* 2160 * static void pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 2161 * 2162 * This function enables the card. All information is stored in 2163 * the first argument, pcmcia_chipset_handle_t. 2164 */ 2165 static void 2166 pccbb_pcmcia_wait_ready(ph) 2167 struct pcic_handle *ph; 2168 { 2169 int i; 2170 2171 DPRINTF(("pccbb_pcmcia_wait_ready: status 0x%02x\n", 2172 Pcic_read(ph, PCIC_IF_STATUS))); 2173 2174 for (i = 0; i < 10000; i++) { 2175 if (Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) { 2176 return; 2177 } 2178 delay(500); 2179 #ifdef CBB_DEBUG 2180 if ((i > 5000) && (i % 100 == 99)) 2181 printf("."); 2182 #endif 2183 } 2184 2185 #ifdef DIAGNOSTIC 2186 printf("pcic_wait_ready: ready never happened, status = %02x\n", 2187 Pcic_read(ph, PCIC_IF_STATUS)); 2188 #endif 2189 } 2190 2191 /* 2192 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2193 * 2194 * This function enables the card. All information is stored in 2195 * the first argument, pcmcia_chipset_handle_t. 2196 */ 2197 STATIC void 2198 pccbb_pcmcia_socket_enable(pch) 2199 pcmcia_chipset_handle_t pch; 2200 { 2201 struct pcic_handle *ph = (struct pcic_handle *)pch; 2202 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2203 int cardtype, win; 2204 u_int8_t power, intr; 2205 pcireg_t spsr; 2206 int voltage; 2207 #define PCIC_INTR_PCI PCIC_INTR_ENABLE 2208 2209 /* this bit is mostly stolen from pcic_attach_card */ 2210 2211 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2212 2213 /* get card Vcc info */ 2214 2215 spsr = 2216 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2217 CB_SOCKET_STAT); 2218 if (spsr & CB_SOCKET_STAT_5VCARD) { 2219 DPRINTF(("5V card\n")); 2220 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2221 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2222 DPRINTF(("3V card\n")); 2223 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2224 } else { 2225 printf("?V card, 0x%x\n", spsr); /* XXX */ 2226 return; 2227 } 2228 2229 /* assert reset bit */ 2230 intr = Pcic_read(ph, PCIC_INTR); 2231 intr &= ~(PCIC_INTR_RESET | PCIC_INTR_ENABLE | PCIC_INTR_CARDTYPE_MASK); 2232 Pcic_write(ph, PCIC_INTR, intr); 2233 2234 /* disable socket i/o: negate output enable bit */ 2235 2236 power = Pcic_read(ph, PCIC_PWRCTL); 2237 power &= ~PCIC_PWRCTL_OE; 2238 Pcic_write(ph, PCIC_PWRCTL, power); 2239 2240 /* power down the socket to reset it, clear the card reset pin */ 2241 2242 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2243 2244 /* 2245 * wait 200ms until power fails (Tpf). Then, wait 100ms since 2246 * we are changing Vcc (Toff). 2247 */ 2248 /* delay(300*1000); too much */ 2249 2250 /* power up the socket */ 2251 pccbb_power(sc, voltage); 2252 2253 /* 2254 * wait 100ms until power raise (Tpr) and 20ms to become 2255 * stable (Tsu(Vcc)). 2256 * 2257 * some machines require some more time to be settled 2258 * (another 200ms is added here). 2259 */ 2260 /* delay((100 + 20 + 200)*1000); too much */ 2261 2262 power = Pcic_read(ph, PCIC_PWRCTL); 2263 power |= PCIC_PWRCTL_OE; 2264 Pcic_write(ph, PCIC_PWRCTL, power); 2265 2266 /* 2267 * hold RESET at least 10us. 2268 */ 2269 delay(10); 2270 delay(2 * 1000); /* XXX: TI1130 requires it. */ 2271 delay(20 * 1000); /* XXX: TI1130 requires it. */ 2272 2273 /* clear the reset flag */ 2274 2275 intr |= PCIC_INTR_RESET; 2276 Pcic_write(ph, PCIC_INTR, intr); 2277 2278 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 2279 2280 delay(20000); 2281 2282 /* wait for the chip to finish initializing */ 2283 2284 pccbb_pcmcia_wait_ready(ph); 2285 2286 /* zero out the address windows */ 2287 2288 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2289 2290 /* set the card type */ 2291 2292 cardtype = pcmcia_card_gettype(ph->pcmcia); 2293 2294 intr |= PCIC_INTR_PCI; 2295 intr |= ((cardtype == PCMCIA_IFTYPE_IO) ? 2296 PCIC_INTR_CARDTYPE_IO : PCIC_INTR_CARDTYPE_MEM); 2297 Pcic_write(ph, PCIC_INTR, intr); 2298 2299 DPRINTF(("%s: pccbb_pcmcia_socket_enable %02x cardtype %s %02x\n", 2300 ph->ph_parent->dv_xname, ph->sock, 2301 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2302 2303 /* reinstall all the memory and io mappings */ 2304 2305 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2306 if (ph->memalloc & (1 << win)) { 2307 pccbb_pcmcia_do_mem_map(ph, win); 2308 } 2309 } 2310 2311 for (win = 0; win < PCIC_IO_WINS; ++win) { 2312 if (ph->ioalloc & (1 << win)) { 2313 pccbb_pcmcia_do_io_map(ph, win); 2314 } 2315 } 2316 } 2317 2318 /* 2319 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2320 * 2321 * This function disables the card. All information is stored in 2322 * the first argument, pcmcia_chipset_handle_t. 2323 */ 2324 STATIC void 2325 pccbb_pcmcia_socket_disable(pch) 2326 pcmcia_chipset_handle_t pch; 2327 { 2328 struct pcic_handle *ph = (struct pcic_handle *)pch; 2329 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2330 u_int8_t power, intr; 2331 2332 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2333 2334 /* reset signal asserting... */ 2335 2336 intr = Pcic_read(ph, PCIC_INTR); 2337 intr &= ~(PCIC_INTR_RESET | PCIC_INTR_ENABLE | PCIC_INTR_CARDTYPE_MASK); 2338 Pcic_write(ph, PCIC_INTR, intr); 2339 delay(2 * 1000); 2340 2341 /* power down the socket */ 2342 power = Pcic_read(ph, PCIC_PWRCTL); 2343 power &= ~PCIC_PWRCTL_OE; 2344 Pcic_write(ph, PCIC_PWRCTL, power); 2345 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2346 /* 2347 * wait 300ms until power fails (Tpf). 2348 */ 2349 delay(300 * 1000); 2350 } 2351 2352 /* 2353 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2354 * 2355 * This function detects whether a card is in the slot or not. 2356 * If a card is inserted, return 1. Otherwise, return 0. 2357 */ 2358 STATIC int 2359 pccbb_pcmcia_card_detect(pch) 2360 pcmcia_chipset_handle_t pch; 2361 { 2362 struct pcic_handle *ph = (struct pcic_handle *)pch; 2363 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2364 2365 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2366 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2367 } 2368 2369 #if 0 2370 STATIC int 2371 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2372 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2373 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2374 #endif 2375 /* 2376 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2377 * bus_size_t size, 2378 * struct pcmcia_mem_handle *pcmhp) 2379 * 2380 * This function only allocates memory region for pccard. This 2381 * function never maps the allcated region to pccard memory area. 2382 * 2383 * XXX: Why the argument of start address is not in? 2384 */ 2385 STATIC int 2386 pccbb_pcmcia_mem_alloc(pch, size, pcmhp) 2387 pcmcia_chipset_handle_t pch; 2388 bus_size_t size; 2389 struct pcmcia_mem_handle *pcmhp; 2390 { 2391 struct pcic_handle *ph = (struct pcic_handle *)pch; 2392 bus_space_handle_t memh; 2393 bus_addr_t addr; 2394 bus_size_t sizepg; 2395 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2396 #if rbus 2397 rbus_tag_t rb; 2398 #endif 2399 2400 /* out of sc->memh, allocate as many pages as necessary */ 2401 2402 /* convert size to PCIC pages */ 2403 /* 2404 * This is not enough; when the requested region is on the page 2405 * boundaries, this may calculate wrong result. 2406 */ 2407 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2408 #if 0 2409 if (sizepg > PCIC_MAX_MEM_PAGES) { 2410 return 1; 2411 } 2412 #endif 2413 2414 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2415 return 1; 2416 } 2417 2418 addr = 0; /* XXX gcc -Wuninitialized */ 2419 2420 #if rbus 2421 rb = sc->sc_rbus_memt; 2422 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2423 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2424 &addr, &memh)) { 2425 return 1; 2426 } 2427 #else 2428 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2429 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2430 0, /* boundary */ 2431 0, /* flags */ 2432 &addr, &memh)) { 2433 return 1; 2434 } 2435 #endif 2436 2437 DPRINTF( 2438 ("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, realsize 0x%lx\n", 2439 addr, size, sizepg * PCIC_MEM_PAGESIZE)); 2440 2441 pcmhp->memt = sc->sc_memt; 2442 pcmhp->memh = memh; 2443 pcmhp->addr = addr; 2444 pcmhp->size = size; 2445 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2446 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2447 pcmhp->mhandle = 0; 2448 /* No offset??? Funny. */ 2449 2450 return 0; 2451 } 2452 2453 /* 2454 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2455 * struct pcmcia_mem_handle *pcmhp) 2456 * 2457 * This function release the memory space allocated by the fuction 2458 * pccbb_pcmcia_mem_alloc(). 2459 */ 2460 STATIC void 2461 pccbb_pcmcia_mem_free(pch, pcmhp) 2462 pcmcia_chipset_handle_t pch; 2463 struct pcmcia_mem_handle *pcmhp; 2464 { 2465 #if rbus 2466 struct pcic_handle *ph = (struct pcic_handle *)pch; 2467 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2468 2469 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2470 #else 2471 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2472 #endif 2473 } 2474 2475 /* 2476 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2477 * 2478 * This function release the memory space allocated by the fuction 2479 * pccbb_pcmcia_mem_alloc(). 2480 */ 2481 STATIC void 2482 pccbb_pcmcia_do_mem_map(ph, win) 2483 struct pcic_handle *ph; 2484 int win; 2485 { 2486 int regbase_win; 2487 bus_addr_t phys_addr; 2488 bus_addr_t phys_end; 2489 2490 #define PCIC_SMM_START_LOW 0 2491 #define PCIC_SMM_START_HIGH 1 2492 #define PCIC_SMM_STOP_LOW 2 2493 #define PCIC_SMM_STOP_HIGH 3 2494 #define PCIC_CMA_LOW 4 2495 #define PCIC_CMA_HIGH 5 2496 2497 u_int8_t start_low, start_high = 0; 2498 u_int8_t stop_low, stop_high; 2499 u_int8_t off_low, off_high; 2500 u_int8_t mem_window; 2501 int reg; 2502 2503 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2504 int mem8 = 2505 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2506 || (kind == PCMCIA_MEM_ATTR); 2507 2508 regbase_win = 0x10 + win * 0x08; 2509 2510 phys_addr = ph->mem[win].addr; 2511 phys_end = phys_addr + ph->mem[win].size; 2512 2513 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2514 phys_addr, phys_end, ph->mem[win].offset)); 2515 2516 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2517 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2518 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2519 2520 /* bit 19:12 */ 2521 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2522 /* bit 23:20 and bit 7 on */ 2523 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2524 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2525 /* bit 31:24, for 32-bit address */ 2526 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2527 2528 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2529 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2530 2531 if (((struct pccbb_softc *)ph-> 2532 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2533 Pcic_write(ph, 0x40 + win, mem_window); 2534 } 2535 2536 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2537 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2538 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2539 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2540 2541 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2542 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2543 2544 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2545 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2546 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2547 | ((kind == PCMCIA_MEM_ATTR) ? 2548 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2549 2550 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2551 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2552 2553 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2554 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2555 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2556 2557 #if defined CBB_DEBUG 2558 { 2559 int r1, r2, r3, r4, r5, r6, r7 = 0; 2560 2561 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2562 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2563 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2564 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2565 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2566 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2567 if (((struct pccbb_softc *)(ph-> 2568 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2569 r7 = Pcic_read(ph, 0x40 + win); 2570 } 2571 2572 DPRINTF(("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2573 "%02x%02x", win, r1, r2, r3, r4, r5, r6)); 2574 if (((struct pccbb_softc *)(ph-> 2575 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2576 DPRINTF((" %02x", r7)); 2577 } 2578 DPRINTF(("\n")); 2579 } 2580 #endif 2581 } 2582 2583 /* 2584 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2585 * bus_addr_t card_addr, bus_size_t size, 2586 * struct pcmcia_mem_handle *pcmhp, 2587 * bus_addr_t *offsetp, int *windowp) 2588 * 2589 * This function maps memory space allocated by the fuction 2590 * pccbb_pcmcia_mem_alloc(). 2591 */ 2592 STATIC int 2593 pccbb_pcmcia_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 2594 pcmcia_chipset_handle_t pch; 2595 int kind; 2596 bus_addr_t card_addr; 2597 bus_size_t size; 2598 struct pcmcia_mem_handle *pcmhp; 2599 bus_addr_t *offsetp; 2600 int *windowp; 2601 { 2602 struct pcic_handle *ph = (struct pcic_handle *)pch; 2603 bus_addr_t busaddr; 2604 long card_offset; 2605 int win; 2606 2607 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2608 if ((ph->memalloc & (1 << win)) == 0) { 2609 ph->memalloc |= (1 << win); 2610 break; 2611 } 2612 } 2613 2614 if (win == PCIC_MEM_WINS) { 2615 return 1; 2616 } 2617 2618 *windowp = win; 2619 2620 /* XXX this is pretty gross */ 2621 2622 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2623 panic("pccbb_pcmcia_mem_map memt is bogus"); 2624 } 2625 2626 busaddr = pcmhp->addr; 2627 2628 /* 2629 * compute the address offset to the pcmcia address space for the 2630 * pcic. this is intentionally signed. The masks and shifts below 2631 * will cause TRT to happen in the pcic registers. Deal with making 2632 * sure the address is aligned, and return the alignment offset. 2633 */ 2634 2635 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2636 card_addr -= *offsetp; 2637 2638 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2639 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2640 (u_long) card_addr)); 2641 2642 /* 2643 * include the offset in the size, and decrement size by one, since 2644 * the hw wants start/stop 2645 */ 2646 size += *offsetp - 1; 2647 2648 card_offset = (((long)card_addr) - ((long)busaddr)); 2649 2650 ph->mem[win].addr = busaddr; 2651 ph->mem[win].size = size; 2652 ph->mem[win].offset = card_offset; 2653 ph->mem[win].kind = kind; 2654 2655 pccbb_pcmcia_do_mem_map(ph, win); 2656 2657 return 0; 2658 } 2659 2660 /* 2661 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2662 * int window) 2663 * 2664 * This function unmaps memory space which mapped by the fuction 2665 * pccbb_pcmcia_mem_map(). 2666 */ 2667 STATIC void 2668 pccbb_pcmcia_mem_unmap(pch, window) 2669 pcmcia_chipset_handle_t pch; 2670 int window; 2671 { 2672 struct pcic_handle *ph = (struct pcic_handle *)pch; 2673 int reg; 2674 2675 if (window >= PCIC_MEM_WINS) { 2676 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2677 } 2678 2679 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2680 reg &= ~(1 << window); 2681 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2682 2683 ph->memalloc &= ~(1 << window); 2684 } 2685 2686 #if defined PCCBB_PCMCIA_POLL 2687 struct pccbb_poll_str { 2688 void *arg; 2689 int (*func) __P((void *)); 2690 int level; 2691 struct pcic_handle *ph; 2692 int count; 2693 int num; 2694 }; 2695 2696 static struct pccbb_poll_str pccbb_poll[10]; 2697 static int pccbb_poll_n = 0; 2698 2699 static void pccbb_pcmcia_poll __P((void *arg)); 2700 2701 static void 2702 pccbb_pcmcia_poll(arg) 2703 void *arg; 2704 { 2705 struct pccbb_poll_str *poll = arg; 2706 struct pcic_handle *ph = poll->ph; 2707 struct pccbb_softc *sc = ph->sc; 2708 int s; 2709 u_int32_t spsr; /* socket present-state reg */ 2710 2711 timeout(pccbb_pcmcia_poll, arg, hz * 2); 2712 switch (poll->level) { 2713 case IPL_NET: 2714 s = splnet(); 2715 break; 2716 case IPL_BIO: 2717 s = splbio(); 2718 break; 2719 case IPL_TTY: /* fallthrough */ 2720 default: 2721 s = spltty(); 2722 break; 2723 } 2724 2725 spsr = 2726 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2727 CB_SOCKET_STAT); 2728 2729 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2730 if (!(spsr & 0x40)) /* CINT low */ 2731 #else 2732 if (1) 2733 #endif 2734 { 2735 if ((*poll->func) (poll->arg) > 0) { 2736 ++poll->count; 2737 // printf("intr: reported from poller, 0x%x\n", spsr); 2738 #if defined LEVEL2 2739 } else { 2740 printf("intr: miss! 0x%x\n", spsr); 2741 #endif 2742 } 2743 } 2744 splx(s); 2745 } 2746 #endif /* defined CB_PCMCIA_POLL */ 2747 2748 /* 2749 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2750 * struct pcmcia_function *pf, 2751 * int ipl, 2752 * int (*func)(void *), 2753 * void *arg); 2754 * 2755 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2756 */ 2757 STATIC void * 2758 pccbb_pcmcia_intr_establish(pch, pf, ipl, func, arg) 2759 pcmcia_chipset_handle_t pch; 2760 struct pcmcia_function *pf; 2761 int ipl; 2762 int (*func) __P((void *)); 2763 void *arg; 2764 { 2765 struct pcic_handle *ph = (struct pcic_handle *)pch; 2766 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2767 2768 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2769 /* what should I do? */ 2770 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2771 DPRINTF( 2772 ("%s does not provide edge nor pulse interrupt\n", 2773 sc->sc_dev.dv_xname)); 2774 return NULL; 2775 } 2776 /* 2777 * XXX Noooooo! The interrupt flag must set properly!! 2778 * dumb pcmcia driver!! 2779 */ 2780 } 2781 2782 return pccbb_intr_establish(sc, IST_LEVEL, ipl, func, arg); 2783 } 2784 2785 /* 2786 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2787 * void *ih) 2788 * 2789 * This function disables PC-Card interrupt. 2790 */ 2791 STATIC void 2792 pccbb_pcmcia_intr_disestablish(pch, ih) 2793 pcmcia_chipset_handle_t pch; 2794 void *ih; 2795 { 2796 struct pcic_handle *ph = (struct pcic_handle *)pch; 2797 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2798 2799 pccbb_intr_disestablish(sc, ih); 2800 } 2801 2802 #if rbus 2803 /* 2804 * static int 2805 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2806 * bus_addr_t addr, bus_size_t size, 2807 * bus_addr_t mask, bus_size_t align, 2808 * int flags, bus_addr_t *addrp; 2809 * bus_space_handle_t *bshp) 2810 * 2811 * This function allocates a portion of memory or io space for 2812 * clients. This function is called from CardBus card drivers. 2813 */ 2814 static int 2815 pccbb_rbus_cb_space_alloc(ct, rb, addr, size, mask, align, flags, addrp, bshp) 2816 cardbus_chipset_tag_t ct; 2817 rbus_tag_t rb; 2818 bus_addr_t addr; 2819 bus_size_t size; 2820 bus_addr_t mask; 2821 bus_size_t align; 2822 int flags; 2823 bus_addr_t *addrp; 2824 bus_space_handle_t *bshp; 2825 { 2826 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2827 2828 DPRINTF( 2829 ("pccbb_rbus_cb_space_alloc: adr %lx, size %lx, mask %lx, align %lx\n", 2830 addr, size, mask, align)); 2831 2832 if (align == 0) { 2833 align = size; 2834 } 2835 2836 if (rb->rb_bt == sc->sc_memt) { 2837 if (align < 16) { 2838 return 1; 2839 } 2840 } else if (rb->rb_bt == sc->sc_iot) { 2841 if (align < 4) { 2842 return 1; 2843 } 2844 } else { 2845 DPRINTF( 2846 ("pccbb_rbus_cb_space_alloc: Bus space tag %x is NOT used.\n", 2847 rb->rb_bt)); 2848 return 1; 2849 /* XXX: panic here? */ 2850 } 2851 2852 /* XXX: hack for avoiding ISA image */ 2853 if (mask < 0x3ff) { 2854 mask = 0x3ff; 2855 addr = 0x300; 2856 } 2857 2858 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 2859 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 2860 return 1; 2861 } 2862 2863 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 2864 2865 return 0; 2866 } 2867 2868 /* 2869 * static int 2870 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 2871 * bus_space_handle_t *bshp, bus_size_t size); 2872 * 2873 * This function is called from CardBus card drivers. 2874 */ 2875 static int 2876 pccbb_rbus_cb_space_free(ct, rb, bsh, size) 2877 cardbus_chipset_tag_t ct; 2878 rbus_tag_t rb; 2879 bus_space_handle_t bsh; 2880 bus_size_t size; 2881 { 2882 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2883 bus_space_tag_t bt = rb->rb_bt; 2884 2885 pccbb_close_win(sc, bt, bsh, size); 2886 2887 if (bt == sc->sc_memt) { 2888 } else if (bt == sc->sc_iot) { 2889 } else { 2890 return 1; 2891 /* XXX: panic here? */ 2892 } 2893 2894 return rbus_space_free(rb, bsh, size, NULL); 2895 } 2896 #endif /* rbus */ 2897 2898 #if rbus 2899 2900 static int 2901 pccbb_open_win(sc, bst, addr, size, bsh, flags) 2902 struct pccbb_softc *sc; 2903 bus_space_tag_t bst; 2904 bus_addr_t addr; 2905 bus_size_t size; 2906 bus_space_handle_t bsh; 2907 int flags; 2908 { 2909 struct pccbb_win_chain_head *head; 2910 bus_addr_t align; 2911 2912 head = &sc->sc_iowindow; 2913 align = 0x04; 2914 if (sc->sc_memt == bst) { 2915 head = &sc->sc_memwindow; 2916 align = 0x1000; 2917 DPRINTF(("using memory window, %x %x %x\n\n", 2918 sc->sc_iot, sc->sc_memt, bst)); 2919 } 2920 2921 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 2922 printf("%s: pccbb_open_win: %s winlist insert failed\n", 2923 sc->sc_dev.dv_xname, 2924 (head == &sc->sc_memwindow) ? "mem" : "io"); 2925 } 2926 pccbb_winset(align, sc, bst); 2927 2928 return 0; 2929 } 2930 2931 static int 2932 pccbb_close_win(sc, bst, bsh, size) 2933 struct pccbb_softc *sc; 2934 bus_space_tag_t bst; 2935 bus_space_handle_t bsh; 2936 bus_size_t size; 2937 { 2938 struct pccbb_win_chain_head *head; 2939 bus_addr_t align; 2940 2941 head = &sc->sc_iowindow; 2942 align = 0x04; 2943 if (sc->sc_memt == bst) { 2944 head = &sc->sc_memwindow; 2945 align = 0x1000; 2946 } 2947 2948 if (pccbb_winlist_delete(head, bsh, size)) { 2949 printf("%s: pccbb_close_win: %s winlist delete failed\n", 2950 sc->sc_dev.dv_xname, 2951 (head == &sc->sc_memwindow) ? "mem" : "io"); 2952 } 2953 pccbb_winset(align, sc, bst); 2954 2955 return 0; 2956 } 2957 2958 static int 2959 pccbb_winlist_insert(head, start, size, bsh, flags) 2960 struct pccbb_win_chain_head *head; 2961 bus_addr_t start; 2962 bus_size_t size; 2963 bus_space_handle_t bsh; 2964 int flags; 2965 { 2966 struct pccbb_win_chain *chainp, *elem; 2967 2968 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 2969 M_NOWAIT)) == NULL) 2970 return 1; /* fail */ 2971 2972 elem->wc_start = start; 2973 elem->wc_end = start + (size - 1); 2974 elem->wc_handle = bsh; 2975 elem->wc_flags = flags; 2976 2977 if ((chainp = TAILQ_FIRST(head)) == NULL) { 2978 TAILQ_INSERT_HEAD(head, elem, wc_list); 2979 return 0; 2980 } 2981 2982 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 2983 if (chainp->wc_end < start) 2984 continue; 2985 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 2986 return 0; 2987 } 2988 2989 TAILQ_INSERT_TAIL(head, elem, wc_list); 2990 2991 return 0; 2992 } 2993 2994 static int 2995 pccbb_winlist_delete(head, bsh, size) 2996 struct pccbb_win_chain_head *head; 2997 bus_space_handle_t bsh; 2998 bus_size_t size; 2999 { 3000 struct pccbb_win_chain *chainp; 3001 3002 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3003 chainp = TAILQ_NEXT(chainp, wc_list)) { 3004 if (chainp->wc_handle != bsh) 3005 continue; 3006 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 3007 printf("pccbb_winlist_delete: window 0x%lx size " 3008 "inconsistent: 0x%lx, 0x%lx\n", 3009 chainp->wc_start, 3010 chainp->wc_end - chainp->wc_start, 3011 size - 1); 3012 return 1; 3013 } 3014 3015 TAILQ_REMOVE(head, chainp, wc_list); 3016 free(chainp, M_DEVBUF); 3017 3018 return 0; 3019 } 3020 3021 return 1; /* fail: no candidate to remove */ 3022 } 3023 3024 static void 3025 pccbb_winset(align, sc, bst) 3026 bus_addr_t align; 3027 struct pccbb_softc *sc; 3028 bus_space_tag_t bst; 3029 { 3030 pci_chipset_tag_t pc; 3031 pcitag_t tag; 3032 bus_addr_t mask = ~(align - 1); 3033 struct { 3034 cardbusreg_t win_start; 3035 cardbusreg_t win_limit; 3036 int win_flags; 3037 } win[2]; 3038 struct pccbb_win_chain *chainp; 3039 int offs; 3040 3041 win[0].win_start = 0xffffffff; 3042 win[0].win_limit = 0; 3043 win[1].win_start = 0xffffffff; 3044 win[1].win_limit = 0; 3045 3046 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3047 offs = 0x2c; 3048 if (sc->sc_memt == bst) { 3049 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3050 offs = 0x1c; 3051 } 3052 3053 if (chainp != NULL) { 3054 win[0].win_start = chainp->wc_start & mask; 3055 win[0].win_limit = chainp->wc_end & mask; 3056 win[0].win_flags = chainp->wc_flags; 3057 chainp = TAILQ_NEXT(chainp, wc_list); 3058 } 3059 3060 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3061 if (win[1].win_start == 0xffffffff) { 3062 /* window 1 is not used */ 3063 if ((win[0].win_flags == chainp->wc_flags) && 3064 (win[0].win_limit + align >= 3065 (chainp->wc_start & mask))) { 3066 /* concatenate */ 3067 win[0].win_limit = chainp->wc_end & mask; 3068 } else { 3069 /* make new window */ 3070 win[1].win_start = chainp->wc_start & mask; 3071 win[1].win_limit = chainp->wc_end & mask; 3072 win[1].win_flags = chainp->wc_flags; 3073 } 3074 continue; 3075 } 3076 3077 /* Both windows are engagad. */ 3078 if (win[0].win_flags == win[1].win_flags) { 3079 /* same flags */ 3080 if (win[0].win_flags == chainp->wc_flags) { 3081 if (win[1].win_start - (win[0].win_limit + 3082 align) < 3083 (chainp->wc_start & mask) - 3084 ((chainp->wc_end & mask) + align)) { 3085 /* 3086 * merge window 0 and 1, and set win1 3087 * to chainp 3088 */ 3089 win[0].win_limit = win[1].win_limit; 3090 win[1].win_start = 3091 chainp->wc_start & mask; 3092 win[1].win_limit = 3093 chainp->wc_end & mask; 3094 } else { 3095 win[1].win_limit = 3096 chainp->wc_end & mask; 3097 } 3098 } else { 3099 /* different flags */ 3100 3101 /* concatenate win0 and win1 */ 3102 win[0].win_limit = win[1].win_limit; 3103 /* allocate win[1] to new space */ 3104 win[1].win_start = chainp->wc_start & mask; 3105 win[1].win_limit = chainp->wc_end & mask; 3106 win[1].win_flags = chainp->wc_flags; 3107 } 3108 } else { 3109 /* the flags of win[0] and win[1] is different */ 3110 if (win[0].win_flags == chainp->wc_flags) { 3111 win[0].win_limit = chainp->wc_end & mask; 3112 /* 3113 * XXX this creates overlapping windows, so 3114 * what should the poor bridge do if one is 3115 * cachable, and the other is not? 3116 */ 3117 printf("%s: overlapping windows\n", 3118 sc->sc_dev.dv_xname); 3119 } else { 3120 win[1].win_limit = chainp->wc_end & mask; 3121 } 3122 } 3123 } 3124 3125 pc = sc->sc_pc; 3126 tag = sc->sc_tag; 3127 pci_conf_write(pc, tag, offs, win[0].win_start); 3128 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3129 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3130 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3131 DPRINTF(("--pccbb_winset: win0 [%x, %lx), win1 [%x, %lx)\n", 3132 pci_conf_read(pc, tag, offs), 3133 pci_conf_read(pc, tag, offs + 4) + align, 3134 pci_conf_read(pc, tag, offs + 8), 3135 pci_conf_read(pc, tag, offs + 12) + align)); 3136 3137 if (bst == sc->sc_memt) { 3138 if (win[0].win_flags & PCCBB_MEM_CACHABLE) { 3139 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3140 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3141 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3142 } 3143 if (win[1].win_flags & PCCBB_MEM_CACHABLE) { 3144 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3145 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3146 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3147 } 3148 } 3149 } 3150 3151 #endif /* rbus */ 3152 3153 static void 3154 pccbb_powerhook(why, arg) 3155 int why; 3156 void *arg; 3157 { 3158 struct pccbb_softc *sc = arg; 3159 u_int32_t reg; 3160 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3161 bus_space_handle_t base_memh = sc->sc_base_memh; 3162 3163 DPRINTF(("%s: power: why %d\n", sc->sc_dev.dv_xname, why)); 3164 3165 if (why == PWR_SUSPEND || why == PWR_STANDBY) { 3166 DPRINTF(("%s: power: why %d stopping intr\n", sc->sc_dev.dv_xname, why)); 3167 if (sc->sc_pil_intr_enable) { 3168 (void)pccbbintr_function(sc); 3169 } 3170 sc->sc_pil_intr_enable = 0; 3171 3172 /* ToDo: deactivate or suspend child devices */ 3173 3174 } 3175 3176 if (why == PWR_RESUME) { 3177 /* CSC Interrupt: Card detect interrupt on */ 3178 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3179 /* Card detect intr is turned on. */ 3180 reg |= CB_SOCKET_MASK_CD; 3181 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3182 /* reset interrupt */ 3183 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3184 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3185 3186 /* 3187 * check for card insertion or removal during suspend period. 3188 * XXX: the code can't cope with card swap (remove then insert). 3189 * how can we detect such situation? 3190 */ 3191 if (why == PWR_RESUME) { 3192 (void)pccbbintr(sc); 3193 } 3194 3195 sc->sc_pil_intr_enable = 1; 3196 DPRINTF(("%s: power: RESUME enabling intr\n", sc->sc_dev.dv_xname)); 3197 3198 /* ToDo: activate or wakeup child devices */ 3199 3200 } 3201 } 3202
Indexes created Sat Sep 27 22:09:54 GMT 2025